1 /* SPDX-License-Identifier: GPL-2.0 */
2 // Copyright (C) 2025 Arm Ltd.
3
4 #ifndef MPAM_INTERNAL_H
5 #define MPAM_INTERNAL_H
6
7 #include <linux/arm_mpam.h>
8 #include <linux/atomic.h>
9 #include <linux/bitmap.h>
10 #include <linux/cpumask.h>
11 #include <linux/io.h>
12 #include <linux/jump_label.h>
13 #include <linux/llist.h>
14 #include <linux/mutex.h>
15 #include <linux/resctrl.h>
16 #include <linux/spinlock.h>
17 #include <linux/srcu.h>
18 #include <linux/types.h>
19
20 #include <asm/mpam.h>
21
22 #define MPAM_MSC_MAX_NUM_RIS 16
23
24 struct platform_device;
25
26 #ifdef CONFIG_MPAM_KUNIT_TEST
27 #define PACKED_FOR_KUNIT __packed
28 #else
29 #define PACKED_FOR_KUNIT
30 #endif
31
32 /*
33 * This 'mon' values must not alias an actual monitor, so must be larger than
34 * U16_MAX, but not be confused with an errno value, so smaller than
35 * (u32)-SZ_4K.
36 * USE_PRE_ALLOCATED is used to avoid confusion with an actual monitor.
37 */
38 #define USE_PRE_ALLOCATED (U16_MAX + 1)
39
mpam_is_enabled(void)40 static inline bool mpam_is_enabled(void)
41 {
42 return static_branch_likely(&mpam_enabled);
43 }
44
45 /*
46 * Structures protected by SRCU may not be freed for a surprising amount of
47 * time (especially if perf is running). To ensure the MPAM error interrupt can
48 * tear down all the structures, build a list of objects that can be garbage
49 * collected once synchronize_srcu() has returned.
50 * If pdev is non-NULL, use devm_kfree().
51 */
52 struct mpam_garbage {
53 /* member of mpam_garbage */
54 struct llist_node llist;
55
56 void *to_free;
57 struct platform_device *pdev;
58 };
59
60 struct mpam_msc {
61 /* member of mpam_all_msc */
62 struct list_head all_msc_list;
63
64 int id;
65 struct platform_device *pdev;
66
67 /* Not modified after mpam_is_enabled() becomes true */
68 enum mpam_msc_iface iface;
69 u32 nrdy_usec;
70 cpumask_t accessibility;
71 bool has_extd_esr;
72
73 int reenable_error_ppi;
74 struct mpam_msc * __percpu *error_dev_id;
75
76 atomic_t online_refs;
77
78 /*
79 * probe_lock is only taken during discovery. After discovery these
80 * properties become read-only and the lists are protected by SRCU.
81 */
82 struct mutex probe_lock;
83 bool probed;
84 u16 partid_max;
85 u8 pmg_max;
86 unsigned long ris_idxs;
87 u32 ris_max;
88 u32 iidr;
89 u16 quirks;
90
91 /*
92 * error_irq_lock is taken when registering/unregistering the error
93 * interrupt and maniupulating the below flags.
94 */
95 struct mutex error_irq_lock;
96 bool error_irq_req;
97 bool error_irq_hw_enabled;
98
99 /* mpam_msc_ris of this component */
100 struct list_head ris;
101
102 /*
103 * part_sel_lock protects access to the MSC hardware registers that are
104 * affected by MPAMCFG_PART_SEL. (including the ID registers that vary
105 * by RIS).
106 * If needed, take msc->probe_lock first.
107 */
108 struct mutex part_sel_lock;
109
110 /*
111 * cfg_lock protects the msc configuration and guards against mbwu_state
112 * save and restore racing.
113 */
114 struct mutex cfg_lock;
115
116 /*
117 * mon_sel_lock protects access to the MSC hardware registers that are
118 * affected by MPAMCFG_MON_SEL, and the mbwu_state.
119 * Access to mon_sel is needed from both process and interrupt contexts,
120 * but is complicated by firmware-backed platforms that can't make any
121 * access unless they can sleep.
122 * Always use the mpam_mon_sel_lock() helpers.
123 * Accesses to mon_sel need to be able to fail if they occur in the wrong
124 * context.
125 * If needed, take msc->probe_lock first.
126 */
127 raw_spinlock_t _mon_sel_lock;
128 unsigned long _mon_sel_flags;
129
130 void __iomem *mapped_hwpage;
131 size_t mapped_hwpage_sz;
132
133 /* Values only used on some platforms for quirks */
134 u32 t241_id;
135
136 struct mpam_garbage garbage;
137 };
138
139 /* Returning false here means accesses to mon_sel must fail and report an error. */
mpam_mon_sel_lock(struct mpam_msc * msc)140 static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc)
141 {
142 /* Locking will require updating to support a firmware backed interface */
143 if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO))
144 return false;
145
146 raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags);
147 return true;
148 }
149
mpam_mon_sel_unlock(struct mpam_msc * msc)150 static inline void mpam_mon_sel_unlock(struct mpam_msc *msc)
151 {
152 raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags);
153 }
154
mpam_mon_sel_lock_held(struct mpam_msc * msc)155 static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc)
156 {
157 lockdep_assert_held_once(&msc->_mon_sel_lock);
158 }
159
mpam_mon_sel_lock_init(struct mpam_msc * msc)160 static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc)
161 {
162 raw_spin_lock_init(&msc->_mon_sel_lock);
163 }
164
165 /* Bits for mpam features bitmaps */
166 enum mpam_device_features {
167 mpam_feat_cpor_part,
168 mpam_feat_cmax_softlim,
169 mpam_feat_cmax_cmax,
170 mpam_feat_cmax_cmin,
171 mpam_feat_cmax_cassoc,
172 mpam_feat_mbw_part,
173 mpam_feat_mbw_min,
174 mpam_feat_mbw_max,
175 mpam_feat_mbw_prop,
176 mpam_feat_intpri_part,
177 mpam_feat_intpri_part_0_low,
178 mpam_feat_dspri_part,
179 mpam_feat_dspri_part_0_low,
180 mpam_feat_msmon,
181 mpam_feat_msmon_csu,
182 mpam_feat_msmon_csu_capture,
183 mpam_feat_msmon_csu_xcl,
184 mpam_feat_msmon_mbwu,
185 mpam_feat_msmon_mbwu_31counter,
186 mpam_feat_msmon_mbwu_44counter,
187 mpam_feat_msmon_mbwu_63counter,
188 mpam_feat_msmon_mbwu_capture,
189 mpam_feat_msmon_mbwu_rwbw,
190 mpam_feat_partid_nrw,
191 MPAM_FEATURE_LAST
192 };
193
194 struct mpam_props {
195 DECLARE_BITMAP(features, MPAM_FEATURE_LAST);
196
197 u16 cpbm_wd;
198 u16 mbw_pbm_bits;
199 u16 bwa_wd;
200 u16 cmax_wd;
201 u16 cassoc_wd;
202 u16 intpri_wd;
203 u16 dspri_wd;
204 u16 num_csu_mon;
205 u16 num_mbwu_mon;
206
207 /*
208 * Kunit tests use memset() to set up feature combinations that should be
209 * removed, and will false-positive if the compiler introduces padding that
210 * isn't cleared during sanitisation.
211 */
212 } PACKED_FOR_KUNIT;
213
214 #define mpam_has_feature(_feat, x) test_bit(_feat, (x)->features)
215 /*
216 * The non-atomic get/set operations are used because if struct mpam_props is
217 * packed, the alignment requirements for atomics aren't met.
218 */
219 #define mpam_set_feature(_feat, x) __set_bit(_feat, (x)->features)
220 #define mpam_clear_feature(_feat, x) __clear_bit(_feat, (x)->features)
221
222 /* Workaround bits for msc->quirks */
223 enum mpam_device_quirks {
224 T241_SCRUB_SHADOW_REGS,
225 T241_FORCE_MBW_MIN_TO_ONE,
226 T241_MBW_COUNTER_SCALE_64,
227 IGNORE_CSU_NRDY,
228 MPAM_QUIRK_LAST
229 };
230
231 #define mpam_has_quirk(_quirk, x) ((1 << (_quirk) & (x)->quirks))
232 #define mpam_set_quirk(_quirk, x) ((x)->quirks |= (1 << (_quirk)))
233
234 struct mpam_quirk {
235 int (*init)(struct mpam_msc *msc, const struct mpam_quirk *quirk);
236
237 u32 iidr;
238 u32 iidr_mask;
239
240 enum mpam_device_quirks workaround;
241 };
242
243 #define MPAM_IIDR_MATCH_ONE (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0xfff) | \
244 FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0xf) | \
245 FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0xf) | \
246 FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0xfff))
247
248 #define MPAM_IIDR_NVIDIA_T241 (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0x241) | \
249 FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0) | \
250 FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0) | \
251 FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x36b))
252
253 #define MPAM_IIDR_ARM_CMN_650 (FIELD_PREP_CONST(MPAMF_IIDR_PRODUCTID, 0) | \
254 FIELD_PREP_CONST(MPAMF_IIDR_VARIANT, 0) | \
255 FIELD_PREP_CONST(MPAMF_IIDR_REVISION, 0) | \
256 FIELD_PREP_CONST(MPAMF_IIDR_IMPLEMENTER, 0x43b))
257
258 /* The values for MSMON_CFG_MBWU_FLT.RWBW */
259 enum mon_filter_options {
260 COUNT_BOTH = 0,
261 COUNT_WRITE = 1,
262 COUNT_READ = 2,
263 };
264
265 struct mon_cfg {
266 /*
267 * mon must be large enough to hold out of range values like
268 * USE_PRE_ALLOCATED
269 */
270 u32 mon;
271 u8 pmg;
272 bool match_pmg;
273 bool csu_exclude_clean;
274 u32 partid;
275 enum mon_filter_options opts;
276 };
277
278 /* Changes to msmon_mbwu_state are protected by the msc's mon_sel_lock. */
279 struct msmon_mbwu_state {
280 bool enabled;
281 bool reset_on_next_read;
282 struct mon_cfg cfg;
283
284 /*
285 * The value to add to the new reading to account for power management,
286 * and overflow.
287 */
288 u64 correction;
289
290 struct mpam_garbage garbage;
291 };
292
293 struct mpam_class {
294 /* mpam_components in this class */
295 struct list_head components;
296
297 cpumask_t affinity;
298
299 struct mpam_props props;
300 u32 nrdy_usec;
301 u16 quirks;
302 u8 level;
303 enum mpam_class_types type;
304
305 /* member of mpam_classes */
306 struct list_head classes_list;
307
308 struct ida ida_csu_mon;
309 struct ida ida_mbwu_mon;
310
311 struct mpam_garbage garbage;
312 };
313
314 struct mpam_config {
315 /* Which configuration values are valid. */
316 DECLARE_BITMAP(features, MPAM_FEATURE_LAST);
317
318 u32 cpbm;
319 u32 mbw_pbm;
320 u16 mbw_max;
321
322 struct mpam_garbage garbage;
323 };
324
325 struct mpam_component {
326 u32 comp_id;
327
328 /* mpam_vmsc in this component */
329 struct list_head vmsc;
330
331 cpumask_t affinity;
332
333 /*
334 * Array of configuration values, indexed by partid.
335 * Read from cpuhp callbacks, hold the cpuhp lock when writing.
336 */
337 struct mpam_config *cfg;
338
339 /* member of mpam_class:components */
340 struct list_head class_list;
341
342 /* parent: */
343 struct mpam_class *class;
344
345 struct mpam_garbage garbage;
346 };
347
348 struct mpam_vmsc {
349 /* member of mpam_component:vmsc_list */
350 struct list_head comp_list;
351
352 /* mpam_msc_ris in this vmsc */
353 struct list_head ris;
354
355 struct mpam_props props;
356
357 /* All RIS in this vMSC are members of this MSC */
358 struct mpam_msc *msc;
359
360 /* parent: */
361 struct mpam_component *comp;
362
363 struct mpam_garbage garbage;
364 };
365
366 struct mpam_msc_ris {
367 u8 ris_idx;
368 u64 idr;
369 struct mpam_props props;
370 bool in_reset_state;
371
372 cpumask_t affinity;
373
374 /* member of mpam_vmsc:ris */
375 struct list_head vmsc_list;
376
377 /* member of mpam_msc:ris */
378 struct list_head msc_list;
379
380 /* parent: */
381 struct mpam_vmsc *vmsc;
382
383 /* msmon mbwu configuration is preserved over reset */
384 struct msmon_mbwu_state *mbwu_state;
385
386 struct mpam_garbage garbage;
387 };
388
389 struct mpam_resctrl_dom {
390 struct mpam_component *ctrl_comp;
391
392 /*
393 * There is no single mon_comp because different events may be backed
394 * by different class/components. mon_comp is indexed by the event
395 * number.
396 */
397 struct mpam_component *mon_comp[QOS_NUM_EVENTS];
398
399 struct rdt_ctrl_domain resctrl_ctrl_dom;
400 struct rdt_l3_mon_domain resctrl_mon_dom;
401 };
402
403 struct mpam_resctrl_res {
404 struct mpam_class *class;
405 struct rdt_resource resctrl_res;
406 bool cdp_enabled;
407 };
408
409 struct mpam_resctrl_mon {
410 struct mpam_class *class;
411
412 /* per-class data that resctrl needs will live here */
413 };
414
mpam_alloc_csu_mon(struct mpam_class * class)415 static inline int mpam_alloc_csu_mon(struct mpam_class *class)
416 {
417 struct mpam_props *cprops = &class->props;
418
419 if (!mpam_has_feature(mpam_feat_msmon_csu, cprops))
420 return -EOPNOTSUPP;
421
422 return ida_alloc_max(&class->ida_csu_mon, cprops->num_csu_mon - 1,
423 GFP_KERNEL);
424 }
425
mpam_free_csu_mon(struct mpam_class * class,int csu_mon)426 static inline void mpam_free_csu_mon(struct mpam_class *class, int csu_mon)
427 {
428 ida_free(&class->ida_csu_mon, csu_mon);
429 }
430
mpam_alloc_mbwu_mon(struct mpam_class * class)431 static inline int mpam_alloc_mbwu_mon(struct mpam_class *class)
432 {
433 struct mpam_props *cprops = &class->props;
434
435 if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops))
436 return -EOPNOTSUPP;
437
438 return ida_alloc_max(&class->ida_mbwu_mon, cprops->num_mbwu_mon - 1,
439 GFP_KERNEL);
440 }
441
mpam_free_mbwu_mon(struct mpam_class * class,int mbwu_mon)442 static inline void mpam_free_mbwu_mon(struct mpam_class *class, int mbwu_mon)
443 {
444 ida_free(&class->ida_mbwu_mon, mbwu_mon);
445 }
446
447 /* List of all classes - protected by srcu*/
448 extern struct srcu_struct mpam_srcu;
449 extern struct list_head mpam_classes;
450
451 /* System wide partid/pmg values */
452 extern u16 mpam_partid_max;
453 extern u8 mpam_pmg_max;
454
455 /* Scheduled work callback to enable mpam once all MSC have been probed */
456 void mpam_enable(struct work_struct *work);
457 void mpam_disable(struct work_struct *work);
458
459 /* Reset all the RIS in a class under cpus_read_lock() */
460 void mpam_reset_class_locked(struct mpam_class *class);
461
462 int mpam_apply_config(struct mpam_component *comp, u16 partid,
463 struct mpam_config *cfg);
464
465 int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx,
466 enum mpam_device_features, u64 *val);
467 void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ctx);
468
469 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level,
470 cpumask_t *affinity);
471
472 #ifdef CONFIG_RESCTRL_FS
473 int mpam_resctrl_setup(void);
474 void mpam_resctrl_exit(void);
475 int mpam_resctrl_online_cpu(unsigned int cpu);
476 void mpam_resctrl_offline_cpu(unsigned int cpu);
477 void mpam_resctrl_teardown_class(struct mpam_class *class);
478 #else
mpam_resctrl_setup(void)479 static inline int mpam_resctrl_setup(void) { return 0; }
mpam_resctrl_exit(void)480 static inline void mpam_resctrl_exit(void) { }
mpam_resctrl_online_cpu(unsigned int cpu)481 static inline int mpam_resctrl_online_cpu(unsigned int cpu) { return 0; }
mpam_resctrl_offline_cpu(unsigned int cpu)482 static inline void mpam_resctrl_offline_cpu(unsigned int cpu) { }
mpam_resctrl_teardown_class(struct mpam_class * class)483 static inline void mpam_resctrl_teardown_class(struct mpam_class *class) { }
484 #endif /* CONFIG_RESCTRL_FS */
485
486 /*
487 * MPAM MSCs have the following register layout. See:
488 * Arm Memory System Resource Partitioning and Monitoring (MPAM) System
489 * Component Specification.
490 * https://developer.arm.com/documentation/ihi0099/aa/
491 */
492 #define MPAM_ARCHITECTURE_V1 0x10
493
494 /* Memory mapped control pages */
495 /* ID Register offsets in the memory mapped page */
496 #define MPAMF_IDR 0x0000 /* features id register */
497 #define MPAMF_IIDR 0x0018 /* implementer id register */
498 #define MPAMF_AIDR 0x0020 /* architectural id register */
499 #define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */
500 #define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */
501 #define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */
502 #define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */
503 #define MPAMF_PRI_IDR 0x0048 /* priority partitioning */
504 #define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */
505 #define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */
506 #define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */
507 #define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */
508
509 /* Configuration and Status Register offsets in the memory mapped page */
510 #define MPAMCFG_PART_SEL 0x0100 /* partid to configure */
511 #define MPAMCFG_CPBM 0x1000 /* cache-portion config */
512 #define MPAMCFG_CMAX 0x0108 /* cache-capacity config */
513 #define MPAMCFG_CMIN 0x0110 /* cache-capacity config */
514 #define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */
515 #define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */
516 #define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */
517 #define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */
518 #define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */
519 #define MPAMCFG_PRI 0x0400 /* priority partitioning config */
520 #define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */
521 #define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */
522
523 #define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */
524 #define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */
525 #define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */
526 #define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */
527 #define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */
528 #define MSMON_CSU 0x0840 /* current cache-usage */
529 #define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */
530 #define MSMON_MBWU 0x0860 /* current mem-bw usage value */
531 #define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */
532 #define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */
533 #define MSMON_MBWU_L_CAPTURE 0x0890 /* last long mem-bw value captured */
534 #define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */
535 #define MPAMF_ESR 0x00F8 /* error status register */
536 #define MPAMF_ECR 0x00F0 /* error control register */
537
538 /* MPAMF_IDR - MPAM features ID register */
539 #define MPAMF_IDR_PARTID_MAX GENMASK(15, 0)
540 #define MPAMF_IDR_PMG_MAX GENMASK(23, 16)
541 #define MPAMF_IDR_HAS_CCAP_PART BIT(24)
542 #define MPAMF_IDR_HAS_CPOR_PART BIT(25)
543 #define MPAMF_IDR_HAS_MBW_PART BIT(26)
544 #define MPAMF_IDR_HAS_PRI_PART BIT(27)
545 #define MPAMF_IDR_EXT BIT(28)
546 #define MPAMF_IDR_HAS_IMPL_IDR BIT(29)
547 #define MPAMF_IDR_HAS_MSMON BIT(30)
548 #define MPAMF_IDR_HAS_PARTID_NRW BIT(31)
549 #define MPAMF_IDR_HAS_RIS BIT(32)
550 #define MPAMF_IDR_HAS_EXTD_ESR BIT(38)
551 #define MPAMF_IDR_HAS_ESR BIT(39)
552 #define MPAMF_IDR_RIS_MAX GENMASK(59, 56)
553
554 /* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */
555 #define MPAMF_MSMON_IDR_MSMON_CSU BIT(16)
556 #define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17)
557 #define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31)
558
559 /* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */
560 #define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0)
561
562 /* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register */
563 #define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0)
564 #define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8)
565 #define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28)
566 #define MPAMF_CCAP_IDR_HAS_CMIN BIT(29)
567 #define MPAMF_CCAP_IDR_NO_CMAX BIT(30)
568 #define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31)
569
570 /* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register */
571 #define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0)
572 #define MPAMF_MBW_IDR_HAS_MIN BIT(10)
573 #define MPAMF_MBW_IDR_HAS_MAX BIT(11)
574 #define MPAMF_MBW_IDR_HAS_PBM BIT(12)
575 #define MPAMF_MBW_IDR_HAS_PROP BIT(13)
576 #define MPAMF_MBW_IDR_WINDWR BIT(14)
577 #define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16)
578
579 /* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */
580 #define MPAMF_PRI_IDR_HAS_INTPRI BIT(0)
581 #define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1)
582 #define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4)
583 #define MPAMF_PRI_IDR_HAS_DSPRI BIT(16)
584 #define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17)
585 #define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20)
586
587 /* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */
588 #define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0)
589 #define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24)
590 #define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25)
591 #define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26)
592 #define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27)
593 #define MPAMF_CSUMON_IDR_HAS_XCL BIT(29)
594 #define MPAMF_CSUMON_IDR_CSU_RO BIT(30)
595 #define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31)
596
597 /* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */
598 #define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0)
599 #define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28)
600 #define MPAMF_MBWUMON_IDR_LWD BIT(29)
601 #define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30)
602 #define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31)
603
604 /* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */
605 #define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0)
606
607 /* MPAMF_IIDR - MPAM implementation ID register */
608 #define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0)
609 #define MPAMF_IIDR_REVISION GENMASK(15, 12)
610 #define MPAMF_IIDR_VARIANT GENMASK(19, 16)
611 #define MPAMF_IIDR_PRODUCTID GENMASK(31, 20)
612
613 /* MPAMF_AIDR - MPAM architecture ID register */
614 #define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0)
615 #define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4)
616
617 /* MPAMCFG_PART_SEL - MPAM partition configuration selection register */
618 #define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0)
619 #define MPAMCFG_PART_SEL_INTERNAL BIT(16)
620 #define MPAMCFG_PART_SEL_RIS GENMASK(27, 24)
621
622 /* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configuration register */
623 #define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0)
624
625 /* MPAMCFG_CMAX - MPAM cache capacity configuration register */
626 #define MPAMCFG_CMAX_SOFTLIM BIT(31)
627 #define MPAMCFG_CMAX_CMAX GENMASK(15, 0)
628
629 /* MPAMCFG_CMIN - MPAM cache capacity configuration register */
630 #define MPAMCFG_CMIN_CMIN GENMASK(15, 0)
631
632 /*
633 * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configuration
634 * register
635 */
636 #define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0)
637
638 /*
639 * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configuration
640 * register
641 */
642 #define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0)
643 #define MPAMCFG_MBW_MAX_HARDLIM BIT(31)
644
645 /*
646 * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width
647 * register
648 */
649 #define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0)
650 #define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8)
651
652 /* MPAMCFG_PRI - MPAM priority partitioning configuration register */
653 #define MPAMCFG_PRI_INTPRI GENMASK(15, 0)
654 #define MPAMCFG_PRI_DSPRI GENMASK(31, 16)
655
656 /*
657 * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning
658 * configuration register
659 */
660 #define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0)
661 #define MPAMCFG_MBW_PROP_EN BIT(31)
662
663 /*
664 * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration register
665 */
666 #define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0)
667 #define MPAMCFG_INTPARTID_INTERNAL BIT(16)
668
669 /* MSMON_CFG_MON_SEL - Memory system performance monitor selection register */
670 #define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0)
671 #define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24)
672
673 /* MPAMF_ESR - MPAM Error Status Register */
674 #define MPAMF_ESR_PARTID_MON GENMASK(15, 0)
675 #define MPAMF_ESR_PMG GENMASK(23, 16)
676 #define MPAMF_ESR_ERRCODE GENMASK(27, 24)
677 #define MPAMF_ESR_OVRWR BIT(31)
678 #define MPAMF_ESR_RIS GENMASK(35, 32)
679
680 /* MPAMF_ECR - MPAM Error Control Register */
681 #define MPAMF_ECR_INTEN BIT(0)
682
683 /* Error conditions in accessing memory mapped registers */
684 #define MPAM_ERRCODE_NONE 0
685 #define MPAM_ERRCODE_PARTID_SEL_RANGE 1
686 #define MPAM_ERRCODE_REQ_PARTID_RANGE 2
687 #define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3
688 #define MPAM_ERRCODE_REQ_PMG_RANGE 4
689 #define MPAM_ERRCODE_MONITOR_RANGE 5
690 #define MPAM_ERRCODE_INTPARTID_RANGE 6
691 #define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7
692 #define MPAM_ERRCODE_UNDEFINED_RIS_PART_SEL 8
693 #define MPAM_ERRCODE_RIS_NO_CONTROL 9
694 #define MPAM_ERRCODE_UNDEFINED_RIS_MON_SEL 10
695 #define MPAM_ERRCODE_RIS_NO_MONITOR 11
696
697 /*
698 * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache storage
699 * usage monitor control register
700 * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory
701 * bandwidth usage monitor control register
702 */
703 #define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0)
704 #define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15)
705 #define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16)
706 #define MSMON_CFG_x_CTL_MATCH_PMG BIT(17)
707 #define MSMON_CFG_MBWU_CTL_SCLEN BIT(19)
708 #define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20)
709 #define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24)
710 #define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25)
711 #define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26)
712 #define MSMON_CFG_x_CTL_CAPT_RESET BIT(27)
713 #define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28)
714 #define MSMON_CFG_x_CTL_EN BIT(31)
715
716 #define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42
717 #define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43
718
719 /*
720 * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache storage
721 * usage monitor filter register
722 * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory
723 * bandwidth usage monitor filter register
724 */
725 #define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0)
726 #define MSMON_CFG_x_FLT_PMG GENMASK(23, 16)
727
728 #define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30)
729 #define MSMON_CFG_CSU_FLT_XCL BIT(31)
730
731 /*
732 * MSMON_CSU - Memory system performance monitor cache storage usage monitor
733 * register
734 * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage usage
735 * capture register
736 * MSMON_MBWU - Memory system performance monitor memory bandwidth usage
737 * monitor register
738 * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth usage
739 * capture register
740 */
741 #define MSMON___VALUE GENMASK(30, 0)
742 #define MSMON___NRDY BIT(31)
743 #define MSMON___L_NRDY BIT(63)
744 #define MSMON___L_VALUE GENMASK(43, 0)
745 #define MSMON___LWD_VALUE GENMASK(62, 0)
746
747 /*
748 * MSMON_CAPT_EVNT - Memory system performance monitoring capture event
749 * generation register
750 */
751 #define MSMON_CAPT_EVNT_NOW BIT(0)
752
753 #endif /* MPAM_INTERNAL_H */
754