1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2020-2025 Intel Corporation
4 */
5
6 #ifndef __IVPU_DRV_H__
7 #define __IVPU_DRV_H__
8
9 #include <drm/drm_device.h>
10 #include <drm/drm_drv.h>
11 #include <drm/drm_managed.h>
12 #include <drm/drm_mm.h>
13 #include <drm/drm_print.h>
14
15 #include <linux/pci.h>
16 #include <linux/xarray.h>
17 #include <uapi/drm/ivpu_accel.h>
18
19 #include "ivpu_mmu_context.h"
20 #include "ivpu_ipc.h"
21
22 #define DRIVER_NAME "intel_vpu"
23 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
24
25 #define PCI_DEVICE_ID_MTL 0x7d1d
26 #define PCI_DEVICE_ID_ARL 0xad1d
27 #define PCI_DEVICE_ID_LNL 0x643e
28 #define PCI_DEVICE_ID_PTL_P 0xb03e
29 #define PCI_DEVICE_ID_WCL 0xfd3e
30 #define PCI_DEVICE_ID_NVL 0xd71d
31
32 #define IVPU_HW_IP_37XX 37
33 #define IVPU_HW_IP_40XX 40
34 #define IVPU_HW_IP_50XX 50
35 #define IVPU_HW_IP_60XX 60
36
37 #define IVPU_HW_IP_REV_LNL_B0 4
38 #define IVPU_HW_IP_REV_NVL_A0 0
39
40 #define IVPU_HW_BTRS_MTL 1
41 #define IVPU_HW_BTRS_LNL 2
42
43 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
44 /* SSID 1 is used by the VPU to represent reserved context */
45 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1
46 #define IVPU_USER_CONTEXT_MIN_SSID 2
47 #define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63)
48
49 #define IVPU_MIN_DB 1
50 #define IVPU_MAX_DB 255
51
52 #define IVPU_JOB_ID_JOB_MASK GENMASK(7, 0)
53 #define IVPU_JOB_ID_CONTEXT_MASK GENMASK(31, 8)
54
55 #define IVPU_NUM_PRIORITIES 4
56 #define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_PRIORITIES)
57
58 #define IVPU_CMDQ_MIN_ID 1
59 #define IVPU_CMDQ_MAX_ID 255
60
61 #define IVPU_PLATFORM_SILICON 0
62 #define IVPU_PLATFORM_SIMICS 2
63 #define IVPU_PLATFORM_FPGA 3
64 #define IVPU_PLATFORM_HSLE 4
65 #define IVPU_PLATFORM_INVALID 8
66
67 #define IVPU_SCHED_MODE_AUTO -1
68
69 #define IVPU_DBG_REG BIT(0)
70 #define IVPU_DBG_IRQ BIT(1)
71 #define IVPU_DBG_MMU BIT(2)
72 #define IVPU_DBG_FILE BIT(3)
73 #define IVPU_DBG_MISC BIT(4)
74 #define IVPU_DBG_FW_BOOT BIT(5)
75 #define IVPU_DBG_PM BIT(6)
76 #define IVPU_DBG_IPC BIT(7)
77 #define IVPU_DBG_BO BIT(8)
78 #define IVPU_DBG_JOB BIT(9)
79 #define IVPU_DBG_JSM BIT(10)
80 #define IVPU_DBG_KREF BIT(11)
81 #define IVPU_DBG_RPM BIT(12)
82 #define IVPU_DBG_MMU_MAP BIT(13)
83 #define IVPU_DBG_IOCTL BIT(14)
84
85 #define ivpu_err(vdev, fmt, ...) \
86 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
87
88 #define ivpu_err_ratelimited(vdev, fmt, ...) \
89 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
90
91 #define ivpu_warn(vdev, fmt, ...) \
92 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
93
94 #define ivpu_warn_ratelimited(vdev, fmt, ...) \
95 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
96
97 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
98
99 #define ivpu_dbg(vdev, type, fmt, args...) do { \
100 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \
101 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \
102 } while (0)
103
104 #define IVPU_WA(wa_name) (vdev->wa.wa_name)
105
106 #define IVPU_PRINT_WA(wa_name) do { \
107 if (IVPU_WA(wa_name)) \
108 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
109 } while (0)
110
111 struct ivpu_wa_table {
112 bool punit_disabled;
113 bool clear_runtime_mem;
114 bool interrupt_clear_with_0;
115 bool disable_clock_relinquish;
116 bool disable_d0i3_msg;
117 bool wp0_during_power_up;
118 bool disable_d0i2;
119 };
120
121 struct ivpu_hw_info;
122 struct ivpu_mmu_info;
123 struct ivpu_fw_info;
124 struct ivpu_ipc_info;
125 struct ivpu_pm_info;
126
127 struct ivpu_device {
128 struct drm_device drm;
129 void __iomem *regb;
130 void __iomem *regv;
131 u32 platform;
132 u32 irq;
133
134 struct ivpu_wa_table wa;
135 struct ivpu_hw_info *hw;
136 struct ivpu_mmu_info *mmu;
137 struct ivpu_fw_info *fw;
138 struct ivpu_ipc_info *ipc;
139 struct ivpu_pm_info *pm;
140
141 struct ivpu_mmu_context gctx;
142 struct ivpu_mmu_context rctx;
143 struct mutex context_list_lock; /* Protects user context addition/removal */
144 struct xarray context_xa;
145 struct xa_limit context_xa_limit;
146
147 struct xarray db_xa;
148 struct xa_limit db_limit;
149 u32 db_next;
150
151 struct work_struct irq_ipc_work;
152 struct work_struct irq_dct_work;
153 struct work_struct context_abort_work;
154
155 struct mutex bo_list_lock; /* Protects bo_list */
156 struct list_head bo_list;
157
158 struct mutex submitted_jobs_lock; /* Protects submitted_jobs */
159 struct xarray submitted_jobs_xa;
160 struct ivpu_ipc_consumer job_done_consumer;
161 atomic_t job_timeout_counter;
162
163 atomic64_t unique_id_counter;
164
165 ktime_t busy_start_ts;
166 ktime_t busy_time;
167
168 struct {
169 int boot;
170 int jsm;
171 int tdr;
172 int inference;
173 int autosuspend;
174 int d0i3_entry_msg;
175 int state_dump_msg;
176 } timeout;
177 };
178
179 /*
180 * file_priv has its own refcount (ref) that allows user space to close the fd
181 * without blocking even if VPU is still processing some jobs.
182 */
183 struct ivpu_file_priv {
184 struct kref ref;
185 struct ivpu_device *vdev;
186 struct mutex lock; /* Protects cmdq */
187 struct xarray cmdq_xa;
188 struct ivpu_mmu_context ctx;
189 struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */
190 struct list_head ms_instance_list;
191 struct ivpu_bo *ms_info_bo;
192 struct xa_limit job_limit;
193 u32 job_id_next;
194 struct xa_limit cmdq_limit;
195 u32 cmdq_id_next;
196 bool has_mmu_faults;
197 bool bound;
198 bool aborted;
199 };
200
201 extern int ivpu_dbg_mask;
202 extern u8 ivpu_pll_min_ratio;
203 extern u8 ivpu_pll_max_ratio;
204 extern int ivpu_sched_mode;
205 extern bool ivpu_disable_mmu_cont_pages;
206 extern bool ivpu_force_snoop;
207
208 #define IVPU_TEST_MODE_FW_TEST BIT(0)
209 #define IVPU_TEST_MODE_NULL_HW BIT(1)
210 #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2)
211 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)
212 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)
213 #define IVPU_TEST_MODE_MIP_DISABLE BIT(6)
214 #define IVPU_TEST_MODE_DISABLE_TIMEOUTS BIT(8)
215 #define IVPU_TEST_MODE_TURBO_ENABLE BIT(9)
216 #define IVPU_TEST_MODE_TURBO_DISABLE BIT(10)
217 #define IVPU_TEST_MODE_CLK_RELINQ_DISABLE BIT(11)
218 #define IVPU_TEST_MODE_CLK_RELINQ_ENABLE BIT(12)
219 #define IVPU_TEST_MODE_D0I2_DISABLE BIT(13)
220 extern int ivpu_test_mode;
221
222 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
223 void ivpu_file_priv_put(struct ivpu_file_priv **link);
224
225 int ivpu_boot(struct ivpu_device *vdev);
226 int ivpu_shutdown(struct ivpu_device *vdev);
227 void ivpu_prepare_for_reset(struct ivpu_device *vdev);
228 bool ivpu_is_capable(struct ivpu_device *vdev, u32 capability);
229
ivpu_revision(struct ivpu_device * vdev)230 static inline u8 ivpu_revision(struct ivpu_device *vdev)
231 {
232 return to_pci_dev(vdev->drm.dev)->revision;
233 }
234
ivpu_device_id(struct ivpu_device * vdev)235 static inline u16 ivpu_device_id(struct ivpu_device *vdev)
236 {
237 return to_pci_dev(vdev->drm.dev)->device;
238 }
239
ivpu_hw_ip_gen(struct ivpu_device * vdev)240 static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)
241 {
242 switch (ivpu_device_id(vdev)) {
243 case PCI_DEVICE_ID_MTL:
244 case PCI_DEVICE_ID_ARL:
245 return IVPU_HW_IP_37XX;
246 case PCI_DEVICE_ID_LNL:
247 return IVPU_HW_IP_40XX;
248 case PCI_DEVICE_ID_PTL_P:
249 case PCI_DEVICE_ID_WCL:
250 return IVPU_HW_IP_50XX;
251 case PCI_DEVICE_ID_NVL:
252 return IVPU_HW_IP_60XX;
253 default:
254 dump_stack();
255 ivpu_err(vdev, "Unknown NPU IP generation\n");
256 return 0;
257 }
258 }
259
ivpu_hw_btrs_gen(struct ivpu_device * vdev)260 static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)
261 {
262 switch (ivpu_device_id(vdev)) {
263 case PCI_DEVICE_ID_MTL:
264 case PCI_DEVICE_ID_ARL:
265 return IVPU_HW_BTRS_MTL;
266 case PCI_DEVICE_ID_LNL:
267 case PCI_DEVICE_ID_PTL_P:
268 case PCI_DEVICE_ID_WCL:
269 case PCI_DEVICE_ID_NVL:
270 return IVPU_HW_BTRS_LNL;
271 default:
272 dump_stack();
273 ivpu_err(vdev, "Unknown buttress generation\n");
274 return 0;
275 }
276 }
277
to_ivpu_device(struct drm_device * dev)278 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
279 {
280 return container_of(dev, struct ivpu_device, drm);
281 }
282
ivpu_get_context_count(struct ivpu_device * vdev)283 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
284 {
285 struct xa_limit ctx_limit = vdev->context_xa_limit;
286
287 return (ctx_limit.max - ctx_limit.min + 1);
288 }
289
ivpu_get_platform(struct ivpu_device * vdev)290 static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
291 {
292 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
293 return vdev->platform;
294 }
295
ivpu_is_silicon(struct ivpu_device * vdev)296 static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
297 {
298 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
299 }
300
ivpu_is_simics(struct ivpu_device * vdev)301 static inline bool ivpu_is_simics(struct ivpu_device *vdev)
302 {
303 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
304 }
305
ivpu_is_fpga(struct ivpu_device * vdev)306 static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
307 {
308 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA ||
309 ivpu_get_platform(vdev) == IVPU_PLATFORM_HSLE;
310 }
311
ivpu_is_force_snoop_enabled(struct ivpu_device * vdev)312 static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev)
313 {
314 return ivpu_force_snoop;
315 }
316
317 #endif /* __IVPU_DRV_H__ */
318