1 /* 2 * PMC-Sierra 8001/8081/8088/8089 SAS/SATA based host adapters driver 3 * 4 * Copyright (c) 2008-2009 USI Co., Ltd. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon 16 * including a substantially similar Disclaimer requirement for further 17 * binary redistribution. 18 * 3. Neither the names of the above-listed copyright holders nor the names 19 * of any contributors may be used to endorse or promote products derived 20 * from this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * NO WARRANTY 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGES. 38 * 39 */ 40 41 #ifndef _PM8001_DEFS_H_ 42 #define _PM8001_DEFS_H_ 43 44 #include <scsi/sas.h> 45 46 #ifdef __LITTLE_ENDIAN_BITFIELD 47 struct sas_identify_frame_local { 48 /* Byte 0 */ 49 u8 frame_type:4; 50 u8 dev_type:3; 51 u8 _un0:1; 52 53 /* Byte 1 */ 54 u8 _un1; 55 56 /* Byte 2 */ 57 union { 58 struct { 59 u8 _un20:1; 60 u8 smp_iport:1; 61 u8 stp_iport:1; 62 u8 ssp_iport:1; 63 u8 _un247:4; 64 }; 65 u8 initiator_bits; 66 }; 67 68 /* Byte 3 */ 69 union { 70 struct { 71 u8 _un30:1; 72 u8 smp_tport:1; 73 u8 stp_tport:1; 74 u8 ssp_tport:1; 75 u8 _un347:4; 76 }; 77 u8 target_bits; 78 }; 79 80 /* Byte 4 - 11 */ 81 u8 _un4_11[8]; 82 83 /* Byte 12 - 19 */ 84 u8 sas_addr[SAS_ADDR_SIZE]; 85 86 /* Byte 20 */ 87 u8 phy_id; 88 89 u8 _un21_27[7]; 90 91 } __packed; 92 93 #elif defined(__BIG_ENDIAN_BITFIELD) 94 struct sas_identify_frame_local { 95 /* Byte 0 */ 96 u8 _un0:1; 97 u8 dev_type:3; 98 u8 frame_type:4; 99 100 /* Byte 1 */ 101 u8 _un1; 102 103 /* Byte 2 */ 104 union { 105 struct { 106 u8 _un247:4; 107 u8 ssp_iport:1; 108 u8 stp_iport:1; 109 u8 smp_iport:1; 110 u8 _un20:1; 111 }; 112 u8 initiator_bits; 113 }; 114 115 /* Byte 3 */ 116 union { 117 struct { 118 u8 _un347:4; 119 u8 ssp_tport:1; 120 u8 stp_tport:1; 121 u8 smp_tport:1; 122 u8 _un30:1; 123 }; 124 u8 target_bits; 125 }; 126 127 /* Byte 4 - 11 */ 128 u8 _un4_11[8]; 129 130 /* Byte 12 - 19 */ 131 u8 sas_addr[SAS_ADDR_SIZE]; 132 133 /* Byte 20 */ 134 u8 phy_id; 135 136 u8 _un21_27[7]; 137 } __packed; 138 #else 139 #error "Bitfield order not defined!" 140 #endif 141 142 enum chip_flavors { 143 chip_8001, 144 chip_8008, 145 chip_8009, 146 chip_8018, 147 chip_8019, 148 chip_8074, 149 chip_8076, 150 chip_8077, 151 chip_8006, 152 chip_8070, 153 chip_8072 154 }; 155 156 enum phy_speed { 157 PHY_SPEED_15 = 0x01, 158 PHY_SPEED_30 = 0x02, 159 PHY_SPEED_60 = 0x04, 160 PHY_SPEED_120 = 0x08, 161 }; 162 163 enum data_direction { 164 DATA_DIR_NONE = 0x0, /* NO TRANSFER */ 165 DATA_DIR_IN = 0x01, /* INBOUND */ 166 DATA_DIR_OUT = 0x02, /* OUTBOUND */ 167 DATA_DIR_BYRECIPIENT = 0x04, /* UNSPECIFIED */ 168 }; 169 170 enum port_type { 171 PORT_TYPE_SAS = (1L << 1), 172 PORT_TYPE_SATA = (1L << 0), 173 }; 174 175 /* driver compile-time configuration */ 176 #define PM8001_MAX_CCB 1024 /* max ccbs supported */ 177 #define PM8001_MPI_QUEUE 1024 /* maximum mpi queue entries */ 178 #define PM8001_MAX_INB_NUM 64 179 #define PM8001_MAX_OUTB_NUM 64 180 #define PM8001_CAN_QUEUE 508 /* SCSI Queue depth */ 181 182 /* Inbound/Outbound queue size */ 183 #define IOMB_SIZE_SPC 64 184 #define IOMB_SIZE_SPCV 128 185 186 /* unchangeable hardware details */ 187 #define PM8001_MAX_PHYS 16 /* max. possible phys */ 188 #define PM8001_MAX_PORTS 16 /* max. possible ports */ 189 #define PM8001_MAX_DEVICES 2048 /* max supported device */ 190 #define PM8001_MAX_MSIX_VEC 64 /* max msi-x int for spcv/ve */ 191 #define PM8001_RESERVE_SLOT 128 192 193 #define PM8001_SECTOR_SIZE 512 194 #define PM8001_PAGE_SIZE_4K 4096 195 #define PM8001_MAX_IO_SIZE (4 * 1024 * 1024) 196 #define PM8001_MAX_DMA_SG (PM8001_MAX_IO_SIZE / PM8001_PAGE_SIZE_4K) 197 #define PM8001_MAX_SECTORS (PM8001_MAX_IO_SIZE / PM8001_SECTOR_SIZE) 198 199 enum memory_region_num { 200 AAP1 = 0x0, /* application acceleration processor */ 201 IOP, /* IO processor */ 202 NVMD, /* NVM device */ 203 FW_FLASH, /* memory for fw flash update */ 204 FORENSIC_MEM, /* memory for fw forensic data */ 205 USI_MAX_MEMCNT_BASE 206 }; 207 #define PM8001_EVENT_LOG_SIZE (128 * 1024) 208 209 /** 210 * maximum DMA memory regions(number of IBQ + number of IBQ CI 211 * + number of OBQ + number of OBQ PI) 212 */ 213 #define USI_MAX_MEMCNT (USI_MAX_MEMCNT_BASE + ((2 * PM8001_MAX_INB_NUM) \ 214 + (2 * PM8001_MAX_OUTB_NUM))) 215 /*error code*/ 216 enum mpi_err { 217 MPI_IO_STATUS_SUCCESS = 0x0, 218 MPI_IO_STATUS_BUSY = 0x01, 219 MPI_IO_STATUS_FAIL = 0x02, 220 }; 221 222 /** 223 * Phy Control constants 224 */ 225 enum phy_control_type { 226 PHY_LINK_RESET = 0x01, 227 PHY_HARD_RESET = 0x02, 228 PHY_NOTIFY_ENABLE_SPINUP = 0x10, 229 }; 230 231 enum pm8001_hba_info_flags { 232 PM8001F_INIT_TIME = (1U << 0), 233 PM8001F_RUN_TIME = (1U << 1), 234 }; 235 236 /** 237 * Phy Status 238 */ 239 #define PHY_LINK_DISABLE 0x00 240 #define PHY_LINK_DOWN 0x01 241 #define PHY_STATE_LINK_UP_SPCV 0x2 242 #define PHY_STATE_LINK_UP_SPC 0x1 243 244 #endif 245