1 /*
2 * Copyright (c) 2017-2018 Cavium, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 /*
29 * File: qlnx_os.c
30 * Author : David C Somayajulu, Cavium, Inc., San Jose, CA 95131.
31 */
32
33 #include <sys/cdefs.h>
34 #include "qlnx_os.h"
35 #include <net/rss_config.h>
36 #include "bcm_osal.h"
37 #include "reg_addr.h"
38 #include "ecore_gtt_reg_addr.h"
39 #include "ecore.h"
40 #include "ecore_chain.h"
41 #include "ecore_status.h"
42 #include "ecore_hw.h"
43 #include "ecore_rt_defs.h"
44 #include "ecore_init_ops.h"
45 #include "ecore_int.h"
46 #include "ecore_cxt.h"
47 #include "ecore_spq.h"
48 #include "ecore_init_fw_funcs.h"
49 #include "ecore_sp_commands.h"
50 #include "ecore_dev_api.h"
51 #include "ecore_l2_api.h"
52 #include "ecore_l2.h"
53 #include "ecore_mcp.h"
54 #include "ecore_hw_defs.h"
55 #include "mcp_public.h"
56 #include "ecore_iro.h"
57 #include "nvm_cfg.h"
58 #include "ecore_dbg_fw_funcs.h"
59 #include "ecore_iov_api.h"
60 #include "ecore_vf_api.h"
61 #include "ecore_vf.h"
62
63 #include "qlnx_ioctl.h"
64 #include "qlnx_def.h"
65 #include "qlnx_ver.h"
66
67 #ifdef QLNX_ENABLE_IWARP
68 #include "qlnx_rdma.h"
69 #endif /* #ifdef QLNX_ENABLE_IWARP */
70
71 #ifdef CONFIG_ECORE_SRIOV
72 #include <sys/nv.h>
73 #include <sys/iov_schema.h>
74 #include <dev/pci/pci_iov.h>
75 #endif /* #ifdef CONFIG_ECORE_SRIOV */
76
77 #include <sys/smp.h>
78
79 /*
80 * static functions
81 */
82 /*
83 * ioctl related functions
84 */
85 static void qlnx_add_sysctls(qlnx_host_t *ha);
86
87 /*
88 * main driver
89 */
90 static void qlnx_release(qlnx_host_t *ha);
91 static void qlnx_fp_isr(void *arg);
92 static void qlnx_init_ifnet(device_t dev, qlnx_host_t *ha);
93 static void qlnx_init(void *arg);
94 static void qlnx_init_locked(qlnx_host_t *ha);
95 static int qlnx_set_multi(qlnx_host_t *ha);
96 static int qlnx_set_promisc_allmulti(qlnx_host_t *ha, int flags);
97 static int _qlnx_set_promisc_allmulti(qlnx_host_t *ha, bool promisc, bool allmulti);
98 static int qlnx_ioctl(if_t ifp, u_long cmd, caddr_t data);
99 static int qlnx_media_change(if_t ifp);
100 static void qlnx_media_status(if_t ifp, struct ifmediareq *ifmr);
101 static void qlnx_stop(qlnx_host_t *ha);
102 static int qlnx_send(qlnx_host_t *ha, struct qlnx_fastpath *fp,
103 struct mbuf **m_headp);
104 static int qlnx_get_ifq_snd_maxlen(qlnx_host_t *ha);
105 static void qlnx_get_mac_addr(qlnx_host_t *ha);
106 static uint32_t qlnx_get_optics(qlnx_host_t *ha,
107 struct qlnx_link_output *if_link);
108 static int qlnx_transmit(if_t ifp, struct mbuf *mp);
109 static int qlnx_transmit_locked(if_t ifp, struct qlnx_fastpath *fp,
110 struct mbuf *mp);
111 static void qlnx_qflush(if_t ifp);
112
113 static int qlnx_alloc_parent_dma_tag(qlnx_host_t *ha);
114 static void qlnx_free_parent_dma_tag(qlnx_host_t *ha);
115 static int qlnx_alloc_tx_dma_tag(qlnx_host_t *ha);
116 static void qlnx_free_tx_dma_tag(qlnx_host_t *ha);
117 static int qlnx_alloc_rx_dma_tag(qlnx_host_t *ha);
118 static void qlnx_free_rx_dma_tag(qlnx_host_t *ha);
119
120 static int qlnx_get_mfw_version(qlnx_host_t *ha, uint32_t *mfw_ver);
121 static int qlnx_get_flash_size(qlnx_host_t *ha, uint32_t *flash_size);
122
123 static int qlnx_nic_setup(struct ecore_dev *cdev,
124 struct ecore_pf_params *func_params);
125 static int qlnx_nic_start(struct ecore_dev *cdev);
126 static int qlnx_slowpath_start(qlnx_host_t *ha);
127 static int qlnx_slowpath_stop(qlnx_host_t *ha);
128 static int qlnx_init_hw(qlnx_host_t *ha);
129 static void qlnx_set_id(struct ecore_dev *cdev, char name[NAME_SIZE],
130 char ver_str[VER_SIZE]);
131 static void qlnx_unload(qlnx_host_t *ha);
132 static int qlnx_load(qlnx_host_t *ha);
133 static void qlnx_dump_buf8(qlnx_host_t *ha, const char *msg, void *dbuf,
134 uint32_t len);
135 static int qlnx_alloc_rx_buffer(qlnx_host_t *ha, struct qlnx_rx_queue *rxq);
136 static void qlnx_reuse_rx_data(struct qlnx_rx_queue *rxq);
137 static void qlnx_update_rx_prod(struct ecore_hwfn *p_hwfn,
138 struct qlnx_rx_queue *rxq);
139 static int qlnx_remove_all_mcast_mac(qlnx_host_t *ha);
140 static int qlnx_set_rx_accept_filter(qlnx_host_t *ha, uint8_t filter);
141 static int qlnx_grc_dumpsize(qlnx_host_t *ha, uint32_t *num_dwords,
142 int hwfn_index);
143 static int qlnx_idle_chk_size(qlnx_host_t *ha, uint32_t *num_dwords,
144 int hwfn_index);
145 static void qlnx_timer(void *arg);
146 static int qlnx_alloc_tx_br(qlnx_host_t *ha, struct qlnx_fastpath *fp);
147 static void qlnx_free_tx_br(qlnx_host_t *ha, struct qlnx_fastpath *fp);
148 static void qlnx_trigger_dump(qlnx_host_t *ha);
149 static uint16_t qlnx_num_tx_compl(qlnx_host_t *ha, struct qlnx_fastpath *fp,
150 struct qlnx_tx_queue *txq);
151 static void qlnx_tx_int(qlnx_host_t *ha, struct qlnx_fastpath *fp,
152 struct qlnx_tx_queue *txq);
153 static int qlnx_rx_int(qlnx_host_t *ha, struct qlnx_fastpath *fp, int budget,
154 int lro_enable);
155 static void qlnx_fp_taskqueue(void *context, int pending);
156 static void qlnx_sample_storm_stats(qlnx_host_t *ha);
157 static int qlnx_alloc_tpa_mbuf(qlnx_host_t *ha, uint16_t rx_buf_size,
158 struct qlnx_agg_info *tpa);
159 static void qlnx_free_tpa_mbuf(qlnx_host_t *ha, struct qlnx_agg_info *tpa);
160
161 static uint64_t qlnx_get_counter(if_t ifp, ift_counter cnt);
162
163 /*
164 * Hooks to the Operating Systems
165 */
166 static int qlnx_pci_probe (device_t);
167 static int qlnx_pci_attach (device_t);
168 static int qlnx_pci_detach (device_t);
169
170 #ifndef QLNX_VF
171
172 #ifdef CONFIG_ECORE_SRIOV
173
174 static int qlnx_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params);
175 static void qlnx_iov_uninit(device_t dev);
176 static int qlnx_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params);
177 static void qlnx_initialize_sriov(qlnx_host_t *ha);
178 static void qlnx_pf_taskqueue(void *context, int pending);
179 static int qlnx_create_pf_taskqueues(qlnx_host_t *ha);
180 static void qlnx_destroy_pf_taskqueues(qlnx_host_t *ha);
181 static void qlnx_inform_vf_link_state(struct ecore_hwfn *p_hwfn, qlnx_host_t *ha);
182
183 #endif /* #ifdef CONFIG_ECORE_SRIOV */
184
185 static device_method_t qlnx_pci_methods[] = {
186 /* Device interface */
187 DEVMETHOD(device_probe, qlnx_pci_probe),
188 DEVMETHOD(device_attach, qlnx_pci_attach),
189 DEVMETHOD(device_detach, qlnx_pci_detach),
190
191 #ifdef CONFIG_ECORE_SRIOV
192 DEVMETHOD(pci_iov_init, qlnx_iov_init),
193 DEVMETHOD(pci_iov_uninit, qlnx_iov_uninit),
194 DEVMETHOD(pci_iov_add_vf, qlnx_iov_add_vf),
195 #endif /* #ifdef CONFIG_ECORE_SRIOV */
196 DEVMETHOD_END
197 };
198
199 static driver_t qlnx_pci_driver = {
200 "ql", qlnx_pci_methods, sizeof (qlnx_host_t),
201 };
202
203 MODULE_VERSION(if_qlnxe,1);
204 DRIVER_MODULE(if_qlnxe, pci, qlnx_pci_driver, 0, 0);
205
206 MODULE_DEPEND(if_qlnxe, pci, 1, 1, 1);
207 MODULE_DEPEND(if_qlnxe, ether, 1, 1, 1);
208
209 #else
210
211 static device_method_t qlnxv_pci_methods[] = {
212 /* Device interface */
213 DEVMETHOD(device_probe, qlnx_pci_probe),
214 DEVMETHOD(device_attach, qlnx_pci_attach),
215 DEVMETHOD(device_detach, qlnx_pci_detach),
216 DEVMETHOD_END
217 };
218
219 static driver_t qlnxv_pci_driver = {
220 "ql", qlnxv_pci_methods, sizeof (qlnx_host_t),
221 };
222
223 MODULE_VERSION(if_qlnxev,1);
224 DRIVER_MODULE(if_qlnxev, pci, qlnxv_pci_driver, 0, 0);
225
226 MODULE_DEPEND(if_qlnxev, pci, 1, 1, 1);
227 MODULE_DEPEND(if_qlnxev, ether, 1, 1, 1);
228
229 #endif /* #ifdef QLNX_VF */
230
231 MALLOC_DEFINE(M_QLNXBUF, "qlnxbuf", "Buffers for qlnx driver");
232
233 char qlnx_ver_str[VER_SIZE];
234 char qlnx_name_str[NAME_SIZE];
235
236 /*
237 * Some PCI Configuration Space Related Defines
238 */
239
240 #ifndef PCI_VENDOR_QLOGIC
241 #define PCI_VENDOR_QLOGIC 0x1077
242 #endif
243
244 /* 40G Adapter QLE45xxx*/
245 #ifndef QLOGIC_PCI_DEVICE_ID_1634
246 #define QLOGIC_PCI_DEVICE_ID_1634 0x1634
247 #endif
248
249 /* 100G Adapter QLE45xxx*/
250 #ifndef QLOGIC_PCI_DEVICE_ID_1644
251 #define QLOGIC_PCI_DEVICE_ID_1644 0x1644
252 #endif
253
254 /* 25G Adapter QLE45xxx*/
255 #ifndef QLOGIC_PCI_DEVICE_ID_1656
256 #define QLOGIC_PCI_DEVICE_ID_1656 0x1656
257 #endif
258
259 /* 50G Adapter QLE45xxx*/
260 #ifndef QLOGIC_PCI_DEVICE_ID_1654
261 #define QLOGIC_PCI_DEVICE_ID_1654 0x1654
262 #endif
263
264 /* 10G/25G/40G Adapter QLE41xxx*/
265 #ifndef QLOGIC_PCI_DEVICE_ID_8070
266 #define QLOGIC_PCI_DEVICE_ID_8070 0x8070
267 #endif
268
269 /* SRIOV Device (All Speeds) Adapter QLE41xxx*/
270 #ifndef QLOGIC_PCI_DEVICE_ID_8090
271 #define QLOGIC_PCI_DEVICE_ID_8090 0x8090
272 #endif
273
274 SYSCTL_NODE(_hw, OID_AUTO, qlnxe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
275 "qlnxe driver parameters");
276
277 /* Number of Queues: 0 (Auto) or 1 to 32 (fixed queue number) */
278 static int qlnxe_queue_count = QLNX_DEFAULT_RSS;
279
280 SYSCTL_INT(_hw_qlnxe, OID_AUTO, queue_count, CTLFLAG_RDTUN,
281 &qlnxe_queue_count, 0, "Multi-Queue queue count");
282
283 /*
284 * Note on RDMA personality setting
285 *
286 * Read the personality configured in NVRAM
287 * If the personality is ETH_ONLY, ETH_IWARP or ETH_ROCE and
288 * the configured personality in sysctl is QLNX_PERSONALITY_DEFAULT
289 * use the personality in NVRAM.
290
291 * Otherwise use t the personality configured in sysctl.
292 *
293 */
294 #define QLNX_PERSONALITY_DEFAULT 0x0 /* use personality in NVRAM */
295 #define QLNX_PERSONALITY_ETH_ONLY 0x1 /* Override with ETH_ONLY */
296 #define QLNX_PERSONALITY_ETH_IWARP 0x2 /* Override with ETH_IWARP */
297 #define QLNX_PERSONALITY_ETH_ROCE 0x3 /* Override with ETH_ROCE */
298 #define QLNX_PERSONALITY_BITS_PER_FUNC 4
299 #define QLNX_PERSONALIY_MASK 0xF
300
301 /* RDMA configuration; 64bit field allows setting for 16 physical functions*/
302 static uint64_t qlnxe_rdma_configuration = 0x22222222;
303
304 SYSCTL_U64(_hw_qlnxe, OID_AUTO, rdma_configuration, CTLFLAG_RDTUN,
305 &qlnxe_rdma_configuration, 0, "RDMA Configuration");
306
307 int
qlnx_vf_device(qlnx_host_t * ha)308 qlnx_vf_device(qlnx_host_t *ha)
309 {
310 uint16_t device_id;
311
312 device_id = ha->device_id;
313
314 if (device_id == QLOGIC_PCI_DEVICE_ID_8090)
315 return 0;
316
317 return -1;
318 }
319
320 static int
qlnx_valid_device(qlnx_host_t * ha)321 qlnx_valid_device(qlnx_host_t *ha)
322 {
323 uint16_t device_id;
324
325 device_id = ha->device_id;
326
327 #ifndef QLNX_VF
328 if ((device_id == QLOGIC_PCI_DEVICE_ID_1634) ||
329 (device_id == QLOGIC_PCI_DEVICE_ID_1644) ||
330 (device_id == QLOGIC_PCI_DEVICE_ID_1656) ||
331 (device_id == QLOGIC_PCI_DEVICE_ID_1654) ||
332 (device_id == QLOGIC_PCI_DEVICE_ID_8070))
333 return 0;
334 #else
335 if (device_id == QLOGIC_PCI_DEVICE_ID_8090)
336 return 0;
337
338 #endif /* #ifndef QLNX_VF */
339 return -1;
340 }
341
342 #ifdef QLNX_ENABLE_IWARP
343 static int
qlnx_rdma_supported(struct qlnx_host * ha)344 qlnx_rdma_supported(struct qlnx_host *ha)
345 {
346 uint16_t device_id;
347
348 device_id = pci_get_device(ha->pci_dev);
349
350 if ((device_id == QLOGIC_PCI_DEVICE_ID_1634) ||
351 (device_id == QLOGIC_PCI_DEVICE_ID_1656) ||
352 (device_id == QLOGIC_PCI_DEVICE_ID_1654) ||
353 (device_id == QLOGIC_PCI_DEVICE_ID_8070))
354 return (0);
355
356 return (-1);
357 }
358 #endif /* #ifdef QLNX_ENABLE_IWARP */
359
360 /*
361 * Name: qlnx_pci_probe
362 * Function: Validate the PCI device to be a QLA80XX device
363 */
364 static int
qlnx_pci_probe(device_t dev)365 qlnx_pci_probe(device_t dev)
366 {
367 snprintf(qlnx_ver_str, sizeof(qlnx_ver_str), "v%d.%d.%d",
368 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR, QLNX_VERSION_BUILD);
369 snprintf(qlnx_name_str, sizeof(qlnx_name_str), "qlnx");
370
371 if (pci_get_vendor(dev) != PCI_VENDOR_QLOGIC) {
372 return (ENXIO);
373 }
374
375 switch (pci_get_device(dev)) {
376 #ifndef QLNX_VF
377
378 case QLOGIC_PCI_DEVICE_ID_1644:
379 device_set_descf(dev, "%s v%d.%d.%d",
380 "Qlogic 100GbE PCI CNA Adapter-Ethernet Function",
381 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
382 QLNX_VERSION_BUILD);
383 break;
384
385 case QLOGIC_PCI_DEVICE_ID_1634:
386 device_set_descf(dev, "%s v%d.%d.%d",
387 "Qlogic 40GbE PCI CNA Adapter-Ethernet Function",
388 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
389 QLNX_VERSION_BUILD);
390 break;
391
392 case QLOGIC_PCI_DEVICE_ID_1656:
393 device_set_descf(dev, "%s v%d.%d.%d",
394 "Qlogic 25GbE PCI CNA Adapter-Ethernet Function",
395 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
396 QLNX_VERSION_BUILD);
397 break;
398
399 case QLOGIC_PCI_DEVICE_ID_1654:
400 device_set_descf(dev, "%s v%d.%d.%d",
401 "Qlogic 50GbE PCI CNA Adapter-Ethernet Function",
402 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
403 QLNX_VERSION_BUILD);
404 break;
405
406 case QLOGIC_PCI_DEVICE_ID_8070:
407 device_set_descf(dev, "%s v%d.%d.%d",
408 "Qlogic 10GbE/25GbE/40GbE PCI CNA (AH)"
409 " Adapter-Ethernet Function",
410 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
411 QLNX_VERSION_BUILD);
412 break;
413
414 #else
415 case QLOGIC_PCI_DEVICE_ID_8090:
416 device_set_descf(dev, "%s v%d.%d.%d",
417 "Qlogic SRIOV PCI CNA (AH) "
418 "Adapter-Ethernet Function",
419 QLNX_VERSION_MAJOR, QLNX_VERSION_MINOR,
420 QLNX_VERSION_BUILD);
421 break;
422
423 #endif /* #ifndef QLNX_VF */
424
425 default:
426 return (ENXIO);
427 }
428
429 #ifdef QLNX_ENABLE_IWARP
430 qlnx_rdma_init();
431 #endif /* #ifdef QLNX_ENABLE_IWARP */
432
433 return (BUS_PROBE_DEFAULT);
434 }
435
436 static uint16_t
qlnx_num_tx_compl(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_tx_queue * txq)437 qlnx_num_tx_compl(qlnx_host_t *ha, struct qlnx_fastpath *fp,
438 struct qlnx_tx_queue *txq)
439 {
440 u16 hw_bd_cons;
441 u16 ecore_cons_idx;
442
443 hw_bd_cons = le16toh(*txq->hw_cons_ptr);
444
445 ecore_cons_idx = ecore_chain_get_cons_idx(&txq->tx_pbl);
446
447 return (hw_bd_cons - ecore_cons_idx);
448 }
449
450 static void
qlnx_sp_intr(void * arg)451 qlnx_sp_intr(void *arg)
452 {
453 struct ecore_hwfn *p_hwfn;
454 qlnx_host_t *ha;
455 int i;
456
457 p_hwfn = arg;
458
459 if (p_hwfn == NULL) {
460 printf("%s: spurious slowpath intr\n", __func__);
461 return;
462 }
463
464 ha = (qlnx_host_t *)p_hwfn->p_dev;
465
466 QL_DPRINT2(ha, "enter\n");
467
468 for (i = 0; i < ha->cdev.num_hwfns; i++) {
469 if (&ha->cdev.hwfns[i] == p_hwfn) {
470 taskqueue_enqueue(ha->sp_taskqueue[i], &ha->sp_task[i]);
471 break;
472 }
473 }
474 QL_DPRINT2(ha, "exit\n");
475
476 return;
477 }
478
479 static void
qlnx_sp_taskqueue(void * context,int pending)480 qlnx_sp_taskqueue(void *context, int pending)
481 {
482 struct ecore_hwfn *p_hwfn;
483
484 p_hwfn = context;
485
486 if (p_hwfn != NULL) {
487 qlnx_sp_isr(p_hwfn);
488 }
489 return;
490 }
491
492 static int
qlnx_create_sp_taskqueues(qlnx_host_t * ha)493 qlnx_create_sp_taskqueues(qlnx_host_t *ha)
494 {
495 int i;
496 uint8_t tq_name[32];
497
498 for (i = 0; i < ha->cdev.num_hwfns; i++) {
499 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[i];
500
501 bzero(tq_name, sizeof (tq_name));
502 snprintf(tq_name, sizeof (tq_name), "ql_sp_tq_%d", i);
503
504 TASK_INIT(&ha->sp_task[i], 0, qlnx_sp_taskqueue, p_hwfn);
505
506 ha->sp_taskqueue[i] = taskqueue_create(tq_name, M_NOWAIT,
507 taskqueue_thread_enqueue, &ha->sp_taskqueue[i]);
508
509 if (ha->sp_taskqueue[i] == NULL)
510 return (-1);
511
512 taskqueue_start_threads(&ha->sp_taskqueue[i], 1, PI_NET, "%s",
513 tq_name);
514
515 QL_DPRINT1(ha, "%p\n", ha->sp_taskqueue[i]);
516 }
517
518 return (0);
519 }
520
521 static void
qlnx_destroy_sp_taskqueues(qlnx_host_t * ha)522 qlnx_destroy_sp_taskqueues(qlnx_host_t *ha)
523 {
524 int i;
525
526 for (i = 0; i < ha->cdev.num_hwfns; i++) {
527 if (ha->sp_taskqueue[i] != NULL) {
528 taskqueue_drain(ha->sp_taskqueue[i], &ha->sp_task[i]);
529 taskqueue_free(ha->sp_taskqueue[i]);
530 }
531 }
532 return;
533 }
534
535 static void
qlnx_fp_taskqueue(void * context,int pending)536 qlnx_fp_taskqueue(void *context, int pending)
537 {
538 struct qlnx_fastpath *fp;
539 qlnx_host_t *ha;
540 if_t ifp;
541
542 fp = context;
543
544 if (fp == NULL)
545 return;
546
547 ha = (qlnx_host_t *)fp->edev;
548
549 ifp = ha->ifp;
550
551 if(if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
552 if (!drbr_empty(ifp, fp->tx_br)) {
553 if(mtx_trylock(&fp->tx_mtx)) {
554 #ifdef QLNX_TRACE_PERF_DATA
555 tx_pkts = fp->tx_pkts_transmitted;
556 tx_compl = fp->tx_pkts_completed;
557 #endif
558
559 qlnx_transmit_locked(ifp, fp, NULL);
560
561 #ifdef QLNX_TRACE_PERF_DATA
562 fp->tx_pkts_trans_fp +=
563 (fp->tx_pkts_transmitted - tx_pkts);
564 fp->tx_pkts_compl_fp +=
565 (fp->tx_pkts_completed - tx_compl);
566 #endif
567 mtx_unlock(&fp->tx_mtx);
568 }
569 }
570 }
571
572 QL_DPRINT2(ha, "exit \n");
573 return;
574 }
575
576 static int
qlnx_create_fp_taskqueues(qlnx_host_t * ha)577 qlnx_create_fp_taskqueues(qlnx_host_t *ha)
578 {
579 int i;
580 uint8_t tq_name[32];
581 struct qlnx_fastpath *fp;
582
583 for (i = 0; i < ha->num_rss; i++) {
584 fp = &ha->fp_array[i];
585
586 bzero(tq_name, sizeof (tq_name));
587 snprintf(tq_name, sizeof (tq_name), "ql_fp_tq_%d", i);
588
589 TASK_INIT(&fp->fp_task, 0, qlnx_fp_taskqueue, fp);
590
591 fp->fp_taskqueue = taskqueue_create(tq_name, M_NOWAIT,
592 taskqueue_thread_enqueue,
593 &fp->fp_taskqueue);
594
595 if (fp->fp_taskqueue == NULL)
596 return (-1);
597
598 taskqueue_start_threads(&fp->fp_taskqueue, 1, PI_NET, "%s",
599 tq_name);
600
601 QL_DPRINT1(ha, "%p\n",fp->fp_taskqueue);
602 }
603
604 return (0);
605 }
606
607 static void
qlnx_destroy_fp_taskqueues(qlnx_host_t * ha)608 qlnx_destroy_fp_taskqueues(qlnx_host_t *ha)
609 {
610 int i;
611 struct qlnx_fastpath *fp;
612
613 for (i = 0; i < ha->num_rss; i++) {
614 fp = &ha->fp_array[i];
615
616 if (fp->fp_taskqueue != NULL) {
617 taskqueue_drain(fp->fp_taskqueue, &fp->fp_task);
618 taskqueue_free(fp->fp_taskqueue);
619 fp->fp_taskqueue = NULL;
620 }
621 }
622 return;
623 }
624
625 static void
qlnx_drain_fp_taskqueues(qlnx_host_t * ha)626 qlnx_drain_fp_taskqueues(qlnx_host_t *ha)
627 {
628 int i;
629 struct qlnx_fastpath *fp;
630
631 for (i = 0; i < ha->num_rss; i++) {
632 fp = &ha->fp_array[i];
633
634 if (fp->fp_taskqueue != NULL) {
635 QLNX_UNLOCK(ha);
636 taskqueue_drain(fp->fp_taskqueue, &fp->fp_task);
637 QLNX_LOCK(ha);
638 }
639 }
640 return;
641 }
642
643 static void
qlnx_get_params(qlnx_host_t * ha)644 qlnx_get_params(qlnx_host_t *ha)
645 {
646 if ((qlnxe_queue_count < 0) || (qlnxe_queue_count > QLNX_MAX_RSS)) {
647 device_printf(ha->pci_dev, "invalid queue_count value (%d)\n",
648 qlnxe_queue_count);
649 qlnxe_queue_count = 0;
650 }
651 return;
652 }
653
654 static void
qlnx_error_recovery_taskqueue(void * context,int pending)655 qlnx_error_recovery_taskqueue(void *context, int pending)
656 {
657 qlnx_host_t *ha;
658
659 ha = context;
660
661 QL_DPRINT2(ha, "enter\n");
662
663 QLNX_LOCK(ha);
664 qlnx_stop(ha);
665 QLNX_UNLOCK(ha);
666
667 #ifdef QLNX_ENABLE_IWARP
668 qlnx_rdma_dev_remove(ha);
669 #endif /* #ifdef QLNX_ENABLE_IWARP */
670
671 qlnx_slowpath_stop(ha);
672 qlnx_slowpath_start(ha);
673
674 #ifdef QLNX_ENABLE_IWARP
675 qlnx_rdma_dev_add(ha);
676 #endif /* #ifdef QLNX_ENABLE_IWARP */
677
678 qlnx_init(ha);
679
680 callout_reset(&ha->qlnx_callout, hz, qlnx_timer, ha);
681
682 QL_DPRINT2(ha, "exit\n");
683
684 return;
685 }
686
687 static int
qlnx_create_error_recovery_taskqueue(qlnx_host_t * ha)688 qlnx_create_error_recovery_taskqueue(qlnx_host_t *ha)
689 {
690 uint8_t tq_name[32];
691
692 bzero(tq_name, sizeof (tq_name));
693 snprintf(tq_name, sizeof (tq_name), "ql_err_tq");
694
695 TASK_INIT(&ha->err_task, 0, qlnx_error_recovery_taskqueue, ha);
696
697 ha->err_taskqueue = taskqueue_create(tq_name, M_NOWAIT,
698 taskqueue_thread_enqueue, &ha->err_taskqueue);
699
700 if (ha->err_taskqueue == NULL)
701 return (-1);
702
703 taskqueue_start_threads(&ha->err_taskqueue, 1, PI_NET, "%s", tq_name);
704
705 QL_DPRINT1(ha, "%p\n",ha->err_taskqueue);
706
707 return (0);
708 }
709
710 static void
qlnx_destroy_error_recovery_taskqueue(qlnx_host_t * ha)711 qlnx_destroy_error_recovery_taskqueue(qlnx_host_t *ha)
712 {
713 if (ha->err_taskqueue != NULL) {
714 taskqueue_drain(ha->err_taskqueue, &ha->err_task);
715 taskqueue_free(ha->err_taskqueue);
716 }
717
718 ha->err_taskqueue = NULL;
719
720 return;
721 }
722
723 /*
724 * Name: qlnx_pci_attach
725 * Function: attaches the device to the operating system
726 */
727 static int
qlnx_pci_attach(device_t dev)728 qlnx_pci_attach(device_t dev)
729 {
730 qlnx_host_t *ha = NULL;
731 uint32_t rsrc_len_reg __unused = 0;
732 uint32_t rsrc_len_dbells = 0;
733 uint32_t rsrc_len_msix __unused = 0;
734 int i;
735 uint32_t mfw_ver;
736 uint32_t num_sp_msix = 0;
737 uint32_t num_rdma_irqs = 0;
738
739 if ((ha = device_get_softc(dev)) == NULL) {
740 device_printf(dev, "cannot get softc\n");
741 return (ENOMEM);
742 }
743
744 memset(ha, 0, sizeof (qlnx_host_t));
745
746 ha->device_id = pci_get_device(dev);
747
748 if (qlnx_valid_device(ha) != 0) {
749 device_printf(dev, "device is not valid device\n");
750 return (ENXIO);
751 }
752 ha->pci_func = pci_get_function(dev);
753
754 ha->pci_dev = dev;
755
756 sx_init(&ha->hw_lock, "qlnx_hw_lock");
757
758 ha->flags.lock_init = 1;
759
760 pci_enable_busmaster(dev);
761
762 /*
763 * map the PCI BARs
764 */
765
766 ha->reg_rid = PCIR_BAR(0);
767 ha->pci_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &ha->reg_rid,
768 RF_ACTIVE);
769
770 if (ha->pci_reg == NULL) {
771 device_printf(dev, "unable to map BAR0\n");
772 goto qlnx_pci_attach_err;
773 }
774
775 rsrc_len_reg = (uint32_t) bus_get_resource_count(dev, SYS_RES_MEMORY,
776 ha->reg_rid);
777
778 ha->dbells_rid = PCIR_BAR(2);
779 rsrc_len_dbells = (uint32_t) bus_get_resource_count(dev,
780 SYS_RES_MEMORY,
781 ha->dbells_rid);
782 if (rsrc_len_dbells) {
783 ha->pci_dbells = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
784 &ha->dbells_rid, RF_ACTIVE);
785
786 if (ha->pci_dbells == NULL) {
787 device_printf(dev, "unable to map BAR1\n");
788 goto qlnx_pci_attach_err;
789 }
790 ha->dbells_phys_addr = (uint64_t)
791 bus_get_resource_start(dev, SYS_RES_MEMORY, ha->dbells_rid);
792
793 ha->dbells_size = rsrc_len_dbells;
794 } else {
795 if (qlnx_vf_device(ha) != 0) {
796 device_printf(dev, " BAR1 size is zero\n");
797 goto qlnx_pci_attach_err;
798 }
799 }
800
801 ha->msix_rid = PCIR_BAR(4);
802 ha->msix_bar = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
803 &ha->msix_rid, RF_ACTIVE);
804
805 if (ha->msix_bar == NULL) {
806 device_printf(dev, "unable to map BAR2\n");
807 goto qlnx_pci_attach_err;
808 }
809
810 rsrc_len_msix = (uint32_t) bus_get_resource_count(dev, SYS_RES_MEMORY,
811 ha->msix_rid);
812
813 ha->dbg_level = 0x0000;
814
815 QL_DPRINT1(ha, "\n\t\t\t"
816 "pci_dev = %p pci_reg = %p, reg_len = 0x%08x reg_rid = 0x%08x"
817 "\n\t\t\tdbells = %p, dbells_len = 0x%08x dbells_rid = 0x%08x"
818 "\n\t\t\tmsix = %p, msix_len = 0x%08x msix_rid = 0x%08x"
819 " msix_avail = 0x%x "
820 "\n\t\t\t[ncpus = %d]\n",
821 ha->pci_dev, ha->pci_reg, rsrc_len_reg,
822 ha->reg_rid, ha->pci_dbells, rsrc_len_dbells, ha->dbells_rid,
823 ha->msix_bar, rsrc_len_msix, ha->msix_rid, pci_msix_count(dev),
824 mp_ncpus);
825 /*
826 * allocate dma tags
827 */
828
829 if (qlnx_alloc_parent_dma_tag(ha))
830 goto qlnx_pci_attach_err;
831
832 if (qlnx_alloc_tx_dma_tag(ha))
833 goto qlnx_pci_attach_err;
834
835 if (qlnx_alloc_rx_dma_tag(ha))
836 goto qlnx_pci_attach_err;
837
838
839 if (qlnx_init_hw(ha) != 0)
840 goto qlnx_pci_attach_err;
841
842 ha->flags.hw_init = 1;
843
844 qlnx_get_params(ha);
845
846 if((pci_get_device(dev) == QLOGIC_PCI_DEVICE_ID_1644) &&
847 (qlnxe_queue_count == QLNX_DEFAULT_RSS)) {
848 qlnxe_queue_count = QLNX_MAX_RSS;
849 }
850
851 /*
852 * Allocate MSI-x vectors
853 */
854 if (qlnx_vf_device(ha) != 0) {
855 if (qlnxe_queue_count == 0)
856 ha->num_rss = QLNX_DEFAULT_RSS;
857 else
858 ha->num_rss = qlnxe_queue_count;
859
860 num_sp_msix = ha->cdev.num_hwfns;
861 } else {
862 uint8_t max_rxq;
863 uint8_t max_txq;
864
865 ecore_vf_get_num_rxqs(&ha->cdev.hwfns[0], &max_rxq);
866 ecore_vf_get_num_rxqs(&ha->cdev.hwfns[0], &max_txq);
867
868 if (max_rxq < max_txq)
869 ha->num_rss = max_rxq;
870 else
871 ha->num_rss = max_txq;
872
873 if (ha->num_rss > QLNX_MAX_VF_RSS)
874 ha->num_rss = QLNX_MAX_VF_RSS;
875
876 num_sp_msix = 0;
877 }
878
879 if (ha->num_rss > mp_ncpus)
880 ha->num_rss = mp_ncpus;
881
882 ha->num_tc = QLNX_MAX_TC;
883
884 ha->msix_count = pci_msix_count(dev);
885
886 #ifdef QLNX_ENABLE_IWARP
887
888 num_rdma_irqs = qlnx_rdma_get_num_irqs(ha);
889
890 #endif /* #ifdef QLNX_ENABLE_IWARP */
891
892 if (!ha->msix_count ||
893 (ha->msix_count < (num_sp_msix + 1 + num_rdma_irqs))) {
894 device_printf(dev, "%s: msix_count[%d] not enough\n", __func__,
895 ha->msix_count);
896 goto qlnx_pci_attach_err;
897 }
898
899 if (ha->msix_count > (ha->num_rss + num_sp_msix + num_rdma_irqs))
900 ha->msix_count = ha->num_rss + num_sp_msix + num_rdma_irqs;
901 else
902 ha->num_rss = ha->msix_count - (num_sp_msix + num_rdma_irqs);
903
904 QL_DPRINT1(ha, "\n\t\t\t"
905 "pci_reg = %p, reg_len = 0x%08x reg_rid = 0x%08x"
906 "\n\t\t\tdbells = %p, dbells_len = 0x%08x dbells_rid = 0x%08x"
907 "\n\t\t\tmsix = %p, msix_len = 0x%08x msix_rid = 0x%08x"
908 " msix_avail = 0x%x msix_alloc = 0x%x"
909 "\n\t\t\t[ncpus = %d][num_rss = 0x%x] [num_tc = 0x%x]\n",
910 ha->pci_reg, rsrc_len_reg,
911 ha->reg_rid, ha->pci_dbells, rsrc_len_dbells, ha->dbells_rid,
912 ha->msix_bar, rsrc_len_msix, ha->msix_rid, pci_msix_count(dev),
913 ha->msix_count, mp_ncpus, ha->num_rss, ha->num_tc);
914
915 if (pci_alloc_msix(dev, &ha->msix_count)) {
916 device_printf(dev, "%s: pci_alloc_msix[%d] failed\n", __func__,
917 ha->msix_count);
918 ha->msix_count = 0;
919 goto qlnx_pci_attach_err;
920 }
921
922 /*
923 * Initialize slow path interrupt and task queue
924 */
925
926 if (num_sp_msix) {
927 if (qlnx_create_sp_taskqueues(ha) != 0)
928 goto qlnx_pci_attach_err;
929
930 for (i = 0; i < ha->cdev.num_hwfns; i++) {
931 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[i];
932
933 ha->sp_irq_rid[i] = i + 1;
934 ha->sp_irq[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ,
935 &ha->sp_irq_rid[i],
936 (RF_ACTIVE | RF_SHAREABLE));
937 if (ha->sp_irq[i] == NULL) {
938 device_printf(dev,
939 "could not allocate mbx interrupt\n");
940 goto qlnx_pci_attach_err;
941 }
942
943 if (bus_setup_intr(dev, ha->sp_irq[i],
944 (INTR_TYPE_NET | INTR_MPSAFE), NULL,
945 qlnx_sp_intr, p_hwfn, &ha->sp_handle[i])) {
946 device_printf(dev,
947 "could not setup slow path interrupt\n");
948 goto qlnx_pci_attach_err;
949 }
950
951 QL_DPRINT1(ha, "p_hwfn [%p] sp_irq_rid %d"
952 " sp_irq %p sp_handle %p\n", p_hwfn,
953 ha->sp_irq_rid[i], ha->sp_irq[i], ha->sp_handle[i]);
954 }
955 }
956
957 /*
958 * initialize fast path interrupt
959 */
960 if (qlnx_create_fp_taskqueues(ha) != 0)
961 goto qlnx_pci_attach_err;
962
963 for (i = 0; i < ha->num_rss; i++) {
964 ha->irq_vec[i].rss_idx = i;
965 ha->irq_vec[i].ha = ha;
966 ha->irq_vec[i].irq_rid = (1 + num_sp_msix) + i;
967
968 ha->irq_vec[i].irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
969 &ha->irq_vec[i].irq_rid,
970 (RF_ACTIVE | RF_SHAREABLE));
971
972 if (ha->irq_vec[i].irq == NULL) {
973 device_printf(dev,
974 "could not allocate interrupt[%d] irq_rid = %d\n",
975 i, ha->irq_vec[i].irq_rid);
976 goto qlnx_pci_attach_err;
977 }
978
979 if (qlnx_alloc_tx_br(ha, &ha->fp_array[i])) {
980 device_printf(dev, "could not allocate tx_br[%d]\n", i);
981 goto qlnx_pci_attach_err;
982 }
983 }
984
985 if (qlnx_vf_device(ha) != 0) {
986 callout_init(&ha->qlnx_callout, 1);
987 ha->flags.callout_init = 1;
988
989 for (i = 0; i < ha->cdev.num_hwfns; i++) {
990 if (qlnx_grc_dumpsize(ha, &ha->grcdump_size[i], i) != 0)
991 goto qlnx_pci_attach_err;
992 if (ha->grcdump_size[i] == 0)
993 goto qlnx_pci_attach_err;
994
995 ha->grcdump_size[i] = ha->grcdump_size[i] << 2;
996 QL_DPRINT1(ha, "grcdump_size[%d] = 0x%08x\n",
997 i, ha->grcdump_size[i]);
998
999 ha->grcdump[i] = qlnx_zalloc(ha->grcdump_size[i]);
1000 if (ha->grcdump[i] == NULL) {
1001 device_printf(dev, "grcdump alloc[%d] failed\n", i);
1002 goto qlnx_pci_attach_err;
1003 }
1004
1005 if (qlnx_idle_chk_size(ha, &ha->idle_chk_size[i], i) != 0)
1006 goto qlnx_pci_attach_err;
1007 if (ha->idle_chk_size[i] == 0)
1008 goto qlnx_pci_attach_err;
1009
1010 ha->idle_chk_size[i] = ha->idle_chk_size[i] << 2;
1011 QL_DPRINT1(ha, "idle_chk_size[%d] = 0x%08x\n",
1012 i, ha->idle_chk_size[i]);
1013
1014 ha->idle_chk[i] = qlnx_zalloc(ha->idle_chk_size[i]);
1015
1016 if (ha->idle_chk[i] == NULL) {
1017 device_printf(dev, "idle_chk alloc failed\n");
1018 goto qlnx_pci_attach_err;
1019 }
1020 }
1021
1022 if (qlnx_create_error_recovery_taskqueue(ha) != 0)
1023 goto qlnx_pci_attach_err;
1024 }
1025
1026 if (qlnx_slowpath_start(ha) != 0)
1027 goto qlnx_pci_attach_err;
1028 else
1029 ha->flags.slowpath_start = 1;
1030
1031 if (qlnx_vf_device(ha) != 0) {
1032 if (qlnx_get_flash_size(ha, &ha->flash_size) != 0) {
1033 qlnx_mdelay(__func__, 1000);
1034 qlnx_trigger_dump(ha);
1035
1036 goto qlnx_pci_attach_err0;
1037 }
1038
1039 if (qlnx_get_mfw_version(ha, &mfw_ver) != 0) {
1040 qlnx_mdelay(__func__, 1000);
1041 qlnx_trigger_dump(ha);
1042
1043 goto qlnx_pci_attach_err0;
1044 }
1045 } else {
1046 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[0];
1047 ecore_mcp_get_mfw_ver(p_hwfn, NULL, &mfw_ver, NULL);
1048 }
1049
1050 snprintf(ha->mfw_ver, sizeof(ha->mfw_ver), "%d.%d.%d.%d",
1051 ((mfw_ver >> 24) & 0xFF), ((mfw_ver >> 16) & 0xFF),
1052 ((mfw_ver >> 8) & 0xFF), (mfw_ver & 0xFF));
1053 snprintf(ha->stormfw_ver, sizeof(ha->stormfw_ver), "%d.%d.%d.%d",
1054 FW_MAJOR_VERSION, FW_MINOR_VERSION, FW_REVISION_VERSION,
1055 FW_ENGINEERING_VERSION);
1056
1057 QL_DPRINT1(ha, "STORM_FW version %s MFW version %s\n",
1058 ha->stormfw_ver, ha->mfw_ver);
1059
1060 qlnx_init_ifnet(dev, ha);
1061
1062 /*
1063 * add sysctls
1064 */
1065 qlnx_add_sysctls(ha);
1066
1067 qlnx_pci_attach_err0:
1068 /*
1069 * create ioctl device interface
1070 */
1071 if (qlnx_vf_device(ha) != 0) {
1072 if (qlnx_make_cdev(ha)) {
1073 device_printf(dev, "%s: ql_make_cdev failed\n", __func__);
1074 goto qlnx_pci_attach_err;
1075 }
1076
1077 #ifdef QLNX_ENABLE_IWARP
1078 qlnx_rdma_dev_add(ha);
1079 #endif /* #ifdef QLNX_ENABLE_IWARP */
1080 }
1081
1082 #ifndef QLNX_VF
1083 #ifdef CONFIG_ECORE_SRIOV
1084
1085 if (qlnx_vf_device(ha) != 0)
1086 qlnx_initialize_sriov(ha);
1087
1088 #endif /* #ifdef CONFIG_ECORE_SRIOV */
1089 #endif /* #ifdef QLNX_VF */
1090
1091 QL_DPRINT2(ha, "success\n");
1092
1093 return (0);
1094
1095 qlnx_pci_attach_err:
1096
1097 qlnx_release(ha);
1098
1099 return (ENXIO);
1100 }
1101
1102 /*
1103 * Name: qlnx_pci_detach
1104 * Function: Unhooks the device from the operating system
1105 */
1106 static int
qlnx_pci_detach(device_t dev)1107 qlnx_pci_detach(device_t dev)
1108 {
1109 qlnx_host_t *ha = NULL;
1110
1111 if ((ha = device_get_softc(dev)) == NULL) {
1112 device_printf(dev, "%s: cannot get softc\n", __func__);
1113 return (ENOMEM);
1114 }
1115
1116 if (qlnx_vf_device(ha) != 0) {
1117 #ifdef CONFIG_ECORE_SRIOV
1118 int ret;
1119
1120 ret = pci_iov_detach(dev);
1121 if (ret) {
1122 device_printf(dev, "%s: SRIOV in use\n", __func__);
1123 return (ret);
1124 }
1125
1126 #endif /* #ifdef CONFIG_ECORE_SRIOV */
1127
1128 #ifdef QLNX_ENABLE_IWARP
1129 if (qlnx_rdma_dev_remove(ha) != 0)
1130 return (EBUSY);
1131 #endif /* #ifdef QLNX_ENABLE_IWARP */
1132 }
1133
1134 QLNX_LOCK(ha);
1135 qlnx_stop(ha);
1136 QLNX_UNLOCK(ha);
1137
1138 qlnx_release(ha);
1139
1140 return (0);
1141 }
1142
1143 #ifdef QLNX_ENABLE_IWARP
1144
1145 static uint8_t
qlnx_get_personality(uint8_t pci_func)1146 qlnx_get_personality(uint8_t pci_func)
1147 {
1148 uint8_t personality;
1149
1150 personality = (qlnxe_rdma_configuration >>
1151 (pci_func * QLNX_PERSONALITY_BITS_PER_FUNC)) &
1152 QLNX_PERSONALIY_MASK;
1153 return (personality);
1154 }
1155
1156 static void
qlnx_set_personality(qlnx_host_t * ha)1157 qlnx_set_personality(qlnx_host_t *ha)
1158 {
1159 uint8_t personality;
1160
1161 personality = qlnx_get_personality(ha->pci_func);
1162
1163 switch (personality) {
1164 case QLNX_PERSONALITY_DEFAULT:
1165 device_printf(ha->pci_dev, "%s: DEFAULT\n",
1166 __func__);
1167 ha->personality = ECORE_PCI_DEFAULT;
1168 break;
1169
1170 case QLNX_PERSONALITY_ETH_ONLY:
1171 device_printf(ha->pci_dev, "%s: ETH_ONLY\n",
1172 __func__);
1173 ha->personality = ECORE_PCI_ETH;
1174 break;
1175
1176 case QLNX_PERSONALITY_ETH_IWARP:
1177 device_printf(ha->pci_dev, "%s: ETH_IWARP\n",
1178 __func__);
1179 ha->personality = ECORE_PCI_ETH_IWARP;
1180 break;
1181
1182 case QLNX_PERSONALITY_ETH_ROCE:
1183 device_printf(ha->pci_dev, "%s: ETH_ROCE\n",
1184 __func__);
1185 ha->personality = ECORE_PCI_ETH_ROCE;
1186 break;
1187 }
1188
1189 return;
1190 }
1191
1192 #endif /* #ifdef QLNX_ENABLE_IWARP */
1193
1194 static int
qlnx_init_hw(qlnx_host_t * ha)1195 qlnx_init_hw(qlnx_host_t *ha)
1196 {
1197 int rval = 0;
1198 struct ecore_hw_prepare_params params;
1199
1200 ha->cdev.ha = ha;
1201 ecore_init_struct(&ha->cdev);
1202
1203 /* ha->dp_module = ECORE_MSG_PROBE |
1204 ECORE_MSG_INTR |
1205 ECORE_MSG_SP |
1206 ECORE_MSG_LINK |
1207 ECORE_MSG_SPQ |
1208 ECORE_MSG_RDMA;
1209 ha->dp_level = ECORE_LEVEL_VERBOSE;*/
1210 //ha->dp_module = ECORE_MSG_RDMA | ECORE_MSG_INTR | ECORE_MSG_LL2;
1211 ha->dp_level = ECORE_LEVEL_NOTICE;
1212 //ha->dp_level = ECORE_LEVEL_VERBOSE;
1213
1214 ecore_init_dp(&ha->cdev, ha->dp_module, ha->dp_level, ha->pci_dev);
1215
1216 ha->cdev.regview = ha->pci_reg;
1217
1218 ha->personality = ECORE_PCI_DEFAULT;
1219
1220 if (qlnx_vf_device(ha) == 0) {
1221 ha->cdev.b_is_vf = true;
1222
1223 if (ha->pci_dbells != NULL) {
1224 ha->cdev.doorbells = ha->pci_dbells;
1225 ha->cdev.db_phys_addr = ha->dbells_phys_addr;
1226 ha->cdev.db_size = ha->dbells_size;
1227 } else {
1228 ha->pci_dbells = ha->pci_reg;
1229 }
1230 } else {
1231 ha->cdev.doorbells = ha->pci_dbells;
1232 ha->cdev.db_phys_addr = ha->dbells_phys_addr;
1233 ha->cdev.db_size = ha->dbells_size;
1234
1235 #ifdef QLNX_ENABLE_IWARP
1236
1237 if (qlnx_rdma_supported(ha) == 0)
1238 qlnx_set_personality(ha);
1239
1240 #endif /* #ifdef QLNX_ENABLE_IWARP */
1241 }
1242 QL_DPRINT2(ha, "%s: %s\n", __func__,
1243 (ha->personality == ECORE_PCI_ETH_IWARP ? "iwarp": "ethernet"));
1244
1245 bzero(¶ms, sizeof (struct ecore_hw_prepare_params));
1246
1247 params.personality = ha->personality;
1248
1249 params.drv_resc_alloc = false;
1250 params.chk_reg_fifo = false;
1251 params.initiate_pf_flr = true;
1252 params.epoch = 0;
1253
1254 ecore_hw_prepare(&ha->cdev, ¶ms);
1255
1256 qlnx_set_id(&ha->cdev, qlnx_name_str, qlnx_ver_str);
1257
1258 QL_DPRINT1(ha, "ha = %p cdev = %p p_hwfn = %p\n",
1259 ha, &ha->cdev, &ha->cdev.hwfns[0]);
1260
1261 return (rval);
1262 }
1263
1264 static void
qlnx_release(qlnx_host_t * ha)1265 qlnx_release(qlnx_host_t *ha)
1266 {
1267 device_t dev;
1268 int i;
1269
1270 dev = ha->pci_dev;
1271
1272 QL_DPRINT2(ha, "enter\n");
1273
1274 for (i = 0; i < QLNX_MAX_HW_FUNCS; i++) {
1275 if (ha->idle_chk[i] != NULL) {
1276 free(ha->idle_chk[i], M_QLNXBUF);
1277 ha->idle_chk[i] = NULL;
1278 }
1279
1280 if (ha->grcdump[i] != NULL) {
1281 free(ha->grcdump[i], M_QLNXBUF);
1282 ha->grcdump[i] = NULL;
1283 }
1284 }
1285
1286 if (ha->flags.callout_init)
1287 callout_drain(&ha->qlnx_callout);
1288
1289 if (ha->flags.slowpath_start) {
1290 qlnx_slowpath_stop(ha);
1291 }
1292
1293 if (ha->flags.hw_init)
1294 ecore_hw_remove(&ha->cdev);
1295
1296 qlnx_del_cdev(ha);
1297
1298 if (ha->ifp != NULL)
1299 ether_ifdetach(ha->ifp);
1300
1301 qlnx_free_tx_dma_tag(ha);
1302
1303 qlnx_free_rx_dma_tag(ha);
1304
1305 qlnx_free_parent_dma_tag(ha);
1306
1307 if (qlnx_vf_device(ha) != 0) {
1308 qlnx_destroy_error_recovery_taskqueue(ha);
1309 }
1310
1311 for (i = 0; i < ha->num_rss; i++) {
1312 struct qlnx_fastpath *fp = &ha->fp_array[i];
1313
1314 if (ha->irq_vec[i].handle) {
1315 (void)bus_teardown_intr(dev, ha->irq_vec[i].irq,
1316 ha->irq_vec[i].handle);
1317 }
1318
1319 if (ha->irq_vec[i].irq) {
1320 (void)bus_release_resource(dev, SYS_RES_IRQ,
1321 ha->irq_vec[i].irq_rid,
1322 ha->irq_vec[i].irq);
1323 }
1324
1325 qlnx_free_tx_br(ha, fp);
1326 }
1327 qlnx_destroy_fp_taskqueues(ha);
1328
1329 for (i = 0; i < ha->cdev.num_hwfns; i++) {
1330 if (ha->sp_handle[i])
1331 (void)bus_teardown_intr(dev, ha->sp_irq[i],
1332 ha->sp_handle[i]);
1333
1334 if (ha->sp_irq[i])
1335 (void) bus_release_resource(dev, SYS_RES_IRQ,
1336 ha->sp_irq_rid[i], ha->sp_irq[i]);
1337 }
1338
1339 qlnx_destroy_sp_taskqueues(ha);
1340
1341 if (ha->msix_count)
1342 pci_release_msi(dev);
1343
1344 if (ha->flags.lock_init) {
1345 sx_destroy(&ha->hw_lock);
1346 }
1347
1348 if (ha->pci_reg)
1349 (void) bus_release_resource(dev, SYS_RES_MEMORY, ha->reg_rid,
1350 ha->pci_reg);
1351
1352 if (ha->dbells_size && ha->pci_dbells)
1353 (void) bus_release_resource(dev, SYS_RES_MEMORY, ha->dbells_rid,
1354 ha->pci_dbells);
1355
1356 if (ha->msix_bar)
1357 (void) bus_release_resource(dev, SYS_RES_MEMORY, ha->msix_rid,
1358 ha->msix_bar);
1359
1360 QL_DPRINT2(ha, "exit\n");
1361 return;
1362 }
1363
1364 static void
qlnx_trigger_dump(qlnx_host_t * ha)1365 qlnx_trigger_dump(qlnx_host_t *ha)
1366 {
1367 int i;
1368
1369 if (ha->ifp != NULL)
1370 if_setdrvflagbits(ha->ifp, 0, (IFF_DRV_OACTIVE | IFF_DRV_RUNNING));
1371
1372 QL_DPRINT2(ha, "enter\n");
1373
1374 if (qlnx_vf_device(ha) == 0)
1375 return;
1376
1377 ha->error_recovery = 1;
1378
1379 for (i = 0; i < ha->cdev.num_hwfns; i++) {
1380 qlnx_grc_dump(ha, &ha->grcdump_dwords[i], i);
1381 qlnx_idle_chk(ha, &ha->idle_chk_dwords[i], i);
1382 }
1383
1384 QL_DPRINT2(ha, "exit\n");
1385
1386 return;
1387 }
1388
1389 static int
qlnx_trigger_dump_sysctl(SYSCTL_HANDLER_ARGS)1390 qlnx_trigger_dump_sysctl(SYSCTL_HANDLER_ARGS)
1391 {
1392 int err, ret = 0;
1393 qlnx_host_t *ha;
1394
1395 err = sysctl_handle_int(oidp, &ret, 0, req);
1396
1397 if (err || !req->newptr)
1398 return (err);
1399
1400 if (ret == 1) {
1401 ha = (qlnx_host_t *)arg1;
1402 qlnx_trigger_dump(ha);
1403 }
1404 return (err);
1405 }
1406
1407 static int
qlnx_set_tx_coalesce(SYSCTL_HANDLER_ARGS)1408 qlnx_set_tx_coalesce(SYSCTL_HANDLER_ARGS)
1409 {
1410 int err, i, ret = 0, usecs = 0;
1411 qlnx_host_t *ha;
1412 struct ecore_hwfn *p_hwfn;
1413 struct qlnx_fastpath *fp;
1414
1415 err = sysctl_handle_int(oidp, &usecs, 0, req);
1416
1417 if (err || !req->newptr || !usecs || (usecs > 255))
1418 return (err);
1419
1420 ha = (qlnx_host_t *)arg1;
1421
1422 if (qlnx_vf_device(ha) == 0)
1423 return (-1);
1424
1425 for (i = 0; i < ha->num_rss; i++) {
1426 p_hwfn = &ha->cdev.hwfns[(i % ha->cdev.num_hwfns)];
1427
1428 fp = &ha->fp_array[i];
1429
1430 if (fp->txq[0]->handle != NULL) {
1431 ret = ecore_set_queue_coalesce(p_hwfn, 0,
1432 (uint16_t)usecs, fp->txq[0]->handle);
1433 }
1434 }
1435
1436 if (!ret)
1437 ha->tx_coalesce_usecs = (uint8_t)usecs;
1438
1439 return (err);
1440 }
1441
1442 static int
qlnx_set_rx_coalesce(SYSCTL_HANDLER_ARGS)1443 qlnx_set_rx_coalesce(SYSCTL_HANDLER_ARGS)
1444 {
1445 int err, i, ret = 0, usecs = 0;
1446 qlnx_host_t *ha;
1447 struct ecore_hwfn *p_hwfn;
1448 struct qlnx_fastpath *fp;
1449
1450 err = sysctl_handle_int(oidp, &usecs, 0, req);
1451
1452 if (err || !req->newptr || !usecs || (usecs > 255))
1453 return (err);
1454
1455 ha = (qlnx_host_t *)arg1;
1456
1457 if (qlnx_vf_device(ha) == 0)
1458 return (-1);
1459
1460 for (i = 0; i < ha->num_rss; i++) {
1461 p_hwfn = &ha->cdev.hwfns[(i % ha->cdev.num_hwfns)];
1462
1463 fp = &ha->fp_array[i];
1464
1465 if (fp->rxq->handle != NULL) {
1466 ret = ecore_set_queue_coalesce(p_hwfn, (uint16_t)usecs,
1467 0, fp->rxq->handle);
1468 }
1469 }
1470
1471 if (!ret)
1472 ha->rx_coalesce_usecs = (uint8_t)usecs;
1473
1474 return (err);
1475 }
1476
1477 static void
qlnx_add_sp_stats_sysctls(qlnx_host_t * ha)1478 qlnx_add_sp_stats_sysctls(qlnx_host_t *ha)
1479 {
1480 struct sysctl_ctx_list *ctx;
1481 struct sysctl_oid_list *children;
1482 struct sysctl_oid *ctx_oid;
1483
1484 ctx = device_get_sysctl_ctx(ha->pci_dev);
1485 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
1486
1487 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "spstat",
1488 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "spstat");
1489 children = SYSCTL_CHILDREN(ctx_oid);
1490
1491 SYSCTL_ADD_QUAD(ctx, children,
1492 OID_AUTO, "sp_interrupts",
1493 CTLFLAG_RD, &ha->sp_interrupts,
1494 "No. of slowpath interrupts");
1495
1496 return;
1497 }
1498
1499 static void
qlnx_add_fp_stats_sysctls(qlnx_host_t * ha)1500 qlnx_add_fp_stats_sysctls(qlnx_host_t *ha)
1501 {
1502 struct sysctl_ctx_list *ctx;
1503 struct sysctl_oid_list *children;
1504 struct sysctl_oid_list *node_children;
1505 struct sysctl_oid *ctx_oid;
1506 int i, j;
1507 uint8_t name_str[16];
1508
1509 ctx = device_get_sysctl_ctx(ha->pci_dev);
1510 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
1511
1512 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fpstat",
1513 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "fpstat");
1514 children = SYSCTL_CHILDREN(ctx_oid);
1515
1516 for (i = 0; i < ha->num_rss; i++) {
1517 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1518 snprintf(name_str, sizeof(name_str), "%d", i);
1519
1520 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str,
1521 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, name_str);
1522 node_children = SYSCTL_CHILDREN(ctx_oid);
1523
1524 /* Tx Related */
1525
1526 SYSCTL_ADD_QUAD(ctx, node_children,
1527 OID_AUTO, "tx_pkts_processed",
1528 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_processed,
1529 "No. of packets processed for transmission");
1530
1531 SYSCTL_ADD_QUAD(ctx, node_children,
1532 OID_AUTO, "tx_pkts_freed",
1533 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_freed,
1534 "No. of freed packets");
1535
1536 SYSCTL_ADD_QUAD(ctx, node_children,
1537 OID_AUTO, "tx_pkts_transmitted",
1538 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_transmitted,
1539 "No. of transmitted packets");
1540
1541 SYSCTL_ADD_QUAD(ctx, node_children,
1542 OID_AUTO, "tx_pkts_completed",
1543 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_completed,
1544 "No. of transmit completions");
1545
1546 SYSCTL_ADD_QUAD(ctx, node_children,
1547 OID_AUTO, "tx_non_tso_pkts",
1548 CTLFLAG_RD, &ha->fp_array[i].tx_non_tso_pkts,
1549 "No. of non LSO transmited packets");
1550
1551 #ifdef QLNX_TRACE_PERF_DATA
1552
1553 SYSCTL_ADD_QUAD(ctx, node_children,
1554 OID_AUTO, "tx_pkts_trans_ctx",
1555 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_trans_ctx,
1556 "No. of transmitted packets in transmit context");
1557
1558 SYSCTL_ADD_QUAD(ctx, node_children,
1559 OID_AUTO, "tx_pkts_compl_ctx",
1560 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_compl_ctx,
1561 "No. of transmit completions in transmit context");
1562
1563 SYSCTL_ADD_QUAD(ctx, node_children,
1564 OID_AUTO, "tx_pkts_trans_fp",
1565 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_trans_fp,
1566 "No. of transmitted packets in taskqueue");
1567
1568 SYSCTL_ADD_QUAD(ctx, node_children,
1569 OID_AUTO, "tx_pkts_compl_fp",
1570 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_compl_fp,
1571 "No. of transmit completions in taskqueue");
1572
1573 SYSCTL_ADD_QUAD(ctx, node_children,
1574 OID_AUTO, "tx_pkts_compl_intr",
1575 CTLFLAG_RD, &ha->fp_array[i].tx_pkts_compl_intr,
1576 "No. of transmit completions in interrupt ctx");
1577 #endif
1578
1579 SYSCTL_ADD_QUAD(ctx, node_children,
1580 OID_AUTO, "tx_tso_pkts",
1581 CTLFLAG_RD, &ha->fp_array[i].tx_tso_pkts,
1582 "No. of LSO transmited packets");
1583
1584 SYSCTL_ADD_QUAD(ctx, node_children,
1585 OID_AUTO, "tx_lso_wnd_min_len",
1586 CTLFLAG_RD, &ha->fp_array[i].tx_lso_wnd_min_len,
1587 "tx_lso_wnd_min_len");
1588
1589 SYSCTL_ADD_QUAD(ctx, node_children,
1590 OID_AUTO, "tx_defrag",
1591 CTLFLAG_RD, &ha->fp_array[i].tx_defrag,
1592 "tx_defrag");
1593
1594 SYSCTL_ADD_QUAD(ctx, node_children,
1595 OID_AUTO, "tx_nsegs_gt_elem_left",
1596 CTLFLAG_RD, &ha->fp_array[i].tx_nsegs_gt_elem_left,
1597 "tx_nsegs_gt_elem_left");
1598
1599 SYSCTL_ADD_UINT(ctx, node_children,
1600 OID_AUTO, "tx_tso_max_nsegs",
1601 CTLFLAG_RD, &ha->fp_array[i].tx_tso_max_nsegs,
1602 ha->fp_array[i].tx_tso_max_nsegs, "tx_tso_max_nsegs");
1603
1604 SYSCTL_ADD_UINT(ctx, node_children,
1605 OID_AUTO, "tx_tso_min_nsegs",
1606 CTLFLAG_RD, &ha->fp_array[i].tx_tso_min_nsegs,
1607 ha->fp_array[i].tx_tso_min_nsegs, "tx_tso_min_nsegs");
1608
1609 SYSCTL_ADD_UINT(ctx, node_children,
1610 OID_AUTO, "tx_tso_max_pkt_len",
1611 CTLFLAG_RD, &ha->fp_array[i].tx_tso_max_pkt_len,
1612 ha->fp_array[i].tx_tso_max_pkt_len,
1613 "tx_tso_max_pkt_len");
1614
1615 SYSCTL_ADD_UINT(ctx, node_children,
1616 OID_AUTO, "tx_tso_min_pkt_len",
1617 CTLFLAG_RD, &ha->fp_array[i].tx_tso_min_pkt_len,
1618 ha->fp_array[i].tx_tso_min_pkt_len,
1619 "tx_tso_min_pkt_len");
1620
1621 for (j = 0; j < QLNX_FP_MAX_SEGS; j++) {
1622 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1623 snprintf(name_str, sizeof(name_str),
1624 "tx_pkts_nseg_%02d", (j+1));
1625
1626 SYSCTL_ADD_QUAD(ctx, node_children,
1627 OID_AUTO, name_str, CTLFLAG_RD,
1628 &ha->fp_array[i].tx_pkts[j], name_str);
1629 }
1630
1631 #ifdef QLNX_TRACE_PERF_DATA
1632 for (j = 0; j < 18; j++) {
1633 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1634 snprintf(name_str, sizeof(name_str),
1635 "tx_pkts_hist_%02d", (j+1));
1636
1637 SYSCTL_ADD_QUAD(ctx, node_children,
1638 OID_AUTO, name_str, CTLFLAG_RD,
1639 &ha->fp_array[i].tx_pkts_hist[j], name_str);
1640 }
1641 for (j = 0; j < 5; j++) {
1642 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1643 snprintf(name_str, sizeof(name_str),
1644 "tx_comInt_%02d", (j+1));
1645
1646 SYSCTL_ADD_QUAD(ctx, node_children,
1647 OID_AUTO, name_str, CTLFLAG_RD,
1648 &ha->fp_array[i].tx_comInt[j], name_str);
1649 }
1650 for (j = 0; j < 18; j++) {
1651 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
1652 snprintf(name_str, sizeof(name_str),
1653 "tx_pkts_q_%02d", (j+1));
1654
1655 SYSCTL_ADD_QUAD(ctx, node_children,
1656 OID_AUTO, name_str, CTLFLAG_RD,
1657 &ha->fp_array[i].tx_pkts_q[j], name_str);
1658 }
1659 #endif
1660
1661 SYSCTL_ADD_QUAD(ctx, node_children,
1662 OID_AUTO, "err_tx_nsegs_gt_elem_left",
1663 CTLFLAG_RD, &ha->fp_array[i].err_tx_nsegs_gt_elem_left,
1664 "err_tx_nsegs_gt_elem_left");
1665
1666 SYSCTL_ADD_QUAD(ctx, node_children,
1667 OID_AUTO, "err_tx_dmamap_create",
1668 CTLFLAG_RD, &ha->fp_array[i].err_tx_dmamap_create,
1669 "err_tx_dmamap_create");
1670
1671 SYSCTL_ADD_QUAD(ctx, node_children,
1672 OID_AUTO, "err_tx_defrag_dmamap_load",
1673 CTLFLAG_RD, &ha->fp_array[i].err_tx_defrag_dmamap_load,
1674 "err_tx_defrag_dmamap_load");
1675
1676 SYSCTL_ADD_QUAD(ctx, node_children,
1677 OID_AUTO, "err_tx_non_tso_max_seg",
1678 CTLFLAG_RD, &ha->fp_array[i].err_tx_non_tso_max_seg,
1679 "err_tx_non_tso_max_seg");
1680
1681 SYSCTL_ADD_QUAD(ctx, node_children,
1682 OID_AUTO, "err_tx_dmamap_load",
1683 CTLFLAG_RD, &ha->fp_array[i].err_tx_dmamap_load,
1684 "err_tx_dmamap_load");
1685
1686 SYSCTL_ADD_QUAD(ctx, node_children,
1687 OID_AUTO, "err_tx_defrag",
1688 CTLFLAG_RD, &ha->fp_array[i].err_tx_defrag,
1689 "err_tx_defrag");
1690
1691 SYSCTL_ADD_QUAD(ctx, node_children,
1692 OID_AUTO, "err_tx_free_pkt_null",
1693 CTLFLAG_RD, &ha->fp_array[i].err_tx_free_pkt_null,
1694 "err_tx_free_pkt_null");
1695
1696 SYSCTL_ADD_QUAD(ctx, node_children,
1697 OID_AUTO, "err_tx_cons_idx_conflict",
1698 CTLFLAG_RD, &ha->fp_array[i].err_tx_cons_idx_conflict,
1699 "err_tx_cons_idx_conflict");
1700
1701 SYSCTL_ADD_QUAD(ctx, node_children,
1702 OID_AUTO, "lro_cnt_64",
1703 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_64,
1704 "lro_cnt_64");
1705
1706 SYSCTL_ADD_QUAD(ctx, node_children,
1707 OID_AUTO, "lro_cnt_128",
1708 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_128,
1709 "lro_cnt_128");
1710
1711 SYSCTL_ADD_QUAD(ctx, node_children,
1712 OID_AUTO, "lro_cnt_256",
1713 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_256,
1714 "lro_cnt_256");
1715
1716 SYSCTL_ADD_QUAD(ctx, node_children,
1717 OID_AUTO, "lro_cnt_512",
1718 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_512,
1719 "lro_cnt_512");
1720
1721 SYSCTL_ADD_QUAD(ctx, node_children,
1722 OID_AUTO, "lro_cnt_1024",
1723 CTLFLAG_RD, &ha->fp_array[i].lro_cnt_1024,
1724 "lro_cnt_1024");
1725
1726 /* Rx Related */
1727
1728 SYSCTL_ADD_QUAD(ctx, node_children,
1729 OID_AUTO, "rx_pkts",
1730 CTLFLAG_RD, &ha->fp_array[i].rx_pkts,
1731 "No. of received packets");
1732
1733 SYSCTL_ADD_QUAD(ctx, node_children,
1734 OID_AUTO, "tpa_start",
1735 CTLFLAG_RD, &ha->fp_array[i].tpa_start,
1736 "No. of tpa_start packets");
1737
1738 SYSCTL_ADD_QUAD(ctx, node_children,
1739 OID_AUTO, "tpa_cont",
1740 CTLFLAG_RD, &ha->fp_array[i].tpa_cont,
1741 "No. of tpa_cont packets");
1742
1743 SYSCTL_ADD_QUAD(ctx, node_children,
1744 OID_AUTO, "tpa_end",
1745 CTLFLAG_RD, &ha->fp_array[i].tpa_end,
1746 "No. of tpa_end packets");
1747
1748 SYSCTL_ADD_QUAD(ctx, node_children,
1749 OID_AUTO, "err_m_getcl",
1750 CTLFLAG_RD, &ha->fp_array[i].err_m_getcl,
1751 "err_m_getcl");
1752
1753 SYSCTL_ADD_QUAD(ctx, node_children,
1754 OID_AUTO, "err_m_getjcl",
1755 CTLFLAG_RD, &ha->fp_array[i].err_m_getjcl,
1756 "err_m_getjcl");
1757
1758 SYSCTL_ADD_QUAD(ctx, node_children,
1759 OID_AUTO, "err_rx_hw_errors",
1760 CTLFLAG_RD, &ha->fp_array[i].err_rx_hw_errors,
1761 "err_rx_hw_errors");
1762
1763 SYSCTL_ADD_QUAD(ctx, node_children,
1764 OID_AUTO, "err_rx_alloc_errors",
1765 CTLFLAG_RD, &ha->fp_array[i].err_rx_alloc_errors,
1766 "err_rx_alloc_errors");
1767 }
1768
1769 return;
1770 }
1771
1772 static void
qlnx_add_hw_stats_sysctls(qlnx_host_t * ha)1773 qlnx_add_hw_stats_sysctls(qlnx_host_t *ha)
1774 {
1775 struct sysctl_ctx_list *ctx;
1776 struct sysctl_oid_list *children;
1777 struct sysctl_oid *ctx_oid;
1778
1779 ctx = device_get_sysctl_ctx(ha->pci_dev);
1780 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
1781
1782 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "hwstat",
1783 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "hwstat");
1784 children = SYSCTL_CHILDREN(ctx_oid);
1785
1786 SYSCTL_ADD_QUAD(ctx, children,
1787 OID_AUTO, "no_buff_discards",
1788 CTLFLAG_RD, &ha->hw_stats.common.no_buff_discards,
1789 "No. of packets discarded due to lack of buffer");
1790
1791 SYSCTL_ADD_QUAD(ctx, children,
1792 OID_AUTO, "packet_too_big_discard",
1793 CTLFLAG_RD, &ha->hw_stats.common.packet_too_big_discard,
1794 "No. of packets discarded because packet was too big");
1795
1796 SYSCTL_ADD_QUAD(ctx, children,
1797 OID_AUTO, "ttl0_discard",
1798 CTLFLAG_RD, &ha->hw_stats.common.ttl0_discard,
1799 "ttl0_discard");
1800
1801 SYSCTL_ADD_QUAD(ctx, children,
1802 OID_AUTO, "rx_ucast_bytes",
1803 CTLFLAG_RD, &ha->hw_stats.common.rx_ucast_bytes,
1804 "rx_ucast_bytes");
1805
1806 SYSCTL_ADD_QUAD(ctx, children,
1807 OID_AUTO, "rx_mcast_bytes",
1808 CTLFLAG_RD, &ha->hw_stats.common.rx_mcast_bytes,
1809 "rx_mcast_bytes");
1810
1811 SYSCTL_ADD_QUAD(ctx, children,
1812 OID_AUTO, "rx_bcast_bytes",
1813 CTLFLAG_RD, &ha->hw_stats.common.rx_bcast_bytes,
1814 "rx_bcast_bytes");
1815
1816 SYSCTL_ADD_QUAD(ctx, children,
1817 OID_AUTO, "rx_ucast_pkts",
1818 CTLFLAG_RD, &ha->hw_stats.common.rx_ucast_pkts,
1819 "rx_ucast_pkts");
1820
1821 SYSCTL_ADD_QUAD(ctx, children,
1822 OID_AUTO, "rx_mcast_pkts",
1823 CTLFLAG_RD, &ha->hw_stats.common.rx_mcast_pkts,
1824 "rx_mcast_pkts");
1825
1826 SYSCTL_ADD_QUAD(ctx, children,
1827 OID_AUTO, "rx_bcast_pkts",
1828 CTLFLAG_RD, &ha->hw_stats.common.rx_bcast_pkts,
1829 "rx_bcast_pkts");
1830
1831 SYSCTL_ADD_QUAD(ctx, children,
1832 OID_AUTO, "mftag_filter_discards",
1833 CTLFLAG_RD, &ha->hw_stats.common.mftag_filter_discards,
1834 "mftag_filter_discards");
1835
1836 SYSCTL_ADD_QUAD(ctx, children,
1837 OID_AUTO, "mac_filter_discards",
1838 CTLFLAG_RD, &ha->hw_stats.common.mac_filter_discards,
1839 "mac_filter_discards");
1840
1841 SYSCTL_ADD_QUAD(ctx, children,
1842 OID_AUTO, "tx_ucast_bytes",
1843 CTLFLAG_RD, &ha->hw_stats.common.tx_ucast_bytes,
1844 "tx_ucast_bytes");
1845
1846 SYSCTL_ADD_QUAD(ctx, children,
1847 OID_AUTO, "tx_mcast_bytes",
1848 CTLFLAG_RD, &ha->hw_stats.common.tx_mcast_bytes,
1849 "tx_mcast_bytes");
1850
1851 SYSCTL_ADD_QUAD(ctx, children,
1852 OID_AUTO, "tx_bcast_bytes",
1853 CTLFLAG_RD, &ha->hw_stats.common.tx_bcast_bytes,
1854 "tx_bcast_bytes");
1855
1856 SYSCTL_ADD_QUAD(ctx, children,
1857 OID_AUTO, "tx_ucast_pkts",
1858 CTLFLAG_RD, &ha->hw_stats.common.tx_ucast_pkts,
1859 "tx_ucast_pkts");
1860
1861 SYSCTL_ADD_QUAD(ctx, children,
1862 OID_AUTO, "tx_mcast_pkts",
1863 CTLFLAG_RD, &ha->hw_stats.common.tx_mcast_pkts,
1864 "tx_mcast_pkts");
1865
1866 SYSCTL_ADD_QUAD(ctx, children,
1867 OID_AUTO, "tx_bcast_pkts",
1868 CTLFLAG_RD, &ha->hw_stats.common.tx_bcast_pkts,
1869 "tx_bcast_pkts");
1870
1871 SYSCTL_ADD_QUAD(ctx, children,
1872 OID_AUTO, "tx_err_drop_pkts",
1873 CTLFLAG_RD, &ha->hw_stats.common.tx_err_drop_pkts,
1874 "tx_err_drop_pkts");
1875
1876 SYSCTL_ADD_QUAD(ctx, children,
1877 OID_AUTO, "tpa_coalesced_pkts",
1878 CTLFLAG_RD, &ha->hw_stats.common.tpa_coalesced_pkts,
1879 "tpa_coalesced_pkts");
1880
1881 SYSCTL_ADD_QUAD(ctx, children,
1882 OID_AUTO, "tpa_coalesced_events",
1883 CTLFLAG_RD, &ha->hw_stats.common.tpa_coalesced_events,
1884 "tpa_coalesced_events");
1885
1886 SYSCTL_ADD_QUAD(ctx, children,
1887 OID_AUTO, "tpa_aborts_num",
1888 CTLFLAG_RD, &ha->hw_stats.common.tpa_aborts_num,
1889 "tpa_aborts_num");
1890
1891 SYSCTL_ADD_QUAD(ctx, children,
1892 OID_AUTO, "tpa_not_coalesced_pkts",
1893 CTLFLAG_RD, &ha->hw_stats.common.tpa_not_coalesced_pkts,
1894 "tpa_not_coalesced_pkts");
1895
1896 SYSCTL_ADD_QUAD(ctx, children,
1897 OID_AUTO, "tpa_coalesced_bytes",
1898 CTLFLAG_RD, &ha->hw_stats.common.tpa_coalesced_bytes,
1899 "tpa_coalesced_bytes");
1900
1901 SYSCTL_ADD_QUAD(ctx, children,
1902 OID_AUTO, "rx_64_byte_packets",
1903 CTLFLAG_RD, &ha->hw_stats.common.rx_64_byte_packets,
1904 "rx_64_byte_packets");
1905
1906 SYSCTL_ADD_QUAD(ctx, children,
1907 OID_AUTO, "rx_65_to_127_byte_packets",
1908 CTLFLAG_RD, &ha->hw_stats.common.rx_65_to_127_byte_packets,
1909 "rx_65_to_127_byte_packets");
1910
1911 SYSCTL_ADD_QUAD(ctx, children,
1912 OID_AUTO, "rx_128_to_255_byte_packets",
1913 CTLFLAG_RD, &ha->hw_stats.common.rx_128_to_255_byte_packets,
1914 "rx_128_to_255_byte_packets");
1915
1916 SYSCTL_ADD_QUAD(ctx, children,
1917 OID_AUTO, "rx_256_to_511_byte_packets",
1918 CTLFLAG_RD, &ha->hw_stats.common.rx_256_to_511_byte_packets,
1919 "rx_256_to_511_byte_packets");
1920
1921 SYSCTL_ADD_QUAD(ctx, children,
1922 OID_AUTO, "rx_512_to_1023_byte_packets",
1923 CTLFLAG_RD, &ha->hw_stats.common.rx_512_to_1023_byte_packets,
1924 "rx_512_to_1023_byte_packets");
1925
1926 SYSCTL_ADD_QUAD(ctx, children,
1927 OID_AUTO, "rx_1024_to_1518_byte_packets",
1928 CTLFLAG_RD, &ha->hw_stats.common.rx_1024_to_1518_byte_packets,
1929 "rx_1024_to_1518_byte_packets");
1930
1931 SYSCTL_ADD_QUAD(ctx, children,
1932 OID_AUTO, "rx_1519_to_1522_byte_packets",
1933 CTLFLAG_RD, &ha->hw_stats.bb.rx_1519_to_1522_byte_packets,
1934 "rx_1519_to_1522_byte_packets");
1935
1936 SYSCTL_ADD_QUAD(ctx, children,
1937 OID_AUTO, "rx_1523_to_2047_byte_packets",
1938 CTLFLAG_RD, &ha->hw_stats.bb.rx_1519_to_2047_byte_packets,
1939 "rx_1523_to_2047_byte_packets");
1940
1941 SYSCTL_ADD_QUAD(ctx, children,
1942 OID_AUTO, "rx_2048_to_4095_byte_packets",
1943 CTLFLAG_RD, &ha->hw_stats.bb.rx_2048_to_4095_byte_packets,
1944 "rx_2048_to_4095_byte_packets");
1945
1946 SYSCTL_ADD_QUAD(ctx, children,
1947 OID_AUTO, "rx_4096_to_9216_byte_packets",
1948 CTLFLAG_RD, &ha->hw_stats.bb.rx_4096_to_9216_byte_packets,
1949 "rx_4096_to_9216_byte_packets");
1950
1951 SYSCTL_ADD_QUAD(ctx, children,
1952 OID_AUTO, "rx_9217_to_16383_byte_packets",
1953 CTLFLAG_RD, &ha->hw_stats.bb.rx_9217_to_16383_byte_packets,
1954 "rx_9217_to_16383_byte_packets");
1955
1956 SYSCTL_ADD_QUAD(ctx, children,
1957 OID_AUTO, "rx_crc_errors",
1958 CTLFLAG_RD, &ha->hw_stats.common.rx_crc_errors,
1959 "rx_crc_errors");
1960
1961 SYSCTL_ADD_QUAD(ctx, children,
1962 OID_AUTO, "rx_mac_crtl_frames",
1963 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_crtl_frames,
1964 "rx_mac_crtl_frames");
1965
1966 SYSCTL_ADD_QUAD(ctx, children,
1967 OID_AUTO, "rx_pause_frames",
1968 CTLFLAG_RD, &ha->hw_stats.common.rx_pause_frames,
1969 "rx_pause_frames");
1970
1971 SYSCTL_ADD_QUAD(ctx, children,
1972 OID_AUTO, "rx_pfc_frames",
1973 CTLFLAG_RD, &ha->hw_stats.common.rx_pfc_frames,
1974 "rx_pfc_frames");
1975
1976 SYSCTL_ADD_QUAD(ctx, children,
1977 OID_AUTO, "rx_align_errors",
1978 CTLFLAG_RD, &ha->hw_stats.common.rx_align_errors,
1979 "rx_align_errors");
1980
1981 SYSCTL_ADD_QUAD(ctx, children,
1982 OID_AUTO, "rx_carrier_errors",
1983 CTLFLAG_RD, &ha->hw_stats.common.rx_carrier_errors,
1984 "rx_carrier_errors");
1985
1986 SYSCTL_ADD_QUAD(ctx, children,
1987 OID_AUTO, "rx_oversize_packets",
1988 CTLFLAG_RD, &ha->hw_stats.common.rx_oversize_packets,
1989 "rx_oversize_packets");
1990
1991 SYSCTL_ADD_QUAD(ctx, children,
1992 OID_AUTO, "rx_jabbers",
1993 CTLFLAG_RD, &ha->hw_stats.common.rx_jabbers,
1994 "rx_jabbers");
1995
1996 SYSCTL_ADD_QUAD(ctx, children,
1997 OID_AUTO, "rx_undersize_packets",
1998 CTLFLAG_RD, &ha->hw_stats.common.rx_undersize_packets,
1999 "rx_undersize_packets");
2000
2001 SYSCTL_ADD_QUAD(ctx, children,
2002 OID_AUTO, "rx_fragments",
2003 CTLFLAG_RD, &ha->hw_stats.common.rx_fragments,
2004 "rx_fragments");
2005
2006 SYSCTL_ADD_QUAD(ctx, children,
2007 OID_AUTO, "tx_64_byte_packets",
2008 CTLFLAG_RD, &ha->hw_stats.common.tx_64_byte_packets,
2009 "tx_64_byte_packets");
2010
2011 SYSCTL_ADD_QUAD(ctx, children,
2012 OID_AUTO, "tx_65_to_127_byte_packets",
2013 CTLFLAG_RD, &ha->hw_stats.common.tx_65_to_127_byte_packets,
2014 "tx_65_to_127_byte_packets");
2015
2016 SYSCTL_ADD_QUAD(ctx, children,
2017 OID_AUTO, "tx_128_to_255_byte_packets",
2018 CTLFLAG_RD, &ha->hw_stats.common.tx_128_to_255_byte_packets,
2019 "tx_128_to_255_byte_packets");
2020
2021 SYSCTL_ADD_QUAD(ctx, children,
2022 OID_AUTO, "tx_256_to_511_byte_packets",
2023 CTLFLAG_RD, &ha->hw_stats.common.tx_256_to_511_byte_packets,
2024 "tx_256_to_511_byte_packets");
2025
2026 SYSCTL_ADD_QUAD(ctx, children,
2027 OID_AUTO, "tx_512_to_1023_byte_packets",
2028 CTLFLAG_RD, &ha->hw_stats.common.tx_512_to_1023_byte_packets,
2029 "tx_512_to_1023_byte_packets");
2030
2031 SYSCTL_ADD_QUAD(ctx, children,
2032 OID_AUTO, "tx_1024_to_1518_byte_packets",
2033 CTLFLAG_RD, &ha->hw_stats.common.tx_1024_to_1518_byte_packets,
2034 "tx_1024_to_1518_byte_packets");
2035
2036 SYSCTL_ADD_QUAD(ctx, children,
2037 OID_AUTO, "tx_1519_to_2047_byte_packets",
2038 CTLFLAG_RD, &ha->hw_stats.bb.tx_1519_to_2047_byte_packets,
2039 "tx_1519_to_2047_byte_packets");
2040
2041 SYSCTL_ADD_QUAD(ctx, children,
2042 OID_AUTO, "tx_2048_to_4095_byte_packets",
2043 CTLFLAG_RD, &ha->hw_stats.bb.tx_2048_to_4095_byte_packets,
2044 "tx_2048_to_4095_byte_packets");
2045
2046 SYSCTL_ADD_QUAD(ctx, children,
2047 OID_AUTO, "tx_4096_to_9216_byte_packets",
2048 CTLFLAG_RD, &ha->hw_stats.bb.tx_4096_to_9216_byte_packets,
2049 "tx_4096_to_9216_byte_packets");
2050
2051 SYSCTL_ADD_QUAD(ctx, children,
2052 OID_AUTO, "tx_9217_to_16383_byte_packets",
2053 CTLFLAG_RD, &ha->hw_stats.bb.tx_9217_to_16383_byte_packets,
2054 "tx_9217_to_16383_byte_packets");
2055
2056 SYSCTL_ADD_QUAD(ctx, children,
2057 OID_AUTO, "tx_pause_frames",
2058 CTLFLAG_RD, &ha->hw_stats.common.tx_pause_frames,
2059 "tx_pause_frames");
2060
2061 SYSCTL_ADD_QUAD(ctx, children,
2062 OID_AUTO, "tx_pfc_frames",
2063 CTLFLAG_RD, &ha->hw_stats.common.tx_pfc_frames,
2064 "tx_pfc_frames");
2065
2066 SYSCTL_ADD_QUAD(ctx, children,
2067 OID_AUTO, "tx_lpi_entry_count",
2068 CTLFLAG_RD, &ha->hw_stats.bb.tx_lpi_entry_count,
2069 "tx_lpi_entry_count");
2070
2071 SYSCTL_ADD_QUAD(ctx, children,
2072 OID_AUTO, "tx_total_collisions",
2073 CTLFLAG_RD, &ha->hw_stats.bb.tx_total_collisions,
2074 "tx_total_collisions");
2075
2076 SYSCTL_ADD_QUAD(ctx, children,
2077 OID_AUTO, "brb_truncates",
2078 CTLFLAG_RD, &ha->hw_stats.common.brb_truncates,
2079 "brb_truncates");
2080
2081 SYSCTL_ADD_QUAD(ctx, children,
2082 OID_AUTO, "brb_discards",
2083 CTLFLAG_RD, &ha->hw_stats.common.brb_discards,
2084 "brb_discards");
2085
2086 SYSCTL_ADD_QUAD(ctx, children,
2087 OID_AUTO, "rx_mac_bytes",
2088 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_bytes,
2089 "rx_mac_bytes");
2090
2091 SYSCTL_ADD_QUAD(ctx, children,
2092 OID_AUTO, "rx_mac_uc_packets",
2093 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_uc_packets,
2094 "rx_mac_uc_packets");
2095
2096 SYSCTL_ADD_QUAD(ctx, children,
2097 OID_AUTO, "rx_mac_mc_packets",
2098 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_mc_packets,
2099 "rx_mac_mc_packets");
2100
2101 SYSCTL_ADD_QUAD(ctx, children,
2102 OID_AUTO, "rx_mac_bc_packets",
2103 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_bc_packets,
2104 "rx_mac_bc_packets");
2105
2106 SYSCTL_ADD_QUAD(ctx, children,
2107 OID_AUTO, "rx_mac_frames_ok",
2108 CTLFLAG_RD, &ha->hw_stats.common.rx_mac_frames_ok,
2109 "rx_mac_frames_ok");
2110
2111 SYSCTL_ADD_QUAD(ctx, children,
2112 OID_AUTO, "tx_mac_bytes",
2113 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_bytes,
2114 "tx_mac_bytes");
2115
2116 SYSCTL_ADD_QUAD(ctx, children,
2117 OID_AUTO, "tx_mac_uc_packets",
2118 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_uc_packets,
2119 "tx_mac_uc_packets");
2120
2121 SYSCTL_ADD_QUAD(ctx, children,
2122 OID_AUTO, "tx_mac_mc_packets",
2123 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_mc_packets,
2124 "tx_mac_mc_packets");
2125
2126 SYSCTL_ADD_QUAD(ctx, children,
2127 OID_AUTO, "tx_mac_bc_packets",
2128 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_bc_packets,
2129 "tx_mac_bc_packets");
2130
2131 SYSCTL_ADD_QUAD(ctx, children,
2132 OID_AUTO, "tx_mac_ctrl_frames",
2133 CTLFLAG_RD, &ha->hw_stats.common.tx_mac_ctrl_frames,
2134 "tx_mac_ctrl_frames");
2135 return;
2136 }
2137
2138 static void
qlnx_add_sysctls(qlnx_host_t * ha)2139 qlnx_add_sysctls(qlnx_host_t *ha)
2140 {
2141 device_t dev = ha->pci_dev;
2142 struct sysctl_ctx_list *ctx;
2143 struct sysctl_oid_list *children;
2144
2145 ctx = device_get_sysctl_ctx(dev);
2146 children = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
2147
2148 qlnx_add_fp_stats_sysctls(ha);
2149 qlnx_add_sp_stats_sysctls(ha);
2150
2151 if (qlnx_vf_device(ha) != 0)
2152 qlnx_add_hw_stats_sysctls(ha);
2153
2154 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "Driver_Version",
2155 CTLFLAG_RD, qlnx_ver_str, 0,
2156 "Driver Version");
2157
2158 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "STORMFW_Version",
2159 CTLFLAG_RD, ha->stormfw_ver, 0,
2160 "STORM Firmware Version");
2161
2162 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "MFW_Version",
2163 CTLFLAG_RD, ha->mfw_ver, 0,
2164 "Management Firmware Version");
2165
2166 SYSCTL_ADD_UINT(ctx, children,
2167 OID_AUTO, "personality", CTLFLAG_RD,
2168 &ha->personality, ha->personality,
2169 "\tpersonality = 0 => Ethernet Only\n"
2170 "\tpersonality = 3 => Ethernet and RoCE\n"
2171 "\tpersonality = 4 => Ethernet and iWARP\n"
2172 "\tpersonality = 6 => Default in Shared Memory\n");
2173
2174 ha->dbg_level = 0;
2175 SYSCTL_ADD_UINT(ctx, children,
2176 OID_AUTO, "debug", CTLFLAG_RW,
2177 &ha->dbg_level, ha->dbg_level, "Debug Level");
2178
2179 ha->dp_level = 0x01;
2180 SYSCTL_ADD_UINT(ctx, children,
2181 OID_AUTO, "dp_level", CTLFLAG_RW,
2182 &ha->dp_level, ha->dp_level, "DP Level");
2183
2184 ha->dbg_trace_lro_cnt = 0;
2185 SYSCTL_ADD_UINT(ctx, children,
2186 OID_AUTO, "dbg_trace_lro_cnt", CTLFLAG_RW,
2187 &ha->dbg_trace_lro_cnt, ha->dbg_trace_lro_cnt,
2188 "Trace LRO Counts");
2189
2190 ha->dbg_trace_tso_pkt_len = 0;
2191 SYSCTL_ADD_UINT(ctx, children,
2192 OID_AUTO, "dbg_trace_tso_pkt_len", CTLFLAG_RW,
2193 &ha->dbg_trace_tso_pkt_len, ha->dbg_trace_tso_pkt_len,
2194 "Trace TSO packet lengths");
2195
2196 ha->dp_module = 0;
2197 SYSCTL_ADD_UINT(ctx, children,
2198 OID_AUTO, "dp_module", CTLFLAG_RW,
2199 &ha->dp_module, ha->dp_module, "DP Module");
2200
2201 ha->err_inject = 0;
2202
2203 SYSCTL_ADD_UINT(ctx, children,
2204 OID_AUTO, "err_inject", CTLFLAG_RW,
2205 &ha->err_inject, ha->err_inject, "Error Inject");
2206
2207 ha->storm_stats_enable = 0;
2208
2209 SYSCTL_ADD_UINT(ctx, children,
2210 OID_AUTO, "storm_stats_enable", CTLFLAG_RW,
2211 &ha->storm_stats_enable, ha->storm_stats_enable,
2212 "Enable Storm Statistics Gathering");
2213
2214 ha->storm_stats_index = 0;
2215
2216 SYSCTL_ADD_UINT(ctx, children,
2217 OID_AUTO, "storm_stats_index", CTLFLAG_RD,
2218 &ha->storm_stats_index, ha->storm_stats_index,
2219 "Enable Storm Statistics Gathering Current Index");
2220
2221 ha->grcdump_taken = 0;
2222 SYSCTL_ADD_UINT(ctx, children,
2223 OID_AUTO, "grcdump_taken", CTLFLAG_RD,
2224 &ha->grcdump_taken, ha->grcdump_taken,
2225 "grcdump_taken");
2226
2227 ha->idle_chk_taken = 0;
2228 SYSCTL_ADD_UINT(ctx, children,
2229 OID_AUTO, "idle_chk_taken", CTLFLAG_RD,
2230 &ha->idle_chk_taken, ha->idle_chk_taken,
2231 "idle_chk_taken");
2232
2233 SYSCTL_ADD_UINT(ctx, children,
2234 OID_AUTO, "rx_coalesce_usecs", CTLFLAG_RD,
2235 &ha->rx_coalesce_usecs, ha->rx_coalesce_usecs,
2236 "rx_coalesce_usecs");
2237
2238 SYSCTL_ADD_UINT(ctx, children,
2239 OID_AUTO, "tx_coalesce_usecs", CTLFLAG_RD,
2240 &ha->tx_coalesce_usecs, ha->tx_coalesce_usecs,
2241 "tx_coalesce_usecs");
2242
2243 SYSCTL_ADD_PROC(ctx, children,
2244 OID_AUTO, "trigger_dump",
2245 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
2246 (void *)ha, 0, qlnx_trigger_dump_sysctl, "I", "trigger_dump");
2247
2248 SYSCTL_ADD_PROC(ctx, children,
2249 OID_AUTO, "set_rx_coalesce_usecs",
2250 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
2251 (void *)ha, 0, qlnx_set_rx_coalesce, "I",
2252 "rx interrupt coalesce period microseconds");
2253
2254 SYSCTL_ADD_PROC(ctx, children,
2255 OID_AUTO, "set_tx_coalesce_usecs",
2256 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
2257 (void *)ha, 0, qlnx_set_tx_coalesce, "I",
2258 "tx interrupt coalesce period microseconds");
2259
2260 ha->rx_pkt_threshold = 128;
2261 SYSCTL_ADD_UINT(ctx, children,
2262 OID_AUTO, "rx_pkt_threshold", CTLFLAG_RW,
2263 &ha->rx_pkt_threshold, ha->rx_pkt_threshold,
2264 "No. of Rx Pkts to process at a time");
2265
2266 ha->rx_jumbo_buf_eq_mtu = 0;
2267 SYSCTL_ADD_UINT(ctx, children,
2268 OID_AUTO, "rx_jumbo_buf_eq_mtu", CTLFLAG_RW,
2269 &ha->rx_jumbo_buf_eq_mtu, ha->rx_jumbo_buf_eq_mtu,
2270 "== 0 => Rx Jumbo buffers are capped to 4Kbytes\n"
2271 "otherwise Rx Jumbo buffers are set to >= MTU size\n");
2272
2273 SYSCTL_ADD_QUAD(ctx, children,
2274 OID_AUTO, "err_illegal_intr", CTLFLAG_RD,
2275 &ha->err_illegal_intr, "err_illegal_intr");
2276
2277 SYSCTL_ADD_QUAD(ctx, children,
2278 OID_AUTO, "err_fp_null", CTLFLAG_RD,
2279 &ha->err_fp_null, "err_fp_null");
2280
2281 SYSCTL_ADD_QUAD(ctx, children,
2282 OID_AUTO, "err_get_proto_invalid_type", CTLFLAG_RD,
2283 &ha->err_get_proto_invalid_type, "err_get_proto_invalid_type");
2284 return;
2285 }
2286
2287 /*****************************************************************************
2288 * Operating System Network Interface Functions
2289 *****************************************************************************/
2290
2291 static void
qlnx_init_ifnet(device_t dev,qlnx_host_t * ha)2292 qlnx_init_ifnet(device_t dev, qlnx_host_t *ha)
2293 {
2294 uint16_t device_id;
2295 if_t ifp;
2296
2297 ifp = ha->ifp = if_alloc(IFT_ETHER);
2298 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2299
2300 device_id = pci_get_device(ha->pci_dev);
2301
2302 if (device_id == QLOGIC_PCI_DEVICE_ID_1634)
2303 if_setbaudrate(ifp, IF_Gbps(40));
2304 else if ((device_id == QLOGIC_PCI_DEVICE_ID_1656) ||
2305 (device_id == QLOGIC_PCI_DEVICE_ID_8070))
2306 if_setbaudrate(ifp, IF_Gbps(25));
2307 else if (device_id == QLOGIC_PCI_DEVICE_ID_1654)
2308 if_setbaudrate(ifp, IF_Gbps(50));
2309 else if (device_id == QLOGIC_PCI_DEVICE_ID_1644)
2310 if_setbaudrate(ifp, IF_Gbps(100));
2311
2312 if_setinitfn(ifp, qlnx_init);
2313 if_setsoftc(ifp, ha);
2314 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
2315 if_setioctlfn(ifp, qlnx_ioctl);
2316 if_settransmitfn(ifp, qlnx_transmit);
2317 if_setqflushfn(ifp, qlnx_qflush);
2318
2319 if_setsendqlen(ifp, qlnx_get_ifq_snd_maxlen(ha));
2320 if_setsendqready(ifp);
2321
2322 if_setgetcounterfn(ifp, qlnx_get_counter);
2323
2324 ha->max_frame_size = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN;
2325
2326 qlnx_get_mac_addr(ha);
2327
2328 if (!ha->primary_mac[0] && !ha->primary_mac[1] &&
2329 !ha->primary_mac[2] && !ha->primary_mac[3] &&
2330 !ha->primary_mac[4] && !ha->primary_mac[5]) {
2331 uint32_t rnd;
2332
2333 rnd = arc4random();
2334
2335 ha->primary_mac[0] = 0x00;
2336 ha->primary_mac[1] = 0x0e;
2337 ha->primary_mac[2] = 0x1e;
2338 ha->primary_mac[3] = rnd & 0xFF;
2339 ha->primary_mac[4] = (rnd >> 8) & 0xFF;
2340 ha->primary_mac[5] = (rnd >> 16) & 0xFF;
2341 }
2342
2343 if_setcapabilities(ifp, IFCAP_HWCSUM);
2344 if_setcapabilitiesbit(ifp, IFCAP_JUMBO_MTU, 0);
2345 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
2346 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0);
2347 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWFILTER, 0);
2348 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
2349 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTSO, 0);
2350 if_setcapabilitiesbit(ifp, IFCAP_TSO4, 0);
2351 if_setcapabilitiesbit(ifp, IFCAP_TSO6, 0);
2352 if_setcapabilitiesbit(ifp, IFCAP_LRO, 0);
2353 if_setcapabilitiesbit(ifp, IFCAP_LINKSTATE, 0);
2354 if_setcapabilitiesbit(ifp, IFCAP_HWSTATS, 0);
2355
2356 if_sethwtsomax(ifp, QLNX_MAX_TSO_FRAME_SIZE -
2357 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN));
2358 if_sethwtsomaxsegcount(ifp, QLNX_MAX_SEGMENTS - 1); /* hdr */
2359 if_sethwtsomaxsegsize(ifp, QLNX_MAX_TX_MBUF_SIZE);
2360
2361 if_setcapenable(ifp, if_getcapabilities(ifp));
2362
2363 if_sethwassist(ifp, CSUM_IP);
2364 if_sethwassistbits(ifp, CSUM_TCP | CSUM_UDP, 0);
2365 if_sethwassistbits(ifp, CSUM_TCP_IPV6 | CSUM_UDP_IPV6, 0);
2366 if_sethwassistbits(ifp, CSUM_TSO, 0);
2367
2368 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
2369
2370 ifmedia_init(&ha->media, IFM_IMASK, qlnx_media_change,\
2371 qlnx_media_status);
2372
2373 if (device_id == QLOGIC_PCI_DEVICE_ID_1634) {
2374 ifmedia_add(&ha->media, (IFM_ETHER | IFM_40G_LR4), 0, NULL);
2375 ifmedia_add(&ha->media, (IFM_ETHER | IFM_40G_SR4), 0, NULL);
2376 ifmedia_add(&ha->media, (IFM_ETHER | IFM_40G_CR4), 0, NULL);
2377 } else if ((device_id == QLOGIC_PCI_DEVICE_ID_1656) ||
2378 (device_id == QLOGIC_PCI_DEVICE_ID_8070)) {
2379 ifmedia_add(&ha->media, (IFM_ETHER | IFM_25G_SR), 0, NULL);
2380 ifmedia_add(&ha->media, (IFM_ETHER | IFM_25G_CR), 0, NULL);
2381 } else if (device_id == QLOGIC_PCI_DEVICE_ID_1654) {
2382 ifmedia_add(&ha->media, (IFM_ETHER | IFM_50G_KR2), 0, NULL);
2383 ifmedia_add(&ha->media, (IFM_ETHER | IFM_50G_CR2), 0, NULL);
2384 } else if (device_id == QLOGIC_PCI_DEVICE_ID_1644) {
2385 ifmedia_add(&ha->media, (IFM_ETHER | IFM_100G_LR4), 0, NULL);
2386 ifmedia_add(&ha->media, (IFM_ETHER | IFM_100G_SR4), 0, NULL);
2387 ifmedia_add(&ha->media, (IFM_ETHER | IFM_100G_CR4), 0, NULL);
2388 }
2389
2390 ifmedia_add(&ha->media, (IFM_ETHER | IFM_FDX), 0, NULL);
2391 ifmedia_add(&ha->media, (IFM_ETHER | IFM_AUTO), 0, NULL);
2392
2393 ifmedia_set(&ha->media, (IFM_ETHER | IFM_AUTO));
2394
2395 ether_ifattach(ifp, ha->primary_mac);
2396 QL_DPRINT2(ha, "exit\n");
2397
2398 return;
2399 }
2400
2401 static void
qlnx_init_locked(qlnx_host_t * ha)2402 qlnx_init_locked(qlnx_host_t *ha)
2403 {
2404 if_t ifp = ha->ifp;
2405
2406 QL_DPRINT1(ha, "Driver Initialization start \n");
2407
2408 qlnx_stop(ha);
2409
2410 if (qlnx_load(ha) == 0) {
2411 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2412 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2413
2414 #ifdef QLNX_ENABLE_IWARP
2415 if (qlnx_vf_device(ha) != 0) {
2416 qlnx_rdma_dev_open(ha);
2417 }
2418 #endif /* #ifdef QLNX_ENABLE_IWARP */
2419 }
2420
2421 return;
2422 }
2423
2424 static void
qlnx_init(void * arg)2425 qlnx_init(void *arg)
2426 {
2427 qlnx_host_t *ha;
2428
2429 ha = (qlnx_host_t *)arg;
2430
2431 QL_DPRINT2(ha, "enter\n");
2432
2433 QLNX_LOCK(ha);
2434 if ((if_getdrvflags(ha->ifp) & IFF_DRV_RUNNING) == 0)
2435 qlnx_init_locked(ha);
2436 QLNX_UNLOCK(ha);
2437
2438 QL_DPRINT2(ha, "exit\n");
2439
2440 return;
2441 }
2442
2443 static u_int
qlnx_mcast_bins_from_maddr(void * arg,struct sockaddr_dl * sdl,u_int mcnt)2444 qlnx_mcast_bins_from_maddr(void *arg, struct sockaddr_dl *sdl, u_int mcnt)
2445 {
2446 uint8_t bit;
2447 uint32_t *bins = arg;
2448
2449 bit = ecore_mcast_bin_from_mac(LLADDR(sdl));
2450 bins[bit / 32] |= 1 << (bit % 32);
2451
2452 return (1);
2453 }
2454
2455 static int
qlnx_set_multi(qlnx_host_t * ha)2456 qlnx_set_multi(qlnx_host_t *ha)
2457 {
2458 struct ecore_filter_mcast mcast;
2459 struct ecore_dev *cdev;
2460 if_t ifp = ha->ifp;
2461 u_int mcnt __unused;
2462 int rc;
2463
2464 if (qlnx_vf_device(ha) == 0)
2465 return (0);
2466
2467 bzero(&mcast, sizeof(struct ecore_filter_mcast));
2468 mcnt = if_foreach_llmaddr(ifp, qlnx_mcast_bins_from_maddr, mcast.bins);
2469 QL_DPRINT1(ha, "total %d multicast MACs found\n", mcnt);
2470
2471 if (memcmp(ha->ecore_mcast_bins, mcast.bins, sizeof(mcast.bins)) == 0)
2472 return (0);
2473
2474 cdev = &ha->cdev;
2475 mcast.opcode = ECORE_FILTER_REPLACE;
2476 rc = ecore_filter_mcast_cmd(cdev, &mcast, ECORE_SPQ_MODE_CB, NULL);
2477 if (rc == 0)
2478 memcpy(ha->ecore_mcast_bins, mcast.bins, sizeof(mcast.bins));
2479
2480 QL_DPRINT1(ha, "ecore_filter_mcast_cmd: end(%d)\n", rc);
2481 return (rc);
2482 }
2483
2484 static int
qlnx_set_promisc_allmulti(qlnx_host_t * ha,int flags)2485 qlnx_set_promisc_allmulti(qlnx_host_t *ha, int flags)
2486 {
2487 int rc = 0;
2488
2489 if (qlnx_vf_device(ha) == 0)
2490 return (0);
2491
2492 rc = _qlnx_set_promisc_allmulti(ha, flags & IFF_PROMISC,
2493 flags & IFF_ALLMULTI);
2494 return (rc);
2495 }
2496
2497 static int
_qlnx_set_promisc_allmulti(qlnx_host_t * ha,bool promisc,bool allmulti)2498 _qlnx_set_promisc_allmulti(qlnx_host_t *ha, bool promisc, bool allmulti)
2499 {
2500 int rc = 0;
2501 uint8_t filter;
2502 bool mcast, ucast;
2503
2504 filter = ha->filter;
2505 filter |= ECORE_ACCEPT_UCAST_MATCHED;
2506 filter |= ECORE_ACCEPT_MCAST_MATCHED;
2507 filter |= ECORE_ACCEPT_BCAST;
2508
2509 mcast = promisc || allmulti;
2510 ucast = promisc;
2511
2512 if (mcast)
2513 filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
2514 else
2515 filter &= ~ECORE_ACCEPT_MCAST_UNMATCHED;
2516
2517 if (ucast)
2518 filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
2519 else
2520 filter &= ~ECORE_ACCEPT_UCAST_UNMATCHED;
2521
2522 if (filter == ha->filter)
2523 return (0);
2524
2525 rc = qlnx_set_rx_accept_filter(ha, filter);
2526 if (rc == 0)
2527 ha->filter = filter;
2528 return (rc);
2529 }
2530
2531 static int
qlnx_rss_query_status(qlnx_host_t * ha)2532 qlnx_rss_query_status(qlnx_host_t *ha)
2533 {
2534 int i;
2535
2536 sx_assert(&ha->hw_lock, SA_XLOCKED);
2537 if (ha->state != QLNX_STATE_OPEN ||
2538 (if_getdrvflags(ha->ifp) & IFF_DRV_RUNNING) == 0)
2539 return (ENXIO);
2540 if (IS_VF(&ha->cdev) && ha->rss_params.rss_enable) {
2541 for (i = 0; i < ha->cdev.num_hwfns; i++) {
2542 struct ecore_vf_iov *iov = ha->cdev.hwfns[i].vf_iov_info;
2543
2544 if (iov == NULL || !iov->rss_configured)
2545 return (ENXIO);
2546 }
2547 }
2548 return (0);
2549 }
2550
2551 static int
qlnx_get_rss_key(qlnx_host_t * ha,struct ifrsskey * ifrk)2552 qlnx_get_rss_key(qlnx_host_t *ha, struct ifrsskey *ifrk)
2553 {
2554 const struct ecore_rss_params *rss = &ha->rss_params;
2555 int error, i;
2556
2557 error = qlnx_rss_query_status(ha);
2558 if (error != 0)
2559 return (error);
2560 ifrk->ifrk_func = rss->rss_enable ? RSS_FUNC_TOEPLITZ : RSS_FUNC_NONE;
2561 ifrk->ifrk_keylen = rss->rss_enable ? sizeof(rss->rss_key) : 0;
2562 _Static_assert(sizeof(ifrk->ifrk_key) >= sizeof(rss->rss_key),
2563 "RSS query buffer too small");
2564 bzero(ifrk->ifrk_key, sizeof(ifrk->ifrk_key));
2565 /* Undo the word conversion used when preparing the firmware request. */
2566 if (rss->rss_enable) {
2567 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
2568 be32enc(ifrk->ifrk_key + i * sizeof(uint32_t),
2569 rss->rss_key[i]);
2570 }
2571 return (0);
2572 }
2573
2574 static int
qlnx_get_rss_hash(qlnx_host_t * ha,struct ifrsshash * ifrh)2575 qlnx_get_rss_hash(qlnx_host_t *ha, struct ifrsshash *ifrh)
2576 {
2577 const struct ecore_rss_params *rss = &ha->rss_params;
2578 uint8_t caps;
2579 int error;
2580
2581 error = qlnx_rss_query_status(ha);
2582 if (error != 0)
2583 return (error);
2584 ifrh->ifrh_func = rss->rss_enable ? RSS_FUNC_TOEPLITZ : RSS_FUNC_NONE;
2585 ifrh->ifrh_types = 0;
2586 caps = rss->rss_enable ? rss->rss_caps : 0;
2587 if (caps & ECORE_RSS_IPV4)
2588 ifrh->ifrh_types |= RSS_TYPE_IPV4;
2589 if (caps & ECORE_RSS_IPV4_TCP)
2590 ifrh->ifrh_types |= RSS_TYPE_TCP_IPV4;
2591 if (caps & ECORE_RSS_IPV4_UDP)
2592 ifrh->ifrh_types |= RSS_TYPE_UDP_IPV4;
2593 if (caps & ECORE_RSS_IPV6)
2594 ifrh->ifrh_types |= RSS_TYPE_IPV6;
2595 if (caps & ECORE_RSS_IPV6_TCP)
2596 ifrh->ifrh_types |= RSS_TYPE_TCP_IPV6;
2597 if (caps & ECORE_RSS_IPV6_UDP)
2598 ifrh->ifrh_types |= RSS_TYPE_UDP_IPV6;
2599 return (0);
2600 }
2601
2602 static int
qlnx_ioctl(if_t ifp,u_long cmd,caddr_t data)2603 qlnx_ioctl(if_t ifp, u_long cmd, caddr_t data)
2604 {
2605 int ret = 0, mask;
2606 int flags;
2607 struct ifreq *ifr = (struct ifreq *)data;
2608 qlnx_host_t *ha;
2609
2610 ha = (qlnx_host_t *)if_getsoftc(ifp);
2611
2612 switch (cmd) {
2613 case SIOCGIFRSSKEY:
2614 QLNX_LOCK(ha);
2615 ret = qlnx_get_rss_key(ha, (struct ifrsskey *)data);
2616 QLNX_UNLOCK(ha);
2617 break;
2618
2619 case SIOCGIFRSSHASH:
2620 QLNX_LOCK(ha);
2621 ret = qlnx_get_rss_hash(ha, (struct ifrsshash *)data);
2622 QLNX_UNLOCK(ha);
2623 break;
2624
2625 case SIOCSIFMTU:
2626 QL_DPRINT4(ha, "SIOCSIFMTU (0x%lx)\n", cmd);
2627
2628 if (ifr->ifr_mtu > QLNX_MAX_MTU) {
2629 ret = EINVAL;
2630 } else {
2631 QLNX_LOCK(ha);
2632 if_setmtu(ifp, ifr->ifr_mtu);
2633 ha->max_frame_size =
2634 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN;
2635 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
2636 qlnx_init_locked(ha);
2637 }
2638
2639 QLNX_UNLOCK(ha);
2640 }
2641
2642 break;
2643
2644 case SIOCSIFFLAGS:
2645 QL_DPRINT4(ha, "SIOCSIFFLAGS (0x%lx)\n", cmd);
2646
2647 QLNX_LOCK(ha);
2648 flags = if_getflags(ifp);
2649
2650 if (flags & IFF_UP) {
2651 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
2652 if (qlnx_set_promisc_allmulti(ha, flags) != 0)
2653 ret = EINVAL;
2654 } else {
2655 ha->max_frame_size = if_getmtu(ifp) +
2656 ETHER_HDR_LEN + ETHER_CRC_LEN;
2657 qlnx_init_locked(ha);
2658 }
2659 } else {
2660 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2661 qlnx_stop(ha);
2662 }
2663
2664 QLNX_UNLOCK(ha);
2665 break;
2666
2667 case SIOCADDMULTI:
2668 case SIOCDELMULTI:
2669 QL_DPRINT4(ha, "%s (0x%lx)\n", "SIOCADDMULTI/SIOCDELMULTI", cmd);
2670
2671 QLNX_LOCK(ha);
2672 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2673 if (qlnx_set_multi(ha) != 0)
2674 ret = EINVAL;
2675 }
2676 QLNX_UNLOCK(ha);
2677 break;
2678
2679 case SIOCSIFMEDIA:
2680 case SIOCGIFMEDIA:
2681 case SIOCGIFXMEDIA:
2682 QL_DPRINT4(ha,
2683 "SIOCSIFMEDIA/SIOCGIFMEDIA/SIOCGIFXMEDIA (0x%lx)\n", cmd);
2684
2685 ret = ifmedia_ioctl(ifp, ifr, &ha->media, cmd);
2686 break;
2687
2688 case SIOCSIFCAP:
2689
2690 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
2691
2692 QL_DPRINT4(ha, "SIOCSIFCAP (0x%lx)\n", cmd);
2693
2694 if (mask & IFCAP_HWCSUM)
2695 if_togglecapenable(ifp, IFCAP_HWCSUM);
2696 if (mask & IFCAP_TSO4)
2697 if_togglecapenable(ifp, IFCAP_TSO4);
2698 if (mask & IFCAP_TSO6)
2699 if_togglecapenable(ifp, IFCAP_TSO6);
2700 if (mask & IFCAP_VLAN_HWTAGGING)
2701 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2702 if (mask & IFCAP_VLAN_HWTSO)
2703 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
2704 if (mask & IFCAP_LRO)
2705 if_togglecapenable(ifp, IFCAP_LRO);
2706
2707 QLNX_LOCK(ha);
2708
2709 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2710 qlnx_init_locked(ha);
2711
2712 QLNX_UNLOCK(ha);
2713
2714 VLAN_CAPABILITIES(ifp);
2715 break;
2716
2717 case SIOCGI2C:
2718 {
2719 struct ifi2creq i2c;
2720 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[0];
2721 struct ecore_ptt *p_ptt;
2722
2723 ret = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2724
2725 if (ret)
2726 break;
2727
2728 if ((i2c.len > sizeof (i2c.data)) ||
2729 (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2)) {
2730 ret = EINVAL;
2731 break;
2732 }
2733
2734 p_ptt = ecore_ptt_acquire(p_hwfn);
2735
2736 if (!p_ptt) {
2737 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
2738 ret = ERESTART;
2739 break;
2740 }
2741
2742 ret = ecore_mcp_phy_sfp_read(p_hwfn, p_ptt,
2743 (ha->pci_func & 0x1), i2c.dev_addr, i2c.offset,
2744 i2c.len, &i2c.data[0]);
2745
2746 ecore_ptt_release(p_hwfn, p_ptt);
2747
2748 if (ret) {
2749 ret = ENODEV;
2750 break;
2751 }
2752
2753 ret = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2754
2755 QL_DPRINT8(ha, "SIOCGI2C copyout ret = %d \
2756 len = %d addr = 0x%02x offset = 0x%04x \
2757 data[0..7]=0x%02x 0x%02x 0x%02x 0x%02x 0x%02x \
2758 0x%02x 0x%02x 0x%02x\n",
2759 ret, i2c.len, i2c.dev_addr, i2c.offset,
2760 i2c.data[0], i2c.data[1], i2c.data[2], i2c.data[3],
2761 i2c.data[4], i2c.data[5], i2c.data[6], i2c.data[7]);
2762 break;
2763 }
2764
2765 default:
2766 QL_DPRINT4(ha, "default (0x%lx)\n", cmd);
2767 ret = ether_ioctl(ifp, cmd, data);
2768 break;
2769 }
2770
2771 return (ret);
2772 }
2773
2774 static int
qlnx_media_change(if_t ifp)2775 qlnx_media_change(if_t ifp)
2776 {
2777 qlnx_host_t *ha;
2778 struct ifmedia *ifm;
2779 int ret = 0;
2780
2781 ha = (qlnx_host_t *)if_getsoftc(ifp);
2782
2783 QL_DPRINT2(ha, "enter\n");
2784
2785 ifm = &ha->media;
2786
2787 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2788 ret = EINVAL;
2789
2790 QL_DPRINT2(ha, "exit\n");
2791
2792 return (ret);
2793 }
2794
2795 static void
qlnx_media_status(if_t ifp,struct ifmediareq * ifmr)2796 qlnx_media_status(if_t ifp, struct ifmediareq *ifmr)
2797 {
2798 qlnx_host_t *ha;
2799
2800 ha = (qlnx_host_t *)if_getsoftc(ifp);
2801
2802 QL_DPRINT2(ha, "enter\n");
2803
2804 ifmr->ifm_status = IFM_AVALID;
2805 ifmr->ifm_active = IFM_ETHER;
2806
2807 if (ha->link_up) {
2808 ifmr->ifm_status |= IFM_ACTIVE;
2809 ifmr->ifm_active |=
2810 (IFM_FDX | qlnx_get_optics(ha, &ha->if_link));
2811
2812 if (ha->if_link.link_partner_caps &
2813 (QLNX_LINK_CAP_Pause | QLNX_LINK_CAP_Asym_Pause))
2814 ifmr->ifm_active |=
2815 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
2816 }
2817
2818 QL_DPRINT2(ha, "exit (%s)\n", (ha->link_up ? "link_up" : "link_down"));
2819
2820 return;
2821 }
2822
2823 static void
qlnx_free_tx_pkt(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_tx_queue * txq)2824 qlnx_free_tx_pkt(qlnx_host_t *ha, struct qlnx_fastpath *fp,
2825 struct qlnx_tx_queue *txq)
2826 {
2827 u16 idx;
2828 struct mbuf *mp;
2829 bus_dmamap_t map;
2830 int i;
2831 // struct eth_tx_bd *tx_data_bd;
2832 struct eth_tx_1st_bd *first_bd;
2833 int nbds = 0;
2834
2835 idx = txq->sw_tx_cons;
2836 mp = txq->sw_tx_ring[idx].mp;
2837 map = txq->sw_tx_ring[idx].map;
2838
2839 if ((mp == NULL) || QL_ERR_INJECT(ha, QL_ERR_INJCT_TX_INT_MBUF_NULL)){
2840 QL_RESET_ERR_INJECT(ha, QL_ERR_INJCT_TX_INT_MBUF_NULL);
2841
2842 QL_DPRINT1(ha, "(mp == NULL) "
2843 " tx_idx = 0x%x"
2844 " ecore_prod_idx = 0x%x"
2845 " ecore_cons_idx = 0x%x"
2846 " hw_bd_cons = 0x%x"
2847 " txq_db_last = 0x%x"
2848 " elem_left = 0x%x\n",
2849 fp->rss_id,
2850 ecore_chain_get_prod_idx(&txq->tx_pbl),
2851 ecore_chain_get_cons_idx(&txq->tx_pbl),
2852 le16toh(*txq->hw_cons_ptr),
2853 txq->tx_db.raw,
2854 ecore_chain_get_elem_left(&txq->tx_pbl));
2855
2856 fp->err_tx_free_pkt_null++;
2857
2858 //DEBUG
2859 qlnx_trigger_dump(ha);
2860
2861 return;
2862 } else {
2863 QLNX_INC_OPACKETS((ha->ifp));
2864 QLNX_INC_OBYTES((ha->ifp), (mp->m_pkthdr.len));
2865
2866 bus_dmamap_sync(ha->tx_tag, map, BUS_DMASYNC_POSTWRITE);
2867 bus_dmamap_unload(ha->tx_tag, map);
2868
2869 fp->tx_pkts_freed++;
2870 fp->tx_pkts_completed++;
2871
2872 m_freem(mp);
2873 }
2874
2875 first_bd = (struct eth_tx_1st_bd *)ecore_chain_consume(&txq->tx_pbl);
2876 nbds = first_bd->data.nbds;
2877
2878 // BD_SET_UNMAP_ADDR_LEN(first_bd, 0, 0);
2879
2880 for (i = 1; i < nbds; i++) {
2881 /* tx_data_bd = */ ecore_chain_consume(&txq->tx_pbl);
2882 // BD_SET_UNMAP_ADDR_LEN(tx_data_bd, 0, 0);
2883 }
2884 txq->sw_tx_ring[idx].flags = 0;
2885 txq->sw_tx_ring[idx].mp = NULL;
2886 txq->sw_tx_ring[idx].map = (bus_dmamap_t)0;
2887
2888 return;
2889 }
2890
2891 static void
qlnx_tx_int(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_tx_queue * txq)2892 qlnx_tx_int(qlnx_host_t *ha, struct qlnx_fastpath *fp,
2893 struct qlnx_tx_queue *txq)
2894 {
2895 u16 hw_bd_cons;
2896 u16 ecore_cons_idx;
2897 uint16_t diff;
2898 uint16_t idx, idx2;
2899
2900 hw_bd_cons = le16toh(*txq->hw_cons_ptr);
2901
2902 while (hw_bd_cons !=
2903 (ecore_cons_idx = ecore_chain_get_cons_idx(&txq->tx_pbl))) {
2904 diff = hw_bd_cons - ecore_cons_idx;
2905 if ((diff > TX_RING_SIZE) ||
2906 QL_ERR_INJECT(ha, QL_ERR_INJCT_TX_INT_DIFF)){
2907 QL_RESET_ERR_INJECT(ha, QL_ERR_INJCT_TX_INT_DIFF);
2908
2909 QL_DPRINT1(ha, "(diff = 0x%x) "
2910 " tx_idx = 0x%x"
2911 " ecore_prod_idx = 0x%x"
2912 " ecore_cons_idx = 0x%x"
2913 " hw_bd_cons = 0x%x"
2914 " txq_db_last = 0x%x"
2915 " elem_left = 0x%x\n",
2916 diff,
2917 fp->rss_id,
2918 ecore_chain_get_prod_idx(&txq->tx_pbl),
2919 ecore_chain_get_cons_idx(&txq->tx_pbl),
2920 le16toh(*txq->hw_cons_ptr),
2921 txq->tx_db.raw,
2922 ecore_chain_get_elem_left(&txq->tx_pbl));
2923
2924 fp->err_tx_cons_idx_conflict++;
2925
2926 //DEBUG
2927 qlnx_trigger_dump(ha);
2928 }
2929
2930 idx = (txq->sw_tx_cons + 1) & (TX_RING_SIZE - 1);
2931 idx2 = (txq->sw_tx_cons + 2) & (TX_RING_SIZE - 1);
2932 prefetch(txq->sw_tx_ring[idx].mp);
2933 prefetch(txq->sw_tx_ring[idx2].mp);
2934
2935 qlnx_free_tx_pkt(ha, fp, txq);
2936
2937 txq->sw_tx_cons = (txq->sw_tx_cons + 1) & (TX_RING_SIZE - 1);
2938 }
2939 return;
2940 }
2941
2942 static int
qlnx_transmit_locked(if_t ifp,struct qlnx_fastpath * fp,struct mbuf * mp)2943 qlnx_transmit_locked(if_t ifp, struct qlnx_fastpath *fp, struct mbuf *mp)
2944 {
2945 int ret = 0;
2946 struct qlnx_tx_queue *txq;
2947 qlnx_host_t * ha;
2948 uint16_t elem_left;
2949
2950 txq = fp->txq[0];
2951 ha = (qlnx_host_t *)fp->edev;
2952
2953 if ((!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) || (!ha->link_up)) {
2954 if(mp != NULL)
2955 ret = drbr_enqueue(ifp, fp->tx_br, mp);
2956 return (ret);
2957 }
2958
2959 if(mp != NULL)
2960 ret = drbr_enqueue(ifp, fp->tx_br, mp);
2961
2962 mp = drbr_peek(ifp, fp->tx_br);
2963
2964 while (mp != NULL) {
2965 if (qlnx_send(ha, fp, &mp)) {
2966 if (mp != NULL) {
2967 drbr_putback(ifp, fp->tx_br, mp);
2968 } else {
2969 fp->tx_pkts_processed++;
2970 drbr_advance(ifp, fp->tx_br);
2971 }
2972 goto qlnx_transmit_locked_exit;
2973
2974 } else {
2975 drbr_advance(ifp, fp->tx_br);
2976 fp->tx_pkts_transmitted++;
2977 fp->tx_pkts_processed++;
2978 ETHER_BPF_MTAP(ifp, mp);
2979 }
2980
2981 mp = drbr_peek(ifp, fp->tx_br);
2982 }
2983
2984 qlnx_transmit_locked_exit:
2985 if((qlnx_num_tx_compl(ha,fp, fp->txq[0]) > QLNX_TX_COMPL_THRESH) ||
2986 ((int)(elem_left = ecore_chain_get_elem_left(&txq->tx_pbl))
2987 < QLNX_TX_ELEM_MAX_THRESH))
2988 (void)qlnx_tx_int(ha, fp, fp->txq[0]);
2989
2990 QL_DPRINT2(ha, "%s: exit ret = %d\n", __func__, ret);
2991 return ret;
2992 }
2993
2994 static int
qlnx_transmit(if_t ifp,struct mbuf * mp)2995 qlnx_transmit(if_t ifp, struct mbuf *mp)
2996 {
2997 qlnx_host_t *ha = (qlnx_host_t *)if_getsoftc(ifp);
2998 struct qlnx_fastpath *fp;
2999 int rss_id = 0, ret = 0;
3000
3001 #ifdef QLNX_TRACEPERF_DATA
3002 uint64_t tx_pkts = 0, tx_compl = 0;
3003 #endif
3004
3005 QL_DPRINT2(ha, "enter\n");
3006
3007 if (M_HASHTYPE_GET(mp) != M_HASHTYPE_NONE)
3008 rss_id = (mp->m_pkthdr.flowid % ECORE_RSS_IND_TABLE_SIZE) %
3009 ha->num_rss;
3010
3011 fp = &ha->fp_array[rss_id];
3012
3013 if (fp->tx_br == NULL) {
3014 ret = EINVAL;
3015 goto qlnx_transmit_exit;
3016 }
3017
3018 if (mtx_trylock(&fp->tx_mtx)) {
3019 #ifdef QLNX_TRACEPERF_DATA
3020 tx_pkts = fp->tx_pkts_transmitted;
3021 tx_compl = fp->tx_pkts_completed;
3022 #endif
3023
3024 ret = qlnx_transmit_locked(ifp, fp, mp);
3025
3026 #ifdef QLNX_TRACEPERF_DATA
3027 fp->tx_pkts_trans_ctx += (fp->tx_pkts_transmitted - tx_pkts);
3028 fp->tx_pkts_compl_ctx += (fp->tx_pkts_completed - tx_compl);
3029 #endif
3030 mtx_unlock(&fp->tx_mtx);
3031 } else {
3032 if (mp != NULL && (fp->fp_taskqueue != NULL)) {
3033 ret = drbr_enqueue(ifp, fp->tx_br, mp);
3034 taskqueue_enqueue(fp->fp_taskqueue, &fp->fp_task);
3035 }
3036 }
3037
3038 qlnx_transmit_exit:
3039
3040 QL_DPRINT2(ha, "exit ret = %d\n", ret);
3041 return ret;
3042 }
3043
3044 static void
qlnx_qflush(if_t ifp)3045 qlnx_qflush(if_t ifp)
3046 {
3047 int rss_id;
3048 struct qlnx_fastpath *fp;
3049 struct mbuf *mp;
3050 qlnx_host_t *ha;
3051
3052 ha = (qlnx_host_t *)if_getsoftc(ifp);
3053
3054 QL_DPRINT2(ha, "enter\n");
3055
3056 for (rss_id = 0; rss_id < ha->num_rss; rss_id++) {
3057 fp = &ha->fp_array[rss_id];
3058
3059 if (fp == NULL)
3060 continue;
3061
3062 if (fp->tx_br) {
3063 mtx_lock(&fp->tx_mtx);
3064
3065 while ((mp = drbr_dequeue(ifp, fp->tx_br)) != NULL) {
3066 fp->tx_pkts_freed++;
3067 m_freem(mp);
3068 }
3069 mtx_unlock(&fp->tx_mtx);
3070 }
3071 }
3072 QL_DPRINT2(ha, "exit\n");
3073
3074 return;
3075 }
3076
3077 static void
qlnx_txq_doorbell_wr32(qlnx_host_t * ha,void * reg_addr,uint32_t value)3078 qlnx_txq_doorbell_wr32(qlnx_host_t *ha, void *reg_addr, uint32_t value)
3079 {
3080 uint32_t offset;
3081
3082 offset = (uint32_t)((uint8_t *)reg_addr - (uint8_t *)ha->pci_dbells);
3083
3084 bus_write_4(ha->pci_dbells, offset, value);
3085 bus_barrier(ha->pci_reg, 0, 0, BUS_SPACE_BARRIER_READ);
3086 bus_barrier(ha->pci_dbells, 0, 0, BUS_SPACE_BARRIER_READ);
3087
3088 return;
3089 }
3090
3091 static uint32_t
qlnx_tcp_offset(qlnx_host_t * ha,struct mbuf * mp)3092 qlnx_tcp_offset(qlnx_host_t *ha, struct mbuf *mp)
3093 {
3094 struct ether_vlan_header *eh = NULL;
3095 struct ip *ip = NULL;
3096 struct ip6_hdr *ip6 = NULL;
3097 struct tcphdr *th = NULL;
3098 uint32_t ehdrlen = 0, ip_hlen = 0, offset = 0;
3099 uint16_t etype = 0;
3100 uint8_t buf[sizeof(struct ip6_hdr)];
3101
3102 eh = mtod(mp, struct ether_vlan_header *);
3103
3104 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3105 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3106 etype = ntohs(eh->evl_proto);
3107 } else {
3108 ehdrlen = ETHER_HDR_LEN;
3109 etype = ntohs(eh->evl_encap_proto);
3110 }
3111
3112 switch (etype) {
3113 case ETHERTYPE_IP:
3114 ip = (struct ip *)(mp->m_data + ehdrlen);
3115
3116 ip_hlen = sizeof (struct ip);
3117
3118 if (mp->m_len < (ehdrlen + ip_hlen)) {
3119 m_copydata(mp, ehdrlen, sizeof(struct ip), buf);
3120 ip = (struct ip *)buf;
3121 }
3122
3123 th = (struct tcphdr *)(ip + 1);
3124 offset = ip_hlen + ehdrlen + (th->th_off << 2);
3125 break;
3126
3127 case ETHERTYPE_IPV6:
3128 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
3129
3130 ip_hlen = sizeof(struct ip6_hdr);
3131
3132 if (mp->m_len < (ehdrlen + ip_hlen)) {
3133 m_copydata(mp, ehdrlen, sizeof (struct ip6_hdr),
3134 buf);
3135 ip6 = (struct ip6_hdr *)buf;
3136 }
3137 th = (struct tcphdr *)(ip6 + 1);
3138 offset = ip_hlen + ehdrlen + (th->th_off << 2);
3139 break;
3140
3141 default:
3142 break;
3143 }
3144
3145 return (offset);
3146 }
3147
3148 static __inline int
qlnx_tso_check(struct qlnx_fastpath * fp,bus_dma_segment_t * segs,int nsegs,uint32_t offset)3149 qlnx_tso_check(struct qlnx_fastpath *fp, bus_dma_segment_t *segs, int nsegs,
3150 uint32_t offset)
3151 {
3152 int i;
3153 uint32_t sum, nbds_in_hdr = 1;
3154 uint32_t window;
3155 bus_dma_segment_t *s_seg;
3156
3157 /* If the header spans multiple segments, skip those segments */
3158
3159 if (nsegs < ETH_TX_LSO_WINDOW_BDS_NUM)
3160 return (0);
3161
3162 i = 0;
3163
3164 while ((i < nsegs) && (offset >= segs->ds_len)) {
3165 offset = offset - segs->ds_len;
3166 segs++;
3167 i++;
3168 nbds_in_hdr++;
3169 }
3170
3171 window = ETH_TX_LSO_WINDOW_BDS_NUM - nbds_in_hdr;
3172
3173 nsegs = nsegs - i;
3174
3175 while (nsegs >= window) {
3176 sum = 0;
3177 s_seg = segs;
3178
3179 for (i = 0; i < window; i++){
3180 sum += s_seg->ds_len;
3181 s_seg++;
3182 }
3183
3184 if (sum < ETH_TX_LSO_WINDOW_MIN_LEN) {
3185 fp->tx_lso_wnd_min_len++;
3186 return (-1);
3187 }
3188
3189 nsegs = nsegs - 1;
3190 segs++;
3191 }
3192
3193 return (0);
3194 }
3195
3196 static int
qlnx_send(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct mbuf ** m_headp)3197 qlnx_send(qlnx_host_t *ha, struct qlnx_fastpath *fp, struct mbuf **m_headp)
3198 {
3199 bus_dma_segment_t *segs;
3200 bus_dmamap_t map = 0;
3201 uint32_t nsegs = 0;
3202 int ret = -1;
3203 struct mbuf *m_head = *m_headp;
3204 uint16_t idx = 0;
3205 uint16_t elem_left;
3206
3207 uint8_t nbd = 0;
3208 struct qlnx_tx_queue *txq;
3209
3210 struct eth_tx_1st_bd *first_bd;
3211 struct eth_tx_2nd_bd *second_bd;
3212 struct eth_tx_3rd_bd *third_bd;
3213 struct eth_tx_bd *tx_data_bd;
3214
3215 int seg_idx = 0;
3216 uint32_t nbds_in_hdr = 0;
3217 uint32_t offset = 0;
3218
3219 #ifdef QLNX_TRACE_PERF_DATA
3220 uint16_t bd_used;
3221 #endif
3222
3223 QL_DPRINT8(ha, "enter[%d]\n", fp->rss_id);
3224
3225 if (!ha->link_up)
3226 return (-1);
3227
3228 first_bd = NULL;
3229 second_bd = NULL;
3230 third_bd = NULL;
3231 tx_data_bd = NULL;
3232
3233 txq = fp->txq[0];
3234
3235 if ((int)(elem_left = ecore_chain_get_elem_left(&txq->tx_pbl)) <
3236 QLNX_TX_ELEM_MIN_THRESH) {
3237 fp->tx_nsegs_gt_elem_left++;
3238 fp->err_tx_nsegs_gt_elem_left++;
3239
3240 return (ENOBUFS);
3241 }
3242
3243 idx = txq->sw_tx_prod;
3244
3245 map = txq->sw_tx_ring[idx].map;
3246 segs = txq->segs;
3247
3248 ret = bus_dmamap_load_mbuf_sg(ha->tx_tag, map, m_head, segs, &nsegs,
3249 BUS_DMA_NOWAIT);
3250
3251 if (ha->dbg_trace_tso_pkt_len) {
3252 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3253 if (!fp->tx_tso_min_pkt_len) {
3254 fp->tx_tso_min_pkt_len = m_head->m_pkthdr.len;
3255 fp->tx_tso_min_pkt_len = m_head->m_pkthdr.len;
3256 } else {
3257 if (fp->tx_tso_min_pkt_len > m_head->m_pkthdr.len)
3258 fp->tx_tso_min_pkt_len =
3259 m_head->m_pkthdr.len;
3260 if (fp->tx_tso_max_pkt_len < m_head->m_pkthdr.len)
3261 fp->tx_tso_max_pkt_len =
3262 m_head->m_pkthdr.len;
3263 }
3264 }
3265 }
3266
3267 if (m_head->m_pkthdr.csum_flags & CSUM_TSO)
3268 offset = qlnx_tcp_offset(ha, m_head);
3269
3270 if ((ret == EFBIG) ||
3271 ((nsegs > QLNX_MAX_SEGMENTS_NON_TSO) && (
3272 (!(m_head->m_pkthdr.csum_flags & CSUM_TSO)) ||
3273 ((m_head->m_pkthdr.csum_flags & CSUM_TSO) &&
3274 qlnx_tso_check(fp, segs, nsegs, offset))))) {
3275 struct mbuf *m;
3276
3277 QL_DPRINT8(ha, "EFBIG [%d]\n", m_head->m_pkthdr.len);
3278
3279 fp->tx_defrag++;
3280
3281 m = m_defrag(m_head, M_NOWAIT);
3282 if (m == NULL) {
3283 fp->err_tx_defrag++;
3284 fp->tx_pkts_freed++;
3285 m_freem(m_head);
3286 *m_headp = NULL;
3287 QL_DPRINT1(ha, "m_defrag() = NULL [%d]\n", ret);
3288 return (ENOBUFS);
3289 }
3290
3291 m_head = m;
3292 *m_headp = m_head;
3293
3294 if ((ret = bus_dmamap_load_mbuf_sg(ha->tx_tag, map, m_head,
3295 segs, &nsegs, BUS_DMA_NOWAIT))) {
3296 fp->err_tx_defrag_dmamap_load++;
3297
3298 QL_DPRINT1(ha,
3299 "bus_dmamap_load_mbuf_sg failed0 [%d, %d]\n",
3300 ret, m_head->m_pkthdr.len);
3301
3302 fp->tx_pkts_freed++;
3303 m_freem(m_head);
3304 *m_headp = NULL;
3305
3306 return (ret);
3307 }
3308
3309 if ((nsegs > QLNX_MAX_SEGMENTS_NON_TSO) &&
3310 !(m_head->m_pkthdr.csum_flags & CSUM_TSO)) {
3311 fp->err_tx_non_tso_max_seg++;
3312
3313 QL_DPRINT1(ha,
3314 "(%d) nsegs too many for non-TSO [%d, %d]\n",
3315 ret, nsegs, m_head->m_pkthdr.len);
3316
3317 fp->tx_pkts_freed++;
3318 m_freem(m_head);
3319 *m_headp = NULL;
3320
3321 return (ret);
3322 }
3323 if (m_head->m_pkthdr.csum_flags & CSUM_TSO)
3324 offset = qlnx_tcp_offset(ha, m_head);
3325
3326 } else if (ret) {
3327 fp->err_tx_dmamap_load++;
3328
3329 QL_DPRINT1(ha, "bus_dmamap_load_mbuf_sg failed1 [%d, %d]\n",
3330 ret, m_head->m_pkthdr.len);
3331 fp->tx_pkts_freed++;
3332 m_freem(m_head);
3333 *m_headp = NULL;
3334 return (ret);
3335 }
3336
3337 QL_ASSERT(ha, (nsegs != 0), ("qlnx_send: empty packet"));
3338
3339 if (ha->dbg_trace_tso_pkt_len) {
3340 if (nsegs < QLNX_FP_MAX_SEGS)
3341 fp->tx_pkts[(nsegs - 1)]++;
3342 else
3343 fp->tx_pkts[(QLNX_FP_MAX_SEGS - 1)]++;
3344 }
3345
3346 #ifdef QLNX_TRACE_PERF_DATA
3347 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3348 if(m_head->m_pkthdr.len <= 2048)
3349 fp->tx_pkts_hist[0]++;
3350 else if((m_head->m_pkthdr.len > 2048) &&
3351 (m_head->m_pkthdr.len <= 4096))
3352 fp->tx_pkts_hist[1]++;
3353 else if((m_head->m_pkthdr.len > 4096) &&
3354 (m_head->m_pkthdr.len <= 8192))
3355 fp->tx_pkts_hist[2]++;
3356 else if((m_head->m_pkthdr.len > 8192) &&
3357 (m_head->m_pkthdr.len <= 12288 ))
3358 fp->tx_pkts_hist[3]++;
3359 else if((m_head->m_pkthdr.len > 11288) &&
3360 (m_head->m_pkthdr.len <= 16394))
3361 fp->tx_pkts_hist[4]++;
3362 else if((m_head->m_pkthdr.len > 16384) &&
3363 (m_head->m_pkthdr.len <= 20480))
3364 fp->tx_pkts_hist[5]++;
3365 else if((m_head->m_pkthdr.len > 20480) &&
3366 (m_head->m_pkthdr.len <= 24576))
3367 fp->tx_pkts_hist[6]++;
3368 else if((m_head->m_pkthdr.len > 24576) &&
3369 (m_head->m_pkthdr.len <= 28672))
3370 fp->tx_pkts_hist[7]++;
3371 else if((m_head->m_pkthdr.len > 28762) &&
3372 (m_head->m_pkthdr.len <= 32768))
3373 fp->tx_pkts_hist[8]++;
3374 else if((m_head->m_pkthdr.len > 32768) &&
3375 (m_head->m_pkthdr.len <= 36864))
3376 fp->tx_pkts_hist[9]++;
3377 else if((m_head->m_pkthdr.len > 36864) &&
3378 (m_head->m_pkthdr.len <= 40960))
3379 fp->tx_pkts_hist[10]++;
3380 else if((m_head->m_pkthdr.len > 40960) &&
3381 (m_head->m_pkthdr.len <= 45056))
3382 fp->tx_pkts_hist[11]++;
3383 else if((m_head->m_pkthdr.len > 45056) &&
3384 (m_head->m_pkthdr.len <= 49152))
3385 fp->tx_pkts_hist[12]++;
3386 else if((m_head->m_pkthdr.len > 49512) &&
3387 m_head->m_pkthdr.len <= 53248))
3388 fp->tx_pkts_hist[13]++;
3389 else if((m_head->m_pkthdr.len > 53248) &&
3390 (m_head->m_pkthdr.len <= 57344))
3391 fp->tx_pkts_hist[14]++;
3392 else if((m_head->m_pkthdr.len > 53248) &&
3393 (m_head->m_pkthdr.len <= 57344))
3394 fp->tx_pkts_hist[15]++;
3395 else if((m_head->m_pkthdr.len > 57344) &&
3396 (m_head->m_pkthdr.len <= 61440))
3397 fp->tx_pkts_hist[16]++;
3398 else
3399 fp->tx_pkts_hist[17]++;
3400 }
3401
3402 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3403 elem_left = ecore_chain_get_elem_left(&txq->tx_pbl);
3404 bd_used = TX_RING_SIZE - elem_left;
3405
3406 if(bd_used <= 100)
3407 fp->tx_pkts_q[0]++;
3408 else if((bd_used > 100) && (bd_used <= 500))
3409 fp->tx_pkts_q[1]++;
3410 else if((bd_used > 500) && (bd_used <= 1000))
3411 fp->tx_pkts_q[2]++;
3412 else if((bd_used > 1000) && (bd_used <= 2000))
3413 fp->tx_pkts_q[3]++;
3414 else if((bd_used > 3000) && (bd_used <= 4000))
3415 fp->tx_pkts_q[4]++;
3416 else if((bd_used > 4000) && (bd_used <= 5000))
3417 fp->tx_pkts_q[5]++;
3418 else if((bd_used > 6000) && (bd_used <= 7000))
3419 fp->tx_pkts_q[6]++;
3420 else if((bd_used > 7000) && (bd_used <= 8000))
3421 fp->tx_pkts_q[7]++;
3422 else if((bd_used > 8000) && (bd_used <= 9000))
3423 fp->tx_pkts_q[8]++;
3424 else if((bd_used > 9000) && (bd_used <= 10000))
3425 fp->tx_pkts_q[9]++;
3426 else if((bd_used > 10000) && (bd_used <= 11000))
3427 fp->tx_pkts_q[10]++;
3428 else if((bd_used > 11000) && (bd_used <= 12000))
3429 fp->tx_pkts_q[11]++;
3430 else if((bd_used > 12000) && (bd_used <= 13000))
3431 fp->tx_pkts_q[12]++;
3432 else if((bd_used > 13000) && (bd_used <= 14000))
3433 fp->tx_pkts_q[13]++;
3434 else if((bd_used > 14000) && (bd_used <= 15000))
3435 fp->tx_pkts_q[14]++;
3436 else if((bd_used > 15000) && (bd_used <= 16000))
3437 fp->tx_pkts_q[15]++;
3438 else
3439 fp->tx_pkts_q[16]++;
3440 }
3441
3442 #endif /* end of QLNX_TRACE_PERF_DATA */
3443
3444 if ((nsegs + QLNX_TX_ELEM_RESERVE) >
3445 (int)(elem_left = ecore_chain_get_elem_left(&txq->tx_pbl))) {
3446 QL_DPRINT1(ha, "(%d, 0x%x) insuffient BDs"
3447 " in chain[%d] trying to free packets\n",
3448 nsegs, elem_left, fp->rss_id);
3449
3450 fp->tx_nsegs_gt_elem_left++;
3451
3452 (void)qlnx_tx_int(ha, fp, txq);
3453
3454 if ((nsegs + QLNX_TX_ELEM_RESERVE) > (int)(elem_left =
3455 ecore_chain_get_elem_left(&txq->tx_pbl))) {
3456 QL_DPRINT1(ha,
3457 "(%d, 0x%x) insuffient BDs in chain[%d]\n",
3458 nsegs, elem_left, fp->rss_id);
3459
3460 fp->err_tx_nsegs_gt_elem_left++;
3461 fp->tx_ring_full = 1;
3462 if (ha->storm_stats_enable)
3463 ha->storm_stats_gather = 1;
3464 return (ENOBUFS);
3465 }
3466 }
3467
3468 bus_dmamap_sync(ha->tx_tag, map, BUS_DMASYNC_PREWRITE);
3469
3470 txq->sw_tx_ring[idx].mp = m_head;
3471
3472 first_bd = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
3473
3474 memset(first_bd, 0, sizeof(*first_bd));
3475
3476 first_bd->data.bd_flags.bitfields =
3477 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
3478
3479 BD_SET_UNMAP_ADDR_LEN(first_bd, segs->ds_addr, segs->ds_len);
3480
3481 nbd++;
3482
3483 if (m_head->m_pkthdr.csum_flags & CSUM_IP) {
3484 first_bd->data.bd_flags.bitfields |=
3485 (1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT);
3486 }
3487
3488 if (m_head->m_pkthdr.csum_flags &
3489 (CSUM_UDP | CSUM_TCP | CSUM_TCP_IPV6 | CSUM_UDP_IPV6)) {
3490 first_bd->data.bd_flags.bitfields |=
3491 (1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT);
3492 }
3493
3494 if (m_head->m_flags & M_VLANTAG) {
3495 first_bd->data.vlan = m_head->m_pkthdr.ether_vtag;
3496 first_bd->data.bd_flags.bitfields |=
3497 (1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT);
3498 }
3499
3500 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3501 first_bd->data.bd_flags.bitfields |=
3502 (1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT);
3503 first_bd->data.bd_flags.bitfields |=
3504 (1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT);
3505
3506 nbds_in_hdr = 1;
3507
3508 if (offset == segs->ds_len) {
3509 BD_SET_UNMAP_ADDR_LEN(first_bd, segs->ds_addr, offset);
3510 segs++;
3511 seg_idx++;
3512
3513 second_bd = (struct eth_tx_2nd_bd *)
3514 ecore_chain_produce(&txq->tx_pbl);
3515 memset(second_bd, 0, sizeof(*second_bd));
3516 nbd++;
3517
3518 if (seg_idx < nsegs) {
3519 BD_SET_UNMAP_ADDR_LEN(second_bd, \
3520 (segs->ds_addr), (segs->ds_len));
3521 segs++;
3522 seg_idx++;
3523 }
3524
3525 third_bd = (struct eth_tx_3rd_bd *)
3526 ecore_chain_produce(&txq->tx_pbl);
3527 memset(third_bd, 0, sizeof(*third_bd));
3528 third_bd->data.lso_mss = m_head->m_pkthdr.tso_segsz;
3529 third_bd->data.bitfields |=
3530 (nbds_in_hdr<<ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
3531 nbd++;
3532
3533 if (seg_idx < nsegs) {
3534 BD_SET_UNMAP_ADDR_LEN(third_bd, \
3535 (segs->ds_addr), (segs->ds_len));
3536 segs++;
3537 seg_idx++;
3538 }
3539
3540 for (; seg_idx < nsegs; seg_idx++) {
3541 tx_data_bd = (struct eth_tx_bd *)
3542 ecore_chain_produce(&txq->tx_pbl);
3543 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
3544 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, \
3545 segs->ds_addr,\
3546 segs->ds_len);
3547 segs++;
3548 nbd++;
3549 }
3550
3551 } else if (offset < segs->ds_len) {
3552 BD_SET_UNMAP_ADDR_LEN(first_bd, segs->ds_addr, offset);
3553
3554 second_bd = (struct eth_tx_2nd_bd *)
3555 ecore_chain_produce(&txq->tx_pbl);
3556 memset(second_bd, 0, sizeof(*second_bd));
3557 BD_SET_UNMAP_ADDR_LEN(second_bd, \
3558 (segs->ds_addr + offset),\
3559 (segs->ds_len - offset));
3560 nbd++;
3561 segs++;
3562
3563 third_bd = (struct eth_tx_3rd_bd *)
3564 ecore_chain_produce(&txq->tx_pbl);
3565 memset(third_bd, 0, sizeof(*third_bd));
3566
3567 BD_SET_UNMAP_ADDR_LEN(third_bd, \
3568 segs->ds_addr,\
3569 segs->ds_len);
3570 third_bd->data.lso_mss = m_head->m_pkthdr.tso_segsz;
3571 third_bd->data.bitfields |=
3572 (nbds_in_hdr<<ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
3573 segs++;
3574 nbd++;
3575
3576 for (seg_idx = 2; seg_idx < nsegs; seg_idx++) {
3577 tx_data_bd = (struct eth_tx_bd *)
3578 ecore_chain_produce(&txq->tx_pbl);
3579 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
3580 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, \
3581 segs->ds_addr,\
3582 segs->ds_len);
3583 segs++;
3584 nbd++;
3585 }
3586
3587 } else {
3588 offset = offset - segs->ds_len;
3589 segs++;
3590
3591 for (seg_idx = 1; seg_idx < nsegs; seg_idx++) {
3592 if (offset)
3593 nbds_in_hdr++;
3594
3595 tx_data_bd = (struct eth_tx_bd *)
3596 ecore_chain_produce(&txq->tx_pbl);
3597 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
3598
3599 if (second_bd == NULL) {
3600 second_bd = (struct eth_tx_2nd_bd *)
3601 tx_data_bd;
3602 } else if (third_bd == NULL) {
3603 third_bd = (struct eth_tx_3rd_bd *)
3604 tx_data_bd;
3605 }
3606
3607 if (offset && (offset < segs->ds_len)) {
3608 BD_SET_UNMAP_ADDR_LEN(tx_data_bd,\
3609 segs->ds_addr, offset);
3610
3611 tx_data_bd = (struct eth_tx_bd *)
3612 ecore_chain_produce(&txq->tx_pbl);
3613
3614 memset(tx_data_bd, 0,
3615 sizeof(*tx_data_bd));
3616
3617 if (second_bd == NULL) {
3618 second_bd =
3619 (struct eth_tx_2nd_bd *)tx_data_bd;
3620 } else if (third_bd == NULL) {
3621 third_bd =
3622 (struct eth_tx_3rd_bd *)tx_data_bd;
3623 }
3624 BD_SET_UNMAP_ADDR_LEN(tx_data_bd,\
3625 (segs->ds_addr + offset), \
3626 (segs->ds_len - offset));
3627 nbd++;
3628 offset = 0;
3629 } else {
3630 if (offset)
3631 offset = offset - segs->ds_len;
3632 BD_SET_UNMAP_ADDR_LEN(tx_data_bd,\
3633 segs->ds_addr, segs->ds_len);
3634 }
3635 segs++;
3636 nbd++;
3637 }
3638
3639 if (third_bd == NULL) {
3640 third_bd = (struct eth_tx_3rd_bd *)
3641 ecore_chain_produce(&txq->tx_pbl);
3642 memset(third_bd, 0, sizeof(*third_bd));
3643 }
3644
3645 third_bd->data.lso_mss = m_head->m_pkthdr.tso_segsz;
3646 third_bd->data.bitfields |=
3647 (nbds_in_hdr<<ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
3648 }
3649 fp->tx_tso_pkts++;
3650 } else {
3651 segs++;
3652 for (seg_idx = 1; seg_idx < nsegs; seg_idx++) {
3653 tx_data_bd = (struct eth_tx_bd *)
3654 ecore_chain_produce(&txq->tx_pbl);
3655 memset(tx_data_bd, 0, sizeof(*tx_data_bd));
3656 BD_SET_UNMAP_ADDR_LEN(tx_data_bd, segs->ds_addr,\
3657 segs->ds_len);
3658 segs++;
3659 nbd++;
3660 }
3661 first_bd->data.bitfields =
3662 (m_head->m_pkthdr.len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
3663 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
3664 first_bd->data.bitfields =
3665 htole16(first_bd->data.bitfields);
3666 fp->tx_non_tso_pkts++;
3667 }
3668
3669 first_bd->data.nbds = nbd;
3670
3671 if (ha->dbg_trace_tso_pkt_len) {
3672 if (fp->tx_tso_max_nsegs < nsegs)
3673 fp->tx_tso_max_nsegs = nsegs;
3674
3675 if ((nsegs < fp->tx_tso_min_nsegs) || (!fp->tx_tso_min_nsegs))
3676 fp->tx_tso_min_nsegs = nsegs;
3677 }
3678
3679 txq->sw_tx_ring[idx].nsegs = nsegs;
3680 txq->sw_tx_prod = (txq->sw_tx_prod + 1) & (TX_RING_SIZE - 1);
3681
3682 txq->tx_db.data.bd_prod =
3683 htole16(ecore_chain_get_prod_idx(&txq->tx_pbl));
3684
3685 qlnx_txq_doorbell_wr32(ha, txq->doorbell_addr, txq->tx_db.raw);
3686
3687 QL_DPRINT8(ha, "exit[%d]\n", fp->rss_id);
3688 return (0);
3689 }
3690
3691 static void
qlnx_stop(qlnx_host_t * ha)3692 qlnx_stop(qlnx_host_t *ha)
3693 {
3694 if_t ifp = ha->ifp;
3695 int i;
3696
3697 if_setdrvflagbits(ifp, 0, (IFF_DRV_OACTIVE | IFF_DRV_RUNNING));
3698
3699 /*
3700 * We simply lock and unlock each fp->tx_mtx to
3701 * propagate the if_drv_flags
3702 * state to each tx thread
3703 */
3704 QL_DPRINT1(ha, "QLNX STATE = %d\n",ha->state);
3705
3706 if (ha->state == QLNX_STATE_OPEN) {
3707 for (i = 0; i < ha->num_rss; i++) {
3708 struct qlnx_fastpath *fp = &ha->fp_array[i];
3709
3710 mtx_lock(&fp->tx_mtx);
3711 mtx_unlock(&fp->tx_mtx);
3712
3713 if (fp->fp_taskqueue != NULL)
3714 taskqueue_enqueue(fp->fp_taskqueue,
3715 &fp->fp_task);
3716 }
3717 }
3718 #ifdef QLNX_ENABLE_IWARP
3719 if (qlnx_vf_device(ha) != 0) {
3720 qlnx_rdma_dev_close(ha);
3721 }
3722 #endif /* #ifdef QLNX_ENABLE_IWARP */
3723
3724 qlnx_unload(ha);
3725
3726 return;
3727 }
3728
3729 static int
qlnx_get_ifq_snd_maxlen(qlnx_host_t * ha)3730 qlnx_get_ifq_snd_maxlen(qlnx_host_t *ha)
3731 {
3732 return(TX_RING_SIZE - 1);
3733 }
3734
3735 static void
qlnx_get_mac_addr(qlnx_host_t * ha)3736 qlnx_get_mac_addr(qlnx_host_t *ha)
3737 {
3738 struct ecore_hwfn *p_hwfn;
3739 unsigned char mac[ETHER_ADDR_LEN];
3740 uint8_t p_is_forced;
3741
3742 p_hwfn = &ha->cdev.hwfns[0];
3743
3744 if (qlnx_vf_device(ha) != 0) {
3745 memcpy(ha->primary_mac, p_hwfn->hw_info.hw_mac_addr, ETH_ALEN);
3746 return;
3747 }
3748
3749 ecore_vf_read_bulletin(p_hwfn, &p_is_forced);
3750 if (ecore_vf_bulletin_get_forced_mac(p_hwfn, mac, &p_is_forced) ==
3751 true) {
3752 device_printf(ha->pci_dev, "%s: p_is_forced = %d"
3753 " mac_addr = %02x:%02x:%02x:%02x:%02x:%02x\n", __func__,
3754 p_is_forced, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
3755 memcpy(ha->primary_mac, mac, ETH_ALEN);
3756 }
3757 }
3758
3759 static uint32_t
qlnx_get_optics(qlnx_host_t * ha,struct qlnx_link_output * if_link)3760 qlnx_get_optics(qlnx_host_t *ha, struct qlnx_link_output *if_link)
3761 {
3762 uint32_t ifm_type = 0;
3763
3764 switch (if_link->media_type) {
3765 case MEDIA_MODULE_FIBER:
3766 case MEDIA_UNSPECIFIED:
3767 if (if_link->speed == (100 * 1000))
3768 ifm_type = IFM_100G_SR4;
3769 else if (if_link->speed == (40 * 1000))
3770 ifm_type = IFM_40G_SR4;
3771 else if (if_link->speed == (25 * 1000))
3772 ifm_type = IFM_25G_SR;
3773 else if (if_link->speed == (10 * 1000))
3774 ifm_type = (IFM_10G_LR | IFM_10G_SR);
3775 else if (if_link->speed == (1 * 1000))
3776 ifm_type = (IFM_1000_SX | IFM_1000_LX);
3777
3778 break;
3779
3780 case MEDIA_DA_TWINAX:
3781 if (if_link->speed == (100 * 1000))
3782 ifm_type = IFM_100G_CR4;
3783 else if (if_link->speed == (40 * 1000))
3784 ifm_type = IFM_40G_CR4;
3785 else if (if_link->speed == (25 * 1000))
3786 ifm_type = IFM_25G_CR;
3787 else if (if_link->speed == (10 * 1000))
3788 ifm_type = IFM_10G_TWINAX;
3789
3790 break;
3791
3792 default :
3793 ifm_type = IFM_UNKNOWN;
3794 break;
3795 }
3796 return (ifm_type);
3797 }
3798
3799 /*****************************************************************************
3800 * Interrupt Service Functions
3801 *****************************************************************************/
3802
3803 static int
qlnx_rx_jumbo_chain(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct mbuf * mp_head,uint16_t len)3804 qlnx_rx_jumbo_chain(qlnx_host_t *ha, struct qlnx_fastpath *fp,
3805 struct mbuf *mp_head, uint16_t len)
3806 {
3807 struct mbuf *mp, *mpf, *mpl;
3808 struct sw_rx_data *sw_rx_data;
3809 struct qlnx_rx_queue *rxq;
3810 uint16_t len_in_buffer;
3811
3812 rxq = fp->rxq;
3813 mpf = mpl = mp = NULL;
3814
3815 while (len) {
3816 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
3817
3818 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
3819 mp = sw_rx_data->data;
3820
3821 if (mp == NULL) {
3822 QL_DPRINT1(ha, "mp = NULL\n");
3823 fp->err_rx_mp_null++;
3824 rxq->sw_rx_cons =
3825 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
3826
3827 if (mpf != NULL)
3828 m_freem(mpf);
3829
3830 return (-1);
3831 }
3832 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
3833 BUS_DMASYNC_POSTREAD);
3834
3835 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
3836 QL_DPRINT1(ha, "New buffer allocation failed, dropping"
3837 " incoming packet and reusing its buffer\n");
3838
3839 qlnx_reuse_rx_data(rxq);
3840 fp->err_rx_alloc_errors++;
3841
3842 if (mpf != NULL)
3843 m_freem(mpf);
3844
3845 return (-1);
3846 }
3847 ecore_chain_consume(&rxq->rx_bd_ring);
3848
3849 if (len > rxq->rx_buf_size)
3850 len_in_buffer = rxq->rx_buf_size;
3851 else
3852 len_in_buffer = len;
3853
3854 len = len - len_in_buffer;
3855
3856 mp->m_flags &= ~M_PKTHDR;
3857 mp->m_next = NULL;
3858 mp->m_len = len_in_buffer;
3859
3860 if (mpf == NULL)
3861 mpf = mpl = mp;
3862 else {
3863 mpl->m_next = mp;
3864 mpl = mp;
3865 }
3866 }
3867
3868 if (mpf != NULL)
3869 mp_head->m_next = mpf;
3870
3871 return (0);
3872 }
3873
3874 static void
qlnx_tpa_start(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_rx_queue * rxq,struct eth_fast_path_rx_tpa_start_cqe * cqe)3875 qlnx_tpa_start(qlnx_host_t *ha,
3876 struct qlnx_fastpath *fp,
3877 struct qlnx_rx_queue *rxq,
3878 struct eth_fast_path_rx_tpa_start_cqe *cqe)
3879 {
3880 uint32_t agg_index;
3881 if_t ifp = ha->ifp;
3882 struct mbuf *mp;
3883 struct mbuf *mpf = NULL, *mpl = NULL, *mpc = NULL;
3884 struct sw_rx_data *sw_rx_data;
3885 dma_addr_t addr;
3886 bus_dmamap_t map;
3887 struct eth_rx_bd *rx_bd;
3888 int i;
3889 uint8_t hash_type;
3890
3891 agg_index = cqe->tpa_agg_index;
3892
3893 QL_DPRINT7(ha, "[rss_id = %d]: enter\n \
3894 \t type = 0x%x\n \
3895 \t bitfields = 0x%x\n \
3896 \t seg_len = 0x%x\n \
3897 \t pars_flags = 0x%x\n \
3898 \t vlan_tag = 0x%x\n \
3899 \t rss_hash = 0x%x\n \
3900 \t len_on_first_bd = 0x%x\n \
3901 \t placement_offset = 0x%x\n \
3902 \t tpa_agg_index = 0x%x\n \
3903 \t header_len = 0x%x\n \
3904 \t ext_bd_len_list[0] = 0x%x\n \
3905 \t ext_bd_len_list[1] = 0x%x\n \
3906 \t ext_bd_len_list[2] = 0x%x\n \
3907 \t ext_bd_len_list[3] = 0x%x\n \
3908 \t ext_bd_len_list[4] = 0x%x\n",
3909 fp->rss_id, cqe->type, cqe->bitfields, cqe->seg_len,
3910 cqe->pars_flags.flags, cqe->vlan_tag,
3911 cqe->rss_hash, cqe->len_on_first_bd, cqe->placement_offset,
3912 cqe->tpa_agg_index, cqe->header_len,
3913 cqe->ext_bd_len_list[0], cqe->ext_bd_len_list[1],
3914 cqe->ext_bd_len_list[2], cqe->ext_bd_len_list[3],
3915 cqe->ext_bd_len_list[4]);
3916
3917 if (agg_index >= ETH_TPA_MAX_AGGS_NUM) {
3918 fp->err_rx_tpa_invalid_agg_num++;
3919 return;
3920 }
3921
3922 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
3923 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map, BUS_DMASYNC_POSTREAD);
3924 mp = sw_rx_data->data;
3925
3926 QL_DPRINT7(ha, "[rss_id = %d]: mp = %p \n ", fp->rss_id, mp);
3927
3928 if (mp == NULL) {
3929 QL_DPRINT7(ha, "[%d]: mp = NULL\n", fp->rss_id);
3930 fp->err_rx_mp_null++;
3931 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
3932
3933 return;
3934 }
3935
3936 if ((le16toh(cqe->pars_flags.flags)) & CQE_FLAGS_ERR) {
3937 QL_DPRINT7(ha, "[%d]: CQE in CONS = %u has error,"
3938 " flags = %x, dropping incoming packet\n", fp->rss_id,
3939 rxq->sw_rx_cons, le16toh(cqe->pars_flags.flags));
3940
3941 fp->err_rx_hw_errors++;
3942
3943 qlnx_reuse_rx_data(rxq);
3944
3945 QLNX_INC_IERRORS(ifp);
3946
3947 return;
3948 }
3949
3950 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
3951 QL_DPRINT7(ha, "[%d]: New buffer allocation failed,"
3952 " dropping incoming packet and reusing its buffer\n",
3953 fp->rss_id);
3954
3955 fp->err_rx_alloc_errors++;
3956 QLNX_INC_IQDROPS(ifp);
3957
3958 /*
3959 * Load the tpa mbuf into the rx ring and save the
3960 * posted mbuf
3961 */
3962
3963 map = sw_rx_data->map;
3964 addr = sw_rx_data->dma_addr;
3965
3966 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod];
3967
3968 sw_rx_data->data = rxq->tpa_info[agg_index].rx_buf.data;
3969 sw_rx_data->dma_addr = rxq->tpa_info[agg_index].rx_buf.dma_addr;
3970 sw_rx_data->map = rxq->tpa_info[agg_index].rx_buf.map;
3971
3972 rxq->tpa_info[agg_index].rx_buf.data = mp;
3973 rxq->tpa_info[agg_index].rx_buf.dma_addr = addr;
3974 rxq->tpa_info[agg_index].rx_buf.map = map;
3975
3976 rx_bd = (struct eth_rx_bd *)
3977 ecore_chain_produce(&rxq->rx_bd_ring);
3978
3979 rx_bd->addr.hi = htole32(U64_HI(sw_rx_data->dma_addr));
3980 rx_bd->addr.lo = htole32(U64_LO(sw_rx_data->dma_addr));
3981
3982 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
3983 BUS_DMASYNC_PREREAD);
3984
3985 rxq->sw_rx_prod = (rxq->sw_rx_prod + 1) & (RX_RING_SIZE - 1);
3986 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
3987
3988 ecore_chain_consume(&rxq->rx_bd_ring);
3989
3990 /* Now reuse any buffers posted in ext_bd_len_list */
3991 for (i = 0; i < ETH_TPA_CQE_START_LEN_LIST_SIZE; i++) {
3992 if (cqe->ext_bd_len_list[i] == 0)
3993 break;
3994
3995 qlnx_reuse_rx_data(rxq);
3996 }
3997
3998 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_ERROR;
3999 return;
4000 }
4001
4002 if (rxq->tpa_info[agg_index].agg_state != QLNX_AGG_STATE_NONE) {
4003 QL_DPRINT7(ha, "[%d]: invalid aggregation state,"
4004 " dropping incoming packet and reusing its buffer\n",
4005 fp->rss_id);
4006
4007 QLNX_INC_IQDROPS(ifp);
4008
4009 /* if we already have mbuf head in aggregation free it */
4010 if (rxq->tpa_info[agg_index].mpf) {
4011 m_freem(rxq->tpa_info[agg_index].mpf);
4012 rxq->tpa_info[agg_index].mpl = NULL;
4013 }
4014 rxq->tpa_info[agg_index].mpf = mp;
4015 rxq->tpa_info[agg_index].mpl = NULL;
4016
4017 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4018 ecore_chain_consume(&rxq->rx_bd_ring);
4019
4020 /* Now reuse any buffers posted in ext_bd_len_list */
4021 for (i = 0; i < ETH_TPA_CQE_START_LEN_LIST_SIZE; i++) {
4022 if (cqe->ext_bd_len_list[i] == 0)
4023 break;
4024
4025 qlnx_reuse_rx_data(rxq);
4026 }
4027 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_ERROR;
4028
4029 return;
4030 }
4031
4032 /*
4033 * first process the ext_bd_len_list
4034 * if this fails then we simply drop the packet
4035 */
4036 ecore_chain_consume(&rxq->rx_bd_ring);
4037 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4038
4039 for (i = 0; i < ETH_TPA_CQE_START_LEN_LIST_SIZE; i++) {
4040 QL_DPRINT7(ha, "[%d]: 4\n ", fp->rss_id);
4041
4042 if (cqe->ext_bd_len_list[i] == 0)
4043 break;
4044
4045 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4046 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4047 BUS_DMASYNC_POSTREAD);
4048
4049 mpc = sw_rx_data->data;
4050
4051 if (mpc == NULL) {
4052 QL_DPRINT7(ha, "[%d]: mpc = NULL\n", fp->rss_id);
4053 fp->err_rx_mp_null++;
4054 if (mpf != NULL)
4055 m_freem(mpf);
4056 mpf = mpl = NULL;
4057 rxq->tpa_info[agg_index].agg_state =
4058 QLNX_AGG_STATE_ERROR;
4059 ecore_chain_consume(&rxq->rx_bd_ring);
4060 rxq->sw_rx_cons =
4061 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4062 continue;
4063 }
4064
4065 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4066 QL_DPRINT7(ha, "[%d]: New buffer allocation failed,"
4067 " dropping incoming packet and reusing its"
4068 " buffer\n", fp->rss_id);
4069
4070 qlnx_reuse_rx_data(rxq);
4071
4072 if (mpf != NULL)
4073 m_freem(mpf);
4074 mpf = mpl = NULL;
4075
4076 rxq->tpa_info[agg_index].agg_state =
4077 QLNX_AGG_STATE_ERROR;
4078
4079 ecore_chain_consume(&rxq->rx_bd_ring);
4080 rxq->sw_rx_cons =
4081 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4082
4083 continue;
4084 }
4085
4086 mpc->m_flags &= ~M_PKTHDR;
4087 mpc->m_next = NULL;
4088 mpc->m_len = cqe->ext_bd_len_list[i];
4089
4090 if (mpf == NULL) {
4091 mpf = mpl = mpc;
4092 } else {
4093 mpl->m_len = ha->rx_buf_size;
4094 mpl->m_next = mpc;
4095 mpl = mpc;
4096 }
4097
4098 ecore_chain_consume(&rxq->rx_bd_ring);
4099 rxq->sw_rx_cons =
4100 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4101 }
4102
4103 if (rxq->tpa_info[agg_index].agg_state != QLNX_AGG_STATE_NONE) {
4104 QL_DPRINT7(ha, "[%d]: invalid aggregation state, dropping"
4105 " incoming packet and reusing its buffer\n",
4106 fp->rss_id);
4107
4108 QLNX_INC_IQDROPS(ifp);
4109
4110 rxq->tpa_info[agg_index].mpf = mp;
4111 rxq->tpa_info[agg_index].mpl = NULL;
4112
4113 return;
4114 }
4115
4116 rxq->tpa_info[agg_index].placement_offset = cqe->placement_offset;
4117
4118 if (mpf != NULL) {
4119 mp->m_len = ha->rx_buf_size;
4120 mp->m_next = mpf;
4121 rxq->tpa_info[agg_index].mpf = mp;
4122 rxq->tpa_info[agg_index].mpl = mpl;
4123 } else {
4124 mp->m_len = cqe->len_on_first_bd + cqe->placement_offset;
4125 rxq->tpa_info[agg_index].mpf = mp;
4126 rxq->tpa_info[agg_index].mpl = mp;
4127 mp->m_next = NULL;
4128 }
4129
4130 mp->m_flags |= M_PKTHDR;
4131
4132 /* assign packet to this interface interface */
4133 mp->m_pkthdr.rcvif = ifp;
4134
4135 /* assume no hardware checksum has complated */
4136 mp->m_pkthdr.csum_flags = 0;
4137
4138 //mp->m_pkthdr.flowid = fp->rss_id;
4139 mp->m_pkthdr.flowid = cqe->rss_hash;
4140
4141 hash_type = cqe->bitfields &
4142 (ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK <<
4143 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT);
4144
4145 switch (hash_type) {
4146 case RSS_HASH_TYPE_IPV4:
4147 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_IPV4);
4148 break;
4149
4150 case RSS_HASH_TYPE_TCP_IPV4:
4151 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_TCP_IPV4);
4152 break;
4153
4154 case RSS_HASH_TYPE_IPV6:
4155 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_IPV6);
4156 break;
4157
4158 case RSS_HASH_TYPE_TCP_IPV6:
4159 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_TCP_IPV6);
4160 break;
4161
4162 default:
4163 M_HASHTYPE_SET(mp, M_HASHTYPE_OPAQUE);
4164 break;
4165 }
4166
4167 mp->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED | CSUM_IP_VALID |
4168 CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
4169
4170 mp->m_pkthdr.csum_data = 0xFFFF;
4171
4172 if (CQE_HAS_VLAN(cqe->pars_flags.flags)) {
4173 mp->m_pkthdr.ether_vtag = le16toh(cqe->vlan_tag);
4174 mp->m_flags |= M_VLANTAG;
4175 }
4176
4177 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_START;
4178
4179 QL_DPRINT7(ha, "[%d]: 5\n\tagg_state = %d\n\t mpf = %p mpl = %p\n",
4180 fp->rss_id, rxq->tpa_info[agg_index].agg_state,
4181 rxq->tpa_info[agg_index].mpf, rxq->tpa_info[agg_index].mpl);
4182
4183 return;
4184 }
4185
4186 static void
qlnx_tpa_cont(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_rx_queue * rxq,struct eth_fast_path_rx_tpa_cont_cqe * cqe)4187 qlnx_tpa_cont(qlnx_host_t *ha, struct qlnx_fastpath *fp,
4188 struct qlnx_rx_queue *rxq,
4189 struct eth_fast_path_rx_tpa_cont_cqe *cqe)
4190 {
4191 struct sw_rx_data *sw_rx_data;
4192 int i;
4193 struct mbuf *mpf = NULL, *mpl = NULL, *mpc = NULL;
4194 struct mbuf *mp;
4195 uint32_t agg_index;
4196
4197 QL_DPRINT7(ha, "[%d]: enter\n \
4198 \t type = 0x%x\n \
4199 \t tpa_agg_index = 0x%x\n \
4200 \t len_list[0] = 0x%x\n \
4201 \t len_list[1] = 0x%x\n \
4202 \t len_list[2] = 0x%x\n \
4203 \t len_list[3] = 0x%x\n \
4204 \t len_list[4] = 0x%x\n \
4205 \t len_list[5] = 0x%x\n",
4206 fp->rss_id, cqe->type, cqe->tpa_agg_index,
4207 cqe->len_list[0], cqe->len_list[1], cqe->len_list[2],
4208 cqe->len_list[3], cqe->len_list[4], cqe->len_list[5]);
4209
4210 agg_index = cqe->tpa_agg_index;
4211
4212 if (agg_index >= ETH_TPA_MAX_AGGS_NUM) {
4213 QL_DPRINT7(ha, "[%d]: 0\n ", fp->rss_id);
4214 fp->err_rx_tpa_invalid_agg_num++;
4215 return;
4216 }
4217
4218 for (i = 0; i < ETH_TPA_CQE_CONT_LEN_LIST_SIZE; i++) {
4219 QL_DPRINT7(ha, "[%d]: 1\n ", fp->rss_id);
4220
4221 if (cqe->len_list[i] == 0)
4222 break;
4223
4224 if (rxq->tpa_info[agg_index].agg_state !=
4225 QLNX_AGG_STATE_START) {
4226 qlnx_reuse_rx_data(rxq);
4227 continue;
4228 }
4229
4230 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4231 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4232 BUS_DMASYNC_POSTREAD);
4233
4234 mpc = sw_rx_data->data;
4235
4236 if (mpc == NULL) {
4237 QL_DPRINT7(ha, "[%d]: mpc = NULL\n", fp->rss_id);
4238
4239 fp->err_rx_mp_null++;
4240 if (mpf != NULL)
4241 m_freem(mpf);
4242 mpf = mpl = NULL;
4243 rxq->tpa_info[agg_index].agg_state =
4244 QLNX_AGG_STATE_ERROR;
4245 ecore_chain_consume(&rxq->rx_bd_ring);
4246 rxq->sw_rx_cons =
4247 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4248 continue;
4249 }
4250
4251 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4252 QL_DPRINT7(ha, "[%d]: New buffer allocation failed,"
4253 " dropping incoming packet and reusing its"
4254 " buffer\n", fp->rss_id);
4255
4256 qlnx_reuse_rx_data(rxq);
4257
4258 if (mpf != NULL)
4259 m_freem(mpf);
4260 mpf = mpl = NULL;
4261
4262 rxq->tpa_info[agg_index].agg_state =
4263 QLNX_AGG_STATE_ERROR;
4264
4265 ecore_chain_consume(&rxq->rx_bd_ring);
4266 rxq->sw_rx_cons =
4267 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4268
4269 continue;
4270 }
4271
4272 mpc->m_flags &= ~M_PKTHDR;
4273 mpc->m_next = NULL;
4274 mpc->m_len = cqe->len_list[i];
4275
4276 if (mpf == NULL) {
4277 mpf = mpl = mpc;
4278 } else {
4279 mpl->m_len = ha->rx_buf_size;
4280 mpl->m_next = mpc;
4281 mpl = mpc;
4282 }
4283
4284 ecore_chain_consume(&rxq->rx_bd_ring);
4285 rxq->sw_rx_cons =
4286 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4287 }
4288
4289 QL_DPRINT7(ha, "[%d]: 2\n" "\tmpf = %p mpl = %p\n",
4290 fp->rss_id, mpf, mpl);
4291
4292 if (mpf != NULL) {
4293 mp = rxq->tpa_info[agg_index].mpl;
4294 mp->m_len = ha->rx_buf_size;
4295 mp->m_next = mpf;
4296 rxq->tpa_info[agg_index].mpl = mpl;
4297 }
4298
4299 return;
4300 }
4301
4302 static int
qlnx_tpa_end(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_rx_queue * rxq,struct eth_fast_path_rx_tpa_end_cqe * cqe)4303 qlnx_tpa_end(qlnx_host_t *ha, struct qlnx_fastpath *fp,
4304 struct qlnx_rx_queue *rxq,
4305 struct eth_fast_path_rx_tpa_end_cqe *cqe)
4306 {
4307 struct sw_rx_data *sw_rx_data;
4308 int i;
4309 struct mbuf *mpf = NULL, *mpl = NULL, *mpc = NULL;
4310 struct mbuf *mp;
4311 uint32_t agg_index;
4312 uint32_t len = 0;
4313 if_t ifp = ha->ifp;
4314
4315 QL_DPRINT7(ha, "[%d]: enter\n \
4316 \t type = 0x%x\n \
4317 \t tpa_agg_index = 0x%x\n \
4318 \t total_packet_len = 0x%x\n \
4319 \t num_of_bds = 0x%x\n \
4320 \t end_reason = 0x%x\n \
4321 \t num_of_coalesced_segs = 0x%x\n \
4322 \t ts_delta = 0x%x\n \
4323 \t len_list[0] = 0x%x\n \
4324 \t len_list[1] = 0x%x\n \
4325 \t len_list[2] = 0x%x\n \
4326 \t len_list[3] = 0x%x\n",
4327 fp->rss_id, cqe->type, cqe->tpa_agg_index,
4328 cqe->total_packet_len, cqe->num_of_bds,
4329 cqe->end_reason, cqe->num_of_coalesced_segs, cqe->ts_delta,
4330 cqe->len_list[0], cqe->len_list[1], cqe->len_list[2],
4331 cqe->len_list[3]);
4332
4333 agg_index = cqe->tpa_agg_index;
4334
4335 if (agg_index >= ETH_TPA_MAX_AGGS_NUM) {
4336 QL_DPRINT7(ha, "[%d]: 0\n ", fp->rss_id);
4337
4338 fp->err_rx_tpa_invalid_agg_num++;
4339 return (0);
4340 }
4341
4342 for (i = 0; i < ETH_TPA_CQE_END_LEN_LIST_SIZE; i++) {
4343 QL_DPRINT7(ha, "[%d]: 1\n ", fp->rss_id);
4344
4345 if (cqe->len_list[i] == 0)
4346 break;
4347
4348 if (rxq->tpa_info[agg_index].agg_state !=
4349 QLNX_AGG_STATE_START) {
4350 QL_DPRINT7(ha, "[%d]: 2\n ", fp->rss_id);
4351
4352 qlnx_reuse_rx_data(rxq);
4353 continue;
4354 }
4355
4356 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4357 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4358 BUS_DMASYNC_POSTREAD);
4359
4360 mpc = sw_rx_data->data;
4361
4362 if (mpc == NULL) {
4363 QL_DPRINT7(ha, "[%d]: mpc = NULL\n", fp->rss_id);
4364
4365 fp->err_rx_mp_null++;
4366 if (mpf != NULL)
4367 m_freem(mpf);
4368 mpf = mpl = NULL;
4369 rxq->tpa_info[agg_index].agg_state =
4370 QLNX_AGG_STATE_ERROR;
4371 ecore_chain_consume(&rxq->rx_bd_ring);
4372 rxq->sw_rx_cons =
4373 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4374 continue;
4375 }
4376
4377 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4378 QL_DPRINT7(ha, "[%d]: New buffer allocation failed,"
4379 " dropping incoming packet and reusing its"
4380 " buffer\n", fp->rss_id);
4381
4382 qlnx_reuse_rx_data(rxq);
4383
4384 if (mpf != NULL)
4385 m_freem(mpf);
4386 mpf = mpl = NULL;
4387
4388 rxq->tpa_info[agg_index].agg_state =
4389 QLNX_AGG_STATE_ERROR;
4390
4391 ecore_chain_consume(&rxq->rx_bd_ring);
4392 rxq->sw_rx_cons =
4393 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4394
4395 continue;
4396 }
4397
4398 mpc->m_flags &= ~M_PKTHDR;
4399 mpc->m_next = NULL;
4400 mpc->m_len = cqe->len_list[i];
4401
4402 if (mpf == NULL) {
4403 mpf = mpl = mpc;
4404 } else {
4405 mpl->m_len = ha->rx_buf_size;
4406 mpl->m_next = mpc;
4407 mpl = mpc;
4408 }
4409
4410 ecore_chain_consume(&rxq->rx_bd_ring);
4411 rxq->sw_rx_cons =
4412 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4413 }
4414
4415 QL_DPRINT7(ha, "[%d]: 5\n ", fp->rss_id);
4416
4417 if (mpf != NULL) {
4418 QL_DPRINT7(ha, "[%d]: 6\n ", fp->rss_id);
4419
4420 mp = rxq->tpa_info[agg_index].mpl;
4421 mp->m_len = ha->rx_buf_size;
4422 mp->m_next = mpf;
4423 }
4424
4425 if (rxq->tpa_info[agg_index].agg_state != QLNX_AGG_STATE_START) {
4426 QL_DPRINT7(ha, "[%d]: 7\n ", fp->rss_id);
4427
4428 if (rxq->tpa_info[agg_index].mpf != NULL)
4429 m_freem(rxq->tpa_info[agg_index].mpf);
4430 rxq->tpa_info[agg_index].mpf = NULL;
4431 rxq->tpa_info[agg_index].mpl = NULL;
4432 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_NONE;
4433 return (0);
4434 }
4435
4436 mp = rxq->tpa_info[agg_index].mpf;
4437 m_adj(mp, rxq->tpa_info[agg_index].placement_offset);
4438 mp->m_pkthdr.len = cqe->total_packet_len;
4439
4440 if (mp->m_next == NULL)
4441 mp->m_len = mp->m_pkthdr.len;
4442 else {
4443 /* compute the total packet length */
4444 mpf = mp;
4445 while (mpf != NULL) {
4446 len += mpf->m_len;
4447 mpf = mpf->m_next;
4448 }
4449
4450 if (cqe->total_packet_len > len) {
4451 mpl = rxq->tpa_info[agg_index].mpl;
4452 mpl->m_len += (cqe->total_packet_len - len);
4453 }
4454 }
4455
4456 QLNX_INC_IPACKETS(ifp);
4457 QLNX_INC_IBYTES(ifp, (cqe->total_packet_len));
4458
4459 QL_DPRINT7(ha, "[%d]: 8 csum_data = 0x%x csum_flags = 0x%" PRIu64 "\n \
4460 m_len = 0x%x m_pkthdr_len = 0x%x\n",
4461 fp->rss_id, mp->m_pkthdr.csum_data,
4462 (uint64_t)mp->m_pkthdr.csum_flags, mp->m_len, mp->m_pkthdr.len);
4463
4464 if_input(ifp, mp);
4465
4466 rxq->tpa_info[agg_index].mpf = NULL;
4467 rxq->tpa_info[agg_index].mpl = NULL;
4468 rxq->tpa_info[agg_index].agg_state = QLNX_AGG_STATE_NONE;
4469
4470 return (cqe->num_of_coalesced_segs);
4471 }
4472
4473 static int
qlnx_rx_int(qlnx_host_t * ha,struct qlnx_fastpath * fp,int budget,int lro_enable)4474 qlnx_rx_int(qlnx_host_t *ha, struct qlnx_fastpath *fp, int budget,
4475 int lro_enable)
4476 {
4477 uint16_t hw_comp_cons, sw_comp_cons;
4478 int rx_pkt = 0;
4479 struct qlnx_rx_queue *rxq = fp->rxq;
4480 if_t ifp = ha->ifp;
4481 struct ecore_dev *cdev = &ha->cdev;
4482 struct ecore_hwfn *p_hwfn;
4483
4484 #ifdef QLNX_SOFT_LRO
4485 struct lro_ctrl *lro;
4486
4487 lro = &rxq->lro;
4488 #endif /* #ifdef QLNX_SOFT_LRO */
4489
4490 hw_comp_cons = le16toh(*rxq->hw_cons_ptr);
4491 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
4492
4493 p_hwfn = &ha->cdev.hwfns[(fp->rss_id % cdev->num_hwfns)];
4494
4495 /* Memory barrier to prevent the CPU from doing speculative reads of CQE
4496 * / BD in the while-loop before reading hw_comp_cons. If the CQE is
4497 * read before it is written by FW, then FW writes CQE and SB, and then
4498 * the CPU reads the hw_comp_cons, it will use an old CQE.
4499 */
4500
4501 /* Loop to complete all indicated BDs */
4502 while (sw_comp_cons != hw_comp_cons) {
4503 union eth_rx_cqe *cqe;
4504 struct eth_fast_path_rx_reg_cqe *fp_cqe;
4505 struct sw_rx_data *sw_rx_data;
4506 register struct mbuf *mp;
4507 enum eth_rx_cqe_type cqe_type;
4508 uint16_t len, pad, len_on_first_bd;
4509 uint8_t *data;
4510 uint8_t hash_type;
4511
4512 /* Get the CQE from the completion ring */
4513 cqe = (union eth_rx_cqe *)
4514 ecore_chain_consume(&rxq->rx_comp_ring);
4515 cqe_type = cqe->fast_path_regular.type;
4516
4517 if (cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH) {
4518 QL_DPRINT3(ha, "Got a slowath CQE\n");
4519
4520 ecore_eth_cqe_completion(p_hwfn,
4521 (struct eth_slow_path_rx_cqe *)cqe);
4522 goto next_cqe;
4523 }
4524
4525 if (cqe_type != ETH_RX_CQE_TYPE_REGULAR) {
4526 switch (cqe_type) {
4527 case ETH_RX_CQE_TYPE_TPA_START:
4528 qlnx_tpa_start(ha, fp, rxq,
4529 &cqe->fast_path_tpa_start);
4530 fp->tpa_start++;
4531 break;
4532
4533 case ETH_RX_CQE_TYPE_TPA_CONT:
4534 qlnx_tpa_cont(ha, fp, rxq,
4535 &cqe->fast_path_tpa_cont);
4536 fp->tpa_cont++;
4537 break;
4538
4539 case ETH_RX_CQE_TYPE_TPA_END:
4540 rx_pkt += qlnx_tpa_end(ha, fp, rxq,
4541 &cqe->fast_path_tpa_end);
4542 fp->tpa_end++;
4543 break;
4544
4545 default:
4546 break;
4547 }
4548
4549 goto next_cqe;
4550 }
4551
4552 /* Get the data from the SW ring */
4553 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_cons];
4554 mp = sw_rx_data->data;
4555
4556 if (mp == NULL) {
4557 QL_DPRINT1(ha, "mp = NULL\n");
4558 fp->err_rx_mp_null++;
4559 rxq->sw_rx_cons =
4560 (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4561 goto next_cqe;
4562 }
4563 bus_dmamap_sync(ha->rx_tag, sw_rx_data->map,
4564 BUS_DMASYNC_POSTREAD);
4565
4566 /* non GRO */
4567 fp_cqe = &cqe->fast_path_regular;/* MK CR TPA check assembly */
4568 len = le16toh(fp_cqe->pkt_len);
4569 pad = fp_cqe->placement_offset;
4570 #if 0
4571 QL_DPRINT3(ha, "CQE type = %x, flags = %x, vlan = %x,"
4572 " len %u, parsing flags = %d pad = %d\n",
4573 cqe_type, fp_cqe->bitfields,
4574 le16toh(fp_cqe->vlan_tag),
4575 len, le16toh(fp_cqe->pars_flags.flags), pad);
4576 #endif
4577 data = mtod(mp, uint8_t *);
4578 data = data + pad;
4579
4580 if (0)
4581 qlnx_dump_buf8(ha, __func__, data, len);
4582
4583 /* For every Rx BD consumed, we allocate a new BD so the BD ring
4584 * is always with a fixed size. If allocation fails, we take the
4585 * consumed BD and return it to the ring in the PROD position.
4586 * The packet that was received on that BD will be dropped (and
4587 * not passed to the upper stack).
4588 */
4589 /* If this is an error packet then drop it */
4590 if ((le16toh(cqe->fast_path_regular.pars_flags.flags)) &
4591 CQE_FLAGS_ERR) {
4592 QL_DPRINT1(ha, "CQE in CONS = %u has error, flags = %x,"
4593 " dropping incoming packet\n", sw_comp_cons,
4594 le16toh(cqe->fast_path_regular.pars_flags.flags));
4595 fp->err_rx_hw_errors++;
4596
4597 qlnx_reuse_rx_data(rxq);
4598
4599 QLNX_INC_IERRORS(ifp);
4600
4601 goto next_cqe;
4602 }
4603
4604 if (qlnx_alloc_rx_buffer(ha, rxq) != 0) {
4605 QL_DPRINT1(ha, "New buffer allocation failed, dropping"
4606 " incoming packet and reusing its buffer\n");
4607 qlnx_reuse_rx_data(rxq);
4608
4609 fp->err_rx_alloc_errors++;
4610
4611 QLNX_INC_IQDROPS(ifp);
4612
4613 goto next_cqe;
4614 }
4615
4616 ecore_chain_consume(&rxq->rx_bd_ring);
4617
4618 len_on_first_bd = fp_cqe->len_on_first_bd;
4619 m_adj(mp, pad);
4620 mp->m_pkthdr.len = len;
4621
4622 if ((len > 60 ) && (len > len_on_first_bd)) {
4623 mp->m_len = len_on_first_bd;
4624
4625 if (qlnx_rx_jumbo_chain(ha, fp, mp,
4626 (len - len_on_first_bd)) != 0) {
4627 m_freem(mp);
4628
4629 QLNX_INC_IQDROPS(ifp);
4630
4631 goto next_cqe;
4632 }
4633
4634 } else if (len_on_first_bd < len) {
4635 fp->err_rx_jumbo_chain_pkts++;
4636 } else {
4637 mp->m_len = len;
4638 }
4639
4640 mp->m_flags |= M_PKTHDR;
4641
4642 /* assign packet to this interface interface */
4643 mp->m_pkthdr.rcvif = ifp;
4644
4645 /* assume no hardware checksum has complated */
4646 mp->m_pkthdr.csum_flags = 0;
4647
4648 mp->m_pkthdr.flowid = fp_cqe->rss_hash;
4649
4650 hash_type = fp_cqe->bitfields &
4651 (ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK <<
4652 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT);
4653
4654 switch (hash_type) {
4655 case RSS_HASH_TYPE_IPV4:
4656 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_IPV4);
4657 break;
4658
4659 case RSS_HASH_TYPE_TCP_IPV4:
4660 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_TCP_IPV4);
4661 break;
4662
4663 case RSS_HASH_TYPE_IPV6:
4664 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_IPV6);
4665 break;
4666
4667 case RSS_HASH_TYPE_TCP_IPV6:
4668 M_HASHTYPE_SET(mp, M_HASHTYPE_RSS_TCP_IPV6);
4669 break;
4670
4671 default:
4672 M_HASHTYPE_SET(mp, M_HASHTYPE_OPAQUE);
4673 break;
4674 }
4675
4676 if (CQE_L3_PACKET(fp_cqe->pars_flags.flags)) {
4677 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4678 }
4679
4680 if (!(CQE_IP_HDR_ERR(fp_cqe->pars_flags.flags))) {
4681 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4682 }
4683
4684 if (CQE_L4_HAS_CSUM(fp_cqe->pars_flags.flags)) {
4685 mp->m_pkthdr.csum_data = 0xFFFF;
4686 mp->m_pkthdr.csum_flags |=
4687 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
4688 }
4689
4690 if (CQE_HAS_VLAN(fp_cqe->pars_flags.flags)) {
4691 mp->m_pkthdr.ether_vtag = le16toh(fp_cqe->vlan_tag);
4692 mp->m_flags |= M_VLANTAG;
4693 }
4694
4695 QLNX_INC_IPACKETS(ifp);
4696 QLNX_INC_IBYTES(ifp, len);
4697
4698 #ifdef QLNX_SOFT_LRO
4699 if (lro_enable)
4700 tcp_lro_queue_mbuf(lro, mp);
4701 else
4702 if_input(ifp, mp);
4703 #else
4704
4705 if_input(ifp, mp);
4706
4707 #endif /* #ifdef QLNX_SOFT_LRO */
4708
4709 rx_pkt++;
4710
4711 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
4712
4713 next_cqe: /* don't consume bd rx buffer */
4714 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
4715 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
4716
4717 /* CR TPA - revisit how to handle budget in TPA perhaps
4718 increase on "end" */
4719 if (rx_pkt == budget)
4720 break;
4721 } /* repeat while sw_comp_cons != hw_comp_cons... */
4722
4723 /* Update producers */
4724 qlnx_update_rx_prod(p_hwfn, rxq);
4725
4726 return rx_pkt;
4727 }
4728
4729 /*
4730 * fast path interrupt
4731 */
4732
4733 static void
qlnx_fp_isr(void * arg)4734 qlnx_fp_isr(void *arg)
4735 {
4736 qlnx_ivec_t *ivec = arg;
4737 qlnx_host_t *ha;
4738 struct qlnx_fastpath *fp = NULL;
4739 int idx;
4740
4741 ha = ivec->ha;
4742
4743 if (ha->state != QLNX_STATE_OPEN) {
4744 return;
4745 }
4746
4747 idx = ivec->rss_idx;
4748
4749 if ((idx = ivec->rss_idx) >= ha->num_rss) {
4750 QL_DPRINT1(ha, "illegal interrupt[%d]\n", idx);
4751 ha->err_illegal_intr++;
4752 return;
4753 }
4754 fp = &ha->fp_array[idx];
4755
4756 if (fp == NULL) {
4757 ha->err_fp_null++;
4758 } else {
4759 int rx_int = 0;
4760 #ifdef QLNX_SOFT_LRO
4761 int total_rx_count = 0;
4762 #endif
4763 int lro_enable, tc;
4764 struct qlnx_tx_queue *txq;
4765 uint16_t elem_left;
4766
4767 lro_enable = if_getcapenable(ha->ifp) & IFCAP_LRO;
4768
4769 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
4770
4771 do {
4772 for (tc = 0; tc < ha->num_tc; tc++) {
4773 txq = fp->txq[tc];
4774
4775 if((int)(elem_left =
4776 ecore_chain_get_elem_left(&txq->tx_pbl)) <
4777 QLNX_TX_ELEM_THRESH) {
4778 if (mtx_trylock(&fp->tx_mtx)) {
4779 #ifdef QLNX_TRACE_PERF_DATA
4780 tx_compl = fp->tx_pkts_completed;
4781 #endif
4782
4783 qlnx_tx_int(ha, fp, fp->txq[tc]);
4784 #ifdef QLNX_TRACE_PERF_DATA
4785 fp->tx_pkts_compl_intr +=
4786 (fp->tx_pkts_completed - tx_compl);
4787 if ((fp->tx_pkts_completed - tx_compl) <= 32)
4788 fp->tx_comInt[0]++;
4789 else if (((fp->tx_pkts_completed - tx_compl) > 32) &&
4790 ((fp->tx_pkts_completed - tx_compl) <= 64))
4791 fp->tx_comInt[1]++;
4792 else if(((fp->tx_pkts_completed - tx_compl) > 64) &&
4793 ((fp->tx_pkts_completed - tx_compl) <= 128))
4794 fp->tx_comInt[2]++;
4795 else if(((fp->tx_pkts_completed - tx_compl) > 128))
4796 fp->tx_comInt[3]++;
4797 #endif
4798 mtx_unlock(&fp->tx_mtx);
4799 }
4800 }
4801 }
4802
4803 rx_int = qlnx_rx_int(ha, fp, ha->rx_pkt_threshold,
4804 lro_enable);
4805
4806 if (rx_int) {
4807 fp->rx_pkts += rx_int;
4808 #ifdef QLNX_SOFT_LRO
4809 total_rx_count += rx_int;
4810 #endif
4811 }
4812
4813 } while (rx_int);
4814
4815 #ifdef QLNX_SOFT_LRO
4816 {
4817 struct lro_ctrl *lro;
4818
4819 lro = &fp->rxq->lro;
4820
4821 if (lro_enable && total_rx_count) {
4822
4823 #ifdef QLNX_TRACE_LRO_CNT
4824 if (lro->lro_mbuf_count & ~1023)
4825 fp->lro_cnt_1024++;
4826 else if (lro->lro_mbuf_count & ~511)
4827 fp->lro_cnt_512++;
4828 else if (lro->lro_mbuf_count & ~255)
4829 fp->lro_cnt_256++;
4830 else if (lro->lro_mbuf_count & ~127)
4831 fp->lro_cnt_128++;
4832 else if (lro->lro_mbuf_count & ~63)
4833 fp->lro_cnt_64++;
4834 #endif /* #ifdef QLNX_TRACE_LRO_CNT */
4835
4836 tcp_lro_flush_all(lro);
4837 }
4838 }
4839 #endif /* #ifdef QLNX_SOFT_LRO */
4840
4841 ecore_sb_update_sb_idx(fp->sb_info);
4842 rmb();
4843 ecore_sb_ack(fp->sb_info, IGU_INT_ENABLE, 1);
4844 }
4845
4846 return;
4847 }
4848
4849 /*
4850 * slow path interrupt processing function
4851 * can be invoked in polled mode or in interrupt mode via taskqueue.
4852 */
4853 void
qlnx_sp_isr(void * arg)4854 qlnx_sp_isr(void *arg)
4855 {
4856 struct ecore_hwfn *p_hwfn;
4857 qlnx_host_t *ha;
4858
4859 p_hwfn = arg;
4860
4861 ha = (qlnx_host_t *)p_hwfn->p_dev;
4862
4863 ha->sp_interrupts++;
4864
4865 QL_DPRINT2(ha, "enter\n");
4866
4867 ecore_int_sp_dpc(p_hwfn);
4868
4869 QL_DPRINT2(ha, "exit\n");
4870
4871 return;
4872 }
4873
4874 /*****************************************************************************
4875 * Support Functions for DMA'able Memory
4876 *****************************************************************************/
4877
4878 static void
qlnx_dmamap_callback(void * arg,bus_dma_segment_t * segs,int nsegs,int error)4879 qlnx_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
4880 {
4881 *((bus_addr_t *)arg) = 0;
4882
4883 if (error) {
4884 printf("%s: bus_dmamap_load failed (%d)\n", __func__, error);
4885 return;
4886 }
4887
4888 *((bus_addr_t *)arg) = segs[0].ds_addr;
4889
4890 return;
4891 }
4892
4893 static int
qlnx_alloc_dmabuf(qlnx_host_t * ha,qlnx_dma_t * dma_buf)4894 qlnx_alloc_dmabuf(qlnx_host_t *ha, qlnx_dma_t *dma_buf)
4895 {
4896 int ret = 0;
4897 bus_addr_t b_addr;
4898
4899 ret = bus_dma_tag_create(
4900 ha->parent_tag,/* parent */
4901 dma_buf->alignment,
4902 ((bus_size_t)(1ULL << 32)),/* boundary */
4903 BUS_SPACE_MAXADDR, /* lowaddr */
4904 BUS_SPACE_MAXADDR, /* highaddr */
4905 NULL, NULL, /* filter, filterarg */
4906 dma_buf->size, /* maxsize */
4907 1, /* nsegments */
4908 dma_buf->size, /* maxsegsize */
4909 0, /* flags */
4910 NULL, NULL, /* lockfunc, lockarg */
4911 &dma_buf->dma_tag);
4912
4913 if (ret) {
4914 QL_DPRINT1(ha, "could not create dma tag\n");
4915 goto qlnx_alloc_dmabuf_exit;
4916 }
4917 ret = bus_dmamem_alloc(dma_buf->dma_tag,
4918 (void **)&dma_buf->dma_b,
4919 (BUS_DMA_ZERO | BUS_DMA_COHERENT | BUS_DMA_NOWAIT),
4920 &dma_buf->dma_map);
4921 if (ret) {
4922 bus_dma_tag_destroy(dma_buf->dma_tag);
4923 QL_DPRINT1(ha, "bus_dmamem_alloc failed\n");
4924 goto qlnx_alloc_dmabuf_exit;
4925 }
4926
4927 ret = bus_dmamap_load(dma_buf->dma_tag,
4928 dma_buf->dma_map,
4929 dma_buf->dma_b,
4930 dma_buf->size,
4931 qlnx_dmamap_callback,
4932 &b_addr, BUS_DMA_NOWAIT);
4933
4934 if (ret || !b_addr) {
4935 bus_dma_tag_destroy(dma_buf->dma_tag);
4936 bus_dmamem_free(dma_buf->dma_tag, dma_buf->dma_b,
4937 dma_buf->dma_map);
4938 ret = -1;
4939 goto qlnx_alloc_dmabuf_exit;
4940 }
4941
4942 dma_buf->dma_addr = b_addr;
4943
4944 qlnx_alloc_dmabuf_exit:
4945
4946 return ret;
4947 }
4948
4949 static void
qlnx_free_dmabuf(qlnx_host_t * ha,qlnx_dma_t * dma_buf)4950 qlnx_free_dmabuf(qlnx_host_t *ha, qlnx_dma_t *dma_buf)
4951 {
4952 bus_dmamap_unload(dma_buf->dma_tag, dma_buf->dma_map);
4953 bus_dmamem_free(dma_buf->dma_tag, dma_buf->dma_b, dma_buf->dma_map);
4954 bus_dma_tag_destroy(dma_buf->dma_tag);
4955 return;
4956 }
4957
4958 void *
qlnx_dma_alloc_coherent(void * ecore_dev,bus_addr_t * phys,uint32_t size)4959 qlnx_dma_alloc_coherent(void *ecore_dev, bus_addr_t *phys, uint32_t size)
4960 {
4961 qlnx_dma_t dma_buf;
4962 qlnx_dma_t *dma_p;
4963 qlnx_host_t *ha __unused;
4964
4965 ha = (qlnx_host_t *)ecore_dev;
4966
4967 size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
4968
4969 memset(&dma_buf, 0, sizeof (qlnx_dma_t));
4970
4971 dma_buf.size = size + PAGE_SIZE;
4972 dma_buf.alignment = 8;
4973
4974 if (qlnx_alloc_dmabuf((qlnx_host_t *)ecore_dev, &dma_buf) != 0)
4975 return (NULL);
4976 bzero((uint8_t *)dma_buf.dma_b, dma_buf.size);
4977
4978 *phys = dma_buf.dma_addr;
4979
4980 dma_p = (qlnx_dma_t *)((uint8_t *)dma_buf.dma_b + size);
4981
4982 memcpy(dma_p, &dma_buf, sizeof(qlnx_dma_t));
4983
4984 QL_DPRINT5(ha, "[%p %p %p %p 0x%08x ]\n",
4985 (void *)dma_buf.dma_map, (void *)dma_buf.dma_tag,
4986 dma_buf.dma_b, (void *)dma_buf.dma_addr, size);
4987
4988 return (dma_buf.dma_b);
4989 }
4990
4991 void
qlnx_dma_free_coherent(void * ecore_dev,void * v_addr,bus_addr_t phys,uint32_t size)4992 qlnx_dma_free_coherent(void *ecore_dev, void *v_addr, bus_addr_t phys,
4993 uint32_t size)
4994 {
4995 qlnx_dma_t dma_buf, *dma_p;
4996 qlnx_host_t *ha;
4997
4998 ha = (qlnx_host_t *)ecore_dev;
4999
5000 if (v_addr == NULL)
5001 return;
5002
5003 size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
5004
5005 dma_p = (qlnx_dma_t *)((uint8_t *)v_addr + size);
5006
5007 QL_DPRINT5(ha, "[%p %p %p %p 0x%08x ]\n",
5008 (void *)dma_p->dma_map, (void *)dma_p->dma_tag,
5009 dma_p->dma_b, (void *)dma_p->dma_addr, size);
5010
5011 dma_buf = *dma_p;
5012
5013 if (!ha->qlnxr_debug)
5014 qlnx_free_dmabuf((qlnx_host_t *)ecore_dev, &dma_buf);
5015 return;
5016 }
5017
5018 static int
qlnx_alloc_parent_dma_tag(qlnx_host_t * ha)5019 qlnx_alloc_parent_dma_tag(qlnx_host_t *ha)
5020 {
5021 int ret;
5022 device_t dev;
5023
5024 dev = ha->pci_dev;
5025
5026 /*
5027 * Allocate parent DMA Tag
5028 */
5029 ret = bus_dma_tag_create(
5030 bus_get_dma_tag(dev), /* parent */
5031 1,((bus_size_t)(1ULL << 32)),/* alignment, boundary */
5032 BUS_SPACE_MAXADDR, /* lowaddr */
5033 BUS_SPACE_MAXADDR, /* highaddr */
5034 NULL, NULL, /* filter, filterarg */
5035 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
5036 0, /* nsegments */
5037 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
5038 0, /* flags */
5039 NULL, NULL, /* lockfunc, lockarg */
5040 &ha->parent_tag);
5041
5042 if (ret) {
5043 QL_DPRINT1(ha, "could not create parent dma tag\n");
5044 return (-1);
5045 }
5046
5047 ha->flags.parent_tag = 1;
5048
5049 return (0);
5050 }
5051
5052 static void
qlnx_free_parent_dma_tag(qlnx_host_t * ha)5053 qlnx_free_parent_dma_tag(qlnx_host_t *ha)
5054 {
5055 if (ha->parent_tag != NULL) {
5056 bus_dma_tag_destroy(ha->parent_tag);
5057 ha->parent_tag = NULL;
5058 }
5059 return;
5060 }
5061
5062 static int
qlnx_alloc_tx_dma_tag(qlnx_host_t * ha)5063 qlnx_alloc_tx_dma_tag(qlnx_host_t *ha)
5064 {
5065 if (bus_dma_tag_create(NULL, /* parent */
5066 1, 0, /* alignment, bounds */
5067 BUS_SPACE_MAXADDR, /* lowaddr */
5068 BUS_SPACE_MAXADDR, /* highaddr */
5069 NULL, NULL, /* filter, filterarg */
5070 QLNX_MAX_TSO_FRAME_SIZE, /* maxsize */
5071 QLNX_MAX_SEGMENTS, /* nsegments */
5072 QLNX_MAX_TX_MBUF_SIZE, /* maxsegsize */
5073 0, /* flags */
5074 NULL, /* lockfunc */
5075 NULL, /* lockfuncarg */
5076 &ha->tx_tag)) {
5077 QL_DPRINT1(ha, "tx_tag alloc failed\n");
5078 return (-1);
5079 }
5080
5081 return (0);
5082 }
5083
5084 static void
qlnx_free_tx_dma_tag(qlnx_host_t * ha)5085 qlnx_free_tx_dma_tag(qlnx_host_t *ha)
5086 {
5087 if (ha->tx_tag != NULL) {
5088 bus_dma_tag_destroy(ha->tx_tag);
5089 ha->tx_tag = NULL;
5090 }
5091 return;
5092 }
5093
5094 static int
qlnx_alloc_rx_dma_tag(qlnx_host_t * ha)5095 qlnx_alloc_rx_dma_tag(qlnx_host_t *ha)
5096 {
5097 if (bus_dma_tag_create(NULL, /* parent */
5098 1, 0, /* alignment, bounds */
5099 BUS_SPACE_MAXADDR, /* lowaddr */
5100 BUS_SPACE_MAXADDR, /* highaddr */
5101 NULL, NULL, /* filter, filterarg */
5102 MJUM9BYTES, /* maxsize */
5103 1, /* nsegments */
5104 MJUM9BYTES, /* maxsegsize */
5105 0, /* flags */
5106 NULL, /* lockfunc */
5107 NULL, /* lockfuncarg */
5108 &ha->rx_tag)) {
5109 QL_DPRINT1(ha, " rx_tag alloc failed\n");
5110
5111 return (-1);
5112 }
5113 return (0);
5114 }
5115
5116 static void
qlnx_free_rx_dma_tag(qlnx_host_t * ha)5117 qlnx_free_rx_dma_tag(qlnx_host_t *ha)
5118 {
5119 if (ha->rx_tag != NULL) {
5120 bus_dma_tag_destroy(ha->rx_tag);
5121 ha->rx_tag = NULL;
5122 }
5123 return;
5124 }
5125
5126 /*********************************
5127 * Exported functions
5128 *********************************/
5129 uint32_t
qlnx_pci_bus_get_bar_size(void * ecore_dev,uint8_t bar_id)5130 qlnx_pci_bus_get_bar_size(void *ecore_dev, uint8_t bar_id)
5131 {
5132 uint32_t bar_size;
5133
5134 bar_id = bar_id * 2;
5135
5136 bar_size = bus_get_resource_count(((qlnx_host_t *)ecore_dev)->pci_dev,
5137 SYS_RES_MEMORY,
5138 PCIR_BAR(bar_id));
5139
5140 return (bar_size);
5141 }
5142
5143 uint32_t
qlnx_pci_read_config_byte(void * ecore_dev,uint32_t pci_reg,uint8_t * reg_value)5144 qlnx_pci_read_config_byte(void *ecore_dev, uint32_t pci_reg, uint8_t *reg_value)
5145 {
5146 *reg_value = pci_read_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5147 pci_reg, 1);
5148 return 0;
5149 }
5150
5151 uint32_t
qlnx_pci_read_config_word(void * ecore_dev,uint32_t pci_reg,uint16_t * reg_value)5152 qlnx_pci_read_config_word(void *ecore_dev, uint32_t pci_reg,
5153 uint16_t *reg_value)
5154 {
5155 *reg_value = pci_read_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5156 pci_reg, 2);
5157 return 0;
5158 }
5159
5160 uint32_t
qlnx_pci_read_config_dword(void * ecore_dev,uint32_t pci_reg,uint32_t * reg_value)5161 qlnx_pci_read_config_dword(void *ecore_dev, uint32_t pci_reg,
5162 uint32_t *reg_value)
5163 {
5164 *reg_value = pci_read_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5165 pci_reg, 4);
5166 return 0;
5167 }
5168
5169 void
qlnx_pci_write_config_byte(void * ecore_dev,uint32_t pci_reg,uint8_t reg_value)5170 qlnx_pci_write_config_byte(void *ecore_dev, uint32_t pci_reg, uint8_t reg_value)
5171 {
5172 pci_write_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5173 pci_reg, reg_value, 1);
5174 return;
5175 }
5176
5177 void
qlnx_pci_write_config_word(void * ecore_dev,uint32_t pci_reg,uint16_t reg_value)5178 qlnx_pci_write_config_word(void *ecore_dev, uint32_t pci_reg,
5179 uint16_t reg_value)
5180 {
5181 pci_write_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5182 pci_reg, reg_value, 2);
5183 return;
5184 }
5185
5186 void
qlnx_pci_write_config_dword(void * ecore_dev,uint32_t pci_reg,uint32_t reg_value)5187 qlnx_pci_write_config_dword(void *ecore_dev, uint32_t pci_reg,
5188 uint32_t reg_value)
5189 {
5190 pci_write_config(((qlnx_host_t *)ecore_dev)->pci_dev,
5191 pci_reg, reg_value, 4);
5192 return;
5193 }
5194
5195 int
qlnx_pci_find_capability(void * ecore_dev,int cap)5196 qlnx_pci_find_capability(void *ecore_dev, int cap)
5197 {
5198 int reg;
5199 qlnx_host_t *ha;
5200
5201 ha = ecore_dev;
5202
5203 if (pci_find_cap(ha->pci_dev, PCIY_EXPRESS, ®) == 0)
5204 return reg;
5205 else {
5206 QL_DPRINT1(ha, "failed\n");
5207 return 0;
5208 }
5209 }
5210
5211 int
qlnx_pci_find_ext_capability(void * ecore_dev,int ext_cap)5212 qlnx_pci_find_ext_capability(void *ecore_dev, int ext_cap)
5213 {
5214 int reg;
5215 qlnx_host_t *ha;
5216
5217 ha = ecore_dev;
5218
5219 if (pci_find_extcap(ha->pci_dev, ext_cap, ®) == 0)
5220 return reg;
5221 else {
5222 QL_DPRINT1(ha, "failed\n");
5223 return 0;
5224 }
5225 }
5226
5227 uint32_t
qlnx_reg_rd32(void * hwfn,uint32_t reg_addr)5228 qlnx_reg_rd32(void *hwfn, uint32_t reg_addr)
5229 {
5230 uint32_t data32;
5231 struct ecore_hwfn *p_hwfn;
5232
5233 p_hwfn = hwfn;
5234
5235 data32 = bus_read_4(((qlnx_host_t *)p_hwfn->p_dev)->pci_reg, \
5236 (bus_size_t)(p_hwfn->reg_offset + reg_addr));
5237
5238 return (data32);
5239 }
5240
5241 void
qlnx_reg_wr32(void * hwfn,uint32_t reg_addr,uint32_t value)5242 qlnx_reg_wr32(void *hwfn, uint32_t reg_addr, uint32_t value)
5243 {
5244 struct ecore_hwfn *p_hwfn = hwfn;
5245
5246 bus_write_4(((qlnx_host_t *)p_hwfn->p_dev)->pci_reg, \
5247 (bus_size_t)(p_hwfn->reg_offset + reg_addr), value);
5248
5249 return;
5250 }
5251
5252 void
qlnx_reg_wr16(void * hwfn,uint32_t reg_addr,uint16_t value)5253 qlnx_reg_wr16(void *hwfn, uint32_t reg_addr, uint16_t value)
5254 {
5255 struct ecore_hwfn *p_hwfn = hwfn;
5256
5257 bus_write_2(((qlnx_host_t *)p_hwfn->p_dev)->pci_reg, \
5258 (bus_size_t)(p_hwfn->reg_offset + reg_addr), value);
5259 return;
5260 }
5261
5262 void
qlnx_dbell_wr32_db(void * hwfn,void * reg_addr,uint32_t value)5263 qlnx_dbell_wr32_db(void *hwfn, void *reg_addr, uint32_t value)
5264 {
5265 struct ecore_dev *cdev;
5266 struct ecore_hwfn *p_hwfn;
5267 uint32_t offset;
5268
5269 p_hwfn = hwfn;
5270
5271 cdev = p_hwfn->p_dev;
5272
5273 offset = (uint32_t)((uint8_t *)reg_addr - (uint8_t *)(p_hwfn->doorbells));
5274 bus_write_4(((qlnx_host_t *)cdev)->pci_dbells, offset, value);
5275
5276 return;
5277 }
5278
5279 void
qlnx_dbell_wr32(void * hwfn,uint32_t reg_addr,uint32_t value)5280 qlnx_dbell_wr32(void *hwfn, uint32_t reg_addr, uint32_t value)
5281 {
5282 struct ecore_hwfn *p_hwfn = hwfn;
5283
5284 bus_write_4(((qlnx_host_t *)p_hwfn->p_dev)->pci_dbells, \
5285 (bus_size_t)(p_hwfn->db_offset + reg_addr), value);
5286
5287 return;
5288 }
5289
5290 uint32_t
qlnx_direct_reg_rd32(void * p_hwfn,uint32_t * reg_addr)5291 qlnx_direct_reg_rd32(void *p_hwfn, uint32_t *reg_addr)
5292 {
5293 uint32_t data32;
5294 bus_size_t offset;
5295 struct ecore_dev *cdev;
5296
5297 cdev = ((struct ecore_hwfn *)p_hwfn)->p_dev;
5298 offset = (bus_size_t)((uint8_t *)reg_addr - (uint8_t *)(cdev->regview));
5299
5300 data32 = bus_read_4(((qlnx_host_t *)cdev)->pci_reg, offset);
5301
5302 return (data32);
5303 }
5304
5305 void
qlnx_direct_reg_wr32(void * p_hwfn,void * reg_addr,uint32_t value)5306 qlnx_direct_reg_wr32(void *p_hwfn, void *reg_addr, uint32_t value)
5307 {
5308 bus_size_t offset;
5309 struct ecore_dev *cdev;
5310
5311 cdev = ((struct ecore_hwfn *)p_hwfn)->p_dev;
5312 offset = (bus_size_t)((uint8_t *)reg_addr - (uint8_t *)(cdev->regview));
5313
5314 bus_write_4(((qlnx_host_t *)cdev)->pci_reg, offset, value);
5315
5316 return;
5317 }
5318
5319 void
qlnx_direct_reg_wr64(void * p_hwfn,void * reg_addr,uint64_t value)5320 qlnx_direct_reg_wr64(void *p_hwfn, void *reg_addr, uint64_t value)
5321 {
5322 bus_size_t offset;
5323 struct ecore_dev *cdev;
5324
5325 cdev = ((struct ecore_hwfn *)p_hwfn)->p_dev;
5326 offset = (bus_size_t)((uint8_t *)reg_addr - (uint8_t *)(cdev->regview));
5327
5328 bus_write_8(((qlnx_host_t *)cdev)->pci_reg, offset, value);
5329 return;
5330 }
5331
5332 void *
qlnx_zalloc(uint32_t size)5333 qlnx_zalloc(uint32_t size)
5334 {
5335 caddr_t va;
5336
5337 va = malloc((unsigned long)size, M_QLNXBUF, M_NOWAIT);
5338 bzero(va, size);
5339 return ((void *)va);
5340 }
5341
5342 void
qlnx_barrier(void * p_dev)5343 qlnx_barrier(void *p_dev)
5344 {
5345 qlnx_host_t *ha;
5346
5347 ha = ((struct ecore_dev *) p_dev)->ha;
5348 bus_barrier(ha->pci_reg, 0, 0, BUS_SPACE_BARRIER_WRITE);
5349 }
5350
5351 void
qlnx_link_update(void * p_hwfn)5352 qlnx_link_update(void *p_hwfn)
5353 {
5354 qlnx_host_t *ha;
5355 int prev_link_state;
5356
5357 ha = (qlnx_host_t *)((struct ecore_hwfn *)p_hwfn)->p_dev;
5358
5359 qlnx_fill_link(ha, p_hwfn, &ha->if_link);
5360
5361 prev_link_state = ha->link_up;
5362 ha->link_up = ha->if_link.link_up;
5363
5364 if (prev_link_state != ha->link_up) {
5365 if (ha->link_up) {
5366 if_link_state_change(ha->ifp, LINK_STATE_UP);
5367 } else {
5368 if_link_state_change(ha->ifp, LINK_STATE_DOWN);
5369 }
5370 }
5371 #ifndef QLNX_VF
5372 #ifdef CONFIG_ECORE_SRIOV
5373
5374 if (qlnx_vf_device(ha) != 0) {
5375 if (ha->sriov_initialized)
5376 qlnx_inform_vf_link_state(p_hwfn, ha);
5377 }
5378
5379 #endif /* #ifdef CONFIG_ECORE_SRIOV */
5380 #endif /* #ifdef QLNX_VF */
5381
5382 return;
5383 }
5384
5385 static void
__qlnx_osal_vf_fill_acquire_resc_req(struct ecore_hwfn * p_hwfn,struct ecore_vf_acquire_sw_info * p_sw_info)5386 __qlnx_osal_vf_fill_acquire_resc_req(struct ecore_hwfn *p_hwfn,
5387 struct ecore_vf_acquire_sw_info *p_sw_info)
5388 {
5389 p_sw_info->driver_version = (QLNX_VERSION_MAJOR << 24) |
5390 (QLNX_VERSION_MINOR << 16) |
5391 QLNX_VERSION_BUILD;
5392 p_sw_info->os_type = VFPF_ACQUIRE_OS_FREEBSD;
5393
5394 return;
5395 }
5396
5397 void
qlnx_osal_vf_fill_acquire_resc_req(void * p_hwfn,void * p_resc_req,void * p_sw_info)5398 qlnx_osal_vf_fill_acquire_resc_req(void *p_hwfn, void *p_resc_req,
5399 void *p_sw_info)
5400 {
5401 __qlnx_osal_vf_fill_acquire_resc_req(p_hwfn, p_sw_info);
5402
5403 return;
5404 }
5405
5406 void
qlnx_fill_link(qlnx_host_t * ha,struct ecore_hwfn * hwfn,struct qlnx_link_output * if_link)5407 qlnx_fill_link(qlnx_host_t *ha, struct ecore_hwfn *hwfn,
5408 struct qlnx_link_output *if_link)
5409 {
5410 struct ecore_mcp_link_params link_params;
5411 struct ecore_mcp_link_state link_state;
5412 uint8_t p_change;
5413 struct ecore_ptt *p_ptt = NULL;
5414
5415 memset(if_link, 0, sizeof(*if_link));
5416 memset(&link_params, 0, sizeof(struct ecore_mcp_link_params));
5417 memset(&link_state, 0, sizeof(struct ecore_mcp_link_state));
5418
5419 ha = (qlnx_host_t *)hwfn->p_dev;
5420
5421 /* Prepare source inputs */
5422 /* we only deal with physical functions */
5423 if (qlnx_vf_device(ha) != 0) {
5424 p_ptt = ecore_ptt_acquire(hwfn);
5425
5426 if (p_ptt == NULL) {
5427 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
5428 return;
5429 }
5430
5431 ecore_mcp_get_media_type(hwfn, p_ptt, &if_link->media_type);
5432 ecore_ptt_release(hwfn, p_ptt);
5433
5434 memcpy(&link_params, ecore_mcp_get_link_params(hwfn),
5435 sizeof(link_params));
5436 memcpy(&link_state, ecore_mcp_get_link_state(hwfn),
5437 sizeof(link_state));
5438 } else {
5439 ecore_mcp_get_media_type(hwfn, NULL, &if_link->media_type);
5440 ecore_vf_read_bulletin(hwfn, &p_change);
5441 ecore_vf_get_link_params(hwfn, &link_params);
5442 ecore_vf_get_link_state(hwfn, &link_state);
5443 }
5444
5445 /* Set the link parameters to pass to protocol driver */
5446 if (link_state.link_up) {
5447 if_link->link_up = true;
5448 if_link->speed = link_state.speed;
5449 }
5450
5451 if_link->supported_caps = QLNX_LINK_CAP_FIBRE;
5452
5453 if (link_params.speed.autoneg)
5454 if_link->supported_caps |= QLNX_LINK_CAP_Autoneg;
5455
5456 if (link_params.pause.autoneg ||
5457 (link_params.pause.forced_rx && link_params.pause.forced_tx))
5458 if_link->supported_caps |= QLNX_LINK_CAP_Asym_Pause;
5459
5460 if (link_params.pause.autoneg || link_params.pause.forced_rx ||
5461 link_params.pause.forced_tx)
5462 if_link->supported_caps |= QLNX_LINK_CAP_Pause;
5463
5464 if (link_params.speed.advertised_speeds &
5465 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
5466 if_link->supported_caps |= QLNX_LINK_CAP_1000baseT_Half |
5467 QLNX_LINK_CAP_1000baseT_Full;
5468
5469 if (link_params.speed.advertised_speeds &
5470 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
5471 if_link->supported_caps |= QLNX_LINK_CAP_10000baseKR_Full;
5472
5473 if (link_params.speed.advertised_speeds &
5474 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
5475 if_link->supported_caps |= QLNX_LINK_CAP_25000baseKR_Full;
5476
5477 if (link_params.speed.advertised_speeds &
5478 NVM_CFG1_PORT_DRV_LINK_SPEED_40G)
5479 if_link->supported_caps |= QLNX_LINK_CAP_40000baseLR4_Full;
5480
5481 if (link_params.speed.advertised_speeds &
5482 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
5483 if_link->supported_caps |= QLNX_LINK_CAP_50000baseKR2_Full;
5484
5485 if (link_params.speed.advertised_speeds &
5486 NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
5487 if_link->supported_caps |= QLNX_LINK_CAP_100000baseKR4_Full;
5488
5489 if_link->advertised_caps = if_link->supported_caps;
5490
5491 if_link->autoneg = link_params.speed.autoneg;
5492 if_link->duplex = QLNX_LINK_DUPLEX;
5493
5494 /* Link partner capabilities */
5495
5496 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_1G_HD)
5497 if_link->link_partner_caps |= QLNX_LINK_CAP_1000baseT_Half;
5498
5499 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_1G_FD)
5500 if_link->link_partner_caps |= QLNX_LINK_CAP_1000baseT_Full;
5501
5502 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_10G)
5503 if_link->link_partner_caps |= QLNX_LINK_CAP_10000baseKR_Full;
5504
5505 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_25G)
5506 if_link->link_partner_caps |= QLNX_LINK_CAP_25000baseKR_Full;
5507
5508 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_40G)
5509 if_link->link_partner_caps |= QLNX_LINK_CAP_40000baseLR4_Full;
5510
5511 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_50G)
5512 if_link->link_partner_caps |= QLNX_LINK_CAP_50000baseKR2_Full;
5513
5514 if (link_state.partner_adv_speed & ECORE_LINK_PARTNER_SPEED_100G)
5515 if_link->link_partner_caps |= QLNX_LINK_CAP_100000baseKR4_Full;
5516
5517 if (link_state.an_complete)
5518 if_link->link_partner_caps |= QLNX_LINK_CAP_Autoneg;
5519
5520 if (link_state.partner_adv_pause)
5521 if_link->link_partner_caps |= QLNX_LINK_CAP_Pause;
5522
5523 if ((link_state.partner_adv_pause ==
5524 ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE) ||
5525 (link_state.partner_adv_pause ==
5526 ECORE_LINK_PARTNER_BOTH_PAUSE))
5527 if_link->link_partner_caps |= QLNX_LINK_CAP_Asym_Pause;
5528
5529 return;
5530 }
5531
5532 void
qlnx_schedule_recovery(void * p_hwfn)5533 qlnx_schedule_recovery(void *p_hwfn)
5534 {
5535 qlnx_host_t *ha;
5536
5537 ha = (qlnx_host_t *)((struct ecore_hwfn *)p_hwfn)->p_dev;
5538
5539 if (qlnx_vf_device(ha) != 0) {
5540 taskqueue_enqueue(ha->err_taskqueue, &ha->err_task);
5541 }
5542
5543 return;
5544 }
5545
5546 static int
qlnx_nic_setup(struct ecore_dev * cdev,struct ecore_pf_params * func_params)5547 qlnx_nic_setup(struct ecore_dev *cdev, struct ecore_pf_params *func_params)
5548 {
5549 int rc, i;
5550
5551 for (i = 0; i < cdev->num_hwfns; i++) {
5552 struct ecore_hwfn *p_hwfn = &cdev->hwfns[i];
5553 p_hwfn->pf_params = *func_params;
5554
5555 #ifdef QLNX_ENABLE_IWARP
5556 if (qlnx_vf_device((qlnx_host_t *)cdev) != 0) {
5557 p_hwfn->using_ll2 = true;
5558 }
5559 #endif /* #ifdef QLNX_ENABLE_IWARP */
5560 }
5561
5562 rc = ecore_resc_alloc(cdev);
5563 if (rc)
5564 goto qlnx_nic_setup_exit;
5565
5566 ecore_resc_setup(cdev);
5567
5568 qlnx_nic_setup_exit:
5569
5570 return rc;
5571 }
5572
5573 static int
qlnx_nic_start(struct ecore_dev * cdev)5574 qlnx_nic_start(struct ecore_dev *cdev)
5575 {
5576 int rc;
5577 struct ecore_hw_init_params params;
5578
5579 bzero(¶ms, sizeof (struct ecore_hw_init_params));
5580
5581 params.p_tunn = NULL;
5582 params.b_hw_start = true;
5583 params.int_mode = cdev->int_mode;
5584 params.allow_npar_tx_switch = true;
5585 params.bin_fw_data = NULL;
5586
5587 rc = ecore_hw_init(cdev, ¶ms);
5588 if (rc) {
5589 ecore_resc_free(cdev);
5590 return rc;
5591 }
5592
5593 return 0;
5594 }
5595
5596 static int
qlnx_slowpath_start(qlnx_host_t * ha)5597 qlnx_slowpath_start(qlnx_host_t *ha)
5598 {
5599 struct ecore_dev *cdev;
5600 struct ecore_pf_params pf_params;
5601 int rc;
5602
5603 memset(&pf_params, 0, sizeof(struct ecore_pf_params));
5604 pf_params.eth_pf_params.num_cons =
5605 (ha->num_rss) * (ha->num_tc + 1);
5606
5607 #ifdef QLNX_ENABLE_IWARP
5608 if (qlnx_vf_device(ha) != 0) {
5609 if(ha->personality == ECORE_PCI_ETH_IWARP) {
5610 device_printf(ha->pci_dev, "setting parameters required by iWARP dev\n");
5611 pf_params.rdma_pf_params.num_qps = 1024;
5612 pf_params.rdma_pf_params.num_srqs = 1024;
5613 pf_params.rdma_pf_params.gl_pi = ECORE_ROCE_PROTOCOL_INDEX;
5614 pf_params.rdma_pf_params.rdma_protocol = ECORE_RDMA_PROTOCOL_IWARP;
5615 } else if(ha->personality == ECORE_PCI_ETH_ROCE) {
5616 device_printf(ha->pci_dev, "setting parameters required by RoCE dev\n");
5617 pf_params.rdma_pf_params.num_qps = 8192;
5618 pf_params.rdma_pf_params.num_srqs = 8192;
5619 //pf_params.rdma_pf_params.min_dpis = 0;
5620 pf_params.rdma_pf_params.min_dpis = 8;
5621 pf_params.rdma_pf_params.roce_edpm_mode = 0;
5622 pf_params.rdma_pf_params.gl_pi = ECORE_ROCE_PROTOCOL_INDEX;
5623 pf_params.rdma_pf_params.rdma_protocol = ECORE_RDMA_PROTOCOL_ROCE;
5624 }
5625 }
5626 #endif /* #ifdef QLNX_ENABLE_IWARP */
5627
5628 cdev = &ha->cdev;
5629
5630 rc = qlnx_nic_setup(cdev, &pf_params);
5631 if (rc)
5632 goto qlnx_slowpath_start_exit;
5633
5634 cdev->int_mode = ECORE_INT_MODE_MSIX;
5635 cdev->int_coalescing_mode = ECORE_COAL_MODE_ENABLE;
5636
5637 #ifdef QLNX_MAX_COALESCE
5638 cdev->rx_coalesce_usecs = 255;
5639 cdev->tx_coalesce_usecs = 255;
5640 #endif
5641
5642 rc = qlnx_nic_start(cdev);
5643
5644 ha->rx_coalesce_usecs = cdev->rx_coalesce_usecs;
5645 ha->tx_coalesce_usecs = cdev->tx_coalesce_usecs;
5646
5647 #ifdef QLNX_USER_LLDP
5648 (void)qlnx_set_lldp_tlvx(ha, NULL);
5649 #endif /* #ifdef QLNX_USER_LLDP */
5650
5651 qlnx_slowpath_start_exit:
5652
5653 return (rc);
5654 }
5655
5656 static int
qlnx_slowpath_stop(qlnx_host_t * ha)5657 qlnx_slowpath_stop(qlnx_host_t *ha)
5658 {
5659 struct ecore_dev *cdev;
5660 device_t dev = ha->pci_dev;
5661 int i;
5662
5663 cdev = &ha->cdev;
5664
5665 ecore_hw_stop(cdev);
5666
5667 for (i = 0; i < ha->cdev.num_hwfns; i++) {
5668 if (ha->sp_handle[i])
5669 (void)bus_teardown_intr(dev, ha->sp_irq[i],
5670 ha->sp_handle[i]);
5671
5672 ha->sp_handle[i] = NULL;
5673
5674 if (ha->sp_irq[i])
5675 (void) bus_release_resource(dev, SYS_RES_IRQ,
5676 ha->sp_irq_rid[i], ha->sp_irq[i]);
5677 ha->sp_irq[i] = NULL;
5678 }
5679
5680 ecore_resc_free(cdev);
5681
5682 return 0;
5683 }
5684
5685 static void
qlnx_set_id(struct ecore_dev * cdev,char name[NAME_SIZE],char ver_str[VER_SIZE])5686 qlnx_set_id(struct ecore_dev *cdev, char name[NAME_SIZE],
5687 char ver_str[VER_SIZE])
5688 {
5689 int i;
5690
5691 memcpy(cdev->name, name, NAME_SIZE);
5692
5693 for_each_hwfn(cdev, i) {
5694 snprintf(cdev->hwfns[i].name, NAME_SIZE, "%s-%d", name, i);
5695 }
5696
5697 cdev->drv_type = DRV_ID_DRV_TYPE_FREEBSD;
5698
5699 return ;
5700 }
5701
5702 void
qlnx_get_protocol_stats(void * cdev,int proto_type,void * proto_stats)5703 qlnx_get_protocol_stats(void *cdev, int proto_type, void *proto_stats)
5704 {
5705 enum ecore_mcp_protocol_type type;
5706 union ecore_mcp_protocol_stats *stats;
5707 struct ecore_eth_stats eth_stats;
5708 qlnx_host_t *ha;
5709
5710 ha = cdev;
5711 stats = proto_stats;
5712 type = proto_type;
5713
5714 switch (type) {
5715 case ECORE_MCP_LAN_STATS:
5716 ecore_get_vport_stats((struct ecore_dev *)cdev, ð_stats);
5717 stats->lan_stats.ucast_rx_pkts = eth_stats.common.rx_ucast_pkts;
5718 stats->lan_stats.ucast_tx_pkts = eth_stats.common.tx_ucast_pkts;
5719 stats->lan_stats.fcs_err = -1;
5720 break;
5721
5722 default:
5723 ha->err_get_proto_invalid_type++;
5724
5725 QL_DPRINT1(ha, "invalid protocol type 0x%x\n", type);
5726 break;
5727 }
5728 return;
5729 }
5730
5731 static int
qlnx_get_mfw_version(qlnx_host_t * ha,uint32_t * mfw_ver)5732 qlnx_get_mfw_version(qlnx_host_t *ha, uint32_t *mfw_ver)
5733 {
5734 struct ecore_hwfn *p_hwfn;
5735 struct ecore_ptt *p_ptt;
5736
5737 p_hwfn = &ha->cdev.hwfns[0];
5738 p_ptt = ecore_ptt_acquire(p_hwfn);
5739
5740 if (p_ptt == NULL) {
5741 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
5742 return (-1);
5743 }
5744 ecore_mcp_get_mfw_ver(p_hwfn, p_ptt, mfw_ver, NULL);
5745
5746 ecore_ptt_release(p_hwfn, p_ptt);
5747
5748 return (0);
5749 }
5750
5751 static int
qlnx_get_flash_size(qlnx_host_t * ha,uint32_t * flash_size)5752 qlnx_get_flash_size(qlnx_host_t *ha, uint32_t *flash_size)
5753 {
5754 struct ecore_hwfn *p_hwfn;
5755 struct ecore_ptt *p_ptt;
5756
5757 p_hwfn = &ha->cdev.hwfns[0];
5758 p_ptt = ecore_ptt_acquire(p_hwfn);
5759
5760 if (p_ptt == NULL) {
5761 QL_DPRINT1(ha,"ecore_ptt_acquire failed\n");
5762 return (-1);
5763 }
5764 ecore_mcp_get_flash_size(p_hwfn, p_ptt, flash_size);
5765
5766 ecore_ptt_release(p_hwfn, p_ptt);
5767
5768 return (0);
5769 }
5770
5771 static int
qlnx_alloc_mem_arrays(qlnx_host_t * ha)5772 qlnx_alloc_mem_arrays(qlnx_host_t *ha)
5773 {
5774 bzero(&ha->txq_array[0], (sizeof(struct qlnx_tx_queue) * QLNX_MAX_RSS));
5775 bzero(&ha->rxq_array[0], (sizeof(struct qlnx_rx_queue) * QLNX_MAX_RSS));
5776 bzero(&ha->sb_array[0], (sizeof(struct ecore_sb_info) * QLNX_MAX_RSS));
5777
5778 return 0;
5779 }
5780
5781 static void
qlnx_init_fp(qlnx_host_t * ha)5782 qlnx_init_fp(qlnx_host_t *ha)
5783 {
5784 int rss_id, txq_array_index, tc;
5785
5786 for (rss_id = 0; rss_id < ha->num_rss; rss_id++) {
5787 struct qlnx_fastpath *fp = &ha->fp_array[rss_id];
5788
5789 fp->rss_id = rss_id;
5790 fp->edev = ha;
5791 fp->sb_info = &ha->sb_array[rss_id];
5792 fp->rxq = &ha->rxq_array[rss_id];
5793 fp->rxq->rxq_id = rss_id;
5794
5795 for (tc = 0; tc < ha->num_tc; tc++) {
5796 txq_array_index = tc * ha->num_rss + rss_id;
5797 fp->txq[tc] = &ha->txq_array[txq_array_index];
5798 fp->txq[tc]->index = txq_array_index;
5799 }
5800
5801 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", qlnx_name_str,
5802 rss_id);
5803
5804 fp->tx_ring_full = 0;
5805
5806 /* reset all the statistics counters */
5807
5808 fp->tx_pkts_processed = 0;
5809 fp->tx_pkts_freed = 0;
5810 fp->tx_pkts_transmitted = 0;
5811 fp->tx_pkts_completed = 0;
5812
5813 #ifdef QLNX_TRACE_PERF_DATA
5814 fp->tx_pkts_trans_ctx = 0;
5815 fp->tx_pkts_compl_ctx = 0;
5816 fp->tx_pkts_trans_fp = 0;
5817 fp->tx_pkts_compl_fp = 0;
5818 fp->tx_pkts_compl_intr = 0;
5819 #endif
5820 fp->tx_lso_wnd_min_len = 0;
5821 fp->tx_defrag = 0;
5822 fp->tx_nsegs_gt_elem_left = 0;
5823 fp->tx_tso_max_nsegs = 0;
5824 fp->tx_tso_min_nsegs = 0;
5825 fp->err_tx_nsegs_gt_elem_left = 0;
5826 fp->err_tx_dmamap_create = 0;
5827 fp->err_tx_defrag_dmamap_load = 0;
5828 fp->err_tx_non_tso_max_seg = 0;
5829 fp->err_tx_dmamap_load = 0;
5830 fp->err_tx_defrag = 0;
5831 fp->err_tx_free_pkt_null = 0;
5832 fp->err_tx_cons_idx_conflict = 0;
5833
5834 fp->rx_pkts = 0;
5835 fp->err_m_getcl = 0;
5836 fp->err_m_getjcl = 0;
5837 }
5838 return;
5839 }
5840
5841 void
qlnx_free_mem_sb(qlnx_host_t * ha,struct ecore_sb_info * sb_info)5842 qlnx_free_mem_sb(qlnx_host_t *ha, struct ecore_sb_info *sb_info)
5843 {
5844 struct ecore_dev *cdev;
5845
5846 cdev = &ha->cdev;
5847
5848 if (sb_info->sb_virt) {
5849 OSAL_DMA_FREE_COHERENT(cdev, ((void *)sb_info->sb_virt),
5850 (sb_info->sb_phys), (sizeof(*sb_info->sb_virt)));
5851 sb_info->sb_virt = NULL;
5852 }
5853 }
5854
5855 static int
qlnx_sb_init(struct ecore_dev * cdev,struct ecore_sb_info * sb_info,void * sb_virt_addr,bus_addr_t sb_phy_addr,u16 sb_id)5856 qlnx_sb_init(struct ecore_dev *cdev, struct ecore_sb_info *sb_info,
5857 void *sb_virt_addr, bus_addr_t sb_phy_addr, u16 sb_id)
5858 {
5859 struct ecore_hwfn *p_hwfn;
5860 int hwfn_index, rc;
5861 u16 rel_sb_id;
5862
5863 hwfn_index = sb_id % cdev->num_hwfns;
5864 p_hwfn = &cdev->hwfns[hwfn_index];
5865 rel_sb_id = sb_id / cdev->num_hwfns;
5866
5867 QL_DPRINT2(((qlnx_host_t *)cdev),
5868 "hwfn_index = %d p_hwfn = %p sb_id = 0x%x rel_sb_id = 0x%x \
5869 sb_info = %p sb_virt_addr = %p sb_phy_addr = %p\n",
5870 hwfn_index, p_hwfn, sb_id, rel_sb_id, sb_info,
5871 sb_virt_addr, (void *)sb_phy_addr);
5872
5873 rc = ecore_int_sb_init(p_hwfn, p_hwfn->p_main_ptt, sb_info,
5874 sb_virt_addr, sb_phy_addr, rel_sb_id);
5875
5876 return rc;
5877 }
5878
5879 /* This function allocates fast-path status block memory */
5880 int
qlnx_alloc_mem_sb(qlnx_host_t * ha,struct ecore_sb_info * sb_info,u16 sb_id)5881 qlnx_alloc_mem_sb(qlnx_host_t *ha, struct ecore_sb_info *sb_info, u16 sb_id)
5882 {
5883 struct status_block_e4 *sb_virt;
5884 bus_addr_t sb_phys;
5885 int rc;
5886 uint32_t size;
5887 struct ecore_dev *cdev;
5888
5889 cdev = &ha->cdev;
5890
5891 size = sizeof(*sb_virt);
5892 sb_virt = OSAL_DMA_ALLOC_COHERENT(cdev, (&sb_phys), size);
5893
5894 if (!sb_virt) {
5895 QL_DPRINT1(ha, "Status block allocation failed\n");
5896 return -ENOMEM;
5897 }
5898
5899 rc = qlnx_sb_init(cdev, sb_info, sb_virt, sb_phys, sb_id);
5900 if (rc) {
5901 OSAL_DMA_FREE_COHERENT(cdev, sb_virt, sb_phys, size);
5902 }
5903
5904 return rc;
5905 }
5906
5907 static void
qlnx_free_rx_buffers(qlnx_host_t * ha,struct qlnx_rx_queue * rxq)5908 qlnx_free_rx_buffers(qlnx_host_t *ha, struct qlnx_rx_queue *rxq)
5909 {
5910 int i;
5911 struct sw_rx_data *rx_buf;
5912
5913 for (i = 0; i < rxq->num_rx_buffers; i++) {
5914 rx_buf = &rxq->sw_rx_ring[i];
5915
5916 if (rx_buf->data != NULL) {
5917 if (rx_buf->map != NULL) {
5918 bus_dmamap_unload(ha->rx_tag, rx_buf->map);
5919 bus_dmamap_destroy(ha->rx_tag, rx_buf->map);
5920 rx_buf->map = NULL;
5921 }
5922 m_freem(rx_buf->data);
5923 rx_buf->data = NULL;
5924 }
5925 }
5926 return;
5927 }
5928
5929 static void
qlnx_free_mem_rxq(qlnx_host_t * ha,struct qlnx_rx_queue * rxq)5930 qlnx_free_mem_rxq(qlnx_host_t *ha, struct qlnx_rx_queue *rxq)
5931 {
5932 struct ecore_dev *cdev;
5933 int i;
5934
5935 cdev = &ha->cdev;
5936
5937 qlnx_free_rx_buffers(ha, rxq);
5938
5939 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
5940 qlnx_free_tpa_mbuf(ha, &rxq->tpa_info[i]);
5941 if (rxq->tpa_info[i].mpf != NULL)
5942 m_freem(rxq->tpa_info[i].mpf);
5943 }
5944
5945 bzero((void *)&rxq->sw_rx_ring[0],
5946 (sizeof (struct sw_rx_data) * RX_RING_SIZE));
5947
5948 /* Free the real RQ ring used by FW */
5949 if (rxq->rx_bd_ring.p_virt_addr) {
5950 ecore_chain_free(cdev, &rxq->rx_bd_ring);
5951 rxq->rx_bd_ring.p_virt_addr = NULL;
5952 }
5953
5954 /* Free the real completion ring used by FW */
5955 if (rxq->rx_comp_ring.p_virt_addr &&
5956 rxq->rx_comp_ring.pbl_sp.p_virt_table) {
5957 ecore_chain_free(cdev, &rxq->rx_comp_ring);
5958 rxq->rx_comp_ring.p_virt_addr = NULL;
5959 rxq->rx_comp_ring.pbl_sp.p_virt_table = NULL;
5960 }
5961
5962 #ifdef QLNX_SOFT_LRO
5963 {
5964 struct lro_ctrl *lro;
5965
5966 lro = &rxq->lro;
5967 tcp_lro_free(lro);
5968 }
5969 #endif /* #ifdef QLNX_SOFT_LRO */
5970
5971 return;
5972 }
5973
5974 static int
qlnx_alloc_rx_buffer(qlnx_host_t * ha,struct qlnx_rx_queue * rxq)5975 qlnx_alloc_rx_buffer(qlnx_host_t *ha, struct qlnx_rx_queue *rxq)
5976 {
5977 register struct mbuf *mp;
5978 uint16_t rx_buf_size;
5979 struct sw_rx_data *sw_rx_data;
5980 struct eth_rx_bd *rx_bd;
5981 dma_addr_t dma_addr;
5982 bus_dmamap_t map;
5983 bus_dma_segment_t segs[1];
5984 int nsegs;
5985 int ret;
5986
5987 rx_buf_size = rxq->rx_buf_size;
5988
5989 mp = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, rx_buf_size);
5990
5991 if (mp == NULL) {
5992 QL_DPRINT1(ha, "Failed to allocate Rx data\n");
5993 return -ENOMEM;
5994 }
5995
5996 mp->m_len = mp->m_pkthdr.len = rx_buf_size;
5997
5998 map = (bus_dmamap_t)0;
5999
6000 ret = bus_dmamap_load_mbuf_sg(ha->rx_tag, map, mp, segs, &nsegs,
6001 BUS_DMA_NOWAIT);
6002 dma_addr = segs[0].ds_addr;
6003
6004 if (ret || !dma_addr || (nsegs != 1)) {
6005 m_freem(mp);
6006 QL_DPRINT1(ha, "bus_dmamap_load failed[%d, 0x%016llx, %d]\n",
6007 ret, (long long unsigned int)dma_addr, nsegs);
6008 return -ENOMEM;
6009 }
6010
6011 sw_rx_data = &rxq->sw_rx_ring[rxq->sw_rx_prod];
6012 sw_rx_data->data = mp;
6013 sw_rx_data->dma_addr = dma_addr;
6014 sw_rx_data->map = map;
6015
6016 /* Advance PROD and get BD pointer */
6017 rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
6018 rx_bd->addr.hi = htole32(U64_HI(dma_addr));
6019 rx_bd->addr.lo = htole32(U64_LO(dma_addr));
6020 bus_dmamap_sync(ha->rx_tag, map, BUS_DMASYNC_PREREAD);
6021
6022 rxq->sw_rx_prod = (rxq->sw_rx_prod + 1) & (RX_RING_SIZE - 1);
6023
6024 return 0;
6025 }
6026
6027 static int
qlnx_alloc_tpa_mbuf(qlnx_host_t * ha,uint16_t rx_buf_size,struct qlnx_agg_info * tpa)6028 qlnx_alloc_tpa_mbuf(qlnx_host_t *ha, uint16_t rx_buf_size,
6029 struct qlnx_agg_info *tpa)
6030 {
6031 struct mbuf *mp;
6032 dma_addr_t dma_addr;
6033 bus_dmamap_t map;
6034 bus_dma_segment_t segs[1];
6035 int nsegs;
6036 int ret;
6037 struct sw_rx_data *rx_buf;
6038
6039 mp = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, rx_buf_size);
6040
6041 if (mp == NULL) {
6042 QL_DPRINT1(ha, "Failed to allocate Rx data\n");
6043 return -ENOMEM;
6044 }
6045
6046 mp->m_len = mp->m_pkthdr.len = rx_buf_size;
6047
6048 map = (bus_dmamap_t)0;
6049
6050 ret = bus_dmamap_load_mbuf_sg(ha->rx_tag, map, mp, segs, &nsegs,
6051 BUS_DMA_NOWAIT);
6052 dma_addr = segs[0].ds_addr;
6053
6054 if (ret || !dma_addr || (nsegs != 1)) {
6055 m_freem(mp);
6056 QL_DPRINT1(ha, "bus_dmamap_load failed[%d, 0x%016llx, %d]\n",
6057 ret, (long long unsigned int)dma_addr, nsegs);
6058 return -ENOMEM;
6059 }
6060
6061 rx_buf = &tpa->rx_buf;
6062
6063 memset(rx_buf, 0, sizeof (struct sw_rx_data));
6064
6065 rx_buf->data = mp;
6066 rx_buf->dma_addr = dma_addr;
6067 rx_buf->map = map;
6068
6069 bus_dmamap_sync(ha->rx_tag, map, BUS_DMASYNC_PREREAD);
6070
6071 return (0);
6072 }
6073
6074 static void
qlnx_free_tpa_mbuf(qlnx_host_t * ha,struct qlnx_agg_info * tpa)6075 qlnx_free_tpa_mbuf(qlnx_host_t *ha, struct qlnx_agg_info *tpa)
6076 {
6077 struct sw_rx_data *rx_buf;
6078
6079 rx_buf = &tpa->rx_buf;
6080
6081 if (rx_buf->data != NULL) {
6082 if (rx_buf->map != NULL) {
6083 bus_dmamap_unload(ha->rx_tag, rx_buf->map);
6084 bus_dmamap_destroy(ha->rx_tag, rx_buf->map);
6085 rx_buf->map = NULL;
6086 }
6087 m_freem(rx_buf->data);
6088 rx_buf->data = NULL;
6089 }
6090 return;
6091 }
6092
6093 /* This function allocates all memory needed per Rx queue */
6094 static int
qlnx_alloc_mem_rxq(qlnx_host_t * ha,struct qlnx_rx_queue * rxq)6095 qlnx_alloc_mem_rxq(qlnx_host_t *ha, struct qlnx_rx_queue *rxq)
6096 {
6097 int i, rc, num_allocated;
6098 struct ecore_dev *cdev;
6099
6100 cdev = &ha->cdev;
6101
6102 rxq->num_rx_buffers = RX_RING_SIZE;
6103
6104 rxq->rx_buf_size = ha->rx_buf_size;
6105
6106 /* Allocate the parallel driver ring for Rx buffers */
6107 bzero((void *)&rxq->sw_rx_ring[0],
6108 (sizeof (struct sw_rx_data) * RX_RING_SIZE));
6109
6110 /* Allocate FW Rx ring */
6111
6112 rc = ecore_chain_alloc(cdev,
6113 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
6114 ECORE_CHAIN_MODE_NEXT_PTR,
6115 ECORE_CHAIN_CNT_TYPE_U16,
6116 RX_RING_SIZE,
6117 sizeof(struct eth_rx_bd),
6118 &rxq->rx_bd_ring, NULL);
6119
6120 if (rc)
6121 goto err;
6122
6123 /* Allocate FW completion ring */
6124 rc = ecore_chain_alloc(cdev,
6125 ECORE_CHAIN_USE_TO_CONSUME,
6126 ECORE_CHAIN_MODE_PBL,
6127 ECORE_CHAIN_CNT_TYPE_U16,
6128 RX_RING_SIZE,
6129 sizeof(union eth_rx_cqe),
6130 &rxq->rx_comp_ring, NULL);
6131
6132 if (rc)
6133 goto err;
6134
6135 /* Allocate buffers for the Rx ring */
6136
6137 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
6138 rc = qlnx_alloc_tpa_mbuf(ha, rxq->rx_buf_size,
6139 &rxq->tpa_info[i]);
6140 if (rc)
6141 break;
6142 }
6143
6144 for (i = 0; i < rxq->num_rx_buffers; i++) {
6145 rc = qlnx_alloc_rx_buffer(ha, rxq);
6146 if (rc)
6147 break;
6148 }
6149 num_allocated = i;
6150 if (!num_allocated) {
6151 QL_DPRINT1(ha, "Rx buffers allocation failed\n");
6152 goto err;
6153 } else if (num_allocated < rxq->num_rx_buffers) {
6154 QL_DPRINT1(ha, "Allocated less buffers than"
6155 " desired (%d allocated)\n", num_allocated);
6156 }
6157
6158 #ifdef QLNX_SOFT_LRO
6159
6160 {
6161 struct lro_ctrl *lro;
6162
6163 lro = &rxq->lro;
6164
6165 if (tcp_lro_init_args(lro, ifp, 0, rxq->num_rx_buffers)) {
6166 QL_DPRINT1(ha, "tcp_lro_init[%d] failed\n",
6167 rxq->rxq_id);
6168 goto err;
6169 }
6170
6171 lro->ifp = ha->ifp;
6172 }
6173 #endif /* #ifdef QLNX_SOFT_LRO */
6174 return 0;
6175
6176 err:
6177 qlnx_free_mem_rxq(ha, rxq);
6178 return -ENOMEM;
6179 }
6180
6181 static void
qlnx_free_mem_txq(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_tx_queue * txq)6182 qlnx_free_mem_txq(qlnx_host_t *ha, struct qlnx_fastpath *fp,
6183 struct qlnx_tx_queue *txq)
6184 {
6185 struct ecore_dev *cdev;
6186
6187 cdev = &ha->cdev;
6188
6189 bzero((void *)&txq->sw_tx_ring[0],
6190 (sizeof (struct sw_tx_bd) * TX_RING_SIZE));
6191
6192 /* Free the real RQ ring used by FW */
6193 if (txq->tx_pbl.p_virt_addr) {
6194 ecore_chain_free(cdev, &txq->tx_pbl);
6195 txq->tx_pbl.p_virt_addr = NULL;
6196 }
6197 return;
6198 }
6199
6200 /* This function allocates all memory needed per Tx queue */
6201 static int
qlnx_alloc_mem_txq(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_tx_queue * txq)6202 qlnx_alloc_mem_txq(qlnx_host_t *ha, struct qlnx_fastpath *fp,
6203 struct qlnx_tx_queue *txq)
6204 {
6205 int ret = ECORE_SUCCESS;
6206 union eth_tx_bd_types *p_virt;
6207 struct ecore_dev *cdev;
6208
6209 cdev = &ha->cdev;
6210
6211 bzero((void *)&txq->sw_tx_ring[0],
6212 (sizeof (struct sw_tx_bd) * TX_RING_SIZE));
6213
6214 /* Allocate the real Tx ring to be used by FW */
6215 ret = ecore_chain_alloc(cdev,
6216 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
6217 ECORE_CHAIN_MODE_PBL,
6218 ECORE_CHAIN_CNT_TYPE_U16,
6219 TX_RING_SIZE,
6220 sizeof(*p_virt),
6221 &txq->tx_pbl, NULL);
6222
6223 if (ret != ECORE_SUCCESS) {
6224 goto err;
6225 }
6226
6227 txq->num_tx_buffers = TX_RING_SIZE;
6228
6229 return 0;
6230
6231 err:
6232 qlnx_free_mem_txq(ha, fp, txq);
6233 return -ENOMEM;
6234 }
6235
6236 static void
qlnx_free_tx_br(qlnx_host_t * ha,struct qlnx_fastpath * fp)6237 qlnx_free_tx_br(qlnx_host_t *ha, struct qlnx_fastpath *fp)
6238 {
6239 struct mbuf *mp;
6240 if_t ifp = ha->ifp;
6241
6242 if (mtx_initialized(&fp->tx_mtx)) {
6243 if (fp->tx_br != NULL) {
6244 mtx_lock(&fp->tx_mtx);
6245
6246 while ((mp = drbr_dequeue(ifp, fp->tx_br)) != NULL) {
6247 fp->tx_pkts_freed++;
6248 m_freem(mp);
6249 }
6250
6251 mtx_unlock(&fp->tx_mtx);
6252
6253 buf_ring_free(fp->tx_br, M_DEVBUF);
6254 fp->tx_br = NULL;
6255 }
6256 mtx_destroy(&fp->tx_mtx);
6257 }
6258 return;
6259 }
6260
6261 static void
qlnx_free_mem_fp(qlnx_host_t * ha,struct qlnx_fastpath * fp)6262 qlnx_free_mem_fp(qlnx_host_t *ha, struct qlnx_fastpath *fp)
6263 {
6264 int tc;
6265
6266 qlnx_free_mem_sb(ha, fp->sb_info);
6267
6268 qlnx_free_mem_rxq(ha, fp->rxq);
6269
6270 for (tc = 0; tc < ha->num_tc; tc++)
6271 qlnx_free_mem_txq(ha, fp, fp->txq[tc]);
6272
6273 return;
6274 }
6275
6276 static int
qlnx_alloc_tx_br(qlnx_host_t * ha,struct qlnx_fastpath * fp)6277 qlnx_alloc_tx_br(qlnx_host_t *ha, struct qlnx_fastpath *fp)
6278 {
6279 snprintf(fp->tx_mtx_name, sizeof(fp->tx_mtx_name),
6280 "qlnx%d_fp%d_tx_mq_lock", ha->dev_unit, fp->rss_id);
6281
6282 mtx_init(&fp->tx_mtx, fp->tx_mtx_name, NULL, MTX_DEF);
6283
6284 fp->tx_br = buf_ring_alloc(TX_RING_SIZE, M_DEVBUF,
6285 M_NOWAIT, &fp->tx_mtx);
6286 if (fp->tx_br == NULL) {
6287 QL_DPRINT1(ha, "buf_ring_alloc failed for fp[%d, %d]\n",
6288 ha->dev_unit, fp->rss_id);
6289 return -ENOMEM;
6290 }
6291 return 0;
6292 }
6293
6294 static int
qlnx_alloc_mem_fp(qlnx_host_t * ha,struct qlnx_fastpath * fp)6295 qlnx_alloc_mem_fp(qlnx_host_t *ha, struct qlnx_fastpath *fp)
6296 {
6297 int rc, tc;
6298
6299 rc = qlnx_alloc_mem_sb(ha, fp->sb_info, fp->rss_id);
6300 if (rc)
6301 goto err;
6302
6303 if (ha->rx_jumbo_buf_eq_mtu) {
6304 if (ha->max_frame_size <= MCLBYTES)
6305 ha->rx_buf_size = MCLBYTES;
6306 else if (ha->max_frame_size <= MJUMPAGESIZE)
6307 ha->rx_buf_size = MJUMPAGESIZE;
6308 else if (ha->max_frame_size <= MJUM9BYTES)
6309 ha->rx_buf_size = MJUM9BYTES;
6310 else if (ha->max_frame_size <= MJUM16BYTES)
6311 ha->rx_buf_size = MJUM16BYTES;
6312 } else {
6313 if (ha->max_frame_size <= MCLBYTES)
6314 ha->rx_buf_size = MCLBYTES;
6315 else
6316 ha->rx_buf_size = MJUMPAGESIZE;
6317 }
6318
6319 rc = qlnx_alloc_mem_rxq(ha, fp->rxq);
6320 if (rc)
6321 goto err;
6322
6323 for (tc = 0; tc < ha->num_tc; tc++) {
6324 rc = qlnx_alloc_mem_txq(ha, fp, fp->txq[tc]);
6325 if (rc)
6326 goto err;
6327 }
6328
6329 return 0;
6330
6331 err:
6332 qlnx_free_mem_fp(ha, fp);
6333 return -ENOMEM;
6334 }
6335
6336 static void
qlnx_free_mem_load(qlnx_host_t * ha)6337 qlnx_free_mem_load(qlnx_host_t *ha)
6338 {
6339 int i;
6340
6341 for (i = 0; i < ha->num_rss; i++) {
6342 struct qlnx_fastpath *fp = &ha->fp_array[i];
6343
6344 qlnx_free_mem_fp(ha, fp);
6345 }
6346 return;
6347 }
6348
6349 static int
qlnx_alloc_mem_load(qlnx_host_t * ha)6350 qlnx_alloc_mem_load(qlnx_host_t *ha)
6351 {
6352 int rc = 0, rss_id;
6353
6354 for (rss_id = 0; rss_id < ha->num_rss; rss_id++) {
6355 struct qlnx_fastpath *fp = &ha->fp_array[rss_id];
6356
6357 rc = qlnx_alloc_mem_fp(ha, fp);
6358 if (rc)
6359 break;
6360 }
6361 return (rc);
6362 }
6363
6364 static int
qlnx_start_vport(struct ecore_dev * cdev,u8 vport_id,u16 mtu,u8 drop_ttl0_flg,u8 inner_vlan_removal_en_flg,u8 tx_switching,u8 hw_lro_enable)6365 qlnx_start_vport(struct ecore_dev *cdev,
6366 u8 vport_id,
6367 u16 mtu,
6368 u8 drop_ttl0_flg,
6369 u8 inner_vlan_removal_en_flg,
6370 u8 tx_switching,
6371 u8 hw_lro_enable)
6372 {
6373 int rc, i;
6374 struct ecore_sp_vport_start_params vport_start_params = { 0 };
6375 qlnx_host_t *ha __unused;
6376
6377 ha = (qlnx_host_t *)cdev;
6378
6379 vport_start_params.remove_inner_vlan = inner_vlan_removal_en_flg;
6380 vport_start_params.tx_switching = 0;
6381 vport_start_params.handle_ptp_pkts = 0;
6382 vport_start_params.only_untagged = 0;
6383 vport_start_params.drop_ttl0 = drop_ttl0_flg;
6384
6385 vport_start_params.tpa_mode =
6386 (hw_lro_enable ? ECORE_TPA_MODE_RSC : ECORE_TPA_MODE_NONE);
6387 vport_start_params.max_buffers_per_cqe = QLNX_TPA_MAX_AGG_BUFFERS;
6388
6389 vport_start_params.vport_id = vport_id;
6390 vport_start_params.mtu = mtu;
6391
6392 QL_DPRINT2(ha, "Setting mtu to %d and VPORT ID = %d\n", mtu, vport_id);
6393
6394 for_each_hwfn(cdev, i) {
6395 struct ecore_hwfn *p_hwfn = &cdev->hwfns[i];
6396
6397 vport_start_params.concrete_fid = p_hwfn->hw_info.concrete_fid;
6398 vport_start_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
6399
6400 rc = ecore_sp_vport_start(p_hwfn, &vport_start_params);
6401
6402 if (rc) {
6403 QL_DPRINT1(ha, "Failed to start VPORT V-PORT %d"
6404 " with MTU %d\n" , vport_id, mtu);
6405 return -ENOMEM;
6406 }
6407
6408 ecore_hw_start_fastpath(p_hwfn);
6409
6410 QL_DPRINT2(ha, "Started V-PORT %d with MTU %d\n",
6411 vport_id, mtu);
6412 }
6413 return 0;
6414 }
6415
6416 static int
qlnx_update_vport(struct ecore_dev * cdev,struct qlnx_update_vport_params * params)6417 qlnx_update_vport(struct ecore_dev *cdev,
6418 struct qlnx_update_vport_params *params)
6419 {
6420 struct ecore_sp_vport_update_params sp_params;
6421 int rc, i, j, fp_index;
6422 struct ecore_hwfn *p_hwfn;
6423 struct ecore_rss_params *rss;
6424 qlnx_host_t *ha = (qlnx_host_t *)cdev;
6425 struct qlnx_fastpath *fp;
6426
6427 memset(&sp_params, 0, sizeof(sp_params));
6428 /* Translate protocol params into sp params */
6429 sp_params.vport_id = params->vport_id;
6430
6431 sp_params.update_vport_active_rx_flg =
6432 params->update_vport_active_rx_flg;
6433 sp_params.vport_active_rx_flg = params->vport_active_rx_flg;
6434
6435 sp_params.update_vport_active_tx_flg =
6436 params->update_vport_active_tx_flg;
6437 sp_params.vport_active_tx_flg = params->vport_active_tx_flg;
6438
6439 sp_params.update_inner_vlan_removal_flg =
6440 params->update_inner_vlan_removal_flg;
6441 sp_params.inner_vlan_removal_flg = params->inner_vlan_removal_flg;
6442
6443 sp_params.sge_tpa_params = params->sge_tpa_params;
6444
6445 /* RSS - is a bit tricky, since upper-layer isn't familiar with hwfns.
6446 * We need to re-fix the rss values per engine for CMT.
6447 */
6448 if (params->rss_params->update_rss_config)
6449 sp_params.rss_params = params->rss_params;
6450 else
6451 sp_params.rss_params = NULL;
6452
6453 for_each_hwfn(cdev, i) {
6454 p_hwfn = &cdev->hwfns[i];
6455
6456 if ((cdev->num_hwfns > 1) &&
6457 params->rss_params->update_rss_config &&
6458 params->rss_params->rss_enable) {
6459 rss = params->rss_params;
6460
6461 for (j = 0; j < ECORE_RSS_IND_TABLE_SIZE; j++) {
6462 fp_index = ((cdev->num_hwfns * j) + i) %
6463 ha->num_rss;
6464
6465 fp = &ha->fp_array[fp_index];
6466 rss->rss_ind_table[j] = fp->rxq->handle;
6467 }
6468
6469 for (j = 0; j < ECORE_RSS_IND_TABLE_SIZE;) {
6470 QL_DPRINT3(ha, "%p %p %p %p %p %p %p %p \n",
6471 rss->rss_ind_table[j],
6472 rss->rss_ind_table[j+1],
6473 rss->rss_ind_table[j+2],
6474 rss->rss_ind_table[j+3],
6475 rss->rss_ind_table[j+4],
6476 rss->rss_ind_table[j+5],
6477 rss->rss_ind_table[j+6],
6478 rss->rss_ind_table[j+7]);
6479 j += 8;
6480 }
6481 }
6482
6483 sp_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
6484
6485 QL_DPRINT1(ha, "Update sp vport ID=%d\n", params->vport_id);
6486
6487 rc = ecore_sp_vport_update(p_hwfn, &sp_params,
6488 ECORE_SPQ_MODE_EBLOCK, NULL);
6489 if (rc) {
6490 QL_DPRINT1(ha, "Failed to update VPORT\n");
6491 return rc;
6492 }
6493
6494 QL_DPRINT2(ha, "Updated V-PORT %d: tx_active_flag %d, \
6495 rx_active_flag %d [tx_update %d], [rx_update %d]\n",
6496 params->vport_id, params->vport_active_tx_flg,
6497 params->vport_active_rx_flg,
6498 params->update_vport_active_tx_flg,
6499 params->update_vport_active_rx_flg);
6500 }
6501
6502 return 0;
6503 }
6504
6505 static void
qlnx_reuse_rx_data(struct qlnx_rx_queue * rxq)6506 qlnx_reuse_rx_data(struct qlnx_rx_queue *rxq)
6507 {
6508 struct eth_rx_bd *rx_bd_cons =
6509 ecore_chain_consume(&rxq->rx_bd_ring);
6510 struct eth_rx_bd *rx_bd_prod =
6511 ecore_chain_produce(&rxq->rx_bd_ring);
6512 struct sw_rx_data *sw_rx_data_cons =
6513 &rxq->sw_rx_ring[rxq->sw_rx_cons];
6514 struct sw_rx_data *sw_rx_data_prod =
6515 &rxq->sw_rx_ring[rxq->sw_rx_prod];
6516
6517 sw_rx_data_prod->data = sw_rx_data_cons->data;
6518 memcpy(rx_bd_prod, rx_bd_cons, sizeof(struct eth_rx_bd));
6519
6520 rxq->sw_rx_cons = (rxq->sw_rx_cons + 1) & (RX_RING_SIZE - 1);
6521 rxq->sw_rx_prod = (rxq->sw_rx_prod + 1) & (RX_RING_SIZE - 1);
6522
6523 return;
6524 }
6525
6526 static void
qlnx_update_rx_prod(struct ecore_hwfn * p_hwfn,struct qlnx_rx_queue * rxq)6527 qlnx_update_rx_prod(struct ecore_hwfn *p_hwfn, struct qlnx_rx_queue *rxq)
6528 {
6529
6530 uint16_t bd_prod;
6531 uint16_t cqe_prod;
6532 union {
6533 struct eth_rx_prod_data rx_prod_data;
6534 uint32_t data32;
6535 } rx_prods;
6536
6537 bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
6538 cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
6539
6540 /* Update producers */
6541 rx_prods.rx_prod_data.bd_prod = htole16(bd_prod);
6542 rx_prods.rx_prod_data.cqe_prod = htole16(cqe_prod);
6543
6544 /* Make sure that the BD and SGE data is updated before updating the
6545 * producers since FW might read the BD/SGE right after the producer
6546 * is updated.
6547 */
6548 wmb();
6549
6550 #ifdef ECORE_CONFIG_DIRECT_HWFN
6551 internal_ram_wr(p_hwfn, rxq->hw_rxq_prod_addr,
6552 sizeof(rx_prods), &rx_prods.data32);
6553 #else
6554 internal_ram_wr(rxq->hw_rxq_prod_addr,
6555 sizeof(rx_prods), &rx_prods.data32);
6556 #endif
6557
6558 /* mmiowb is needed to synchronize doorbell writes from more than one
6559 * processor. It guarantees that the write arrives to the device before
6560 * the napi lock is released and another qlnx_poll is called (possibly
6561 * on another CPU). Without this barrier, the next doorbell can bypass
6562 * this doorbell. This is applicable to IA64/Altix systems.
6563 */
6564 wmb();
6565
6566 return;
6567 }
6568
6569 static int
qlnx_start_queues(qlnx_host_t * ha)6570 qlnx_start_queues(qlnx_host_t *ha)
6571 {
6572 uint8_t rss_key[RSS_KEYSIZE];
6573 int rc, tc, i, vport_id = 0,
6574 drop_ttl0_flg = 1, vlan_removal_en = 1,
6575 tx_switching = 0, hw_lro_enable = 0;
6576 struct ecore_dev *cdev = &ha->cdev;
6577 struct ecore_rss_params *rss_params = &ha->rss_params;
6578 struct qlnx_update_vport_params vport_update_params;
6579 if_t ifp;
6580 struct ecore_hwfn *p_hwfn;
6581 struct ecore_sge_tpa_params tpa_params;
6582 struct ecore_queue_start_common_params qparams;
6583 struct qlnx_fastpath *fp;
6584
6585 ifp = ha->ifp;
6586
6587 QL_DPRINT1(ha, "Num RSS = %d\n", ha->num_rss);
6588
6589 if (!ha->num_rss) {
6590 QL_DPRINT1(ha, "Cannot update V-VPORT as active as there"
6591 " are no Rx queues\n");
6592 return -EINVAL;
6593 }
6594
6595 #ifndef QLNX_SOFT_LRO
6596 hw_lro_enable = if_getcapenable(ifp) & IFCAP_LRO;
6597 #endif /* #ifndef QLNX_SOFT_LRO */
6598
6599 rc = qlnx_start_vport(cdev, vport_id, if_getmtu(ifp), drop_ttl0_flg,
6600 vlan_removal_en, tx_switching, hw_lro_enable);
6601
6602 if (rc) {
6603 QL_DPRINT1(ha, "Start V-PORT failed %d\n", rc);
6604 return rc;
6605 }
6606
6607 QL_DPRINT2(ha, "Start vport ramrod passed, "
6608 "vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
6609 vport_id, (int)(if_getmtu(ifp) + 0xe), vlan_removal_en);
6610
6611 for_each_rss(i) {
6612 struct ecore_rxq_start_ret_params rx_ret_params;
6613 struct ecore_txq_start_ret_params tx_ret_params;
6614
6615 fp = &ha->fp_array[i];
6616 p_hwfn = &cdev->hwfns[(fp->rss_id % cdev->num_hwfns)];
6617
6618 bzero(&qparams, sizeof(struct ecore_queue_start_common_params));
6619 bzero(&rx_ret_params,
6620 sizeof (struct ecore_rxq_start_ret_params));
6621
6622 qparams.queue_id = i ;
6623 qparams.vport_id = vport_id;
6624 qparams.stats_id = vport_id;
6625 qparams.p_sb = fp->sb_info;
6626 qparams.sb_idx = RX_PI;
6627
6628
6629 rc = ecore_eth_rx_queue_start(p_hwfn,
6630 p_hwfn->hw_info.opaque_fid,
6631 &qparams,
6632 fp->rxq->rx_buf_size, /* bd_max_bytes */
6633 /* bd_chain_phys_addr */
6634 fp->rxq->rx_bd_ring.p_phys_addr,
6635 /* cqe_pbl_addr */
6636 ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring),
6637 /* cqe_pbl_size */
6638 ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring),
6639 &rx_ret_params);
6640
6641 if (rc) {
6642 QL_DPRINT1(ha, "Start RXQ #%d failed %d\n", i, rc);
6643 return rc;
6644 }
6645
6646 fp->rxq->hw_rxq_prod_addr = rx_ret_params.p_prod;
6647 fp->rxq->handle = rx_ret_params.p_handle;
6648 fp->rxq->hw_cons_ptr =
6649 &fp->sb_info->sb_virt->pi_array[RX_PI];
6650
6651 qlnx_update_rx_prod(p_hwfn, fp->rxq);
6652
6653 for (tc = 0; tc < ha->num_tc; tc++) {
6654 struct qlnx_tx_queue *txq = fp->txq[tc];
6655
6656 bzero(&qparams,
6657 sizeof(struct ecore_queue_start_common_params));
6658 bzero(&tx_ret_params,
6659 sizeof (struct ecore_txq_start_ret_params));
6660
6661 qparams.queue_id = txq->index / cdev->num_hwfns ;
6662 qparams.vport_id = vport_id;
6663 qparams.stats_id = vport_id;
6664 qparams.p_sb = fp->sb_info;
6665 qparams.sb_idx = TX_PI(tc);
6666
6667 rc = ecore_eth_tx_queue_start(p_hwfn,
6668 p_hwfn->hw_info.opaque_fid,
6669 &qparams, tc,
6670 /* bd_chain_phys_addr */
6671 ecore_chain_get_pbl_phys(&txq->tx_pbl),
6672 ecore_chain_get_page_cnt(&txq->tx_pbl),
6673 &tx_ret_params);
6674
6675 if (rc) {
6676 QL_DPRINT1(ha, "Start TXQ #%d failed %d\n",
6677 txq->index, rc);
6678 return rc;
6679 }
6680
6681 txq->doorbell_addr = tx_ret_params.p_doorbell;
6682 txq->handle = tx_ret_params.p_handle;
6683
6684 txq->hw_cons_ptr =
6685 &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
6686 SET_FIELD(txq->tx_db.data.params,
6687 ETH_DB_DATA_DEST, DB_DEST_XCM);
6688 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
6689 DB_AGG_CMD_SET);
6690 SET_FIELD(txq->tx_db.data.params,
6691 ETH_DB_DATA_AGG_VAL_SEL,
6692 DQ_XCM_ETH_TX_BD_PROD_CMD);
6693
6694 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
6695 }
6696 }
6697
6698 /* Fill struct with RSS params */
6699 if (ha->num_rss > 1) {
6700 rss_params->update_rss_config = 1;
6701 rss_params->rss_enable = 1;
6702 rss_params->update_rss_capabilities = 1;
6703 rss_params->update_rss_ind_table = 1;
6704 rss_params->update_rss_key = 1;
6705 rss_params->rss_caps = ECORE_RSS_IPV4 | ECORE_RSS_IPV6 |
6706 ECORE_RSS_IPV4_TCP | ECORE_RSS_IPV6_TCP;
6707 rss_params->rss_table_size_log = 7; /* 2^7 = 128 */
6708
6709 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
6710 fp = &ha->fp_array[(i % ha->num_rss)];
6711 rss_params->rss_ind_table[i] = fp->rxq->handle;
6712 }
6713
6714 _Static_assert(sizeof(rss_params->rss_key) == RSS_KEYSIZE,
6715 "RSS key size mismatch");
6716 rss_getkey(rss_key);
6717 /* The shared code converts these host-order words to LE. */
6718 for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
6719 rss_params->rss_key[i] =
6720 be32dec(rss_key + i * sizeof(uint32_t));
6721
6722 } else {
6723 memset(rss_params, 0, sizeof(*rss_params));
6724 }
6725
6726 /* Prepare and send the vport enable */
6727 memset(&vport_update_params, 0, sizeof(vport_update_params));
6728 vport_update_params.vport_id = vport_id;
6729 vport_update_params.update_vport_active_tx_flg = 1;
6730 vport_update_params.vport_active_tx_flg = 1;
6731 vport_update_params.update_vport_active_rx_flg = 1;
6732 vport_update_params.vport_active_rx_flg = 1;
6733 vport_update_params.rss_params = rss_params;
6734 vport_update_params.update_inner_vlan_removal_flg = 1;
6735 vport_update_params.inner_vlan_removal_flg = 1;
6736
6737 if (hw_lro_enable) {
6738 memset(&tpa_params, 0, sizeof (struct ecore_sge_tpa_params));
6739
6740 tpa_params.max_buffers_per_cqe = QLNX_TPA_MAX_AGG_BUFFERS;
6741
6742 tpa_params.update_tpa_en_flg = 1;
6743 tpa_params.tpa_ipv4_en_flg = 1;
6744 tpa_params.tpa_ipv6_en_flg = 1;
6745
6746 tpa_params.update_tpa_param_flg = 1;
6747 tpa_params.tpa_pkt_split_flg = 0;
6748 tpa_params.tpa_hdr_data_split_flg = 0;
6749 tpa_params.tpa_gro_consistent_flg = 0;
6750 tpa_params.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
6751 tpa_params.tpa_max_size = (uint16_t)(-1);
6752 tpa_params.tpa_min_size_to_start = if_getmtu(ifp) / 2;
6753 tpa_params.tpa_min_size_to_cont = if_getmtu(ifp) / 2;
6754
6755 vport_update_params.sge_tpa_params = &tpa_params;
6756 }
6757
6758 rc = qlnx_update_vport(cdev, &vport_update_params);
6759 if (rc) {
6760 QL_DPRINT1(ha, "Update V-PORT failed %d\n", rc);
6761 return rc;
6762 }
6763
6764 return 0;
6765 }
6766
6767 static int
qlnx_drain_txq(qlnx_host_t * ha,struct qlnx_fastpath * fp,struct qlnx_tx_queue * txq)6768 qlnx_drain_txq(qlnx_host_t *ha, struct qlnx_fastpath *fp,
6769 struct qlnx_tx_queue *txq)
6770 {
6771 uint16_t hw_bd_cons;
6772 uint16_t ecore_cons_idx;
6773
6774 QL_DPRINT2(ha, "enter\n");
6775
6776 hw_bd_cons = le16toh(*txq->hw_cons_ptr);
6777
6778 while (hw_bd_cons !=
6779 (ecore_cons_idx = ecore_chain_get_cons_idx(&txq->tx_pbl))) {
6780 mtx_lock(&fp->tx_mtx);
6781
6782 (void)qlnx_tx_int(ha, fp, txq);
6783
6784 mtx_unlock(&fp->tx_mtx);
6785
6786 qlnx_mdelay(__func__, 2);
6787
6788 hw_bd_cons = le16toh(*txq->hw_cons_ptr);
6789 }
6790
6791 QL_DPRINT2(ha, "[%d, %d]: done\n", fp->rss_id, txq->index);
6792
6793 return 0;
6794 }
6795
6796 static int
qlnx_stop_queues(qlnx_host_t * ha)6797 qlnx_stop_queues(qlnx_host_t *ha)
6798 {
6799 struct qlnx_update_vport_params vport_update_params;
6800 struct ecore_dev *cdev;
6801 struct qlnx_fastpath *fp;
6802 int rc, tc, i;
6803
6804 cdev = &ha->cdev;
6805
6806 /* Disable the vport */
6807
6808 memset(&vport_update_params, 0, sizeof(vport_update_params));
6809
6810 vport_update_params.vport_id = 0;
6811 vport_update_params.update_vport_active_tx_flg = 1;
6812 vport_update_params.vport_active_tx_flg = 0;
6813 vport_update_params.update_vport_active_rx_flg = 1;
6814 vport_update_params.vport_active_rx_flg = 0;
6815 vport_update_params.rss_params = &ha->rss_params;
6816 vport_update_params.rss_params->update_rss_config = 0;
6817 vport_update_params.rss_params->rss_enable = 0;
6818 vport_update_params.update_inner_vlan_removal_flg = 0;
6819 vport_update_params.inner_vlan_removal_flg = 0;
6820
6821 QL_DPRINT1(ha, "Update vport ID= %d\n", vport_update_params.vport_id);
6822
6823 rc = qlnx_update_vport(cdev, &vport_update_params);
6824 if (rc) {
6825 QL_DPRINT1(ha, "Failed to update vport\n");
6826 return rc;
6827 }
6828
6829 /* Flush Tx queues. If needed, request drain from MCP */
6830 for_each_rss(i) {
6831 fp = &ha->fp_array[i];
6832
6833 for (tc = 0; tc < ha->num_tc; tc++) {
6834 struct qlnx_tx_queue *txq = fp->txq[tc];
6835
6836 rc = qlnx_drain_txq(ha, fp, txq);
6837 if (rc)
6838 return rc;
6839 }
6840 }
6841
6842 /* Stop all Queues in reverse order*/
6843 for (i = ha->num_rss - 1; i >= 0; i--) {
6844 struct ecore_hwfn *p_hwfn = &cdev->hwfns[(i % cdev->num_hwfns)];
6845
6846 fp = &ha->fp_array[i];
6847
6848 /* Stop the Tx Queue(s)*/
6849 for (tc = 0; tc < ha->num_tc; tc++) {
6850 int tx_queue_id __unused;
6851
6852 tx_queue_id = tc * ha->num_rss + i;
6853 rc = ecore_eth_tx_queue_stop(p_hwfn,
6854 fp->txq[tc]->handle);
6855
6856 if (rc) {
6857 QL_DPRINT1(ha, "Failed to stop TXQ #%d\n",
6858 tx_queue_id);
6859 return rc;
6860 }
6861 }
6862
6863 /* Stop the Rx Queue*/
6864 rc = ecore_eth_rx_queue_stop(p_hwfn, fp->rxq->handle, false,
6865 false);
6866 if (rc) {
6867 QL_DPRINT1(ha, "Failed to stop RXQ #%d\n", i);
6868 return rc;
6869 }
6870 }
6871
6872 /* Stop the vport */
6873 for_each_hwfn(cdev, i) {
6874 struct ecore_hwfn *p_hwfn = &cdev->hwfns[i];
6875
6876 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid, 0);
6877
6878 if (rc) {
6879 QL_DPRINT1(ha, "Failed to stop VPORT\n");
6880 return rc;
6881 }
6882 }
6883
6884 return rc;
6885 }
6886
6887 static int
qlnx_set_ucast_rx_mac(qlnx_host_t * ha,enum ecore_filter_opcode opcode,unsigned char mac[ETH_ALEN])6888 qlnx_set_ucast_rx_mac(qlnx_host_t *ha,
6889 enum ecore_filter_opcode opcode,
6890 unsigned char mac[ETH_ALEN])
6891 {
6892 struct ecore_filter_ucast ucast;
6893 struct ecore_dev *cdev;
6894 int rc;
6895
6896 cdev = &ha->cdev;
6897
6898 bzero(&ucast, sizeof(struct ecore_filter_ucast));
6899
6900 ucast.opcode = opcode;
6901 ucast.type = ECORE_FILTER_MAC;
6902 ucast.is_rx_filter = 1;
6903 ucast.vport_to_add_to = 0;
6904 memcpy(&ucast.mac[0], mac, ETH_ALEN);
6905
6906 rc = ecore_filter_ucast_cmd(cdev, &ucast, ECORE_SPQ_MODE_CB, NULL);
6907
6908 return (rc);
6909 }
6910
6911 static int
qlnx_remove_all_ucast_mac(qlnx_host_t * ha)6912 qlnx_remove_all_ucast_mac(qlnx_host_t *ha)
6913 {
6914 struct ecore_filter_ucast ucast;
6915 struct ecore_dev *cdev;
6916 int rc;
6917
6918 bzero(&ucast, sizeof(struct ecore_filter_ucast));
6919
6920 ucast.opcode = ECORE_FILTER_REPLACE;
6921 ucast.type = ECORE_FILTER_MAC;
6922 ucast.is_rx_filter = 1;
6923
6924 cdev = &ha->cdev;
6925
6926 rc = ecore_filter_ucast_cmd(cdev, &ucast, ECORE_SPQ_MODE_CB, NULL);
6927
6928 return (rc);
6929 }
6930
6931 static int
qlnx_remove_all_mcast_mac(qlnx_host_t * ha)6932 qlnx_remove_all_mcast_mac(qlnx_host_t *ha)
6933 {
6934 struct ecore_filter_mcast mcast;
6935 struct ecore_dev *cdev;
6936 int rc;
6937
6938 cdev = &ha->cdev;
6939
6940 bzero(&mcast, sizeof(struct ecore_filter_mcast));
6941 mcast.opcode = ECORE_FILTER_FLUSH;
6942
6943 rc = ecore_filter_mcast_cmd(cdev, &mcast, ECORE_SPQ_MODE_CB, NULL);
6944 if (rc == 0)
6945 bzero(ha->ecore_mcast_bins, sizeof(ha->ecore_mcast_bins));
6946
6947 return (rc);
6948 }
6949
6950 static int
qlnx_clean_filters(qlnx_host_t * ha)6951 qlnx_clean_filters(qlnx_host_t *ha)
6952 {
6953 int rc = 0;
6954
6955 /* Reset rx filter */
6956 ha->filter = 0;
6957
6958 /* Remove all unicast macs */
6959 rc = qlnx_remove_all_ucast_mac(ha);
6960 if (rc)
6961 return rc;
6962
6963 /* Remove all multicast macs */
6964 rc = qlnx_remove_all_mcast_mac(ha);
6965 if (rc)
6966 return rc;
6967
6968 rc = qlnx_set_ucast_rx_mac(ha, ECORE_FILTER_FLUSH, ha->primary_mac);
6969
6970 return (rc);
6971 }
6972
6973 static int
qlnx_set_rx_accept_filter(qlnx_host_t * ha,uint8_t filter)6974 qlnx_set_rx_accept_filter(qlnx_host_t *ha, uint8_t filter)
6975 {
6976 struct ecore_filter_accept_flags accept;
6977 int rc = 0;
6978 struct ecore_dev *cdev;
6979
6980 cdev = &ha->cdev;
6981
6982 bzero(&accept, sizeof(struct ecore_filter_accept_flags));
6983
6984 accept.update_rx_mode_config = 1;
6985 accept.rx_accept_filter = filter;
6986
6987 accept.update_tx_mode_config = 1;
6988 accept.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
6989 ECORE_ACCEPT_MCAST_MATCHED | ECORE_ACCEPT_BCAST;
6990
6991 rc = ecore_filter_accept_cmd(cdev, 0, accept, false, false,
6992 ECORE_SPQ_MODE_CB, NULL);
6993
6994 return (rc);
6995 }
6996
6997 static int
qlnx_set_rx_mode(qlnx_host_t * ha)6998 qlnx_set_rx_mode(qlnx_host_t *ha)
6999 {
7000 int rc = 0;
7001 const if_t ifp = ha->ifp;
7002
7003 rc = qlnx_set_ucast_rx_mac(ha, ECORE_FILTER_REPLACE, if_getlladdr(ifp));
7004 if (rc)
7005 return rc;
7006
7007 rc = qlnx_set_multi(ha);
7008 if (rc)
7009 return rc;
7010
7011 if (qlnx_vf_device(ha) == 0)
7012 rc = _qlnx_set_promisc_allmulti(ha, true, true);
7013 else
7014 rc = qlnx_set_promisc_allmulti(ha, if_getflags(ifp));
7015
7016 return (rc);
7017 }
7018
7019 static int
qlnx_set_link(qlnx_host_t * ha,bool link_up)7020 qlnx_set_link(qlnx_host_t *ha, bool link_up)
7021 {
7022 int i, rc = 0;
7023 struct ecore_dev *cdev;
7024 struct ecore_hwfn *hwfn;
7025 struct ecore_ptt *ptt;
7026
7027 if (qlnx_vf_device(ha) == 0)
7028 return (0);
7029
7030 cdev = &ha->cdev;
7031
7032 for_each_hwfn(cdev, i) {
7033 hwfn = &cdev->hwfns[i];
7034
7035 ptt = ecore_ptt_acquire(hwfn);
7036 if (!ptt)
7037 return -EBUSY;
7038
7039 rc = ecore_mcp_set_link(hwfn, ptt, link_up);
7040
7041 ecore_ptt_release(hwfn, ptt);
7042
7043 if (rc)
7044 return rc;
7045 }
7046 return (rc);
7047 }
7048
7049 static uint64_t
qlnx_get_counter(if_t ifp,ift_counter cnt)7050 qlnx_get_counter(if_t ifp, ift_counter cnt)
7051 {
7052 qlnx_host_t *ha;
7053 uint64_t count;
7054
7055 ha = (qlnx_host_t *)if_getsoftc(ifp);
7056
7057 switch (cnt) {
7058 case IFCOUNTER_IPACKETS:
7059 count = ha->hw_stats.common.rx_ucast_pkts +
7060 ha->hw_stats.common.rx_mcast_pkts +
7061 ha->hw_stats.common.rx_bcast_pkts;
7062 break;
7063
7064 case IFCOUNTER_IERRORS:
7065 count = ha->hw_stats.common.rx_crc_errors +
7066 ha->hw_stats.common.rx_align_errors +
7067 ha->hw_stats.common.rx_oversize_packets +
7068 ha->hw_stats.common.rx_undersize_packets;
7069 break;
7070
7071 case IFCOUNTER_OPACKETS:
7072 count = ha->hw_stats.common.tx_ucast_pkts +
7073 ha->hw_stats.common.tx_mcast_pkts +
7074 ha->hw_stats.common.tx_bcast_pkts;
7075 break;
7076
7077 case IFCOUNTER_OERRORS:
7078 count = ha->hw_stats.common.tx_err_drop_pkts;
7079 break;
7080
7081 case IFCOUNTER_COLLISIONS:
7082 return (0);
7083
7084 case IFCOUNTER_IBYTES:
7085 count = ha->hw_stats.common.rx_ucast_bytes +
7086 ha->hw_stats.common.rx_mcast_bytes +
7087 ha->hw_stats.common.rx_bcast_bytes;
7088 break;
7089
7090 case IFCOUNTER_OBYTES:
7091 count = ha->hw_stats.common.tx_ucast_bytes +
7092 ha->hw_stats.common.tx_mcast_bytes +
7093 ha->hw_stats.common.tx_bcast_bytes;
7094 break;
7095
7096 case IFCOUNTER_IMCASTS:
7097 count = ha->hw_stats.common.rx_mcast_bytes;
7098 break;
7099
7100 case IFCOUNTER_OMCASTS:
7101 count = ha->hw_stats.common.tx_mcast_bytes;
7102 break;
7103
7104 case IFCOUNTER_IQDROPS:
7105 case IFCOUNTER_OQDROPS:
7106 case IFCOUNTER_NOPROTO:
7107
7108 default:
7109 return (if_get_counter_default(ifp, cnt));
7110 }
7111 return (count);
7112 }
7113
7114 static void
qlnx_timer(void * arg)7115 qlnx_timer(void *arg)
7116 {
7117 qlnx_host_t *ha;
7118
7119 ha = (qlnx_host_t *)arg;
7120
7121 if (ha->error_recovery) {
7122 ha->error_recovery = 0;
7123 taskqueue_enqueue(ha->err_taskqueue, &ha->err_task);
7124 return;
7125 }
7126
7127 ecore_get_vport_stats(&ha->cdev, &ha->hw_stats);
7128
7129 if (ha->storm_stats_gather)
7130 qlnx_sample_storm_stats(ha);
7131
7132 callout_reset(&ha->qlnx_callout, hz, qlnx_timer, ha);
7133
7134 return;
7135 }
7136
7137 static int
qlnx_load(qlnx_host_t * ha)7138 qlnx_load(qlnx_host_t *ha)
7139 {
7140 int i;
7141 int rc = 0;
7142 device_t dev;
7143
7144 dev = ha->pci_dev;
7145
7146 QL_DPRINT2(ha, "enter\n");
7147
7148 rc = qlnx_alloc_mem_arrays(ha);
7149 if (rc)
7150 goto qlnx_load_exit0;
7151
7152 qlnx_init_fp(ha);
7153
7154 rc = qlnx_alloc_mem_load(ha);
7155 if (rc)
7156 goto qlnx_load_exit1;
7157
7158 QL_DPRINT2(ha, "Allocated %d RSS queues on %d TC/s\n",
7159 ha->num_rss, ha->num_tc);
7160
7161 for (i = 0; i < ha->num_rss; i++) {
7162 if ((rc = bus_setup_intr(dev, ha->irq_vec[i].irq,
7163 (INTR_TYPE_NET | INTR_MPSAFE),
7164 NULL, qlnx_fp_isr, &ha->irq_vec[i],
7165 &ha->irq_vec[i].handle))) {
7166 QL_DPRINT1(ha, "could not setup interrupt\n");
7167 goto qlnx_load_exit2;
7168 }
7169
7170 QL_DPRINT2(ha, "rss_id = %d irq_rid %d \
7171 irq %p handle %p\n", i,
7172 ha->irq_vec[i].irq_rid,
7173 ha->irq_vec[i].irq, ha->irq_vec[i].handle);
7174
7175 bus_bind_intr(dev, ha->irq_vec[i].irq, (i % mp_ncpus));
7176 }
7177
7178 rc = qlnx_start_queues(ha);
7179 if (rc)
7180 goto qlnx_load_exit2;
7181
7182 QL_DPRINT2(ha, "Start VPORT, RXQ and TXQ succeeded\n");
7183
7184 /* Add primary mac and set Rx filters */
7185 rc = qlnx_set_rx_mode(ha);
7186 if (rc)
7187 goto qlnx_load_exit2;
7188
7189 /* Ask for link-up using current configuration */
7190 qlnx_set_link(ha, true);
7191
7192 if (qlnx_vf_device(ha) == 0)
7193 qlnx_link_update(&ha->cdev.hwfns[0]);
7194
7195 ha->state = QLNX_STATE_OPEN;
7196
7197 bzero(&ha->hw_stats, sizeof(struct ecore_eth_stats));
7198
7199 if (ha->flags.callout_init)
7200 callout_reset(&ha->qlnx_callout, hz, qlnx_timer, ha);
7201
7202 goto qlnx_load_exit0;
7203
7204 qlnx_load_exit2:
7205 qlnx_free_mem_load(ha);
7206
7207 qlnx_load_exit1:
7208 ha->num_rss = 0;
7209
7210 qlnx_load_exit0:
7211 QL_DPRINT2(ha, "exit [%d]\n", rc);
7212 return rc;
7213 }
7214
7215 static void
qlnx_drain_soft_lro(qlnx_host_t * ha)7216 qlnx_drain_soft_lro(qlnx_host_t *ha)
7217 {
7218 #ifdef QLNX_SOFT_LRO
7219
7220 if_t ifp;
7221 int i;
7222
7223 ifp = ha->ifp;
7224
7225 if (if_getcapenable(ifp) & IFCAP_LRO) {
7226 for (i = 0; i < ha->num_rss; i++) {
7227 struct qlnx_fastpath *fp = &ha->fp_array[i];
7228 struct lro_ctrl *lro;
7229
7230 lro = &fp->rxq->lro;
7231
7232 tcp_lro_flush_all(lro);
7233 }
7234 }
7235
7236 #endif /* #ifdef QLNX_SOFT_LRO */
7237
7238 return;
7239 }
7240
7241 static void
qlnx_unload(qlnx_host_t * ha)7242 qlnx_unload(qlnx_host_t *ha)
7243 {
7244 struct ecore_dev *cdev;
7245 device_t dev;
7246 int i;
7247
7248 cdev = &ha->cdev;
7249 dev = ha->pci_dev;
7250
7251 QL_DPRINT2(ha, "enter\n");
7252 QL_DPRINT1(ha, " QLNX STATE = %d\n",ha->state);
7253
7254 if (ha->state == QLNX_STATE_OPEN) {
7255 qlnx_set_link(ha, false);
7256 qlnx_clean_filters(ha);
7257 qlnx_stop_queues(ha);
7258 ecore_hw_stop_fastpath(cdev);
7259
7260 for (i = 0; i < ha->num_rss; i++) {
7261 if (ha->irq_vec[i].handle) {
7262 (void)bus_teardown_intr(dev,
7263 ha->irq_vec[i].irq,
7264 ha->irq_vec[i].handle);
7265 ha->irq_vec[i].handle = NULL;
7266 }
7267 }
7268
7269 qlnx_drain_fp_taskqueues(ha);
7270 qlnx_drain_soft_lro(ha);
7271 qlnx_free_mem_load(ha);
7272 }
7273
7274 if (ha->flags.callout_init)
7275 callout_drain(&ha->qlnx_callout);
7276
7277 qlnx_mdelay(__func__, 1000);
7278
7279 ha->state = QLNX_STATE_CLOSED;
7280
7281 QL_DPRINT2(ha, "exit\n");
7282 return;
7283 }
7284
7285 static int
qlnx_grc_dumpsize(qlnx_host_t * ha,uint32_t * num_dwords,int hwfn_index)7286 qlnx_grc_dumpsize(qlnx_host_t *ha, uint32_t *num_dwords, int hwfn_index)
7287 {
7288 int rval = -1;
7289 struct ecore_hwfn *p_hwfn;
7290 struct ecore_ptt *p_ptt;
7291
7292 ecore_dbg_set_app_ver(ecore_dbg_get_fw_func_ver());
7293
7294 p_hwfn = &ha->cdev.hwfns[hwfn_index];
7295 p_ptt = ecore_ptt_acquire(p_hwfn);
7296
7297 if (!p_ptt) {
7298 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
7299 return (rval);
7300 }
7301
7302 rval = ecore_dbg_grc_get_dump_buf_size(p_hwfn, p_ptt, num_dwords);
7303
7304 if (rval == DBG_STATUS_OK)
7305 rval = 0;
7306 else {
7307 QL_DPRINT1(ha, "ecore_dbg_grc_get_dump_buf_size failed"
7308 "[0x%x]\n", rval);
7309 }
7310
7311 ecore_ptt_release(p_hwfn, p_ptt);
7312
7313 return (rval);
7314 }
7315
7316 static int
qlnx_idle_chk_size(qlnx_host_t * ha,uint32_t * num_dwords,int hwfn_index)7317 qlnx_idle_chk_size(qlnx_host_t *ha, uint32_t *num_dwords, int hwfn_index)
7318 {
7319 int rval = -1;
7320 struct ecore_hwfn *p_hwfn;
7321 struct ecore_ptt *p_ptt;
7322
7323 ecore_dbg_set_app_ver(ecore_dbg_get_fw_func_ver());
7324
7325 p_hwfn = &ha->cdev.hwfns[hwfn_index];
7326 p_ptt = ecore_ptt_acquire(p_hwfn);
7327
7328 if (!p_ptt) {
7329 QL_DPRINT1(ha, "ecore_ptt_acquire failed\n");
7330 return (rval);
7331 }
7332
7333 rval = ecore_dbg_idle_chk_get_dump_buf_size(p_hwfn, p_ptt, num_dwords);
7334
7335 if (rval == DBG_STATUS_OK)
7336 rval = 0;
7337 else {
7338 QL_DPRINT1(ha, "ecore_dbg_idle_chk_get_dump_buf_size failed"
7339 " [0x%x]\n", rval);
7340 }
7341
7342 ecore_ptt_release(p_hwfn, p_ptt);
7343
7344 return (rval);
7345 }
7346
7347 static void
qlnx_sample_storm_stats(qlnx_host_t * ha)7348 qlnx_sample_storm_stats(qlnx_host_t *ha)
7349 {
7350 int i, index;
7351 struct ecore_dev *cdev;
7352 qlnx_storm_stats_t *s_stats;
7353 uint32_t reg;
7354 struct ecore_ptt *p_ptt;
7355 struct ecore_hwfn *hwfn;
7356
7357 if (ha->storm_stats_index >= QLNX_STORM_STATS_SAMPLES_PER_HWFN) {
7358 ha->storm_stats_gather = 0;
7359 return;
7360 }
7361
7362 cdev = &ha->cdev;
7363
7364 for_each_hwfn(cdev, i) {
7365 hwfn = &cdev->hwfns[i];
7366
7367 p_ptt = ecore_ptt_acquire(hwfn);
7368 if (!p_ptt)
7369 return;
7370
7371 index = ha->storm_stats_index +
7372 (i * QLNX_STORM_STATS_SAMPLES_PER_HWFN);
7373
7374 s_stats = &ha->storm_stats[index];
7375
7376 /* XSTORM */
7377 reg = XSEM_REG_FAST_MEMORY +
7378 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7379 s_stats->xstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7380
7381 reg = XSEM_REG_FAST_MEMORY +
7382 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7383 s_stats->xstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7384
7385 reg = XSEM_REG_FAST_MEMORY +
7386 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7387 s_stats->xstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7388
7389 reg = XSEM_REG_FAST_MEMORY +
7390 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7391 s_stats->xstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7392
7393 /* YSTORM */
7394 reg = YSEM_REG_FAST_MEMORY +
7395 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7396 s_stats->ystorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7397
7398 reg = YSEM_REG_FAST_MEMORY +
7399 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7400 s_stats->ystorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7401
7402 reg = YSEM_REG_FAST_MEMORY +
7403 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7404 s_stats->ystorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7405
7406 reg = YSEM_REG_FAST_MEMORY +
7407 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7408 s_stats->ystorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7409
7410 /* PSTORM */
7411 reg = PSEM_REG_FAST_MEMORY +
7412 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7413 s_stats->pstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7414
7415 reg = PSEM_REG_FAST_MEMORY +
7416 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7417 s_stats->pstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7418
7419 reg = PSEM_REG_FAST_MEMORY +
7420 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7421 s_stats->pstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7422
7423 reg = PSEM_REG_FAST_MEMORY +
7424 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7425 s_stats->pstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7426
7427 /* TSTORM */
7428 reg = TSEM_REG_FAST_MEMORY +
7429 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7430 s_stats->tstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7431
7432 reg = TSEM_REG_FAST_MEMORY +
7433 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7434 s_stats->tstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7435
7436 reg = TSEM_REG_FAST_MEMORY +
7437 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7438 s_stats->tstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7439
7440 reg = TSEM_REG_FAST_MEMORY +
7441 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7442 s_stats->tstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7443
7444 /* MSTORM */
7445 reg = MSEM_REG_FAST_MEMORY +
7446 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7447 s_stats->mstorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7448
7449 reg = MSEM_REG_FAST_MEMORY +
7450 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7451 s_stats->mstorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7452
7453 reg = MSEM_REG_FAST_MEMORY +
7454 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7455 s_stats->mstorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7456
7457 reg = MSEM_REG_FAST_MEMORY +
7458 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7459 s_stats->mstorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7460
7461 /* USTORM */
7462 reg = USEM_REG_FAST_MEMORY +
7463 SEM_FAST_REG_STORM_ACTIVE_CYCLES_BB_K2;
7464 s_stats->ustorm_active_cycles = ecore_rd(hwfn, p_ptt, reg);
7465
7466 reg = USEM_REG_FAST_MEMORY +
7467 SEM_FAST_REG_STORM_STALL_CYCLES_BB_K2;
7468 s_stats->ustorm_stall_cycles = ecore_rd(hwfn, p_ptt, reg);
7469
7470 reg = USEM_REG_FAST_MEMORY +
7471 SEM_FAST_REG_IDLE_SLEEPING_CYCLES_BB_K2;
7472 s_stats->ustorm_sleeping_cycles = ecore_rd(hwfn, p_ptt, reg);
7473
7474 reg = USEM_REG_FAST_MEMORY +
7475 SEM_FAST_REG_IDLE_INACTIVE_CYCLES_BB_K2;
7476 s_stats->ustorm_inactive_cycles = ecore_rd(hwfn, p_ptt, reg);
7477
7478 ecore_ptt_release(hwfn, p_ptt);
7479 }
7480
7481 ha->storm_stats_index++;
7482
7483 return;
7484 }
7485
7486 /*
7487 * Name: qlnx_dump_buf8
7488 * Function: dumps a buffer as bytes
7489 */
7490 static void
qlnx_dump_buf8(qlnx_host_t * ha,const char * msg,void * dbuf,uint32_t len)7491 qlnx_dump_buf8(qlnx_host_t *ha, const char *msg, void *dbuf, uint32_t len)
7492 {
7493 device_t dev;
7494 uint32_t i = 0;
7495 uint8_t *buf;
7496
7497 dev = ha->pci_dev;
7498 buf = dbuf;
7499
7500 device_printf(dev, "%s: %s 0x%x dump start\n", __func__, msg, len);
7501
7502 while (len >= 16) {
7503 device_printf(dev,"0x%08x:"
7504 " %02x %02x %02x %02x %02x %02x %02x %02x"
7505 " %02x %02x %02x %02x %02x %02x %02x %02x\n", i,
7506 buf[0], buf[1], buf[2], buf[3],
7507 buf[4], buf[5], buf[6], buf[7],
7508 buf[8], buf[9], buf[10], buf[11],
7509 buf[12], buf[13], buf[14], buf[15]);
7510 i += 16;
7511 len -= 16;
7512 buf += 16;
7513 }
7514 switch (len) {
7515 case 1:
7516 device_printf(dev,"0x%08x: %02x\n", i, buf[0]);
7517 break;
7518 case 2:
7519 device_printf(dev,"0x%08x: %02x %02x\n", i, buf[0], buf[1]);
7520 break;
7521 case 3:
7522 device_printf(dev,"0x%08x: %02x %02x %02x\n",
7523 i, buf[0], buf[1], buf[2]);
7524 break;
7525 case 4:
7526 device_printf(dev,"0x%08x: %02x %02x %02x %02x\n", i,
7527 buf[0], buf[1], buf[2], buf[3]);
7528 break;
7529 case 5:
7530 device_printf(dev,"0x%08x:"
7531 " %02x %02x %02x %02x %02x\n", i,
7532 buf[0], buf[1], buf[2], buf[3], buf[4]);
7533 break;
7534 case 6:
7535 device_printf(dev,"0x%08x:"
7536 " %02x %02x %02x %02x %02x %02x\n", i,
7537 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
7538 break;
7539 case 7:
7540 device_printf(dev,"0x%08x:"
7541 " %02x %02x %02x %02x %02x %02x %02x\n", i,
7542 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]);
7543 break;
7544 case 8:
7545 device_printf(dev,"0x%08x:"
7546 " %02x %02x %02x %02x %02x %02x %02x %02x\n", i,
7547 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7548 buf[7]);
7549 break;
7550 case 9:
7551 device_printf(dev,"0x%08x:"
7552 " %02x %02x %02x %02x %02x %02x %02x %02x"
7553 " %02x\n", i,
7554 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7555 buf[7], buf[8]);
7556 break;
7557 case 10:
7558 device_printf(dev,"0x%08x:"
7559 " %02x %02x %02x %02x %02x %02x %02x %02x"
7560 " %02x %02x\n", i,
7561 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7562 buf[7], buf[8], buf[9]);
7563 break;
7564 case 11:
7565 device_printf(dev,"0x%08x:"
7566 " %02x %02x %02x %02x %02x %02x %02x %02x"
7567 " %02x %02x %02x\n", i,
7568 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7569 buf[7], buf[8], buf[9], buf[10]);
7570 break;
7571 case 12:
7572 device_printf(dev,"0x%08x:"
7573 " %02x %02x %02x %02x %02x %02x %02x %02x"
7574 " %02x %02x %02x %02x\n", i,
7575 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7576 buf[7], buf[8], buf[9], buf[10], buf[11]);
7577 break;
7578 case 13:
7579 device_printf(dev,"0x%08x:"
7580 " %02x %02x %02x %02x %02x %02x %02x %02x"
7581 " %02x %02x %02x %02x %02x\n", i,
7582 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7583 buf[7], buf[8], buf[9], buf[10], buf[11], buf[12]);
7584 break;
7585 case 14:
7586 device_printf(dev,"0x%08x:"
7587 " %02x %02x %02x %02x %02x %02x %02x %02x"
7588 " %02x %02x %02x %02x %02x %02x\n", i,
7589 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7590 buf[7], buf[8], buf[9], buf[10], buf[11], buf[12],
7591 buf[13]);
7592 break;
7593 case 15:
7594 device_printf(dev,"0x%08x:"
7595 " %02x %02x %02x %02x %02x %02x %02x %02x"
7596 " %02x %02x %02x %02x %02x %02x %02x\n", i,
7597 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
7598 buf[7], buf[8], buf[9], buf[10], buf[11], buf[12],
7599 buf[13], buf[14]);
7600 break;
7601 default:
7602 break;
7603 }
7604
7605 device_printf(dev, "%s: %s dump end\n", __func__, msg);
7606
7607 return;
7608 }
7609
7610 #ifdef CONFIG_ECORE_SRIOV
7611
7612 static void
__qlnx_osal_iov_vf_cleanup(struct ecore_hwfn * p_hwfn,uint8_t rel_vf_id)7613 __qlnx_osal_iov_vf_cleanup(struct ecore_hwfn *p_hwfn, uint8_t rel_vf_id)
7614 {
7615 struct ecore_public_vf_info *vf_info;
7616
7617 vf_info = ecore_iov_get_public_vf_info(p_hwfn, rel_vf_id, false);
7618
7619 if (!vf_info)
7620 return;
7621
7622 /* Clear the VF mac */
7623 memset(vf_info->forced_mac, 0, ETH_ALEN);
7624
7625 vf_info->forced_vlan = 0;
7626
7627 return;
7628 }
7629
7630 void
qlnx_osal_iov_vf_cleanup(void * p_hwfn,uint8_t relative_vf_id)7631 qlnx_osal_iov_vf_cleanup(void *p_hwfn, uint8_t relative_vf_id)
7632 {
7633 __qlnx_osal_iov_vf_cleanup(p_hwfn, relative_vf_id);
7634 return;
7635 }
7636
7637 static int
__qlnx_iov_chk_ucast(struct ecore_hwfn * p_hwfn,int vfid,struct ecore_filter_ucast * params)7638 __qlnx_iov_chk_ucast(struct ecore_hwfn *p_hwfn, int vfid,
7639 struct ecore_filter_ucast *params)
7640 {
7641 struct ecore_public_vf_info *vf;
7642
7643 if (!ecore_iov_vf_has_vport_instance(p_hwfn, vfid)) {
7644 QL_DPRINT1(((qlnx_host_t *)p_hwfn->p_dev),
7645 "VF[%d] vport not initialized\n", vfid);
7646 return ECORE_INVAL;
7647 }
7648
7649 vf = ecore_iov_get_public_vf_info(p_hwfn, vfid, true);
7650 if (!vf)
7651 return -EINVAL;
7652
7653 /* No real decision to make; Store the configured MAC */
7654 if (params->type == ECORE_FILTER_MAC ||
7655 params->type == ECORE_FILTER_MAC_VLAN)
7656 memcpy(params->mac, vf->forced_mac, ETH_ALEN);
7657
7658 return 0;
7659 }
7660
7661 int
qlnx_iov_chk_ucast(void * p_hwfn,int vfid,void * params)7662 qlnx_iov_chk_ucast(void *p_hwfn, int vfid, void *params)
7663 {
7664 return (__qlnx_iov_chk_ucast(p_hwfn, vfid, params));
7665 }
7666
7667 static int
__qlnx_iov_update_vport(struct ecore_hwfn * hwfn,uint8_t vfid,struct ecore_sp_vport_update_params * params,uint16_t * tlvs)7668 __qlnx_iov_update_vport(struct ecore_hwfn *hwfn, uint8_t vfid,
7669 struct ecore_sp_vport_update_params *params, uint16_t * tlvs)
7670 {
7671 if (!ecore_iov_vf_has_vport_instance(hwfn, vfid)) {
7672 QL_DPRINT1(((qlnx_host_t *)hwfn->p_dev),
7673 "VF[%d] vport not initialized\n", vfid);
7674 return ECORE_INVAL;
7675 }
7676
7677 /* Untrusted VFs can't even be trusted to know that fact.
7678 * Simply indicate everything is configured fine, and trace
7679 * configuration 'behind their back'.
7680 */
7681 if (!(*tlvs & BIT(ECORE_IOV_VP_UPDATE_ACCEPT_PARAM)))
7682 return 0;
7683
7684 return 0;
7685
7686 }
7687 int
qlnx_iov_update_vport(void * hwfn,uint8_t vfid,void * params,uint16_t * tlvs)7688 qlnx_iov_update_vport(void *hwfn, uint8_t vfid, void *params, uint16_t *tlvs)
7689 {
7690 return(__qlnx_iov_update_vport(hwfn, vfid, params, tlvs));
7691 }
7692
7693 static int
qlnx_find_hwfn_index(struct ecore_hwfn * p_hwfn)7694 qlnx_find_hwfn_index(struct ecore_hwfn *p_hwfn)
7695 {
7696 int i;
7697 struct ecore_dev *cdev;
7698
7699 cdev = p_hwfn->p_dev;
7700
7701 for (i = 0; i < cdev->num_hwfns; i++) {
7702 if (&cdev->hwfns[i] == p_hwfn)
7703 break;
7704 }
7705
7706 if (i >= cdev->num_hwfns)
7707 return (-1);
7708
7709 return (i);
7710 }
7711
7712 static int
__qlnx_pf_vf_msg(struct ecore_hwfn * p_hwfn,uint16_t rel_vf_id)7713 __qlnx_pf_vf_msg(struct ecore_hwfn *p_hwfn, uint16_t rel_vf_id)
7714 {
7715 qlnx_host_t *ha = (qlnx_host_t *)p_hwfn->p_dev;
7716 int i;
7717
7718 QL_DPRINT2(ha, "ha = %p cdev = %p p_hwfn = %p rel_vf_id = %d\n",
7719 ha, p_hwfn->p_dev, p_hwfn, rel_vf_id);
7720
7721 if ((i = qlnx_find_hwfn_index(p_hwfn)) == -1)
7722 return (-1);
7723
7724 if (ha->sriov_task[i].pf_taskqueue != NULL) {
7725 atomic_testandset_32(&ha->sriov_task[i].flags,
7726 QLNX_SRIOV_TASK_FLAGS_VF_PF_MSG);
7727
7728 taskqueue_enqueue(ha->sriov_task[i].pf_taskqueue,
7729 &ha->sriov_task[i].pf_task);
7730 }
7731
7732 return (ECORE_SUCCESS);
7733 }
7734
7735 int
qlnx_pf_vf_msg(void * p_hwfn,uint16_t relative_vf_id)7736 qlnx_pf_vf_msg(void *p_hwfn, uint16_t relative_vf_id)
7737 {
7738 return (__qlnx_pf_vf_msg(p_hwfn, relative_vf_id));
7739 }
7740
7741 static void
__qlnx_vf_flr_update(struct ecore_hwfn * p_hwfn)7742 __qlnx_vf_flr_update(struct ecore_hwfn *p_hwfn)
7743 {
7744 qlnx_host_t *ha = (qlnx_host_t *)p_hwfn->p_dev;
7745 int i;
7746
7747 if (!ha->sriov_initialized)
7748 return;
7749
7750 QL_DPRINT2(ha, "ha = %p cdev = %p p_hwfn = %p \n",
7751 ha, p_hwfn->p_dev, p_hwfn);
7752
7753 if ((i = qlnx_find_hwfn_index(p_hwfn)) == -1)
7754 return;
7755
7756 if (ha->sriov_task[i].pf_taskqueue != NULL) {
7757 atomic_testandset_32(&ha->sriov_task[i].flags,
7758 QLNX_SRIOV_TASK_FLAGS_VF_FLR_UPDATE);
7759
7760 taskqueue_enqueue(ha->sriov_task[i].pf_taskqueue,
7761 &ha->sriov_task[i].pf_task);
7762 }
7763
7764 return;
7765 }
7766
7767 void
qlnx_vf_flr_update(void * p_hwfn)7768 qlnx_vf_flr_update(void *p_hwfn)
7769 {
7770 __qlnx_vf_flr_update(p_hwfn);
7771
7772 return;
7773 }
7774
7775 #ifndef QLNX_VF
7776
7777 static void
qlnx_vf_bulleting_update(struct ecore_hwfn * p_hwfn)7778 qlnx_vf_bulleting_update(struct ecore_hwfn *p_hwfn)
7779 {
7780 qlnx_host_t *ha = (qlnx_host_t *)p_hwfn->p_dev;
7781 int i;
7782
7783 QL_DPRINT2(ha, "ha = %p cdev = %p p_hwfn = %p \n",
7784 ha, p_hwfn->p_dev, p_hwfn);
7785
7786 if ((i = qlnx_find_hwfn_index(p_hwfn)) == -1)
7787 return;
7788
7789 QL_DPRINT2(ha, "ha = %p cdev = %p p_hwfn = %p i = %d\n",
7790 ha, p_hwfn->p_dev, p_hwfn, i);
7791
7792 if (ha->sriov_task[i].pf_taskqueue != NULL) {
7793 atomic_testandset_32(&ha->sriov_task[i].flags,
7794 QLNX_SRIOV_TASK_FLAGS_BULLETIN_UPDATE);
7795
7796 taskqueue_enqueue(ha->sriov_task[i].pf_taskqueue,
7797 &ha->sriov_task[i].pf_task);
7798 }
7799 }
7800
7801 static void
qlnx_initialize_sriov(qlnx_host_t * ha)7802 qlnx_initialize_sriov(qlnx_host_t *ha)
7803 {
7804 device_t dev;
7805 nvlist_t *pf_schema, *vf_schema;
7806 int iov_error;
7807
7808 dev = ha->pci_dev;
7809
7810 pf_schema = pci_iov_schema_alloc_node();
7811 vf_schema = pci_iov_schema_alloc_node();
7812
7813 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL);
7814 pci_iov_schema_add_bool(vf_schema, "allow-set-mac",
7815 IOV_SCHEMA_HASDEFAULT, FALSE);
7816 pci_iov_schema_add_bool(vf_schema, "allow-promisc",
7817 IOV_SCHEMA_HASDEFAULT, FALSE);
7818 pci_iov_schema_add_uint16(vf_schema, "num-queues",
7819 IOV_SCHEMA_HASDEFAULT, 1);
7820
7821 iov_error = pci_iov_attach(dev, pf_schema, vf_schema);
7822
7823 if (iov_error != 0) {
7824 ha->sriov_initialized = 0;
7825 } else {
7826 device_printf(dev, "SRIOV initialized\n");
7827 ha->sriov_initialized = 1;
7828 }
7829
7830 return;
7831 }
7832
7833 static void
qlnx_sriov_disable(qlnx_host_t * ha)7834 qlnx_sriov_disable(qlnx_host_t *ha)
7835 {
7836 struct ecore_dev *cdev;
7837 int i, j;
7838
7839 cdev = &ha->cdev;
7840
7841 ecore_iov_set_vfs_to_disable(cdev, true);
7842
7843 for_each_hwfn(cdev, i) {
7844 struct ecore_hwfn *hwfn = &cdev->hwfns[i];
7845 struct ecore_ptt *ptt = ecore_ptt_acquire(hwfn);
7846
7847 if (!ptt) {
7848 QL_DPRINT1(ha, "Failed to acquire ptt\n");
7849 return;
7850 }
7851 /* Clean WFQ db and configure equal weight for all vports */
7852 ecore_clean_wfq_db(hwfn, ptt);
7853
7854 ecore_for_each_vf(hwfn, j) {
7855 int k = 0;
7856
7857 if (!ecore_iov_is_valid_vfid(hwfn, j, true, false))
7858 continue;
7859
7860 if (ecore_iov_is_vf_started(hwfn, j)) {
7861 /* Wait until VF is disabled before releasing */
7862
7863 for (k = 0; k < 100; k++) {
7864 if (!ecore_iov_is_vf_stopped(hwfn, j)) {
7865 qlnx_mdelay(__func__, 10);
7866 } else
7867 break;
7868 }
7869 }
7870
7871 if (k < 100)
7872 ecore_iov_release_hw_for_vf(&cdev->hwfns[i],
7873 ptt, j);
7874 else {
7875 QL_DPRINT1(ha,
7876 "Timeout waiting for VF's FLR to end\n");
7877 }
7878 }
7879 ecore_ptt_release(hwfn, ptt);
7880 }
7881
7882 ecore_iov_set_vfs_to_disable(cdev, false);
7883
7884 return;
7885 }
7886
7887 static void
qlnx_sriov_enable_qid_config(struct ecore_hwfn * hwfn,u16 vfid,struct ecore_iov_vf_init_params * params)7888 qlnx_sriov_enable_qid_config(struct ecore_hwfn *hwfn, u16 vfid,
7889 struct ecore_iov_vf_init_params *params)
7890 {
7891 u16 base, i;
7892
7893 /* Since we have an equal resource distribution per-VF, and we assume
7894 * PF has acquired the ECORE_PF_L2_QUE first queues, we start setting
7895 * sequentially from there.
7896 */
7897 base = FEAT_NUM(hwfn, ECORE_PF_L2_QUE) + vfid * params->num_queues;
7898
7899 params->rel_vf_id = vfid;
7900
7901 for (i = 0; i < params->num_queues; i++) {
7902 params->req_rx_queue[i] = base + i;
7903 params->req_tx_queue[i] = base + i;
7904 }
7905
7906 /* PF uses indices 0 for itself; Set vport/RSS afterwards */
7907 params->vport_id = vfid + 1;
7908 params->rss_eng_id = vfid + 1;
7909
7910 return;
7911 }
7912
7913 static int
qlnx_iov_init(device_t dev,uint16_t num_vfs,const nvlist_t * nvlist_params)7914 qlnx_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *nvlist_params)
7915 {
7916 qlnx_host_t *ha;
7917 struct ecore_dev *cdev;
7918 struct ecore_iov_vf_init_params params;
7919 int ret, j, i;
7920 uint32_t max_vfs;
7921
7922 if ((ha = device_get_softc(dev)) == NULL) {
7923 device_printf(dev, "%s: cannot get softc\n", __func__);
7924 return (-1);
7925 }
7926
7927 if (qlnx_create_pf_taskqueues(ha) != 0)
7928 goto qlnx_iov_init_err0;
7929
7930 cdev = &ha->cdev;
7931
7932 max_vfs = RESC_NUM(&cdev->hwfns[0], ECORE_VPORT);
7933
7934 QL_DPRINT2(ha," dev = %p enter num_vfs = %d max_vfs = %d\n",
7935 dev, num_vfs, max_vfs);
7936
7937 if (num_vfs >= max_vfs) {
7938 QL_DPRINT1(ha, "Can start at most %d VFs\n",
7939 (RESC_NUM(&cdev->hwfns[0], ECORE_VPORT) - 1));
7940 goto qlnx_iov_init_err0;
7941 }
7942
7943 ha->vf_attr = malloc(((sizeof (qlnx_vf_attr_t) * num_vfs)), M_QLNXBUF,
7944 M_NOWAIT);
7945
7946 if (ha->vf_attr == NULL)
7947 goto qlnx_iov_init_err0;
7948
7949 memset(¶ms, 0, sizeof(params));
7950
7951 /* Initialize HW for VF access */
7952 for_each_hwfn(cdev, j) {
7953 struct ecore_hwfn *hwfn = &cdev->hwfns[j];
7954 struct ecore_ptt *ptt = ecore_ptt_acquire(hwfn);
7955
7956 /* Make sure not to use more than 16 queues per VF */
7957 params.num_queues = min_t(int,
7958 (FEAT_NUM(hwfn, ECORE_VF_L2_QUE) / num_vfs),
7959 16);
7960
7961 if (!ptt) {
7962 QL_DPRINT1(ha, "Failed to acquire ptt\n");
7963 goto qlnx_iov_init_err1;
7964 }
7965
7966 for (i = 0; i < num_vfs; i++) {
7967 if (!ecore_iov_is_valid_vfid(hwfn, i, false, true))
7968 continue;
7969
7970 qlnx_sriov_enable_qid_config(hwfn, i, ¶ms);
7971
7972 ret = ecore_iov_init_hw_for_vf(hwfn, ptt, ¶ms);
7973
7974 if (ret) {
7975 QL_DPRINT1(ha, "Failed to enable VF[%d]\n", i);
7976 ecore_ptt_release(hwfn, ptt);
7977 goto qlnx_iov_init_err1;
7978 }
7979 }
7980
7981 ecore_ptt_release(hwfn, ptt);
7982 }
7983
7984 ha->num_vfs = num_vfs;
7985 qlnx_inform_vf_link_state(&cdev->hwfns[0], ha);
7986
7987 QL_DPRINT2(ha," dev = %p exit num_vfs = %d\n", dev, num_vfs);
7988
7989 return (0);
7990
7991 qlnx_iov_init_err1:
7992 qlnx_sriov_disable(ha);
7993
7994 qlnx_iov_init_err0:
7995 qlnx_destroy_pf_taskqueues(ha);
7996 ha->num_vfs = 0;
7997
7998 return (-1);
7999 }
8000
8001 static void
qlnx_iov_uninit(device_t dev)8002 qlnx_iov_uninit(device_t dev)
8003 {
8004 qlnx_host_t *ha;
8005
8006 if ((ha = device_get_softc(dev)) == NULL) {
8007 device_printf(dev, "%s: cannot get softc\n", __func__);
8008 return;
8009 }
8010
8011 QL_DPRINT2(ha," dev = %p enter\n", dev);
8012
8013 qlnx_sriov_disable(ha);
8014 qlnx_destroy_pf_taskqueues(ha);
8015
8016 free(ha->vf_attr, M_QLNXBUF);
8017 ha->vf_attr = NULL;
8018
8019 ha->num_vfs = 0;
8020
8021 QL_DPRINT2(ha," dev = %p exit\n", dev);
8022 return;
8023 }
8024
8025 static int
qlnx_iov_add_vf(device_t dev,uint16_t vfnum,const nvlist_t * params)8026 qlnx_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
8027 {
8028 qlnx_host_t *ha;
8029 qlnx_vf_attr_t *vf_attr;
8030 unsigned const char *mac;
8031 size_t size;
8032 struct ecore_hwfn *p_hwfn;
8033
8034 if ((ha = device_get_softc(dev)) == NULL) {
8035 device_printf(dev, "%s: cannot get softc\n", __func__);
8036 return (-1);
8037 }
8038
8039 QL_DPRINT2(ha," dev = %p enter vfnum = %d\n", dev, vfnum);
8040
8041 if (vfnum > (ha->num_vfs - 1)) {
8042 QL_DPRINT1(ha, " VF[%d] is greater than max allowed [%d]\n",
8043 vfnum, (ha->num_vfs - 1));
8044 }
8045
8046 vf_attr = &ha->vf_attr[vfnum];
8047
8048 if (nvlist_exists_binary(params, "mac-addr")) {
8049 mac = nvlist_get_binary(params, "mac-addr", &size);
8050 bcopy(mac, vf_attr->mac_addr, ETHER_ADDR_LEN);
8051 device_printf(dev,
8052 "%s: mac_addr = %02x:%02x:%02x:%02x:%02x:%02x\n",
8053 __func__, vf_attr->mac_addr[0],
8054 vf_attr->mac_addr[1], vf_attr->mac_addr[2],
8055 vf_attr->mac_addr[3], vf_attr->mac_addr[4],
8056 vf_attr->mac_addr[5]);
8057 p_hwfn = &ha->cdev.hwfns[0];
8058 ecore_iov_bulletin_set_mac(p_hwfn, vf_attr->mac_addr,
8059 vfnum);
8060 }
8061
8062 QL_DPRINT2(ha," dev = %p exit vfnum = %d\n", dev, vfnum);
8063 return (0);
8064 }
8065
8066 static void
qlnx_handle_vf_msg(qlnx_host_t * ha,struct ecore_hwfn * p_hwfn)8067 qlnx_handle_vf_msg(qlnx_host_t *ha, struct ecore_hwfn *p_hwfn)
8068 {
8069 uint64_t events[ECORE_VF_ARRAY_LENGTH];
8070 struct ecore_ptt *ptt;
8071 int i;
8072
8073 ptt = ecore_ptt_acquire(p_hwfn);
8074 if (!ptt) {
8075 QL_DPRINT1(ha, "Can't acquire PTT; re-scheduling\n");
8076 __qlnx_pf_vf_msg(p_hwfn, 0);
8077 return;
8078 }
8079
8080 ecore_iov_pf_get_pending_events(p_hwfn, events);
8081
8082 QL_DPRINT2(ha, "Event mask of VF events:"
8083 "0x%" PRIu64 "0x%" PRIu64 " 0x%" PRIu64 "\n",
8084 events[0], events[1], events[2]);
8085
8086 ecore_for_each_vf(p_hwfn, i) {
8087 /* Skip VFs with no pending messages */
8088 if (!(events[i / 64] & (1ULL << (i % 64))))
8089 continue;
8090
8091 QL_DPRINT2(ha,
8092 "Handling VF message from VF 0x%02x [Abs 0x%02x]\n",
8093 i, p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
8094
8095 /* Copy VF's message to PF's request buffer for that VF */
8096 if (ecore_iov_copy_vf_msg(p_hwfn, ptt, i))
8097 continue;
8098
8099 ecore_iov_process_mbx_req(p_hwfn, ptt, i);
8100 }
8101
8102 ecore_ptt_release(p_hwfn, ptt);
8103
8104 return;
8105 }
8106
8107 static void
qlnx_handle_vf_flr_update(qlnx_host_t * ha,struct ecore_hwfn * p_hwfn)8108 qlnx_handle_vf_flr_update(qlnx_host_t *ha, struct ecore_hwfn *p_hwfn)
8109 {
8110 struct ecore_ptt *ptt;
8111 int ret;
8112
8113 ptt = ecore_ptt_acquire(p_hwfn);
8114
8115 if (!ptt) {
8116 QL_DPRINT1(ha, "Can't acquire PTT; re-scheduling\n");
8117 __qlnx_vf_flr_update(p_hwfn);
8118 return;
8119 }
8120
8121 ret = ecore_iov_vf_flr_cleanup(p_hwfn, ptt);
8122
8123 if (ret) {
8124 QL_DPRINT1(ha, "ecore_iov_vf_flr_cleanup failed; re-scheduling\n");
8125 }
8126
8127 ecore_ptt_release(p_hwfn, ptt);
8128
8129 return;
8130 }
8131
8132 static void
qlnx_handle_bulletin_update(qlnx_host_t * ha,struct ecore_hwfn * p_hwfn)8133 qlnx_handle_bulletin_update(qlnx_host_t *ha, struct ecore_hwfn *p_hwfn)
8134 {
8135 struct ecore_ptt *ptt;
8136 int i;
8137
8138 ptt = ecore_ptt_acquire(p_hwfn);
8139
8140 if (!ptt) {
8141 QL_DPRINT1(ha, "Can't acquire PTT; re-scheduling\n");
8142 qlnx_vf_bulleting_update(p_hwfn);
8143 return;
8144 }
8145
8146 ecore_for_each_vf(p_hwfn, i) {
8147 QL_DPRINT1(ha, "ecore_iov_post_vf_bulletin[%p, %d]\n",
8148 p_hwfn, i);
8149 ecore_iov_post_vf_bulletin(p_hwfn, i, ptt);
8150 }
8151
8152 ecore_ptt_release(p_hwfn, ptt);
8153
8154 return;
8155 }
8156
8157 static void
qlnx_pf_taskqueue(void * context,int pending)8158 qlnx_pf_taskqueue(void *context, int pending)
8159 {
8160 struct ecore_hwfn *p_hwfn;
8161 qlnx_host_t *ha;
8162 int i;
8163
8164 p_hwfn = context;
8165
8166 if (p_hwfn == NULL)
8167 return;
8168
8169 ha = (qlnx_host_t *)(p_hwfn->p_dev);
8170
8171 if ((i = qlnx_find_hwfn_index(p_hwfn)) == -1)
8172 return;
8173
8174 if (atomic_testandclear_32(&ha->sriov_task[i].flags,
8175 QLNX_SRIOV_TASK_FLAGS_VF_PF_MSG))
8176 qlnx_handle_vf_msg(ha, p_hwfn);
8177
8178 if (atomic_testandclear_32(&ha->sriov_task[i].flags,
8179 QLNX_SRIOV_TASK_FLAGS_VF_FLR_UPDATE))
8180 qlnx_handle_vf_flr_update(ha, p_hwfn);
8181
8182 if (atomic_testandclear_32(&ha->sriov_task[i].flags,
8183 QLNX_SRIOV_TASK_FLAGS_BULLETIN_UPDATE))
8184 qlnx_handle_bulletin_update(ha, p_hwfn);
8185
8186 return;
8187 }
8188
8189 static int
qlnx_create_pf_taskqueues(qlnx_host_t * ha)8190 qlnx_create_pf_taskqueues(qlnx_host_t *ha)
8191 {
8192 int i;
8193 uint8_t tq_name[32];
8194
8195 for (i = 0; i < ha->cdev.num_hwfns; i++) {
8196 struct ecore_hwfn *p_hwfn = &ha->cdev.hwfns[i];
8197
8198 bzero(tq_name, sizeof (tq_name));
8199 snprintf(tq_name, sizeof (tq_name), "ql_pf_tq_%d", i);
8200
8201 TASK_INIT(&ha->sriov_task[i].pf_task, 0, qlnx_pf_taskqueue, p_hwfn);
8202
8203 ha->sriov_task[i].pf_taskqueue = taskqueue_create(tq_name, M_NOWAIT,
8204 taskqueue_thread_enqueue,
8205 &ha->sriov_task[i].pf_taskqueue);
8206
8207 if (ha->sriov_task[i].pf_taskqueue == NULL)
8208 return (-1);
8209
8210 taskqueue_start_threads(&ha->sriov_task[i].pf_taskqueue, 1,
8211 PI_NET, "%s", tq_name);
8212
8213 QL_DPRINT1(ha, "%p\n", ha->sriov_task[i].pf_taskqueue);
8214 }
8215
8216 return (0);
8217 }
8218
8219 static void
qlnx_destroy_pf_taskqueues(qlnx_host_t * ha)8220 qlnx_destroy_pf_taskqueues(qlnx_host_t *ha)
8221 {
8222 int i;
8223
8224 for (i = 0; i < ha->cdev.num_hwfns; i++) {
8225 if (ha->sriov_task[i].pf_taskqueue != NULL) {
8226 taskqueue_drain(ha->sriov_task[i].pf_taskqueue,
8227 &ha->sriov_task[i].pf_task);
8228 taskqueue_free(ha->sriov_task[i].pf_taskqueue);
8229 ha->sriov_task[i].pf_taskqueue = NULL;
8230 }
8231 }
8232 return;
8233 }
8234
8235 static void
qlnx_inform_vf_link_state(struct ecore_hwfn * p_hwfn,qlnx_host_t * ha)8236 qlnx_inform_vf_link_state(struct ecore_hwfn *p_hwfn, qlnx_host_t *ha)
8237 {
8238 struct ecore_mcp_link_capabilities caps;
8239 struct ecore_mcp_link_params params;
8240 struct ecore_mcp_link_state link;
8241 int i;
8242
8243 if (!p_hwfn->pf_iov_info)
8244 return;
8245
8246 memset(¶ms, 0, sizeof(struct ecore_mcp_link_params));
8247 memset(&link, 0, sizeof(struct ecore_mcp_link_state));
8248 memset(&caps, 0, sizeof(struct ecore_mcp_link_capabilities));
8249
8250 memcpy(&caps, ecore_mcp_get_link_capabilities(p_hwfn), sizeof(caps));
8251 memcpy(&link, ecore_mcp_get_link_state(p_hwfn), sizeof(link));
8252 memcpy(¶ms, ecore_mcp_get_link_params(p_hwfn), sizeof(params));
8253
8254 QL_DPRINT2(ha, "called\n");
8255
8256 /* Update bulletin of all future possible VFs with link configuration */
8257 for (i = 0; i < p_hwfn->p_dev->p_iov_info->total_vfs; i++) {
8258 /* Modify link according to the VF's configured link state */
8259
8260 link.link_up = false;
8261
8262 if (ha->link_up) {
8263 link.link_up = true;
8264 /* Set speed according to maximum supported by HW.
8265 * that is 40G for regular devices and 100G for CMT
8266 * mode devices.
8267 */
8268 link.speed = (p_hwfn->p_dev->num_hwfns > 1) ?
8269 100000 : link.speed;
8270 }
8271 QL_DPRINT2(ha, "link [%d] = %d\n", i, link.link_up);
8272 ecore_iov_set_link(p_hwfn, i, ¶ms, &link, &caps);
8273 }
8274
8275 qlnx_vf_bulleting_update(p_hwfn);
8276
8277 return;
8278 }
8279 #endif /* #ifndef QLNX_VF */
8280 #endif /* #ifdef CONFIG_ECORE_SRIOV */
8281