1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/dts-v1/; 5#include "dt-bindings/clock/microchip,mpfs-clock.h" 6 7/ { 8 #address-cells = <2>; 9 #size-cells = <2>; 10 model = "Microchip PolarFire SoC"; 11 compatible = "microchip,mpfs"; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 timebase-frequency = <1000000>; 17 18 cpu0: cpu@0 { 19 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 20 device_type = "cpu"; 21 i-cache-block-size = <64>; 22 i-cache-sets = <128>; 23 i-cache-size = <16384>; 24 reg = <0>; 25 riscv,isa = "rv64imac"; 26 riscv,isa-base = "rv64i"; 27 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", 28 "zihpm"; 29 clocks = <&clkcfg CLK_CPU>; 30 status = "disabled"; 31 32 cpu0_intc: interrupt-controller { 33 #interrupt-cells = <1>; 34 compatible = "riscv,cpu-intc"; 35 interrupt-controller; 36 }; 37 }; 38 39 cpu1: cpu@1 { 40 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 41 d-cache-block-size = <64>; 42 d-cache-sets = <64>; 43 d-cache-size = <32768>; 44 d-tlb-sets = <1>; 45 d-tlb-size = <32>; 46 device_type = "cpu"; 47 i-cache-block-size = <64>; 48 i-cache-sets = <64>; 49 i-cache-size = <32768>; 50 i-tlb-sets = <1>; 51 i-tlb-size = <32>; 52 mmu-type = "riscv,sv39"; 53 reg = <1>; 54 riscv,isa = "rv64imafdc"; 55 riscv,isa-base = "rv64i"; 56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 57 "zifencei", "zihpm"; 58 clocks = <&clkcfg CLK_CPU>; 59 tlb-split; 60 next-level-cache = <&cctrllr>; 61 status = "okay"; 62 63 cpu1_intc: interrupt-controller { 64 #interrupt-cells = <1>; 65 compatible = "riscv,cpu-intc"; 66 interrupt-controller; 67 }; 68 }; 69 70 cpu2: cpu@2 { 71 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 72 d-cache-block-size = <64>; 73 d-cache-sets = <64>; 74 d-cache-size = <32768>; 75 d-tlb-sets = <1>; 76 d-tlb-size = <32>; 77 device_type = "cpu"; 78 i-cache-block-size = <64>; 79 i-cache-sets = <64>; 80 i-cache-size = <32768>; 81 i-tlb-sets = <1>; 82 i-tlb-size = <32>; 83 mmu-type = "riscv,sv39"; 84 reg = <2>; 85 riscv,isa = "rv64imafdc"; 86 riscv,isa-base = "rv64i"; 87 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 88 "zifencei", "zihpm"; 89 clocks = <&clkcfg CLK_CPU>; 90 tlb-split; 91 next-level-cache = <&cctrllr>; 92 status = "okay"; 93 94 cpu2_intc: interrupt-controller { 95 #interrupt-cells = <1>; 96 compatible = "riscv,cpu-intc"; 97 interrupt-controller; 98 }; 99 }; 100 101 cpu3: cpu@3 { 102 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 103 d-cache-block-size = <64>; 104 d-cache-sets = <64>; 105 d-cache-size = <32768>; 106 d-tlb-sets = <1>; 107 d-tlb-size = <32>; 108 device_type = "cpu"; 109 i-cache-block-size = <64>; 110 i-cache-sets = <64>; 111 i-cache-size = <32768>; 112 i-tlb-sets = <1>; 113 i-tlb-size = <32>; 114 mmu-type = "riscv,sv39"; 115 reg = <3>; 116 riscv,isa = "rv64imafdc"; 117 riscv,isa-base = "rv64i"; 118 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 119 "zifencei", "zihpm"; 120 clocks = <&clkcfg CLK_CPU>; 121 tlb-split; 122 next-level-cache = <&cctrllr>; 123 status = "okay"; 124 125 cpu3_intc: interrupt-controller { 126 #interrupt-cells = <1>; 127 compatible = "riscv,cpu-intc"; 128 interrupt-controller; 129 }; 130 }; 131 132 cpu4: cpu@4 { 133 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 134 d-cache-block-size = <64>; 135 d-cache-sets = <64>; 136 d-cache-size = <32768>; 137 d-tlb-sets = <1>; 138 d-tlb-size = <32>; 139 device_type = "cpu"; 140 i-cache-block-size = <64>; 141 i-cache-sets = <64>; 142 i-cache-size = <32768>; 143 i-tlb-sets = <1>; 144 i-tlb-size = <32>; 145 mmu-type = "riscv,sv39"; 146 reg = <4>; 147 riscv,isa = "rv64imafdc"; 148 riscv,isa-base = "rv64i"; 149 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 150 "zifencei", "zihpm"; 151 clocks = <&clkcfg CLK_CPU>; 152 tlb-split; 153 next-level-cache = <&cctrllr>; 154 status = "okay"; 155 cpu4_intc: interrupt-controller { 156 #interrupt-cells = <1>; 157 compatible = "riscv,cpu-intc"; 158 interrupt-controller; 159 }; 160 }; 161 162 cpu-map { 163 cluster0 { 164 core0 { 165 cpu = <&cpu0>; 166 }; 167 168 core1 { 169 cpu = <&cpu1>; 170 }; 171 172 core2 { 173 cpu = <&cpu2>; 174 }; 175 176 core3 { 177 cpu = <&cpu3>; 178 }; 179 180 core4 { 181 cpu = <&cpu4>; 182 }; 183 }; 184 }; 185 }; 186 187 refclk: mssrefclk { 188 compatible = "fixed-clock"; 189 #clock-cells = <0>; 190 }; 191 192 syscontroller: syscontroller { 193 compatible = "microchip,mpfs-sys-controller"; 194 mboxes = <&mbox 0>; 195 }; 196 197 scbclk: mssclkclk { 198 compatible = "fixed-clock"; 199 #clock-cells = <0>; 200 clock-frequency = <80000000>; 201 }; 202 203 soc { 204 #address-cells = <2>; 205 #size-cells = <2>; 206 compatible = "simple-bus"; 207 ranges; 208 209 cctrllr: cache-controller@2010000 { 210 compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache"; 211 reg = <0x0 0x2010000 0x0 0x1000>; 212 cache-block-size = <64>; 213 cache-level = <2>; 214 cache-sets = <1024>; 215 cache-size = <2097152>; 216 cache-unified; 217 interrupt-parent = <&plic>; 218 interrupts = <1>, <3>, <4>, <2>; 219 }; 220 221 clint: clint@2000000 { 222 compatible = "sifive,fu540-c000-clint", "sifive,clint0"; 223 reg = <0x0 0x2000000 0x0 0xC000>; 224 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 225 <&cpu1_intc 3>, <&cpu1_intc 7>, 226 <&cpu2_intc 3>, <&cpu2_intc 7>, 227 <&cpu3_intc 3>, <&cpu3_intc 7>, 228 <&cpu4_intc 3>, <&cpu4_intc 7>; 229 }; 230 231 plic: interrupt-controller@c000000 { 232 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 233 reg = <0x0 0xc000000 0x0 0x4000000>; 234 #address-cells = <0>; 235 #interrupt-cells = <1>; 236 interrupt-controller; 237 interrupts-extended = <&cpu0_intc 11>, 238 <&cpu1_intc 11>, <&cpu1_intc 9>, 239 <&cpu2_intc 11>, <&cpu2_intc 9>, 240 <&cpu3_intc 11>, <&cpu3_intc 9>, 241 <&cpu4_intc 11>, <&cpu4_intc 9>; 242 riscv,ndev = <186>; 243 }; 244 245 pdma: dma-controller@3000000 { 246 compatible = "microchip,mpfs-pdma", "sifive,pdma0"; 247 reg = <0x0 0x3000000 0x0 0x8000>; 248 interrupt-parent = <&plic>; 249 interrupts = <5 6>, <7 8>, <9 10>, <11 12>; 250 dma-channels = <4>; 251 #dma-cells = <1>; 252 }; 253 254 mss_top_sysreg: syscon@20002000 { 255 compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; 256 reg = <0x0 0x20002000 0x0 0x1000>; 257 #address-cells = <1>; 258 #size-cells = <1>; 259 #reset-cells = <1>; 260 261 irqmux: interrupt-controller@54 { 262 compatible = "microchip,mpfs-irqmux"; 263 reg = <0x54 0x4>; 264 #address-cells = <0>; 265 #interrupt-cells = <1>; 266 interrupt-map-mask = <0x7f>; 267 }; 268 269 iomux0: pinctrl@200 { 270 compatible = "microchip,mpfs-pinctrl-iomux0"; 271 reg = <0x200 0x4>; 272 pinctrl-use-default; 273 274 }; 275 276 mssio: pinctrl@204 { 277 compatible = "microchip,mpfs-pinctrl-mssio"; 278 reg = <0x204 0x7c>; 279 /* on icicle ref design at least */ 280 pinctrl-use-default; 281 }; 282 }; 283 284 sysreg_scb: syscon@20003000 { 285 compatible = "microchip,mpfs-sysreg-scb", "syscon"; 286 reg = <0x0 0x20003000 0x0 0x1000>; 287 }; 288 289 ccc_se: clock-controller@38010000 { 290 compatible = "microchip,mpfs-ccc"; 291 reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, 292 <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>; 293 #clock-cells = <1>; 294 status = "disabled"; 295 }; 296 297 ccc_ne: clock-controller@38040000 { 298 compatible = "microchip,mpfs-ccc"; 299 reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>, 300 <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>; 301 #clock-cells = <1>; 302 status = "disabled"; 303 }; 304 305 ccc_nw: clock-controller@38100000 { 306 compatible = "microchip,mpfs-ccc"; 307 reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>, 308 <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>; 309 #clock-cells = <1>; 310 status = "disabled"; 311 }; 312 313 ccc_sw: clock-controller@38400000 { 314 compatible = "microchip,mpfs-ccc"; 315 reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>, 316 <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>; 317 #clock-cells = <1>; 318 status = "disabled"; 319 }; 320 321 mmuart0: serial@20000000 { 322 compatible = "ns16550a"; 323 reg = <0x0 0x20000000 0x0 0x400>; 324 reg-io-width = <4>; 325 reg-shift = <2>; 326 interrupt-parent = <&plic>; 327 interrupts = <90>; 328 current-speed = <115200>; 329 clocks = <&clkcfg CLK_MMUART0>; 330 status = "disabled"; /* Reserved for the HSS */ 331 }; 332 333 mmuart1: serial@20100000 { 334 compatible = "ns16550a"; 335 reg = <0x0 0x20100000 0x0 0x400>; 336 reg-io-width = <4>; 337 reg-shift = <2>; 338 interrupt-parent = <&plic>; 339 interrupts = <91>; 340 current-speed = <115200>; 341 clocks = <&clkcfg CLK_MMUART1>; 342 status = "disabled"; 343 }; 344 345 mmuart2: serial@20102000 { 346 compatible = "ns16550a"; 347 reg = <0x0 0x20102000 0x0 0x400>; 348 reg-io-width = <4>; 349 reg-shift = <2>; 350 interrupt-parent = <&plic>; 351 interrupts = <92>; 352 current-speed = <115200>; 353 clocks = <&clkcfg CLK_MMUART2>; 354 status = "disabled"; 355 }; 356 357 mmuart3: serial@20104000 { 358 compatible = "ns16550a"; 359 reg = <0x0 0x20104000 0x0 0x400>; 360 reg-io-width = <4>; 361 reg-shift = <2>; 362 interrupt-parent = <&plic>; 363 interrupts = <93>; 364 current-speed = <115200>; 365 clocks = <&clkcfg CLK_MMUART3>; 366 status = "disabled"; 367 }; 368 369 mmuart4: serial@20106000 { 370 compatible = "ns16550a"; 371 reg = <0x0 0x20106000 0x0 0x400>; 372 reg-io-width = <4>; 373 reg-shift = <2>; 374 interrupt-parent = <&plic>; 375 interrupts = <94>; 376 clocks = <&clkcfg CLK_MMUART4>; 377 current-speed = <115200>; 378 status = "disabled"; 379 }; 380 381 /* Common node entry for emmc/sd */ 382 mmc: mmc@20008000 { 383 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; 384 reg = <0x0 0x20008000 0x0 0x1000>; 385 interrupt-parent = <&plic>; 386 interrupts = <88>; 387 clocks = <&clkcfg CLK_MMC>; 388 max-frequency = <200000000>; 389 status = "disabled"; 390 }; 391 392 spi0: spi@20108000 { 393 compatible = "microchip,mpfs-spi"; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 reg = <0x0 0x20108000 0x0 0x1000>; 397 interrupt-parent = <&plic>; 398 interrupts = <54>; 399 clocks = <&clkcfg CLK_SPI0>; 400 status = "disabled"; 401 }; 402 403 spi1: spi@20109000 { 404 compatible = "microchip,mpfs-spi"; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 reg = <0x0 0x20109000 0x0 0x1000>; 408 interrupt-parent = <&plic>; 409 interrupts = <55>; 410 clocks = <&clkcfg CLK_SPI1>; 411 status = "disabled"; 412 }; 413 414 qspi: spi@21000000 { 415 compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 reg = <0x0 0x21000000 0x0 0x1000>; 419 interrupt-parent = <&plic>; 420 interrupts = <85>; 421 clocks = <&clkcfg CLK_QSPI>; 422 status = "disabled"; 423 }; 424 425 i2c0: i2c@2010a000 { 426 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 427 reg = <0x0 0x2010a000 0x0 0x1000>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 interrupt-parent = <&plic>; 431 interrupts = <58>; 432 clocks = <&clkcfg CLK_I2C0>; 433 clock-frequency = <100000>; 434 status = "disabled"; 435 }; 436 437 i2c1: i2c@2010b000 { 438 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 439 reg = <0x0 0x2010b000 0x0 0x1000>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 interrupt-parent = <&plic>; 443 interrupts = <61>; 444 clocks = <&clkcfg CLK_I2C1>; 445 clock-frequency = <100000>; 446 status = "disabled"; 447 }; 448 449 can0: can@2010c000 { 450 compatible = "microchip,mpfs-can"; 451 reg = <0x0 0x2010c000 0x0 0x1000>; 452 clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>; 453 interrupt-parent = <&plic>; 454 interrupts = <56>; 455 resets = <&mss_top_sysreg CLK_CAN0>; 456 status = "disabled"; 457 }; 458 459 can1: can@2010d000 { 460 compatible = "microchip,mpfs-can"; 461 reg = <0x0 0x2010d000 0x0 0x1000>; 462 clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>; 463 interrupt-parent = <&plic>; 464 interrupts = <57>; 465 resets = <&mss_top_sysreg CLK_CAN1>; 466 status = "disabled"; 467 }; 468 469 mac0: ethernet@20110000 { 470 compatible = "microchip,mpfs-macb", "cdns,macb"; 471 reg = <0x0 0x20110000 0x0 0x2000>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 interrupt-parent = <&plic>; 475 interrupts = <64>, <65>, <66>, <67>, <68>, <69>; 476 local-mac-address = [00 00 00 00 00 00]; 477 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>; 478 clock-names = "pclk", "hclk", "tsu_clk"; 479 resets = <&mss_top_sysreg CLK_MAC0>; 480 status = "disabled"; 481 }; 482 483 mac1: ethernet@20112000 { 484 compatible = "microchip,mpfs-macb", "cdns,macb"; 485 reg = <0x0 0x20112000 0x0 0x2000>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 interrupt-parent = <&plic>; 489 interrupts = <70>, <71>, <72>, <73>, <74>, <75>; 490 local-mac-address = [00 00 00 00 00 00]; 491 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>, <&refclk>; 492 clock-names = "pclk", "hclk", "tsu_clk"; 493 resets = <&mss_top_sysreg CLK_MAC1>; 494 status = "disabled"; 495 }; 496 497 gpio0: gpio@20120000 { 498 compatible = "microchip,mpfs-gpio"; 499 reg = <0x0 0x20120000 0x0 0x1000>; 500 interrupt-parent = <&irqmux>; 501 interrupt-controller; 502 #interrupt-cells = <1>; 503 interrupts = <0>, <1>, <2>, <3>, 504 <4>, <5>, <6>, <7>, 505 <8>, <9>, <10>, <11>, 506 <12>, <13>; 507 clocks = <&clkcfg CLK_GPIO0>; 508 gpio-controller; 509 #gpio-cells = <2>; 510 ngpios = <14>; 511 status = "disabled"; 512 }; 513 514 gpio1: gpio@20121000 { 515 compatible = "microchip,mpfs-gpio"; 516 reg = <0x0 0x20121000 0x0 0x1000>; 517 interrupt-parent = <&irqmux>; 518 interrupt-controller; 519 #interrupt-cells = <1>; 520 interrupts = <32>, <33>, <34>, <35>, 521 <36>, <37>, <38>, <39>, 522 <40>, <41>, <42>, <43>, 523 <44>, <45>, <46>, <47>, 524 <48>, <49>, <50>, <51>, 525 <52>, <53>, <54>, <55>; 526 clocks = <&clkcfg CLK_GPIO1>; 527 gpio-controller; 528 #gpio-cells = <2>; 529 ngpios = <24>; 530 status = "disabled"; 531 }; 532 533 gpio2: gpio@20122000 { 534 compatible = "microchip,mpfs-gpio"; 535 reg = <0x0 0x20122000 0x0 0x1000>; 536 interrupt-parent = <&irqmux>; 537 interrupt-controller; 538 #interrupt-cells = <1>; 539 interrupts = <64>, <65>, <66>, <67>, 540 <68>, <69>, <70>, <71>, 541 <72>, <73>, <74>, <75>, 542 <76>, <77>, <78>, <79>, 543 <80>, <81>, <82>, <83>, 544 <84>, <85>, <86>, <87>, 545 <88>, <89>, <90>, <91>, 546 <92>, <93>, <94>, <95>; 547 clocks = <&clkcfg CLK_GPIO2>; 548 gpio-controller; 549 #gpio-cells = <2>; 550 ngpios = <32>; 551 status = "disabled"; 552 }; 553 554 rtc: rtc@20124000 { 555 compatible = "microchip,mpfs-rtc"; 556 reg = <0x0 0x20124000 0x0 0x1000>; 557 interrupt-parent = <&plic>; 558 interrupts = <80>, <81>; 559 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; 560 clock-names = "rtc", "rtcref"; 561 status = "disabled"; 562 }; 563 564 usb: usb@20201000 { 565 compatible = "microchip,mpfs-musb"; 566 reg = <0x0 0x20201000 0x0 0x1000>; 567 interrupt-parent = <&plic>; 568 interrupts = <86>, <87>; 569 clocks = <&clkcfg CLK_USB>; 570 interrupt-names = "dma","mc"; 571 status = "disabled"; 572 }; 573 574 control_scb: syscon@37020000 { 575 compatible = "microchip,mpfs-control-scb", "syscon"; 576 reg = <0x0 0x37020000 0x0 0x100>; 577 }; 578 579 mbox: mailbox@37020800 { 580 compatible = "microchip,mpfs-mailbox"; 581 reg = <0x0 0x37020800 0x0 0x1000>; 582 interrupt-parent = <&plic>; 583 interrupts = <96>; 584 #mbox-cells = <1>; 585 status = "disabled"; 586 }; 587 588 syscontroller_qspi: spi@37020100 { 589 compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 reg = <0x0 0x37020100 0x0 0x100>; 593 interrupt-parent = <&plic>; 594 interrupts = <110>; 595 clocks = <&scbclk>; 596 status = "disabled"; 597 }; 598 599 clkcfg: clkcfg@3e001000 { 600 compatible = "microchip,mpfs-clkcfg"; 601 reg = <0x0 0x3e001000 0x0 0x1000>; 602 clocks = <&refclk>; 603 #clock-cells = <1>; 604 }; 605 }; 606}; 607