1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/math.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/tty.h>
18 #include <linux/serial_reg.h>
19 #include <linux/serial_core.h>
20 #include <linux/8250_pci.h>
21 #include <linux/bitops.h>
22 #include <linux/bitfield.h>
23
24 #include <asm/byteorder.h>
25 #include <asm/io.h>
26
27 #include "8250.h"
28 #include "8250_pcilib.h"
29
30 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
31 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
32 #define PCI_DEVICE_ID_OCTPRO 0x0001
33 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
34 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
35 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
36 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
38 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
40 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
42 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
43 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
44 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
45 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
46 #define PCI_DEVICE_ID_TITAN_200I 0x8028
47 #define PCI_DEVICE_ID_TITAN_400I 0x8048
48 #define PCI_DEVICE_ID_TITAN_800I 0x8088
49 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
50 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
51 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
52 #define PCI_DEVICE_ID_TITAN_100E 0xA010
53 #define PCI_DEVICE_ID_TITAN_200E 0xA012
54 #define PCI_DEVICE_ID_TITAN_400E 0xA013
55 #define PCI_DEVICE_ID_TITAN_800E 0xA014
56 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
57 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
58 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
59 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
60 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
61 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
62 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
63 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
67
68 #define PCI_DEVICE_ID_WCHCN_CH352_2S 0x3253
69 #define PCI_DEVICE_ID_WCHCN_CH355_4S 0x7173
70
71 #define PCI_VENDOR_ID_AGESTAR 0x5372
72 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
73 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
74 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
75
76 #define PCI_DEVICE_ID_WCHIC_CH384_4S 0x3470
77 #define PCI_DEVICE_ID_WCHIC_CH384_8S 0x3853
78
79 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
80 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
81 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027
82 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
83 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046
84 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121
85 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
86 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145
87 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
88 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
89 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
90 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
91 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
92 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323
93 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
94 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343
95 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
96 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
97
98 #define PCI_DEVICE_ID_ADDIDATA_CPCI7500 0x7003
99 #define PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG 0x7024
100 #define PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG 0x7025
101 #define PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG 0x7026
102
103 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
104 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
105 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
106
107 /*
108 * init function returns:
109 * > 0 - number of ports
110 * = 0 - use board->num_ports
111 * < 0 - error
112 */
113 struct pci_serial_quirk {
114 u32 vendor;
115 u32 device;
116 u32 subvendor;
117 u32 subdevice;
118 int (*probe)(struct pci_dev *dev);
119 int (*init)(struct pci_dev *dev);
120 int (*setup)(struct serial_private *,
121 const struct pciserial_board *,
122 struct uart_8250_port *, int);
123 void (*exit)(struct pci_dev *dev);
124 };
125
126 struct f815xxa_data {
127 spinlock_t lock;
128 int idx;
129 };
130
131 struct serial_private {
132 struct pci_dev *dev;
133 unsigned int nr;
134 struct pci_serial_quirk *quirk;
135 const struct pciserial_board *board;
136 int line[];
137 };
138
139 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
140
141 static const struct pci_device_id pci_use_msi[] = {
142 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
143 0xA000, 0x1000) },
144 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
145 0xA000, 0x1000) },
146 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
147 0xA000, 0x1000) },
148 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
149 0xA000, 0x1000) },
150 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
151 PCI_ANY_ID, PCI_ANY_ID) },
152 { }
153 };
154
155 static int pci_default_setup(struct serial_private*,
156 const struct pciserial_board*, struct uart_8250_port *, int);
157
moan_device(const char * str,struct pci_dev * dev)158 static void moan_device(const char *str, struct pci_dev *dev)
159 {
160 pci_err(dev, "%s\n"
161 "Please send the output of lspci -vv, this\n"
162 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
163 "manufacturer and name of serial board or\n"
164 "modem board to <linux-serial@vger.kernel.org>.\n",
165 str, dev->vendor, dev->device,
166 dev->subsystem_vendor, dev->subsystem_device);
167 }
168
169 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,u8 bar,unsigned int offset,int regshift)170 setup_port(struct serial_private *priv, struct uart_8250_port *port,
171 u8 bar, unsigned int offset, int regshift)
172 {
173 void __iomem *iomem = NULL;
174
175 if (pci_resource_flags(priv->dev, bar) & IORESOURCE_MEM) {
176 iomem = pcim_iomap(priv->dev, bar, 0);
177 if (!iomem)
178 return -ENOMEM;
179 }
180
181 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift, iomem);
182 }
183
184 /*
185 * ADDI-DATA GmbH communication cards <info@addi-data.com>
186 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)187 static int addidata_apci7800_setup(struct serial_private *priv,
188 const struct pciserial_board *board,
189 struct uart_8250_port *port, int idx)
190 {
191 unsigned int bar = 0, offset = board->first_offset;
192 bar = FL_GET_BASE(board->flags);
193
194 if (idx < 2) {
195 offset += idx * board->uart_offset;
196 } else if ((idx >= 2) && (idx < 4)) {
197 bar += 1;
198 offset += ((idx - 2) * board->uart_offset);
199 } else if ((idx >= 4) && (idx < 6)) {
200 bar += 2;
201 offset += ((idx - 4) * board->uart_offset);
202 } else if (idx >= 6) {
203 bar += 3;
204 offset += ((idx - 6) * board->uart_offset);
205 }
206
207 return setup_port(priv, port, bar, offset, board->reg_shift);
208 }
209
210 /*
211 * AFAVLAB uses a different mixture of BARs and offsets
212 * Not that ugly ;) -- HW
213 */
214 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)215 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
216 struct uart_8250_port *port, int idx)
217 {
218 unsigned int bar, offset = board->first_offset;
219
220 bar = FL_GET_BASE(board->flags);
221 if (idx < 4)
222 bar += idx;
223 else {
224 bar = 4;
225 offset += (idx - 4) * board->uart_offset;
226 }
227
228 return setup_port(priv, port, bar, offset, board->reg_shift);
229 }
230
231 /*
232 * HP's Remote Management Console. The Diva chip came in several
233 * different versions. N-class, L2000 and A500 have two Diva chips, each
234 * with 3 UARTs (the third UART on the second chip is unused). Superdome
235 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
236 * one Diva chip, but it has been expanded to 5 UARTs.
237 */
pci_hp_diva_init(struct pci_dev * dev)238 static int pci_hp_diva_init(struct pci_dev *dev)
239 {
240 int rc = 0;
241
242 switch (dev->subsystem_device) {
243 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
244 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
245 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
246 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
247 rc = 3;
248 break;
249 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
250 rc = 2;
251 break;
252 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
253 rc = 4;
254 break;
255 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
256 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
257 rc = 1;
258 break;
259 }
260
261 return rc;
262 }
263
264 /*
265 * HP's Diva chip puts the 4th/5th serial port further out, and
266 * some serial ports are supposed to be hidden on certain models.
267 */
268 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)269 pci_hp_diva_setup(struct serial_private *priv,
270 const struct pciserial_board *board,
271 struct uart_8250_port *port, int idx)
272 {
273 unsigned int offset = board->first_offset;
274 unsigned int bar = FL_GET_BASE(board->flags);
275
276 switch (priv->dev->subsystem_device) {
277 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
278 if (idx == 3)
279 idx++;
280 break;
281 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
282 if (idx > 0)
283 idx++;
284 if (idx > 2)
285 idx++;
286 break;
287 }
288 if (idx > 2)
289 offset = 0x18;
290
291 offset += idx * board->uart_offset;
292
293 return setup_port(priv, port, bar, offset, board->reg_shift);
294 }
295
296 /*
297 * Added for EKF Intel i960 serial boards
298 */
pci_inteli960ni_init(struct pci_dev * dev)299 static int pci_inteli960ni_init(struct pci_dev *dev)
300 {
301 u32 oldval;
302
303 if (!(dev->subsystem_device & 0x1000))
304 return -ENODEV;
305
306 /* is firmware started? */
307 pci_read_config_dword(dev, 0x44, &oldval);
308 if (oldval == 0x00001000L) { /* RESET value */
309 pci_dbg(dev, "Local i960 firmware missing\n");
310 return -ENODEV;
311 }
312 return 0;
313 }
314
315 /*
316 * Some PCI serial cards using the PLX 9050 PCI interface chip require
317 * that the card interrupt be explicitly enabled or disabled. This
318 * seems to be mainly needed on card using the PLX which also use I/O
319 * mapped memory.
320 */
pci_plx9050_init(struct pci_dev * dev)321 static int pci_plx9050_init(struct pci_dev *dev)
322 {
323 u8 irq_config;
324 void __iomem *p;
325
326 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
327 moan_device("no memory in bar 0", dev);
328 return 0;
329 }
330
331 irq_config = 0x41;
332 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
333 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
334 irq_config = 0x43;
335
336 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
337 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
338 /*
339 * As the megawolf cards have the int pins active
340 * high, and have 2 UART chips, both ints must be
341 * enabled on the 9050. Also, the UARTS are set in
342 * 16450 mode by default, so we have to enable the
343 * 16C950 'enhanced' mode so that we can use the
344 * deep FIFOs
345 */
346 irq_config = 0x5b;
347 /*
348 * enable/disable interrupts
349 */
350 p = ioremap(pci_resource_start(dev, 0), 0x80);
351 if (p == NULL)
352 return -ENOMEM;
353 writel(irq_config, p + 0x4c);
354
355 /*
356 * Read the register back to ensure that it took effect.
357 */
358 readl(p + 0x4c);
359 iounmap(p);
360
361 return 0;
362 }
363
pci_plx9050_exit(struct pci_dev * dev)364 static void pci_plx9050_exit(struct pci_dev *dev)
365 {
366 u8 __iomem *p;
367
368 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
369 return;
370
371 /*
372 * disable interrupts
373 */
374 p = ioremap(pci_resource_start(dev, 0), 0x80);
375 if (p != NULL) {
376 writel(0, p + 0x4c);
377
378 /*
379 * Read the register back to ensure that it took effect.
380 */
381 readl(p + 0x4c);
382 iounmap(p);
383 }
384 }
385
386 #define NI8420_INT_ENABLE_REG 0x38
387 #define NI8420_INT_ENABLE_BIT 0x2000
388
pci_ni8420_exit(struct pci_dev * dev)389 static void pci_ni8420_exit(struct pci_dev *dev)
390 {
391 void __iomem *p;
392 unsigned int bar = 0;
393
394 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
395 moan_device("no memory in bar", dev);
396 return;
397 }
398
399 p = pci_ioremap_bar(dev, bar);
400 if (p == NULL)
401 return;
402
403 /* Disable the CPU Interrupt */
404 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
405 p + NI8420_INT_ENABLE_REG);
406 iounmap(p);
407 }
408
409
410 /* MITE registers */
411 #define MITE_IOWBSR1 0xc4
412 #define MITE_IOWCR1 0xf4
413 #define MITE_LCIMR1 0x08
414 #define MITE_LCIMR2 0x10
415
416 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
417
pci_ni8430_exit(struct pci_dev * dev)418 static void pci_ni8430_exit(struct pci_dev *dev)
419 {
420 void __iomem *p;
421 unsigned int bar = 0;
422
423 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
424 moan_device("no memory in bar", dev);
425 return;
426 }
427
428 p = pci_ioremap_bar(dev, bar);
429 if (p == NULL)
430 return;
431
432 /* Disable the CPU Interrupt */
433 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
434 iounmap(p);
435 }
436
437 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
438 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)439 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
440 struct uart_8250_port *port, int idx)
441 {
442 unsigned int bar, offset = board->first_offset;
443
444 bar = 0;
445
446 if (idx < 4) {
447 /* first four channels map to 0, 0x100, 0x200, 0x300 */
448 offset += idx * board->uart_offset;
449 } else if (idx < 8) {
450 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
451 offset += idx * board->uart_offset + 0xC00;
452 } else /* we have only 8 ports on PMC-OCTALPRO */
453 return 1;
454
455 return setup_port(priv, port, bar, offset, board->reg_shift);
456 }
457
458 /*
459 * This does initialization for PMC OCTALPRO cards:
460 * maps the device memory, resets the UARTs (needed, bc
461 * if the module is removed and inserted again, the card
462 * is in the sleep mode) and enables global interrupt.
463 */
464
465 /* global control register offset for SBS PMC-OctalPro */
466 #define OCT_REG_CR_OFF 0x500
467
sbs_init(struct pci_dev * dev)468 static int sbs_init(struct pci_dev *dev)
469 {
470 u8 __iomem *p;
471
472 p = pci_ioremap_bar(dev, 0);
473
474 if (p == NULL)
475 return -ENOMEM;
476 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
477 writeb(0x10, p + OCT_REG_CR_OFF);
478 udelay(50);
479 writeb(0x0, p + OCT_REG_CR_OFF);
480
481 /* Set bit-2 (INTENABLE) of Control Register */
482 writeb(0x4, p + OCT_REG_CR_OFF);
483 iounmap(p);
484
485 return 0;
486 }
487
488 /*
489 * Disables the global interrupt of PMC-OctalPro
490 */
491
sbs_exit(struct pci_dev * dev)492 static void sbs_exit(struct pci_dev *dev)
493 {
494 u8 __iomem *p;
495
496 p = pci_ioremap_bar(dev, 0);
497 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
498 if (p != NULL)
499 writeb(0, p + OCT_REG_CR_OFF);
500 iounmap(p);
501 }
502
503 /*
504 * SIIG serial cards have an PCI interface chip which also controls
505 * the UART clocking frequency. Each UART can be clocked independently
506 * (except cards equipped with 4 UARTs) and initial clocking settings
507 * are stored in the EEPROM chip. It can cause problems because this
508 * version of serial driver doesn't support differently clocked UART's
509 * on single PCI card. To prevent this, initialization functions set
510 * high frequency clocking for all UART's on given card. It is safe (I
511 * hope) because it doesn't touch EEPROM settings to prevent conflicts
512 * with other OSes (like M$ DOS).
513 *
514 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
515 *
516 * There is two family of SIIG serial cards with different PCI
517 * interface chip and different configuration methods:
518 * - 10x cards have control registers in IO and/or memory space;
519 * - 20x cards have control registers in standard PCI configuration space.
520 *
521 * Note: all 10x cards have PCI device ids 0x10..
522 * all 20x cards have PCI device ids 0x20..
523 *
524 * There are also Quartet Serial cards which use Oxford Semiconductor
525 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
526 *
527 * Note: some SIIG cards are probed by the parport_serial object.
528 */
529
530 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
531 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
532
pci_siig10x_init(struct pci_dev * dev)533 static int pci_siig10x_init(struct pci_dev *dev)
534 {
535 u16 data;
536 void __iomem *p;
537
538 switch (dev->device & 0xfff8) {
539 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
540 data = 0xffdf;
541 break;
542 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
543 data = 0xf7ff;
544 break;
545 default: /* 1S1P, 4S */
546 data = 0xfffb;
547 break;
548 }
549
550 p = ioremap(pci_resource_start(dev, 0), 0x80);
551 if (p == NULL)
552 return -ENOMEM;
553
554 writew(readw(p + 0x28) & data, p + 0x28);
555 readw(p + 0x28);
556 iounmap(p);
557 return 0;
558 }
559
560 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
561 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
562
pci_siig20x_init(struct pci_dev * dev)563 static int pci_siig20x_init(struct pci_dev *dev)
564 {
565 u8 data;
566
567 /* Change clock frequency for the first UART. */
568 pci_read_config_byte(dev, 0x6f, &data);
569 pci_write_config_byte(dev, 0x6f, data & 0xef);
570
571 /* If this card has 2 UART, we have to do the same with second UART. */
572 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
573 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
574 pci_read_config_byte(dev, 0x73, &data);
575 pci_write_config_byte(dev, 0x73, data & 0xef);
576 }
577 return 0;
578 }
579
pci_siig_init(struct pci_dev * dev)580 static int pci_siig_init(struct pci_dev *dev)
581 {
582 unsigned int type = dev->device & 0xff00;
583
584 if (type == 0x1000)
585 return pci_siig10x_init(dev);
586 if (type == 0x2000)
587 return pci_siig20x_init(dev);
588
589 moan_device("Unknown SIIG card", dev);
590 return -ENODEV;
591 }
592
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)593 static int pci_siig_setup(struct serial_private *priv,
594 const struct pciserial_board *board,
595 struct uart_8250_port *port, int idx)
596 {
597 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
598
599 if (idx > 3) {
600 bar = 4;
601 offset = (idx - 4) * 8;
602 }
603
604 return setup_port(priv, port, bar, offset, 0);
605 }
606
607 /*
608 * Timedia has an explosion of boards, and to avoid the PCI table from
609 * growing *huge*, we use this function to collapse some 70 entries
610 * in the PCI table into one, for sanity's and compactness's sake.
611 */
612 static const unsigned short timedia_single_port[] = {
613 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
614 };
615
616 static const unsigned short timedia_dual_port[] = {
617 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
618 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
619 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
620 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
621 0xD079, 0
622 };
623
624 static const unsigned short timedia_quad_port[] = {
625 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
626 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
627 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
628 0xB157, 0
629 };
630
631 static const unsigned short timedia_eight_port[] = {
632 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
633 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
634 };
635
636 static const struct timedia_struct {
637 int num;
638 const unsigned short *ids;
639 } timedia_data[] = {
640 { 1, timedia_single_port },
641 { 2, timedia_dual_port },
642 { 4, timedia_quad_port },
643 { 8, timedia_eight_port }
644 };
645
646 /*
647 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
648 * listing them individually, this driver merely grabs them all with
649 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
650 * and should be left free to be claimed by parport_serial instead.
651 */
pci_timedia_probe(struct pci_dev * dev)652 static int pci_timedia_probe(struct pci_dev *dev)
653 {
654 /*
655 * Check the third digit of the subdevice ID
656 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
657 */
658 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
659 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
660 dev->subsystem_device);
661 return -ENODEV;
662 }
663
664 return 0;
665 }
666
pci_timedia_init(struct pci_dev * dev)667 static int pci_timedia_init(struct pci_dev *dev)
668 {
669 const unsigned short *ids;
670 int i, j;
671
672 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
673 ids = timedia_data[i].ids;
674 for (j = 0; ids[j]; j++)
675 if (dev->subsystem_device == ids[j])
676 return timedia_data[i].num;
677 }
678 return 0;
679 }
680
681 /*
682 * Timedia/SUNIX uses a mixture of BARs and offsets
683 * Ugh, this is ugly as all hell --- TYT
684 */
685 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)686 pci_timedia_setup(struct serial_private *priv,
687 const struct pciserial_board *board,
688 struct uart_8250_port *port, int idx)
689 {
690 unsigned int bar = 0, offset = board->first_offset;
691
692 switch (idx) {
693 case 0:
694 bar = 0;
695 break;
696 case 1:
697 offset = board->uart_offset;
698 bar = 0;
699 break;
700 case 2:
701 bar = 1;
702 break;
703 case 3:
704 offset = board->uart_offset;
705 fallthrough;
706 case 4: /* BAR 2 */
707 case 5: /* BAR 3 */
708 case 6: /* BAR 4 */
709 case 7: /* BAR 5 */
710 bar = idx - 2;
711 }
712
713 return setup_port(priv, port, bar, offset, board->reg_shift);
714 }
715
716 /*
717 * Some Titan cards are also a little weird
718 */
719 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)720 titan_400l_800l_setup(struct serial_private *priv,
721 const struct pciserial_board *board,
722 struct uart_8250_port *port, int idx)
723 {
724 unsigned int bar, offset = board->first_offset;
725
726 switch (idx) {
727 case 0:
728 bar = 1;
729 break;
730 case 1:
731 bar = 2;
732 break;
733 default:
734 bar = 4;
735 offset = (idx - 2) * board->uart_offset;
736 }
737
738 return setup_port(priv, port, bar, offset, board->reg_shift);
739 }
740
pci_xircom_init(struct pci_dev * dev)741 static int pci_xircom_init(struct pci_dev *dev)
742 {
743 msleep(100);
744 return 0;
745 }
746
pci_ni8420_init(struct pci_dev * dev)747 static int pci_ni8420_init(struct pci_dev *dev)
748 {
749 void __iomem *p;
750 unsigned int bar = 0;
751
752 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
753 moan_device("no memory in bar", dev);
754 return 0;
755 }
756
757 p = pci_ioremap_bar(dev, bar);
758 if (p == NULL)
759 return -ENOMEM;
760
761 /* Enable CPU Interrupt */
762 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
763 p + NI8420_INT_ENABLE_REG);
764
765 iounmap(p);
766 return 0;
767 }
768
769 #define MITE_IOWBSR1_WSIZE 0xa
770 #define MITE_IOWBSR1_WIN_OFFSET 0x800
771 #define MITE_IOWBSR1_WENAB (1 << 7)
772 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
773 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
774 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
775
pci_ni8430_init(struct pci_dev * dev)776 static int pci_ni8430_init(struct pci_dev *dev)
777 {
778 void __iomem *p;
779 struct pci_bus_region region;
780 u32 device_window;
781 unsigned int bar = 0;
782
783 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
784 moan_device("no memory in bar", dev);
785 return 0;
786 }
787
788 p = pci_ioremap_bar(dev, bar);
789 if (p == NULL)
790 return -ENOMEM;
791
792 /*
793 * Set device window address and size in BAR0, while acknowledging that
794 * the resource structure may contain a translated address that differs
795 * from the address the device responds to.
796 */
797 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
798 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
799 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
800 writel(device_window, p + MITE_IOWBSR1);
801
802 /* Set window access to go to RAMSEL IO address space */
803 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
804 p + MITE_IOWCR1);
805
806 /* Enable IO Bus Interrupt 0 */
807 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
808
809 /* Enable CPU Interrupt */
810 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
811
812 iounmap(p);
813 return 0;
814 }
815
816 /* UART Port Control Register */
817 #define NI8430_PORTCON 0x0f
818 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
819
820 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)821 pci_ni8430_setup(struct serial_private *priv,
822 const struct pciserial_board *board,
823 struct uart_8250_port *port, int idx)
824 {
825 struct pci_dev *dev = priv->dev;
826 void __iomem *p;
827 unsigned int bar, offset = board->first_offset;
828
829 if (idx >= board->num_ports)
830 return 1;
831
832 bar = FL_GET_BASE(board->flags);
833 offset += idx * board->uart_offset;
834
835 p = pci_ioremap_bar(dev, bar);
836 if (!p)
837 return -ENOMEM;
838
839 /* enable the transceiver */
840 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
841 p + offset + NI8430_PORTCON);
842
843 iounmap(p);
844
845 return setup_port(priv, port, bar, offset, board->reg_shift);
846 }
847
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)848 static int pci_netmos_9900_setup(struct serial_private *priv,
849 const struct pciserial_board *board,
850 struct uart_8250_port *port, int idx)
851 {
852 unsigned int bar;
853
854 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
855 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
856 /* netmos apparently orders BARs by datasheet layout, so serial
857 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
858 */
859 bar = 3 * idx;
860
861 return setup_port(priv, port, bar, 0, board->reg_shift);
862 }
863
864 return pci_default_setup(priv, board, port, idx);
865 }
866
867 /* the 99xx series comes with a range of device IDs and a variety
868 * of capabilities:
869 *
870 * 9900 has varying capabilities and can cascade to sub-controllers
871 * (cascading should be purely internal)
872 * 9904 is hardwired with 4 serial ports
873 * 9912 and 9922 are hardwired with 2 serial ports
874 */
pci_netmos_9900_numports(struct pci_dev * dev)875 static int pci_netmos_9900_numports(struct pci_dev *dev)
876 {
877 unsigned int c = dev->class;
878 unsigned int pi;
879 unsigned short sub_serports;
880
881 pi = c & 0xff;
882
883 if (pi == 2)
884 return 1;
885
886 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
887 /* two possibilities: 0x30ps encodes number of parallel and
888 * serial ports, or 0x1000 indicates *something*. This is not
889 * immediately obvious, since the 2s1p+4s configuration seems
890 * to offer all functionality on functions 0..2, while still
891 * advertising the same function 3 as the 4s+2s1p config.
892 */
893 sub_serports = dev->subsystem_device & 0xf;
894 if (sub_serports > 0)
895 return sub_serports;
896
897 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
898 return 0;
899 }
900
901 moan_device("unknown NetMos/Mostech program interface", dev);
902 return 0;
903 }
904
pci_netmos_init(struct pci_dev * dev)905 static int pci_netmos_init(struct pci_dev *dev)
906 {
907 /* subdevice 0x00PS means <P> parallel, <S> serial */
908 unsigned int num_serial = dev->subsystem_device & 0xf;
909
910 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
911 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
912 return 0;
913
914 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
915 dev->subsystem_device == 0x0299)
916 return 0;
917
918 switch (dev->device) { /* FALLTHROUGH on all */
919 case PCI_DEVICE_ID_NETMOS_9904:
920 case PCI_DEVICE_ID_NETMOS_9912:
921 case PCI_DEVICE_ID_NETMOS_9922:
922 case PCI_DEVICE_ID_NETMOS_9900:
923 num_serial = pci_netmos_9900_numports(dev);
924 break;
925
926 default:
927 break;
928 }
929
930 if (num_serial == 0) {
931 moan_device("unknown NetMos/Mostech device", dev);
932 return -ENODEV;
933 }
934
935 return num_serial;
936 }
937
938 /*
939 * These chips are available with optionally one parallel port and up to
940 * two serial ports. Unfortunately they all have the same product id.
941 *
942 * Basic configuration is done over a region of 32 I/O ports. The base
943 * ioport is called INTA or INTC, depending on docs/other drivers.
944 *
945 * The region of the 32 I/O ports is configured in POSIO0R...
946 */
947
948 /* registers */
949 #define ITE_887x_MISCR 0x9c
950 #define ITE_887x_INTCBAR 0x78
951 #define ITE_887x_UARTBAR 0x7c
952 #define ITE_887x_PS0BAR 0x10
953 #define ITE_887x_POSIO0 0x60
954
955 /* I/O space size */
956 #define ITE_887x_IOSIZE 32
957 /* I/O space size (bits 26-24; 8 bytes = 011b) */
958 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
959 /* I/O space size (bits 26-24; 32 bytes = 101b) */
960 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
961 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
962 #define ITE_887x_POSIO_SPEED (3 << 29)
963 /* enable IO_Space bit */
964 #define ITE_887x_POSIO_ENABLE (1 << 31)
965
966 /* inta_addr are the configuration addresses of the ITE */
967 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
pci_ite887x_init(struct pci_dev * dev)968 static int pci_ite887x_init(struct pci_dev *dev)
969 {
970 int ret, i, type;
971 struct resource *iobase = NULL;
972 u32 miscr, uartbar, ioport;
973
974 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
975 return serial_8250_warn_need_ioport(dev);
976
977 /* search for the base-ioport */
978 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
979 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
980 "ite887x");
981 if (iobase != NULL) {
982 /* write POSIO0R - speed | size | ioport */
983 pci_write_config_dword(dev, ITE_887x_POSIO0,
984 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
985 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
986 /* write INTCBAR - ioport */
987 pci_write_config_dword(dev, ITE_887x_INTCBAR,
988 inta_addr[i]);
989 ret = inb(inta_addr[i]);
990 if (ret != 0xff) {
991 /* ioport connected */
992 break;
993 }
994 release_region(iobase->start, ITE_887x_IOSIZE);
995 }
996 }
997
998 if (i == ARRAY_SIZE(inta_addr)) {
999 pci_err(dev, "could not find iobase\n");
1000 return -ENODEV;
1001 }
1002
1003 /* start of undocumented type checking (see parport_pc.c) */
1004 type = inb(iobase->start + 0x18) & 0x0f;
1005
1006 switch (type) {
1007 case 0x2: /* ITE8871 (1P) */
1008 case 0xa: /* ITE8875 (1P) */
1009 ret = 0;
1010 break;
1011 case 0xe: /* ITE8872 (2S1P) */
1012 ret = 2;
1013 break;
1014 case 0x6: /* ITE8873 (1S) */
1015 ret = 1;
1016 break;
1017 case 0x8: /* ITE8874 (2S) */
1018 ret = 2;
1019 break;
1020 default:
1021 moan_device("Unknown ITE887x", dev);
1022 ret = -ENODEV;
1023 }
1024
1025 /* configure all serial ports */
1026 for (i = 0; i < ret; i++) {
1027 /* read the I/O port from the device */
1028 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
1029 &ioport);
1030 ioport &= 0x0000FF00; /* the actual base address */
1031 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
1032 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
1033 ITE_887x_POSIO_IOSIZE_8 | ioport);
1034
1035 /* write the ioport to the UARTBAR */
1036 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
1037 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
1038 uartbar |= (ioport << (16 * i)); /* set the ioport */
1039 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
1040
1041 /* get current config */
1042 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
1043 /* disable interrupts (UARTx_Routing[3:0]) */
1044 miscr &= ~(0xf << (12 - 4 * i));
1045 /* activate the UART (UARTx_En) */
1046 miscr |= 1 << (23 - i);
1047 /* write new config with activated UART */
1048 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
1049 }
1050
1051 if (ret <= 0) {
1052 /* the device has no UARTs if we get here */
1053 release_region(iobase->start, ITE_887x_IOSIZE);
1054 }
1055
1056 return ret;
1057 }
1058
pci_ite887x_exit(struct pci_dev * dev)1059 static void pci_ite887x_exit(struct pci_dev *dev)
1060 {
1061 u32 ioport;
1062 /* the ioport is bit 0-15 in POSIO0R */
1063 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1064 ioport &= 0xffff;
1065 release_region(ioport, ITE_887x_IOSIZE);
1066 }
1067
1068 /*
1069 * Oxford Semiconductor Inc.
1070 * Check if an OxSemi device is part of the Tornado range of devices.
1071 */
1072 #define PCI_VENDOR_ID_ENDRUN 0x7401
1073 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1074
pci_oxsemi_tornado_p(struct pci_dev * dev)1075 static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
1076 {
1077 /* OxSemi Tornado devices are all 0xCxxx */
1078 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1079 (dev->device & 0xf000) != 0xc000)
1080 return false;
1081
1082 /* EndRun devices are all 0xExxx */
1083 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1084 (dev->device & 0xf000) != 0xe000)
1085 return false;
1086
1087 return true;
1088 }
1089
1090 /*
1091 * Determine the number of ports available on a Tornado device.
1092 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1093 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1094 {
1095 u8 __iomem *p;
1096 unsigned long deviceID;
1097 unsigned int number_uarts = 0;
1098
1099 if (!pci_oxsemi_tornado_p(dev))
1100 return 0;
1101
1102 p = pci_iomap(dev, 0, 5);
1103 if (p == NULL)
1104 return -ENOMEM;
1105
1106 deviceID = ioread32(p);
1107 /* Tornado device */
1108 if (deviceID == 0x07000200) {
1109 number_uarts = ioread8(p + 4);
1110 pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1111 number_uarts,
1112 dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1113 "EndRun" : "Oxford");
1114 }
1115 pci_iounmap(dev, p);
1116 return number_uarts;
1117 }
1118
1119 /* Tornado-specific constants for the TCR and CPR registers; see below. */
1120 #define OXSEMI_TORNADO_TCR_MASK 0xf
1121 #define OXSEMI_TORNADO_CPR_MASK 0x1ff
1122 #define OXSEMI_TORNADO_CPR_MIN 0x008
1123 #define OXSEMI_TORNADO_CPR_DEF 0x10f
1124
1125 /*
1126 * Determine the oversampling rate, the clock prescaler, and the clock
1127 * divisor for the requested baud rate. The clock rate is 62.5 MHz,
1128 * which is four times the baud base, and the prescaler increments in
1129 * steps of 1/8. Therefore to make calculations on integers we need
1130 * to use a scaled clock rate, which is the baud base multiplied by 32
1131 * (or our assumed UART clock rate multiplied by 2).
1132 *
1133 * The allowed oversampling rates are from 4 up to 16 inclusive (values
1134 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1135 * values between 1.000 and 63.875 inclusive (operation for values from
1136 * 0.000 to 0.875 has not been specified). The clock divisor is the usual
1137 * unsigned 16-bit integer.
1138 *
1139 * For the most accurate baud rate we use a table of predetermined
1140 * oversampling rates and clock prescalers that records all possible
1141 * products of the two parameters in the range from 4 up to 255 inclusive,
1142 * and additionally 335 for the 1500000bps rate, with the prescaler scaled
1143 * by 8. The table is sorted by the decreasing value of the oversampling
1144 * rate and ties are resolved by sorting by the decreasing value of the
1145 * product. This way preference is given to higher oversampling rates.
1146 *
1147 * We iterate over the table and choose the product of an oversampling
1148 * rate and a clock prescaler that gives the lowest integer division
1149 * result deviation, or if an exact integer divider is found we stop
1150 * looking for it right away. We do some fixup if the resulting clock
1151 * divisor required would be out of its unsigned 16-bit integer range.
1152 *
1153 * Finally we abuse the supposed fractional part returned to encode the
1154 * 4-bit value of the oversampling rate and the 9-bit value of the clock
1155 * prescaler which will end up in the TCR and CPR/CPR2 registers.
1156 */
pci_oxsemi_tornado_get_divisor(struct uart_port * port,unsigned int baud,unsigned int * frac)1157 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
1158 unsigned int baud,
1159 unsigned int *frac)
1160 {
1161 static u8 p[][2] = {
1162 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
1163 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, },
1164 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
1165 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, },
1166 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
1167 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
1168 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, },
1169 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
1170 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, },
1171 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, },
1172 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
1173 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
1174 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, },
1175 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
1176 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, },
1177 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, },
1178 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, },
1179 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, },
1180 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, },
1181 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, },
1182 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, },
1183 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, },
1184 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, },
1185 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, },
1186 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, },
1187 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, },
1188 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, },
1189 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, },
1190 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, },
1191 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, },
1192 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, },
1193 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, },
1194 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, },
1195 { 4, 9, }, { 4, 8, },
1196 };
1197 /* Scale the quotient for comparison to get the fractional part. */
1198 const unsigned int quot_scale = 65536;
1199 unsigned int sclk = port->uartclk * 2;
1200 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
1201 unsigned int best_squot;
1202 unsigned int squot;
1203 unsigned int quot;
1204 u16 cpr;
1205 u8 tcr;
1206 int i;
1207
1208 best_squot = quot_scale;
1209 for (i = 0; i < ARRAY_SIZE(p); i++) {
1210 unsigned int spre;
1211 unsigned int srem;
1212 u8 cp;
1213 u8 tc;
1214
1215 tc = p[i][0];
1216 cp = p[i][1];
1217 spre = tc * cp;
1218
1219 srem = sdiv % spre;
1220 if (srem > spre / 2)
1221 srem = spre - srem;
1222 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
1223
1224 if (srem == 0) {
1225 tcr = tc;
1226 cpr = cp;
1227 quot = sdiv / spre;
1228 break;
1229 } else if (squot < best_squot) {
1230 best_squot = squot;
1231 tcr = tc;
1232 cpr = cp;
1233 quot = DIV_ROUND_CLOSEST(sdiv, spre);
1234 }
1235 }
1236 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
1237 quot % 2 == 0) {
1238 quot >>= 1;
1239 tcr <<= 1;
1240 }
1241 while (quot > UART_DIV_MAX) {
1242 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
1243 quot >>= 1;
1244 tcr <<= 1;
1245 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
1246 quot >>= 1;
1247 cpr <<= 1;
1248 } else {
1249 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
1250 cpr = OXSEMI_TORNADO_CPR_MASK;
1251 }
1252 }
1253
1254 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
1255 return quot;
1256 }
1257
1258 /*
1259 * Set the oversampling rate in the transmitter clock cycle register (TCR),
1260 * the clock prescaler in the clock prescaler register (CPR and CPR2), and
1261 * the clock divisor in the divisor latch (DLL and DLM). Note that for
1262 * backwards compatibility any write to CPR clears CPR2 and therefore CPR
1263 * has to be written first, followed by CPR2, which occupies the location
1264 * of CKS used with earlier UART designs.
1265 */
pci_oxsemi_tornado_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)1266 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
1267 unsigned int baud,
1268 unsigned int quot,
1269 unsigned int quot_frac)
1270 {
1271 struct uart_8250_port *up = up_to_u8250p(port);
1272 u8 cpr2 = quot_frac >> 16;
1273 u8 cpr = quot_frac >> 8;
1274 u8 tcr = quot_frac;
1275
1276 serial_icr_write(up, UART_TCR, tcr);
1277 serial_icr_write(up, UART_CPR, cpr);
1278 serial_icr_write(up, UART_CKS, cpr2);
1279 serial8250_do_set_divisor(port, baud, quot);
1280 }
1281
1282 /*
1283 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1284 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used.
1285 */
pci_oxsemi_tornado_set_mctrl(struct uart_port * port,unsigned int mctrl)1286 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
1287 unsigned int mctrl)
1288 {
1289 struct uart_8250_port *up = up_to_u8250p(port);
1290
1291 up->mcr |= UART_MCR_CLKSEL;
1292 serial8250_do_set_mctrl(port, mctrl);
1293 }
1294
1295 /*
1296 * We require EFR features for clock programming, so set UPF_FULL_PROBE
1297 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting.
1298 */
pci_oxsemi_tornado_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * up,int idx)1299 static int pci_oxsemi_tornado_setup(struct serial_private *priv,
1300 const struct pciserial_board *board,
1301 struct uart_8250_port *up, int idx)
1302 {
1303 struct pci_dev *dev = priv->dev;
1304
1305 if (pci_oxsemi_tornado_p(dev)) {
1306 up->port.flags |= UPF_FULL_PROBE;
1307 up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
1308 up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
1309 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
1310 }
1311
1312 return pci_default_setup(priv, board, up, idx);
1313 }
1314
1315 #define QPCR_TEST_FOR1 0x3F
1316 #define QPCR_TEST_GET1 0x00
1317 #define QPCR_TEST_FOR2 0x40
1318 #define QPCR_TEST_GET2 0x40
1319 #define QPCR_TEST_FOR3 0x80
1320 #define QPCR_TEST_GET3 0x40
1321 #define QPCR_TEST_FOR4 0xC0
1322 #define QPCR_TEST_GET4 0x80
1323
1324 #define QOPR_CLOCK_X1 0x0000
1325 #define QOPR_CLOCK_X2 0x0001
1326 #define QOPR_CLOCK_X4 0x0002
1327 #define QOPR_CLOCK_X8 0x0003
1328 #define QOPR_CLOCK_RATE_MASK 0x0003
1329
1330 /* Quatech devices have their own extra interface features */
1331 static struct pci_device_id quatech_cards[] = {
1332 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) },
1333 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) },
1334 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) },
1335 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) },
1336 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) },
1337 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) },
1338 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) },
1339 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) },
1340 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) },
1341 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) },
1342 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) },
1343 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
1344 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
1345 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
1346 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
1347 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
1348 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
1349 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
1350 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
1351 { 0, }
1352 };
1353
pci_quatech_rqopr(struct uart_8250_port * port)1354 static int pci_quatech_rqopr(struct uart_8250_port *port)
1355 {
1356 unsigned long base = port->port.iobase;
1357 u8 LCR, val;
1358
1359 LCR = inb(base + UART_LCR);
1360 outb(0xBF, base + UART_LCR);
1361 val = inb(base + UART_SCR);
1362 outb(LCR, base + UART_LCR);
1363 return val;
1364 }
1365
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1366 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1367 {
1368 unsigned long base = port->port.iobase;
1369 u8 LCR;
1370
1371 LCR = inb(base + UART_LCR);
1372 outb(0xBF, base + UART_LCR);
1373 inb(base + UART_SCR);
1374 outb(qopr, base + UART_SCR);
1375 outb(LCR, base + UART_LCR);
1376 }
1377
pci_quatech_rqmcr(struct uart_8250_port * port)1378 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1379 {
1380 unsigned long base = port->port.iobase;
1381 u8 LCR, val, qmcr;
1382
1383 LCR = inb(base + UART_LCR);
1384 outb(0xBF, base + UART_LCR);
1385 val = inb(base + UART_SCR);
1386 outb(val | 0x10, base + UART_SCR);
1387 qmcr = inb(base + UART_MCR);
1388 outb(val, base + UART_SCR);
1389 outb(LCR, base + UART_LCR);
1390
1391 return qmcr;
1392 }
1393
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1394 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1395 {
1396 unsigned long base = port->port.iobase;
1397 u8 LCR, val;
1398
1399 LCR = inb(base + UART_LCR);
1400 outb(0xBF, base + UART_LCR);
1401 val = inb(base + UART_SCR);
1402 outb(val | 0x10, base + UART_SCR);
1403 outb(qmcr, base + UART_MCR);
1404 outb(val, base + UART_SCR);
1405 outb(LCR, base + UART_LCR);
1406 }
1407
pci_quatech_has_qmcr(struct uart_8250_port * port)1408 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1409 {
1410 unsigned long base = port->port.iobase;
1411 u8 LCR, val;
1412
1413 LCR = inb(base + UART_LCR);
1414 outb(0xBF, base + UART_LCR);
1415 val = inb(base + UART_SCR);
1416 if (val & 0x20) {
1417 outb(0x80, UART_LCR);
1418 if (!(inb(UART_SCR) & 0x20)) {
1419 outb(LCR, base + UART_LCR);
1420 return 1;
1421 }
1422 }
1423 return 0;
1424 }
1425
pci_quatech_test(struct uart_8250_port * port)1426 static int pci_quatech_test(struct uart_8250_port *port)
1427 {
1428 u8 reg, qopr;
1429
1430 qopr = pci_quatech_rqopr(port);
1431 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1432 reg = pci_quatech_rqopr(port) & 0xC0;
1433 if (reg != QPCR_TEST_GET1)
1434 return -EINVAL;
1435 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1436 reg = pci_quatech_rqopr(port) & 0xC0;
1437 if (reg != QPCR_TEST_GET2)
1438 return -EINVAL;
1439 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1440 reg = pci_quatech_rqopr(port) & 0xC0;
1441 if (reg != QPCR_TEST_GET3)
1442 return -EINVAL;
1443 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1444 reg = pci_quatech_rqopr(port) & 0xC0;
1445 if (reg != QPCR_TEST_GET4)
1446 return -EINVAL;
1447
1448 pci_quatech_wqopr(port, qopr);
1449 return 0;
1450 }
1451
pci_quatech_clock(struct uart_8250_port * port)1452 static int pci_quatech_clock(struct uart_8250_port *port)
1453 {
1454 u8 qopr, reg, set;
1455 unsigned long clock;
1456
1457 if (pci_quatech_test(port) < 0)
1458 return 1843200;
1459
1460 qopr = pci_quatech_rqopr(port);
1461
1462 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1463 reg = pci_quatech_rqopr(port);
1464 if (reg & QOPR_CLOCK_X8) {
1465 clock = 1843200;
1466 goto out;
1467 }
1468 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1469 reg = pci_quatech_rqopr(port);
1470 if (!(reg & QOPR_CLOCK_X8)) {
1471 clock = 1843200;
1472 goto out;
1473 }
1474 reg &= QOPR_CLOCK_X8;
1475 if (reg == QOPR_CLOCK_X2) {
1476 clock = 3685400;
1477 set = QOPR_CLOCK_X2;
1478 } else if (reg == QOPR_CLOCK_X4) {
1479 clock = 7372800;
1480 set = QOPR_CLOCK_X4;
1481 } else if (reg == QOPR_CLOCK_X8) {
1482 clock = 14745600;
1483 set = QOPR_CLOCK_X8;
1484 } else {
1485 clock = 1843200;
1486 set = QOPR_CLOCK_X1;
1487 }
1488 qopr &= ~QOPR_CLOCK_RATE_MASK;
1489 qopr |= set;
1490
1491 out:
1492 pci_quatech_wqopr(port, qopr);
1493 return clock;
1494 }
1495
pci_quatech_rs422(struct uart_8250_port * port)1496 static int pci_quatech_rs422(struct uart_8250_port *port)
1497 {
1498 u8 qmcr;
1499 int rs422 = 0;
1500
1501 if (!pci_quatech_has_qmcr(port))
1502 return 0;
1503 qmcr = pci_quatech_rqmcr(port);
1504 pci_quatech_wqmcr(port, 0xFF);
1505 if (pci_quatech_rqmcr(port))
1506 rs422 = 1;
1507 pci_quatech_wqmcr(port, qmcr);
1508 return rs422;
1509 }
1510
pci_quatech_init(struct pci_dev * dev)1511 static int pci_quatech_init(struct pci_dev *dev)
1512 {
1513 const struct pci_device_id *match;
1514 bool amcc = false;
1515
1516 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1517 return serial_8250_warn_need_ioport(dev);
1518
1519 match = pci_match_id(quatech_cards, dev);
1520 if (match)
1521 amcc = match->driver_data;
1522 else
1523 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1524
1525 if (amcc) {
1526 unsigned long base = pci_resource_start(dev, 0);
1527 if (base) {
1528 u32 tmp;
1529
1530 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1531 tmp = inl(base + 0x3c);
1532 outl(tmp | 0x01000000, base + 0x3c);
1533 outl(tmp & ~0x01000000, base + 0x3c);
1534 }
1535 }
1536 return 0;
1537 }
1538
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1539 static int pci_quatech_setup(struct serial_private *priv,
1540 const struct pciserial_board *board,
1541 struct uart_8250_port *port, int idx)
1542 {
1543 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1544 return serial_8250_warn_need_ioport(priv->dev);
1545
1546 /* Needed by pci_quatech calls below */
1547 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1548 /* Set up the clocking */
1549 port->port.uartclk = pci_quatech_clock(port);
1550 /* For now just warn about RS422 */
1551 if (pci_quatech_rs422(port))
1552 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1553 return pci_default_setup(priv, board, port, idx);
1554 }
1555
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1556 static int pci_default_setup(struct serial_private *priv,
1557 const struct pciserial_board *board,
1558 struct uart_8250_port *port, int idx)
1559 {
1560 unsigned int bar, offset = board->first_offset, maxnr;
1561
1562 bar = FL_GET_BASE(board->flags);
1563 if (board->flags & FL_BASE_BARS)
1564 bar += idx;
1565 else
1566 offset += idx * board->uart_offset;
1567
1568 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1569 (board->reg_shift + 3);
1570
1571 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1572 return 1;
1573
1574 return setup_port(priv, port, bar, offset, board->reg_shift);
1575 }
1576
1577 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1578 ce4100_serial_setup(struct serial_private *priv,
1579 const struct pciserial_board *board,
1580 struct uart_8250_port *port, int idx)
1581 {
1582 int ret;
1583
1584 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1585 port->port.iotype = UPIO_MEM32;
1586 port->port.type = PORT_XSCALE;
1587 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1588 port->port.regshift = 2;
1589
1590 return ret;
1591 }
1592
1593 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1594 pci_omegapci_setup(struct serial_private *priv,
1595 const struct pciserial_board *board,
1596 struct uart_8250_port *port, int idx)
1597 {
1598 return setup_port(priv, port, 2, idx * 8, 0);
1599 }
1600
1601 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1602 pci_brcm_trumanage_setup(struct serial_private *priv,
1603 const struct pciserial_board *board,
1604 struct uart_8250_port *port, int idx)
1605 {
1606 int ret = pci_default_setup(priv, board, port, idx);
1607
1608 port->port.type = PORT_BRCM_TRUMANAGE;
1609 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1610 return ret;
1611 }
1612
1613 /* RTS will control by MCR if this bit is 0 */
1614 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1615 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1616 #define FINTEK_RTS_INVERT BIT(5)
1617
1618 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1619 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios,
1620 struct serial_rs485 *rs485)
1621 {
1622 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1623 u8 setting;
1624 u8 *index = (u8 *) port->private_data;
1625
1626 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1627
1628 if (rs485->flags & SER_RS485_ENABLED) {
1629 /* Enable RTS H/W control mode */
1630 setting |= FINTEK_RTS_CONTROL_BY_HW;
1631
1632 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1633 /* RTS driving high on TX */
1634 setting &= ~FINTEK_RTS_INVERT;
1635 } else {
1636 /* RTS driving low on TX */
1637 setting |= FINTEK_RTS_INVERT;
1638 }
1639 } else {
1640 /* Disable RTS H/W control mode */
1641 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1642 }
1643
1644 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1645
1646 return 0;
1647 }
1648
1649 static const struct serial_rs485 pci_fintek_rs485_supported = {
1650 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
1651 /* F81504/508/512 does not support RTS delay before or after send */
1652 };
1653
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1654 static int pci_fintek_setup(struct serial_private *priv,
1655 const struct pciserial_board *board,
1656 struct uart_8250_port *port, int idx)
1657 {
1658 struct pci_dev *pdev = priv->dev;
1659 u8 *data;
1660 u8 config_base;
1661 u16 iobase;
1662
1663 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1664 return serial_8250_warn_need_ioport(pdev);
1665
1666 config_base = 0x40 + 0x08 * idx;
1667
1668 /* Get the io address from configuration space */
1669 pci_read_config_word(pdev, config_base + 4, &iobase);
1670
1671 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1672
1673 port->port.iotype = UPIO_PORT;
1674 port->port.iobase = iobase;
1675 port->port.rs485_config = pci_fintek_rs485_config;
1676 port->port.rs485_supported = pci_fintek_rs485_supported;
1677
1678 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1679 if (!data)
1680 return -ENOMEM;
1681
1682 /* preserve index in PCI configuration space */
1683 *data = idx;
1684 port->port.private_data = data;
1685
1686 return 0;
1687 }
1688
pci_fintek_init(struct pci_dev * dev)1689 static int pci_fintek_init(struct pci_dev *dev)
1690 {
1691 unsigned long iobase;
1692 u32 max_port, i;
1693 resource_size_t bar_data[3];
1694 u8 config_base;
1695 struct serial_private *priv = pci_get_drvdata(dev);
1696
1697 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1698 return serial_8250_warn_need_ioport(dev);
1699
1700 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1701 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1702 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1703 return -ENODEV;
1704
1705 switch (dev->device) {
1706 case 0x1104: /* 4 ports */
1707 case 0x1108: /* 8 ports */
1708 max_port = dev->device & 0xff;
1709 break;
1710 case 0x1112: /* 12 ports */
1711 max_port = 12;
1712 break;
1713 default:
1714 return -EINVAL;
1715 }
1716
1717 /* Get the io address dispatch from the BIOS */
1718 bar_data[0] = pci_resource_start(dev, 5);
1719 bar_data[1] = pci_resource_start(dev, 4);
1720 bar_data[2] = pci_resource_start(dev, 3);
1721
1722 for (i = 0; i < max_port; ++i) {
1723 /* UART0 configuration offset start from 0x40 */
1724 config_base = 0x40 + 0x08 * i;
1725
1726 /* Calculate Real IO Port */
1727 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1728
1729 /* Enable UART I/O port */
1730 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1731
1732 /* Select 128-byte FIFO and 8x FIFO threshold */
1733 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1734
1735 /* LSB UART */
1736 pci_write_config_byte(dev, config_base + 0x04,
1737 (u8)(iobase & 0xff));
1738
1739 /* MSB UART */
1740 pci_write_config_byte(dev, config_base + 0x05,
1741 (u8)((iobase & 0xff00) >> 8));
1742
1743 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1744
1745 if (!priv) {
1746 /* First init without port data
1747 * force init to RS232 Mode
1748 */
1749 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1750 }
1751 }
1752
1753 return max_port;
1754 }
1755
f815xxa_mem_serial_out(struct uart_port * p,unsigned int offset,u32 value)1756 static void f815xxa_mem_serial_out(struct uart_port *p, unsigned int offset, u32 value)
1757 {
1758 struct f815xxa_data *data = p->private_data;
1759 unsigned long flags;
1760
1761 spin_lock_irqsave(&data->lock, flags);
1762 writeb(value, p->membase + offset);
1763 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1764 spin_unlock_irqrestore(&data->lock, flags);
1765 }
1766
pci_fintek_f815xxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1767 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1768 const struct pciserial_board *board,
1769 struct uart_8250_port *port, int idx)
1770 {
1771 struct pci_dev *pdev = priv->dev;
1772 struct f815xxa_data *data;
1773
1774 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1775 if (!data)
1776 return -ENOMEM;
1777
1778 data->idx = idx;
1779 spin_lock_init(&data->lock);
1780
1781 port->port.private_data = data;
1782 port->port.iotype = UPIO_MEM;
1783 port->port.flags |= UPF_IOREMAP;
1784 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1785 port->port.serial_out = f815xxa_mem_serial_out;
1786
1787 return 0;
1788 }
1789
pci_fintek_f815xxa_init(struct pci_dev * dev)1790 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1791 {
1792 u32 max_port, i;
1793 int config_base;
1794
1795 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1796 return -ENODEV;
1797
1798 switch (dev->device) {
1799 case 0x1204: /* 4 ports */
1800 case 0x1208: /* 8 ports */
1801 max_port = dev->device & 0xff;
1802 break;
1803 case 0x1212: /* 12 ports */
1804 max_port = 12;
1805 break;
1806 default:
1807 return -EINVAL;
1808 }
1809
1810 /* Set to mmio decode */
1811 pci_write_config_byte(dev, 0x209, 0x40);
1812
1813 for (i = 0; i < max_port; ++i) {
1814 /* UART0 configuration offset start from 0x2A0 */
1815 config_base = 0x2A0 + 0x08 * i;
1816
1817 /* Select 128-byte FIFO and 8x FIFO threshold */
1818 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1819
1820 /* Enable UART I/O port */
1821 pci_write_config_byte(dev, config_base + 0, 0x01);
1822 }
1823
1824 return max_port;
1825 }
1826
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1827 static int skip_tx_en_setup(struct serial_private *priv,
1828 const struct pciserial_board *board,
1829 struct uart_8250_port *port, int idx)
1830 {
1831 port->port.quirks |= UPQ_NO_TXEN_TEST;
1832 pci_dbg(priv->dev,
1833 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1834 priv->dev->vendor, priv->dev->device,
1835 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1836
1837 return pci_default_setup(priv, board, port, idx);
1838 }
1839
kt_handle_break(struct uart_port * p)1840 static void kt_handle_break(struct uart_port *p)
1841 {
1842 struct uart_8250_port *up = up_to_u8250p(p);
1843 /*
1844 * On receipt of a BI, serial device in Intel ME (Intel
1845 * management engine) needs to have its fifos cleared for sane
1846 * SOL (Serial Over Lan) output.
1847 */
1848 serial8250_clear_and_reinit_fifos(up);
1849 }
1850
kt_serial_in(struct uart_port * p,unsigned int offset)1851 static u32 kt_serial_in(struct uart_port *p, unsigned int offset)
1852 {
1853 struct uart_8250_port *up = up_to_u8250p(p);
1854 u32 val;
1855
1856 /*
1857 * When the Intel ME (management engine) gets reset its serial
1858 * port registers could return 0 momentarily. Functions like
1859 * serial8250_console_write, read and save the IER, perform
1860 * some operation and then restore it. In order to avoid
1861 * setting IER register inadvertently to 0, if the value read
1862 * is 0, double check with ier value in uart_8250_port and use
1863 * that instead. up->ier should be the same value as what is
1864 * currently configured.
1865 */
1866 val = inb(p->iobase + offset);
1867 if (offset == UART_IER) {
1868 if (val == 0)
1869 val = up->ier;
1870 }
1871 return val;
1872 }
1873
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1874 static int kt_serial_setup(struct serial_private *priv,
1875 const struct pciserial_board *board,
1876 struct uart_8250_port *port, int idx)
1877 {
1878 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1879 return serial_8250_warn_need_ioport(priv->dev);
1880
1881 port->port.flags |= UPF_BUG_THRE;
1882 port->port.serial_in = kt_serial_in;
1883 port->port.handle_break = kt_handle_break;
1884 return skip_tx_en_setup(priv, board, port, idx);
1885 }
1886
pci_eg20t_init(struct pci_dev * dev)1887 static int pci_eg20t_init(struct pci_dev *dev)
1888 {
1889 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1890 return -ENODEV;
1891 #else
1892 return 0;
1893 #endif
1894 }
1895
1896 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1897 pci_wch_ch353_setup(struct serial_private *priv,
1898 const struct pciserial_board *board,
1899 struct uart_8250_port *port, int idx)
1900 {
1901 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1902 return serial_8250_warn_need_ioport(priv->dev);
1903
1904 port->port.flags |= UPF_FIXED_TYPE;
1905 port->port.type = PORT_16550A;
1906 return pci_default_setup(priv, board, port, idx);
1907 }
1908
1909 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1910 pci_wch_ch355_setup(struct serial_private *priv,
1911 const struct pciserial_board *board,
1912 struct uart_8250_port *port, int idx)
1913 {
1914 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1915 return serial_8250_warn_need_ioport(priv->dev);
1916
1917 port->port.flags |= UPF_FIXED_TYPE;
1918 port->port.type = PORT_16550A;
1919 return pci_default_setup(priv, board, port, idx);
1920 }
1921
1922 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1923 pci_wch_ch38x_setup(struct serial_private *priv,
1924 const struct pciserial_board *board,
1925 struct uart_8250_port *port, int idx)
1926 {
1927 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1928 return serial_8250_warn_need_ioport(priv->dev);
1929
1930 port->port.flags |= UPF_FIXED_TYPE;
1931 port->port.type = PORT_16850;
1932 return pci_default_setup(priv, board, port, idx);
1933 }
1934
1935
1936 #define CH384_XINT_ENABLE_REG 0xEB
1937 #define CH384_XINT_ENABLE_BIT 0x02
1938
pci_wch_ch38x_init(struct pci_dev * dev)1939 static int pci_wch_ch38x_init(struct pci_dev *dev)
1940 {
1941 int max_port;
1942 unsigned long iobase;
1943
1944 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1945 return serial_8250_warn_need_ioport(dev);
1946
1947 switch (dev->device) {
1948 case 0x3853: /* 8 ports */
1949 max_port = 8;
1950 break;
1951 default:
1952 return -EINVAL;
1953 }
1954
1955 iobase = pci_resource_start(dev, 0);
1956 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1957
1958 return max_port;
1959 }
1960
pci_wch_ch38x_exit(struct pci_dev * dev)1961 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1962 {
1963 unsigned long iobase;
1964
1965 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) {
1966 serial_8250_warn_need_ioport(dev);
1967 return;
1968 }
1969
1970 iobase = pci_resource_start(dev, 0);
1971 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1972 }
1973
1974
1975 static int
pci_sunix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1976 pci_sunix_setup(struct serial_private *priv,
1977 const struct pciserial_board *board,
1978 struct uart_8250_port *port, int idx)
1979 {
1980 int bar;
1981 int offset;
1982
1983 port->port.flags |= UPF_FIXED_TYPE;
1984 port->port.type = PORT_SUNIX;
1985
1986 if (idx < 4) {
1987 bar = 0;
1988 offset = idx * board->uart_offset;
1989 } else {
1990 bar = 1;
1991 idx -= 4;
1992 idx = div_s64_rem(idx, 4, &offset);
1993 offset = idx * 64 + offset * board->uart_offset;
1994 }
1995
1996 return setup_port(priv, port, bar, offset, 0);
1997 }
1998
1999 #define MOXA_PUART_GPIO_EN 0x09
2000 #define MOXA_PUART_GPIO_OUT 0x0A
2001
2002 #define MOXA_GPIO_PIN2 BIT(2)
2003
2004 #define MOXA_RS232 0x00
2005 #define MOXA_RS422 0x01
2006 #define MOXA_RS485_4W 0x0B
2007 #define MOXA_RS485_2W 0x0F
2008 #define MOXA_UIR_OFFSET 0x04
2009 #define MOXA_EVEN_RS_MASK GENMASK(3, 0)
2010 #define MOXA_ODD_RS_MASK GENMASK(7, 4)
2011
2012 enum {
2013 MOXA_SUPP_RS232 = BIT(0),
2014 MOXA_SUPP_RS422 = BIT(1),
2015 MOXA_SUPP_RS485 = BIT(2),
2016 };
2017
moxa_get_nports(unsigned short device)2018 static unsigned short moxa_get_nports(unsigned short device)
2019 {
2020 switch (device) {
2021 case PCI_DEVICE_ID_MOXA_CP116E_A_A:
2022 case PCI_DEVICE_ID_MOXA_CP116E_A_B:
2023 return 8;
2024 }
2025
2026 return FIELD_GET(0x00F0, device);
2027 }
2028
pci_moxa_is_mini_pcie(unsigned short device)2029 static bool pci_moxa_is_mini_pcie(unsigned short device)
2030 {
2031 if (device == PCI_DEVICE_ID_MOXA_CP102N ||
2032 device == PCI_DEVICE_ID_MOXA_CP104N ||
2033 device == PCI_DEVICE_ID_MOXA_CP112N ||
2034 device == PCI_DEVICE_ID_MOXA_CP114N ||
2035 device == PCI_DEVICE_ID_MOXA_CP132N ||
2036 device == PCI_DEVICE_ID_MOXA_CP134N)
2037 return true;
2038
2039 return false;
2040 }
2041
pci_moxa_supported_rs(struct pci_dev * dev)2042 static unsigned int pci_moxa_supported_rs(struct pci_dev *dev)
2043 {
2044 switch (dev->device & 0x0F00) {
2045 case 0x0000:
2046 case 0x0600:
2047 return MOXA_SUPP_RS232;
2048 case 0x0100:
2049 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2050 case 0x0300:
2051 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2052 }
2053 return 0;
2054 }
2055
pci_moxa_set_interface(const struct pci_dev * dev,unsigned int port_idx,u8 mode)2056 static int pci_moxa_set_interface(const struct pci_dev *dev,
2057 unsigned int port_idx,
2058 u8 mode)
2059 {
2060 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2061 resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2;
2062 u8 val;
2063
2064 val = inb(UIR_addr);
2065
2066 if (port_idx % 2) {
2067 val &= ~MOXA_ODD_RS_MASK;
2068 val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode);
2069 } else {
2070 val &= ~MOXA_EVEN_RS_MASK;
2071 val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode);
2072 }
2073 outb(val, UIR_addr);
2074
2075 return 0;
2076 }
2077
pci_moxa_init(struct pci_dev * dev)2078 static int pci_moxa_init(struct pci_dev *dev)
2079 {
2080 unsigned short device = dev->device;
2081 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2082 unsigned int i, num_ports = moxa_get_nports(device);
2083 u8 val, init_mode = MOXA_RS232;
2084
2085 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
2086 return serial_8250_warn_need_ioport(dev);
2087
2088 if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) {
2089 init_mode = MOXA_RS422;
2090 }
2091 for (i = 0; i < num_ports; ++i)
2092 pci_moxa_set_interface(dev, i, init_mode);
2093
2094 /*
2095 * Enable hardware buffer to prevent break signal output when system boots up.
2096 * This hardware buffer is only supported on Mini PCIe series.
2097 */
2098 if (pci_moxa_is_mini_pcie(device)) {
2099 /* Set GPIO direction */
2100 val = inb(iobar_addr + MOXA_PUART_GPIO_EN);
2101 val |= MOXA_GPIO_PIN2;
2102 outb(val, iobar_addr + MOXA_PUART_GPIO_EN);
2103 /* Enable low GPIO */
2104 val = inb(iobar_addr + MOXA_PUART_GPIO_OUT);
2105 val &= ~MOXA_GPIO_PIN2;
2106 outb(val, iobar_addr + MOXA_PUART_GPIO_OUT);
2107 }
2108
2109 return num_ports;
2110 }
2111
2112 static int
pci_moxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)2113 pci_moxa_setup(struct serial_private *priv,
2114 const struct pciserial_board *board,
2115 struct uart_8250_port *port, int idx)
2116 {
2117 unsigned int bar = FL_GET_BASE(board->flags);
2118 int offset;
2119
2120 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
2121 return serial_8250_warn_need_ioport(priv->dev);
2122
2123 if (board->num_ports == 4 && idx == 3)
2124 offset = 7 * board->uart_offset;
2125 else
2126 offset = idx * board->uart_offset;
2127
2128 return setup_port(priv, port, bar, offset, 0);
2129 }
2130
2131 /*
2132 * Master list of serial port init/setup/exit quirks.
2133 * This does not describe the general nature of the port.
2134 * (ie, baud base, number and location of ports, etc)
2135 *
2136 * This list is ordered alphabetically by vendor then device.
2137 * Specific entries must come before more generic entries.
2138 */
2139 static struct pci_serial_quirk pci_serial_quirks[] = {
2140 /*
2141 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2142 */
2143 {
2144 .vendor = PCI_VENDOR_ID_AMCC,
2145 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2146 .subvendor = PCI_ANY_ID,
2147 .subdevice = PCI_ANY_ID,
2148 .setup = addidata_apci7800_setup,
2149 },
2150 /*
2151 * AFAVLAB cards - these may be called via parport_serial
2152 * It is not clear whether this applies to all products.
2153 */
2154 {
2155 .vendor = PCI_VENDOR_ID_AFAVLAB,
2156 .device = PCI_ANY_ID,
2157 .subvendor = PCI_ANY_ID,
2158 .subdevice = PCI_ANY_ID,
2159 .setup = afavlab_setup,
2160 },
2161 /*
2162 * HP Diva
2163 */
2164 {
2165 .vendor = PCI_VENDOR_ID_HP,
2166 .device = PCI_DEVICE_ID_HP_DIVA,
2167 .subvendor = PCI_ANY_ID,
2168 .subdevice = PCI_ANY_ID,
2169 .init = pci_hp_diva_init,
2170 .setup = pci_hp_diva_setup,
2171 },
2172 /*
2173 * HPE PCI serial device
2174 */
2175 {
2176 .vendor = PCI_VENDOR_ID_HP_3PAR,
2177 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2178 .subvendor = PCI_ANY_ID,
2179 .subdevice = PCI_ANY_ID,
2180 .setup = pci_hp_diva_setup,
2181 },
2182 /*
2183 * Intel
2184 */
2185 {
2186 .vendor = PCI_VENDOR_ID_INTEL,
2187 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2188 .subvendor = 0xe4bf,
2189 .subdevice = PCI_ANY_ID,
2190 .init = pci_inteli960ni_init,
2191 .setup = pci_default_setup,
2192 },
2193 {
2194 .vendor = PCI_VENDOR_ID_INTEL,
2195 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2196 .subvendor = PCI_ANY_ID,
2197 .subdevice = PCI_ANY_ID,
2198 .setup = skip_tx_en_setup,
2199 },
2200 {
2201 .vendor = PCI_VENDOR_ID_INTEL,
2202 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2203 .subvendor = PCI_ANY_ID,
2204 .subdevice = PCI_ANY_ID,
2205 .setup = skip_tx_en_setup,
2206 },
2207 {
2208 .vendor = PCI_VENDOR_ID_INTEL,
2209 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2210 .subvendor = PCI_ANY_ID,
2211 .subdevice = PCI_ANY_ID,
2212 .setup = skip_tx_en_setup,
2213 },
2214 {
2215 .vendor = PCI_VENDOR_ID_INTEL,
2216 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2217 .subvendor = PCI_ANY_ID,
2218 .subdevice = PCI_ANY_ID,
2219 .setup = ce4100_serial_setup,
2220 },
2221 {
2222 .vendor = PCI_VENDOR_ID_INTEL,
2223 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2224 .subvendor = PCI_ANY_ID,
2225 .subdevice = PCI_ANY_ID,
2226 .setup = kt_serial_setup,
2227 },
2228 /*
2229 * ITE
2230 */
2231 {
2232 .vendor = PCI_VENDOR_ID_ITE,
2233 .device = PCI_DEVICE_ID_ITE_8872,
2234 .subvendor = PCI_ANY_ID,
2235 .subdevice = PCI_ANY_ID,
2236 .init = pci_ite887x_init,
2237 .setup = pci_default_setup,
2238 .exit = pci_ite887x_exit,
2239 },
2240 /*
2241 * National Instruments
2242 */
2243 {
2244 .vendor = PCI_VENDOR_ID_NI,
2245 .device = PCI_DEVICE_ID_NI_PCI23216,
2246 .subvendor = PCI_ANY_ID,
2247 .subdevice = PCI_ANY_ID,
2248 .init = pci_ni8420_init,
2249 .setup = pci_default_setup,
2250 .exit = pci_ni8420_exit,
2251 },
2252 {
2253 .vendor = PCI_VENDOR_ID_NI,
2254 .device = PCI_DEVICE_ID_NI_PCI2328,
2255 .subvendor = PCI_ANY_ID,
2256 .subdevice = PCI_ANY_ID,
2257 .init = pci_ni8420_init,
2258 .setup = pci_default_setup,
2259 .exit = pci_ni8420_exit,
2260 },
2261 {
2262 .vendor = PCI_VENDOR_ID_NI,
2263 .device = PCI_DEVICE_ID_NI_PCI2324,
2264 .subvendor = PCI_ANY_ID,
2265 .subdevice = PCI_ANY_ID,
2266 .init = pci_ni8420_init,
2267 .setup = pci_default_setup,
2268 .exit = pci_ni8420_exit,
2269 },
2270 {
2271 .vendor = PCI_VENDOR_ID_NI,
2272 .device = PCI_DEVICE_ID_NI_PCI2322,
2273 .subvendor = PCI_ANY_ID,
2274 .subdevice = PCI_ANY_ID,
2275 .init = pci_ni8420_init,
2276 .setup = pci_default_setup,
2277 .exit = pci_ni8420_exit,
2278 },
2279 {
2280 .vendor = PCI_VENDOR_ID_NI,
2281 .device = PCI_DEVICE_ID_NI_PCI2324I,
2282 .subvendor = PCI_ANY_ID,
2283 .subdevice = PCI_ANY_ID,
2284 .init = pci_ni8420_init,
2285 .setup = pci_default_setup,
2286 .exit = pci_ni8420_exit,
2287 },
2288 {
2289 .vendor = PCI_VENDOR_ID_NI,
2290 .device = PCI_DEVICE_ID_NI_PCI2322I,
2291 .subvendor = PCI_ANY_ID,
2292 .subdevice = PCI_ANY_ID,
2293 .init = pci_ni8420_init,
2294 .setup = pci_default_setup,
2295 .exit = pci_ni8420_exit,
2296 },
2297 {
2298 .vendor = PCI_VENDOR_ID_NI,
2299 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2300 .subvendor = PCI_ANY_ID,
2301 .subdevice = PCI_ANY_ID,
2302 .init = pci_ni8420_init,
2303 .setup = pci_default_setup,
2304 .exit = pci_ni8420_exit,
2305 },
2306 {
2307 .vendor = PCI_VENDOR_ID_NI,
2308 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2309 .subvendor = PCI_ANY_ID,
2310 .subdevice = PCI_ANY_ID,
2311 .init = pci_ni8420_init,
2312 .setup = pci_default_setup,
2313 .exit = pci_ni8420_exit,
2314 },
2315 {
2316 .vendor = PCI_VENDOR_ID_NI,
2317 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2318 .subvendor = PCI_ANY_ID,
2319 .subdevice = PCI_ANY_ID,
2320 .init = pci_ni8420_init,
2321 .setup = pci_default_setup,
2322 .exit = pci_ni8420_exit,
2323 },
2324 {
2325 .vendor = PCI_VENDOR_ID_NI,
2326 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2327 .subvendor = PCI_ANY_ID,
2328 .subdevice = PCI_ANY_ID,
2329 .init = pci_ni8420_init,
2330 .setup = pci_default_setup,
2331 .exit = pci_ni8420_exit,
2332 },
2333 {
2334 .vendor = PCI_VENDOR_ID_NI,
2335 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2336 .subvendor = PCI_ANY_ID,
2337 .subdevice = PCI_ANY_ID,
2338 .init = pci_ni8420_init,
2339 .setup = pci_default_setup,
2340 .exit = pci_ni8420_exit,
2341 },
2342 {
2343 .vendor = PCI_VENDOR_ID_NI,
2344 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2345 .subvendor = PCI_ANY_ID,
2346 .subdevice = PCI_ANY_ID,
2347 .init = pci_ni8420_init,
2348 .setup = pci_default_setup,
2349 .exit = pci_ni8420_exit,
2350 },
2351 {
2352 .vendor = PCI_VENDOR_ID_NI,
2353 .device = PCI_ANY_ID,
2354 .subvendor = PCI_ANY_ID,
2355 .subdevice = PCI_ANY_ID,
2356 .init = pci_ni8430_init,
2357 .setup = pci_ni8430_setup,
2358 .exit = pci_ni8430_exit,
2359 },
2360 /* Quatech */
2361 {
2362 .vendor = PCI_VENDOR_ID_QUATECH,
2363 .device = PCI_ANY_ID,
2364 .subvendor = PCI_ANY_ID,
2365 .subdevice = PCI_ANY_ID,
2366 .init = pci_quatech_init,
2367 .setup = pci_quatech_setup,
2368 },
2369 /*
2370 * Panacom
2371 */
2372 {
2373 .vendor = PCI_VENDOR_ID_PANACOM,
2374 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2375 .subvendor = PCI_ANY_ID,
2376 .subdevice = PCI_ANY_ID,
2377 .init = pci_plx9050_init,
2378 .setup = pci_default_setup,
2379 .exit = pci_plx9050_exit,
2380 },
2381 {
2382 .vendor = PCI_VENDOR_ID_PANACOM,
2383 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2384 .subvendor = PCI_ANY_ID,
2385 .subdevice = PCI_ANY_ID,
2386 .init = pci_plx9050_init,
2387 .setup = pci_default_setup,
2388 .exit = pci_plx9050_exit,
2389 },
2390 /*
2391 * PLX
2392 */
2393 {
2394 .vendor = PCI_VENDOR_ID_PLX,
2395 .device = PCI_DEVICE_ID_PLX_9050,
2396 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2397 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2398 .init = pci_plx9050_init,
2399 .setup = pci_default_setup,
2400 .exit = pci_plx9050_exit,
2401 },
2402 {
2403 .vendor = PCI_VENDOR_ID_PLX,
2404 .device = PCI_DEVICE_ID_PLX_9050,
2405 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2406 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2407 .init = pci_plx9050_init,
2408 .setup = pci_default_setup,
2409 .exit = pci_plx9050_exit,
2410 },
2411 {
2412 .vendor = PCI_VENDOR_ID_PLX,
2413 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2414 .subvendor = PCI_VENDOR_ID_PLX,
2415 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2416 .init = pci_plx9050_init,
2417 .setup = pci_default_setup,
2418 .exit = pci_plx9050_exit,
2419 },
2420 /*
2421 * SBS Technologies, Inc., PMC-OCTALPRO 232
2422 */
2423 {
2424 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2425 .device = PCI_DEVICE_ID_OCTPRO,
2426 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2427 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2428 .init = sbs_init,
2429 .setup = sbs_setup,
2430 .exit = sbs_exit,
2431 },
2432 /*
2433 * SBS Technologies, Inc., PMC-OCTALPRO 422
2434 */
2435 {
2436 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2437 .device = PCI_DEVICE_ID_OCTPRO,
2438 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2439 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2440 .init = sbs_init,
2441 .setup = sbs_setup,
2442 .exit = sbs_exit,
2443 },
2444 /*
2445 * SBS Technologies, Inc., P-Octal 232
2446 */
2447 {
2448 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2449 .device = PCI_DEVICE_ID_OCTPRO,
2450 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2451 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2452 .init = sbs_init,
2453 .setup = sbs_setup,
2454 .exit = sbs_exit,
2455 },
2456 /*
2457 * SBS Technologies, Inc., P-Octal 422
2458 */
2459 {
2460 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2461 .device = PCI_DEVICE_ID_OCTPRO,
2462 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2463 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2464 .init = sbs_init,
2465 .setup = sbs_setup,
2466 .exit = sbs_exit,
2467 },
2468 /*
2469 * SIIG cards - these may be called via parport_serial
2470 */
2471 {
2472 .vendor = PCI_VENDOR_ID_SIIG,
2473 .device = PCI_ANY_ID,
2474 .subvendor = PCI_ANY_ID,
2475 .subdevice = PCI_ANY_ID,
2476 .init = pci_siig_init,
2477 .setup = pci_siig_setup,
2478 },
2479 /*
2480 * Titan cards
2481 */
2482 {
2483 .vendor = PCI_VENDOR_ID_TITAN,
2484 .device = PCI_DEVICE_ID_TITAN_400L,
2485 .subvendor = PCI_ANY_ID,
2486 .subdevice = PCI_ANY_ID,
2487 .setup = titan_400l_800l_setup,
2488 },
2489 {
2490 .vendor = PCI_VENDOR_ID_TITAN,
2491 .device = PCI_DEVICE_ID_TITAN_800L,
2492 .subvendor = PCI_ANY_ID,
2493 .subdevice = PCI_ANY_ID,
2494 .setup = titan_400l_800l_setup,
2495 },
2496 /*
2497 * Timedia cards
2498 */
2499 {
2500 .vendor = PCI_VENDOR_ID_TIMEDIA,
2501 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2502 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2503 .subdevice = PCI_ANY_ID,
2504 .probe = pci_timedia_probe,
2505 .init = pci_timedia_init,
2506 .setup = pci_timedia_setup,
2507 },
2508 {
2509 .vendor = PCI_VENDOR_ID_TIMEDIA,
2510 .device = PCI_ANY_ID,
2511 .subvendor = PCI_ANY_ID,
2512 .subdevice = PCI_ANY_ID,
2513 .setup = pci_timedia_setup,
2514 },
2515 /*
2516 * Sunix PCI serial boards
2517 */
2518 {
2519 .vendor = PCI_VENDOR_ID_SUNIX,
2520 .device = PCI_DEVICE_ID_SUNIX_1999,
2521 .subvendor = PCI_VENDOR_ID_SUNIX,
2522 .subdevice = PCI_ANY_ID,
2523 .setup = pci_sunix_setup,
2524 },
2525 /*
2526 * Xircom cards
2527 */
2528 {
2529 .vendor = PCI_VENDOR_ID_XIRCOM,
2530 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2531 .subvendor = PCI_ANY_ID,
2532 .subdevice = PCI_ANY_ID,
2533 .init = pci_xircom_init,
2534 .setup = pci_default_setup,
2535 },
2536 /*
2537 * Netmos cards - these may be called via parport_serial
2538 */
2539 {
2540 .vendor = PCI_VENDOR_ID_NETMOS,
2541 .device = PCI_ANY_ID,
2542 .subvendor = PCI_ANY_ID,
2543 .subdevice = PCI_ANY_ID,
2544 .init = pci_netmos_init,
2545 .setup = pci_netmos_9900_setup,
2546 },
2547 /*
2548 * EndRun Technologies
2549 */
2550 {
2551 .vendor = PCI_VENDOR_ID_ENDRUN,
2552 .device = PCI_ANY_ID,
2553 .subvendor = PCI_ANY_ID,
2554 .subdevice = PCI_ANY_ID,
2555 .init = pci_oxsemi_tornado_init,
2556 .setup = pci_default_setup,
2557 },
2558 /*
2559 * For Oxford Semiconductor Tornado based devices
2560 */
2561 {
2562 .vendor = PCI_VENDOR_ID_OXSEMI,
2563 .device = PCI_ANY_ID,
2564 .subvendor = PCI_ANY_ID,
2565 .subdevice = PCI_ANY_ID,
2566 .init = pci_oxsemi_tornado_init,
2567 .setup = pci_oxsemi_tornado_setup,
2568 },
2569 {
2570 .vendor = PCI_VENDOR_ID_MAINPINE,
2571 .device = PCI_ANY_ID,
2572 .subvendor = PCI_ANY_ID,
2573 .subdevice = PCI_ANY_ID,
2574 .init = pci_oxsemi_tornado_init,
2575 .setup = pci_oxsemi_tornado_setup,
2576 },
2577 {
2578 .vendor = PCI_VENDOR_ID_DIGI,
2579 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2580 .subvendor = PCI_SUBVENDOR_ID_IBM,
2581 .subdevice = PCI_ANY_ID,
2582 .init = pci_oxsemi_tornado_init,
2583 .setup = pci_oxsemi_tornado_setup,
2584 },
2585 /*
2586 * Brainboxes devices - all Oxsemi based
2587 */
2588 {
2589 .vendor = PCI_VENDOR_ID_INTASHIELD,
2590 .device = 0x4027,
2591 .subvendor = PCI_ANY_ID,
2592 .subdevice = PCI_ANY_ID,
2593 .init = pci_oxsemi_tornado_init,
2594 .setup = pci_oxsemi_tornado_setup,
2595 },
2596 {
2597 .vendor = PCI_VENDOR_ID_INTASHIELD,
2598 .device = 0x4028,
2599 .subvendor = PCI_ANY_ID,
2600 .subdevice = PCI_ANY_ID,
2601 .init = pci_oxsemi_tornado_init,
2602 .setup = pci_oxsemi_tornado_setup,
2603 },
2604 {
2605 .vendor = PCI_VENDOR_ID_INTASHIELD,
2606 .device = 0x4029,
2607 .subvendor = PCI_ANY_ID,
2608 .subdevice = PCI_ANY_ID,
2609 .init = pci_oxsemi_tornado_init,
2610 .setup = pci_oxsemi_tornado_setup,
2611 },
2612 {
2613 .vendor = PCI_VENDOR_ID_INTASHIELD,
2614 .device = 0x4019,
2615 .subvendor = PCI_ANY_ID,
2616 .subdevice = PCI_ANY_ID,
2617 .init = pci_oxsemi_tornado_init,
2618 .setup = pci_oxsemi_tornado_setup,
2619 },
2620 {
2621 .vendor = PCI_VENDOR_ID_INTASHIELD,
2622 .device = 0x4016,
2623 .subvendor = PCI_ANY_ID,
2624 .subdevice = PCI_ANY_ID,
2625 .init = pci_oxsemi_tornado_init,
2626 .setup = pci_oxsemi_tornado_setup,
2627 },
2628 {
2629 .vendor = PCI_VENDOR_ID_INTASHIELD,
2630 .device = 0x4015,
2631 .subvendor = PCI_ANY_ID,
2632 .subdevice = PCI_ANY_ID,
2633 .init = pci_oxsemi_tornado_init,
2634 .setup = pci_oxsemi_tornado_setup,
2635 },
2636 {
2637 .vendor = PCI_VENDOR_ID_INTASHIELD,
2638 .device = 0x400A,
2639 .subvendor = PCI_ANY_ID,
2640 .subdevice = PCI_ANY_ID,
2641 .init = pci_oxsemi_tornado_init,
2642 .setup = pci_oxsemi_tornado_setup,
2643 },
2644 {
2645 .vendor = PCI_VENDOR_ID_INTASHIELD,
2646 .device = 0x400E,
2647 .subvendor = PCI_ANY_ID,
2648 .subdevice = PCI_ANY_ID,
2649 .init = pci_oxsemi_tornado_init,
2650 .setup = pci_oxsemi_tornado_setup,
2651 },
2652 {
2653 .vendor = PCI_VENDOR_ID_INTASHIELD,
2654 .device = 0x400C,
2655 .subvendor = PCI_ANY_ID,
2656 .subdevice = PCI_ANY_ID,
2657 .init = pci_oxsemi_tornado_init,
2658 .setup = pci_oxsemi_tornado_setup,
2659 },
2660 {
2661 .vendor = PCI_VENDOR_ID_INTASHIELD,
2662 .device = 0x400B,
2663 .subvendor = PCI_ANY_ID,
2664 .subdevice = PCI_ANY_ID,
2665 .init = pci_oxsemi_tornado_init,
2666 .setup = pci_oxsemi_tornado_setup,
2667 },
2668 {
2669 .vendor = PCI_VENDOR_ID_INTASHIELD,
2670 .device = 0x400F,
2671 .subvendor = PCI_ANY_ID,
2672 .subdevice = PCI_ANY_ID,
2673 .init = pci_oxsemi_tornado_init,
2674 .setup = pci_oxsemi_tornado_setup,
2675 },
2676 {
2677 .vendor = PCI_VENDOR_ID_INTASHIELD,
2678 .device = 0x4010,
2679 .subvendor = PCI_ANY_ID,
2680 .subdevice = PCI_ANY_ID,
2681 .init = pci_oxsemi_tornado_init,
2682 .setup = pci_oxsemi_tornado_setup,
2683 },
2684 {
2685 .vendor = PCI_VENDOR_ID_INTASHIELD,
2686 .device = 0x4011,
2687 .subvendor = PCI_ANY_ID,
2688 .subdevice = PCI_ANY_ID,
2689 .init = pci_oxsemi_tornado_init,
2690 .setup = pci_oxsemi_tornado_setup,
2691 },
2692 {
2693 .vendor = PCI_VENDOR_ID_INTASHIELD,
2694 .device = 0x401D,
2695 .subvendor = PCI_ANY_ID,
2696 .subdevice = PCI_ANY_ID,
2697 .init = pci_oxsemi_tornado_init,
2698 .setup = pci_oxsemi_tornado_setup,
2699 },
2700 {
2701 .vendor = PCI_VENDOR_ID_INTASHIELD,
2702 .device = 0x401E,
2703 .subvendor = PCI_ANY_ID,
2704 .subdevice = PCI_ANY_ID,
2705 .init = pci_oxsemi_tornado_init,
2706 .setup = pci_oxsemi_tornado_setup,
2707 },
2708 {
2709 .vendor = PCI_VENDOR_ID_INTASHIELD,
2710 .device = 0x4013,
2711 .subvendor = PCI_ANY_ID,
2712 .subdevice = PCI_ANY_ID,
2713 .init = pci_oxsemi_tornado_init,
2714 .setup = pci_oxsemi_tornado_setup,
2715 },
2716 {
2717 .vendor = PCI_VENDOR_ID_INTASHIELD,
2718 .device = 0x4017,
2719 .subvendor = PCI_ANY_ID,
2720 .subdevice = PCI_ANY_ID,
2721 .init = pci_oxsemi_tornado_init,
2722 .setup = pci_oxsemi_tornado_setup,
2723 },
2724 {
2725 .vendor = PCI_VENDOR_ID_INTASHIELD,
2726 .device = 0x4018,
2727 .subvendor = PCI_ANY_ID,
2728 .subdevice = PCI_ANY_ID,
2729 .init = pci_oxsemi_tornado_init,
2730 .setup = pci_oxsemi_tornado_setup,
2731 },
2732 {
2733 .vendor = PCI_VENDOR_ID_INTASHIELD,
2734 .device = 0x4026,
2735 .subvendor = PCI_ANY_ID,
2736 .subdevice = PCI_ANY_ID,
2737 .init = pci_oxsemi_tornado_init,
2738 .setup = pci_oxsemi_tornado_setup,
2739 },
2740 {
2741 .vendor = PCI_VENDOR_ID_INTASHIELD,
2742 .device = 0x4021,
2743 .subvendor = PCI_ANY_ID,
2744 .subdevice = PCI_ANY_ID,
2745 .init = pci_oxsemi_tornado_init,
2746 .setup = pci_oxsemi_tornado_setup,
2747 },
2748 {
2749 .vendor = PCI_VENDOR_ID_INTEL,
2750 .device = 0x8811,
2751 .subvendor = PCI_ANY_ID,
2752 .subdevice = PCI_ANY_ID,
2753 .init = pci_eg20t_init,
2754 .setup = pci_default_setup,
2755 },
2756 {
2757 .vendor = PCI_VENDOR_ID_INTEL,
2758 .device = 0x8812,
2759 .subvendor = PCI_ANY_ID,
2760 .subdevice = PCI_ANY_ID,
2761 .init = pci_eg20t_init,
2762 .setup = pci_default_setup,
2763 },
2764 {
2765 .vendor = PCI_VENDOR_ID_INTEL,
2766 .device = 0x8813,
2767 .subvendor = PCI_ANY_ID,
2768 .subdevice = PCI_ANY_ID,
2769 .init = pci_eg20t_init,
2770 .setup = pci_default_setup,
2771 },
2772 {
2773 .vendor = PCI_VENDOR_ID_INTEL,
2774 .device = 0x8814,
2775 .subvendor = PCI_ANY_ID,
2776 .subdevice = PCI_ANY_ID,
2777 .init = pci_eg20t_init,
2778 .setup = pci_default_setup,
2779 },
2780 {
2781 .vendor = 0x10DB,
2782 .device = 0x8027,
2783 .subvendor = PCI_ANY_ID,
2784 .subdevice = PCI_ANY_ID,
2785 .init = pci_eg20t_init,
2786 .setup = pci_default_setup,
2787 },
2788 {
2789 .vendor = 0x10DB,
2790 .device = 0x8028,
2791 .subvendor = PCI_ANY_ID,
2792 .subdevice = PCI_ANY_ID,
2793 .init = pci_eg20t_init,
2794 .setup = pci_default_setup,
2795 },
2796 {
2797 .vendor = 0x10DB,
2798 .device = 0x8029,
2799 .subvendor = PCI_ANY_ID,
2800 .subdevice = PCI_ANY_ID,
2801 .init = pci_eg20t_init,
2802 .setup = pci_default_setup,
2803 },
2804 {
2805 .vendor = 0x10DB,
2806 .device = 0x800C,
2807 .subvendor = PCI_ANY_ID,
2808 .subdevice = PCI_ANY_ID,
2809 .init = pci_eg20t_init,
2810 .setup = pci_default_setup,
2811 },
2812 {
2813 .vendor = 0x10DB,
2814 .device = 0x800D,
2815 .subvendor = PCI_ANY_ID,
2816 .subdevice = PCI_ANY_ID,
2817 .init = pci_eg20t_init,
2818 .setup = pci_default_setup,
2819 },
2820 /*
2821 * Cronyx Omega PCI (PLX-chip based)
2822 */
2823 {
2824 .vendor = PCI_VENDOR_ID_PLX,
2825 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2826 .subvendor = PCI_ANY_ID,
2827 .subdevice = PCI_ANY_ID,
2828 .setup = pci_omegapci_setup,
2829 },
2830 /* WCH CH353 1S1P card (16550 clone) */
2831 {
2832 .vendor = PCI_VENDOR_ID_WCHCN,
2833 .device = PCI_DEVICE_ID_WCHCN_CH353_1S1P,
2834 .subvendor = PCI_ANY_ID,
2835 .subdevice = PCI_ANY_ID,
2836 .setup = pci_wch_ch353_setup,
2837 },
2838 /* WCH CH353 2S1P card (16550 clone) */
2839 {
2840 .vendor = PCI_VENDOR_ID_WCHCN,
2841 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1P,
2842 .subvendor = PCI_ANY_ID,
2843 .subdevice = PCI_ANY_ID,
2844 .setup = pci_wch_ch353_setup,
2845 },
2846 /* WCH CH353 4S card (16550 clone) */
2847 {
2848 .vendor = PCI_VENDOR_ID_WCHCN,
2849 .device = PCI_DEVICE_ID_WCHCN_CH353_4S,
2850 .subvendor = PCI_ANY_ID,
2851 .subdevice = PCI_ANY_ID,
2852 .setup = pci_wch_ch353_setup,
2853 },
2854 /* WCH CH353 2S1PF card (16550 clone) */
2855 {
2856 .vendor = PCI_VENDOR_ID_WCHCN,
2857 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1PF,
2858 .subvendor = PCI_ANY_ID,
2859 .subdevice = PCI_ANY_ID,
2860 .setup = pci_wch_ch353_setup,
2861 },
2862 /* WCH CH352 2S card (16550 clone) */
2863 {
2864 .vendor = PCI_VENDOR_ID_WCHCN,
2865 .device = PCI_DEVICE_ID_WCHCN_CH352_2S,
2866 .subvendor = PCI_ANY_ID,
2867 .subdevice = PCI_ANY_ID,
2868 .setup = pci_wch_ch353_setup,
2869 },
2870 /* WCH CH355 4S card (16550 clone) */
2871 {
2872 .vendor = PCI_VENDOR_ID_WCHCN,
2873 .device = PCI_DEVICE_ID_WCHCN_CH355_4S,
2874 .subvendor = PCI_ANY_ID,
2875 .subdevice = PCI_ANY_ID,
2876 .setup = pci_wch_ch355_setup,
2877 },
2878 /* WCH CH382 2S card (16850 clone) */
2879 {
2880 .vendor = PCI_VENDOR_ID_WCHIC,
2881 .device = PCI_DEVICE_ID_WCHIC_CH382_2S,
2882 .subvendor = PCI_ANY_ID,
2883 .subdevice = PCI_ANY_ID,
2884 .setup = pci_wch_ch38x_setup,
2885 },
2886 /* WCH CH382 2S1P card (16850 clone) */
2887 {
2888 .vendor = PCI_VENDOR_ID_WCHIC,
2889 .device = PCI_DEVICE_ID_WCHIC_CH382_2S1P,
2890 .subvendor = PCI_ANY_ID,
2891 .subdevice = PCI_ANY_ID,
2892 .setup = pci_wch_ch38x_setup,
2893 },
2894 /* WCH CH384 4S card (16850 clone) */
2895 {
2896 .vendor = PCI_VENDOR_ID_WCHIC,
2897 .device = PCI_DEVICE_ID_WCHIC_CH384_4S,
2898 .subvendor = PCI_ANY_ID,
2899 .subdevice = PCI_ANY_ID,
2900 .setup = pci_wch_ch38x_setup,
2901 },
2902 /* WCH CH384 8S card (16850 clone) */
2903 {
2904 .vendor = PCI_VENDOR_ID_WCHIC,
2905 .device = PCI_DEVICE_ID_WCHIC_CH384_8S,
2906 .subvendor = PCI_ANY_ID,
2907 .subdevice = PCI_ANY_ID,
2908 .init = pci_wch_ch38x_init,
2909 .exit = pci_wch_ch38x_exit,
2910 .setup = pci_wch_ch38x_setup,
2911 },
2912 /*
2913 * Broadcom TruManage (NetXtreme)
2914 */
2915 {
2916 .vendor = PCI_VENDOR_ID_BROADCOM,
2917 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2918 .subvendor = PCI_ANY_ID,
2919 .subdevice = PCI_ANY_ID,
2920 .setup = pci_brcm_trumanage_setup,
2921 },
2922 {
2923 .vendor = 0x1c29,
2924 .device = 0x1104,
2925 .subvendor = PCI_ANY_ID,
2926 .subdevice = PCI_ANY_ID,
2927 .setup = pci_fintek_setup,
2928 .init = pci_fintek_init,
2929 },
2930 {
2931 .vendor = 0x1c29,
2932 .device = 0x1108,
2933 .subvendor = PCI_ANY_ID,
2934 .subdevice = PCI_ANY_ID,
2935 .setup = pci_fintek_setup,
2936 .init = pci_fintek_init,
2937 },
2938 {
2939 .vendor = 0x1c29,
2940 .device = 0x1112,
2941 .subvendor = PCI_ANY_ID,
2942 .subdevice = PCI_ANY_ID,
2943 .setup = pci_fintek_setup,
2944 .init = pci_fintek_init,
2945 },
2946 /*
2947 * MOXA
2948 */
2949 {
2950 .vendor = PCI_VENDOR_ID_MOXA,
2951 .device = PCI_ANY_ID,
2952 .subvendor = PCI_ANY_ID,
2953 .subdevice = PCI_ANY_ID,
2954 .init = pci_moxa_init,
2955 .setup = pci_moxa_setup,
2956 },
2957 {
2958 .vendor = 0x1c29,
2959 .device = 0x1204,
2960 .subvendor = PCI_ANY_ID,
2961 .subdevice = PCI_ANY_ID,
2962 .setup = pci_fintek_f815xxa_setup,
2963 .init = pci_fintek_f815xxa_init,
2964 },
2965 {
2966 .vendor = 0x1c29,
2967 .device = 0x1208,
2968 .subvendor = PCI_ANY_ID,
2969 .subdevice = PCI_ANY_ID,
2970 .setup = pci_fintek_f815xxa_setup,
2971 .init = pci_fintek_f815xxa_init,
2972 },
2973 {
2974 .vendor = 0x1c29,
2975 .device = 0x1212,
2976 .subvendor = PCI_ANY_ID,
2977 .subdevice = PCI_ANY_ID,
2978 .setup = pci_fintek_f815xxa_setup,
2979 .init = pci_fintek_f815xxa_init,
2980 },
2981
2982 /*
2983 * Default "match everything" terminator entry
2984 */
2985 {
2986 .vendor = PCI_ANY_ID,
2987 .device = PCI_ANY_ID,
2988 .subvendor = PCI_ANY_ID,
2989 .subdevice = PCI_ANY_ID,
2990 .setup = pci_default_setup,
2991 }
2992 };
2993
quirk_id_matches(u32 quirk_id,u32 dev_id)2994 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2995 {
2996 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2997 }
2998
find_quirk(struct pci_dev * dev)2999 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
3000 {
3001 struct pci_serial_quirk *quirk;
3002
3003 for (quirk = pci_serial_quirks; ; quirk++)
3004 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
3005 quirk_id_matches(quirk->device, dev->device) &&
3006 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
3007 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
3008 break;
3009 return quirk;
3010 }
3011
3012 /*
3013 * This is the configuration table for all of the PCI serial boards
3014 * which we support. It is directly indexed by the pci_board_num_t enum
3015 * value, which is encoded in the pci_device_id PCI probe table's
3016 * driver_data member.
3017 *
3018 * The makeup of these names are:
3019 * pbn_bn{_bt}_n_baud{_offsetinhex}
3020 *
3021 * bn = PCI BAR number
3022 * bt = Index using PCI BARs
3023 * n = number of serial ports
3024 * baud = baud rate
3025 * offsetinhex = offset for each sequential port (in hex)
3026 *
3027 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
3028 *
3029 * Please note: in theory if n = 1, _bt infix should make no difference.
3030 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
3031 */
3032 enum pci_board_num_t {
3033 pbn_default = 0,
3034
3035 pbn_b0_1_115200,
3036 pbn_b0_2_115200,
3037 pbn_b0_4_115200,
3038 pbn_b0_5_115200,
3039 pbn_b0_8_115200,
3040
3041 pbn_b0_1_921600,
3042 pbn_b0_2_921600,
3043 pbn_b0_4_921600,
3044
3045 pbn_b0_2_1130000,
3046
3047 pbn_b0_4_1152000,
3048
3049 pbn_b0_4_1250000,
3050
3051 pbn_b0_2_1843200,
3052 pbn_b0_4_1843200,
3053
3054 pbn_b0_1_15625000,
3055
3056 pbn_b0_bt_1_115200,
3057 pbn_b0_bt_2_115200,
3058 pbn_b0_bt_4_115200,
3059 pbn_b0_bt_8_115200,
3060
3061 pbn_b0_bt_1_460800,
3062 pbn_b0_bt_2_460800,
3063 pbn_b0_bt_4_460800,
3064
3065 pbn_b0_bt_1_921600,
3066 pbn_b0_bt_2_921600,
3067 pbn_b0_bt_4_921600,
3068 pbn_b0_bt_8_921600,
3069
3070 pbn_b1_1_115200,
3071 pbn_b1_2_115200,
3072 pbn_b1_4_115200,
3073 pbn_b1_8_115200,
3074 pbn_b1_16_115200,
3075
3076 pbn_b1_1_921600,
3077 pbn_b1_2_921600,
3078 pbn_b1_4_921600,
3079 pbn_b1_8_921600,
3080
3081 pbn_b1_2_1250000,
3082
3083 pbn_b1_bt_1_115200,
3084 pbn_b1_bt_2_115200,
3085 pbn_b1_bt_4_115200,
3086
3087 pbn_b1_bt_2_921600,
3088
3089 pbn_b1_1_1382400,
3090 pbn_b1_2_1382400,
3091 pbn_b1_4_1382400,
3092 pbn_b1_8_1382400,
3093
3094 pbn_b2_1_115200,
3095 pbn_b2_2_115200,
3096 pbn_b2_4_115200,
3097 pbn_b2_8_115200,
3098
3099 pbn_b2_1_460800,
3100 pbn_b2_4_460800,
3101 pbn_b2_8_460800,
3102 pbn_b2_16_460800,
3103
3104 pbn_b2_1_921600,
3105 pbn_b2_4_921600,
3106 pbn_b2_8_921600,
3107
3108 pbn_b2_8_1152000,
3109
3110 pbn_b2_bt_1_115200,
3111 pbn_b2_bt_2_115200,
3112 pbn_b2_bt_4_115200,
3113
3114 pbn_b2_bt_2_921600,
3115 pbn_b2_bt_4_921600,
3116
3117 pbn_b3_2_115200,
3118 pbn_b3_4_115200,
3119 pbn_b3_8_115200,
3120
3121 pbn_b4_bt_2_921600,
3122 pbn_b4_bt_4_921600,
3123 pbn_b4_bt_8_921600,
3124
3125 /*
3126 * Board-specific versions.
3127 */
3128 pbn_panacom,
3129 pbn_panacom2,
3130 pbn_panacom4,
3131 pbn_plx_romulus,
3132 pbn_oxsemi,
3133 pbn_oxsemi_1_15625000,
3134 pbn_oxsemi_2_15625000,
3135 pbn_oxsemi_4_15625000,
3136 pbn_oxsemi_8_15625000,
3137 pbn_intel_i960,
3138 pbn_sgi_ioc3,
3139 pbn_computone_4,
3140 pbn_computone_6,
3141 pbn_computone_8,
3142 pbn_sbsxrsio,
3143 pbn_pasemi_1682M,
3144 pbn_ni8430_2,
3145 pbn_ni8430_4,
3146 pbn_ni8430_8,
3147 pbn_ni8430_16,
3148 pbn_ADDIDATA_PCIe_1_3906250,
3149 pbn_ADDIDATA_PCIe_2_3906250,
3150 pbn_ADDIDATA_PCIe_4_3906250,
3151 pbn_ADDIDATA_PCIe_8_3906250,
3152 pbn_ce4100_1_115200,
3153 pbn_omegapci,
3154 pbn_NETMOS9900_2s_115200,
3155 pbn_brcm_trumanage,
3156 pbn_fintek_4,
3157 pbn_fintek_8,
3158 pbn_fintek_12,
3159 pbn_fintek_F81504A,
3160 pbn_fintek_F81508A,
3161 pbn_fintek_F81512A,
3162 pbn_wch382_2,
3163 pbn_wch384_4,
3164 pbn_wch384_8,
3165 pbn_sunix_pci_1s,
3166 pbn_sunix_pci_2s,
3167 pbn_sunix_pci_4s,
3168 pbn_sunix_pci_8s,
3169 pbn_sunix_pci_16s,
3170 pbn_titan_1_4000000,
3171 pbn_titan_2_4000000,
3172 pbn_titan_4_4000000,
3173 pbn_titan_8_4000000,
3174 pbn_moxa_2,
3175 pbn_moxa_4,
3176 pbn_moxa_8,
3177 };
3178
3179 /*
3180 * uart_offset - the space between channels
3181 * reg_shift - describes how the UART registers are mapped
3182 * to PCI memory by the card.
3183 * For example IER register on SBS, Inc. PMC-OctPro is located at
3184 * offset 0x10 from the UART base, while UART_IER is defined as 1
3185 * in include/linux/serial_reg.h,
3186 * see first lines of serial_in() and serial_out() in 8250.c
3187 */
3188
3189 static struct pciserial_board pci_boards[] = {
3190 [pbn_default] = {
3191 .flags = FL_BASE0,
3192 .num_ports = 1,
3193 .base_baud = 115200,
3194 .uart_offset = 8,
3195 },
3196 [pbn_b0_1_115200] = {
3197 .flags = FL_BASE0,
3198 .num_ports = 1,
3199 .base_baud = 115200,
3200 .uart_offset = 8,
3201 },
3202 [pbn_b0_2_115200] = {
3203 .flags = FL_BASE0,
3204 .num_ports = 2,
3205 .base_baud = 115200,
3206 .uart_offset = 8,
3207 },
3208 [pbn_b0_4_115200] = {
3209 .flags = FL_BASE0,
3210 .num_ports = 4,
3211 .base_baud = 115200,
3212 .uart_offset = 8,
3213 },
3214 [pbn_b0_5_115200] = {
3215 .flags = FL_BASE0,
3216 .num_ports = 5,
3217 .base_baud = 115200,
3218 .uart_offset = 8,
3219 },
3220 [pbn_b0_8_115200] = {
3221 .flags = FL_BASE0,
3222 .num_ports = 8,
3223 .base_baud = 115200,
3224 .uart_offset = 8,
3225 },
3226 [pbn_b0_1_921600] = {
3227 .flags = FL_BASE0,
3228 .num_ports = 1,
3229 .base_baud = 921600,
3230 .uart_offset = 8,
3231 },
3232 [pbn_b0_2_921600] = {
3233 .flags = FL_BASE0,
3234 .num_ports = 2,
3235 .base_baud = 921600,
3236 .uart_offset = 8,
3237 },
3238 [pbn_b0_4_921600] = {
3239 .flags = FL_BASE0,
3240 .num_ports = 4,
3241 .base_baud = 921600,
3242 .uart_offset = 8,
3243 },
3244
3245 [pbn_b0_2_1130000] = {
3246 .flags = FL_BASE0,
3247 .num_ports = 2,
3248 .base_baud = 1130000,
3249 .uart_offset = 8,
3250 },
3251
3252 [pbn_b0_4_1152000] = {
3253 .flags = FL_BASE0,
3254 .num_ports = 4,
3255 .base_baud = 1152000,
3256 .uart_offset = 8,
3257 },
3258
3259 [pbn_b0_4_1250000] = {
3260 .flags = FL_BASE0,
3261 .num_ports = 4,
3262 .base_baud = 1250000,
3263 .uart_offset = 8,
3264 },
3265
3266 [pbn_b0_2_1843200] = {
3267 .flags = FL_BASE0,
3268 .num_ports = 2,
3269 .base_baud = 1843200,
3270 .uart_offset = 8,
3271 },
3272 [pbn_b0_4_1843200] = {
3273 .flags = FL_BASE0,
3274 .num_ports = 4,
3275 .base_baud = 1843200,
3276 .uart_offset = 8,
3277 },
3278
3279 [pbn_b0_1_15625000] = {
3280 .flags = FL_BASE0,
3281 .num_ports = 1,
3282 .base_baud = 15625000,
3283 .uart_offset = 8,
3284 },
3285
3286 [pbn_b0_bt_1_115200] = {
3287 .flags = FL_BASE0|FL_BASE_BARS,
3288 .num_ports = 1,
3289 .base_baud = 115200,
3290 .uart_offset = 8,
3291 },
3292 [pbn_b0_bt_2_115200] = {
3293 .flags = FL_BASE0|FL_BASE_BARS,
3294 .num_ports = 2,
3295 .base_baud = 115200,
3296 .uart_offset = 8,
3297 },
3298 [pbn_b0_bt_4_115200] = {
3299 .flags = FL_BASE0|FL_BASE_BARS,
3300 .num_ports = 4,
3301 .base_baud = 115200,
3302 .uart_offset = 8,
3303 },
3304 [pbn_b0_bt_8_115200] = {
3305 .flags = FL_BASE0|FL_BASE_BARS,
3306 .num_ports = 8,
3307 .base_baud = 115200,
3308 .uart_offset = 8,
3309 },
3310
3311 [pbn_b0_bt_1_460800] = {
3312 .flags = FL_BASE0|FL_BASE_BARS,
3313 .num_ports = 1,
3314 .base_baud = 460800,
3315 .uart_offset = 8,
3316 },
3317 [pbn_b0_bt_2_460800] = {
3318 .flags = FL_BASE0|FL_BASE_BARS,
3319 .num_ports = 2,
3320 .base_baud = 460800,
3321 .uart_offset = 8,
3322 },
3323 [pbn_b0_bt_4_460800] = {
3324 .flags = FL_BASE0|FL_BASE_BARS,
3325 .num_ports = 4,
3326 .base_baud = 460800,
3327 .uart_offset = 8,
3328 },
3329
3330 [pbn_b0_bt_1_921600] = {
3331 .flags = FL_BASE0|FL_BASE_BARS,
3332 .num_ports = 1,
3333 .base_baud = 921600,
3334 .uart_offset = 8,
3335 },
3336 [pbn_b0_bt_2_921600] = {
3337 .flags = FL_BASE0|FL_BASE_BARS,
3338 .num_ports = 2,
3339 .base_baud = 921600,
3340 .uart_offset = 8,
3341 },
3342 [pbn_b0_bt_4_921600] = {
3343 .flags = FL_BASE0|FL_BASE_BARS,
3344 .num_ports = 4,
3345 .base_baud = 921600,
3346 .uart_offset = 8,
3347 },
3348 [pbn_b0_bt_8_921600] = {
3349 .flags = FL_BASE0|FL_BASE_BARS,
3350 .num_ports = 8,
3351 .base_baud = 921600,
3352 .uart_offset = 8,
3353 },
3354
3355 [pbn_b1_1_115200] = {
3356 .flags = FL_BASE1,
3357 .num_ports = 1,
3358 .base_baud = 115200,
3359 .uart_offset = 8,
3360 },
3361 [pbn_b1_2_115200] = {
3362 .flags = FL_BASE1,
3363 .num_ports = 2,
3364 .base_baud = 115200,
3365 .uart_offset = 8,
3366 },
3367 [pbn_b1_4_115200] = {
3368 .flags = FL_BASE1,
3369 .num_ports = 4,
3370 .base_baud = 115200,
3371 .uart_offset = 8,
3372 },
3373 [pbn_b1_8_115200] = {
3374 .flags = FL_BASE1,
3375 .num_ports = 8,
3376 .base_baud = 115200,
3377 .uart_offset = 8,
3378 },
3379 [pbn_b1_16_115200] = {
3380 .flags = FL_BASE1,
3381 .num_ports = 16,
3382 .base_baud = 115200,
3383 .uart_offset = 8,
3384 },
3385
3386 [pbn_b1_1_921600] = {
3387 .flags = FL_BASE1,
3388 .num_ports = 1,
3389 .base_baud = 921600,
3390 .uart_offset = 8,
3391 },
3392 [pbn_b1_2_921600] = {
3393 .flags = FL_BASE1,
3394 .num_ports = 2,
3395 .base_baud = 921600,
3396 .uart_offset = 8,
3397 },
3398 [pbn_b1_4_921600] = {
3399 .flags = FL_BASE1,
3400 .num_ports = 4,
3401 .base_baud = 921600,
3402 .uart_offset = 8,
3403 },
3404 [pbn_b1_8_921600] = {
3405 .flags = FL_BASE1,
3406 .num_ports = 8,
3407 .base_baud = 921600,
3408 .uart_offset = 8,
3409 },
3410 [pbn_b1_2_1250000] = {
3411 .flags = FL_BASE1,
3412 .num_ports = 2,
3413 .base_baud = 1250000,
3414 .uart_offset = 8,
3415 },
3416
3417 [pbn_b1_bt_1_115200] = {
3418 .flags = FL_BASE1|FL_BASE_BARS,
3419 .num_ports = 1,
3420 .base_baud = 115200,
3421 .uart_offset = 8,
3422 },
3423 [pbn_b1_bt_2_115200] = {
3424 .flags = FL_BASE1|FL_BASE_BARS,
3425 .num_ports = 2,
3426 .base_baud = 115200,
3427 .uart_offset = 8,
3428 },
3429 [pbn_b1_bt_4_115200] = {
3430 .flags = FL_BASE1|FL_BASE_BARS,
3431 .num_ports = 4,
3432 .base_baud = 115200,
3433 .uart_offset = 8,
3434 },
3435
3436 [pbn_b1_bt_2_921600] = {
3437 .flags = FL_BASE1|FL_BASE_BARS,
3438 .num_ports = 2,
3439 .base_baud = 921600,
3440 .uart_offset = 8,
3441 },
3442
3443 [pbn_b1_1_1382400] = {
3444 .flags = FL_BASE1,
3445 .num_ports = 1,
3446 .base_baud = 1382400,
3447 .uart_offset = 8,
3448 },
3449 [pbn_b1_2_1382400] = {
3450 .flags = FL_BASE1,
3451 .num_ports = 2,
3452 .base_baud = 1382400,
3453 .uart_offset = 8,
3454 },
3455 [pbn_b1_4_1382400] = {
3456 .flags = FL_BASE1,
3457 .num_ports = 4,
3458 .base_baud = 1382400,
3459 .uart_offset = 8,
3460 },
3461 [pbn_b1_8_1382400] = {
3462 .flags = FL_BASE1,
3463 .num_ports = 8,
3464 .base_baud = 1382400,
3465 .uart_offset = 8,
3466 },
3467
3468 [pbn_b2_1_115200] = {
3469 .flags = FL_BASE2,
3470 .num_ports = 1,
3471 .base_baud = 115200,
3472 .uart_offset = 8,
3473 },
3474 [pbn_b2_2_115200] = {
3475 .flags = FL_BASE2,
3476 .num_ports = 2,
3477 .base_baud = 115200,
3478 .uart_offset = 8,
3479 },
3480 [pbn_b2_4_115200] = {
3481 .flags = FL_BASE2,
3482 .num_ports = 4,
3483 .base_baud = 115200,
3484 .uart_offset = 8,
3485 },
3486 [pbn_b2_8_115200] = {
3487 .flags = FL_BASE2,
3488 .num_ports = 8,
3489 .base_baud = 115200,
3490 .uart_offset = 8,
3491 },
3492
3493 [pbn_b2_1_460800] = {
3494 .flags = FL_BASE2,
3495 .num_ports = 1,
3496 .base_baud = 460800,
3497 .uart_offset = 8,
3498 },
3499 [pbn_b2_4_460800] = {
3500 .flags = FL_BASE2,
3501 .num_ports = 4,
3502 .base_baud = 460800,
3503 .uart_offset = 8,
3504 },
3505 [pbn_b2_8_460800] = {
3506 .flags = FL_BASE2,
3507 .num_ports = 8,
3508 .base_baud = 460800,
3509 .uart_offset = 8,
3510 },
3511 [pbn_b2_16_460800] = {
3512 .flags = FL_BASE2,
3513 .num_ports = 16,
3514 .base_baud = 460800,
3515 .uart_offset = 8,
3516 },
3517
3518 [pbn_b2_1_921600] = {
3519 .flags = FL_BASE2,
3520 .num_ports = 1,
3521 .base_baud = 921600,
3522 .uart_offset = 8,
3523 },
3524 [pbn_b2_4_921600] = {
3525 .flags = FL_BASE2,
3526 .num_ports = 4,
3527 .base_baud = 921600,
3528 .uart_offset = 8,
3529 },
3530 [pbn_b2_8_921600] = {
3531 .flags = FL_BASE2,
3532 .num_ports = 8,
3533 .base_baud = 921600,
3534 .uart_offset = 8,
3535 },
3536
3537 [pbn_b2_8_1152000] = {
3538 .flags = FL_BASE2,
3539 .num_ports = 8,
3540 .base_baud = 1152000,
3541 .uart_offset = 8,
3542 },
3543
3544 [pbn_b2_bt_1_115200] = {
3545 .flags = FL_BASE2|FL_BASE_BARS,
3546 .num_ports = 1,
3547 .base_baud = 115200,
3548 .uart_offset = 8,
3549 },
3550 [pbn_b2_bt_2_115200] = {
3551 .flags = FL_BASE2|FL_BASE_BARS,
3552 .num_ports = 2,
3553 .base_baud = 115200,
3554 .uart_offset = 8,
3555 },
3556 [pbn_b2_bt_4_115200] = {
3557 .flags = FL_BASE2|FL_BASE_BARS,
3558 .num_ports = 4,
3559 .base_baud = 115200,
3560 .uart_offset = 8,
3561 },
3562
3563 [pbn_b2_bt_2_921600] = {
3564 .flags = FL_BASE2|FL_BASE_BARS,
3565 .num_ports = 2,
3566 .base_baud = 921600,
3567 .uart_offset = 8,
3568 },
3569 [pbn_b2_bt_4_921600] = {
3570 .flags = FL_BASE2|FL_BASE_BARS,
3571 .num_ports = 4,
3572 .base_baud = 921600,
3573 .uart_offset = 8,
3574 },
3575
3576 [pbn_b3_2_115200] = {
3577 .flags = FL_BASE3,
3578 .num_ports = 2,
3579 .base_baud = 115200,
3580 .uart_offset = 8,
3581 },
3582 [pbn_b3_4_115200] = {
3583 .flags = FL_BASE3,
3584 .num_ports = 4,
3585 .base_baud = 115200,
3586 .uart_offset = 8,
3587 },
3588 [pbn_b3_8_115200] = {
3589 .flags = FL_BASE3,
3590 .num_ports = 8,
3591 .base_baud = 115200,
3592 .uart_offset = 8,
3593 },
3594
3595 [pbn_b4_bt_2_921600] = {
3596 .flags = FL_BASE4,
3597 .num_ports = 2,
3598 .base_baud = 921600,
3599 .uart_offset = 8,
3600 },
3601 [pbn_b4_bt_4_921600] = {
3602 .flags = FL_BASE4,
3603 .num_ports = 4,
3604 .base_baud = 921600,
3605 .uart_offset = 8,
3606 },
3607 [pbn_b4_bt_8_921600] = {
3608 .flags = FL_BASE4,
3609 .num_ports = 8,
3610 .base_baud = 921600,
3611 .uart_offset = 8,
3612 },
3613
3614 /*
3615 * Entries following this are board-specific.
3616 */
3617
3618 /*
3619 * Panacom - IOMEM
3620 */
3621 [pbn_panacom] = {
3622 .flags = FL_BASE2,
3623 .num_ports = 2,
3624 .base_baud = 921600,
3625 .uart_offset = 0x400,
3626 .reg_shift = 7,
3627 },
3628 [pbn_panacom2] = {
3629 .flags = FL_BASE2|FL_BASE_BARS,
3630 .num_ports = 2,
3631 .base_baud = 921600,
3632 .uart_offset = 0x400,
3633 .reg_shift = 7,
3634 },
3635 [pbn_panacom4] = {
3636 .flags = FL_BASE2|FL_BASE_BARS,
3637 .num_ports = 4,
3638 .base_baud = 921600,
3639 .uart_offset = 0x400,
3640 .reg_shift = 7,
3641 },
3642
3643 /* I think this entry is broken - the first_offset looks wrong --rmk */
3644 [pbn_plx_romulus] = {
3645 .flags = FL_BASE2,
3646 .num_ports = 4,
3647 .base_baud = 921600,
3648 .uart_offset = 8 << 2,
3649 .reg_shift = 2,
3650 .first_offset = 0x03,
3651 },
3652
3653 /*
3654 * This board uses the size of PCI Base region 0 to
3655 * signal now many ports are available
3656 */
3657 [pbn_oxsemi] = {
3658 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3659 .num_ports = 32,
3660 .base_baud = 115200,
3661 .uart_offset = 8,
3662 },
3663 [pbn_oxsemi_1_15625000] = {
3664 .flags = FL_BASE0,
3665 .num_ports = 1,
3666 .base_baud = 15625000,
3667 .uart_offset = 0x200,
3668 .first_offset = 0x1000,
3669 },
3670 [pbn_oxsemi_2_15625000] = {
3671 .flags = FL_BASE0,
3672 .num_ports = 2,
3673 .base_baud = 15625000,
3674 .uart_offset = 0x200,
3675 .first_offset = 0x1000,
3676 },
3677 [pbn_oxsemi_4_15625000] = {
3678 .flags = FL_BASE0,
3679 .num_ports = 4,
3680 .base_baud = 15625000,
3681 .uart_offset = 0x200,
3682 .first_offset = 0x1000,
3683 },
3684 [pbn_oxsemi_8_15625000] = {
3685 .flags = FL_BASE0,
3686 .num_ports = 8,
3687 .base_baud = 15625000,
3688 .uart_offset = 0x200,
3689 .first_offset = 0x1000,
3690 },
3691
3692
3693 /*
3694 * EKF addition for i960 Boards form EKF with serial port.
3695 * Max 256 ports.
3696 */
3697 [pbn_intel_i960] = {
3698 .flags = FL_BASE0,
3699 .num_ports = 32,
3700 .base_baud = 921600,
3701 .uart_offset = 8 << 2,
3702 .reg_shift = 2,
3703 .first_offset = 0x10000,
3704 },
3705 [pbn_sgi_ioc3] = {
3706 .flags = FL_BASE0|FL_NOIRQ,
3707 .num_ports = 1,
3708 .base_baud = 458333,
3709 .uart_offset = 8,
3710 .reg_shift = 0,
3711 .first_offset = 0x20178,
3712 },
3713
3714 /*
3715 * Computone - uses IOMEM.
3716 */
3717 [pbn_computone_4] = {
3718 .flags = FL_BASE0,
3719 .num_ports = 4,
3720 .base_baud = 921600,
3721 .uart_offset = 0x40,
3722 .reg_shift = 2,
3723 .first_offset = 0x200,
3724 },
3725 [pbn_computone_6] = {
3726 .flags = FL_BASE0,
3727 .num_ports = 6,
3728 .base_baud = 921600,
3729 .uart_offset = 0x40,
3730 .reg_shift = 2,
3731 .first_offset = 0x200,
3732 },
3733 [pbn_computone_8] = {
3734 .flags = FL_BASE0,
3735 .num_ports = 8,
3736 .base_baud = 921600,
3737 .uart_offset = 0x40,
3738 .reg_shift = 2,
3739 .first_offset = 0x200,
3740 },
3741 [pbn_sbsxrsio] = {
3742 .flags = FL_BASE0,
3743 .num_ports = 8,
3744 .base_baud = 460800,
3745 .uart_offset = 256,
3746 .reg_shift = 4,
3747 },
3748 /*
3749 * PA Semi PWRficient PA6T-1682M on-chip UART
3750 */
3751 [pbn_pasemi_1682M] = {
3752 .flags = FL_BASE0,
3753 .num_ports = 1,
3754 .base_baud = 8333333,
3755 },
3756 /*
3757 * National Instruments 843x
3758 */
3759 [pbn_ni8430_16] = {
3760 .flags = FL_BASE0,
3761 .num_ports = 16,
3762 .base_baud = 3686400,
3763 .uart_offset = 0x10,
3764 .first_offset = 0x800,
3765 },
3766 [pbn_ni8430_8] = {
3767 .flags = FL_BASE0,
3768 .num_ports = 8,
3769 .base_baud = 3686400,
3770 .uart_offset = 0x10,
3771 .first_offset = 0x800,
3772 },
3773 [pbn_ni8430_4] = {
3774 .flags = FL_BASE0,
3775 .num_ports = 4,
3776 .base_baud = 3686400,
3777 .uart_offset = 0x10,
3778 .first_offset = 0x800,
3779 },
3780 [pbn_ni8430_2] = {
3781 .flags = FL_BASE0,
3782 .num_ports = 2,
3783 .base_baud = 3686400,
3784 .uart_offset = 0x10,
3785 .first_offset = 0x800,
3786 },
3787 /*
3788 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3789 */
3790 [pbn_ADDIDATA_PCIe_1_3906250] = {
3791 .flags = FL_BASE0,
3792 .num_ports = 1,
3793 .base_baud = 3906250,
3794 .uart_offset = 0x200,
3795 .first_offset = 0x1000,
3796 },
3797 [pbn_ADDIDATA_PCIe_2_3906250] = {
3798 .flags = FL_BASE0,
3799 .num_ports = 2,
3800 .base_baud = 3906250,
3801 .uart_offset = 0x200,
3802 .first_offset = 0x1000,
3803 },
3804 [pbn_ADDIDATA_PCIe_4_3906250] = {
3805 .flags = FL_BASE0,
3806 .num_ports = 4,
3807 .base_baud = 3906250,
3808 .uart_offset = 0x200,
3809 .first_offset = 0x1000,
3810 },
3811 [pbn_ADDIDATA_PCIe_8_3906250] = {
3812 .flags = FL_BASE0,
3813 .num_ports = 8,
3814 .base_baud = 3906250,
3815 .uart_offset = 0x200,
3816 .first_offset = 0x1000,
3817 },
3818 [pbn_ce4100_1_115200] = {
3819 .flags = FL_BASE_BARS,
3820 .num_ports = 2,
3821 .base_baud = 921600,
3822 .reg_shift = 2,
3823 },
3824 [pbn_omegapci] = {
3825 .flags = FL_BASE0,
3826 .num_ports = 8,
3827 .base_baud = 115200,
3828 .uart_offset = 0x200,
3829 },
3830 [pbn_NETMOS9900_2s_115200] = {
3831 .flags = FL_BASE0,
3832 .num_ports = 2,
3833 .base_baud = 115200,
3834 },
3835 [pbn_brcm_trumanage] = {
3836 .flags = FL_BASE0,
3837 .num_ports = 1,
3838 .reg_shift = 2,
3839 .base_baud = 115200,
3840 },
3841 [pbn_fintek_4] = {
3842 .num_ports = 4,
3843 .uart_offset = 8,
3844 .base_baud = 115200,
3845 .first_offset = 0x40,
3846 },
3847 [pbn_fintek_8] = {
3848 .num_ports = 8,
3849 .uart_offset = 8,
3850 .base_baud = 115200,
3851 .first_offset = 0x40,
3852 },
3853 [pbn_fintek_12] = {
3854 .num_ports = 12,
3855 .uart_offset = 8,
3856 .base_baud = 115200,
3857 .first_offset = 0x40,
3858 },
3859 [pbn_fintek_F81504A] = {
3860 .num_ports = 4,
3861 .uart_offset = 8,
3862 .base_baud = 115200,
3863 },
3864 [pbn_fintek_F81508A] = {
3865 .num_ports = 8,
3866 .uart_offset = 8,
3867 .base_baud = 115200,
3868 },
3869 [pbn_fintek_F81512A] = {
3870 .num_ports = 12,
3871 .uart_offset = 8,
3872 .base_baud = 115200,
3873 },
3874 [pbn_wch382_2] = {
3875 .flags = FL_BASE0,
3876 .num_ports = 2,
3877 .base_baud = 115200,
3878 .uart_offset = 8,
3879 .first_offset = 0xC0,
3880 },
3881 [pbn_wch384_4] = {
3882 .flags = FL_BASE0,
3883 .num_ports = 4,
3884 .base_baud = 115200,
3885 .uart_offset = 8,
3886 .first_offset = 0xC0,
3887 },
3888 [pbn_wch384_8] = {
3889 .flags = FL_BASE0,
3890 .num_ports = 8,
3891 .base_baud = 115200,
3892 .uart_offset = 8,
3893 .first_offset = 0x00,
3894 },
3895 [pbn_sunix_pci_1s] = {
3896 .num_ports = 1,
3897 .base_baud = 921600,
3898 .uart_offset = 0x8,
3899 },
3900 [pbn_sunix_pci_2s] = {
3901 .num_ports = 2,
3902 .base_baud = 921600,
3903 .uart_offset = 0x8,
3904 },
3905 [pbn_sunix_pci_4s] = {
3906 .num_ports = 4,
3907 .base_baud = 921600,
3908 .uart_offset = 0x8,
3909 },
3910 [pbn_sunix_pci_8s] = {
3911 .num_ports = 8,
3912 .base_baud = 921600,
3913 .uart_offset = 0x8,
3914 },
3915 [pbn_sunix_pci_16s] = {
3916 .num_ports = 16,
3917 .base_baud = 921600,
3918 .uart_offset = 0x8,
3919 },
3920 [pbn_titan_1_4000000] = {
3921 .flags = FL_BASE0,
3922 .num_ports = 1,
3923 .base_baud = 4000000,
3924 .uart_offset = 0x200,
3925 .first_offset = 0x1000,
3926 },
3927 [pbn_titan_2_4000000] = {
3928 .flags = FL_BASE0,
3929 .num_ports = 2,
3930 .base_baud = 4000000,
3931 .uart_offset = 0x200,
3932 .first_offset = 0x1000,
3933 },
3934 [pbn_titan_4_4000000] = {
3935 .flags = FL_BASE0,
3936 .num_ports = 4,
3937 .base_baud = 4000000,
3938 .uart_offset = 0x200,
3939 .first_offset = 0x1000,
3940 },
3941 [pbn_titan_8_4000000] = {
3942 .flags = FL_BASE0,
3943 .num_ports = 8,
3944 .base_baud = 4000000,
3945 .uart_offset = 0x200,
3946 .first_offset = 0x1000,
3947 },
3948 [pbn_moxa_2] = {
3949 .flags = FL_BASE1,
3950 .num_ports = 2,
3951 .base_baud = 921600,
3952 .uart_offset = 0x200,
3953 },
3954 [pbn_moxa_4] = {
3955 .flags = FL_BASE1,
3956 .num_ports = 4,
3957 .base_baud = 921600,
3958 .uart_offset = 0x200,
3959 },
3960 [pbn_moxa_8] = {
3961 .flags = FL_BASE1,
3962 .num_ports = 8,
3963 .base_baud = 921600,
3964 .uart_offset = 0x200,
3965 },
3966 };
3967
3968 #define REPORT_CONFIG(option) \
3969 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
3970 #define REPORT_8250_CONFIG(option) \
3971 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
3972 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
3973
3974 static const struct pci_device_id blacklist[] = {
3975 /* softmodems */
3976 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3977 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3978 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3979
3980 /* multi-io cards handled by parport_serial */
3981 /* WCH CH353 2S1P */
3982 { PCI_VDEVICE(WCHCN, 0x7053), REPORT_CONFIG(PARPORT_SERIAL), },
3983 /* WCH CH353 1S1P */
3984 { PCI_VDEVICE(WCHCN, 0x5053), REPORT_CONFIG(PARPORT_SERIAL), },
3985 /* WCH CH382 2S1P */
3986 { PCI_VDEVICE(WCHIC, 0x3250), REPORT_CONFIG(PARPORT_SERIAL), },
3987
3988 /* Intel platforms with MID UART */
3989 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
3990 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
3991 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
3992 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
3993 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
3994 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
3995
3996 /* Intel platforms with DesignWare UART */
3997 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
3998 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
3999 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
4000 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
4001 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
4002 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
4003 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
4004 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
4005 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
4006 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
4007 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
4008 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
4009 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
4010
4011 /* Exar devices */
4012 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
4013 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
4014
4015 /* Pericom devices */
4016 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
4017 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
4018
4019 /* End of the black list */
4020 { }
4021 };
4022
serial_pci_is_class_communication(struct pci_dev * dev)4023 static int serial_pci_is_class_communication(struct pci_dev *dev)
4024 {
4025 /*
4026 * If it is not a communications device or the programming
4027 * interface is greater than 6, give up.
4028 */
4029 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
4030 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
4031 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
4032 (dev->class & 0xff) > 6)
4033 return -ENODEV;
4034
4035 return 0;
4036 }
4037
4038 /*
4039 * Given a complete unknown PCI device, try to use some heuristics to
4040 * guess what the configuration might be, based on the pitiful PCI
4041 * serial specs. Returns 0 on success, -ENODEV on failure.
4042 */
4043 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)4044 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
4045 {
4046 int num_iomem, num_port, first_port = -1, i;
4047 int rc;
4048
4049 rc = serial_pci_is_class_communication(dev);
4050 if (rc)
4051 return rc;
4052
4053 /*
4054 * Should we try to make guesses for multiport serial devices later?
4055 */
4056 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
4057 return -ENODEV;
4058
4059 num_iomem = num_port = 0;
4060 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4061 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4062 num_port++;
4063 if (first_port == -1)
4064 first_port = i;
4065 }
4066 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4067 num_iomem++;
4068 }
4069
4070 /*
4071 * If there is 1 or 0 iomem regions, and exactly one port,
4072 * use it. We guess the number of ports based on the IO
4073 * region size.
4074 */
4075 if (num_iomem <= 1 && num_port == 1) {
4076 board->flags = first_port;
4077 board->num_ports = pci_resource_len(dev, first_port) / 8;
4078 return 0;
4079 }
4080
4081 /*
4082 * Now guess if we've got a board which indexes by BARs.
4083 * Each IO BAR should be 8 bytes, and they should follow
4084 * consecutively.
4085 */
4086 first_port = -1;
4087 num_port = 0;
4088 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4089 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4090 pci_resource_len(dev, i) == 8 &&
4091 (first_port == -1 || (first_port + num_port) == i)) {
4092 num_port++;
4093 if (first_port == -1)
4094 first_port = i;
4095 }
4096 }
4097
4098 if (num_port > 1) {
4099 board->flags = first_port | FL_BASE_BARS;
4100 board->num_ports = num_port;
4101 return 0;
4102 }
4103
4104 return -ENODEV;
4105 }
4106
4107 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)4108 serial_pci_matches(const struct pciserial_board *board,
4109 const struct pciserial_board *guessed)
4110 {
4111 return
4112 board->num_ports == guessed->num_ports &&
4113 board->base_baud == guessed->base_baud &&
4114 board->uart_offset == guessed->uart_offset &&
4115 board->reg_shift == guessed->reg_shift &&
4116 board->first_offset == guessed->first_offset;
4117 }
4118
4119 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)4120 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
4121 {
4122 struct uart_8250_port uart;
4123 struct serial_private *priv;
4124 struct pci_serial_quirk *quirk;
4125 int rc, nr_ports, i;
4126
4127 nr_ports = board->num_ports;
4128
4129 /*
4130 * Find an init and setup quirks.
4131 */
4132 quirk = find_quirk(dev);
4133
4134 /*
4135 * Run the new-style initialization function.
4136 * The initialization function returns:
4137 * <0 - error
4138 * 0 - use board->num_ports
4139 * >0 - number of ports
4140 */
4141 if (quirk->init) {
4142 rc = quirk->init(dev);
4143 if (rc < 0) {
4144 priv = ERR_PTR(rc);
4145 goto err_out;
4146 }
4147 if (rc)
4148 nr_ports = rc;
4149 }
4150
4151 priv = kzalloc_flex(*priv, line, nr_ports);
4152 if (!priv) {
4153 priv = ERR_PTR(-ENOMEM);
4154 goto err_deinit;
4155 }
4156
4157 priv->dev = dev;
4158 priv->quirk = quirk;
4159
4160 memset(&uart, 0, sizeof(uart));
4161 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4162 uart.port.uartclk = board->base_baud * 16;
4163
4164 if (board->flags & FL_NOIRQ) {
4165 uart.port.irq = 0;
4166 } else {
4167 if (pci_match_id(pci_use_msi, dev)) {
4168 pci_dbg(dev, "Using MSI(-X) interrupts\n");
4169 pci_set_master(dev);
4170 uart.port.flags &= ~UPF_SHARE_IRQ;
4171 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
4172 } else {
4173 pci_dbg(dev, "Using legacy interrupts\n");
4174 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_INTX);
4175 }
4176 if (rc < 0) {
4177 kfree(priv);
4178 priv = ERR_PTR(rc);
4179 goto err_deinit;
4180 }
4181
4182 uart.port.irq = pci_irq_vector(dev, 0);
4183 }
4184
4185 uart.port.dev = &dev->dev;
4186
4187 for (i = 0; i < nr_ports; i++) {
4188 if (quirk->setup(priv, board, &uart, i))
4189 break;
4190
4191 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4192 uart.port.iobase, uart.port.irq, uart.port.iotype);
4193
4194 priv->line[i] = serial8250_register_8250_port(&uart);
4195 if (priv->line[i] < 0) {
4196 pci_err(dev,
4197 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4198 uart.port.iobase, uart.port.irq,
4199 uart.port.iotype, priv->line[i]);
4200 break;
4201 }
4202 }
4203 priv->nr = i;
4204 priv->board = board;
4205 return priv;
4206
4207 err_deinit:
4208 if (quirk->exit)
4209 quirk->exit(dev);
4210 err_out:
4211 return priv;
4212 }
4213 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4214
pciserial_detach_ports(struct serial_private * priv)4215 static void pciserial_detach_ports(struct serial_private *priv)
4216 {
4217 struct pci_serial_quirk *quirk;
4218 int i;
4219
4220 for (i = 0; i < priv->nr; i++)
4221 serial8250_unregister_port(priv->line[i]);
4222
4223 /*
4224 * Find the exit quirks.
4225 */
4226 quirk = find_quirk(priv->dev);
4227 if (quirk->exit)
4228 quirk->exit(priv->dev);
4229 }
4230
pciserial_remove_ports(struct serial_private * priv)4231 void pciserial_remove_ports(struct serial_private *priv)
4232 {
4233 pciserial_detach_ports(priv);
4234 kfree(priv);
4235 }
4236 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4237
pciserial_suspend_ports(struct serial_private * priv)4238 void pciserial_suspend_ports(struct serial_private *priv)
4239 {
4240 int i;
4241
4242 for (i = 0; i < priv->nr; i++)
4243 if (priv->line[i] >= 0)
4244 serial8250_suspend_port(priv->line[i]);
4245
4246 /*
4247 * Ensure that every init quirk is properly torn down
4248 */
4249 if (priv->quirk->exit)
4250 priv->quirk->exit(priv->dev);
4251 }
4252 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4253
pciserial_resume_ports(struct serial_private * priv)4254 void pciserial_resume_ports(struct serial_private *priv)
4255 {
4256 int i;
4257
4258 /*
4259 * Ensure that the board is correctly configured.
4260 */
4261 if (priv->quirk->init)
4262 priv->quirk->init(priv->dev);
4263
4264 for (i = 0; i < priv->nr; i++)
4265 if (priv->line[i] >= 0)
4266 serial8250_resume_port(priv->line[i]);
4267 }
4268 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4269
4270 /*
4271 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4272 * to the arrangement of serial ports on a PCI card.
4273 */
4274 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)4275 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4276 {
4277 struct pci_serial_quirk *quirk;
4278 struct serial_private *priv;
4279 const struct pciserial_board *board;
4280 const struct pci_device_id *exclude;
4281 struct pciserial_board tmp;
4282 int rc;
4283
4284 quirk = find_quirk(dev);
4285 if (quirk->probe) {
4286 rc = quirk->probe(dev);
4287 if (rc)
4288 return rc;
4289 }
4290
4291 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4292 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
4293 return -EINVAL;
4294 }
4295
4296 board = &pci_boards[ent->driver_data];
4297
4298 exclude = pci_match_id(blacklist, dev);
4299 if (exclude) {
4300 if (exclude->driver_data)
4301 pci_warn(dev, "ignoring port, enable %s to handle\n",
4302 (const char *)exclude->driver_data);
4303 return -ENODEV;
4304 }
4305
4306 rc = pcim_enable_device(dev);
4307 pci_save_state(dev);
4308 if (rc)
4309 return rc;
4310
4311 if (ent->driver_data == pbn_default) {
4312 /*
4313 * Use a copy of the pci_board entry for this;
4314 * avoid changing entries in the table.
4315 */
4316 memcpy(&tmp, board, sizeof(struct pciserial_board));
4317 board = &tmp;
4318
4319 /*
4320 * We matched one of our class entries. Try to
4321 * determine the parameters of this board.
4322 */
4323 rc = serial_pci_guess_board(dev, &tmp);
4324 if (rc)
4325 return rc;
4326 } else {
4327 /*
4328 * We matched an explicit entry. If we are able to
4329 * detect this boards settings with our heuristic,
4330 * then we no longer need this entry.
4331 */
4332 memcpy(&tmp, &pci_boards[pbn_default],
4333 sizeof(struct pciserial_board));
4334 rc = serial_pci_guess_board(dev, &tmp);
4335 if (rc == 0 && serial_pci_matches(board, &tmp))
4336 moan_device("Redundant entry in serial pci_table.",
4337 dev);
4338 }
4339
4340 priv = pciserial_init_ports(dev, board);
4341 if (IS_ERR(priv))
4342 return PTR_ERR(priv);
4343
4344 pci_set_drvdata(dev, priv);
4345 return 0;
4346 }
4347
pciserial_remove_one(struct pci_dev * dev)4348 static void pciserial_remove_one(struct pci_dev *dev)
4349 {
4350 struct serial_private *priv = pci_get_drvdata(dev);
4351
4352 pciserial_remove_ports(priv);
4353 }
4354
4355 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)4356 static int pciserial_suspend_one(struct device *dev)
4357 {
4358 struct serial_private *priv = dev_get_drvdata(dev);
4359
4360 if (priv)
4361 pciserial_suspend_ports(priv);
4362
4363 return 0;
4364 }
4365
pciserial_resume_one(struct device * dev)4366 static int pciserial_resume_one(struct device *dev)
4367 {
4368 struct pci_dev *pdev = to_pci_dev(dev);
4369 struct serial_private *priv = pci_get_drvdata(pdev);
4370 int err;
4371
4372 if (priv) {
4373 /*
4374 * The device may have been disabled. Re-enable it.
4375 */
4376 err = pci_enable_device(pdev);
4377 /* FIXME: We cannot simply error out here */
4378 if (err)
4379 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4380 pciserial_resume_ports(priv);
4381 }
4382 return 0;
4383 }
4384 #endif
4385
4386 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4387 pciserial_resume_one);
4388
4389 static const struct pci_device_id serial_pci_tbl[] = {
4390 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
4391 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4392 pbn_b0_4_921600 },
4393 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4394 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4395 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4396 pbn_b2_8_921600 },
4397 /* Advantech also use 0x3618 and 0xf618 */
4398 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4399 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4400 pbn_b0_4_921600 },
4401 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4402 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4403 pbn_b0_4_921600 },
4404 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4405 PCI_SUBVENDOR_ID_CONNECT_TECH,
4406 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4407 pbn_b1_8_1382400 },
4408 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4409 PCI_SUBVENDOR_ID_CONNECT_TECH,
4410 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4411 pbn_b1_4_1382400 },
4412 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4413 PCI_SUBVENDOR_ID_CONNECT_TECH,
4414 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4415 pbn_b1_2_1382400 },
4416 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4417 PCI_SUBVENDOR_ID_CONNECT_TECH,
4418 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4419 pbn_b1_8_1382400 },
4420 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4421 PCI_SUBVENDOR_ID_CONNECT_TECH,
4422 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4423 pbn_b1_4_1382400 },
4424 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4425 PCI_SUBVENDOR_ID_CONNECT_TECH,
4426 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4427 pbn_b1_2_1382400 },
4428 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4429 PCI_SUBVENDOR_ID_CONNECT_TECH,
4430 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4431 pbn_b1_8_921600 },
4432 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4433 PCI_SUBVENDOR_ID_CONNECT_TECH,
4434 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4435 pbn_b1_8_921600 },
4436 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4437 PCI_SUBVENDOR_ID_CONNECT_TECH,
4438 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4439 pbn_b1_4_921600 },
4440 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4441 PCI_SUBVENDOR_ID_CONNECT_TECH,
4442 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4443 pbn_b1_4_921600 },
4444 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4445 PCI_SUBVENDOR_ID_CONNECT_TECH,
4446 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4447 pbn_b1_2_921600 },
4448 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4449 PCI_SUBVENDOR_ID_CONNECT_TECH,
4450 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4451 pbn_b1_8_921600 },
4452 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4453 PCI_SUBVENDOR_ID_CONNECT_TECH,
4454 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4455 pbn_b1_8_921600 },
4456 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4457 PCI_SUBVENDOR_ID_CONNECT_TECH,
4458 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4459 pbn_b1_4_921600 },
4460 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4461 PCI_SUBVENDOR_ID_CONNECT_TECH,
4462 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4463 pbn_b1_2_1250000 },
4464 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4465 PCI_SUBVENDOR_ID_CONNECT_TECH,
4466 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4467 pbn_b0_2_1843200 },
4468 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4469 PCI_SUBVENDOR_ID_CONNECT_TECH,
4470 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4471 pbn_b0_4_1843200 },
4472 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4473 PCI_VENDOR_ID_AFAVLAB,
4474 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4475 pbn_b0_4_1152000 },
4476 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478 pbn_b2_bt_1_115200 },
4479 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481 pbn_b2_bt_2_115200 },
4482 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484 pbn_b2_bt_4_115200 },
4485 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487 pbn_b2_bt_2_115200 },
4488 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490 pbn_b2_bt_4_115200 },
4491 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493 pbn_b2_8_115200 },
4494 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496 pbn_b2_8_460800 },
4497 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499 pbn_b2_8_115200 },
4500
4501 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 pbn_b2_bt_2_115200 },
4504 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506 pbn_b2_bt_2_921600 },
4507 /*
4508 * VScom SPCOM800, from sl@s.pl
4509 */
4510 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512 pbn_b2_8_921600 },
4513 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4515 pbn_b2_4_921600 },
4516 /* Unknown card - subdevice 0x1584 */
4517 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4518 PCI_VENDOR_ID_PLX,
4519 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4520 pbn_b2_4_115200 },
4521 /* Unknown card - subdevice 0x1588 */
4522 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4523 PCI_VENDOR_ID_PLX,
4524 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4525 pbn_b2_8_115200 },
4526 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4527 PCI_SUBVENDOR_ID_KEYSPAN,
4528 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4529 pbn_panacom },
4530 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532 pbn_panacom4 },
4533 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535 pbn_panacom2 },
4536 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4537 PCI_VENDOR_ID_ESDGMBH,
4538 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4539 pbn_b2_4_115200 },
4540 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4541 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4542 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4543 pbn_b2_4_460800 },
4544 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4545 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4546 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4547 pbn_b2_8_460800 },
4548 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4549 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4550 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4551 pbn_b2_16_460800 },
4552 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4553 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4554 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4555 pbn_b2_16_460800 },
4556 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4557 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4558 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4559 pbn_b2_4_460800 },
4560 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4561 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4562 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4563 pbn_b2_8_460800 },
4564 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4565 PCI_SUBVENDOR_ID_EXSYS,
4566 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4567 pbn_b2_4_115200 },
4568 /*
4569 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4570 * (Exoray@isys.ca)
4571 */
4572 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4573 0x10b5, 0x106a, 0, 0,
4574 pbn_plx_romulus },
4575 /*
4576 * Quatech cards. These actually have configurable clocks but for
4577 * now we just use the default.
4578 *
4579 * 100 series are RS232, 200 series RS422,
4580 */
4581 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_b1_4_115200 },
4584 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_b1_2_115200 },
4587 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_b2_2_115200 },
4590 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_b1_2_115200 },
4593 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_b2_2_115200 },
4596 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_b1_4_115200 },
4599 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_b1_8_115200 },
4602 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 pbn_b1_8_115200 },
4605 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_b1_4_115200 },
4608 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_b1_2_115200 },
4611 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_b1_4_115200 },
4614 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 pbn_b1_2_115200 },
4617 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_b2_4_115200 },
4620 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_b2_2_115200 },
4623 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 pbn_b2_1_115200 },
4626 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 pbn_b2_4_115200 },
4629 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 pbn_b2_2_115200 },
4632 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 pbn_b2_1_115200 },
4635 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 pbn_b0_8_115200 },
4638
4639 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4640 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4641 0, 0,
4642 pbn_b0_4_921600 },
4643 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4644 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4645 0, 0,
4646 pbn_b0_4_1152000 },
4647 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 pbn_b0_bt_2_921600 },
4650
4651 /*
4652 * The below card is a little controversial since it is the
4653 * subject of a PCI vendor/device ID clash. (See
4654 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4655 * For now just used the hex ID 0x950a.
4656 */
4657 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4658 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4659 0, 0, pbn_b0_2_115200 },
4660 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4661 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4662 0, 0, pbn_b0_2_115200 },
4663 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665 pbn_b0_2_1130000 },
4666 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4667 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4668 pbn_b0_1_921600 },
4669 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4671 pbn_b0_4_115200 },
4672 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674 pbn_b0_bt_2_921600 },
4675 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4677 pbn_b2_8_1152000 },
4678
4679 /*
4680 * Oxford Semiconductor Inc. Tornado PCI express device range.
4681 */
4682 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 pbn_b0_1_15625000 },
4685 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_b0_1_15625000 },
4688 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_oxsemi_1_15625000 },
4691 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693 pbn_oxsemi_1_15625000 },
4694 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 pbn_b0_1_15625000 },
4697 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699 pbn_b0_1_15625000 },
4700 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702 pbn_oxsemi_1_15625000 },
4703 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705 pbn_oxsemi_1_15625000 },
4706 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708 pbn_b0_1_15625000 },
4709 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 pbn_b0_1_15625000 },
4712 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 pbn_b0_1_15625000 },
4715 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717 pbn_b0_1_15625000 },
4718 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 pbn_oxsemi_2_15625000 },
4721 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723 pbn_oxsemi_2_15625000 },
4724 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726 pbn_oxsemi_4_15625000 },
4727 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729 pbn_oxsemi_4_15625000 },
4730 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732 pbn_oxsemi_8_15625000 },
4733 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735 pbn_oxsemi_8_15625000 },
4736 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738 pbn_oxsemi_1_15625000 },
4739 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741 pbn_oxsemi_1_15625000 },
4742 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744 pbn_oxsemi_1_15625000 },
4745 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747 pbn_oxsemi_1_15625000 },
4748 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750 pbn_oxsemi_1_15625000 },
4751 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753 pbn_oxsemi_1_15625000 },
4754 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756 pbn_oxsemi_1_15625000 },
4757 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759 pbn_oxsemi_1_15625000 },
4760 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762 pbn_oxsemi_1_15625000 },
4763 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765 pbn_oxsemi_1_15625000 },
4766 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768 pbn_oxsemi_1_15625000 },
4769 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771 pbn_oxsemi_1_15625000 },
4772 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774 pbn_oxsemi_1_15625000 },
4775 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777 pbn_oxsemi_1_15625000 },
4778 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780 pbn_oxsemi_1_15625000 },
4781 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783 pbn_oxsemi_1_15625000 },
4784 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786 pbn_oxsemi_1_15625000 },
4787 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789 pbn_oxsemi_1_15625000 },
4790 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792 pbn_oxsemi_1_15625000 },
4793 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795 pbn_oxsemi_1_15625000 },
4796 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798 pbn_oxsemi_1_15625000 },
4799 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801 pbn_oxsemi_1_15625000 },
4802 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804 pbn_oxsemi_1_15625000 },
4805 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4807 pbn_oxsemi_1_15625000 },
4808 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810 pbn_oxsemi_1_15625000 },
4811 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4813 pbn_oxsemi_1_15625000 },
4814 /*
4815 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4816 */
4817 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4818 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4819 pbn_oxsemi_1_15625000 },
4820 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4821 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4822 pbn_oxsemi_2_15625000 },
4823 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4824 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4825 pbn_oxsemi_4_15625000 },
4826 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4827 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4828 pbn_oxsemi_8_15625000 },
4829
4830 /*
4831 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4832 */
4833 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4834 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4835 pbn_oxsemi_2_15625000 },
4836 /*
4837 * EndRun Technologies. PCI express device range.
4838 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4839 */
4840 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4842 pbn_oxsemi_2_15625000 },
4843
4844 /*
4845 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4846 * from skokodyn@yahoo.com
4847 */
4848 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4849 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4850 pbn_sbsxrsio },
4851 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4852 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4853 pbn_sbsxrsio },
4854 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4855 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4856 pbn_sbsxrsio },
4857 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4858 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4859 pbn_sbsxrsio },
4860
4861 /*
4862 * Digitan DS560-558, from jimd@esoft.com
4863 */
4864 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4865 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4866 pbn_b1_1_115200 },
4867
4868 /*
4869 * Titan Electronic cards
4870 * The 400L and 800L have a custom setup quirk.
4871 */
4872 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4874 pbn_b0_1_921600 },
4875 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4877 pbn_b0_2_921600 },
4878 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4880 pbn_b0_4_921600 },
4881 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4883 pbn_b0_4_921600 },
4884 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4886 pbn_b1_1_921600 },
4887 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4889 pbn_b1_bt_2_921600 },
4890 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4892 pbn_b0_bt_4_921600 },
4893 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4895 pbn_b0_bt_8_921600 },
4896 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898 pbn_b4_bt_2_921600 },
4899 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901 pbn_b4_bt_4_921600 },
4902 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904 pbn_b4_bt_8_921600 },
4905 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4907 pbn_b0_4_921600 },
4908 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4910 pbn_b0_4_921600 },
4911 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4913 pbn_b0_4_921600 },
4914 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4916 pbn_titan_1_4000000 },
4917 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4919 pbn_titan_2_4000000 },
4920 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4922 pbn_titan_4_4000000 },
4923 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4925 pbn_titan_8_4000000 },
4926 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4928 pbn_titan_2_4000000 },
4929 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4931 pbn_titan_2_4000000 },
4932 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4934 pbn_b0_bt_2_921600 },
4935 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4937 pbn_b0_4_921600 },
4938 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4940 pbn_b0_4_921600 },
4941 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4943 pbn_b0_4_921600 },
4944 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4946 pbn_b0_4_921600 },
4947
4948 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950 pbn_b2_1_460800 },
4951 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953 pbn_b2_1_460800 },
4954 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956 pbn_b2_1_460800 },
4957 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4959 pbn_b2_bt_2_921600 },
4960 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4962 pbn_b2_bt_2_921600 },
4963 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4965 pbn_b2_bt_2_921600 },
4966 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4968 pbn_b2_bt_4_921600 },
4969 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971 pbn_b2_bt_4_921600 },
4972 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4974 pbn_b2_bt_4_921600 },
4975 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4977 pbn_b0_1_921600 },
4978 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4980 pbn_b0_1_921600 },
4981 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4983 pbn_b0_1_921600 },
4984 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4986 pbn_b0_bt_2_921600 },
4987 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4989 pbn_b0_bt_2_921600 },
4990 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4992 pbn_b0_bt_2_921600 },
4993 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4995 pbn_b0_bt_4_921600 },
4996 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4998 pbn_b0_bt_4_921600 },
4999 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
5000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5001 pbn_b0_bt_4_921600 },
5002 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
5003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5004 pbn_b0_bt_8_921600 },
5005 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
5006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5007 pbn_b0_bt_8_921600 },
5008 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
5009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5010 pbn_b0_bt_8_921600 },
5011
5012 /*
5013 * Computone devices submitted by Doug McNash dmcnash@computone.com
5014 */
5015 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5016 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
5017 0, 0, pbn_computone_4 },
5018 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5019 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
5020 0, 0, pbn_computone_8 },
5021 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5022 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
5023 0, 0, pbn_computone_6 },
5024
5025 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
5026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5027 pbn_oxsemi },
5028 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
5029 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
5030 pbn_b0_bt_1_921600 },
5031
5032 /*
5033 * Sunix PCI serial boards
5034 */
5035 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5036 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
5037 pbn_sunix_pci_1s },
5038 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5039 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
5040 pbn_sunix_pci_2s },
5041 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5042 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
5043 pbn_sunix_pci_4s },
5044 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5045 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
5046 pbn_sunix_pci_4s },
5047 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5048 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
5049 pbn_sunix_pci_8s },
5050 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5051 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
5052 pbn_sunix_pci_8s },
5053 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5054 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
5055 pbn_sunix_pci_16s },
5056
5057 /*
5058 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
5059 */
5060 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
5061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5062 pbn_b0_bt_8_115200 },
5063 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5065 pbn_b0_bt_8_115200 },
5066
5067 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5068 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5069 pbn_b0_bt_2_115200 },
5070 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5072 pbn_b0_bt_2_115200 },
5073 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5074 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5075 pbn_b0_bt_2_115200 },
5076 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5078 pbn_b0_bt_4_460800 },
5079 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5080 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5081 pbn_b0_bt_4_460800 },
5082 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5084 pbn_b0_bt_2_460800 },
5085 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5087 pbn_b0_bt_2_460800 },
5088 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5090 pbn_b0_bt_2_460800 },
5091 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5093 pbn_b0_bt_1_115200 },
5094 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5096 pbn_b0_bt_1_460800 },
5097
5098 /*
5099 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5100 * Cards are identified by their subsystem vendor IDs, which
5101 * (in hex) match the model number.
5102 *
5103 * Note that JC140x are RS422/485 cards which require ox950
5104 * ACR = 0x10, and as such are not currently fully supported.
5105 */
5106 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5107 0x1204, 0x0004, 0, 0,
5108 pbn_b0_4_921600 },
5109 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5110 0x1208, 0x0004, 0, 0,
5111 pbn_b0_4_921600 },
5112 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5113 0x1402, 0x0002, 0, 0,
5114 pbn_b0_2_921600 }, */
5115 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5116 0x1404, 0x0004, 0, 0,
5117 pbn_b0_4_921600 }, */
5118 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5119 0x1208, 0x0004, 0, 0,
5120 pbn_b0_4_921600 },
5121
5122 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5123 0x1204, 0x0004, 0, 0,
5124 pbn_b0_4_921600 },
5125 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5126 0x1208, 0x0004, 0, 0,
5127 pbn_b0_4_921600 },
5128 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5129 0x1208, 0x0004, 0, 0,
5130 pbn_b0_4_921600 },
5131 /*
5132 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5133 */
5134 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5136 pbn_b1_1_1382400 },
5137
5138 /*
5139 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5140 */
5141 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5143 pbn_b1_1_1382400 },
5144
5145 /*
5146 * RAStel 2 port modem, gerg@moreton.com.au
5147 */
5148 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5150 pbn_b2_bt_2_115200 },
5151
5152 /*
5153 * EKF addition for i960 Boards form EKF with serial port
5154 */
5155 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5156 0xE4BF, PCI_ANY_ID, 0, 0,
5157 pbn_intel_i960 },
5158
5159 /*
5160 * Xircom Cardbus/Ethernet combos
5161 */
5162 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5164 pbn_b0_1_115200 },
5165 /*
5166 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5167 */
5168 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5170 pbn_b0_1_115200 },
5171
5172 /*
5173 * Untested PCI modems, sent in from various folks...
5174 */
5175
5176 /*
5177 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5178 */
5179 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5180 0x1048, 0x1500, 0, 0,
5181 pbn_b1_1_115200 },
5182
5183 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5184 0xFF00, 0, 0, 0,
5185 pbn_sgi_ioc3 },
5186
5187 /*
5188 * HP Diva card
5189 */
5190 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5191 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5192 pbn_b1_1_115200 },
5193 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5195 pbn_b0_5_115200 },
5196 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5198 pbn_b2_1_115200 },
5199 /* HPE PCI serial device */
5200 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5201 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5202 pbn_b1_1_115200 },
5203
5204 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5206 pbn_b3_2_115200 },
5207 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5209 pbn_b3_4_115200 },
5210 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5212 pbn_b3_8_115200 },
5213 /*
5214 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5215 */
5216 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5218 pbn_b0_1_115200 },
5219 /*
5220 * ITE
5221 */
5222 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5223 PCI_ANY_ID, PCI_ANY_ID,
5224 0, 0,
5225 pbn_b1_bt_1_115200 },
5226
5227 /*
5228 * IntaShield IS-100
5229 */
5230 { PCI_VENDOR_ID_INTASHIELD, 0x0D60,
5231 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5232 pbn_b2_1_115200 },
5233 /*
5234 * IntaShield IS-200
5235 */
5236 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */
5238 pbn_b2_2_115200 },
5239 /*
5240 * IntaShield IS-400
5241 */
5242 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5244 pbn_b2_4_115200 },
5245 /*
5246 * IntaShield IX-100
5247 */
5248 { PCI_VENDOR_ID_INTASHIELD, 0x4027,
5249 PCI_ANY_ID, PCI_ANY_ID,
5250 0, 0,
5251 pbn_oxsemi_1_15625000 },
5252 /*
5253 * IntaShield IX-200
5254 */
5255 { PCI_VENDOR_ID_INTASHIELD, 0x4028,
5256 PCI_ANY_ID, PCI_ANY_ID,
5257 0, 0,
5258 pbn_oxsemi_2_15625000 },
5259 /*
5260 * IntaShield IX-400
5261 */
5262 { PCI_VENDOR_ID_INTASHIELD, 0x4029,
5263 PCI_ANY_ID, PCI_ANY_ID,
5264 0, 0,
5265 pbn_oxsemi_4_15625000 },
5266 /* Brainboxes Devices */
5267 /*
5268 * Brainboxes UC-101
5269 */
5270 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5271 PCI_ANY_ID, PCI_ANY_ID,
5272 0, 0,
5273 pbn_b2_2_115200 },
5274 { PCI_VENDOR_ID_INTASHIELD, 0x0BA2,
5275 PCI_ANY_ID, PCI_ANY_ID,
5276 0, 0,
5277 pbn_b2_2_115200 },
5278 { PCI_VENDOR_ID_INTASHIELD, 0x0BA3,
5279 PCI_ANY_ID, PCI_ANY_ID,
5280 0, 0,
5281 pbn_b2_2_115200 },
5282 /*
5283 * Brainboxes UC-235/246
5284 */
5285 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5286 PCI_ANY_ID, PCI_ANY_ID,
5287 0, 0,
5288 pbn_b2_1_115200 },
5289 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
5290 PCI_ANY_ID, PCI_ANY_ID,
5291 0, 0,
5292 pbn_b2_1_115200 },
5293 /*
5294 * Brainboxes UC-253/UC-734
5295 */
5296 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
5297 PCI_ANY_ID, PCI_ANY_ID,
5298 0, 0,
5299 pbn_b2_2_115200 },
5300 /*
5301 * Brainboxes UC-260/271/701/756
5302 */
5303 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5304 PCI_ANY_ID, PCI_ANY_ID,
5305 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5306 pbn_b2_4_115200 },
5307 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5308 PCI_ANY_ID, PCI_ANY_ID,
5309 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5310 pbn_b2_4_115200 },
5311 /*
5312 * Brainboxes UC-268
5313 */
5314 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5315 PCI_ANY_ID, PCI_ANY_ID,
5316 0, 0,
5317 pbn_b2_4_115200 },
5318 /*
5319 * Brainboxes UC-275/279
5320 */
5321 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5322 PCI_ANY_ID, PCI_ANY_ID,
5323 0, 0,
5324 pbn_b2_8_115200 },
5325 /*
5326 * Brainboxes UC-302
5327 */
5328 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5329 PCI_ANY_ID, PCI_ANY_ID,
5330 0, 0,
5331 pbn_b2_2_115200 },
5332 { PCI_VENDOR_ID_INTASHIELD, 0x08E2,
5333 PCI_ANY_ID, PCI_ANY_ID,
5334 0, 0,
5335 pbn_b2_2_115200 },
5336 { PCI_VENDOR_ID_INTASHIELD, 0x08E3,
5337 PCI_ANY_ID, PCI_ANY_ID,
5338 0, 0,
5339 pbn_b2_2_115200 },
5340 /*
5341 * Brainboxes UC-310
5342 */
5343 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5344 PCI_ANY_ID, PCI_ANY_ID,
5345 0, 0,
5346 pbn_b2_2_115200 },
5347 /*
5348 * Brainboxes UC-313
5349 */
5350 { PCI_VENDOR_ID_INTASHIELD, 0x08A1,
5351 PCI_ANY_ID, PCI_ANY_ID,
5352 0, 0,
5353 pbn_b2_2_115200 },
5354 { PCI_VENDOR_ID_INTASHIELD, 0x08A2,
5355 PCI_ANY_ID, PCI_ANY_ID,
5356 0, 0,
5357 pbn_b2_2_115200 },
5358 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5359 PCI_ANY_ID, PCI_ANY_ID,
5360 0, 0,
5361 pbn_b2_2_115200 },
5362 /*
5363 * Brainboxes UC-320/324
5364 */
5365 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5366 PCI_ANY_ID, PCI_ANY_ID,
5367 0, 0,
5368 pbn_b2_1_115200 },
5369 /*
5370 * Brainboxes UC-346
5371 */
5372 { PCI_VENDOR_ID_INTASHIELD, 0x0B01,
5373 PCI_ANY_ID, PCI_ANY_ID,
5374 0, 0,
5375 pbn_b2_4_115200 },
5376 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5377 PCI_ANY_ID, PCI_ANY_ID,
5378 0, 0,
5379 pbn_b2_4_115200 },
5380 /*
5381 * Brainboxes UC-357
5382 */
5383 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5384 PCI_ANY_ID, PCI_ANY_ID,
5385 0, 0,
5386 pbn_b2_2_115200 },
5387 { PCI_VENDOR_ID_INTASHIELD, 0x0A82,
5388 PCI_ANY_ID, PCI_ANY_ID,
5389 0, 0,
5390 pbn_b2_2_115200 },
5391 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5392 PCI_ANY_ID, PCI_ANY_ID,
5393 0, 0,
5394 pbn_b2_2_115200 },
5395 /*
5396 * Brainboxes UC-368
5397 */
5398 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5399 PCI_ANY_ID, PCI_ANY_ID,
5400 0, 0,
5401 pbn_b2_4_115200 },
5402 { PCI_VENDOR_ID_INTASHIELD, 0x0C42,
5403 PCI_ANY_ID, PCI_ANY_ID,
5404 0, 0,
5405 pbn_b2_4_115200 },
5406 { PCI_VENDOR_ID_INTASHIELD, 0x0C43,
5407 PCI_ANY_ID, PCI_ANY_ID,
5408 0, 0,
5409 pbn_b2_4_115200 },
5410 /*
5411 * Brainboxes UC-420
5412 */
5413 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5414 PCI_ANY_ID, PCI_ANY_ID,
5415 0, 0,
5416 pbn_b2_4_115200 },
5417 /*
5418 * Brainboxes UC-607
5419 */
5420 { PCI_VENDOR_ID_INTASHIELD, 0x09A1,
5421 PCI_ANY_ID, PCI_ANY_ID,
5422 0, 0,
5423 pbn_b2_2_115200 },
5424 { PCI_VENDOR_ID_INTASHIELD, 0x09A2,
5425 PCI_ANY_ID, PCI_ANY_ID,
5426 0, 0,
5427 pbn_b2_2_115200 },
5428 { PCI_VENDOR_ID_INTASHIELD, 0x09A3,
5429 PCI_ANY_ID, PCI_ANY_ID,
5430 0, 0,
5431 pbn_b2_2_115200 },
5432 /*
5433 * Brainboxes UC-836
5434 */
5435 { PCI_VENDOR_ID_INTASHIELD, 0x0D41,
5436 PCI_ANY_ID, PCI_ANY_ID,
5437 0, 0,
5438 pbn_b2_4_115200 },
5439 /*
5440 * Brainboxes UP-189
5441 */
5442 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
5443 PCI_ANY_ID, PCI_ANY_ID,
5444 0, 0,
5445 pbn_b2_2_115200 },
5446 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
5447 PCI_ANY_ID, PCI_ANY_ID,
5448 0, 0,
5449 pbn_b2_2_115200 },
5450 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
5451 PCI_ANY_ID, PCI_ANY_ID,
5452 0, 0,
5453 pbn_b2_2_115200 },
5454 /*
5455 * Brainboxes UP-200
5456 */
5457 { PCI_VENDOR_ID_INTASHIELD, 0x0B21,
5458 PCI_ANY_ID, PCI_ANY_ID,
5459 0, 0,
5460 pbn_b2_2_115200 },
5461 { PCI_VENDOR_ID_INTASHIELD, 0x0B22,
5462 PCI_ANY_ID, PCI_ANY_ID,
5463 0, 0,
5464 pbn_b2_2_115200 },
5465 { PCI_VENDOR_ID_INTASHIELD, 0x0B23,
5466 PCI_ANY_ID, PCI_ANY_ID,
5467 0, 0,
5468 pbn_b2_2_115200 },
5469 /*
5470 * Brainboxes UP-869
5471 */
5472 { PCI_VENDOR_ID_INTASHIELD, 0x0C01,
5473 PCI_ANY_ID, PCI_ANY_ID,
5474 0, 0,
5475 pbn_b2_2_115200 },
5476 { PCI_VENDOR_ID_INTASHIELD, 0x0C02,
5477 PCI_ANY_ID, PCI_ANY_ID,
5478 0, 0,
5479 pbn_b2_2_115200 },
5480 { PCI_VENDOR_ID_INTASHIELD, 0x0C03,
5481 PCI_ANY_ID, PCI_ANY_ID,
5482 0, 0,
5483 pbn_b2_2_115200 },
5484 /*
5485 * Brainboxes UP-880
5486 */
5487 { PCI_VENDOR_ID_INTASHIELD, 0x0C21,
5488 PCI_ANY_ID, PCI_ANY_ID,
5489 0, 0,
5490 pbn_b2_2_115200 },
5491 { PCI_VENDOR_ID_INTASHIELD, 0x0C22,
5492 PCI_ANY_ID, PCI_ANY_ID,
5493 0, 0,
5494 pbn_b2_2_115200 },
5495 { PCI_VENDOR_ID_INTASHIELD, 0x0C23,
5496 PCI_ANY_ID, PCI_ANY_ID,
5497 0, 0,
5498 pbn_b2_2_115200 },
5499 /*
5500 * Brainboxes PX-101
5501 */
5502 { PCI_VENDOR_ID_INTASHIELD, 0x4005,
5503 PCI_ANY_ID, PCI_ANY_ID,
5504 0, 0,
5505 pbn_b0_2_115200 },
5506 { PCI_VENDOR_ID_INTASHIELD, 0x4019,
5507 PCI_ANY_ID, PCI_ANY_ID,
5508 0, 0,
5509 pbn_oxsemi_2_15625000 },
5510 /*
5511 * Brainboxes PX-235/246
5512 */
5513 { PCI_VENDOR_ID_INTASHIELD, 0x4004,
5514 PCI_ANY_ID, PCI_ANY_ID,
5515 0, 0,
5516 pbn_b0_1_115200 },
5517 { PCI_VENDOR_ID_INTASHIELD, 0x4016,
5518 PCI_ANY_ID, PCI_ANY_ID,
5519 0, 0,
5520 pbn_oxsemi_1_15625000 },
5521 /*
5522 * Brainboxes PX-203/PX-257
5523 */
5524 { PCI_VENDOR_ID_INTASHIELD, 0x4006,
5525 PCI_ANY_ID, PCI_ANY_ID,
5526 0, 0,
5527 pbn_b0_2_115200 },
5528 { PCI_VENDOR_ID_INTASHIELD, 0x4015,
5529 PCI_ANY_ID, PCI_ANY_ID,
5530 0, 0,
5531 pbn_oxsemi_2_15625000 },
5532 /*
5533 * Brainboxes PX-260/PX-701
5534 */
5535 { PCI_VENDOR_ID_INTASHIELD, 0x400A,
5536 PCI_ANY_ID, PCI_ANY_ID,
5537 0, 0,
5538 pbn_oxsemi_4_15625000 },
5539 /*
5540 * Brainboxes PX-275/279
5541 */
5542 { PCI_VENDOR_ID_INTASHIELD, 0x0E41,
5543 PCI_ANY_ID, PCI_ANY_ID,
5544 0, 0,
5545 pbn_b2_8_115200 },
5546 /*
5547 * Brainboxes PX-310
5548 */
5549 { PCI_VENDOR_ID_INTASHIELD, 0x400E,
5550 PCI_ANY_ID, PCI_ANY_ID,
5551 0, 0,
5552 pbn_oxsemi_2_15625000 },
5553 /*
5554 * Brainboxes PX-313
5555 */
5556 { PCI_VENDOR_ID_INTASHIELD, 0x400C,
5557 PCI_ANY_ID, PCI_ANY_ID,
5558 0, 0,
5559 pbn_oxsemi_2_15625000 },
5560 /*
5561 * Brainboxes PX-320/324/PX-376/PX-387
5562 */
5563 { PCI_VENDOR_ID_INTASHIELD, 0x400B,
5564 PCI_ANY_ID, PCI_ANY_ID,
5565 0, 0,
5566 pbn_oxsemi_1_15625000 },
5567 /*
5568 * Brainboxes PX-335/346
5569 */
5570 { PCI_VENDOR_ID_INTASHIELD, 0x400F,
5571 PCI_ANY_ID, PCI_ANY_ID,
5572 0, 0,
5573 pbn_oxsemi_4_15625000 },
5574 /*
5575 * Brainboxes PX-368
5576 */
5577 { PCI_VENDOR_ID_INTASHIELD, 0x4010,
5578 PCI_ANY_ID, PCI_ANY_ID,
5579 0, 0,
5580 pbn_oxsemi_4_15625000 },
5581 /*
5582 * Brainboxes PX-420
5583 */
5584 { PCI_VENDOR_ID_INTASHIELD, 0x4000,
5585 PCI_ANY_ID, PCI_ANY_ID,
5586 0, 0,
5587 pbn_b0_4_115200 },
5588 { PCI_VENDOR_ID_INTASHIELD, 0x4011,
5589 PCI_ANY_ID, PCI_ANY_ID,
5590 0, 0,
5591 pbn_oxsemi_4_15625000 },
5592 /*
5593 * Brainboxes PX-475
5594 */
5595 { PCI_VENDOR_ID_INTASHIELD, 0x401D,
5596 PCI_ANY_ID, PCI_ANY_ID,
5597 0, 0,
5598 pbn_oxsemi_1_15625000 },
5599 /*
5600 * Brainboxes PX-803/PX-857
5601 */
5602 { PCI_VENDOR_ID_INTASHIELD, 0x4009,
5603 PCI_ANY_ID, PCI_ANY_ID,
5604 0, 0,
5605 pbn_b0_2_115200 },
5606 { PCI_VENDOR_ID_INTASHIELD, 0x4018,
5607 PCI_ANY_ID, PCI_ANY_ID,
5608 0, 0,
5609 pbn_oxsemi_2_15625000 },
5610 { PCI_VENDOR_ID_INTASHIELD, 0x401E,
5611 PCI_ANY_ID, PCI_ANY_ID,
5612 0, 0,
5613 pbn_oxsemi_2_15625000 },
5614 /*
5615 * Brainboxes PX-820
5616 */
5617 { PCI_VENDOR_ID_INTASHIELD, 0x4002,
5618 PCI_ANY_ID, PCI_ANY_ID,
5619 0, 0,
5620 pbn_b0_4_115200 },
5621 { PCI_VENDOR_ID_INTASHIELD, 0x4013,
5622 PCI_ANY_ID, PCI_ANY_ID,
5623 0, 0,
5624 pbn_oxsemi_4_15625000 },
5625 /*
5626 * Brainboxes PX-835/PX-846
5627 */
5628 { PCI_VENDOR_ID_INTASHIELD, 0x4008,
5629 PCI_ANY_ID, PCI_ANY_ID,
5630 0, 0,
5631 pbn_b0_1_115200 },
5632 { PCI_VENDOR_ID_INTASHIELD, 0x4017,
5633 PCI_ANY_ID, PCI_ANY_ID,
5634 0, 0,
5635 pbn_oxsemi_1_15625000 },
5636 /*
5637 * Brainboxes XC-235
5638 */
5639 { PCI_VENDOR_ID_INTASHIELD, 0x4026,
5640 PCI_ANY_ID, PCI_ANY_ID,
5641 0, 0,
5642 pbn_oxsemi_1_15625000 },
5643 /*
5644 * Brainboxes XC-475
5645 */
5646 { PCI_VENDOR_ID_INTASHIELD, 0x4021,
5647 PCI_ANY_ID, PCI_ANY_ID,
5648 0, 0,
5649 pbn_oxsemi_1_15625000 },
5650
5651 /*
5652 * Perle PCI-RAS cards
5653 */
5654 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5655 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5656 0, 0, pbn_b2_4_921600 },
5657 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5658 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5659 0, 0, pbn_b2_8_921600 },
5660
5661 /*
5662 * Mainpine series cards: Fairly standard layout but fools
5663 * parts of the autodetect in some cases and uses otherwise
5664 * unmatched communications subclasses in the PCI Express case
5665 */
5666
5667 { /* RockForceDUO */
5668 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5669 PCI_VENDOR_ID_MAINPINE, 0x0200,
5670 0, 0, pbn_b0_2_115200 },
5671 { /* RockForceQUATRO */
5672 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5673 PCI_VENDOR_ID_MAINPINE, 0x0300,
5674 0, 0, pbn_b0_4_115200 },
5675 { /* RockForceDUO+ */
5676 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5677 PCI_VENDOR_ID_MAINPINE, 0x0400,
5678 0, 0, pbn_b0_2_115200 },
5679 { /* RockForceQUATRO+ */
5680 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5681 PCI_VENDOR_ID_MAINPINE, 0x0500,
5682 0, 0, pbn_b0_4_115200 },
5683 { /* RockForce+ */
5684 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5685 PCI_VENDOR_ID_MAINPINE, 0x0600,
5686 0, 0, pbn_b0_2_115200 },
5687 { /* RockForce+ */
5688 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5689 PCI_VENDOR_ID_MAINPINE, 0x0700,
5690 0, 0, pbn_b0_4_115200 },
5691 { /* RockForceOCTO+ */
5692 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5693 PCI_VENDOR_ID_MAINPINE, 0x0800,
5694 0, 0, pbn_b0_8_115200 },
5695 { /* RockForceDUO+ */
5696 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5697 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5698 0, 0, pbn_b0_2_115200 },
5699 { /* RockForceQUARTRO+ */
5700 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5701 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5702 0, 0, pbn_b0_4_115200 },
5703 { /* RockForceOCTO+ */
5704 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5705 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5706 0, 0, pbn_b0_8_115200 },
5707 { /* RockForceD1 */
5708 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5709 PCI_VENDOR_ID_MAINPINE, 0x2000,
5710 0, 0, pbn_b0_1_115200 },
5711 { /* RockForceF1 */
5712 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5713 PCI_VENDOR_ID_MAINPINE, 0x2100,
5714 0, 0, pbn_b0_1_115200 },
5715 { /* RockForceD2 */
5716 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5717 PCI_VENDOR_ID_MAINPINE, 0x2200,
5718 0, 0, pbn_b0_2_115200 },
5719 { /* RockForceF2 */
5720 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5721 PCI_VENDOR_ID_MAINPINE, 0x2300,
5722 0, 0, pbn_b0_2_115200 },
5723 { /* RockForceD4 */
5724 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5725 PCI_VENDOR_ID_MAINPINE, 0x2400,
5726 0, 0, pbn_b0_4_115200 },
5727 { /* RockForceF4 */
5728 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5729 PCI_VENDOR_ID_MAINPINE, 0x2500,
5730 0, 0, pbn_b0_4_115200 },
5731 { /* RockForceD8 */
5732 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5733 PCI_VENDOR_ID_MAINPINE, 0x2600,
5734 0, 0, pbn_b0_8_115200 },
5735 { /* RockForceF8 */
5736 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5737 PCI_VENDOR_ID_MAINPINE, 0x2700,
5738 0, 0, pbn_b0_8_115200 },
5739 { /* IQ Express D1 */
5740 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5741 PCI_VENDOR_ID_MAINPINE, 0x3000,
5742 0, 0, pbn_b0_1_115200 },
5743 { /* IQ Express F1 */
5744 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5745 PCI_VENDOR_ID_MAINPINE, 0x3100,
5746 0, 0, pbn_b0_1_115200 },
5747 { /* IQ Express D2 */
5748 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5749 PCI_VENDOR_ID_MAINPINE, 0x3200,
5750 0, 0, pbn_b0_2_115200 },
5751 { /* IQ Express F2 */
5752 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5753 PCI_VENDOR_ID_MAINPINE, 0x3300,
5754 0, 0, pbn_b0_2_115200 },
5755 { /* IQ Express D4 */
5756 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5757 PCI_VENDOR_ID_MAINPINE, 0x3400,
5758 0, 0, pbn_b0_4_115200 },
5759 { /* IQ Express F4 */
5760 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5761 PCI_VENDOR_ID_MAINPINE, 0x3500,
5762 0, 0, pbn_b0_4_115200 },
5763 { /* IQ Express D8 */
5764 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5765 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5766 0, 0, pbn_b0_8_115200 },
5767 { /* IQ Express F8 */
5768 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5769 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5770 0, 0, pbn_b0_8_115200 },
5771
5772
5773 /*
5774 * PA Semi PA6T-1682M on-chip UART
5775 */
5776 { PCI_VENDOR_ID_PASEMI, 0xa004,
5777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5778 pbn_pasemi_1682M },
5779
5780 /*
5781 * National Instruments
5782 */
5783 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5785 pbn_b1_16_115200 },
5786 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5788 pbn_b1_8_115200 },
5789 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5791 pbn_b1_bt_4_115200 },
5792 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5794 pbn_b1_bt_2_115200 },
5795 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5797 pbn_b1_bt_4_115200 },
5798 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5800 pbn_b1_bt_2_115200 },
5801 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5803 pbn_b1_16_115200 },
5804 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5806 pbn_b1_8_115200 },
5807 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5809 pbn_b1_bt_4_115200 },
5810 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5812 pbn_b1_bt_2_115200 },
5813 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5815 pbn_b1_bt_4_115200 },
5816 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5818 pbn_b1_bt_2_115200 },
5819 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5821 pbn_ni8430_2 },
5822 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5824 pbn_ni8430_2 },
5825 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5826 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5827 pbn_ni8430_4 },
5828 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5829 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5830 pbn_ni8430_4 },
5831 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5833 pbn_ni8430_8 },
5834 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5836 pbn_ni8430_8 },
5837 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5839 pbn_ni8430_16 },
5840 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5842 pbn_ni8430_16 },
5843 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5845 pbn_ni8430_2 },
5846 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5848 pbn_ni8430_2 },
5849 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5851 pbn_ni8430_4 },
5852 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5854 pbn_ni8430_4 },
5855
5856 /*
5857 * MOXA
5858 */
5859 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 },
5860 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 },
5861 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 },
5862 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 },
5863 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 },
5864 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 },
5865 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 },
5866 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 },
5867 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 },
5868 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 },
5869 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 },
5870 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 },
5871 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 },
5872 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 },
5873 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 },
5874 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 },
5875 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 },
5876 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 },
5877
5878 /*
5879 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5880 */
5881 { PCI_VENDOR_ID_ADDIDATA,
5882 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5883 PCI_ANY_ID,
5884 PCI_ANY_ID,
5885 0,
5886 0,
5887 pbn_b0_4_115200 },
5888
5889 { PCI_VENDOR_ID_ADDIDATA,
5890 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5891 PCI_ANY_ID,
5892 PCI_ANY_ID,
5893 0,
5894 0,
5895 pbn_b0_2_115200 },
5896
5897 { PCI_VENDOR_ID_ADDIDATA,
5898 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5899 PCI_ANY_ID,
5900 PCI_ANY_ID,
5901 0,
5902 0,
5903 pbn_b0_1_115200 },
5904
5905 { PCI_VENDOR_ID_AMCC,
5906 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5907 PCI_ANY_ID,
5908 PCI_ANY_ID,
5909 0,
5910 0,
5911 pbn_b1_8_115200 },
5912
5913 { PCI_VENDOR_ID_ADDIDATA,
5914 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5915 PCI_ANY_ID,
5916 PCI_ANY_ID,
5917 0,
5918 0,
5919 pbn_b0_4_115200 },
5920
5921 { PCI_VENDOR_ID_ADDIDATA,
5922 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5923 PCI_ANY_ID,
5924 PCI_ANY_ID,
5925 0,
5926 0,
5927 pbn_b0_2_115200 },
5928
5929 { PCI_VENDOR_ID_ADDIDATA,
5930 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5931 PCI_ANY_ID,
5932 PCI_ANY_ID,
5933 0,
5934 0,
5935 pbn_b0_1_115200 },
5936
5937 { PCI_VENDOR_ID_ADDIDATA,
5938 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5939 PCI_ANY_ID,
5940 PCI_ANY_ID,
5941 0,
5942 0,
5943 pbn_b0_4_115200 },
5944
5945 { PCI_VENDOR_ID_ADDIDATA,
5946 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5947 PCI_ANY_ID,
5948 PCI_ANY_ID,
5949 0,
5950 0,
5951 pbn_b0_2_115200 },
5952
5953 { PCI_VENDOR_ID_ADDIDATA,
5954 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5955 PCI_ANY_ID,
5956 PCI_ANY_ID,
5957 0,
5958 0,
5959 pbn_b0_1_115200 },
5960
5961 { PCI_VENDOR_ID_ADDIDATA,
5962 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5963 PCI_ANY_ID,
5964 PCI_ANY_ID,
5965 0,
5966 0,
5967 pbn_b0_8_115200 },
5968
5969 { PCI_VENDOR_ID_ADDIDATA,
5970 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5971 PCI_ANY_ID,
5972 PCI_ANY_ID,
5973 0,
5974 0,
5975 pbn_ADDIDATA_PCIe_4_3906250 },
5976
5977 { PCI_VENDOR_ID_ADDIDATA,
5978 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5979 PCI_ANY_ID,
5980 PCI_ANY_ID,
5981 0,
5982 0,
5983 pbn_ADDIDATA_PCIe_2_3906250 },
5984
5985 { PCI_VENDOR_ID_ADDIDATA,
5986 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5987 PCI_ANY_ID,
5988 PCI_ANY_ID,
5989 0,
5990 0,
5991 pbn_ADDIDATA_PCIe_1_3906250 },
5992
5993 { PCI_VENDOR_ID_ADDIDATA,
5994 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5995 PCI_ANY_ID,
5996 PCI_ANY_ID,
5997 0,
5998 0,
5999 pbn_ADDIDATA_PCIe_8_3906250 },
6000
6001 { PCI_VENDOR_ID_ADDIDATA,
6002 PCI_DEVICE_ID_ADDIDATA_CPCI7500,
6003 PCI_ANY_ID,
6004 PCI_ANY_ID,
6005 0,
6006 0,
6007 pbn_b0_4_115200 },
6008
6009 { PCI_VENDOR_ID_ADDIDATA,
6010 PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG,
6011 PCI_ANY_ID,
6012 PCI_ANY_ID,
6013 0,
6014 0,
6015 pbn_b0_4_115200 },
6016
6017 { PCI_VENDOR_ID_ADDIDATA,
6018 PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG,
6019 PCI_ANY_ID,
6020 PCI_ANY_ID,
6021 0,
6022 0,
6023 pbn_b0_2_115200 },
6024
6025 { PCI_VENDOR_ID_ADDIDATA,
6026 PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG,
6027 PCI_ANY_ID,
6028 PCI_ANY_ID,
6029 0,
6030 0,
6031 pbn_b0_1_115200 },
6032
6033 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
6034 PCI_VENDOR_ID_IBM, 0x0299,
6035 0, 0, pbn_b0_bt_2_115200 },
6036
6037 /*
6038 * other NetMos 9835 devices are most likely handled by the
6039 * parport_serial driver, check drivers/parport/parport_serial.c
6040 * before adding them here.
6041 */
6042
6043 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
6044 0xA000, 0x1000,
6045 0, 0, pbn_b0_1_115200 },
6046
6047 /* the 9901 is a rebranded 9912 */
6048 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
6049 0xA000, 0x1000,
6050 0, 0, pbn_b0_1_115200 },
6051
6052 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
6053 0xA000, 0x1000,
6054 0, 0, pbn_b0_1_115200 },
6055
6056 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
6057 0xA000, 0x1000,
6058 0, 0, pbn_b0_1_115200 },
6059
6060 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
6061 0xA000, 0x1000,
6062 0, 0, pbn_b0_1_115200 },
6063
6064 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
6065 0xA000, 0x3002,
6066 0, 0, pbn_NETMOS9900_2s_115200 },
6067
6068 /*
6069 * Best Connectivity and Rosewill PCI Multi I/O cards
6070 */
6071
6072 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6073 0xA000, 0x1000,
6074 0, 0, pbn_b0_1_115200 },
6075
6076 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6077 0xA000, 0x3002,
6078 0, 0, pbn_b0_bt_2_115200 },
6079
6080 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6081 0xA000, 0x3004,
6082 0, 0, pbn_b0_bt_4_115200 },
6083
6084 /*
6085 * ASIX AX99100 PCIe to Multi I/O Controller
6086 */
6087 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
6088 0xA000, 0x1000,
6089 0, 0, pbn_b0_1_115200 },
6090
6091 /* Intel CE4100 */
6092 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
6093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6094 pbn_ce4100_1_115200 },
6095
6096 /*
6097 * Cronyx Omega PCI
6098 */
6099 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
6100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6101 pbn_omegapci },
6102
6103 /*
6104 * Broadcom TruManage
6105 */
6106 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
6107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6108 pbn_brcm_trumanage },
6109
6110 /*
6111 * AgeStar as-prs2-009
6112 */
6113 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
6114 PCI_ANY_ID, PCI_ANY_ID,
6115 0, 0, pbn_b0_bt_2_115200 },
6116
6117 /*
6118 * WCH CH353 series devices: The 2S1P is handled by parport_serial
6119 * so not listed here.
6120 */
6121 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_4S,
6122 PCI_ANY_ID, PCI_ANY_ID,
6123 0, 0, pbn_b0_bt_4_115200 },
6124
6125 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1PF,
6126 PCI_ANY_ID, PCI_ANY_ID,
6127 0, 0, pbn_b0_bt_2_115200 },
6128
6129 { PCI_VENDOR_ID_WCHCN, PCI_DEVICE_ID_WCHCN_CH355_4S,
6130 PCI_ANY_ID, PCI_ANY_ID,
6131 0, 0, pbn_b0_bt_4_115200 },
6132
6133 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S,
6134 PCI_ANY_ID, PCI_ANY_ID,
6135 0, 0, pbn_wch382_2 },
6136
6137 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_4S,
6138 PCI_ANY_ID, PCI_ANY_ID,
6139 0, 0, pbn_wch384_4 },
6140
6141 { PCI_VENDOR_ID_WCHIC, PCI_DEVICE_ID_WCHIC_CH384_8S,
6142 PCI_ANY_ID, PCI_ANY_ID,
6143 0, 0, pbn_wch384_8 },
6144 /*
6145 * Realtek RealManage
6146 */
6147 { PCI_VENDOR_ID_REALTEK, 0x816a,
6148 PCI_ANY_ID, PCI_ANY_ID,
6149 0, 0, pbn_b0_1_115200 },
6150
6151 { PCI_VENDOR_ID_REALTEK, 0x816b,
6152 PCI_ANY_ID, PCI_ANY_ID,
6153 0, 0, pbn_b0_1_115200 },
6154
6155 /* Fintek PCI serial cards */
6156 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
6157 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
6158 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
6159 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
6160 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
6161 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
6162
6163 /* MKS Tenta SCOM-080x serial cards */
6164 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
6165 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
6166
6167 /* Amazon PCI serial device */
6168 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
6169
6170 /*
6171 * These entries match devices with class COMMUNICATION_SERIAL,
6172 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
6173 */
6174 { PCI_ANY_ID, PCI_ANY_ID,
6175 PCI_ANY_ID, PCI_ANY_ID,
6176 PCI_CLASS_COMMUNICATION_SERIAL << 8,
6177 0xffff00, pbn_default },
6178 { PCI_ANY_ID, PCI_ANY_ID,
6179 PCI_ANY_ID, PCI_ANY_ID,
6180 PCI_CLASS_COMMUNICATION_MODEM << 8,
6181 0xffff00, pbn_default },
6182 { PCI_ANY_ID, PCI_ANY_ID,
6183 PCI_ANY_ID, PCI_ANY_ID,
6184 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
6185 0xffff00, pbn_default },
6186 { 0, }
6187 };
6188
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)6189 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
6190 pci_channel_state_t state)
6191 {
6192 struct serial_private *priv = pci_get_drvdata(dev);
6193
6194 if (state == pci_channel_io_perm_failure)
6195 return PCI_ERS_RESULT_DISCONNECT;
6196
6197 if (priv)
6198 pciserial_detach_ports(priv);
6199
6200 pci_disable_device(dev);
6201
6202 return PCI_ERS_RESULT_NEED_RESET;
6203 }
6204
serial8250_io_slot_reset(struct pci_dev * dev)6205 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
6206 {
6207 int rc;
6208
6209 rc = pci_enable_device(dev);
6210
6211 if (rc)
6212 return PCI_ERS_RESULT_DISCONNECT;
6213
6214 pci_restore_state(dev);
6215
6216 return PCI_ERS_RESULT_RECOVERED;
6217 }
6218
serial8250_io_resume(struct pci_dev * dev)6219 static void serial8250_io_resume(struct pci_dev *dev)
6220 {
6221 struct serial_private *priv = pci_get_drvdata(dev);
6222 struct serial_private *new;
6223
6224 if (!priv)
6225 return;
6226
6227 new = pciserial_init_ports(dev, priv->board);
6228 if (!IS_ERR(new)) {
6229 pci_set_drvdata(dev, new);
6230 kfree(priv);
6231 }
6232 }
6233
6234 static const struct pci_error_handlers serial8250_err_handler = {
6235 .error_detected = serial8250_io_error_detected,
6236 .slot_reset = serial8250_io_slot_reset,
6237 .resume = serial8250_io_resume,
6238 };
6239
6240 static struct pci_driver serial_pci_driver = {
6241 .name = "serial",
6242 .probe = pciserial_init_one,
6243 .remove = pciserial_remove_one,
6244 .driver = {
6245 .pm = &pciserial_pm_ops,
6246 },
6247 .id_table = serial_pci_tbl,
6248 .err_handler = &serial8250_err_handler,
6249 };
6250
6251 module_pci_driver(serial_pci_driver);
6252
6253 MODULE_LICENSE("GPL");
6254 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
6255 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
6256 MODULE_IMPORT_NS("SERIAL_8250_PCI");
6257