1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Xilinx XADC driver
4 *
5 * Copyright 2013-2014 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 *
8 * Documentation for the parts can be found at:
9 * - XADC hardmacro: Xilinx UG480
10 * - ZYNQ XADC interface: Xilinx UG585
11 * - AXI XADC interface: Xilinx PG019
12 */
13
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/overflow.h>
22 #include <linux/platform_device.h>
23 #include <linux/property.h>
24 #include <linux/slab.h>
25 #include <linux/sysfs.h>
26
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/events.h>
29 #include <linux/iio/iio.h>
30 #include <linux/iio/sysfs.h>
31 #include <linux/iio/trigger.h>
32 #include <linux/iio/trigger_consumer.h>
33 #include <linux/iio/triggered_buffer.h>
34
35 #include "xilinx-xadc.h"
36
37 static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
38
39 /* ZYNQ register definitions */
40 #define XADC_ZYNQ_REG_CFG 0x00
41 #define XADC_ZYNQ_REG_INTSTS 0x04
42 #define XADC_ZYNQ_REG_INTMSK 0x08
43 #define XADC_ZYNQ_REG_STATUS 0x0c
44 #define XADC_ZYNQ_REG_CFIFO 0x10
45 #define XADC_ZYNQ_REG_DFIFO 0x14
46 #define XADC_ZYNQ_REG_CTL 0x18
47
48 #define XADC_ZYNQ_CFG_ENABLE BIT(31)
49 #define XADC_ZYNQ_CFG_CFIFOTH_MASK (0xf << 20)
50 #define XADC_ZYNQ_CFG_CFIFOTH_OFFSET 20
51 #define XADC_ZYNQ_CFG_DFIFOTH_MASK (0xf << 16)
52 #define XADC_ZYNQ_CFG_DFIFOTH_OFFSET 16
53 #define XADC_ZYNQ_CFG_WEDGE BIT(13)
54 #define XADC_ZYNQ_CFG_REDGE BIT(12)
55 #define XADC_ZYNQ_CFG_TCKRATE_MASK (0x3 << 8)
56 #define XADC_ZYNQ_CFG_TCKRATE_DIV2 (0x0 << 8)
57 #define XADC_ZYNQ_CFG_TCKRATE_DIV4 (0x1 << 8)
58 #define XADC_ZYNQ_CFG_TCKRATE_DIV8 (0x2 << 8)
59 #define XADC_ZYNQ_CFG_TCKRATE_DIV16 (0x3 << 8)
60 #define XADC_ZYNQ_CFG_IGAP_MASK 0x1f
61 #define XADC_ZYNQ_CFG_IGAP(x) (x)
62
63 #define XADC_ZYNQ_INT_CFIFO_LTH BIT(9)
64 #define XADC_ZYNQ_INT_DFIFO_GTH BIT(8)
65 #define XADC_ZYNQ_INT_ALARM_MASK 0xff
66 #define XADC_ZYNQ_INT_ALARM_OFFSET 0
67
68 #define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16)
69 #define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET 16
70 #define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12)
71 #define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET 12
72 #define XADC_ZYNQ_STATUS_CFIFOF BIT(11)
73 #define XADC_ZYNQ_STATUS_CFIFOE BIT(10)
74 #define XADC_ZYNQ_STATUS_DFIFOF BIT(9)
75 #define XADC_ZYNQ_STATUS_DFIFOE BIT(8)
76 #define XADC_ZYNQ_STATUS_OT BIT(7)
77 #define XADC_ZYNQ_STATUS_ALM(x) BIT(x)
78
79 #define XADC_ZYNQ_CTL_RESET BIT(4)
80
81 #define XADC_ZYNQ_CMD_NOP 0x00
82 #define XADC_ZYNQ_CMD_READ 0x01
83 #define XADC_ZYNQ_CMD_WRITE 0x02
84
85 #define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data))
86
87 /* AXI register definitions */
88 #define XADC_AXI_REG_RESET 0x00
89 #define XADC_AXI_REG_STATUS 0x04
90 #define XADC_AXI_REG_ALARM_STATUS 0x08
91 #define XADC_AXI_REG_CONVST 0x0c
92 #define XADC_AXI_REG_XADC_RESET 0x10
93 #define XADC_AXI_REG_GIER 0x5c
94 #define XADC_AXI_REG_IPISR 0x60
95 #define XADC_AXI_REG_IPIER 0x68
96
97 /* 7 Series */
98 #define XADC_7S_AXI_ADC_REG_OFFSET 0x200
99
100 /* UltraScale */
101 #define XADC_US_AXI_ADC_REG_OFFSET 0x400
102
103 #define XADC_AXI_RESET_MAGIC 0xa
104 #define XADC_AXI_GIER_ENABLE BIT(31)
105
106 #define XADC_AXI_INT_EOS BIT(4)
107 #define XADC_AXI_INT_ALARM_MASK 0x3c0f
108
109 #define XADC_FLAGS_BUFFERED BIT(0)
110 #define XADC_FLAGS_IRQ_OPTIONAL BIT(1)
111
112 /*
113 * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
114 * not have a hardware FIFO. Which means an interrupt is generated for each
115 * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
116 * overloaded by the interrupts that it soft-lockups. For this reason the driver
117 * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
118 * but still responsive.
119 */
120 #define XADC_MAX_SAMPLERATE 150000
121
xadc_write_reg(struct xadc * xadc,unsigned int reg,uint32_t val)122 static void xadc_write_reg(struct xadc *xadc, unsigned int reg,
123 uint32_t val)
124 {
125 writel(val, xadc->base + reg);
126 }
127
xadc_read_reg(struct xadc * xadc,unsigned int reg,uint32_t * val)128 static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
129 uint32_t *val)
130 {
131 *val = readl(xadc->base + reg);
132 }
133
134 /*
135 * The ZYNQ interface uses two asynchronous FIFOs for communication with the
136 * XADC. Reads and writes to the XADC register are performed by submitting a
137 * request to the command FIFO (CFIFO), once the request has been completed the
138 * result can be read from the data FIFO (DFIFO). The method currently used in
139 * this driver is to submit the request for a read/write operation, then go to
140 * sleep and wait for an interrupt that signals that a response is available in
141 * the data FIFO.
142 */
143
xadc_zynq_write_fifo(struct xadc * xadc,uint32_t * cmd,unsigned int n)144 static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,
145 unsigned int n)
146 {
147 unsigned int i;
148
149 for (i = 0; i < n; i++)
150 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
151 }
152
xadc_zynq_drain_fifo(struct xadc * xadc)153 static void xadc_zynq_drain_fifo(struct xadc *xadc)
154 {
155 uint32_t status, tmp;
156
157 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
158
159 while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
160 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
161 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
162 }
163 }
164
xadc_zynq_update_intmsk(struct xadc * xadc,unsigned int mask,unsigned int val)165 static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,
166 unsigned int val)
167 {
168 xadc->zynq_intmask &= ~mask;
169 xadc->zynq_intmask |= val;
170
171 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,
172 xadc->zynq_intmask | xadc->zynq_masked_alarm);
173 }
174
xadc_zynq_write_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t val)175 static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
176 uint16_t val)
177 {
178 uint32_t cmd[1];
179 uint32_t tmp;
180 int ret;
181
182 spin_lock_irq(&xadc->lock);
183 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
184 XADC_ZYNQ_INT_DFIFO_GTH);
185
186 reinit_completion(&xadc->completion);
187
188 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
189 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
190 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
191 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
192 tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
193 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
194
195 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
196 spin_unlock_irq(&xadc->lock);
197
198 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
199 if (ret == 0)
200 ret = -EIO;
201 else
202 ret = 0;
203
204 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
205
206 return ret;
207 }
208
xadc_zynq_read_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t * val)209 static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,
210 uint16_t *val)
211 {
212 uint32_t cmd[2];
213 uint32_t resp, tmp;
214 int ret;
215
216 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
217 cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
218
219 spin_lock_irq(&xadc->lock);
220 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
221 XADC_ZYNQ_INT_DFIFO_GTH);
222 xadc_zynq_drain_fifo(xadc);
223 reinit_completion(&xadc->completion);
224
225 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
226 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
227 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
228 tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
229 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
230
231 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
232 spin_unlock_irq(&xadc->lock);
233 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
234 if (ret == 0)
235 ret = -EIO;
236 if (ret < 0)
237 return ret;
238
239 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
240 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
241
242 *val = resp & 0xffff;
243
244 return 0;
245 }
246
xadc_zynq_transform_alarm(unsigned int alarm)247 static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
248 {
249 return ((alarm & 0x80) >> 4) |
250 ((alarm & 0x78) << 1) |
251 (alarm & 0x07);
252 }
253
254 /*
255 * The ZYNQ threshold interrupts are level sensitive. Since we can't make the
256 * threshold condition go way from within the interrupt handler, this means as
257 * soon as a threshold condition is present we would enter the interrupt handler
258 * again and again. To work around this we mask all active thresholds interrupts
259 * in the interrupt handler and start a timer. In this timer we poll the
260 * interrupt status and only if the interrupt is inactive we unmask it again.
261 */
xadc_zynq_unmask_worker(struct work_struct * work)262 static void xadc_zynq_unmask_worker(struct work_struct *work)
263 {
264 struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);
265 unsigned int misc_sts, unmask;
266
267 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);
268
269 misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
270
271 spin_lock_irq(&xadc->lock);
272
273 /* Clear those bits which are not active anymore */
274 unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
275 xadc->zynq_masked_alarm &= misc_sts;
276
277 /* Also clear those which are masked out anyway */
278 xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
279
280 /* Clear the interrupts before we unmask them */
281 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
282
283 xadc_zynq_update_intmsk(xadc, 0, 0);
284
285 spin_unlock_irq(&xadc->lock);
286
287 /* if still pending some alarm re-trigger the timer */
288 if (xadc->zynq_masked_alarm) {
289 schedule_delayed_work(&xadc->zynq_unmask_work,
290 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
291 }
292
293 }
294
xadc_zynq_interrupt_handler(int irq,void * devid)295 static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
296 {
297 struct iio_dev *indio_dev = devid;
298 struct xadc *xadc = iio_priv(indio_dev);
299 uint32_t status;
300
301 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
302
303 status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);
304
305 if (!status)
306 return IRQ_NONE;
307
308 spin_lock(&xadc->lock);
309
310 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
311
312 if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
313 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
314 XADC_ZYNQ_INT_DFIFO_GTH);
315 complete(&xadc->completion);
316 }
317
318 status &= XADC_ZYNQ_INT_ALARM_MASK;
319 if (status) {
320 xadc->zynq_masked_alarm |= status;
321 /*
322 * mask the current event interrupt,
323 * unmask it when the interrupt is no more active.
324 */
325 xadc_zynq_update_intmsk(xadc, 0, 0);
326
327 xadc_handle_events(indio_dev,
328 xadc_zynq_transform_alarm(status));
329
330 /* unmask the required interrupts in timer. */
331 schedule_delayed_work(&xadc->zynq_unmask_work,
332 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
333 }
334 spin_unlock(&xadc->lock);
335
336 return IRQ_HANDLED;
337 }
338
339 #define XADC_ZYNQ_TCK_RATE_MAX 50000000
340 #define XADC_ZYNQ_IGAP_DEFAULT 20
341 #define XADC_ZYNQ_PCAP_RATE_MAX 200000000
342
xadc_zynq_setup(struct platform_device * pdev,struct iio_dev * indio_dev,int irq)343 static int xadc_zynq_setup(struct platform_device *pdev,
344 struct iio_dev *indio_dev, int irq)
345 {
346 struct xadc *xadc = iio_priv(indio_dev);
347 unsigned long pcap_rate;
348 unsigned int tck_div;
349 unsigned int div;
350 unsigned int igap;
351 unsigned int tck_rate;
352 int ret;
353
354 /* TODO: Figure out how to make igap and tck_rate configurable */
355 igap = XADC_ZYNQ_IGAP_DEFAULT;
356 tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
357
358 xadc->zynq_intmask = ~0;
359
360 pcap_rate = clk_get_rate(xadc->clk);
361 if (!pcap_rate)
362 return -EINVAL;
363
364 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
365 ret = clk_set_rate(xadc->clk,
366 (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX);
367 if (ret)
368 return ret;
369 }
370
371 if (tck_rate > pcap_rate / 2) {
372 div = 2;
373 } else {
374 div = pcap_rate / tck_rate;
375 if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX)
376 div++;
377 }
378
379 if (div <= 3)
380 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2;
381 else if (div <= 7)
382 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4;
383 else if (div <= 15)
384 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8;
385 else
386 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16;
387
388 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);
389 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
390 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
391 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
392 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
393 XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
394 tck_div | XADC_ZYNQ_CFG_IGAP(igap));
395
396 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
397 ret = clk_set_rate(xadc->clk, pcap_rate);
398 if (ret)
399 return ret;
400 }
401
402 return 0;
403 }
404
xadc_zynq_get_dclk_rate(struct xadc * xadc)405 static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
406 {
407 unsigned int div;
408 uint32_t val;
409
410 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
411
412 switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) {
413 case XADC_ZYNQ_CFG_TCKRATE_DIV4:
414 div = 4;
415 break;
416 case XADC_ZYNQ_CFG_TCKRATE_DIV8:
417 div = 8;
418 break;
419 case XADC_ZYNQ_CFG_TCKRATE_DIV16:
420 div = 16;
421 break;
422 default:
423 div = 2;
424 break;
425 }
426
427 return clk_get_rate(xadc->clk) / div;
428 }
429
xadc_zynq_update_alarm(struct xadc * xadc,unsigned int alarm)430 static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
431 {
432 unsigned long flags;
433 uint32_t status;
434
435 /* Move OT to bit 7 */
436 alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
437
438 spin_lock_irqsave(&xadc->lock, flags);
439
440 /* Clear previous interrupts if any. */
441 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
442 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
443
444 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,
445 ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
446
447 spin_unlock_irqrestore(&xadc->lock, flags);
448 }
449
450 static const struct xadc_ops xadc_zynq_ops = {
451 .read = xadc_zynq_read_adc_reg,
452 .write = xadc_zynq_write_adc_reg,
453 .setup = xadc_zynq_setup,
454 .get_dclk_rate = xadc_zynq_get_dclk_rate,
455 .interrupt_handler = xadc_zynq_interrupt_handler,
456 .update_alarm = xadc_zynq_update_alarm,
457 .type = XADC_TYPE_S7,
458 /* Temp in C = (val * 503.975) / 2**bits - 273.15 */
459 .temp_scale = 503975,
460 .temp_offset = 273150,
461 };
462
463 static const unsigned int xadc_axi_reg_offsets[] = {
464 [XADC_TYPE_S7] = XADC_7S_AXI_ADC_REG_OFFSET,
465 [XADC_TYPE_US] = XADC_US_AXI_ADC_REG_OFFSET,
466 };
467
xadc_axi_read_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t * val)468 static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
469 uint16_t *val)
470 {
471 uint32_t val32;
472
473 xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
474 &val32);
475 *val = val32 & 0xffff;
476
477 return 0;
478 }
479
xadc_axi_write_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t val)480 static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
481 uint16_t val)
482 {
483 xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
484 val);
485
486 return 0;
487 }
488
xadc_axi_setup(struct platform_device * pdev,struct iio_dev * indio_dev,int irq)489 static int xadc_axi_setup(struct platform_device *pdev,
490 struct iio_dev *indio_dev, int irq)
491 {
492 struct xadc *xadc = iio_priv(indio_dev);
493
494 xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);
495 xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);
496
497 return 0;
498 }
499
xadc_axi_interrupt_handler(int irq,void * devid)500 static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
501 {
502 struct iio_dev *indio_dev = devid;
503 struct xadc *xadc = iio_priv(indio_dev);
504 uint32_t status, mask;
505 unsigned int events;
506
507 xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
508 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);
509 status &= mask;
510
511 if (!status)
512 return IRQ_NONE;
513
514 if ((status & XADC_AXI_INT_EOS) && xadc->trigger)
515 iio_trigger_poll(xadc->trigger);
516
517 if (status & XADC_AXI_INT_ALARM_MASK) {
518 /*
519 * The order of the bits in the AXI-XADC status register does
520 * not match the order of the bits in the XADC alarm enable
521 * register. xadc_handle_events() expects the events to be in
522 * the same order as the XADC alarm enable register.
523 */
524 events = (status & 0x000e) >> 1;
525 events |= (status & 0x0001) << 3;
526 events |= (status & 0x3c00) >> 6;
527 xadc_handle_events(indio_dev, events);
528 }
529
530 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);
531
532 return IRQ_HANDLED;
533 }
534
xadc_axi_update_alarm(struct xadc * xadc,unsigned int alarm)535 static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
536 {
537 uint32_t val;
538 unsigned long flags;
539
540 /*
541 * The order of the bits in the AXI-XADC status register does not match
542 * the order of the bits in the XADC alarm enable register. We get
543 * passed the alarm mask in the same order as in the XADC alarm enable
544 * register.
545 */
546 alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) |
547 ((alarm & 0xf0) << 6);
548
549 spin_lock_irqsave(&xadc->lock, flags);
550 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
551 val &= ~XADC_AXI_INT_ALARM_MASK;
552 val |= alarm;
553 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
554 spin_unlock_irqrestore(&xadc->lock, flags);
555 }
556
xadc_axi_get_dclk(struct xadc * xadc)557 static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
558 {
559 return clk_get_rate(xadc->clk);
560 }
561
562 static const struct xadc_ops xadc_7s_axi_ops = {
563 .read = xadc_axi_read_adc_reg,
564 .write = xadc_axi_write_adc_reg,
565 .setup = xadc_axi_setup,
566 .get_dclk_rate = xadc_axi_get_dclk,
567 .update_alarm = xadc_axi_update_alarm,
568 .interrupt_handler = xadc_axi_interrupt_handler,
569 .flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
570 .type = XADC_TYPE_S7,
571 /* Temp in C = (val * 503.975) / 2**bits - 273.15 */
572 .temp_scale = 503975,
573 .temp_offset = 273150,
574 };
575
576 static const struct xadc_ops xadc_us_axi_ops = {
577 .read = xadc_axi_read_adc_reg,
578 .write = xadc_axi_write_adc_reg,
579 .setup = xadc_axi_setup,
580 .get_dclk_rate = xadc_axi_get_dclk,
581 .update_alarm = xadc_axi_update_alarm,
582 .interrupt_handler = xadc_axi_interrupt_handler,
583 .flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
584 .type = XADC_TYPE_US,
585 /**
586 * Values below are for UltraScale+ (SYSMONE4) using internal reference.
587 * See https://docs.xilinx.com/v/u/en-US/ug580-ultrascale-sysmon
588 */
589 .temp_scale = 509314,
590 .temp_offset = 280231,
591 };
592
_xadc_update_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t mask,uint16_t val)593 static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
594 uint16_t mask, uint16_t val)
595 {
596 uint16_t tmp;
597 int ret;
598
599 ret = _xadc_read_adc_reg(xadc, reg, &tmp);
600 if (ret)
601 return ret;
602
603 return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
604 }
605
xadc_update_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t mask,uint16_t val)606 static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
607 uint16_t mask, uint16_t val)
608 {
609 int ret;
610
611 mutex_lock(&xadc->mutex);
612 ret = _xadc_update_adc_reg(xadc, reg, mask, val);
613 mutex_unlock(&xadc->mutex);
614
615 return ret;
616 }
617
xadc_get_dclk_rate(struct xadc * xadc)618 static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
619 {
620 return xadc->ops->get_dclk_rate(xadc);
621 }
622
xadc_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * mask)623 static int xadc_update_scan_mode(struct iio_dev *indio_dev,
624 const unsigned long *mask)
625 {
626 struct xadc *xadc = iio_priv(indio_dev);
627 size_t n;
628 void *data;
629
630 n = bitmap_weight(mask, iio_get_masklength(indio_dev));
631
632 data = devm_krealloc_array(indio_dev->dev.parent, xadc->data,
633 n, sizeof(*xadc->data), GFP_KERNEL);
634 if (!data)
635 return -ENOMEM;
636
637 memset(data, 0, n * sizeof(*xadc->data));
638 xadc->data = data;
639
640 return 0;
641 }
642
xadc_scan_index_to_channel(unsigned int scan_index)643 static unsigned int xadc_scan_index_to_channel(unsigned int scan_index)
644 {
645 switch (scan_index) {
646 case 5:
647 return XADC_REG_VCCPINT;
648 case 6:
649 return XADC_REG_VCCPAUX;
650 case 7:
651 return XADC_REG_VCCO_DDR;
652 case 8:
653 return XADC_REG_TEMP;
654 case 9:
655 return XADC_REG_VCCINT;
656 case 10:
657 return XADC_REG_VCCAUX;
658 case 11:
659 return XADC_REG_VPVN;
660 case 12:
661 return XADC_REG_VREFP;
662 case 13:
663 return XADC_REG_VREFN;
664 case 14:
665 return XADC_REG_VCCBRAM;
666 default:
667 return XADC_REG_VAUX(scan_index - 16);
668 }
669 }
670
xadc_trigger_handler(int irq,void * p)671 static irqreturn_t xadc_trigger_handler(int irq, void *p)
672 {
673 struct iio_poll_func *pf = p;
674 struct iio_dev *indio_dev = pf->indio_dev;
675 struct xadc *xadc = iio_priv(indio_dev);
676 unsigned int chan;
677 int i, j;
678
679 if (!xadc->data)
680 goto out;
681
682 j = 0;
683 iio_for_each_active_channel(indio_dev, i) {
684 chan = xadc_scan_index_to_channel(i);
685 xadc_read_adc_reg(xadc, chan, &xadc->data[j]);
686 j++;
687 }
688
689 iio_push_to_buffers(indio_dev, xadc->data);
690
691 out:
692 iio_trigger_notify_done(indio_dev->trig);
693
694 return IRQ_HANDLED;
695 }
696
xadc_trigger_set_state(struct iio_trigger * trigger,bool state)697 static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
698 {
699 struct xadc *xadc = iio_trigger_get_drvdata(trigger);
700 unsigned long flags;
701 unsigned int convst;
702 unsigned int val;
703 int ret = 0;
704
705 mutex_lock(&xadc->mutex);
706
707 if (state) {
708 /* Only one of the two triggers can be active at a time. */
709 if (xadc->trigger != NULL) {
710 ret = -EBUSY;
711 goto err_out;
712 } else {
713 xadc->trigger = trigger;
714 if (trigger == xadc->convst_trigger)
715 convst = XADC_CONF0_EC;
716 else
717 convst = 0;
718 }
719 ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,
720 convst);
721 if (ret)
722 goto err_out;
723 } else {
724 xadc->trigger = NULL;
725 }
726
727 spin_lock_irqsave(&xadc->lock, flags);
728 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
729 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
730 if (state)
731 val |= XADC_AXI_INT_EOS;
732 else
733 val &= ~XADC_AXI_INT_EOS;
734 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
735 spin_unlock_irqrestore(&xadc->lock, flags);
736
737 err_out:
738 mutex_unlock(&xadc->mutex);
739
740 return ret;
741 }
742
743 static const struct iio_trigger_ops xadc_trigger_ops = {
744 .set_trigger_state = &xadc_trigger_set_state,
745 };
746
xadc_alloc_trigger(struct iio_dev * indio_dev,const char * name)747 static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
748 const char *name)
749 {
750 struct device *dev = indio_dev->dev.parent;
751 struct iio_trigger *trig;
752 int ret;
753
754 trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name,
755 iio_device_id(indio_dev), name);
756 if (trig == NULL)
757 return ERR_PTR(-ENOMEM);
758
759 trig->ops = &xadc_trigger_ops;
760 iio_trigger_set_drvdata(trig, iio_priv(indio_dev));
761
762 ret = devm_iio_trigger_register(dev, trig);
763 if (ret)
764 return ERR_PTR(ret);
765
766 return trig;
767 }
768
xadc_power_adc_b(struct xadc * xadc,unsigned int seq_mode)769 static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
770 {
771 uint16_t val;
772
773 /*
774 * As per datasheet the power-down bits are don't care in the
775 * UltraScale, but as per reality setting the power-down bit for the
776 * non-existing ADC-B powers down the main ADC, so just return and don't
777 * do anything.
778 */
779 if (xadc->ops->type == XADC_TYPE_US)
780 return 0;
781
782 /* Powerdown the ADC-B when it is not needed. */
783 switch (seq_mode) {
784 case XADC_CONF1_SEQ_SIMULTANEOUS:
785 case XADC_CONF1_SEQ_INDEPENDENT:
786 val = 0;
787 break;
788 default:
789 val = XADC_CONF2_PD_ADC_B;
790 break;
791 }
792
793 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
794 val);
795 }
796
xadc_get_seq_mode(struct xadc * xadc,unsigned long scan_mode)797 static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
798 {
799 unsigned int aux_scan_mode = scan_mode >> 16;
800
801 /* UltraScale has only one ADC and supports only continuous mode */
802 if (xadc->ops->type == XADC_TYPE_US)
803 return XADC_CONF1_SEQ_CONTINUOUS;
804
805 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
806 return XADC_CONF1_SEQ_SIMULTANEOUS;
807
808 if ((aux_scan_mode & 0xff00) == 0 ||
809 (aux_scan_mode & 0x00ff) == 0)
810 return XADC_CONF1_SEQ_CONTINUOUS;
811
812 return XADC_CONF1_SEQ_SIMULTANEOUS;
813 }
814
xadc_postdisable(struct iio_dev * indio_dev)815 static int xadc_postdisable(struct iio_dev *indio_dev)
816 {
817 struct xadc *xadc = iio_priv(indio_dev);
818 unsigned long scan_mask;
819 int seq_mode;
820 int ret;
821 int i;
822
823 scan_mask = 1; /* Run calibration as part of the sequence */
824 for (i = 0; i < indio_dev->num_channels; i++)
825 scan_mask |= BIT(indio_dev->channels[i].scan_index);
826
827 /*
828 * Use the correct sequencer mode for the idle state: simultaneous
829 * mode for dual external mux configurations, continuous otherwise.
830 */
831 seq_mode = xadc_get_seq_mode(xadc, scan_mask);
832
833 /* Enable all channels and calibration */
834 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
835 if (ret)
836 return ret;
837
838 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
839 if (ret)
840 return ret;
841
842 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
843 seq_mode);
844 if (ret)
845 return ret;
846
847 return xadc_power_adc_b(xadc, seq_mode);
848 }
849
xadc_preenable(struct iio_dev * indio_dev)850 static int xadc_preenable(struct iio_dev *indio_dev)
851 {
852 struct xadc *xadc = iio_priv(indio_dev);
853 unsigned long scan_mask;
854 int seq_mode;
855 int ret;
856
857 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
858 XADC_CONF1_SEQ_DEFAULT);
859 if (ret)
860 goto err;
861
862 scan_mask = *indio_dev->active_scan_mask;
863 seq_mode = xadc_get_seq_mode(xadc, scan_mask);
864
865 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
866 if (ret)
867 goto err;
868
869 /*
870 * In simultaneous mode the upper and lower aux channels are samples at
871 * the same time. In this mode the upper 8 bits in the sequencer
872 * register are don't care and the lower 8 bits control two channels
873 * each. As such we must set the bit if either the channel in the lower
874 * group or the upper group is enabled.
875 */
876 if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS)
877 scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000;
878
879 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
880 if (ret)
881 goto err;
882
883 ret = xadc_power_adc_b(xadc, seq_mode);
884 if (ret)
885 goto err;
886
887 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
888 seq_mode);
889 if (ret)
890 goto err;
891
892 return 0;
893 err:
894 xadc_postdisable(indio_dev);
895 return ret;
896 }
897
898 static const struct iio_buffer_setup_ops xadc_buffer_ops = {
899 .preenable = &xadc_preenable,
900 .postdisable = &xadc_postdisable,
901 };
902
xadc_read_samplerate(struct xadc * xadc)903 static int xadc_read_samplerate(struct xadc *xadc)
904 {
905 unsigned int div;
906 uint16_t val16;
907 int ret;
908
909 ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
910 if (ret)
911 return ret;
912
913 div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
914 if (div < 2)
915 div = 2;
916
917 return xadc_get_dclk_rate(xadc) / div / 26;
918 }
919
xadc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)920 static int xadc_read_raw(struct iio_dev *indio_dev,
921 struct iio_chan_spec const *chan, int *val, int *val2, long info)
922 {
923 struct xadc *xadc = iio_priv(indio_dev);
924 unsigned int bits = chan->scan_type.realbits;
925 uint16_t val16;
926 int ret;
927
928 switch (info) {
929 case IIO_CHAN_INFO_RAW:
930 if (iio_buffer_enabled(indio_dev))
931 return -EBUSY;
932 ret = xadc_read_adc_reg(xadc, chan->address, &val16);
933 if (ret < 0)
934 return ret;
935
936 val16 >>= chan->scan_type.shift;
937 if (chan->scan_type.sign == 'u')
938 *val = val16;
939 else
940 *val = sign_extend32(val16, bits - 1);
941
942 return IIO_VAL_INT;
943 case IIO_CHAN_INFO_SCALE:
944 switch (chan->type) {
945 case IIO_VOLTAGE:
946 /* V = (val * 3.0) / 2**bits */
947 switch (chan->address) {
948 case XADC_REG_VCCINT:
949 case XADC_REG_VCCAUX:
950 case XADC_REG_VREFP:
951 case XADC_REG_VREFN:
952 case XADC_REG_VCCBRAM:
953 case XADC_REG_VCCPINT:
954 case XADC_REG_VCCPAUX:
955 case XADC_REG_VCCO_DDR:
956 *val = 3000;
957 break;
958 default:
959 *val = 1000;
960 break;
961 }
962 *val2 = bits;
963 return IIO_VAL_FRACTIONAL_LOG2;
964 case IIO_TEMP:
965 *val = xadc->ops->temp_scale;
966 *val2 = bits;
967 return IIO_VAL_FRACTIONAL_LOG2;
968 default:
969 return -EINVAL;
970 }
971 case IIO_CHAN_INFO_OFFSET:
972 /* Only the temperature channel has an offset */
973 *val = -((xadc->ops->temp_offset << bits) / xadc->ops->temp_scale);
974 return IIO_VAL_INT;
975 case IIO_CHAN_INFO_SAMP_FREQ:
976 ret = xadc_read_samplerate(xadc);
977 if (ret < 0)
978 return ret;
979
980 *val = ret;
981 return IIO_VAL_INT;
982 default:
983 return -EINVAL;
984 }
985 }
986
xadc_write_samplerate(struct xadc * xadc,int val)987 static int xadc_write_samplerate(struct xadc *xadc, int val)
988 {
989 unsigned long clk_rate = xadc_get_dclk_rate(xadc);
990 unsigned int div;
991
992 if (!clk_rate)
993 return -EINVAL;
994
995 if (val <= 0)
996 return -EINVAL;
997
998 /* Max. 150 kSPS */
999 if (val > XADC_MAX_SAMPLERATE)
1000 val = XADC_MAX_SAMPLERATE;
1001
1002 val *= 26;
1003
1004 /* Min 1MHz */
1005 if (val < 1000000)
1006 val = 1000000;
1007
1008 /*
1009 * We want to round down, but only if we do not exceed the 150 kSPS
1010 * limit.
1011 */
1012 div = clk_rate / val;
1013 if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE)
1014 div++;
1015 if (div < 2)
1016 div = 2;
1017 else if (div > 0xff)
1018 div = 0xff;
1019
1020 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
1021 div << XADC_CONF2_DIV_OFFSET);
1022 }
1023
xadc_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)1024 static int xadc_write_raw(struct iio_dev *indio_dev,
1025 struct iio_chan_spec const *chan, int val, int val2, long info)
1026 {
1027 struct xadc *xadc = iio_priv(indio_dev);
1028
1029 if (info != IIO_CHAN_INFO_SAMP_FREQ)
1030 return -EINVAL;
1031
1032 return xadc_write_samplerate(xadc, val);
1033 }
1034
1035 static const struct iio_event_spec xadc_temp_events[] = {
1036 {
1037 .type = IIO_EV_TYPE_THRESH,
1038 .dir = IIO_EV_DIR_RISING,
1039 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
1040 BIT(IIO_EV_INFO_VALUE) |
1041 BIT(IIO_EV_INFO_HYSTERESIS),
1042 },
1043 };
1044
1045 /* Separate values for upper and lower thresholds, but only a shared enabled */
1046 static const struct iio_event_spec xadc_voltage_events[] = {
1047 {
1048 .type = IIO_EV_TYPE_THRESH,
1049 .dir = IIO_EV_DIR_RISING,
1050 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1051 }, {
1052 .type = IIO_EV_TYPE_THRESH,
1053 .dir = IIO_EV_DIR_FALLING,
1054 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1055 }, {
1056 .type = IIO_EV_TYPE_THRESH,
1057 .dir = IIO_EV_DIR_EITHER,
1058 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1059 },
1060 };
1061
1062 #define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \
1063 .type = IIO_TEMP, \
1064 .indexed = 1, \
1065 .channel = (_chan), \
1066 .address = (_addr), \
1067 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1068 BIT(IIO_CHAN_INFO_SCALE) | \
1069 BIT(IIO_CHAN_INFO_OFFSET), \
1070 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1071 .event_spec = xadc_temp_events, \
1072 .num_event_specs = ARRAY_SIZE(xadc_temp_events), \
1073 .scan_index = (_scan_index), \
1074 .scan_type = { \
1075 .sign = 'u', \
1076 .realbits = (_bits), \
1077 .storagebits = 16, \
1078 .shift = 16 - (_bits), \
1079 .endianness = IIO_CPU, \
1080 }, \
1081 }
1082
1083 #define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \
1084 .type = IIO_VOLTAGE, \
1085 .indexed = 1, \
1086 .channel = (_chan), \
1087 .address = (_addr), \
1088 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1089 BIT(IIO_CHAN_INFO_SCALE), \
1090 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1091 .event_spec = (_alarm) ? xadc_voltage_events : NULL, \
1092 .num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \
1093 .scan_index = (_scan_index), \
1094 .scan_type = { \
1095 .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
1096 .realbits = (_bits), \
1097 .storagebits = 16, \
1098 .shift = 16 - (_bits), \
1099 .endianness = IIO_CPU, \
1100 }, \
1101 .extend_name = _ext, \
1102 }
1103
1104 /* 7 Series */
1105 #define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \
1106 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12)
1107 #define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1108 XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 12, _ext, _alarm)
1109
1110 static const struct iio_chan_spec xadc_7s_channels[] = {
1111 XADC_7S_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1112 XADC_7S_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1113 XADC_7S_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1114 XADC_7S_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1115 XADC_7S_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
1116 XADC_7S_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
1117 XADC_7S_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
1118 XADC_7S_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1119 XADC_7S_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1120 XADC_7S_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1121 XADC_7S_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1122 XADC_7S_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1123 XADC_7S_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1124 XADC_7S_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1125 XADC_7S_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1126 XADC_7S_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1127 XADC_7S_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1128 XADC_7S_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1129 XADC_7S_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1130 XADC_7S_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1131 XADC_7S_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1132 XADC_7S_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1133 XADC_7S_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1134 XADC_7S_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1135 XADC_7S_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1136 XADC_7S_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1137 };
1138
1139 /* UltraScale */
1140 #define XADC_US_CHAN_TEMP(_chan, _scan_index, _addr) \
1141 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 10)
1142 #define XADC_US_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1143 XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 10, _ext, _alarm)
1144
1145 static const struct iio_chan_spec xadc_us_channels[] = {
1146 XADC_US_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1147 XADC_US_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1148 XADC_US_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1149 XADC_US_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1150 XADC_US_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpsintlp", true),
1151 XADC_US_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpsintfp", true),
1152 XADC_US_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccpsaux", true),
1153 XADC_US_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1154 XADC_US_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1155 XADC_US_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1156 XADC_US_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1157 XADC_US_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1158 XADC_US_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1159 XADC_US_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1160 XADC_US_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1161 XADC_US_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1162 XADC_US_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1163 XADC_US_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1164 XADC_US_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1165 XADC_US_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1166 XADC_US_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1167 XADC_US_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1168 XADC_US_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1169 XADC_US_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1170 XADC_US_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1171 XADC_US_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1172 };
1173
1174 static const struct iio_info xadc_info = {
1175 .read_raw = &xadc_read_raw,
1176 .write_raw = &xadc_write_raw,
1177 .read_event_config = &xadc_read_event_config,
1178 .write_event_config = &xadc_write_event_config,
1179 .read_event_value = &xadc_read_event_value,
1180 .write_event_value = &xadc_write_event_value,
1181 .update_scan_mode = &xadc_update_scan_mode,
1182 };
1183
1184 static const struct of_device_id xadc_of_match_table[] = {
1185 {
1186 .compatible = "xlnx,zynq-xadc-1.00.a",
1187 .data = &xadc_zynq_ops
1188 }, {
1189 .compatible = "xlnx,axi-xadc-1.00.a",
1190 .data = &xadc_7s_axi_ops
1191 }, {
1192 .compatible = "xlnx,system-management-wiz-1.3",
1193 .data = &xadc_us_axi_ops
1194 },
1195 { }
1196 };
1197 MODULE_DEVICE_TABLE(of, xadc_of_match_table);
1198
xadc_parse_dt(struct iio_dev * indio_dev,unsigned int * conf,int irq)1199 static int xadc_parse_dt(struct iio_dev *indio_dev, unsigned int *conf, int irq)
1200 {
1201 struct device *dev = indio_dev->dev.parent;
1202 struct xadc *xadc = iio_priv(indio_dev);
1203 const struct iio_chan_spec *channel_templates;
1204 struct iio_chan_spec *channels, *chan;
1205 struct fwnode_handle *chan_node, *child;
1206 unsigned int max_channels;
1207 unsigned int num_channels;
1208 const char *external_mux;
1209 u32 ext_mux_chan;
1210 u32 reg;
1211 int ret;
1212 int i;
1213
1214 *conf = 0;
1215
1216 ret = device_property_read_string(dev, "xlnx,external-mux", &external_mux);
1217 if (ret < 0 || strcasecmp(external_mux, "none") == 0)
1218 xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;
1219 else if (strcasecmp(external_mux, "single") == 0)
1220 xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;
1221 else if (strcasecmp(external_mux, "dual") == 0)
1222 xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;
1223 else
1224 return -EINVAL;
1225
1226 if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {
1227 ret = device_property_read_u32(dev, "xlnx,external-mux-channel", &ext_mux_chan);
1228 if (ret < 0)
1229 return ret;
1230
1231 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {
1232 if (ext_mux_chan == 0)
1233 ext_mux_chan = XADC_REG_VPVN;
1234 else if (ext_mux_chan <= 16)
1235 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1236 else
1237 return -EINVAL;
1238 } else {
1239 if (ext_mux_chan > 0 && ext_mux_chan <= 8)
1240 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1241 else
1242 return -EINVAL;
1243 }
1244
1245 *conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan);
1246 }
1247 if (xadc->ops->type == XADC_TYPE_S7) {
1248 channel_templates = xadc_7s_channels;
1249 max_channels = ARRAY_SIZE(xadc_7s_channels);
1250 } else {
1251 channel_templates = xadc_us_channels;
1252 max_channels = ARRAY_SIZE(xadc_us_channels);
1253 }
1254 channels = devm_kmemdup_array(dev, channel_templates, max_channels,
1255 sizeof(*channel_templates), GFP_KERNEL);
1256 if (!channels)
1257 return -ENOMEM;
1258
1259 num_channels = 9;
1260 chan = &channels[9];
1261
1262 chan_node = device_get_named_child_node(dev, "xlnx,channels");
1263 fwnode_for_each_child_node(chan_node, child) {
1264 if (num_channels >= max_channels) {
1265 fwnode_handle_put(child);
1266 break;
1267 }
1268
1269 ret = fwnode_property_read_u32(child, "reg", ®);
1270 if (ret || reg > 16)
1271 continue;
1272
1273 if (fwnode_property_read_bool(child, "xlnx,bipolar"))
1274 chan->scan_type.sign = 's';
1275
1276 if (reg == 0) {
1277 chan->scan_index = 11;
1278 chan->address = XADC_REG_VPVN;
1279 } else {
1280 chan->scan_index = 15 + reg;
1281 chan->address = XADC_REG_VAUX(reg - 1);
1282 }
1283 num_channels++;
1284 chan++;
1285 }
1286 fwnode_handle_put(chan_node);
1287
1288 /* No IRQ => no events */
1289 if (irq <= 0) {
1290 for (i = 0; i < num_channels; i++) {
1291 channels[i].event_spec = NULL;
1292 channels[i].num_event_specs = 0;
1293 }
1294 }
1295
1296 indio_dev->num_channels = num_channels;
1297 indio_dev->channels = devm_krealloc_array(dev, channels,
1298 num_channels, sizeof(*channels),
1299 GFP_KERNEL);
1300 /* If we can't resize the channels array, just use the original */
1301 if (!indio_dev->channels)
1302 indio_dev->channels = channels;
1303
1304 return 0;
1305 }
1306
1307 static const char * const xadc_type_names[] = {
1308 [XADC_TYPE_S7] = "xadc",
1309 [XADC_TYPE_US] = "xilinx-system-monitor",
1310 };
1311
xadc_cancel_delayed_work(void * data)1312 static void xadc_cancel_delayed_work(void *data)
1313 {
1314 struct delayed_work *work = data;
1315
1316 cancel_delayed_work_sync(work);
1317 }
1318
xadc_probe(struct platform_device * pdev)1319 static int xadc_probe(struct platform_device *pdev)
1320 {
1321 struct device *dev = &pdev->dev;
1322 const struct xadc_ops *ops;
1323 struct iio_dev *indio_dev;
1324 unsigned int bipolar_mask;
1325 unsigned int conf0;
1326 struct xadc *xadc;
1327 int ret;
1328 int irq;
1329 int i;
1330
1331 ops = device_get_match_data(dev);
1332 if (!ops)
1333 return -EINVAL;
1334
1335 irq = platform_get_irq_optional(pdev, 0);
1336 if (irq < 0 &&
1337 (irq != -ENXIO || !(ops->flags & XADC_FLAGS_IRQ_OPTIONAL)))
1338 return irq;
1339
1340 indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc));
1341 if (!indio_dev)
1342 return -ENOMEM;
1343
1344 xadc = iio_priv(indio_dev);
1345 xadc->ops = ops;
1346 init_completion(&xadc->completion);
1347 mutex_init(&xadc->mutex);
1348 spin_lock_init(&xadc->lock);
1349 INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);
1350
1351 xadc->base = devm_platform_ioremap_resource(pdev, 0);
1352 if (IS_ERR(xadc->base))
1353 return PTR_ERR(xadc->base);
1354
1355 indio_dev->name = xadc_type_names[xadc->ops->type];
1356 indio_dev->modes = INDIO_DIRECT_MODE;
1357 indio_dev->info = &xadc_info;
1358
1359 ret = xadc_parse_dt(indio_dev, &conf0, irq);
1360 if (ret)
1361 return ret;
1362
1363 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1364 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1365 &iio_pollfunc_store_time,
1366 &xadc_trigger_handler,
1367 &xadc_buffer_ops);
1368 if (ret)
1369 return ret;
1370
1371 if (irq > 0) {
1372 xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
1373 if (IS_ERR(xadc->convst_trigger))
1374 return PTR_ERR(xadc->convst_trigger);
1375
1376 xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,
1377 "samplerate");
1378 if (IS_ERR(xadc->samplerate_trigger))
1379 return PTR_ERR(xadc->samplerate_trigger);
1380 }
1381 }
1382
1383 xadc->clk = devm_clk_get_enabled(dev, NULL);
1384 if (IS_ERR(xadc->clk))
1385 return PTR_ERR(xadc->clk);
1386
1387 /*
1388 * Make sure not to exceed the maximum samplerate since otherwise the
1389 * resulting interrupt storm will soft-lock the system.
1390 */
1391 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1392 ret = xadc_read_samplerate(xadc);
1393 if (ret < 0)
1394 return ret;
1395
1396 if (ret > XADC_MAX_SAMPLERATE) {
1397 ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);
1398 if (ret < 0)
1399 return ret;
1400 }
1401 }
1402
1403 if (irq > 0) {
1404 ret = devm_request_irq(dev, irq, xadc->ops->interrupt_handler,
1405 0, dev_name(dev), indio_dev);
1406 if (ret)
1407 return ret;
1408
1409 ret = devm_add_action_or_reset(dev, xadc_cancel_delayed_work,
1410 &xadc->zynq_unmask_work);
1411 if (ret)
1412 return ret;
1413 }
1414
1415 ret = xadc->ops->setup(pdev, indio_dev, irq);
1416 if (ret)
1417 return ret;
1418
1419 for (i = 0; i < 16; i++)
1420 xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1421 &xadc->threshold[i]);
1422
1423 ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
1424 if (ret)
1425 return ret;
1426
1427 bipolar_mask = 0;
1428 for (i = 0; i < indio_dev->num_channels; i++) {
1429 if (indio_dev->channels[i].scan_type.sign == 's')
1430 bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
1431 }
1432
1433 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);
1434 if (ret)
1435 return ret;
1436
1437 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),
1438 bipolar_mask >> 16);
1439 if (ret)
1440 return ret;
1441
1442 /* Go to non-buffered mode */
1443 xadc_postdisable(indio_dev);
1444
1445 return devm_iio_device_register(dev, indio_dev);
1446 }
1447
1448 static struct platform_driver xadc_driver = {
1449 .probe = xadc_probe,
1450 .driver = {
1451 .name = "xadc",
1452 .of_match_table = xadc_of_match_table,
1453 },
1454 };
1455 module_platform_driver(xadc_driver);
1456
1457 MODULE_LICENSE("GPL v2");
1458 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1459 MODULE_DESCRIPTION("Xilinx XADC IIO driver");
1460