1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/bits.h>
4 #include <linux/clk.h>
5 #include <linux/i2c.h>
6 #include <linux/i2c-mux.h>
7 #include <linux/mfd/syscon.h>
8 #include <linux/mutex.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11 #include <linux/unaligned.h>
12
13 enum rtl9300_bus_freq {
14 RTL9300_I2C_STD_FREQ, // 100kHz
15 RTL9300_I2C_FAST_FREQ, // 400kHz
16 RTL9300_I2C_SUPER_FAST_FREQ, // 2.5MHz
17 RTL9300_I2C_SLOW_FREQ, // 50kHz
18 };
19
20 #define RTL9300_I2C_MAX_SUPER_FAST_FREQ 2500000
21 #define RTL9300_I2C_MAX_SLOW_FREQ 50000
22
23
24 struct rtl9300_i2c;
25
26 struct rtl9300_i2c_chan {
27 struct i2c_adapter adap;
28 struct rtl9300_i2c *i2c;
29 enum rtl9300_bus_freq bus_freq;
30 u8 sda_num;
31 u32 clk_div;
32 };
33
34 enum rtl9300_i2c_reg_scope {
35 REG_SCOPE_GLOBAL,
36 REG_SCOPE_MASTER,
37 };
38
39 struct rtl9300_i2c_reg_field {
40 struct reg_field field;
41 enum rtl9300_i2c_reg_scope scope;
42 };
43
44 enum rtl9300_i2c_reg_fields {
45 F_DATA_WIDTH = 0,
46 F_DEV_ADDR,
47 F_I2C_FAIL,
48 F_I2C_TRIG,
49 F_MEM_ADDR,
50 F_MEM_ADDR_WIDTH,
51 F_RD_MODE,
52 F_RWOP,
53 F_SCL_FREQ,
54 F_SCL_SEL,
55 F_SDA_OUT_SEL,
56 F_SDA_SEL,
57 F_BUSY,
58 F_CLK_DIV,
59 F_EXT_SCK_5MS,
60
61 /* keep last */
62 F_NUM_FIELDS
63 };
64
65 struct rtl9300_i2c_drv_data {
66 struct rtl9300_i2c_reg_field field_desc[F_NUM_FIELDS];
67 int (*select_scl)(struct rtl9300_i2c *i2c, u8 scl);
68 int (*config_chan)(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan);
69 void (*config_clock)(u32 clock_freq, struct rtl9300_i2c_chan *chan);
70 int (*misc_init)(struct rtl9300_i2c *i2c);
71 u32 rd_reg;
72 u32 wd_reg;
73 u8 max_nchan;
74 u8 max_data_len;
75 u8 reg_addr_8bit_len;
76 };
77
78 #define RTL9300_I2C_MUX_NCHAN 8
79 #define RTL9310_I2C_MUX_NCHAN 12
80 #define RTL9607_I2C_MUX_NCHAN 1
81
82 #define RTL9300_I2C_MAX_DATA_LEN 16
83 #define RTL9607_I2C_MAX_DATA_LEN 4
84
85 struct rtl9300_i2c {
86 struct regmap *regmap;
87 struct device *dev;
88 struct rtl9300_i2c_chan chans[RTL9310_I2C_MUX_NCHAN];
89 struct regmap_field *fields[F_NUM_FIELDS];
90 u32 reg_base;
91 u32 rd_reg;
92 u32 wd_reg;
93 u8 scl_num;
94 u8 sda_num;
95 struct mutex lock;
96 struct clk *clk;
97 };
98
99 DEFINE_GUARD(rtl9300_i2c, struct rtl9300_i2c *, mutex_lock(&_T->lock), mutex_unlock(&_T->lock))
100
101 enum rtl9300_i2c_xfer_type {
102 RTL9300_I2C_XFER_BYTE,
103 RTL9300_I2C_XFER_WORD,
104 RTL9300_I2C_XFER_BLOCK,
105 };
106
107 struct rtl9300_i2c_xfer {
108 enum rtl9300_i2c_xfer_type type;
109 u16 dev_addr;
110 u8 reg_addr;
111 u8 reg_addr_len;
112 u8 *data;
113 u8 data_len;
114 bool write;
115 };
116
117 #define RTL9300_I2C_MST_CTRL1 0x0
118 #define RTL9300_I2C_MST_CTRL2 0x4
119 #define RTL9300_I2C_MST_DATA_WORD0 0x8
120 #define RTL9300_I2C_MST_DATA_WORD1 0xc
121 #define RTL9300_I2C_MST_DATA_WORD2 0x10
122 #define RTL9300_I2C_MST_DATA_WORD3 0x14
123 #define RTL9300_I2C_MST_GLB_CTRL 0x384
124 #define RTL9300_REG_ADDR_8BIT_LEN 1
125
126 #define RTL9310_I2C_MST_IF_CTRL 0x1004
127 #define RTL9310_I2C_MST_IF_SEL 0x1008
128 #define RTL9310_I2C_MST_CTRL 0x0
129 #define RTL9310_I2C_MST_MEMADDR_CTRL 0x4
130 #define RTL9310_I2C_MST_DATA_CTRL 0x8
131
132 #define RTL9607_I2C_CONFIG 0x22f50
133 #define RTL9607_IO_MODE_EN 0x23014
134 #define RTL9607_I2C_IND_WD 0x0
135 #define RTL9607_I2C_IND_ADR 0x8
136 #define RTL9607_I2C_IND_CMD 0x10
137 #define RTL9607_I2C_IND_RD 0x18
138 #define RTL9607_REG_ADDR_8BIT_LEN 0
139
rtl9300_i2c_reg_addr_set(struct rtl9300_i2c * i2c,u32 reg,u16 len)140 static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len)
141 {
142 int ret;
143
144 ret = regmap_field_write(i2c->fields[F_MEM_ADDR_WIDTH], len);
145 if (ret)
146 return ret;
147
148 return regmap_field_write(i2c->fields[F_MEM_ADDR], reg);
149 }
150
rtl9300_i2c_select_scl(struct rtl9300_i2c * i2c,u8 scl)151 static int rtl9300_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl)
152 {
153 return regmap_field_write(i2c->fields[F_SCL_SEL], 1);
154 }
155
rtl9310_i2c_select_scl(struct rtl9300_i2c * i2c,u8 scl)156 static int rtl9310_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl)
157 {
158 return regmap_field_update_bits(i2c->fields[F_SCL_SEL], BIT(scl), BIT(scl));
159 }
160
rtl9300_i2c_config_chan(struct rtl9300_i2c * i2c,struct rtl9300_i2c_chan * chan)161 static int rtl9300_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan)
162 {
163 const struct rtl9300_i2c_drv_data *drv_data;
164 int ret;
165
166 if (i2c->sda_num == chan->sda_num)
167 return 0;
168
169 ret = regmap_field_write(i2c->fields[F_SCL_FREQ], chan->bus_freq);
170 if (ret)
171 return ret;
172
173 drv_data = device_get_match_data(i2c->dev);
174 ret = drv_data->select_scl(i2c, i2c->scl_num);
175 if (ret)
176 return ret;
177
178 ret = regmap_field_update_bits(i2c->fields[F_SDA_SEL], BIT(chan->sda_num),
179 BIT(chan->sda_num));
180 if (ret)
181 return ret;
182
183 ret = regmap_field_write(i2c->fields[F_SDA_OUT_SEL], chan->sda_num);
184 if (ret)
185 return ret;
186
187 i2c->sda_num = chan->sda_num;
188 return 0;
189 }
190
rtl9607_i2c_config_chan(struct rtl9300_i2c * i2c,struct rtl9300_i2c_chan * chan)191 static int rtl9607_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan)
192 {
193 const struct rtl9300_i2c_drv_data *drv_data;
194 int ret;
195
196 if (i2c->sda_num == chan->sda_num)
197 return 0;
198
199 ret = regmap_field_write(i2c->fields[F_CLK_DIV], chan->clk_div);
200 if (ret)
201 return ret;
202
203 drv_data = device_get_match_data(i2c->dev);
204 ret = drv_data->select_scl(i2c, i2c->scl_num);
205 if (ret)
206 return ret;
207
208 i2c->sda_num = chan->sda_num;
209 return 0;
210 }
211
rtl9300_i2c_config_clock(u32 clock_freq,struct rtl9300_i2c_chan * chan)212 static void rtl9300_i2c_config_clock(u32 clock_freq, struct rtl9300_i2c_chan *chan)
213 {
214 struct rtl9300_i2c *i2c = chan->i2c;
215
216 switch (clock_freq) {
217 case I2C_MAX_STANDARD_MODE_FREQ:
218 chan->bus_freq = RTL9300_I2C_STD_FREQ;
219 break;
220 case I2C_MAX_FAST_MODE_FREQ:
221 chan->bus_freq = RTL9300_I2C_FAST_FREQ;
222 break;
223 case RTL9300_I2C_MAX_SUPER_FAST_FREQ:
224 chan->bus_freq = RTL9300_I2C_SUPER_FAST_FREQ;
225 break;
226 case RTL9300_I2C_MAX_SLOW_FREQ:
227 chan->bus_freq = RTL9300_I2C_SLOW_FREQ;
228 break;
229 default:
230 dev_warn(i2c->dev, "SDA%d clock-frequency %d not supported using default\n",
231 chan->sda_num, clock_freq);
232 break;
233 }
234 }
235
rtl9607_i2c_config_clock(u32 clock_freq,struct rtl9300_i2c_chan * chan)236 static void rtl9607_i2c_config_clock(u32 clock_freq, struct rtl9300_i2c_chan *chan)
237 {
238 struct rtl9300_i2c *i2c = chan->i2c;
239
240 chan->clk_div = clk_get_rate(i2c->clk) / clock_freq - 1;
241 }
242
rtl9300_i2c_read(struct rtl9300_i2c * i2c,u8 * buf,u8 len)243 static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, u8 len)
244 {
245 u32 vals[4] = {};
246 int i, ret;
247
248 if (len > 16)
249 return -EIO;
250
251 ret = regmap_bulk_read(i2c->regmap, i2c->rd_reg, vals, ARRAY_SIZE(vals));
252 if (ret)
253 return ret;
254
255 for (i = 0; i < len; i++) {
256 buf[i] = vals[i/4] & 0xff;
257 vals[i/4] >>= 8;
258 }
259
260 return 0;
261 }
262
rtl9300_i2c_write(struct rtl9300_i2c * i2c,u8 * buf,u8 len)263 static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, u8 len)
264 {
265 u32 vals[4] = {};
266 int i;
267
268 if (len > 16)
269 return -EIO;
270
271 for (i = 0; i < len; i++) {
272 unsigned int shift = (i % 4) * 8;
273 unsigned int reg = i / 4;
274
275 vals[reg] |= buf[i] << shift;
276 }
277
278 return regmap_bulk_write(i2c->regmap, i2c->wd_reg, vals, ARRAY_SIZE(vals));
279 }
280
rtl9300_i2c_writel(struct rtl9300_i2c * i2c,u32 data)281 static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data)
282 {
283 return regmap_write(i2c->regmap, i2c->wd_reg, data);
284 }
285
rtl9300_i2c_prepare_xfer(struct rtl9300_i2c * i2c,struct rtl9300_i2c_xfer * xfer)286 static int rtl9300_i2c_prepare_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_xfer *xfer)
287 {
288 const struct rtl9300_i2c_drv_data *drv_data;
289 int ret;
290
291 drv_data = device_get_match_data(i2c->dev);
292 if (xfer->data_len < 1 || xfer->data_len > drv_data->max_data_len)
293 return -EINVAL;
294
295 ret = regmap_field_write(i2c->fields[F_DEV_ADDR], xfer->dev_addr);
296 if (ret)
297 return ret;
298
299 ret = rtl9300_i2c_reg_addr_set(i2c, xfer->reg_addr, xfer->reg_addr_len);
300 if (ret)
301 return ret;
302
303 ret = regmap_field_write(i2c->fields[F_RWOP], xfer->write);
304 if (ret)
305 return ret;
306
307 ret = regmap_field_write(i2c->fields[F_DATA_WIDTH], (xfer->data_len - 1) & 0xf);
308 if (ret)
309 return ret;
310
311 if (xfer->write) {
312 switch (xfer->type) {
313 case RTL9300_I2C_XFER_BYTE:
314 ret = rtl9300_i2c_writel(i2c, *xfer->data);
315 break;
316 case RTL9300_I2C_XFER_WORD:
317 ret = rtl9300_i2c_writel(i2c, get_unaligned((const u16 *)xfer->data));
318 break;
319 default:
320 ret = rtl9300_i2c_write(i2c, xfer->data, xfer->data_len);
321 break;
322 }
323 }
324
325 return ret;
326 }
327
rtl9300_i2c_do_xfer(struct rtl9300_i2c * i2c,struct rtl9300_i2c_xfer * xfer)328 static int rtl9300_i2c_do_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_xfer *xfer)
329 {
330 u32 val;
331 int ret;
332
333 ret = regmap_field_write(i2c->fields[F_I2C_TRIG], 1);
334 if (ret)
335 return ret;
336
337 ret = regmap_field_read_poll_timeout(i2c->fields[F_BUSY], val, !val, 100, 100000);
338 if (ret)
339 return ret;
340
341 ret = regmap_field_read(i2c->fields[F_I2C_FAIL], &val);
342 if (ret)
343 return ret;
344 if (val)
345 return -EIO;
346
347 if (!xfer->write) {
348 switch (xfer->type) {
349 case RTL9300_I2C_XFER_BYTE:
350 ret = regmap_read(i2c->regmap, i2c->rd_reg, &val);
351 if (ret)
352 return ret;
353
354 *xfer->data = val & 0xff;
355 break;
356 case RTL9300_I2C_XFER_WORD:
357 ret = regmap_read(i2c->regmap, i2c->rd_reg, &val);
358 if (ret)
359 return ret;
360
361 put_unaligned(val & 0xffff, (u16*)xfer->data);
362 break;
363 default:
364 ret = rtl9300_i2c_read(i2c, xfer->data, xfer->data_len);
365 if (ret)
366 return ret;
367 break;
368 }
369 }
370
371 return 0;
372 }
373
rtl9300_i2c_smbus_xfer(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)374 static int rtl9300_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, unsigned short flags,
375 char read_write, u8 command, int size,
376 union i2c_smbus_data *data)
377 {
378 struct rtl9300_i2c_chan *chan = i2c_get_adapdata(adap);
379 const struct rtl9300_i2c_drv_data *drv_data;
380 struct rtl9300_i2c *i2c = chan->i2c;
381 struct rtl9300_i2c_xfer xfer = {0};
382 int ret;
383
384 if (addr > 0x7f)
385 return -EINVAL;
386
387 guard(rtl9300_i2c)(i2c);
388
389 drv_data = device_get_match_data(i2c->dev);
390 ret = drv_data->config_chan(i2c, chan);
391 if (ret)
392 return ret;
393
394 xfer.dev_addr = addr & 0x7f;
395 xfer.write = (read_write == I2C_SMBUS_WRITE);
396 xfer.reg_addr = command;
397 xfer.reg_addr_len = drv_data->reg_addr_8bit_len;
398
399 switch (size) {
400 case I2C_SMBUS_BYTE:
401 xfer.data = (read_write == I2C_SMBUS_READ) ? &data->byte : &command;
402 xfer.data_len = 1;
403 xfer.reg_addr = 0;
404 xfer.reg_addr_len = 0;
405 xfer.type = RTL9300_I2C_XFER_BYTE;
406 break;
407 case I2C_SMBUS_BYTE_DATA:
408 xfer.data = &data->byte;
409 xfer.data_len = 1;
410 xfer.type = RTL9300_I2C_XFER_BYTE;
411 break;
412 case I2C_SMBUS_WORD_DATA:
413 xfer.data = (u8 *)&data->word;
414 xfer.data_len = 2;
415 xfer.type = RTL9300_I2C_XFER_WORD;
416 break;
417 case I2C_SMBUS_BLOCK_DATA:
418 xfer.data = &data->block[0];
419 xfer.data_len = data->block[0] + 1;
420 xfer.type = RTL9300_I2C_XFER_BLOCK;
421 break;
422 case I2C_SMBUS_I2C_BLOCK_DATA:
423 xfer.data = &data->block[1];
424 xfer.data_len = data->block[0];
425 xfer.type = RTL9300_I2C_XFER_BLOCK;
426 break;
427 default:
428 dev_err(&adap->dev, "Unsupported transaction %d\n", size);
429 return -EOPNOTSUPP;
430 }
431
432 ret = rtl9300_i2c_prepare_xfer(i2c, &xfer);
433 if (ret)
434 return ret;
435
436 return rtl9300_i2c_do_xfer(i2c, &xfer);
437 }
438
rtl9300_i2c_func(struct i2c_adapter * a)439 static u32 rtl9300_i2c_func(struct i2c_adapter *a)
440 {
441 return I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |
442 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
443 I2C_FUNC_SMBUS_I2C_BLOCK;
444 }
445
446 static const struct i2c_algorithm rtl9300_i2c_algo = {
447 .smbus_xfer = rtl9300_i2c_smbus_xfer,
448 .functionality = rtl9300_i2c_func,
449 };
450
451 static struct i2c_adapter_quirks rtl9300_i2c_quirks = {
452 .flags = I2C_AQ_NO_CLK_STRETCH | I2C_AQ_NO_ZERO_LEN,
453 .max_read_len = 16,
454 .max_write_len = 16,
455 };
456
rtl9300_i2c_init(struct rtl9300_i2c * i2c)457 static int rtl9300_i2c_init(struct rtl9300_i2c *i2c)
458 {
459 /* only use standard read format */
460 return regmap_field_write(i2c->fields[F_RD_MODE], 0);
461 }
462
rtl9607_i2c_init(struct rtl9300_i2c * i2c)463 static int rtl9607_i2c_init(struct rtl9300_i2c *i2c)
464 {
465 return regmap_field_write(i2c->fields[F_EXT_SCK_5MS], 1);
466 }
467
rtl9300_i2c_probe(struct platform_device * pdev)468 static int rtl9300_i2c_probe(struct platform_device *pdev)
469 {
470 struct device *dev = &pdev->dev;
471 struct rtl9300_i2c *i2c;
472 const struct rtl9300_i2c_drv_data *drv_data;
473 struct reg_field fields[F_NUM_FIELDS];
474 u32 clock_freq, scl_num, sda_num;
475 int ret, i = 0;
476
477 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
478 if (!i2c)
479 return -ENOMEM;
480
481 i2c->regmap = syscon_node_to_regmap(dev->parent->of_node);
482 if (IS_ERR(i2c->regmap))
483 return PTR_ERR(i2c->regmap);
484 i2c->dev = dev;
485
486 mutex_init(&i2c->lock);
487
488 ret = device_property_read_u32(dev, "reg", &i2c->reg_base);
489 if (ret)
490 return ret;
491
492 ret = device_property_read_u32(dev, "realtek,scl", &scl_num);
493 if (ret || scl_num != 1)
494 scl_num = 0;
495 i2c->scl_num = (u8)scl_num;
496
497 platform_set_drvdata(pdev, i2c);
498
499 drv_data = device_get_match_data(i2c->dev);
500 if (device_get_child_node_count(dev) > drv_data->max_nchan)
501 return dev_err_probe(dev, -EINVAL, "Too many channels\n");
502
503 i2c->rd_reg = i2c->reg_base + drv_data->rd_reg;
504 i2c->wd_reg = i2c->reg_base + drv_data->wd_reg;
505 for (i = 0; i < F_NUM_FIELDS; i++) {
506 fields[i] = drv_data->field_desc[i].field;
507 if (drv_data->field_desc[i].scope == REG_SCOPE_MASTER)
508 fields[i].reg += i2c->reg_base;
509 }
510 ret = devm_regmap_field_bulk_alloc(dev, i2c->regmap, i2c->fields,
511 fields, F_NUM_FIELDS);
512 if (ret)
513 return ret;
514
515 i2c->clk = devm_clk_get_optional_enabled(dev, NULL);
516 if (IS_ERR(i2c->clk))
517 return dev_err_probe(dev, PTR_ERR(i2c->clk), "Failed to enable i2c clock\n");
518
519 i = 0;
520 for_each_child_of_node_scoped(dev->of_node, child) {
521 struct rtl9300_i2c_chan *chan = &i2c->chans[i];
522 struct i2c_adapter *adap = &chan->adap;
523
524 ret = of_property_read_u32(child, "reg", &sda_num);
525 if (ret)
526 return ret;
527
528 ret = of_property_read_u32(child, "clock-frequency", &clock_freq);
529 if (ret)
530 clock_freq = I2C_MAX_STANDARD_MODE_FREQ;
531
532 chan->sda_num = sda_num;
533 chan->i2c = i2c;
534
535 drv_data->config_clock(clock_freq, chan);
536
537 adap = &i2c->chans[i].adap;
538 adap->owner = THIS_MODULE;
539 adap->algo = &rtl9300_i2c_algo;
540 adap->quirks = &rtl9300_i2c_quirks;
541 adap->retries = 3;
542 adap->dev.parent = dev;
543 i2c_set_adapdata(adap, chan);
544 adap->dev.of_node = child;
545 snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_num);
546 i++;
547
548 ret = devm_i2c_add_adapter(dev, adap);
549 if (ret)
550 return ret;
551 }
552 i2c->sda_num = 0xff;
553
554 ret = drv_data->misc_init(i2c);
555 if (ret)
556 return ret;
557
558 return 0;
559 }
560
561 #define GLB_REG_FIELD(reg, msb, lsb) \
562 { .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_GLOBAL }
563 #define MST_REG_FIELD(reg, msb, lsb) \
564 { .field = REG_FIELD(reg, msb, lsb), .scope = REG_SCOPE_MASTER }
565
566 static const struct rtl9300_i2c_drv_data rtl9300_i2c_drv_data = {
567 .field_desc = {
568 [F_MEM_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 8, 31),
569 [F_SDA_OUT_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 4, 6),
570 [F_SCL_SEL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 3, 3),
571 [F_RWOP] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 2, 2),
572 [F_I2C_FAIL] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 1, 1),
573 [F_I2C_TRIG] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 0, 0),
574 [F_RD_MODE] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 15, 15),
575 [F_DEV_ADDR] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 8, 14),
576 [F_DATA_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 4, 7),
577 [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 2, 3),
578 [F_SCL_FREQ] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL2, 0, 1),
579 [F_SDA_SEL] = GLB_REG_FIELD(RTL9300_I2C_MST_GLB_CTRL, 0, 7),
580 [F_BUSY] = MST_REG_FIELD(RTL9300_I2C_MST_CTRL1, 0, 0),
581 },
582 .select_scl = rtl9300_i2c_select_scl,
583 .config_chan = rtl9300_i2c_config_chan,
584 .config_clock = rtl9300_i2c_config_clock,
585 .misc_init = rtl9300_i2c_init,
586 .rd_reg = RTL9300_I2C_MST_DATA_WORD0,
587 .wd_reg = RTL9300_I2C_MST_DATA_WORD0,
588 .max_nchan = RTL9300_I2C_MUX_NCHAN,
589 .max_data_len = RTL9300_I2C_MAX_DATA_LEN,
590 .reg_addr_8bit_len = RTL9300_REG_ADDR_8BIT_LEN,
591 };
592
593 static const struct rtl9300_i2c_drv_data rtl9310_i2c_drv_data = {
594 .field_desc = {
595 [F_SCL_SEL] = GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 12, 13),
596 [F_SDA_SEL] = GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 0, 11),
597 [F_SCL_FREQ] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 30, 31),
598 [F_DEV_ADDR] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 11, 17),
599 [F_SDA_OUT_SEL] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 18, 21),
600 [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 9, 10),
601 [F_DATA_WIDTH] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 5, 8),
602 [F_RD_MODE] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 4, 4),
603 [F_RWOP] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 2, 2),
604 [F_I2C_FAIL] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 1, 1),
605 [F_I2C_TRIG] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 0, 0),
606 [F_MEM_ADDR] = MST_REG_FIELD(RTL9310_I2C_MST_MEMADDR_CTRL, 0, 23),
607 [F_BUSY] = MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 0, 0),
608 },
609 .select_scl = rtl9310_i2c_select_scl,
610 .config_chan = rtl9300_i2c_config_chan,
611 .config_clock = rtl9300_i2c_config_clock,
612 .misc_init = rtl9300_i2c_init,
613 .rd_reg = RTL9310_I2C_MST_DATA_CTRL,
614 .wd_reg = RTL9310_I2C_MST_DATA_CTRL,
615 .max_nchan = RTL9310_I2C_MUX_NCHAN,
616 .max_data_len = RTL9300_I2C_MAX_DATA_LEN,
617 .reg_addr_8bit_len = RTL9300_REG_ADDR_8BIT_LEN,
618 };
619
620 static const struct rtl9300_i2c_drv_data rtl9607_i2c_drv_data = {
621 .field_desc = {
622 [F_SCL_SEL] = GLB_REG_FIELD(RTL9607_IO_MODE_EN, 13, 14),
623 [F_EXT_SCK_5MS] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 26, 26),
624 [F_DEV_ADDR] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 14, 20),
625 [F_MEM_ADDR_WIDTH] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 12, 13),
626 [F_DATA_WIDTH] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 10, 11),
627 [F_CLK_DIV] = MST_REG_FIELD(RTL9607_I2C_CONFIG, 0, 9),
628 [F_I2C_FAIL] = MST_REG_FIELD(RTL9607_I2C_IND_CMD, 3, 3),
629 [F_BUSY] = MST_REG_FIELD(RTL9607_I2C_IND_CMD, 2, 2),
630 [F_RWOP] = MST_REG_FIELD(RTL9607_I2C_IND_CMD, 1, 1),
631 [F_I2C_TRIG] = MST_REG_FIELD(RTL9607_I2C_IND_CMD, 0, 0),
632 [F_MEM_ADDR] = MST_REG_FIELD(RTL9607_I2C_IND_ADR, 0, 31),
633 },
634 .select_scl = rtl9310_i2c_select_scl,
635 .config_chan = rtl9607_i2c_config_chan,
636 .config_clock = rtl9607_i2c_config_clock,
637 .misc_init = rtl9607_i2c_init,
638 .rd_reg = RTL9607_I2C_IND_RD,
639 .wd_reg = RTL9607_I2C_IND_WD,
640 .max_nchan = RTL9607_I2C_MUX_NCHAN,
641 .max_data_len = RTL9607_I2C_MAX_DATA_LEN,
642 .reg_addr_8bit_len = RTL9607_REG_ADDR_8BIT_LEN,
643 };
644
645 static const struct of_device_id i2c_rtl9300_dt_ids[] = {
646 { .compatible = "realtek,rtl9301-i2c", .data = (void *) &rtl9300_i2c_drv_data },
647 { .compatible = "realtek,rtl9302b-i2c", .data = (void *) &rtl9300_i2c_drv_data },
648 { .compatible = "realtek,rtl9302c-i2c", .data = (void *) &rtl9300_i2c_drv_data },
649 { .compatible = "realtek,rtl9303-i2c", .data = (void *) &rtl9300_i2c_drv_data },
650 { .compatible = "realtek,rtl9310-i2c", .data = (void *) &rtl9310_i2c_drv_data },
651 { .compatible = "realtek,rtl9311-i2c", .data = (void *) &rtl9310_i2c_drv_data },
652 { .compatible = "realtek,rtl9312-i2c", .data = (void *) &rtl9310_i2c_drv_data },
653 { .compatible = "realtek,rtl9313-i2c", .data = (void *) &rtl9310_i2c_drv_data },
654 { .compatible = "realtek,rtl9607-i2c", .data = (void *) &rtl9607_i2c_drv_data },
655 {}
656 };
657 MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids);
658
659 static struct platform_driver rtl9300_i2c_driver = {
660 .probe = rtl9300_i2c_probe,
661 .driver = {
662 .name = "i2c-rtl9300",
663 .of_match_table = i2c_rtl9300_dt_ids,
664 },
665 };
666
667 module_platform_driver(rtl9300_i2c_driver);
668
669 MODULE_DESCRIPTION("RTL9300 I2C controller driver");
670 MODULE_LICENSE("GPL");
671