1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 Schneider Electric 4 * 5 * Clément Léger <clement.leger@bootlin.com> 6 */ 7 8 #include <linux/array_size.h> 9 #include <linux/bits.h> 10 #include <linux/bitops.h> 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/device/devres.h> 14 #include <linux/mdio.h> 15 #include <linux/of.h> 16 #include <linux/of_platform.h> 17 #include <linux/pcs-rzn1-miic.h> 18 #include <linux/phylink.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 #include <dt-bindings/net/pcs-rzn1-miic.h> 24 #include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h> 25 26 #define MIIC_PRCMD 0x0 27 #define MIIC_ESID_CODE 0x4 28 29 #define MIIC_MODCTRL 0x8 30 31 #define MIIC_PHY_LINK 0x14 32 33 #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) 34 35 #define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0) 36 #define CONV_MODE_10MBPS 0 37 #define CONV_MODE_100MBPS 1 38 #define CONV_MODE_1000MBPS 2 39 40 #define MIIC_CONVCTRL_CONV_MODE GENMASK(3, 2) 41 #define CONV_MODE_MII 0 42 #define CONV_MODE_RMII 1 43 #define CONV_MODE_RGMII 2 44 45 #define MIIC_CONVCTRL_FULLD BIT(8) 46 #define MIIC_CONVCTRL_RGMII_LINK BIT(12) 47 #define MIIC_CONVCTRL_RGMII_DUPLEX BIT(13) 48 #define MIIC_CONVCTRL_RGMII_SPEED GENMASK(15, 14) 49 50 #define MIIC_CONVRST 0x114 51 #define MIIC_CONVRST_PHYIF_RST(port) BIT(port) 52 #define MIIC_CONVRST_PHYIF_RST_MASK GENMASK(4, 0) 53 54 #define MIIC_SWCTRL 0x304 55 #define MIIC_SWDUPC 0x308 56 57 #define MIIC_MODCTRL_CONF_CONV_MAX 6 58 #define MIIC_MODCTRL_CONF_NONE -1 59 60 #define MIIC_MAX_NUM_RSTS 2 61 62 /** 63 * struct modctrl_match - Matching table entry for convctrl configuration 64 * See section 8.2.1 of manual. 65 * @mode_cfg: Configuration value for convctrl 66 * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN, 67 * then index 1 - 5 are CONV1 - CONV5 for RZ/N1 SoCs. In case 68 * of RZ/T2H and RZ/N2H SoCs, the first index is SWITCH_PORTIN then 69 * index 0 - 3 are CONV0 - CONV3. 70 */ 71 struct modctrl_match { 72 u32 mode_cfg; 73 u8 conv[MIIC_MODCTRL_CONF_CONV_MAX]; 74 }; 75 76 static struct modctrl_match modctrl_match_table[] = { 77 {0x0, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 78 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 79 {0x1, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 80 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 81 {0x2, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 82 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 83 {0x3, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 84 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 85 86 {0x8, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 87 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 88 {0x9, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 89 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 90 {0xA, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 91 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 92 {0xB, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 93 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}, 94 95 {0x10, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 96 MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}}, 97 {0x11, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 98 MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 99 {0x12, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 100 MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}}, 101 {0x13, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD, 102 MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}} 103 }; 104 105 static const char * const conf_to_string[] = { 106 [MIIC_GMAC1_PORT] = "GMAC1_PORT", 107 [MIIC_GMAC2_PORT] = "GMAC2_PORT", 108 [MIIC_RTOS_PORT] = "RTOS_PORT", 109 [MIIC_SERCOS_PORTA] = "SERCOS_PORTA", 110 [MIIC_SERCOS_PORTB] = "SERCOS_PORTB", 111 [MIIC_ETHERCAT_PORTA] = "ETHERCAT_PORTA", 112 [MIIC_ETHERCAT_PORTB] = "ETHERCAT_PORTB", 113 [MIIC_ETHERCAT_PORTC] = "ETHERCAT_PORTC", 114 [MIIC_SWITCH_PORTA] = "SWITCH_PORTA", 115 [MIIC_SWITCH_PORTB] = "SWITCH_PORTB", 116 [MIIC_SWITCH_PORTC] = "SWITCH_PORTC", 117 [MIIC_SWITCH_PORTD] = "SWITCH_PORTD", 118 [MIIC_HSR_PORTA] = "HSR_PORTA", 119 [MIIC_HSR_PORTB] = "HSR_PORTB", 120 }; 121 122 static const char * const index_to_string[] = { 123 "SWITCH_PORTIN", 124 "CONV1", 125 "CONV2", 126 "CONV3", 127 "CONV4", 128 "CONV5", 129 }; 130 131 static struct modctrl_match rzt2h_modctrl_match_table[] = { 132 {0x0, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1, 133 ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}}, 134 135 {0x1, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1, 136 ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}}, 137 138 {0x2, {ETHSS_GMAC0_PORT, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1, 139 ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}}, 140 141 {0x3, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1, 142 ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}}, 143 144 {0x4, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1, 145 ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}}, 146 147 {0x5, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1, 148 ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}}, 149 150 {0x6, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1, 151 ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}}, 152 153 {0x7, {MIIC_MODCTRL_CONF_NONE, ETHSS_GMAC0_PORT, ETHSS_GMAC1_PORT, 154 ETHSS_GMAC2_PORT, MIIC_MODCTRL_CONF_NONE}} 155 }; 156 157 static const char * const rzt2h_conf_to_string[] = { 158 [ETHSS_GMAC0_PORT] = "GMAC0_PORT", 159 [ETHSS_GMAC1_PORT] = "GMAC1_PORT", 160 [ETHSS_GMAC2_PORT] = "GMAC2_PORT", 161 [ETHSS_ESC_PORT0] = "ETHERCAT_PORT0", 162 [ETHSS_ESC_PORT1] = "ETHERCAT_PORT1", 163 [ETHSS_ESC_PORT2] = "ETHERCAT_PORT2", 164 [ETHSS_ETHSW_PORT0] = "SWITCH_PORT0", 165 [ETHSS_ETHSW_PORT1] = "SWITCH_PORT1", 166 [ETHSS_ETHSW_PORT2] = "SWITCH_PORT2", 167 }; 168 169 static const char * const rzt2h_index_to_string[] = { 170 "SWITCH_PORTIN", 171 "CONV0", 172 "CONV1", 173 "CONV2", 174 "CONV3", 175 }; 176 177 static const char * const rzt2h_reset_ids[] = { 178 "rst", 179 "crst", 180 }; 181 182 /** 183 * struct miic_phy_link_cfg - MIIC PHY_LINK configuration 184 * @mask: Mask of phy_link bits 185 * @val: Value of phy_link bits 186 */ 187 struct miic_phy_link_cfg { 188 u32 mask; 189 u32 val; 190 }; 191 192 /** 193 * struct miic - MII converter structure 194 * @base: base address of the MII converter 195 * @dev: Device associated to the MII converter 196 * @lock: Lock used for read-modify-write access 197 * @rsts: Reset controls for the MII converter 198 * @of_data: Pointer to OF data 199 * @link_cfg: MIIC PHY_LINK configuration 200 */ 201 struct miic { 202 void __iomem *base; 203 struct device *dev; 204 spinlock_t lock; 205 struct reset_control_bulk_data rsts[MIIC_MAX_NUM_RSTS]; 206 const struct miic_of_data *of_data; 207 struct miic_phy_link_cfg link_cfg; 208 }; 209 210 enum miic_type { 211 MIIC_TYPE_RZN1, 212 MIIC_TYPE_RZT2H, 213 }; 214 215 /** 216 * struct miic_of_data - OF data for MII converter 217 * @match_table: Matching table for convctrl configuration 218 * @match_table_count: Number of entries in the matching table 219 * @conf_conv_count: Number of entries in the conf_conv array 220 * @conf_to_string: String representations of the configuration values 221 * @conf_to_string_count: Number of entries in the conf_to_string array 222 * @index_to_string: String representations of the index values 223 * @index_to_string_count: Number of entries in the index_to_string array 224 * @miic_port_start: MIIC port start number 225 * @miic_port_max: Maximum MIIC supported 226 * @sw_mode_mask: Switch mode mask 227 * @reset_ids: Reset names array 228 * @reset_count: Number of entries in the reset_ids array 229 * @init_unlock_lock_regs: Flag to indicate if registers need to be unlocked 230 * before access. 231 * @miic_write: Function pointer to write a value to a MIIC register 232 * @type: Type of MIIC 233 */ 234 struct miic_of_data { 235 struct modctrl_match *match_table; 236 u8 match_table_count; 237 u8 conf_conv_count; 238 const char * const *conf_to_string; 239 u8 conf_to_string_count; 240 const char * const *index_to_string; 241 u8 index_to_string_count; 242 u8 miic_port_start; 243 u8 miic_port_max; 244 u8 sw_mode_mask; 245 const char * const *reset_ids; 246 u8 reset_count; 247 bool init_unlock_lock_regs; 248 void (*miic_write)(struct miic *miic, int offset, u32 value); 249 enum miic_type type; 250 }; 251 252 /** 253 * struct miic_port - Per port MII converter struct 254 * @miic: backiling to MII converter structure 255 * @pcs: PCS structure associated to the port 256 * @port: port number 257 * @interface: interface mode of the port 258 */ 259 struct miic_port { 260 struct miic *miic; 261 struct phylink_pcs pcs; 262 int port; 263 phy_interface_t interface; 264 }; 265 266 static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs) 267 { 268 return container_of(pcs, struct miic_port, pcs); 269 } 270 271 static void miic_unlock_regs(struct miic *miic) 272 { 273 /* Clear protection state */ 274 writel(0x0000, miic->base + MIIC_PRCMD); 275 276 /* Unprotect register writes */ 277 writel(0x00A5, miic->base + MIIC_PRCMD); 278 writel(0x0001, miic->base + MIIC_PRCMD); 279 writel(0xFFFE, miic->base + MIIC_PRCMD); 280 writel(0x0001, miic->base + MIIC_PRCMD); 281 } 282 283 static void miic_lock_regs(struct miic *miic) 284 { 285 /* Protect register writes */ 286 writel(0x0000, miic->base + MIIC_PRCMD); 287 } 288 289 static void miic_reg_writel_unlocked(struct miic *miic, int offset, u32 value) 290 { 291 writel(value, miic->base + offset); 292 } 293 294 static void miic_reg_writel_locked(struct miic *miic, int offset, u32 value) 295 { 296 miic_unlock_regs(miic); 297 writel(value, miic->base + offset); 298 miic_lock_regs(miic); 299 } 300 301 static void miic_reg_writel(struct miic *miic, int offset, u32 value) 302 { 303 miic->of_data->miic_write(miic, offset, value); 304 } 305 306 static u32 miic_reg_readl(struct miic *miic, int offset) 307 { 308 return readl(miic->base + offset); 309 } 310 311 static void miic_reg_rmw(struct miic *miic, int offset, u32 mask, u32 val) 312 { 313 u32 reg; 314 315 spin_lock(&miic->lock); 316 317 reg = miic_reg_readl(miic, offset); 318 reg &= ~mask; 319 reg |= val; 320 miic_reg_writel(miic, offset, reg); 321 322 spin_unlock(&miic->lock); 323 } 324 325 static void miic_converter_enable(struct miic *miic, int port, int enable) 326 { 327 u32 val = 0; 328 329 if (enable) 330 val = MIIC_CONVRST_PHYIF_RST(port); 331 332 miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val); 333 } 334 335 static int miic_config(struct phylink_pcs *pcs, unsigned int neg_mode, 336 phy_interface_t interface, 337 const unsigned long *advertising, bool permit) 338 { 339 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 340 struct miic *miic = miic_port->miic; 341 u32 speed, conv_mode, val, mask; 342 int port = miic_port->port; 343 344 switch (interface) { 345 case PHY_INTERFACE_MODE_RMII: 346 conv_mode = CONV_MODE_RMII; 347 speed = CONV_MODE_100MBPS; 348 break; 349 case PHY_INTERFACE_MODE_RGMII: 350 case PHY_INTERFACE_MODE_RGMII_ID: 351 case PHY_INTERFACE_MODE_RGMII_TXID: 352 case PHY_INTERFACE_MODE_RGMII_RXID: 353 conv_mode = CONV_MODE_RGMII; 354 speed = CONV_MODE_1000MBPS; 355 break; 356 case PHY_INTERFACE_MODE_MII: 357 conv_mode = CONV_MODE_MII; 358 /* When in MII mode, speed should be set to 0 (which is actually 359 * CONV_MODE_10MBPS) 360 */ 361 speed = CONV_MODE_10MBPS; 362 break; 363 default: 364 return -EOPNOTSUPP; 365 } 366 367 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, conv_mode); 368 mask = MIIC_CONVCTRL_CONV_MODE; 369 370 /* Update speed only if we are going to change the interface because 371 * the link might already be up and it would break it if the speed is 372 * changed. 373 */ 374 if (interface != miic_port->interface) { 375 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed); 376 mask |= MIIC_CONVCTRL_CONV_SPEED; 377 miic_port->interface = interface; 378 } 379 380 miic_reg_rmw(miic, MIIC_CONVCTRL(port), mask, val); 381 miic_converter_enable(miic, miic_port->port, 1); 382 383 return 0; 384 } 385 386 static void miic_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, 387 phy_interface_t interface, int speed, int duplex) 388 { 389 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 390 struct miic *miic = miic_port->miic; 391 u32 conv_speed = 0, val = 0; 392 int port = miic_port->port; 393 394 if (duplex == DUPLEX_FULL) 395 val |= MIIC_CONVCTRL_FULLD; 396 397 /* No speed in MII through-mode */ 398 if (interface != PHY_INTERFACE_MODE_MII) { 399 switch (speed) { 400 case SPEED_1000: 401 conv_speed = CONV_MODE_1000MBPS; 402 break; 403 case SPEED_100: 404 conv_speed = CONV_MODE_100MBPS; 405 break; 406 case SPEED_10: 407 conv_speed = CONV_MODE_10MBPS; 408 break; 409 default: 410 return; 411 } 412 } 413 414 val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, conv_speed); 415 416 miic_reg_rmw(miic, MIIC_CONVCTRL(port), 417 (MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val); 418 } 419 420 static int miic_pre_init(struct phylink_pcs *pcs) 421 { 422 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 423 struct miic *miic = miic_port->miic; 424 u32 val, mask; 425 426 /* Start RX clock if required */ 427 if (pcs->rxc_always_on) { 428 /* In MII through mode, the clock signals will be driven by the 429 * external PHY, which might not be initialized yet. Set RMII 430 * as default mode to ensure that a reference clock signal is 431 * generated. 432 */ 433 miic_port->interface = PHY_INTERFACE_MODE_RMII; 434 435 val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII) | 436 FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, CONV_MODE_100MBPS); 437 mask = MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED; 438 439 miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port), mask, val); 440 441 miic_converter_enable(miic, miic_port->port, 1); 442 } 443 444 return 0; 445 } 446 447 static const struct phylink_pcs_ops miic_phylink_ops = { 448 .pcs_config = miic_config, 449 .pcs_link_up = miic_link_up, 450 .pcs_pre_init = miic_pre_init, 451 }; 452 453 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np) 454 { 455 const struct miic_of_data *of_data; 456 struct platform_device *pdev; 457 struct miic_port *miic_port; 458 struct device_node *pcs_np; 459 struct miic *miic; 460 u32 port; 461 462 if (!of_device_is_available(np)) 463 return ERR_PTR(-ENODEV); 464 465 if (of_property_read_u32(np, "reg", &port)) 466 return ERR_PTR(-EINVAL); 467 468 /* The PCS pdev is attached to the parent node */ 469 pcs_np = of_get_parent(np); 470 if (!pcs_np) 471 return ERR_PTR(-ENODEV); 472 473 if (!of_device_is_available(pcs_np)) { 474 of_node_put(pcs_np); 475 return ERR_PTR(-ENODEV); 476 } 477 478 pdev = of_find_device_by_node(pcs_np); 479 of_node_put(pcs_np); 480 if (!pdev || !platform_get_drvdata(pdev)) { 481 if (pdev) 482 put_device(&pdev->dev); 483 return ERR_PTR(-EPROBE_DEFER); 484 } 485 486 miic = platform_get_drvdata(pdev); 487 of_data = miic->of_data; 488 if (port > of_data->miic_port_max || port < of_data->miic_port_start) { 489 put_device(&pdev->dev); 490 return ERR_PTR(-EINVAL); 491 } 492 493 miic_port = kzalloc_obj(*miic_port); 494 if (!miic_port) { 495 put_device(&pdev->dev); 496 return ERR_PTR(-ENOMEM); 497 } 498 499 device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER); 500 put_device(&pdev->dev); 501 502 miic_port->miic = miic; 503 miic_port->port = port - of_data->miic_port_start; 504 miic_port->pcs.ops = &miic_phylink_ops; 505 506 phy_interface_set_rgmii(miic_port->pcs.supported_interfaces); 507 __set_bit(PHY_INTERFACE_MODE_RMII, miic_port->pcs.supported_interfaces); 508 __set_bit(PHY_INTERFACE_MODE_MII, miic_port->pcs.supported_interfaces); 509 510 return &miic_port->pcs; 511 } 512 EXPORT_SYMBOL(miic_create); 513 514 void miic_destroy(struct phylink_pcs *pcs) 515 { 516 struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); 517 518 miic_converter_enable(miic_port->miic, miic_port->port, 0); 519 kfree(miic_port); 520 } 521 EXPORT_SYMBOL(miic_destroy); 522 523 static int miic_init_hw(struct miic *miic, u32 cfg_mode) 524 { 525 u8 sw_mode_mask = miic->of_data->sw_mode_mask; 526 int port; 527 528 /* Unlock write access to accessory registers (cf datasheet). If this 529 * is going to be used in conjunction with the Cortex-M3, this sequence 530 * will have to be moved in register write 531 */ 532 if (miic->of_data->init_unlock_lock_regs) 533 miic_unlock_regs(miic); 534 535 /* TODO: Replace with FIELD_PREP() when compile-time constant 536 * restriction is lifted. Currently __ffs() returns 0 for sw_mode_mask. 537 */ 538 miic_reg_writel(miic, MIIC_MODCTRL, 539 ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask)); 540 541 for (port = 0; port < miic->of_data->miic_port_max; port++) { 542 miic_converter_enable(miic, port, 0); 543 /* Disable speed/duplex control from these registers, datasheet 544 * says switch registers should be used to setup switch port 545 * speed and duplex. 546 */ 547 miic_reg_writel(miic, MIIC_SWCTRL, 0x0); 548 miic_reg_writel(miic, MIIC_SWDUPC, 0x0); 549 } 550 551 return 0; 552 } 553 554 static bool miic_modctrl_match(s8 *table_val, s8 *dt_val, u8 count) 555 { 556 int i; 557 558 for (i = 0; i < count; i++) { 559 if (dt_val[i] == MIIC_MODCTRL_CONF_NONE) 560 continue; 561 562 if (dt_val[i] != table_val[i]) 563 return false; 564 } 565 566 return true; 567 } 568 569 static void miic_dump_conf(struct miic *miic, s8 *conf) 570 { 571 const struct miic_of_data *of_data = miic->of_data; 572 const char *conf_name; 573 int i; 574 575 for (i = 0; i < of_data->conf_conv_count; i++) { 576 if (conf[i] != MIIC_MODCTRL_CONF_NONE) 577 conf_name = of_data->conf_to_string[conf[i]]; 578 else 579 conf_name = "NONE"; 580 581 dev_err(miic->dev, "%s: %s\n", 582 of_data->index_to_string[i], conf_name); 583 } 584 } 585 586 static int miic_match_dt_conf(struct miic *miic, s8 *dt_val, u32 *mode_cfg) 587 { 588 const struct miic_of_data *of_data = miic->of_data; 589 struct modctrl_match *table_entry; 590 int i; 591 592 for (i = 0; i < of_data->match_table_count; i++) { 593 table_entry = &of_data->match_table[i]; 594 595 if (miic_modctrl_match(table_entry->conv, dt_val, 596 miic->of_data->conf_conv_count)) { 597 *mode_cfg = table_entry->mode_cfg; 598 return 0; 599 } 600 } 601 602 dev_err(miic->dev, "Failed to apply requested configuration\n"); 603 miic_dump_conf(miic, dt_val); 604 605 return -EINVAL; 606 } 607 608 static void miic_configure_phy_link(struct miic *miic, u32 conf, 609 u32 port, bool active_low) 610 { 611 bool polarity_active_high; 612 u32 mask, shift; 613 614 /* determine shift and polarity for this conf */ 615 if (miic->of_data->type == MIIC_TYPE_RZN1) { 616 switch (conf) { 617 /* switch ports => bits [3:0] (shift 0), active when low */ 618 case MIIC_SWITCH_PORTA: 619 case MIIC_SWITCH_PORTB: 620 case MIIC_SWITCH_PORTC: 621 case MIIC_SWITCH_PORTD: 622 shift = 0; 623 polarity_active_high = false; 624 break; 625 626 /* EtherCAT ports => bits [7:4] (shift 4), active when high */ 627 case MIIC_ETHERCAT_PORTA: 628 case MIIC_ETHERCAT_PORTB: 629 case MIIC_ETHERCAT_PORTC: 630 shift = 4; 631 polarity_active_high = true; 632 break; 633 634 /* Sercos ports => bits [11:8] (shift 8), active when high */ 635 case MIIC_SERCOS_PORTA: 636 case MIIC_SERCOS_PORTB: 637 shift = 8; 638 polarity_active_high = true; 639 break; 640 641 default: 642 return; 643 } 644 } else { 645 switch (conf) { 646 /* ETHSW ports => bits [3:0] (shift 0), active when low */ 647 case ETHSS_ETHSW_PORT0: 648 case ETHSS_ETHSW_PORT1: 649 case ETHSS_ETHSW_PORT2: 650 shift = 0; 651 polarity_active_high = false; 652 break; 653 654 /* ESC ports => bits [7:4] (shift 4), active when high */ 655 case ETHSS_ESC_PORT0: 656 case ETHSS_ESC_PORT1: 657 case ETHSS_ESC_PORT2: 658 shift = 4; 659 polarity_active_high = true; 660 break; 661 662 default: 663 return; 664 } 665 } 666 667 mask = BIT(port + shift); 668 669 miic->link_cfg.mask |= mask; 670 if (polarity_active_high != active_low) 671 miic->link_cfg.val |= mask; 672 else 673 miic->link_cfg.val &= ~mask; 674 } 675 676 static int miic_parse_dt(struct miic *miic, u32 *mode_cfg) 677 { 678 struct device_node *np = miic->dev->of_node; 679 struct device_node *conv; 680 bool active_low; 681 int port, ret; 682 s8 *dt_val; 683 u32 conf; 684 685 dt_val = kmalloc_objs(*dt_val, miic->of_data->conf_conv_count); 686 if (!dt_val) 687 return -ENOMEM; 688 689 memset(dt_val, MIIC_MODCTRL_CONF_NONE, 690 sizeof(*dt_val) * miic->of_data->conf_conv_count); 691 692 if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0) 693 dt_val[0] = conf; 694 695 for_each_available_child_of_node(np, conv) { 696 if (of_property_read_u32(conv, "reg", &port)) 697 continue; 698 699 if (of_property_read_u32(conv, "renesas,miic-input", &conf)) 700 continue; 701 702 /* Adjust for 0 based index */ 703 dt_val[port + !miic->of_data->miic_port_start] = conf; 704 705 active_low = of_property_read_bool(conv, "renesas,miic-phy-link-active-low"); 706 707 miic_configure_phy_link(miic, conf, port, active_low); 708 } 709 710 ret = miic_match_dt_conf(miic, dt_val, mode_cfg); 711 kfree(dt_val); 712 713 return ret; 714 } 715 716 static void miic_reset_control_bulk_assert(void *data) 717 { 718 struct miic *miic = data; 719 int ret; 720 721 ret = reset_control_bulk_assert(miic->of_data->reset_count, miic->rsts); 722 if (ret) 723 dev_err(miic->dev, "failed to assert reset lines\n"); 724 } 725 726 static int miic_reset_control_init(struct miic *miic) 727 { 728 const struct miic_of_data *of_data = miic->of_data; 729 struct device *dev = miic->dev; 730 int ret; 731 u8 i; 732 733 if (!of_data->reset_count) 734 return 0; 735 736 for (i = 0; i < of_data->reset_count; i++) 737 miic->rsts[i].id = of_data->reset_ids[i]; 738 739 ret = devm_reset_control_bulk_get_exclusive(dev, of_data->reset_count, 740 miic->rsts); 741 if (ret) 742 return dev_err_probe(dev, ret, 743 "failed to get bulk reset lines\n"); 744 745 ret = reset_control_bulk_deassert(of_data->reset_count, miic->rsts); 746 if (ret) 747 return dev_err_probe(dev, ret, 748 "failed to deassert reset lines\n"); 749 750 ret = devm_add_action_or_reset(dev, miic_reset_control_bulk_assert, 751 miic); 752 if (ret) 753 return dev_err_probe(dev, ret, "failed to add reset action\n"); 754 755 return 0; 756 } 757 758 static int miic_probe(struct platform_device *pdev) 759 { 760 struct device *dev = &pdev->dev; 761 struct miic *miic; 762 u32 mode_cfg; 763 int ret; 764 765 miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL); 766 if (!miic) 767 return -ENOMEM; 768 769 miic->of_data = of_device_get_match_data(dev); 770 miic->dev = dev; 771 772 ret = miic_parse_dt(miic, &mode_cfg); 773 if (ret < 0) 774 return ret; 775 776 spin_lock_init(&miic->lock); 777 miic->base = devm_platform_ioremap_resource(pdev, 0); 778 if (IS_ERR(miic->base)) 779 return PTR_ERR(miic->base); 780 781 ret = miic_reset_control_init(miic); 782 if (ret) 783 return ret; 784 785 ret = devm_pm_runtime_enable(dev); 786 if (ret < 0) 787 return ret; 788 789 ret = pm_runtime_resume_and_get(dev); 790 if (ret < 0) 791 return ret; 792 793 ret = miic_init_hw(miic, mode_cfg); 794 if (ret) 795 goto disable_runtime_pm; 796 797 miic_reg_rmw(miic, MIIC_PHY_LINK, miic->link_cfg.mask, miic->link_cfg.val); 798 799 /* miic_create() relies on that fact that data are attached to the 800 * platform device to determine if the driver is ready so this needs to 801 * be the last thing to be done after everything is initialized 802 * properly. 803 */ 804 platform_set_drvdata(pdev, miic); 805 806 return 0; 807 808 disable_runtime_pm: 809 pm_runtime_put(dev); 810 811 return ret; 812 } 813 814 static void miic_remove(struct platform_device *pdev) 815 { 816 pm_runtime_put(&pdev->dev); 817 } 818 819 static struct miic_of_data rzn1_miic_of_data = { 820 .match_table = modctrl_match_table, 821 .match_table_count = ARRAY_SIZE(modctrl_match_table), 822 .conf_conv_count = MIIC_MODCTRL_CONF_CONV_MAX, 823 .conf_to_string = conf_to_string, 824 .conf_to_string_count = ARRAY_SIZE(conf_to_string), 825 .index_to_string = index_to_string, 826 .index_to_string_count = ARRAY_SIZE(index_to_string), 827 .miic_port_start = 1, 828 .miic_port_max = 5, 829 .sw_mode_mask = GENMASK(4, 0), 830 .init_unlock_lock_regs = true, 831 .miic_write = miic_reg_writel_unlocked, 832 .type = MIIC_TYPE_RZN1, 833 }; 834 835 static struct miic_of_data rzt2h_miic_of_data = { 836 .match_table = rzt2h_modctrl_match_table, 837 .match_table_count = ARRAY_SIZE(rzt2h_modctrl_match_table), 838 .conf_conv_count = 5, 839 .conf_to_string = rzt2h_conf_to_string, 840 .conf_to_string_count = ARRAY_SIZE(rzt2h_conf_to_string), 841 .index_to_string = rzt2h_index_to_string, 842 .index_to_string_count = ARRAY_SIZE(rzt2h_index_to_string), 843 .miic_port_start = 0, 844 .miic_port_max = 4, 845 .sw_mode_mask = GENMASK(2, 0), 846 .reset_ids = rzt2h_reset_ids, 847 .reset_count = ARRAY_SIZE(rzt2h_reset_ids), 848 .miic_write = miic_reg_writel_locked, 849 .type = MIIC_TYPE_RZT2H, 850 }; 851 852 static const struct of_device_id miic_of_mtable[] = { 853 { .compatible = "renesas,r9a09g077-miic", .data = &rzt2h_miic_of_data }, 854 { .compatible = "renesas,rzn1-miic", .data = &rzn1_miic_of_data }, 855 { /* sentinel */ } 856 }; 857 MODULE_DEVICE_TABLE(of, miic_of_mtable); 858 859 static struct platform_driver miic_driver = { 860 .driver = { 861 .name = "rzn1_miic", 862 .suppress_bind_attrs = true, 863 .of_match_table = miic_of_mtable, 864 }, 865 .probe = miic_probe, 866 .remove = miic_remove, 867 }; 868 module_platform_driver(miic_driver); 869 870 MODULE_LICENSE("GPL"); 871 MODULE_DESCRIPTION("Renesas MII converter PCS driver"); 872 MODULE_AUTHOR("Clément Léger <clement.leger@bootlin.com>"); 873