1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * MediaTek MT6359 PMIC AUXADC IIO driver
4 *
5 * Copyright (c) 2021 MediaTek Inc.
6 * Copyright (c) 2024 Collabora Ltd
7 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/cleanup.h>
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/property.h>
17 #include <linux/regmap.h>
18 #include <linux/types.h>
19
20 #include <linux/iio/iio.h>
21
22 #include <linux/mfd/mt6397/core.h>
23
24 #include <dt-bindings/iio/adc/mediatek,mt6357-auxadc.h>
25 #include <dt-bindings/iio/adc/mediatek,mt6358-auxadc.h>
26 #include <dt-bindings/iio/adc/mediatek,mt6359-auxadc.h>
27 #include <dt-bindings/iio/adc/mediatek,mt6363-auxadc.h>
28
29 #define AUXADC_AVG_TIME_US 10
30 #define AUXADC_POLL_DELAY_US 100
31 #define AUXADC_TIMEOUT_US 32000
32 #define IMP_STOP_DELAY_US 150
33 #define IMP_POLL_DELAY_US 1000
34
35 /* For PMIC_RG_RESET_VAL and MT6358_IMP0_CLEAR, the bits specific purpose is unknown. */
36 #define PMIC_RG_RESET_VAL (BIT(0) | BIT(3))
37 #define PMIC_AUXADC_RDY_BIT BIT(15)
38 #define MT6357_IMP_ADC_NUM 30
39 #define MT6358_IMP_ADC_NUM 28
40
41 #define MT6358_DCM_CK_SW_EN GENMASK(1, 0)
42 #define MT6358_IMP0_CLEAR (BIT(14) | BIT(7))
43 #define MT6358_IMP0_IRQ_RDY BIT(8)
44 #define MT6358_IMP1_AUTOREPEAT_EN BIT(15)
45
46 #define MT6359_IMP0_CONV_EN BIT(0)
47 #define MT6359_IMP1_IRQ_RDY BIT(15)
48
49 #define MT6363_EXT_CHAN_MASK GENMASK(2, 0)
50 #define MT6363_EXT_PURES_MASK GENMASK(4, 3)
51 #define MT6363_PULLUP_RES_100K 0
52 #define MT6363_PULLUP_RES_30K 1
53 #define MT6363_PULLUP_RES_OPEN 3
54
55 enum mtk_pmic_auxadc_regs {
56 PMIC_AUXADC_ADC0,
57 PMIC_AUXADC_DCM_CON,
58 PMIC_AUXADC_IMP0,
59 PMIC_AUXADC_IMP1,
60 PMIC_AUXADC_IMP3,
61 PMIC_AUXADC_RQST0,
62 PMIC_AUXADC_RQST1,
63 PMIC_AUXADC_RQST3,
64 PMIC_AUXADC_SDMADC_CON0,
65 PMIC_HK_TOP_WKEY,
66 PMIC_HK_TOP_RST_CON0,
67 PMIC_FGADC_R_CON0,
68 PMIC_AUXADC_REGS_MAX
69 };
70
71 enum mtk_pmic_auxadc_channels {
72 PMIC_AUXADC_CHAN_BATADC,
73 PMIC_AUXADC_CHAN_ISENSE,
74 PMIC_AUXADC_CHAN_VCDT,
75 PMIC_AUXADC_CHAN_BAT_TEMP,
76 PMIC_AUXADC_CHAN_BATID,
77 PMIC_AUXADC_CHAN_CHIP_TEMP,
78 PMIC_AUXADC_CHAN_VCORE_TEMP,
79 PMIC_AUXADC_CHAN_VPROC_TEMP,
80 PMIC_AUXADC_CHAN_VGPU_TEMP,
81 PMIC_AUXADC_CHAN_ACCDET,
82 PMIC_AUXADC_CHAN_VDCXO,
83 PMIC_AUXADC_CHAN_TSX_TEMP,
84 PMIC_AUXADC_CHAN_HPOFS_CAL,
85 PMIC_AUXADC_CHAN_DCXO_TEMP,
86 PMIC_AUXADC_CHAN_VTREF,
87 PMIC_AUXADC_CHAN_VBIF,
88 PMIC_AUXADC_CHAN_VSYSSNS,
89 PMIC_AUXADC_CHAN_VIN1,
90 PMIC_AUXADC_CHAN_VIN2,
91 PMIC_AUXADC_CHAN_VIN3,
92 PMIC_AUXADC_CHAN_VIN4,
93 PMIC_AUXADC_CHAN_VIN5,
94 PMIC_AUXADC_CHAN_VIN6,
95 PMIC_AUXADC_CHAN_VIN7,
96 PMIC_AUXADC_CHAN_IBAT,
97 PMIC_AUXADC_CHAN_VBAT,
98 PMIC_AUXADC_CHAN_MAX
99 };
100
101 /**
102 * struct mt6359_auxadc - Main driver structure
103 * @dev: Device pointer
104 * @regmap: Regmap from SoC PMIC Wrapper
105 * @chip_info: PMIC specific chip info
106 * @lock: Mutex to serialize AUXADC reading vs configuration
107 * @timed_out: Signals whether the last read timed out
108 */
109 struct mt6359_auxadc {
110 struct device *dev;
111 struct regmap *regmap;
112 const struct mtk_pmic_auxadc_info *chip_info;
113 struct mutex lock;
114 bool timed_out;
115 };
116
117 /**
118 * struct mtk_pmic_auxadc_chan - PMIC AUXADC channel data
119 * @req_idx: Request register number
120 * @req_mask: Bitmask to activate a channel
121 * @rdy_idx: Readiness register number
122 * @rdy_mask: Bitmask to determine channel readiness
123 * @ext_sel_idx: PMIC GPIO channel register number
124 * @ext_sel_ch: PMIC GPIO number
125 * @ext_sel_pu: PMIC GPIO channel pullup resistor selector
126 * @num_samples: Number of AUXADC samples for averaging
127 * @r_ratio: Resistance ratio fractional
128 */
129 struct mtk_pmic_auxadc_chan {
130 u8 req_idx;
131 u16 req_mask;
132 u8 rdy_idx;
133 u16 rdy_mask;
134 s8 ext_sel_idx;
135 u8 ext_sel_ch;
136 u8 ext_sel_pu;
137 u16 num_samples;
138 struct u8_fract r_ratio;
139 };
140
141 /**
142 * struct mtk_pmic_auxadc_info - PMIC specific chip info
143 * @model_name: PMIC model name
144 * @channels: IIO specification of ADC channels
145 * @num_channels: Number of ADC channels
146 * @desc: PMIC AUXADC channel data
147 * @regs: List of PMIC specific registers
148 * @sec_unlock_key: Security unlock key for HK_TOP writes
149 * @vref_mV: AUXADC Reference Voltage (VREF) in millivolts
150 * @imp_adc_num: ADC channel for battery impedance readings
151 * @is_spmi: Defines whether this PMIC communicates over SPMI
152 * @no_reset: If true, this PMIC does not support ADC reset
153 * @read_imp: Callback to read impedance channels
154 */
155 struct mtk_pmic_auxadc_info {
156 const char *model_name;
157 const struct iio_chan_spec *channels;
158 u8 num_channels;
159 const struct mtk_pmic_auxadc_chan *desc;
160 const u16 *regs;
161 u16 sec_unlock_key;
162 u32 vref_mV;
163 u8 imp_adc_num;
164 bool is_spmi;
165 bool no_reset;
166 int (*read_imp)(struct mt6359_auxadc *adc_dev,
167 const struct iio_chan_spec *chan, int *vbat, int *ibat);
168 };
169
170 #define MTK_PMIC_ADC_EXT_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \
171 _ext_sel_idx, _ext_sel_ch, _ext_sel_pu, \
172 _samples, _rnum, _rdiv) \
173 [PMIC_AUXADC_CHAN_##_ch_idx] = { \
174 .req_idx = _req_idx, \
175 .req_mask = BIT(_req_bit), \
176 .rdy_idx = _rdy_idx, \
177 .rdy_mask = BIT(_rdy_bit), \
178 .ext_sel_idx = _ext_sel_idx, \
179 .ext_sel_ch = _ext_sel_ch, \
180 .ext_sel_pu = _ext_sel_pu, \
181 .num_samples = _samples, \
182 .r_ratio = { _rnum, _rdiv } \
183 }
184
185 #define MTK_PMIC_ADC_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \
186 _samples, _rnum, _rdiv) \
187 MTK_PMIC_ADC_EXT_CHAN(_ch_idx, _req_idx, _req_bit, _rdy_idx, _rdy_bit, \
188 -1, 0, 0, _samples, _rnum, _rdiv)
189
190 #define MTK_PMIC_IIO_CHAN(_model, _name, _ch_idx, _adc_idx, _nbits, _ch_type) \
191 { \
192 .type = _ch_type, \
193 .channel = _model##_AUXADC_##_ch_idx, \
194 .address = _adc_idx, \
195 .scan_index = PMIC_AUXADC_CHAN_##_ch_idx, \
196 .datasheet_name = __stringify(_name), \
197 .scan_type = { \
198 .sign = 'u', \
199 .realbits = _nbits, \
200 .storagebits = 16, \
201 .endianness = IIO_CPU \
202 }, \
203 .indexed = 1, \
204 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE) \
205 }
206
207 static const struct iio_chan_spec mt6357_auxadc_channels[] = {
208 MTK_PMIC_IIO_CHAN(MT6357, bat_adc, BATADC, 0, 15, IIO_RESISTANCE),
209 MTK_PMIC_IIO_CHAN(MT6357, isense, ISENSE, 1, 12, IIO_CURRENT),
210 MTK_PMIC_IIO_CHAN(MT6357, cdt_v, VCDT, 2, 12, IIO_TEMP),
211 MTK_PMIC_IIO_CHAN(MT6357, batt_temp, BAT_TEMP, 3, 12, IIO_TEMP),
212 MTK_PMIC_IIO_CHAN(MT6357, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP),
213 MTK_PMIC_IIO_CHAN(MT6357, acc_det, ACCDET, 5, 12, IIO_RESISTANCE),
214 MTK_PMIC_IIO_CHAN(MT6357, dcxo_v, VDCXO, 6, 12, IIO_VOLTAGE),
215 MTK_PMIC_IIO_CHAN(MT6357, tsx_temp, TSX_TEMP, 7, 15, IIO_TEMP),
216 MTK_PMIC_IIO_CHAN(MT6357, hp_ofs_cal, HPOFS_CAL, 9, 15, IIO_RESISTANCE),
217 MTK_PMIC_IIO_CHAN(MT6357, dcxo_temp, DCXO_TEMP, 36, 15, IIO_TEMP),
218 MTK_PMIC_IIO_CHAN(MT6357, vcore_temp, VCORE_TEMP, 40, 12, IIO_TEMP),
219 MTK_PMIC_IIO_CHAN(MT6357, vproc_temp, VPROC_TEMP, 41, 12, IIO_TEMP),
220
221 /* Battery impedance channels */
222 MTK_PMIC_IIO_CHAN(MT6357, batt_v, VBAT, 0, 15, IIO_VOLTAGE),
223 };
224
225 static const struct mtk_pmic_auxadc_chan mt6357_auxadc_ch_desc[] = {
226 MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1),
227 MTK_PMIC_ADC_CHAN(ISENSE, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1),
228 MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
229 MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
230 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
231 MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
232 MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 128, 1, 1),
233 MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 256, 1, 1),
234 MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, 16, 1, 1),
235 MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
236 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
237 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 6, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
238
239 /* Battery impedance channels */
240 MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1),
241 };
242
243 static const u16 mt6357_auxadc_regs[] = {
244 [PMIC_HK_TOP_RST_CON0] = 0x0f90,
245 [PMIC_AUXADC_DCM_CON] = 0x122e,
246 [PMIC_AUXADC_ADC0] = 0x1088,
247 [PMIC_AUXADC_IMP0] = 0x119c,
248 [PMIC_AUXADC_IMP1] = 0x119e,
249 [PMIC_AUXADC_RQST0] = 0x110e,
250 [PMIC_AUXADC_RQST1] = 0x1114,
251 };
252
253 static const struct iio_chan_spec mt6358_auxadc_channels[] = {
254 MTK_PMIC_IIO_CHAN(MT6358, bat_adc, BATADC, 0, 15, IIO_RESISTANCE),
255 MTK_PMIC_IIO_CHAN(MT6358, cdt_v, VCDT, 2, 12, IIO_TEMP),
256 MTK_PMIC_IIO_CHAN(MT6358, batt_temp, BAT_TEMP, 3, 12, IIO_TEMP),
257 MTK_PMIC_IIO_CHAN(MT6358, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP),
258 MTK_PMIC_IIO_CHAN(MT6358, acc_det, ACCDET, 5, 12, IIO_RESISTANCE),
259 MTK_PMIC_IIO_CHAN(MT6358, dcxo_v, VDCXO, 6, 12, IIO_VOLTAGE),
260 MTK_PMIC_IIO_CHAN(MT6358, tsx_temp, TSX_TEMP, 7, 15, IIO_TEMP),
261 MTK_PMIC_IIO_CHAN(MT6358, hp_ofs_cal, HPOFS_CAL, 9, 15, IIO_RESISTANCE),
262 MTK_PMIC_IIO_CHAN(MT6358, dcxo_temp, DCXO_TEMP, 10, 15, IIO_TEMP),
263 MTK_PMIC_IIO_CHAN(MT6358, bif_v, VBIF, 11, 12, IIO_VOLTAGE),
264 MTK_PMIC_IIO_CHAN(MT6358, vcore_temp, VCORE_TEMP, 38, 12, IIO_TEMP),
265 MTK_PMIC_IIO_CHAN(MT6358, vproc_temp, VPROC_TEMP, 39, 12, IIO_TEMP),
266 MTK_PMIC_IIO_CHAN(MT6358, vgpu_temp, VGPU_TEMP, 40, 12, IIO_TEMP),
267
268 /* Battery impedance channels */
269 MTK_PMIC_IIO_CHAN(MT6358, batt_v, VBAT, 0, 15, IIO_VOLTAGE),
270 };
271
272 static const struct mtk_pmic_auxadc_chan mt6358_auxadc_ch_desc[] = {
273 MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 128, 3, 1),
274 MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
275 MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP0, 8, 8, 2, 1),
276 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
277 MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
278 MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP0, 8, 8, 3, 2),
279 MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP0, 8, 128, 1, 1),
280 MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP0, 8, 256, 1, 1),
281 MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP0, 8, 16, 1, 1),
282 MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP0, 8, 8, 2, 1),
283 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
284 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
285 MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP0, 8, 8, 1, 1),
286
287 /* Battery impedance channels */
288 MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP0, 8, 128, 7, 2),
289 };
290
291 static const u16 mt6358_auxadc_regs[] = {
292 [PMIC_HK_TOP_RST_CON0] = 0x0f90,
293 [PMIC_AUXADC_DCM_CON] = 0x1260,
294 [PMIC_AUXADC_ADC0] = 0x1088,
295 [PMIC_AUXADC_IMP0] = 0x1208,
296 [PMIC_AUXADC_IMP1] = 0x120a,
297 [PMIC_AUXADC_RQST0] = 0x1108,
298 [PMIC_AUXADC_RQST1] = 0x110a,
299 };
300
301 static const struct iio_chan_spec mt6359_auxadc_channels[] = {
302 MTK_PMIC_IIO_CHAN(MT6359, bat_adc, BATADC, 0, 15, IIO_RESISTANCE),
303 MTK_PMIC_IIO_CHAN(MT6359, batt_temp, BAT_TEMP, 3, 12, IIO_TEMP),
304 MTK_PMIC_IIO_CHAN(MT6359, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP),
305 MTK_PMIC_IIO_CHAN(MT6359, acc_det, ACCDET, 5, 12, IIO_RESISTANCE),
306 MTK_PMIC_IIO_CHAN(MT6359, dcxo_v, VDCXO, 6, 12, IIO_VOLTAGE),
307 MTK_PMIC_IIO_CHAN(MT6359, tsx_temp, TSX_TEMP, 7, 15, IIO_TEMP),
308 MTK_PMIC_IIO_CHAN(MT6359, hp_ofs_cal, HPOFS_CAL, 9, 15, IIO_RESISTANCE),
309 MTK_PMIC_IIO_CHAN(MT6359, dcxo_temp, DCXO_TEMP, 10, 15, IIO_TEMP),
310 MTK_PMIC_IIO_CHAN(MT6359, bif_v, VBIF, 11, 12, IIO_VOLTAGE),
311 MTK_PMIC_IIO_CHAN(MT6359, vcore_temp, VCORE_TEMP, 30, 12, IIO_TEMP),
312 MTK_PMIC_IIO_CHAN(MT6359, vproc_temp, VPROC_TEMP, 31, 12, IIO_TEMP),
313 MTK_PMIC_IIO_CHAN(MT6359, vgpu_temp, VGPU_TEMP, 32, 12, IIO_TEMP),
314
315 /* Battery impedance channels */
316 MTK_PMIC_IIO_CHAN(MT6359, batt_v, VBAT, 0, 15, IIO_VOLTAGE),
317 MTK_PMIC_IIO_CHAN(MT6359, batt_i, IBAT, 0, 15, IIO_CURRENT),
318 };
319
320 static const struct mtk_pmic_auxadc_chan mt6359_auxadc_ch_desc[] = {
321 MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2),
322 MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_IMP1, 15, 8, 5, 2),
323 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_IMP1, 15, 8, 1, 1),
324 MTK_PMIC_ADC_CHAN(ACCDET, PMIC_AUXADC_RQST0, 5, PMIC_AUXADC_IMP1, 15, 8, 1, 1),
325 MTK_PMIC_ADC_CHAN(VDCXO, PMIC_AUXADC_RQST0, 6, PMIC_AUXADC_IMP1, 15, 8, 3, 2),
326 MTK_PMIC_ADC_CHAN(TSX_TEMP, PMIC_AUXADC_RQST0, 7, PMIC_AUXADC_IMP1, 15, 128, 1, 1),
327 MTK_PMIC_ADC_CHAN(HPOFS_CAL, PMIC_AUXADC_RQST0, 9, PMIC_AUXADC_IMP1, 15, 256, 1, 1),
328 MTK_PMIC_ADC_CHAN(DCXO_TEMP, PMIC_AUXADC_RQST0, 10, PMIC_AUXADC_IMP1, 15, 16, 1, 1),
329 MTK_PMIC_ADC_CHAN(VBIF, PMIC_AUXADC_RQST0, 11, PMIC_AUXADC_IMP1, 15, 8, 5, 2),
330 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST1, 8, PMIC_AUXADC_IMP1, 15, 8, 1, 1),
331 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST1, 9, PMIC_AUXADC_IMP1, 15, 8, 1, 1),
332 MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST1, 10, PMIC_AUXADC_IMP1, 15, 8, 1, 1),
333
334 /* Battery impedance channels */
335 MTK_PMIC_ADC_CHAN(VBAT, 0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2),
336 MTK_PMIC_ADC_CHAN(IBAT, 0, 0, PMIC_AUXADC_IMP1, 15, 128, 7, 2),
337 };
338
339 static const u16 mt6359_auxadc_regs[] = {
340 [PMIC_FGADC_R_CON0] = 0x0d88,
341 [PMIC_HK_TOP_WKEY] = 0x0fb4,
342 [PMIC_HK_TOP_RST_CON0] = 0x0f90,
343 [PMIC_AUXADC_RQST0] = 0x1108,
344 [PMIC_AUXADC_RQST1] = 0x110a,
345 [PMIC_AUXADC_ADC0] = 0x1088,
346 [PMIC_AUXADC_IMP0] = 0x1208,
347 [PMIC_AUXADC_IMP1] = 0x120a,
348 [PMIC_AUXADC_IMP3] = 0x120e,
349 };
350
351 static const struct iio_chan_spec mt6363_auxadc_channels[] = {
352 MTK_PMIC_IIO_CHAN(MT6363, bat_adc, BATADC, 0, 15, IIO_RESISTANCE),
353 MTK_PMIC_IIO_CHAN(MT6363, cdt_v, VCDT, 2, 12, IIO_TEMP),
354 MTK_PMIC_IIO_CHAN(MT6363, batt_temp, BAT_TEMP, 3, 12, IIO_TEMP),
355 MTK_PMIC_IIO_CHAN(MT6363, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP),
356 MTK_PMIC_IIO_CHAN(MT6363, sys_sns_v, VSYSSNS, 6, 15, IIO_VOLTAGE),
357 MTK_PMIC_IIO_CHAN(MT6363, tref_v, VTREF, 11, 12, IIO_VOLTAGE),
358 MTK_PMIC_IIO_CHAN(MT6363, vcore_temp, VCORE_TEMP, 38, 12, IIO_TEMP),
359 MTK_PMIC_IIO_CHAN(MT6363, vproc_temp, VPROC_TEMP, 39, 12, IIO_TEMP),
360 MTK_PMIC_IIO_CHAN(MT6363, vgpu_temp, VGPU_TEMP, 40, 12, IIO_TEMP),
361
362 /* For VIN, ADC12 holds the result depending on which GPIO was activated */
363 MTK_PMIC_IIO_CHAN(MT6363, in1_v, VIN1, 45, 15, IIO_VOLTAGE),
364 MTK_PMIC_IIO_CHAN(MT6363, in2_v, VIN2, 45, 15, IIO_VOLTAGE),
365 MTK_PMIC_IIO_CHAN(MT6363, in3_v, VIN3, 45, 15, IIO_VOLTAGE),
366 MTK_PMIC_IIO_CHAN(MT6363, in4_v, VIN4, 45, 15, IIO_VOLTAGE),
367 MTK_PMIC_IIO_CHAN(MT6363, in5_v, VIN5, 45, 15, IIO_VOLTAGE),
368 MTK_PMIC_IIO_CHAN(MT6363, in6_v, VIN6, 45, 15, IIO_VOLTAGE),
369 MTK_PMIC_IIO_CHAN(MT6363, in7_v, VIN7, 45, 15, IIO_VOLTAGE),
370 };
371
372 static const struct mtk_pmic_auxadc_chan mt6363_auxadc_ch_desc[] = {
373 MTK_PMIC_ADC_CHAN(BATADC, PMIC_AUXADC_RQST0, 0, PMIC_AUXADC_ADC0, 15, 64, 4, 1),
374 MTK_PMIC_ADC_CHAN(VCDT, PMIC_AUXADC_RQST0, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
375 MTK_PMIC_ADC_CHAN(BAT_TEMP, PMIC_AUXADC_RQST0, 3, PMIC_AUXADC_ADC0, 15, 32, 3, 2),
376 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
377 MTK_PMIC_ADC_CHAN(VSYSSNS, PMIC_AUXADC_RQST1, 6, PMIC_AUXADC_ADC0, 15, 64, 3, 1),
378 MTK_PMIC_ADC_CHAN(VTREF, PMIC_AUXADC_RQST1, 3, PMIC_AUXADC_ADC0, 15, 32, 3, 2),
379 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST3, 0, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
380 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST3, 1, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
381 MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST3, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
382
383 MTK_PMIC_ADC_EXT_CHAN(VIN1,
384 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
385 PMIC_AUXADC_SDMADC_CON0, 1, MT6363_PULLUP_RES_100K, 32, 1, 1),
386 MTK_PMIC_ADC_EXT_CHAN(VIN2,
387 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
388 PMIC_AUXADC_SDMADC_CON0, 2, MT6363_PULLUP_RES_100K, 32, 1, 1),
389 MTK_PMIC_ADC_EXT_CHAN(VIN3,
390 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
391 PMIC_AUXADC_SDMADC_CON0, 3, MT6363_PULLUP_RES_100K, 32, 1, 1),
392 MTK_PMIC_ADC_EXT_CHAN(VIN4,
393 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
394 PMIC_AUXADC_SDMADC_CON0, 4, MT6363_PULLUP_RES_100K, 32, 1, 1),
395 MTK_PMIC_ADC_EXT_CHAN(VIN5,
396 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
397 PMIC_AUXADC_SDMADC_CON0, 5, MT6363_PULLUP_RES_100K, 32, 1, 1),
398 MTK_PMIC_ADC_EXT_CHAN(VIN6,
399 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
400 PMIC_AUXADC_SDMADC_CON0, 6, MT6363_PULLUP_RES_100K, 32, 1, 1),
401 MTK_PMIC_ADC_EXT_CHAN(VIN7,
402 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
403 PMIC_AUXADC_SDMADC_CON0, 7, MT6363_PULLUP_RES_100K, 32, 1, 1),
404 };
405
406 static const u16 mt6363_auxadc_regs[] = {
407 [PMIC_AUXADC_RQST0] = 0x1108,
408 [PMIC_AUXADC_RQST1] = 0x1109,
409 [PMIC_AUXADC_RQST3] = 0x110c,
410 [PMIC_AUXADC_ADC0] = 0x1088,
411 [PMIC_AUXADC_IMP0] = 0x1208,
412 [PMIC_AUXADC_IMP1] = 0x1209,
413 };
414
415 static const struct iio_chan_spec mt6373_auxadc_channels[] = {
416 MTK_PMIC_IIO_CHAN(MT6363, chip_temp, CHIP_TEMP, 4, 12, IIO_TEMP),
417 MTK_PMIC_IIO_CHAN(MT6363, vcore_temp, VCORE_TEMP, 38, 12, IIO_TEMP),
418 MTK_PMIC_IIO_CHAN(MT6363, vproc_temp, VPROC_TEMP, 39, 12, IIO_TEMP),
419 MTK_PMIC_IIO_CHAN(MT6363, vgpu_temp, VGPU_TEMP, 40, 12, IIO_TEMP),
420
421 /* For VIN, ADC12 holds the result depending on which GPIO was activated */
422 MTK_PMIC_IIO_CHAN(MT6363, in1_v, VIN1, 45, 15, IIO_VOLTAGE),
423 MTK_PMIC_IIO_CHAN(MT6363, in2_v, VIN2, 45, 15, IIO_VOLTAGE),
424 MTK_PMIC_IIO_CHAN(MT6363, in3_v, VIN3, 45, 15, IIO_VOLTAGE),
425 MTK_PMIC_IIO_CHAN(MT6363, in4_v, VIN4, 45, 15, IIO_VOLTAGE),
426 MTK_PMIC_IIO_CHAN(MT6363, in5_v, VIN5, 45, 15, IIO_VOLTAGE),
427 };
428
429 static const struct mtk_pmic_auxadc_chan mt6373_auxadc_ch_desc[] = {
430 MTK_PMIC_ADC_CHAN(CHIP_TEMP, PMIC_AUXADC_RQST0, 4, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
431 MTK_PMIC_ADC_CHAN(VCORE_TEMP, PMIC_AUXADC_RQST3, 0, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
432 MTK_PMIC_ADC_CHAN(VPROC_TEMP, PMIC_AUXADC_RQST3, 1, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
433 MTK_PMIC_ADC_CHAN(VGPU_TEMP, PMIC_AUXADC_RQST3, 2, PMIC_AUXADC_ADC0, 15, 32, 1, 1),
434
435 MTK_PMIC_ADC_EXT_CHAN(VIN1,
436 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
437 PMIC_AUXADC_SDMADC_CON0, 1, MT6363_PULLUP_RES_30K, 32, 1, 1),
438 MTK_PMIC_ADC_EXT_CHAN(VIN2,
439 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
440 PMIC_AUXADC_SDMADC_CON0, 2, MT6363_PULLUP_RES_OPEN, 32, 1, 1),
441 MTK_PMIC_ADC_EXT_CHAN(VIN3,
442 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
443 PMIC_AUXADC_SDMADC_CON0, 3, MT6363_PULLUP_RES_OPEN, 32, 1, 1),
444 MTK_PMIC_ADC_EXT_CHAN(VIN4,
445 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
446 PMIC_AUXADC_SDMADC_CON0, 4, MT6363_PULLUP_RES_OPEN, 32, 1, 1),
447 MTK_PMIC_ADC_EXT_CHAN(VIN5,
448 PMIC_AUXADC_RQST1, 4, PMIC_AUXADC_ADC0, 15,
449 PMIC_AUXADC_SDMADC_CON0, 5, MT6363_PULLUP_RES_OPEN, 32, 1, 1),
450 };
451
mt6358_stop_imp_conv(struct mt6359_auxadc * adc_dev)452 static void mt6358_stop_imp_conv(struct mt6359_auxadc *adc_dev)
453 {
454 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info;
455 struct regmap *regmap = adc_dev->regmap;
456
457 regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6358_IMP0_CLEAR);
458 regmap_clear_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6358_IMP0_CLEAR);
459 regmap_clear_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP1], MT6358_IMP1_AUTOREPEAT_EN);
460 regmap_clear_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK_SW_EN);
461 }
462
mt6358_start_imp_conv(struct mt6359_auxadc * adc_dev,const struct iio_chan_spec * chan)463 static int mt6358_start_imp_conv(struct mt6359_auxadc *adc_dev, const struct iio_chan_spec *chan)
464 {
465 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info;
466 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index];
467 struct regmap *regmap = adc_dev->regmap;
468 u32 val;
469 int ret;
470
471 regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_DCM_CON], MT6358_DCM_CK_SW_EN);
472 regmap_set_bits(regmap, cinfo->regs[PMIC_AUXADC_IMP1], MT6358_IMP1_AUTOREPEAT_EN);
473
474 ret = regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx],
475 val, val & desc->rdy_mask,
476 IMP_POLL_DELAY_US, AUXADC_TIMEOUT_US);
477 if (ret) {
478 mt6358_stop_imp_conv(adc_dev);
479 return ret;
480 }
481
482 return 0;
483 }
484
mt6358_read_imp(struct mt6359_auxadc * adc_dev,const struct iio_chan_spec * chan,int * vbat,int * ibat)485 static int mt6358_read_imp(struct mt6359_auxadc *adc_dev,
486 const struct iio_chan_spec *chan, int *vbat, int *ibat)
487 {
488 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info;
489 struct regmap *regmap = adc_dev->regmap;
490 u16 reg_adc0 = cinfo->regs[PMIC_AUXADC_ADC0];
491 u32 val_v;
492 int ret;
493
494 ret = mt6358_start_imp_conv(adc_dev, chan);
495 if (ret)
496 return ret;
497
498 /* Read the params before stopping */
499 val_v = 0;
500 regmap_read(regmap, reg_adc0 + (cinfo->imp_adc_num << 1), &val_v);
501
502 mt6358_stop_imp_conv(adc_dev);
503
504 if (vbat)
505 *vbat = val_v;
506 if (ibat)
507 *ibat = 0;
508
509 return 0;
510 }
511
mt6359_read_imp(struct mt6359_auxadc * adc_dev,const struct iio_chan_spec * chan,int * vbat,int * ibat)512 static int mt6359_read_imp(struct mt6359_auxadc *adc_dev,
513 const struct iio_chan_spec *chan, int *vbat, int *ibat)
514 {
515 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info;
516 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index];
517 struct regmap *regmap = adc_dev->regmap;
518 u32 val, val_v, val_i;
519 int ret;
520
521 /* Start conversion */
522 regmap_write(regmap, cinfo->regs[PMIC_AUXADC_IMP0], MT6359_IMP0_CONV_EN);
523 ret = regmap_read_poll_timeout(regmap, cinfo->regs[desc->rdy_idx],
524 val, val & desc->rdy_mask,
525 IMP_POLL_DELAY_US, AUXADC_TIMEOUT_US);
526
527 /* Stop conversion regardless of the result */
528 regmap_write(regmap, cinfo->regs[PMIC_AUXADC_IMP0], 0);
529 if (ret)
530 return ret;
531
532 /* If it succeeded, wait for the registers to be populated */
533 fsleep(IMP_STOP_DELAY_US);
534
535 ret = regmap_read(regmap, cinfo->regs[PMIC_AUXADC_IMP3], &val_v);
536 if (ret)
537 return ret;
538
539 ret = regmap_read(regmap, cinfo->regs[PMIC_FGADC_R_CON0], &val_i);
540 if (ret)
541 return ret;
542
543 if (vbat)
544 *vbat = val_v;
545 if (ibat)
546 *ibat = val_i;
547
548 return 0;
549 }
550
551 static const struct mtk_pmic_auxadc_info mt6357_chip_info = {
552 .model_name = "MT6357",
553 .channels = mt6357_auxadc_channels,
554 .num_channels = ARRAY_SIZE(mt6357_auxadc_channels),
555 .desc = mt6357_auxadc_ch_desc,
556 .regs = mt6357_auxadc_regs,
557 .imp_adc_num = MT6357_IMP_ADC_NUM,
558 .read_imp = mt6358_read_imp,
559 .vref_mV = 1800,
560 };
561
562 static const struct mtk_pmic_auxadc_info mt6358_chip_info = {
563 .model_name = "MT6358",
564 .channels = mt6358_auxadc_channels,
565 .num_channels = ARRAY_SIZE(mt6358_auxadc_channels),
566 .desc = mt6358_auxadc_ch_desc,
567 .regs = mt6358_auxadc_regs,
568 .imp_adc_num = MT6358_IMP_ADC_NUM,
569 .read_imp = mt6358_read_imp,
570 .vref_mV = 1800,
571 };
572
573 static const struct mtk_pmic_auxadc_info mt6359_chip_info = {
574 .model_name = "MT6359",
575 .channels = mt6359_auxadc_channels,
576 .num_channels = ARRAY_SIZE(mt6359_auxadc_channels),
577 .desc = mt6359_auxadc_ch_desc,
578 .regs = mt6359_auxadc_regs,
579 .sec_unlock_key = 0x6359,
580 .read_imp = mt6359_read_imp,
581 .vref_mV = 1800,
582 };
583
584 static const struct mtk_pmic_auxadc_info mt6363_chip_info = {
585 .model_name = "MT6363",
586 .channels = mt6363_auxadc_channels,
587 .num_channels = ARRAY_SIZE(mt6363_auxadc_channels),
588 .desc = mt6363_auxadc_ch_desc,
589 .regs = mt6363_auxadc_regs,
590 .is_spmi = true,
591 .no_reset = true,
592 .vref_mV = 1840,
593 };
594
595 static const struct mtk_pmic_auxadc_info mt6373_chip_info = {
596 .model_name = "MT6373",
597 .channels = mt6373_auxadc_channels,
598 .num_channels = ARRAY_SIZE(mt6373_auxadc_channels),
599 .desc = mt6373_auxadc_ch_desc,
600 .regs = mt6363_auxadc_regs,
601 .is_spmi = true,
602 .no_reset = true,
603 .vref_mV = 1840,
604 };
605
mt6359_auxadc_reset(struct mt6359_auxadc * adc_dev)606 static void mt6359_auxadc_reset(struct mt6359_auxadc *adc_dev)
607 {
608 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info;
609 struct regmap *regmap = adc_dev->regmap;
610
611 /* Some PMICs do not support reset */
612 if (cinfo->no_reset)
613 return;
614
615 /* Unlock HK_TOP writes */
616 if (cinfo->sec_unlock_key)
617 regmap_write(regmap, cinfo->regs[PMIC_HK_TOP_WKEY], cinfo->sec_unlock_key);
618
619 /* Assert ADC reset */
620 regmap_set_bits(regmap, cinfo->regs[PMIC_HK_TOP_RST_CON0], PMIC_RG_RESET_VAL);
621
622 /* De-assert ADC reset. No wait required, as pwrap takes care of that for us. */
623 regmap_clear_bits(regmap, cinfo->regs[PMIC_HK_TOP_RST_CON0], PMIC_RG_RESET_VAL);
624
625 /* Lock HK_TOP writes again */
626 if (cinfo->sec_unlock_key)
627 regmap_write(regmap, cinfo->regs[PMIC_HK_TOP_WKEY], 0);
628 }
629
630 /**
631 * mt6359_auxadc_sample_adc_val() - Start ADC channel sampling and read value
632 * @adc_dev: Main driver structure
633 * @chan: IIO Channel spec for requested ADC
634 * @out: Preallocated variable to store the value read from HW
635 *
636 * This function starts the sampling for an ADC channel, waits until all
637 * of the samples are averaged and then reads the value from the HW.
638 *
639 * Note that the caller must stop the ADC sampling on its own, as this
640 * function *never* stops it.
641 *
642 * Return:
643 * Negative number for error;
644 * Upon success returns zero and writes the read value to *out.
645 */
mt6359_auxadc_sample_adc_val(struct mt6359_auxadc * adc_dev,const struct iio_chan_spec * chan,u32 * out)646 static int mt6359_auxadc_sample_adc_val(struct mt6359_auxadc *adc_dev,
647 const struct iio_chan_spec *chan, u32 *out)
648 {
649 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info;
650 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index];
651 struct regmap *regmap = adc_dev->regmap;
652 u32 reg, rdy_mask, val, lval;
653 int ret;
654
655 /* Request to start sampling for ADC channel */
656 ret = regmap_write(regmap, cinfo->regs[desc->req_idx], desc->req_mask);
657 if (ret)
658 return ret;
659
660 /* Wait until all samples are averaged */
661 fsleep(desc->num_samples * AUXADC_AVG_TIME_US);
662
663 reg = cinfo->regs[PMIC_AUXADC_ADC0] + (chan->address << 1);
664 rdy_mask = PMIC_AUXADC_RDY_BIT;
665
666 /*
667 * Even though for both PWRAP and SPMI cases the ADC HW signals that
668 * the data is ready by setting AUXADC_RDY_BIT, for SPMI the register
669 * read is only 8 bits long: for this case, the check has to be done
670 * on the ADC(x)_H register (high bits) and the rdy_mask needs to be
671 * shifted to the right by the same 8 bits.
672 */
673 if (cinfo->is_spmi) {
674 rdy_mask >>= 8;
675 reg += 1;
676 }
677
678 ret = regmap_read_poll_timeout(regmap, reg, val, val & rdy_mask,
679 AUXADC_POLL_DELAY_US, AUXADC_TIMEOUT_US);
680 if (ret) {
681 dev_dbg(adc_dev->dev, "ADC read timeout for chan %lu\n", chan->address);
682 return ret;
683 }
684
685 if (cinfo->is_spmi) {
686 ret = regmap_read(regmap, reg - 1, &lval);
687 if (ret)
688 return ret;
689
690 val = (val << 8) | lval;
691 }
692
693 *out = val;
694 return 0;
695 }
696
mt6359_auxadc_read_adc(struct mt6359_auxadc * adc_dev,const struct iio_chan_spec * chan,int * out)697 static int mt6359_auxadc_read_adc(struct mt6359_auxadc *adc_dev,
698 const struct iio_chan_spec *chan, int *out)
699 {
700 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info;
701 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index];
702 struct regmap *regmap = adc_dev->regmap;
703 int ret, adc_stop_err;
704 u8 ext_sel;
705 u32 val;
706
707 if (desc->ext_sel_idx >= 0) {
708 ext_sel = FIELD_PREP(MT6363_EXT_PURES_MASK, desc->ext_sel_pu);
709 ext_sel |= FIELD_PREP(MT6363_EXT_CHAN_MASK, desc->ext_sel_ch);
710
711 ret = regmap_update_bits(regmap, cinfo->regs[desc->ext_sel_idx],
712 MT6363_EXT_PURES_MASK | MT6363_EXT_CHAN_MASK,
713 ext_sel);
714 if (ret)
715 return ret;
716 }
717
718 /*
719 * Get sampled value, then stop sampling unconditionally; the gathered
720 * value is good regardless of if the ADC could be stopped.
721 *
722 * Note that if the ADC cannot be stopped but sampling was ok, this
723 * function will not return any error, but will set the timed_out
724 * status: this is not critical, as the ADC may auto recover and auto
725 * stop after some time (depending on the PMIC model); if not, the next
726 * read attempt will return -ETIMEDOUT and, for models that support it,
727 * reset will be triggered.
728 */
729 ret = mt6359_auxadc_sample_adc_val(adc_dev, chan, &val);
730
731 adc_stop_err = regmap_write(regmap, cinfo->regs[desc->req_idx], 0);
732 if (adc_stop_err) {
733 dev_warn(adc_dev->dev, "Could not stop the ADC: %d\n,", adc_stop_err);
734 adc_dev->timed_out = true;
735 }
736
737 /* If any sampling error occurred, the retrieved value is invalid */
738 if (ret)
739 return ret;
740
741 /* ...and deactivate the ADC GPIO if previously done */
742 if (desc->ext_sel_idx >= 0) {
743 ext_sel = FIELD_PREP(MT6363_EXT_PURES_MASK, MT6363_PULLUP_RES_OPEN);
744
745 ret = regmap_update_bits(regmap, cinfo->regs[desc->ext_sel_idx],
746 MT6363_EXT_PURES_MASK, ext_sel);
747 if (ret)
748 return ret;
749 }
750
751 /* Everything went fine, give back the ADC reading */
752 *out = val & GENMASK(chan->scan_type.realbits - 1, 0);
753 return 0;
754 }
755
mt6359_auxadc_read_label(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,char * label)756 static int mt6359_auxadc_read_label(struct iio_dev *indio_dev,
757 const struct iio_chan_spec *chan, char *label)
758 {
759 return sysfs_emit(label, "%s\n", chan->datasheet_name);
760 }
761
mt6359_auxadc_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long mask)762 static int mt6359_auxadc_read_raw(struct iio_dev *indio_dev,
763 const struct iio_chan_spec *chan,
764 int *val, int *val2, long mask)
765 {
766 struct mt6359_auxadc *adc_dev = iio_priv(indio_dev);
767 const struct mtk_pmic_auxadc_info *cinfo = adc_dev->chip_info;
768 const struct mtk_pmic_auxadc_chan *desc = &cinfo->desc[chan->scan_index];
769 int ret;
770
771 if (mask == IIO_CHAN_INFO_SCALE) {
772 *val = desc->r_ratio.numerator * cinfo->vref_mV;
773
774 if (desc->r_ratio.denominator > 1) {
775 *val2 = desc->r_ratio.denominator;
776 return IIO_VAL_FRACTIONAL;
777 }
778
779 return IIO_VAL_INT;
780 }
781
782 scoped_guard(mutex, &adc_dev->lock) {
783 switch (chan->scan_index) {
784 case PMIC_AUXADC_CHAN_IBAT:
785 if (!adc_dev->chip_info->read_imp)
786 return -EOPNOTSUPP;
787
788 ret = adc_dev->chip_info->read_imp(adc_dev, chan, NULL, val);
789 break;
790 case PMIC_AUXADC_CHAN_VBAT:
791 if (!adc_dev->chip_info->read_imp)
792 return -EOPNOTSUPP;
793
794 ret = adc_dev->chip_info->read_imp(adc_dev, chan, val, NULL);
795 break;
796 default:
797 ret = mt6359_auxadc_read_adc(adc_dev, chan, val);
798 break;
799 }
800 }
801
802 if (ret) {
803 /*
804 * If we get more than one timeout, it's possible that the
805 * AUXADC is stuck: perform a full reset to recover it.
806 */
807 if (ret == -ETIMEDOUT) {
808 if (adc_dev->timed_out) {
809 dev_warn(adc_dev->dev, "Resetting stuck ADC!\r\n");
810 mt6359_auxadc_reset(adc_dev);
811 }
812 adc_dev->timed_out = true;
813 }
814 return ret;
815 }
816 adc_dev->timed_out = false;
817
818 return IIO_VAL_INT;
819 }
820
821 static const struct iio_info mt6359_auxadc_iio_info = {
822 .read_label = mt6359_auxadc_read_label,
823 .read_raw = mt6359_auxadc_read_raw,
824 };
825
mt6359_auxadc_probe(struct platform_device * pdev)826 static int mt6359_auxadc_probe(struct platform_device *pdev)
827 {
828 const struct mtk_pmic_auxadc_info *chip_info;
829 struct device *dev = &pdev->dev;
830 struct device *mfd_dev = dev->parent;
831 struct mt6359_auxadc *adc_dev;
832 struct iio_dev *indio_dev;
833 struct device *regmap_dev;
834 struct regmap *regmap;
835 int ret;
836
837 chip_info = device_get_match_data(dev);
838 if (!chip_info)
839 return -EINVAL;
840 /*
841 * The regmap for this device has to be acquired differently for
842 * SoC PMIC Wrapper and SPMI PMIC cases:
843 *
844 * If this is under SPMI, the regmap comes from the direct parent of
845 * this driver: this_device->parent(mfd).
846 * ... or ...
847 * If this is under the SoC PMIC Wrapper, the regmap comes from the
848 * parent of the MT6397 MFD: this_device->parent(mfd)->parent(pwrap)
849 */
850 if (chip_info->is_spmi)
851 regmap_dev = mfd_dev;
852 else
853 regmap_dev = mfd_dev->parent;
854
855
856 /* Regmap is from SoC PMIC Wrapper, parent of the mt6397 MFD */
857 regmap = dev_get_regmap(regmap_dev, NULL);
858 if (!regmap)
859 return dev_err_probe(dev, -ENODEV, "Failed to get regmap\n");
860
861 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc_dev));
862 if (!indio_dev)
863 return -ENOMEM;
864
865 adc_dev = iio_priv(indio_dev);
866 adc_dev->regmap = regmap;
867 adc_dev->dev = dev;
868 adc_dev->chip_info = chip_info;
869
870 mutex_init(&adc_dev->lock);
871
872 mt6359_auxadc_reset(adc_dev);
873
874 indio_dev->name = adc_dev->chip_info->model_name;
875 indio_dev->info = &mt6359_auxadc_iio_info;
876 indio_dev->modes = INDIO_DIRECT_MODE;
877 indio_dev->channels = adc_dev->chip_info->channels;
878 indio_dev->num_channels = adc_dev->chip_info->num_channels;
879
880 ret = devm_iio_device_register(dev, indio_dev);
881 if (ret)
882 return dev_err_probe(dev, ret, "failed to register iio device\n");
883
884 return 0;
885 }
886
887 static const struct of_device_id mt6359_auxadc_of_match[] = {
888 { .compatible = "mediatek,mt6357-auxadc", .data = &mt6357_chip_info },
889 { .compatible = "mediatek,mt6358-auxadc", .data = &mt6358_chip_info },
890 { .compatible = "mediatek,mt6359-auxadc", .data = &mt6359_chip_info },
891 { .compatible = "mediatek,mt6363-auxadc", .data = &mt6363_chip_info },
892 { .compatible = "mediatek,mt6373-auxadc", .data = &mt6373_chip_info },
893 { }
894 };
895 MODULE_DEVICE_TABLE(of, mt6359_auxadc_of_match);
896
897 static struct platform_driver mt6359_auxadc_driver = {
898 .driver = {
899 .name = "mt6359-auxadc",
900 .of_match_table = mt6359_auxadc_of_match,
901 },
902 .probe = mt6359_auxadc_probe,
903 };
904 module_platform_driver(mt6359_auxadc_driver);
905
906 MODULE_LICENSE("GPL");
907 MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
908 MODULE_DESCRIPTION("MediaTek MT6359 PMIC AUXADC Driver");
909