1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * This file is part of wl18xx
4 *
5 * Copyright (C) 2011 Texas Instruments
6 */
7
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/ip.h>
11 #include <linux/firmware.h>
12 #include <linux/etherdevice.h>
13 #include <linux/irq.h>
14
15 #include "../wlcore/wlcore.h"
16 #include "../wlcore/debug.h"
17 #include "../wlcore/io.h"
18 #include "../wlcore/acx.h"
19 #include "../wlcore/tx.h"
20 #include "../wlcore/rx.h"
21 #include "../wlcore/boot.h"
22
23 #include "reg.h"
24 #include "conf.h"
25 #include "cmd.h"
26 #include "acx.h"
27 #include "tx.h"
28 #include "wl18xx.h"
29 #include "io.h"
30 #include "scan.h"
31 #include "event.h"
32 #include "debugfs.h"
33
34 #define WL18XX_RX_CHECKSUM_MASK 0x40
35
36 static char *ht_mode_param = NULL;
37 static char *board_type_param = NULL;
38 static bool checksum_param = false;
39 static int num_rx_desc_param = -1;
40
41 /* phy paramters */
42 static int dc2dc_param = -1;
43 static int n_antennas_2_param = -1;
44 static int n_antennas_5_param = -1;
45 static int low_band_component_param = -1;
46 static int low_band_component_type_param = -1;
47 static int high_band_component_param = -1;
48 static int high_band_component_type_param = -1;
49 static int pwr_limit_reference_11_abg_param = -1;
50
51 static const u8 wl18xx_rate_to_idx_2ghz[] = {
52 /* MCS rates are used only with 11n */
53 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
54 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
55 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
56 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
57 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
58 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
59 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
60 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
61 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
62 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
63 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
64 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
65 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
66 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
67 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
68 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
69
70 11, /* WL18XX_CONF_HW_RXTX_RATE_54 */
71 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */
72 9, /* WL18XX_CONF_HW_RXTX_RATE_36 */
73 8, /* WL18XX_CONF_HW_RXTX_RATE_24 */
74
75 /* TI-specific rate */
76 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
77
78 7, /* WL18XX_CONF_HW_RXTX_RATE_18 */
79 6, /* WL18XX_CONF_HW_RXTX_RATE_12 */
80 3, /* WL18XX_CONF_HW_RXTX_RATE_11 */
81 5, /* WL18XX_CONF_HW_RXTX_RATE_9 */
82 4, /* WL18XX_CONF_HW_RXTX_RATE_6 */
83 2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
84 1, /* WL18XX_CONF_HW_RXTX_RATE_2 */
85 0 /* WL18XX_CONF_HW_RXTX_RATE_1 */
86 };
87
88 static const u8 wl18xx_rate_to_idx_5ghz[] = {
89 /* MCS rates are used only with 11n */
90 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
91 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
92 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
93 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
94 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
95 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
96 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
97 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
98 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
99 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
100 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
101 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
102 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
103 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
104 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
105 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
106
107 7, /* WL18XX_CONF_HW_RXTX_RATE_54 */
108 6, /* WL18XX_CONF_HW_RXTX_RATE_48 */
109 5, /* WL18XX_CONF_HW_RXTX_RATE_36 */
110 4, /* WL18XX_CONF_HW_RXTX_RATE_24 */
111
112 /* TI-specific rate */
113 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
114
115 3, /* WL18XX_CONF_HW_RXTX_RATE_18 */
116 2, /* WL18XX_CONF_HW_RXTX_RATE_12 */
117 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */
118 1, /* WL18XX_CONF_HW_RXTX_RATE_9 */
119 0, /* WL18XX_CONF_HW_RXTX_RATE_6 */
120 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
121 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */
122 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */
123 };
124
125 static const u8 *wl18xx_band_rate_to_idx[] = {
126 [NL80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
127 [NL80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
128 };
129
130 enum wl18xx_hw_rates {
131 WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
132 WL18XX_CONF_HW_RXTX_RATE_MCS14,
133 WL18XX_CONF_HW_RXTX_RATE_MCS13,
134 WL18XX_CONF_HW_RXTX_RATE_MCS12,
135 WL18XX_CONF_HW_RXTX_RATE_MCS11,
136 WL18XX_CONF_HW_RXTX_RATE_MCS10,
137 WL18XX_CONF_HW_RXTX_RATE_MCS9,
138 WL18XX_CONF_HW_RXTX_RATE_MCS8,
139 WL18XX_CONF_HW_RXTX_RATE_MCS7,
140 WL18XX_CONF_HW_RXTX_RATE_MCS6,
141 WL18XX_CONF_HW_RXTX_RATE_MCS5,
142 WL18XX_CONF_HW_RXTX_RATE_MCS4,
143 WL18XX_CONF_HW_RXTX_RATE_MCS3,
144 WL18XX_CONF_HW_RXTX_RATE_MCS2,
145 WL18XX_CONF_HW_RXTX_RATE_MCS1,
146 WL18XX_CONF_HW_RXTX_RATE_MCS0,
147 WL18XX_CONF_HW_RXTX_RATE_54,
148 WL18XX_CONF_HW_RXTX_RATE_48,
149 WL18XX_CONF_HW_RXTX_RATE_36,
150 WL18XX_CONF_HW_RXTX_RATE_24,
151 WL18XX_CONF_HW_RXTX_RATE_22,
152 WL18XX_CONF_HW_RXTX_RATE_18,
153 WL18XX_CONF_HW_RXTX_RATE_12,
154 WL18XX_CONF_HW_RXTX_RATE_11,
155 WL18XX_CONF_HW_RXTX_RATE_9,
156 WL18XX_CONF_HW_RXTX_RATE_6,
157 WL18XX_CONF_HW_RXTX_RATE_5_5,
158 WL18XX_CONF_HW_RXTX_RATE_2,
159 WL18XX_CONF_HW_RXTX_RATE_1,
160 WL18XX_CONF_HW_RXTX_RATE_MAX,
161 };
162
163 static struct wlcore_conf wl18xx_conf = {
164 .sg = {
165 .params = {
166 [WL18XX_CONF_SG_PARAM_0] = 0,
167 /* Configuration Parameters */
168 [WL18XX_CONF_SG_ANTENNA_CONFIGURATION] = 0,
169 [WL18XX_CONF_SG_ZIGBEE_COEX] = 0,
170 [WL18XX_CONF_SG_TIME_SYNC] = 0,
171 [WL18XX_CONF_SG_PARAM_4] = 0,
172 [WL18XX_CONF_SG_PARAM_5] = 0,
173 [WL18XX_CONF_SG_PARAM_6] = 0,
174 [WL18XX_CONF_SG_PARAM_7] = 0,
175 [WL18XX_CONF_SG_PARAM_8] = 0,
176 [WL18XX_CONF_SG_PARAM_9] = 0,
177 [WL18XX_CONF_SG_PARAM_10] = 0,
178 [WL18XX_CONF_SG_PARAM_11] = 0,
179 [WL18XX_CONF_SG_PARAM_12] = 0,
180 [WL18XX_CONF_SG_PARAM_13] = 0,
181 [WL18XX_CONF_SG_PARAM_14] = 0,
182 [WL18XX_CONF_SG_PARAM_15] = 0,
183 [WL18XX_CONF_SG_PARAM_16] = 0,
184 [WL18XX_CONF_SG_PARAM_17] = 0,
185 [WL18XX_CONF_SG_PARAM_18] = 0,
186 [WL18XX_CONF_SG_PARAM_19] = 0,
187 [WL18XX_CONF_SG_PARAM_20] = 0,
188 [WL18XX_CONF_SG_PARAM_21] = 0,
189 [WL18XX_CONF_SG_PARAM_22] = 0,
190 [WL18XX_CONF_SG_PARAM_23] = 0,
191 [WL18XX_CONF_SG_PARAM_24] = 0,
192 [WL18XX_CONF_SG_PARAM_25] = 0,
193 /* Active Scan Parameters */
194 [WL18XX_CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
195 [WL18XX_CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
196 [WL18XX_CONF_SG_PARAM_28] = 0,
197 /* Passive Scan Parameters */
198 [WL18XX_CONF_SG_PARAM_29] = 0,
199 [WL18XX_CONF_SG_PARAM_30] = 0,
200 [WL18XX_CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
201 /* Passive Scan in Dual Antenna Parameters */
202 [WL18XX_CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
203 [WL18XX_CONF_SG_BEACON_HV3_COLL_TH_IN_PASSIVE_SCAN] = 0,
204 [WL18XX_CONF_SG_TX_RX_PROTECT_BW_IN_PASSIVE_SCAN] = 0,
205 /* General Parameters */
206 [WL18XX_CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
207 [WL18XX_CONF_SG_PARAM_36] = 0,
208 [WL18XX_CONF_SG_BEACON_MISS_PERCENT] = 60,
209 [WL18XX_CONF_SG_PARAM_38] = 0,
210 [WL18XX_CONF_SG_RXT] = 1200,
211 [WL18XX_CONF_SG_UNUSED] = 0,
212 [WL18XX_CONF_SG_ADAPTIVE_RXT_TXT] = 1,
213 [WL18XX_CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
214 [WL18XX_CONF_SG_HV3_MAX_SERVED] = 6,
215 [WL18XX_CONF_SG_PARAM_44] = 0,
216 [WL18XX_CONF_SG_PARAM_45] = 0,
217 [WL18XX_CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
218 [WL18XX_CONF_SG_GEMINI_PARAM_47] = 0,
219 [WL18XX_CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 0,
220 /* AP Parameters */
221 [WL18XX_CONF_SG_AP_BEACON_MISS_TX] = 3,
222 [WL18XX_CONF_SG_PARAM_50] = 0,
223 [WL18XX_CONF_SG_AP_BEACON_WINDOW_INTERVAL] = 2,
224 [WL18XX_CONF_SG_AP_CONNECTION_PROTECTION_TIME] = 30,
225 [WL18XX_CONF_SG_PARAM_53] = 0,
226 [WL18XX_CONF_SG_PARAM_54] = 0,
227 /* CTS Diluting Parameters */
228 [WL18XX_CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
229 [WL18XX_CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
230 [WL18XX_CONF_SG_TEMP_PARAM_1] = 0,
231 [WL18XX_CONF_SG_TEMP_PARAM_2] = 0,
232 [WL18XX_CONF_SG_TEMP_PARAM_3] = 0,
233 [WL18XX_CONF_SG_TEMP_PARAM_4] = 0,
234 [WL18XX_CONF_SG_TEMP_PARAM_5] = 0,
235 [WL18XX_CONF_SG_TEMP_PARAM_6] = 0,
236 [WL18XX_CONF_SG_TEMP_PARAM_7] = 0,
237 [WL18XX_CONF_SG_TEMP_PARAM_8] = 0,
238 [WL18XX_CONF_SG_TEMP_PARAM_9] = 0,
239 [WL18XX_CONF_SG_TEMP_PARAM_10] = 0,
240 },
241 .state = CONF_SG_PROTECTIVE,
242 },
243 .rx = {
244 .rx_msdu_life_time = 512000,
245 .packet_detection_threshold = 0,
246 .ps_poll_timeout = 15,
247 .upsd_timeout = 15,
248 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
249 .rx_cca_threshold = 0,
250 .irq_blk_threshold = 0xFFFF,
251 .irq_pkt_threshold = 0,
252 .irq_timeout = 600,
253 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
254 },
255 .tx = {
256 .tx_energy_detection = 0,
257 .sta_rc_conf = {
258 .enabled_rates = 0,
259 .short_retry_limit = 10,
260 .long_retry_limit = 10,
261 .aflags = 0,
262 },
263 .ac_conf_count = 4,
264 .ac_conf = {
265 [CONF_TX_AC_BE] = {
266 .ac = CONF_TX_AC_BE,
267 .cw_min = 15,
268 .cw_max = 63,
269 .aifsn = 3,
270 .tx_op_limit = 0,
271 },
272 [CONF_TX_AC_BK] = {
273 .ac = CONF_TX_AC_BK,
274 .cw_min = 15,
275 .cw_max = 63,
276 .aifsn = 7,
277 .tx_op_limit = 0,
278 },
279 [CONF_TX_AC_VI] = {
280 .ac = CONF_TX_AC_VI,
281 .cw_min = 15,
282 .cw_max = 63,
283 .aifsn = CONF_TX_AIFS_PIFS,
284 .tx_op_limit = 3008,
285 },
286 [CONF_TX_AC_VO] = {
287 .ac = CONF_TX_AC_VO,
288 .cw_min = 15,
289 .cw_max = 63,
290 .aifsn = CONF_TX_AIFS_PIFS,
291 .tx_op_limit = 1504,
292 },
293 },
294 .max_tx_retries = 100,
295 .ap_aging_period = 300,
296 .tid_conf_count = 4,
297 .tid_conf = {
298 [CONF_TX_AC_BE] = {
299 .queue_id = CONF_TX_AC_BE,
300 .channel_type = CONF_CHANNEL_TYPE_EDCF,
301 .tsid = CONF_TX_AC_BE,
302 .ps_scheme = CONF_PS_SCHEME_LEGACY,
303 .ack_policy = CONF_ACK_POLICY_LEGACY,
304 .apsd_conf = {0, 0},
305 },
306 [CONF_TX_AC_BK] = {
307 .queue_id = CONF_TX_AC_BK,
308 .channel_type = CONF_CHANNEL_TYPE_EDCF,
309 .tsid = CONF_TX_AC_BK,
310 .ps_scheme = CONF_PS_SCHEME_LEGACY,
311 .ack_policy = CONF_ACK_POLICY_LEGACY,
312 .apsd_conf = {0, 0},
313 },
314 [CONF_TX_AC_VI] = {
315 .queue_id = CONF_TX_AC_VI,
316 .channel_type = CONF_CHANNEL_TYPE_EDCF,
317 .tsid = CONF_TX_AC_VI,
318 .ps_scheme = CONF_PS_SCHEME_LEGACY,
319 .ack_policy = CONF_ACK_POLICY_LEGACY,
320 .apsd_conf = {0, 0},
321 },
322 [CONF_TX_AC_VO] = {
323 .queue_id = CONF_TX_AC_VO,
324 .channel_type = CONF_CHANNEL_TYPE_EDCF,
325 .tsid = CONF_TX_AC_VO,
326 .ps_scheme = CONF_PS_SCHEME_LEGACY,
327 .ack_policy = CONF_ACK_POLICY_LEGACY,
328 .apsd_conf = {0, 0},
329 },
330 },
331 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
332 .tx_compl_timeout = 350,
333 .tx_compl_threshold = 10,
334 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
335 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
336 .tmpl_short_retry_limit = 10,
337 .tmpl_long_retry_limit = 10,
338 .tx_watchdog_timeout = 5000,
339 .slow_link_thold = 3,
340 .fast_link_thold = 30,
341 },
342 .conn = {
343 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
344 .listen_interval = 1,
345 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
346 .suspend_listen_interval = 3,
347 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
348 .bcn_filt_ie_count = 3,
349 .bcn_filt_ie = {
350 [0] = {
351 .ie = WLAN_EID_CHANNEL_SWITCH,
352 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
353 },
354 [1] = {
355 .ie = WLAN_EID_HT_OPERATION,
356 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
357 },
358 [2] = {
359 .ie = WLAN_EID_ERP_INFO,
360 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
361 },
362 },
363 .synch_fail_thold = 12,
364 .bss_lose_timeout = 400,
365 .beacon_rx_timeout = 10000,
366 .broadcast_timeout = 20000,
367 .rx_broadcast_in_ps = 1,
368 .ps_poll_threshold = 10,
369 .bet_enable = CONF_BET_MODE_ENABLE,
370 .bet_max_consecutive = 50,
371 .psm_entry_retries = 8,
372 .psm_exit_retries = 16,
373 .psm_entry_nullfunc_retries = 3,
374 .dynamic_ps_timeout = 1500,
375 .forced_ps = false,
376 .keep_alive_interval = 55000,
377 .max_listen_interval = 20,
378 .sta_sleep_auth = WL1271_PSM_ILLEGAL,
379 .suspend_rx_ba_activity = 0,
380 },
381 .itrim = {
382 .enable = false,
383 .timeout = 50000,
384 },
385 .pm_config = {
386 .host_clk_settling_time = 5000,
387 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
388 },
389 .roam_trigger = {
390 .trigger_pacing = 1,
391 .avg_weight_rssi_beacon = 20,
392 .avg_weight_rssi_data = 10,
393 .avg_weight_snr_beacon = 20,
394 .avg_weight_snr_data = 10,
395 },
396 .scan = {
397 .min_dwell_time_active = 7500,
398 .max_dwell_time_active = 30000,
399 .min_dwell_time_active_long = 25000,
400 .max_dwell_time_active_long = 50000,
401 .dwell_time_passive = 100000,
402 .dwell_time_dfs = 150000,
403 .num_probe_reqs = 2,
404 .split_scan_timeout = 50000,
405 },
406 .sched_scan = {
407 /*
408 * Values are in TU/1000 but since sched scan FW command
409 * params are in TUs rounding up may occur.
410 */
411 .base_dwell_time = 7500,
412 .max_dwell_time_delta = 22500,
413 /* based on 250bits per probe @1Mbps */
414 .dwell_time_delta_per_probe = 2000,
415 /* based on 250bits per probe @6Mbps (plus a bit more) */
416 .dwell_time_delta_per_probe_5 = 350,
417 .dwell_time_passive = 100000,
418 .dwell_time_dfs = 150000,
419 .num_probe_reqs = 2,
420 .rssi_threshold = -90,
421 .snr_threshold = 0,
422 .num_short_intervals = SCAN_MAX_SHORT_INTERVALS,
423 .long_interval = 30000,
424 },
425 .ht = {
426 .rx_ba_win_size = 32,
427 .tx_ba_win_size = 64,
428 .inactivity_timeout = 10000,
429 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
430 },
431 .mem = {
432 .num_stations = 1,
433 .ssid_profiles = 1,
434 .rx_block_num = 40,
435 .tx_min_block_num = 40,
436 .dynamic_memory = 1,
437 .min_req_tx_blocks = 45,
438 .min_req_rx_blocks = 22,
439 .tx_min = 27,
440 },
441 .fm_coex = {
442 .enable = true,
443 .swallow_period = 5,
444 .n_divider_fref_set_1 = 0xff, /* default */
445 .n_divider_fref_set_2 = 12,
446 .m_divider_fref_set_1 = 0xffff,
447 .m_divider_fref_set_2 = 148, /* default */
448 .coex_pll_stabilization_time = 0xffffffff, /* default */
449 .ldo_stabilization_time = 0xffff, /* default */
450 .fm_disturbed_band_margin = 0xff, /* default */
451 .swallow_clk_diff = 0xff, /* default */
452 },
453 .rx_streaming = {
454 .duration = 150,
455 .queues = 0x1,
456 .interval = 20,
457 .always = 0,
458 },
459 .fwlog = {
460 .mode = WL12XX_FWLOG_CONTINUOUS,
461 .mem_blocks = 0,
462 .severity = 0,
463 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
464 .output = WL12XX_FWLOG_OUTPUT_DBG_PINS,
465 .threshold = 0,
466 },
467 .rate = {
468 .rate_retry_score = 32000,
469 .per_add = 8192,
470 .per_th1 = 2048,
471 .per_th2 = 4096,
472 .max_per = 8100,
473 .inverse_curiosity_factor = 5,
474 .tx_fail_low_th = 4,
475 .tx_fail_high_th = 10,
476 .per_alpha_shift = 4,
477 .per_add_shift = 13,
478 .per_beta1_shift = 10,
479 .per_beta2_shift = 8,
480 .rate_check_up = 2,
481 .rate_check_down = 12,
482 .rate_retry_policy = {
483 0x00, 0x00, 0x00, 0x00, 0x00,
484 0x00, 0x00, 0x00, 0x00, 0x00,
485 0x00, 0x00, 0x00,
486 },
487 },
488 .hangover = {
489 .recover_time = 0,
490 .hangover_period = 20,
491 .dynamic_mode = 1,
492 .early_termination_mode = 1,
493 .max_period = 20,
494 .min_period = 1,
495 .increase_delta = 1,
496 .decrease_delta = 2,
497 .quiet_time = 4,
498 .increase_time = 1,
499 .window_size = 16,
500 },
501 .recovery = {
502 .bug_on_recovery = 0,
503 .no_recovery = 0,
504 },
505 };
506
507 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
508 .ht = {
509 .mode = HT_MODE_WIDE,
510 },
511 .phy = {
512 .phy_standalone = 0x00,
513 .primary_clock_setting_time = 0x05,
514 .clock_valid_on_wake_up = 0x00,
515 .secondary_clock_setting_time = 0x05,
516 .board_type = BOARD_TYPE_HDK_18XX,
517 .auto_detect = 0x00,
518 .dedicated_fem = FEM_NONE,
519 .low_band_component = COMPONENT_3_WAY_SWITCH,
520 .low_band_component_type = 0x05,
521 .high_band_component = COMPONENT_2_WAY_SWITCH,
522 .high_band_component_type = 0x09,
523 .tcxo_ldo_voltage = 0x00,
524 .xtal_itrim_val = 0x04,
525 .srf_state = 0x00,
526 .io_configuration = 0x01,
527 .sdio_configuration = 0x00,
528 .settings = 0x00,
529 .enable_clpc = 0x00,
530 .enable_tx_low_pwr_on_siso_rdl = 0x00,
531 .rx_profile = 0x00,
532 .pwr_limit_reference_11_abg = 0x64,
533 .per_chan_pwr_limit_arr_11abg = {
534 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
535 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
536 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
537 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
538 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
539 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
540 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
541 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
542 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
543 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
544 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
545 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
546 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
547 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
548 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
549 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
550 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
551 .pwr_limit_reference_11p = 0x64,
552 .per_chan_bo_mode_11_abg = { 0x00, 0x00, 0x00, 0x00,
553 0x00, 0x00, 0x00, 0x00,
554 0x00, 0x00, 0x00, 0x00,
555 0x00 },
556 .per_chan_bo_mode_11_p = { 0x00, 0x00, 0x00, 0x00 },
557 .per_chan_pwr_limit_arr_11p = { 0xff, 0xff, 0xff, 0xff,
558 0xff, 0xff, 0xff },
559 .psat = 0,
560 .external_pa_dc2dc = 0,
561 .number_of_assembled_ant2_4 = 2,
562 .number_of_assembled_ant5 = 1,
563 .low_power_val = 0xff,
564 .med_power_val = 0xff,
565 .high_power_val = 0xff,
566 .low_power_val_2nd = 0xff,
567 .med_power_val_2nd = 0xff,
568 .high_power_val_2nd = 0xff,
569 .tx_rf_margin = 1,
570 },
571 .ap_sleep = { /* disabled by default */
572 .idle_duty_cycle = 0,
573 .connected_duty_cycle = 0,
574 .max_stations_thresh = 0,
575 .idle_conn_thresh = 0,
576 },
577 };
578
579 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
580 [PART_TOP_PRCM_ELP_SOC] = {
581 .mem = { .start = 0x00A00000, .size = 0x00012000 },
582 .reg = { .start = 0x00807000, .size = 0x00005000 },
583 .mem2 = { .start = 0x00800000, .size = 0x0000B000 },
584 .mem3 = { .start = 0x00401594, .size = 0x00001020 },
585 },
586 [PART_DOWN] = {
587 .mem = { .start = 0x00000000, .size = 0x00014000 },
588 .reg = { .start = 0x00810000, .size = 0x0000BFFF },
589 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
590 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
591 },
592 [PART_BOOT] = {
593 .mem = { .start = 0x00700000, .size = 0x0000030c },
594 .reg = { .start = 0x00802000, .size = 0x00014578 },
595 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
596 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
597 },
598 [PART_WORK] = {
599 .mem = { .start = 0x00800000, .size = 0x000050FC },
600 .reg = { .start = 0x00B00404, .size = 0x00001000 },
601 .mem2 = { .start = 0x00C00000, .size = 0x00000400 },
602 .mem3 = { .start = 0x00401594, .size = 0x00001020 },
603 },
604 [PART_PHY_INIT] = {
605 .mem = { .start = WL18XX_PHY_INIT_MEM_ADDR,
606 .size = WL18XX_PHY_INIT_MEM_SIZE },
607 .reg = { .start = 0x00000000, .size = 0x00000000 },
608 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
609 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
610 },
611 };
612
613 static const int wl18xx_rtable[REG_TABLE_LEN] = {
614 [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL,
615 [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR,
616 [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK,
617 [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR,
618 [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR,
619 [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H,
620 [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK,
621 [REG_PC_ON_RECOVERY] = WL18XX_SCR_PAD4,
622 [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B,
623 [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS,
624
625 /* data access memory addresses, used with partition translation */
626 [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA,
627 [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA,
628
629 /* raw data access memory addresses */
630 [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
631 };
632
633 static const struct wl18xx_clk_cfg wl18xx_clk_table_coex[NUM_CLOCK_CONFIGS] = {
634 [CLOCK_CONFIG_16_2_M] = { 8, 121, 0, 0, false },
635 [CLOCK_CONFIG_16_368_M] = { 8, 120, 0, 0, false },
636 [CLOCK_CONFIG_16_8_M] = { 8, 117, 0, 0, false },
637 [CLOCK_CONFIG_19_2_M] = { 10, 128, 0, 0, false },
638 [CLOCK_CONFIG_26_M] = { 11, 104, 0, 0, false },
639 [CLOCK_CONFIG_32_736_M] = { 8, 120, 0, 0, false },
640 [CLOCK_CONFIG_33_6_M] = { 8, 117, 0, 0, false },
641 [CLOCK_CONFIG_38_468_M] = { 10, 128, 0, 0, false },
642 [CLOCK_CONFIG_52_M] = { 11, 104, 0, 0, false },
643 };
644
645 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
646 [CLOCK_CONFIG_16_2_M] = { 7, 104, 801, 4, true },
647 [CLOCK_CONFIG_16_368_M] = { 9, 132, 3751, 4, true },
648 [CLOCK_CONFIG_16_8_M] = { 7, 100, 0, 0, false },
649 [CLOCK_CONFIG_19_2_M] = { 8, 100, 0, 0, false },
650 [CLOCK_CONFIG_26_M] = { 13, 120, 0, 0, false },
651 [CLOCK_CONFIG_32_736_M] = { 9, 132, 3751, 4, true },
652 [CLOCK_CONFIG_33_6_M] = { 7, 100, 0, 0, false },
653 [CLOCK_CONFIG_38_468_M] = { 8, 100, 0, 0, false },
654 [CLOCK_CONFIG_52_M] = { 13, 120, 0, 0, false },
655 };
656
657 /* TODO: maybe move to a new header file? */
658 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw-4.bin"
659
wl18xx_identify_chip(struct wl1271 * wl)660 static int wl18xx_identify_chip(struct wl1271 *wl)
661 {
662 int ret = 0;
663
664 switch (wl->chip.id) {
665 case CHIP_ID_185x_PG20:
666 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)",
667 wl->chip.id);
668 wl->sr_fw_name = WL18XX_FW_NAME;
669 /* wl18xx uses the same firmware for PLT */
670 wl->plt_fw_name = WL18XX_FW_NAME;
671 wl->quirks |= WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
672 WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
673 WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN |
674 WLCORE_QUIRK_TX_PAD_LAST_FRAME |
675 WLCORE_QUIRK_REGDOMAIN_CONF |
676 WLCORE_QUIRK_DUAL_PROBE_TMPL;
677
678 wlcore_set_min_fw_ver(wl, WL18XX_CHIP_VER,
679 WL18XX_IFTYPE_VER, WL18XX_MAJOR_VER,
680 WL18XX_SUBTYPE_VER, WL18XX_MINOR_VER,
681 /* there's no separate multi-role FW */
682 0, 0, 0, 0);
683 break;
684 case CHIP_ID_185x_PG10:
685 wl1271_warning("chip id 0x%x (185x PG10) is deprecated",
686 wl->chip.id);
687 ret = -ENODEV;
688 goto out;
689
690 default:
691 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
692 ret = -ENODEV;
693 goto out;
694 }
695
696 wl->fw_mem_block_size = 272;
697 wl->fwlog_end = 0x40000000;
698
699 wl->scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
700 wl->scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
701 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_PROBE_REQ_2_4_PERIODIC;
702 wl->sched_scan_templ_id_5 = CMD_TEMPL_PROBE_REQ_5_PERIODIC;
703 wl->max_channels_5 = WL18XX_MAX_CHANNELS_5GHZ;
704 wl->ba_rx_session_count_max = WL18XX_RX_BA_MAX_SESSIONS;
705 out:
706 return ret;
707 }
708
wl18xx_set_clk(struct wl1271 * wl)709 static int wl18xx_set_clk(struct wl1271 *wl)
710 {
711 u16 clk_freq;
712 int ret;
713
714 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
715 if (ret < 0)
716 goto out;
717
718 /* TODO: PG2: apparently we need to read the clk type */
719
720 ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq);
721 if (ret < 0)
722 goto out;
723
724 wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
725 wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
726 wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
727 wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
728
729 /* coex PLL configuration */
730 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_N,
731 wl18xx_clk_table_coex[clk_freq].n);
732 if (ret < 0)
733 goto out;
734
735 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_M,
736 wl18xx_clk_table_coex[clk_freq].m);
737 if (ret < 0)
738 goto out;
739
740 /* bypass the swallowing logic */
741 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN,
742 PLLSH_COEX_PLL_SWALLOW_EN_VAL1);
743 if (ret < 0)
744 goto out;
745
746 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
747 wl18xx_clk_table[clk_freq].n);
748 if (ret < 0)
749 goto out;
750
751 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M,
752 wl18xx_clk_table[clk_freq].m);
753 if (ret < 0)
754 goto out;
755
756 if (wl18xx_clk_table[clk_freq].swallow) {
757 /* first the 16 lower bits */
758 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
759 wl18xx_clk_table[clk_freq].q &
760 PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
761 if (ret < 0)
762 goto out;
763
764 /* then the 16 higher bits, masked out */
765 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
766 (wl18xx_clk_table[clk_freq].q >> 16) &
767 PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
768 if (ret < 0)
769 goto out;
770
771 /* first the 16 lower bits */
772 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
773 wl18xx_clk_table[clk_freq].p &
774 PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
775 if (ret < 0)
776 goto out;
777
778 /* then the 16 higher bits, masked out */
779 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
780 (wl18xx_clk_table[clk_freq].p >> 16) &
781 PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
782 if (ret < 0)
783 goto out;
784 } else {
785 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
786 PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
787 if (ret < 0)
788 goto out;
789 }
790
791 /* choose WCS PLL */
792 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_SEL,
793 PLLSH_WL_PLL_SEL_WCS_PLL);
794 if (ret < 0)
795 goto out;
796
797 /* enable both PLLs */
798 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL1);
799 if (ret < 0)
800 goto out;
801
802 udelay(1000);
803
804 /* disable coex PLL */
805 ret = wl18xx_top_reg_write(wl, PLLSH_WL_PLL_EN, PLLSH_WL_PLL_EN_VAL2);
806 if (ret < 0)
807 goto out;
808
809 /* reset the swallowing logic */
810 ret = wl18xx_top_reg_write(wl, PLLSH_COEX_PLL_SWALLOW_EN,
811 PLLSH_COEX_PLL_SWALLOW_EN_VAL2);
812
813 out:
814 return ret;
815 }
816
wl18xx_boot_soft_reset(struct wl1271 * wl)817 static int wl18xx_boot_soft_reset(struct wl1271 *wl)
818 {
819 int ret;
820
821 /* disable Rx/Tx */
822 ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0);
823 if (ret < 0)
824 goto out;
825
826 /* disable auto calibration on start*/
827 ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff);
828
829 out:
830 return ret;
831 }
832
wl18xx_pre_boot(struct wl1271 * wl)833 static int wl18xx_pre_boot(struct wl1271 *wl)
834 {
835 int ret;
836
837 ret = wl18xx_set_clk(wl);
838 if (ret < 0)
839 goto out;
840
841 /* Continue the ELP wake up sequence */
842 ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
843 if (ret < 0)
844 goto out;
845
846 udelay(500);
847
848 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
849 if (ret < 0)
850 goto out;
851
852 /* Disable interrupts */
853 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
854 if (ret < 0)
855 goto out;
856
857 ret = wl18xx_boot_soft_reset(wl);
858
859 out:
860 return ret;
861 }
862
wl18xx_pre_upload(struct wl1271 * wl)863 static int wl18xx_pre_upload(struct wl1271 *wl)
864 {
865 u32 tmp;
866 int ret;
867 u16 irq_invert;
868
869 BUILD_BUG_ON(sizeof(struct wl18xx_mac_and_phy_params) >
870 WL18XX_PHY_INIT_MEM_SIZE);
871
872 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
873 if (ret < 0)
874 goto out;
875
876 /* TODO: check if this is all needed */
877 ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
878 if (ret < 0)
879 goto out;
880
881 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
882 if (ret < 0)
883 goto out;
884
885 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
886
887 ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp);
888 if (ret < 0)
889 goto out;
890
891 /*
892 * Workaround for FDSP code RAM corruption (needed for PG2.1
893 * and newer; for older chips it's a NOP). Change FDSP clock
894 * settings so that it's muxed to the ATGP clock instead of
895 * its own clock.
896 */
897
898 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
899 if (ret < 0)
900 goto out;
901
902 /* disable FDSP clock */
903 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
904 MEM_FDSP_CLK_120_DISABLE);
905 if (ret < 0)
906 goto out;
907
908 /* set ATPG clock toward FDSP Code RAM rather than its own clock */
909 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
910 MEM_FDSP_CODERAM_FUNC_CLK_SEL);
911 if (ret < 0)
912 goto out;
913
914 /* re-enable FDSP clock */
915 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
916 MEM_FDSP_CLK_120_ENABLE);
917 if (ret < 0)
918 goto out;
919
920 ret = irq_get_trigger_type(wl->irq);
921 if ((ret == IRQ_TYPE_LEVEL_LOW) || (ret == IRQ_TYPE_EDGE_FALLING)) {
922 wl1271_info("using inverted interrupt logic: %d", ret);
923 ret = wlcore_set_partition(wl,
924 &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
925 if (ret < 0)
926 goto out;
927
928 ret = wl18xx_top_reg_read(wl, TOP_FN0_CCCR_REG_32, &irq_invert);
929 if (ret < 0)
930 goto out;
931
932 irq_invert |= BIT(1);
933 ret = wl18xx_top_reg_write(wl, TOP_FN0_CCCR_REG_32, irq_invert);
934 if (ret < 0)
935 goto out;
936
937 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
938 }
939
940 out:
941 return ret;
942 }
943
wl18xx_set_mac_and_phy(struct wl1271 * wl)944 static int wl18xx_set_mac_and_phy(struct wl1271 *wl)
945 {
946 struct wl18xx_priv *priv = wl->priv;
947 struct wl18xx_mac_and_phy_params *params;
948 int ret;
949
950 params = kmemdup(&priv->conf.phy, sizeof(*params), GFP_KERNEL);
951 if (!params) {
952 ret = -ENOMEM;
953 goto out;
954 }
955
956 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
957 if (ret < 0)
958 goto out;
959
960 ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, params,
961 sizeof(*params), false);
962
963 out:
964 kfree(params);
965 return ret;
966 }
967
wl18xx_enable_interrupts(struct wl1271 * wl)968 static int wl18xx_enable_interrupts(struct wl1271 *wl)
969 {
970 u32 event_mask, intr_mask;
971 int ret;
972
973 event_mask = WL18XX_ACX_EVENTS_VECTOR;
974 intr_mask = WL18XX_INTR_MASK;
975
976 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask);
977 if (ret < 0)
978 goto out;
979
980 wlcore_enable_interrupts(wl);
981
982 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
983 WL1271_ACX_INTR_ALL & ~intr_mask);
984 if (ret < 0)
985 goto disable_interrupts;
986
987 return ret;
988
989 disable_interrupts:
990 wlcore_disable_interrupts(wl);
991
992 out:
993 return ret;
994 }
995
wl18xx_boot(struct wl1271 * wl)996 static int wl18xx_boot(struct wl1271 *wl)
997 {
998 int ret;
999
1000 ret = wl18xx_pre_boot(wl);
1001 if (ret < 0)
1002 goto out;
1003
1004 ret = wl18xx_pre_upload(wl);
1005 if (ret < 0)
1006 goto out;
1007
1008 ret = wlcore_boot_upload_firmware(wl);
1009 if (ret < 0)
1010 goto out;
1011
1012 ret = wl18xx_set_mac_and_phy(wl);
1013 if (ret < 0)
1014 goto out;
1015
1016 wl->event_mask = BSS_LOSS_EVENT_ID |
1017 SCAN_COMPLETE_EVENT_ID |
1018 RADAR_DETECTED_EVENT_ID |
1019 RSSI_SNR_TRIGGER_0_EVENT_ID |
1020 PERIODIC_SCAN_COMPLETE_EVENT_ID |
1021 PERIODIC_SCAN_REPORT_EVENT_ID |
1022 DUMMY_PACKET_EVENT_ID |
1023 PEER_REMOVE_COMPLETE_EVENT_ID |
1024 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
1025 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
1026 INACTIVE_STA_EVENT_ID |
1027 CHANNEL_SWITCH_COMPLETE_EVENT_ID |
1028 DFS_CHANNELS_CONFIG_COMPLETE_EVENT |
1029 SMART_CONFIG_SYNC_EVENT_ID |
1030 SMART_CONFIG_DECODE_EVENT_ID |
1031 TIME_SYNC_EVENT_ID |
1032 FW_LOGGER_INDICATION |
1033 RX_BA_WIN_SIZE_CHANGE_EVENT_ID;
1034
1035 wl->ap_event_mask = MAX_TX_FAILURE_EVENT_ID;
1036
1037 ret = wlcore_boot_run_firmware(wl);
1038 if (ret < 0)
1039 goto out;
1040
1041 ret = wl18xx_enable_interrupts(wl);
1042
1043 out:
1044 return ret;
1045 }
1046
wl18xx_trigger_cmd(struct wl1271 * wl,int cmd_box_addr,void * buf,size_t len)1047 static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1048 void *buf, size_t len)
1049 {
1050 struct wl18xx_priv *priv = wl->priv;
1051
1052 memcpy(priv->cmd_buf, buf, len);
1053 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
1054
1055 return wlcore_write(wl, cmd_box_addr, priv->cmd_buf,
1056 WL18XX_CMD_MAX_SIZE, false);
1057 }
1058
wl18xx_ack_event(struct wl1271 * wl)1059 static int wl18xx_ack_event(struct wl1271 *wl)
1060 {
1061 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1062 WL18XX_INTR_TRIG_EVENT_ACK);
1063 }
1064
wl18xx_calc_tx_blocks(struct wl1271 * wl,u32 len,u32 spare_blks)1065 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1066 {
1067 u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
1068 return (len + blk_size - 1) / blk_size + spare_blks;
1069 }
1070
1071 static void
wl18xx_set_tx_desc_blocks(struct wl1271 * wl,struct wl1271_tx_hw_descr * desc,u32 blks,u32 spare_blks)1072 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1073 u32 blks, u32 spare_blks)
1074 {
1075 desc->wl18xx_mem.total_mem_blocks = blks;
1076 }
1077
1078 static void
wl18xx_set_tx_desc_data_len(struct wl1271 * wl,struct wl1271_tx_hw_descr * desc,struct sk_buff * skb)1079 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1080 struct sk_buff *skb)
1081 {
1082 desc->length = cpu_to_le16(skb->len);
1083
1084 /* if only the last frame is to be padded, we unset this bit on Tx */
1085 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME)
1086 desc->wl18xx_mem.ctrl = WL18XX_TX_CTRL_NOT_PADDED;
1087 else
1088 desc->wl18xx_mem.ctrl = 0;
1089
1090 wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
1091 "len: %d life: %d mem: %d", desc->hlid,
1092 le16_to_cpu(desc->length),
1093 le16_to_cpu(desc->life_time),
1094 desc->wl18xx_mem.total_mem_blocks);
1095 }
1096
1097 static enum wl_rx_buf_align
wl18xx_get_rx_buf_align(struct wl1271 * wl,u32 rx_desc)1098 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1099 {
1100 if (rx_desc & RX_BUF_PADDED_PAYLOAD)
1101 return WLCORE_RX_BUF_PADDED;
1102
1103 return WLCORE_RX_BUF_ALIGNED;
1104 }
1105
wl18xx_get_rx_packet_len(struct wl1271 * wl,void * rx_data,u32 data_len)1106 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1107 u32 data_len)
1108 {
1109 struct wl1271_rx_descriptor *desc = rx_data;
1110
1111 /* invalid packet */
1112 if (data_len < sizeof(*desc))
1113 return 0;
1114
1115 return data_len - sizeof(*desc);
1116 }
1117
wl18xx_tx_immediate_completion(struct wl1271 * wl)1118 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
1119 {
1120 wl18xx_tx_immediate_complete(wl);
1121 }
1122
wl18xx_set_host_cfg_bitmap(struct wl1271 * wl,u32 extra_mem_blk)1123 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk)
1124 {
1125 int ret;
1126 u32 sdio_align_size = 0;
1127 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
1128 HOST_IF_CFG_ADD_RX_ALIGNMENT;
1129
1130 /* Enable Tx SDIO padding */
1131 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
1132 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1133 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
1134 }
1135
1136 /* Enable Rx SDIO padding */
1137 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
1138 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
1139 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
1140 }
1141
1142 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
1143 sdio_align_size, extra_mem_blk,
1144 WL18XX_HOST_IF_LEN_SIZE_FIELD);
1145 if (ret < 0)
1146 return ret;
1147
1148 return 0;
1149 }
1150
wl18xx_hw_init(struct wl1271 * wl)1151 static int wl18xx_hw_init(struct wl1271 *wl)
1152 {
1153 int ret;
1154 struct wl18xx_priv *priv = wl->priv;
1155
1156 /* (re)init private structures. Relevant on recovery as well. */
1157 priv->last_fw_rls_idx = 0;
1158 priv->extra_spare_key_count = 0;
1159
1160 /* set the default amount of spare blocks in the bitmap */
1161 ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE);
1162 if (ret < 0)
1163 return ret;
1164
1165 /* set the dynamic fw traces bitmap */
1166 ret = wl18xx_acx_dynamic_fw_traces(wl);
1167 if (ret < 0)
1168 return ret;
1169
1170 if (checksum_param) {
1171 ret = wl18xx_acx_set_checksum_state(wl);
1172 if (ret != 0)
1173 return ret;
1174 }
1175
1176 return ret;
1177 }
1178
wl18xx_convert_fw_status_8_9_1(struct wl1271 * wl,void * raw_fw_status,struct wl_fw_status * fw_status)1179 static void wl18xx_convert_fw_status_8_9_1(struct wl1271 *wl,
1180 void *raw_fw_status,
1181 struct wl_fw_status *fw_status)
1182 {
1183 struct wl18xx_fw_status_8_9_1 *int_fw_status = raw_fw_status;
1184
1185 fw_status->intr = le32_to_cpu(int_fw_status->intr);
1186 fw_status->fw_rx_counter = int_fw_status->fw_rx_counter;
1187 fw_status->drv_rx_counter = int_fw_status->drv_rx_counter;
1188 fw_status->tx_results_counter = int_fw_status->tx_results_counter;
1189 fw_status->rx_pkt_descs = int_fw_status->rx_pkt_descs;
1190
1191 fw_status->fw_localtime = le32_to_cpu(int_fw_status->fw_localtime);
1192 fw_status->link_ps_bitmap = le32_to_cpu(int_fw_status->link_ps_bitmap);
1193 fw_status->link_fast_bitmap =
1194 le32_to_cpu(int_fw_status->link_fast_bitmap);
1195 fw_status->total_released_blks =
1196 le32_to_cpu(int_fw_status->total_released_blks);
1197 fw_status->tx_total = le32_to_cpu(int_fw_status->tx_total);
1198
1199 fw_status->counters.tx_released_pkts =
1200 int_fw_status->counters.tx_released_pkts;
1201 fw_status->counters.tx_lnk_free_pkts =
1202 int_fw_status->counters.tx_lnk_free_pkts;
1203 fw_status->counters.tx_lnk_sec_pn16 =
1204 int_fw_status->counters.tx_lnk_sec_pn16;
1205 fw_status->counters.tx_voice_released_blks =
1206 int_fw_status->counters.tx_voice_released_blks;
1207 fw_status->counters.tx_last_rate =
1208 int_fw_status->counters.tx_last_rate;
1209 fw_status->counters.tx_last_rate_mbps =
1210 int_fw_status->counters.tx_last_rate_mbps;
1211 fw_status->counters.hlid =
1212 int_fw_status->counters.hlid;
1213
1214 fw_status->log_start_addr = le32_to_cpu(int_fw_status->log_start_addr);
1215
1216 fw_status->priv = &int_fw_status->priv;
1217 }
1218
wl18xx_convert_fw_status_8_9_0(struct wl1271 * wl,void * raw_fw_status,struct wl_fw_status * fw_status)1219 static void wl18xx_convert_fw_status_8_9_0(struct wl1271 *wl,
1220 void *raw_fw_status,
1221 struct wl_fw_status *fw_status)
1222 {
1223 struct wl18xx_fw_status *int_fw_status = raw_fw_status;
1224
1225 fw_status->intr = le32_to_cpu(int_fw_status->intr);
1226 fw_status->fw_rx_counter = int_fw_status->fw_rx_counter;
1227 fw_status->drv_rx_counter = int_fw_status->drv_rx_counter;
1228 fw_status->tx_results_counter = int_fw_status->tx_results_counter;
1229 fw_status->rx_pkt_descs = int_fw_status->rx_pkt_descs;
1230
1231 fw_status->fw_localtime = le32_to_cpu(int_fw_status->fw_localtime);
1232 fw_status->link_ps_bitmap = le32_to_cpu(int_fw_status->link_ps_bitmap);
1233 fw_status->link_fast_bitmap =
1234 le32_to_cpu(int_fw_status->link_fast_bitmap);
1235 fw_status->total_released_blks =
1236 le32_to_cpu(int_fw_status->total_released_blks);
1237 fw_status->tx_total = le32_to_cpu(int_fw_status->tx_total);
1238
1239 fw_status->counters.tx_released_pkts =
1240 int_fw_status->counters.tx_released_pkts;
1241 fw_status->counters.tx_lnk_free_pkts =
1242 int_fw_status->counters.tx_lnk_free_pkts;
1243 fw_status->counters.tx_voice_released_blks =
1244 int_fw_status->counters.tx_voice_released_blks;
1245 fw_status->counters.tx_last_rate =
1246 int_fw_status->counters.tx_last_rate;
1247 fw_status->counters.tx_last_rate_mbps =
1248 int_fw_status->counters.tx_last_rate_mbps;
1249 fw_status->counters.hlid =
1250 int_fw_status->counters.hlid;
1251
1252 fw_status->log_start_addr = le32_to_cpu(int_fw_status->log_start_addr);
1253
1254 fw_status->priv = &int_fw_status->priv;
1255 }
1256
wl18xx_convert_fw_status(struct wl1271 * wl,void * raw_fw_status,struct wl_fw_status * fw_status)1257 static void wl18xx_convert_fw_status(struct wl1271 *wl, void *raw_fw_status,
1258 struct wl_fw_status *fw_status)
1259 {
1260 if (wl->chip.fw_ver[FW_VER_MAJOR] == 0)
1261 wl18xx_convert_fw_status_8_9_0(wl, raw_fw_status, fw_status);
1262 else
1263 wl18xx_convert_fw_status_8_9_1(wl, raw_fw_status, fw_status);
1264 }
1265
wl18xx_set_tx_desc_csum(struct wl1271 * wl,struct wl1271_tx_hw_descr * desc,struct sk_buff * skb)1266 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
1267 struct wl1271_tx_hw_descr *desc,
1268 struct sk_buff *skb)
1269 {
1270 u32 ip_hdr_offset;
1271 struct iphdr *ip_hdr;
1272
1273 if (!checksum_param) {
1274 desc->wl18xx_checksum_data = 0;
1275 return;
1276 }
1277
1278 if (skb->ip_summed != CHECKSUM_PARTIAL) {
1279 desc->wl18xx_checksum_data = 0;
1280 return;
1281 }
1282
1283 ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
1284 if (WARN_ON(ip_hdr_offset >= (1<<7))) {
1285 desc->wl18xx_checksum_data = 0;
1286 return;
1287 }
1288
1289 desc->wl18xx_checksum_data = ip_hdr_offset << 1;
1290
1291 /* FW is interested only in the LSB of the protocol TCP=0 UDP=1 */
1292 ip_hdr = (void *)skb_network_header(skb);
1293 desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
1294 }
1295
wl18xx_set_rx_csum(struct wl1271 * wl,struct wl1271_rx_descriptor * desc,struct sk_buff * skb)1296 static void wl18xx_set_rx_csum(struct wl1271 *wl,
1297 struct wl1271_rx_descriptor *desc,
1298 struct sk_buff *skb)
1299 {
1300 if (desc->status & WL18XX_RX_CHECKSUM_MASK)
1301 skb->ip_summed = CHECKSUM_UNNECESSARY;
1302 }
1303
wl18xx_is_mimo_supported(struct wl1271 * wl)1304 static bool wl18xx_is_mimo_supported(struct wl1271 *wl)
1305 {
1306 struct wl18xx_priv *priv = wl->priv;
1307
1308 /* only support MIMO with multiple antennas, and when SISO
1309 * is not forced through config
1310 */
1311 return (priv->conf.phy.number_of_assembled_ant2_4 >= 2) &&
1312 (priv->conf.ht.mode != HT_MODE_WIDE) &&
1313 (priv->conf.ht.mode != HT_MODE_SISO20);
1314 }
1315
1316 /*
1317 * TODO: instead of having these two functions to get the rate mask,
1318 * we should modify the wlvif->rate_set instead
1319 */
wl18xx_sta_get_ap_rate_mask(struct wl1271 * wl,struct wl12xx_vif * wlvif)1320 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1321 struct wl12xx_vif *wlvif)
1322 {
1323 u32 hw_rate_set = wlvif->rate_set;
1324
1325 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1326 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1327 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1328 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
1329
1330 /* we don't support MIMO in wide-channel mode */
1331 hw_rate_set &= ~CONF_TX_MIMO_RATES;
1332 } else if (wl18xx_is_mimo_supported(wl)) {
1333 wl1271_debug(DEBUG_ACX, "using MIMO channel rate mask");
1334 hw_rate_set |= CONF_TX_MIMO_RATES;
1335 }
1336
1337 return hw_rate_set;
1338 }
1339
wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 * wl,struct wl12xx_vif * wlvif)1340 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
1341 struct wl12xx_vif *wlvif)
1342 {
1343 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1344 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1345 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1346
1347 /* sanity check - we don't support this */
1348 if (WARN_ON(wlvif->band != NL80211_BAND_5GHZ))
1349 return 0;
1350
1351 return CONF_TX_RATE_USE_WIDE_CHAN;
1352 } else if (wl18xx_is_mimo_supported(wl) &&
1353 wlvif->band == NL80211_BAND_2GHZ) {
1354 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
1355 /*
1356 * we don't care about HT channel here - if a peer doesn't
1357 * support MIMO, we won't enable it in its rates
1358 */
1359 return CONF_TX_MIMO_RATES;
1360 } else {
1361 return 0;
1362 }
1363 }
1364
wl18xx_rdl_name(enum wl18xx_rdl_num rdl_num)1365 static const char *wl18xx_rdl_name(enum wl18xx_rdl_num rdl_num)
1366 {
1367 switch (rdl_num) {
1368 case RDL_1_HP:
1369 return "183xH";
1370 case RDL_2_SP:
1371 return "183x or 180x";
1372 case RDL_3_HP:
1373 return "187xH";
1374 case RDL_4_SP:
1375 return "187x";
1376 case RDL_5_SP:
1377 return "RDL11 - Not Supported";
1378 case RDL_6_SP:
1379 return "180xD";
1380 case RDL_7_SP:
1381 return "RDL13 - Not Supported (1893Q)";
1382 case RDL_8_SP:
1383 return "18xxQ";
1384 case RDL_NONE:
1385 return "UNTRIMMED";
1386 default:
1387 return "UNKNOWN";
1388 }
1389 }
1390
wl18xx_get_pg_ver(struct wl1271 * wl,s8 * ver)1391 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1392 {
1393 u32 fuse;
1394 s8 rom = 0, metal = 0, pg_ver = 0, rdl_ver = 0, package_type = 0;
1395 int ret;
1396
1397 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1398 if (ret < 0)
1399 goto out;
1400
1401 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse);
1402 if (ret < 0)
1403 goto out;
1404
1405 package_type = (fuse >> WL18XX_PACKAGE_TYPE_OFFSET) & 1;
1406
1407 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse);
1408 if (ret < 0)
1409 goto out;
1410
1411 pg_ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
1412 rom = (fuse & WL18XX_ROM_VER_MASK) >> WL18XX_ROM_VER_OFFSET;
1413
1414 if ((rom <= 0xE) && (package_type == WL18XX_PACKAGE_TYPE_WSP))
1415 metal = (fuse & WL18XX_METAL_VER_MASK) >>
1416 WL18XX_METAL_VER_OFFSET;
1417 else
1418 metal = (fuse & WL18XX_NEW_METAL_VER_MASK) >>
1419 WL18XX_NEW_METAL_VER_OFFSET;
1420
1421 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse);
1422 if (ret < 0)
1423 goto out;
1424
1425 rdl_ver = (fuse & WL18XX_RDL_VER_MASK) >> WL18XX_RDL_VER_OFFSET;
1426
1427 wl1271_info("wl18xx HW: %s, PG %d.%d (ROM 0x%x)",
1428 wl18xx_rdl_name(rdl_ver), pg_ver, metal, rom);
1429
1430 if (ver)
1431 *ver = pg_ver;
1432
1433 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
1434
1435 out:
1436 return ret;
1437 }
1438
wl18xx_load_conf_file(struct device * dev,struct wlcore_conf * conf,struct wl18xx_priv_conf * priv_conf,const char * file)1439 static int wl18xx_load_conf_file(struct device *dev, struct wlcore_conf *conf,
1440 struct wl18xx_priv_conf *priv_conf,
1441 const char *file)
1442 {
1443 struct wlcore_conf_file *conf_file;
1444 const struct firmware *fw;
1445 int ret;
1446
1447 ret = request_firmware(&fw, file, dev);
1448 if (ret < 0) {
1449 wl1271_error("could not get configuration binary %s: %d",
1450 file, ret);
1451 return ret;
1452 }
1453
1454 if (fw->size != WL18XX_CONF_SIZE) {
1455 wl1271_error("%s configuration binary size is wrong, expected %zu got %zu",
1456 file, WL18XX_CONF_SIZE, fw->size);
1457 ret = -EINVAL;
1458 goto out_release;
1459 }
1460
1461 conf_file = (struct wlcore_conf_file *) fw->data;
1462
1463 if (conf_file->header.magic != cpu_to_le32(WL18XX_CONF_MAGIC)) {
1464 wl1271_error("configuration binary file magic number mismatch, "
1465 "expected 0x%0x got 0x%0x", WL18XX_CONF_MAGIC,
1466 conf_file->header.magic);
1467 ret = -EINVAL;
1468 goto out_release;
1469 }
1470
1471 if (conf_file->header.version != cpu_to_le32(WL18XX_CONF_VERSION)) {
1472 wl1271_error("configuration binary file version not supported, "
1473 "expected 0x%08x got 0x%08x",
1474 WL18XX_CONF_VERSION, conf_file->header.version);
1475 ret = -EINVAL;
1476 goto out_release;
1477 }
1478
1479 memcpy(conf, &conf_file->core, sizeof(*conf));
1480 memcpy(priv_conf, &conf_file->priv, sizeof(*priv_conf));
1481
1482 out_release:
1483 release_firmware(fw);
1484 return ret;
1485 }
1486
wl18xx_conf_init(struct wl1271 * wl,struct device * dev)1487 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev)
1488 {
1489 struct platform_device *pdev = wl->pdev;
1490 struct wlcore_platdev_data *pdata = dev_get_platdata(&pdev->dev);
1491 struct wl18xx_priv *priv = wl->priv;
1492
1493 if (wl18xx_load_conf_file(dev, &wl->conf, &priv->conf,
1494 pdata->family->cfg_name) < 0) {
1495 wl1271_warning("falling back to default config");
1496
1497 /* apply driver default configuration */
1498 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl->conf));
1499 /* apply default private configuration */
1500 memcpy(&priv->conf, &wl18xx_default_priv_conf,
1501 sizeof(priv->conf));
1502 }
1503
1504 return 0;
1505 }
1506
wl18xx_plt_init(struct wl1271 * wl)1507 static int wl18xx_plt_init(struct wl1271 *wl)
1508 {
1509 int ret;
1510
1511 /* calibrator based auto/fem detect not supported for 18xx */
1512 if (wl->plt_mode == PLT_FEM_DETECT) {
1513 wl1271_error("wl18xx_plt_init: PLT FEM_DETECT not supported");
1514 return -EINVAL;
1515 }
1516
1517 ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1518 if (ret < 0)
1519 return ret;
1520
1521 return wl->ops->boot(wl);
1522 }
1523
wl18xx_get_mac(struct wl1271 * wl)1524 static int wl18xx_get_mac(struct wl1271 *wl)
1525 {
1526 u32 mac1, mac2;
1527 int ret;
1528
1529 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1530 if (ret < 0)
1531 goto out;
1532
1533 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1);
1534 if (ret < 0)
1535 goto out;
1536
1537 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2);
1538 if (ret < 0)
1539 goto out;
1540
1541 /* these are the two parts of the BD_ADDR */
1542 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1543 ((mac1 & 0xff000000) >> 24);
1544 wl->fuse_nic_addr = (mac1 & 0xffffff);
1545
1546 if (!wl->fuse_oui_addr && !wl->fuse_nic_addr) {
1547 u8 mac[ETH_ALEN];
1548
1549 eth_random_addr(mac);
1550
1551 wl->fuse_oui_addr = (mac[0] << 16) + (mac[1] << 8) + mac[2];
1552 wl->fuse_nic_addr = (mac[3] << 16) + (mac[4] << 8) + mac[5];
1553 wl1271_warning("MAC address from fuse not available, using random locally administered addresses.");
1554 }
1555
1556 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1557
1558 out:
1559 return ret;
1560 }
1561
wl18xx_handle_static_data(struct wl1271 * wl,struct wl1271_static_data * static_data)1562 static int wl18xx_handle_static_data(struct wl1271 *wl,
1563 struct wl1271_static_data *static_data)
1564 {
1565 struct wl18xx_static_data_priv *static_data_priv =
1566 (struct wl18xx_static_data_priv *) static_data->priv;
1567 size_t fw_status_len;
1568
1569 strscpy(wl->chip.phy_fw_ver_str, static_data_priv->phy_version,
1570 sizeof(wl->chip.phy_fw_ver_str));
1571
1572 wl1271_info("PHY firmware version: %s", static_data_priv->phy_version);
1573
1574 /* Adjust the firmware status size according to the firmware version */
1575 if (wl->chip.fw_ver[FW_VER_MAJOR] == 0)
1576 fw_status_len = sizeof(struct wl18xx_fw_status);
1577 else
1578 fw_status_len = sizeof(struct wl18xx_fw_status_8_9_1);
1579
1580 if (wl->fw_status_len != fw_status_len) {
1581 void *new_status = krealloc(wl->raw_fw_status, fw_status_len,
1582 GFP_KERNEL | __GFP_ZERO);
1583 if (!new_status)
1584 return -ENOMEM;
1585
1586 wl->raw_fw_status = new_status;
1587 wl->fw_status_len = fw_status_len;
1588 }
1589
1590 return 0;
1591 }
1592
wl18xx_get_spare_blocks(struct wl1271 * wl,bool is_gem)1593 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1594 {
1595 struct wl18xx_priv *priv = wl->priv;
1596
1597 /* If we have keys requiring extra spare, indulge them */
1598 if (priv->extra_spare_key_count)
1599 return WL18XX_TX_HW_EXTRA_BLOCK_SPARE;
1600
1601 return WL18XX_TX_HW_BLOCK_SPARE;
1602 }
1603
wl18xx_set_key(struct wl1271 * wl,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key_conf)1604 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1605 struct ieee80211_vif *vif,
1606 struct ieee80211_sta *sta,
1607 struct ieee80211_key_conf *key_conf)
1608 {
1609 struct wl18xx_priv *priv = wl->priv;
1610 bool change_spare = false, special_enc;
1611 int ret;
1612
1613 wl1271_debug(DEBUG_CRYPT, "extra spare keys before: %d",
1614 priv->extra_spare_key_count);
1615
1616 special_enc = key_conf->cipher == WL1271_CIPHER_SUITE_GEM ||
1617 key_conf->cipher == WLAN_CIPHER_SUITE_TKIP;
1618
1619 ret = wlcore_set_key(wl, cmd, vif, sta, key_conf);
1620 if (ret < 0)
1621 goto out;
1622
1623 /*
1624 * when adding the first or removing the last GEM/TKIP key,
1625 * we have to adjust the number of spare blocks.
1626 */
1627 if (special_enc) {
1628 if (cmd == SET_KEY) {
1629 /* first key */
1630 change_spare = (priv->extra_spare_key_count == 0);
1631 priv->extra_spare_key_count++;
1632 } else if (cmd == DISABLE_KEY) {
1633 /* last key */
1634 change_spare = (priv->extra_spare_key_count == 1);
1635 priv->extra_spare_key_count--;
1636 }
1637 }
1638
1639 wl1271_debug(DEBUG_CRYPT, "extra spare keys after: %d",
1640 priv->extra_spare_key_count);
1641
1642 if (!change_spare)
1643 goto out;
1644
1645 /* key is now set, change the spare blocks */
1646 if (priv->extra_spare_key_count)
1647 ret = wl18xx_set_host_cfg_bitmap(wl,
1648 WL18XX_TX_HW_EXTRA_BLOCK_SPARE);
1649 else
1650 ret = wl18xx_set_host_cfg_bitmap(wl,
1651 WL18XX_TX_HW_BLOCK_SPARE);
1652
1653 out:
1654 return ret;
1655 }
1656
wl18xx_pre_pkt_send(struct wl1271 * wl,u32 buf_offset,u32 last_len)1657 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl,
1658 u32 buf_offset, u32 last_len)
1659 {
1660 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) {
1661 struct wl1271_tx_hw_descr *last_desc;
1662
1663 /* get the last TX HW descriptor written to the aggr buf */
1664 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf +
1665 buf_offset - last_len);
1666
1667 /* the last frame is padded up to an SDIO block */
1668 last_desc->wl18xx_mem.ctrl &= ~WL18XX_TX_CTRL_NOT_PADDED;
1669 return ALIGN(buf_offset, WL12XX_BUS_BLOCK_SIZE);
1670 }
1671
1672 /* no modifications */
1673 return buf_offset;
1674 }
1675
wl18xx_sta_rc_update(struct wl1271 * wl,struct wl12xx_vif * wlvif)1676 static void wl18xx_sta_rc_update(struct wl1271 *wl,
1677 struct wl12xx_vif *wlvif)
1678 {
1679 bool wide = wlvif->rc_update_bw >= IEEE80211_STA_RX_BW_40;
1680
1681 wl1271_debug(DEBUG_MAC80211, "mac80211 sta_rc_update wide %d", wide);
1682
1683 /* sanity */
1684 if (WARN_ON(wlvif->bss_type != BSS_TYPE_STA_BSS))
1685 return;
1686
1687 /* ignore the change before association */
1688 if (!test_bit(WLVIF_FLAG_STA_ASSOCIATED, &wlvif->flags))
1689 return;
1690
1691 /*
1692 * If we started out as wide, we can change the operation mode. If we
1693 * thought this was a 20mhz AP, we have to reconnect
1694 */
1695 if (wlvif->sta.role_chan_type == NL80211_CHAN_HT40MINUS ||
1696 wlvif->sta.role_chan_type == NL80211_CHAN_HT40PLUS)
1697 wl18xx_acx_peer_ht_operation_mode(wl, wlvif->sta.hlid, wide);
1698 else
1699 ieee80211_connection_loss(wl12xx_wlvif_to_vif(wlvif));
1700 }
1701
wl18xx_set_peer_cap(struct wl1271 * wl,struct ieee80211_sta_ht_cap * ht_cap,bool allow_ht_operation,u32 rate_set,u8 hlid)1702 static int wl18xx_set_peer_cap(struct wl1271 *wl,
1703 struct ieee80211_sta_ht_cap *ht_cap,
1704 bool allow_ht_operation,
1705 u32 rate_set, u8 hlid)
1706 {
1707 return wl18xx_acx_set_peer_cap(wl, ht_cap, allow_ht_operation,
1708 rate_set, hlid);
1709 }
1710
wl18xx_lnk_high_prio(struct wl1271 * wl,u8 hlid,struct wl1271_link * lnk)1711 static bool wl18xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1712 struct wl1271_link *lnk)
1713 {
1714 u8 thold;
1715 struct wl18xx_fw_status_priv *status_priv =
1716 (struct wl18xx_fw_status_priv *)wl->fw_status->priv;
1717 unsigned long suspend_bitmap;
1718
1719 /* if we don't have the link map yet, assume they all low prio */
1720 if (!status_priv)
1721 return false;
1722
1723 /* suspended links are never high priority */
1724 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap);
1725 if (test_bit(hlid, &suspend_bitmap))
1726 return false;
1727
1728 /* the priority thresholds are taken from FW */
1729 if (test_bit(hlid, &wl->fw_fast_lnk_map) &&
1730 !test_bit(hlid, &wl->ap_fw_ps_map))
1731 thold = status_priv->tx_fast_link_prio_threshold;
1732 else
1733 thold = status_priv->tx_slow_link_prio_threshold;
1734
1735 return lnk->allocated_pkts < thold;
1736 }
1737
wl18xx_lnk_low_prio(struct wl1271 * wl,u8 hlid,struct wl1271_link * lnk)1738 static bool wl18xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1739 struct wl1271_link *lnk)
1740 {
1741 u8 thold;
1742 struct wl18xx_fw_status_priv *status_priv =
1743 (struct wl18xx_fw_status_priv *)wl->fw_status->priv;
1744 unsigned long suspend_bitmap;
1745
1746 /* if we don't have the link map yet, assume they all low prio */
1747 if (!status_priv)
1748 return true;
1749
1750 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap);
1751 if (test_bit(hlid, &suspend_bitmap))
1752 thold = status_priv->tx_suspend_threshold;
1753 else if (test_bit(hlid, &wl->fw_fast_lnk_map) &&
1754 !test_bit(hlid, &wl->ap_fw_ps_map))
1755 thold = status_priv->tx_fast_stop_threshold;
1756 else
1757 thold = status_priv->tx_slow_stop_threshold;
1758
1759 return lnk->allocated_pkts < thold;
1760 }
1761
wl18xx_convert_hwaddr(struct wl1271 * wl,u32 hwaddr)1762 static u32 wl18xx_convert_hwaddr(struct wl1271 *wl, u32 hwaddr)
1763 {
1764 return hwaddr & ~0x80000000;
1765 }
1766
1767 static int wl18xx_setup(struct wl1271 *wl);
1768
1769 static struct wlcore_ops wl18xx_ops = {
1770 .setup = wl18xx_setup,
1771 .identify_chip = wl18xx_identify_chip,
1772 .boot = wl18xx_boot,
1773 .plt_init = wl18xx_plt_init,
1774 .trigger_cmd = wl18xx_trigger_cmd,
1775 .ack_event = wl18xx_ack_event,
1776 .wait_for_event = wl18xx_wait_for_event,
1777 .process_mailbox_events = wl18xx_process_mailbox_events,
1778 .calc_tx_blocks = wl18xx_calc_tx_blocks,
1779 .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
1780 .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
1781 .get_rx_buf_align = wl18xx_get_rx_buf_align,
1782 .get_rx_packet_len = wl18xx_get_rx_packet_len,
1783 .tx_immediate_compl = wl18xx_tx_immediate_completion,
1784 .tx_delayed_compl = NULL,
1785 .hw_init = wl18xx_hw_init,
1786 .convert_fw_status = wl18xx_convert_fw_status,
1787 .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
1788 .get_pg_ver = wl18xx_get_pg_ver,
1789 .set_rx_csum = wl18xx_set_rx_csum,
1790 .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
1791 .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
1792 .get_mac = wl18xx_get_mac,
1793 .debugfs_init = wl18xx_debugfs_add_files,
1794 .scan_start = wl18xx_scan_start,
1795 .scan_stop = wl18xx_scan_stop,
1796 .sched_scan_start = wl18xx_sched_scan_start,
1797 .sched_scan_stop = wl18xx_scan_sched_scan_stop,
1798 .handle_static_data = wl18xx_handle_static_data,
1799 .get_spare_blocks = wl18xx_get_spare_blocks,
1800 .set_key = wl18xx_set_key,
1801 .channel_switch = wl18xx_cmd_channel_switch,
1802 .pre_pkt_send = wl18xx_pre_pkt_send,
1803 .sta_rc_update = wl18xx_sta_rc_update,
1804 .set_peer_cap = wl18xx_set_peer_cap,
1805 .convert_hwaddr = wl18xx_convert_hwaddr,
1806 .lnk_high_prio = wl18xx_lnk_high_prio,
1807 .lnk_low_prio = wl18xx_lnk_low_prio,
1808 .smart_config_start = wl18xx_cmd_smart_config_start,
1809 .smart_config_stop = wl18xx_cmd_smart_config_stop,
1810 .smart_config_set_group_key = wl18xx_cmd_smart_config_set_group_key,
1811 .interrupt_notify = wl18xx_acx_interrupt_notify_config,
1812 .rx_ba_filter = wl18xx_acx_rx_ba_filter,
1813 .ap_sleep = wl18xx_acx_ap_sleep,
1814 .set_cac = wl18xx_cmd_set_cac,
1815 .dfs_master_restart = wl18xx_cmd_dfs_master_restart,
1816 };
1817
1818 /* HT cap appropriate for wide channels in 2Ghz */
1819 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_2ghz = {
1820 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1821 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40 |
1822 IEEE80211_HT_CAP_GRN_FLD,
1823 .ht_supported = true,
1824 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1825 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1826 .mcs = {
1827 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1828 .rx_highest = cpu_to_le16(150),
1829 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1830 },
1831 };
1832
1833 /* HT cap appropriate for wide channels in 5Ghz */
1834 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_5ghz = {
1835 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1836 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1837 IEEE80211_HT_CAP_GRN_FLD,
1838 .ht_supported = true,
1839 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1840 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1841 .mcs = {
1842 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1843 .rx_highest = cpu_to_le16(150),
1844 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1845 },
1846 };
1847
1848 /* HT cap appropriate for SISO 20 */
1849 static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
1850 .cap = IEEE80211_HT_CAP_SGI_20 |
1851 IEEE80211_HT_CAP_GRN_FLD,
1852 .ht_supported = true,
1853 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1854 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1855 .mcs = {
1856 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1857 .rx_highest = cpu_to_le16(72),
1858 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1859 },
1860 };
1861
1862 /* HT cap appropriate for MIMO rates in 20mhz channel */
1863 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = {
1864 .cap = IEEE80211_HT_CAP_SGI_20 |
1865 IEEE80211_HT_CAP_GRN_FLD,
1866 .ht_supported = true,
1867 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1868 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1869 .mcs = {
1870 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1871 .rx_highest = cpu_to_le16(144),
1872 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1873 },
1874 };
1875
1876 static const struct ieee80211_iface_limit wl18xx_iface_limits[] = {
1877 {
1878 .max = 2,
1879 .types = BIT(NL80211_IFTYPE_STATION),
1880 },
1881 {
1882 .max = 1,
1883 .types = BIT(NL80211_IFTYPE_AP)
1884 | BIT(NL80211_IFTYPE_P2P_GO)
1885 | BIT(NL80211_IFTYPE_P2P_CLIENT)
1886 #ifdef CONFIG_MAC80211_MESH
1887 | BIT(NL80211_IFTYPE_MESH_POINT)
1888 #endif
1889 },
1890 {
1891 .max = 1,
1892 .types = BIT(NL80211_IFTYPE_P2P_DEVICE),
1893 },
1894 };
1895
1896 static const struct ieee80211_iface_limit wl18xx_iface_ap_limits[] = {
1897 {
1898 .max = 2,
1899 .types = BIT(NL80211_IFTYPE_AP),
1900 },
1901 #ifdef CONFIG_MAC80211_MESH
1902 {
1903 .max = 1,
1904 .types = BIT(NL80211_IFTYPE_MESH_POINT),
1905 },
1906 #endif
1907 {
1908 .max = 1,
1909 .types = BIT(NL80211_IFTYPE_P2P_DEVICE),
1910 },
1911 };
1912
1913 static const struct ieee80211_iface_combination
1914 wl18xx_iface_combinations[] = {
1915 {
1916 .max_interfaces = 3,
1917 .limits = wl18xx_iface_limits,
1918 .n_limits = ARRAY_SIZE(wl18xx_iface_limits),
1919 .num_different_channels = 2,
1920 },
1921 {
1922 .max_interfaces = 2,
1923 .limits = wl18xx_iface_ap_limits,
1924 .n_limits = ARRAY_SIZE(wl18xx_iface_ap_limits),
1925 .num_different_channels = 1,
1926 .radar_detect_widths = BIT(NL80211_CHAN_NO_HT) |
1927 BIT(NL80211_CHAN_HT20) |
1928 BIT(NL80211_CHAN_HT40MINUS) |
1929 BIT(NL80211_CHAN_HT40PLUS),
1930 }
1931 };
1932
wl18xx_setup(struct wl1271 * wl)1933 static int wl18xx_setup(struct wl1271 *wl)
1934 {
1935 struct wl18xx_priv *priv = wl->priv;
1936 int ret;
1937
1938 BUILD_BUG_ON(WL18XX_MAX_LINKS > WLCORE_MAX_LINKS);
1939 BUILD_BUG_ON(WL18XX_MAX_AP_STATIONS > WL18XX_MAX_LINKS);
1940 BUILD_BUG_ON(WL18XX_CONF_SG_PARAMS_MAX > WLCORE_CONF_SG_PARAMS_MAX);
1941
1942 wl->rtable = wl18xx_rtable;
1943 wl->num_tx_desc = WL18XX_NUM_TX_DESCRIPTORS;
1944 wl->num_rx_desc = WL18XX_NUM_RX_DESCRIPTORS;
1945 wl->num_links = WL18XX_MAX_LINKS;
1946 wl->max_ap_stations = WL18XX_MAX_AP_STATIONS;
1947 wl->iface_combinations = wl18xx_iface_combinations;
1948 wl->n_iface_combinations = ARRAY_SIZE(wl18xx_iface_combinations);
1949 wl->num_mac_addr = WL18XX_NUM_MAC_ADDRESSES;
1950 wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1951 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1952 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1953 wl->fw_status_len = sizeof(struct wl18xx_fw_status);
1954 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1955 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
1956 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
1957
1958 if (num_rx_desc_param != -1)
1959 wl->num_rx_desc = num_rx_desc_param;
1960
1961 ret = wl18xx_conf_init(wl, wl->dev);
1962 if (ret < 0)
1963 return ret;
1964
1965 /* If the module param is set, update it in conf */
1966 if (board_type_param) {
1967 if (!strcmp(board_type_param, "fpga")) {
1968 priv->conf.phy.board_type = BOARD_TYPE_FPGA_18XX;
1969 } else if (!strcmp(board_type_param, "hdk")) {
1970 priv->conf.phy.board_type = BOARD_TYPE_HDK_18XX;
1971 } else if (!strcmp(board_type_param, "dvp")) {
1972 priv->conf.phy.board_type = BOARD_TYPE_DVP_18XX;
1973 } else if (!strcmp(board_type_param, "evb")) {
1974 priv->conf.phy.board_type = BOARD_TYPE_EVB_18XX;
1975 } else if (!strcmp(board_type_param, "com8")) {
1976 priv->conf.phy.board_type = BOARD_TYPE_COM8_18XX;
1977 } else {
1978 wl1271_error("invalid board type '%s'",
1979 board_type_param);
1980 return -EINVAL;
1981 }
1982 }
1983
1984 if (priv->conf.phy.board_type >= NUM_BOARD_TYPES) {
1985 wl1271_error("invalid board type '%d'",
1986 priv->conf.phy.board_type);
1987 return -EINVAL;
1988 }
1989
1990 if (low_band_component_param != -1)
1991 priv->conf.phy.low_band_component = low_band_component_param;
1992 if (low_band_component_type_param != -1)
1993 priv->conf.phy.low_band_component_type =
1994 low_band_component_type_param;
1995 if (high_band_component_param != -1)
1996 priv->conf.phy.high_band_component = high_band_component_param;
1997 if (high_band_component_type_param != -1)
1998 priv->conf.phy.high_band_component_type =
1999 high_band_component_type_param;
2000 if (pwr_limit_reference_11_abg_param != -1)
2001 priv->conf.phy.pwr_limit_reference_11_abg =
2002 pwr_limit_reference_11_abg_param;
2003 if (n_antennas_2_param != -1)
2004 priv->conf.phy.number_of_assembled_ant2_4 = n_antennas_2_param;
2005 if (n_antennas_5_param != -1)
2006 priv->conf.phy.number_of_assembled_ant5 = n_antennas_5_param;
2007 if (dc2dc_param != -1)
2008 priv->conf.phy.external_pa_dc2dc = dc2dc_param;
2009
2010 if (ht_mode_param) {
2011 if (!strcmp(ht_mode_param, "default"))
2012 priv->conf.ht.mode = HT_MODE_DEFAULT;
2013 else if (!strcmp(ht_mode_param, "wide"))
2014 priv->conf.ht.mode = HT_MODE_WIDE;
2015 else if (!strcmp(ht_mode_param, "siso20"))
2016 priv->conf.ht.mode = HT_MODE_SISO20;
2017 else {
2018 wl1271_error("invalid ht_mode '%s'", ht_mode_param);
2019 return -EINVAL;
2020 }
2021 }
2022
2023 if (priv->conf.ht.mode == HT_MODE_DEFAULT) {
2024 /*
2025 * Only support mimo with multiple antennas. Fall back to
2026 * siso40.
2027 */
2028 if (wl18xx_is_mimo_supported(wl))
2029 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ,
2030 &wl18xx_mimo_ht_cap_2ghz);
2031 else
2032 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ,
2033 &wl18xx_siso40_ht_cap_2ghz);
2034
2035 /* 5Ghz is always wide */
2036 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ,
2037 &wl18xx_siso40_ht_cap_5ghz);
2038 } else if (priv->conf.ht.mode == HT_MODE_WIDE) {
2039 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ,
2040 &wl18xx_siso40_ht_cap_2ghz);
2041 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ,
2042 &wl18xx_siso40_ht_cap_5ghz);
2043 } else if (priv->conf.ht.mode == HT_MODE_SISO20) {
2044 wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ,
2045 &wl18xx_siso20_ht_cap);
2046 wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ,
2047 &wl18xx_siso20_ht_cap);
2048 }
2049
2050 if (!checksum_param) {
2051 wl18xx_ops.set_rx_csum = NULL;
2052 wl18xx_ops.init_vif = NULL;
2053 }
2054
2055 /* Enable 11a Band only if we have 5G antennas */
2056 wl->enable_11a = (priv->conf.phy.number_of_assembled_ant5 != 0);
2057
2058 return 0;
2059 }
2060
wl18xx_probe(struct platform_device * pdev)2061 static int wl18xx_probe(struct platform_device *pdev)
2062 {
2063 struct wl1271 *wl;
2064 struct ieee80211_hw *hw;
2065 int ret;
2066
2067 hw = wlcore_alloc_hw(sizeof(struct wl18xx_priv),
2068 WL18XX_AGGR_BUFFER_SIZE,
2069 sizeof(struct wl18xx_event_mailbox));
2070 if (IS_ERR(hw)) {
2071 wl1271_error("can't allocate hw");
2072 ret = PTR_ERR(hw);
2073 goto out;
2074 }
2075
2076 wl = hw->priv;
2077 wl->ops = &wl18xx_ops;
2078 wl->ptable = wl18xx_ptable;
2079 ret = wlcore_probe(wl, pdev);
2080 if (ret)
2081 goto out_free;
2082
2083 return ret;
2084
2085 out_free:
2086 wlcore_free_hw(wl);
2087 out:
2088 return ret;
2089 }
2090
2091 static const struct platform_device_id wl18xx_id_table[] = {
2092 { "wl18xx", 0 },
2093 { } /* Terminating Entry */
2094 };
2095 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
2096
2097 static struct platform_driver wl18xx_driver = {
2098 .probe = wl18xx_probe,
2099 .remove = wlcore_remove,
2100 .id_table = wl18xx_id_table,
2101 .driver = {
2102 .name = "wl18xx_driver",
2103 }
2104 };
2105
2106 module_platform_driver(wl18xx_driver);
2107 module_param_named(ht_mode, ht_mode_param, charp, 0400);
2108 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or siso20");
2109
2110 module_param_named(board_type, board_type_param, charp, 0400);
2111 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
2112 "dvp");
2113
2114 module_param_named(checksum, checksum_param, bool, 0400);
2115 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to false)");
2116
2117 module_param_named(dc2dc, dc2dc_param, int, 0400);
2118 MODULE_PARM_DESC(dc2dc, "External DC2DC: u8 (defaults to 0)");
2119
2120 module_param_named(n_antennas_2, n_antennas_2_param, int, 0400);
2121 MODULE_PARM_DESC(n_antennas_2,
2122 "Number of installed 2.4GHz antennas: 1 (default) or 2");
2123
2124 module_param_named(n_antennas_5, n_antennas_5_param, int, 0400);
2125 MODULE_PARM_DESC(n_antennas_5,
2126 "Number of installed 5GHz antennas: 1 (default) or 2");
2127
2128 module_param_named(low_band_component, low_band_component_param, int, 0400);
2129 MODULE_PARM_DESC(low_band_component, "Low band component: u8 "
2130 "(default is 0x01)");
2131
2132 module_param_named(low_band_component_type, low_band_component_type_param,
2133 int, 0400);
2134 MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 "
2135 "(default is 0x05 or 0x06 depending on the board_type)");
2136
2137 module_param_named(high_band_component, high_band_component_param, int, 0400);
2138 MODULE_PARM_DESC(high_band_component, "High band component: u8, "
2139 "(default is 0x01)");
2140
2141 module_param_named(high_band_component_type, high_band_component_type_param,
2142 int, 0400);
2143 MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 "
2144 "(default is 0x09)");
2145
2146 module_param_named(pwr_limit_reference_11_abg,
2147 pwr_limit_reference_11_abg_param, int, 0400);
2148 MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 "
2149 "(default is 0xc8)");
2150
2151 module_param_named(num_rx_desc, num_rx_desc_param, int, 0400);
2152 MODULE_PARM_DESC(num_rx_desc_param,
2153 "Number of Rx descriptors: u8 (default is 32)");
2154
2155 MODULE_DESCRIPTION("TI WiLink 8 wireless driver");
2156 MODULE_LICENSE("GPL v2");
2157 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
2158 MODULE_FIRMWARE(WL18XX_FW_NAME);
2159