1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022-2026 Intel Corporation 4 */ 5 6 #ifndef _XE_TILE_TYPES_H_ 7 #define _XE_TILE_TYPES_H_ 8 9 #include <linux/mutex_types.h> 10 #include <linux/workqueue_types.h> 11 12 #include "xe_lmtt_types.h" 13 #include "xe_memirq_types.h" 14 #include "xe_mert.h" 15 #include "xe_mmio_types.h" 16 #include "xe_tile_sriov_vf_types.h" 17 18 #define tile_to_xe(tile__) \ 19 _Generic(tile__, \ 20 const struct xe_tile * : (const struct xe_device *)((tile__)->xe), \ 21 struct xe_tile * : (tile__)->xe) 22 23 /** 24 * struct xe_tile - hardware tile structure 25 * 26 * From a driver perspective, a "tile" is effectively a complete GPU, containing 27 * an SGunit, 1-2 GTs, and (for discrete platforms) VRAM. 28 * 29 * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI 30 * device and designate one "root" tile as being responsible for external PCI 31 * communication. PCI BAR0 exposes the GGTT and MMIO register space for each 32 * tile in a stacked layout, and PCI BAR2 exposes the local memory associated 33 * with each tile similarly. Device-wide interrupts can be enabled/disabled 34 * at the root tile, and the MSTR_TILE_INTR register will report which tiles 35 * have interrupts that need servicing. 36 */ 37 struct xe_tile { 38 /** @xe: Backpointer to tile's PCI device */ 39 struct xe_device *xe; 40 41 /** @id: ID of the tile */ 42 u8 id; 43 44 /** 45 * @primary_gt: Primary GT 46 */ 47 struct xe_gt *primary_gt; 48 49 /** 50 * @media_gt: Media GT 51 * 52 * Only present on devices with media version >= 13. 53 */ 54 struct xe_gt *media_gt; 55 56 /** 57 * @mmio: MMIO info for a tile. 58 * 59 * Each tile has its own 16MB space in BAR0, laid out as: 60 * * 0-4MB: registers 61 * * 4MB-8MB: reserved 62 * * 8MB-16MB: global GTT 63 */ 64 struct xe_mmio mmio; 65 66 /** @mem: memory management info for tile */ 67 struct { 68 /** 69 * @mem.kernel_vram: kernel-dedicated VRAM info for tile. 70 * 71 * Although VRAM is associated with a specific tile, it can 72 * still be accessed by all tiles' GTs. 73 */ 74 struct xe_vram_region *kernel_vram; 75 76 /** 77 * @mem.vram: general purpose VRAM info for tile. 78 * 79 * Although VRAM is associated with a specific tile, it can 80 * still be accessed by all tiles' GTs. 81 */ 82 struct xe_vram_region *vram; 83 84 /** @mem.ggtt: Global graphics translation table */ 85 struct xe_ggtt *ggtt; 86 87 /** 88 * @mem.kernel_bb_pool: Pool from which batchbuffers are allocated. 89 * 90 * Media GT shares a pool with its primary GT. 91 */ 92 struct xe_sa_manager *kernel_bb_pool; 93 94 /** 95 * @mem.reclaim_pool: Pool for PRLs allocated. 96 * 97 * Only main GT has page reclaim list allocations. 98 */ 99 struct xe_sa_manager *reclaim_pool; 100 } mem; 101 102 /** @sriov: tile level virtualization data */ 103 union { 104 struct { 105 /** @sriov.pf.lmtt: Local Memory Translation Table. */ 106 struct xe_lmtt lmtt; 107 } pf; 108 struct { 109 /** @sriov.vf.self_config: VF configuration data */ 110 struct xe_tile_sriov_vf_selfconfig self_config; 111 } vf; 112 } sriov; 113 114 /** @memirq: Memory Based Interrupts. */ 115 struct xe_memirq memirq; 116 117 /** @csc_hw_error_work: worker to report CSC HW errors */ 118 struct work_struct csc_hw_error_work; 119 120 /** @pcode: tile's PCODE */ 121 struct { 122 /** @pcode.lock: protecting tile's PCODE mailbox data */ 123 struct mutex lock; 124 } pcode; 125 126 /** @migrate: Migration helper for vram blits and clearing */ 127 struct xe_migrate *migrate; 128 129 /** @sysfs: sysfs' kobj used by xe_tile_sysfs */ 130 struct kobject *sysfs; 131 132 /** @debugfs: debugfs directory associated with this tile */ 133 struct dentry *debugfs; 134 135 /** @mert: MERT-related data */ 136 struct xe_mert mert; 137 }; 138 139 #endif 140