1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe driver for Marvell Armada 370 and Armada XP SoCs 4 * 5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/init.h> 16 #include <linux/irqchip/chained_irq.h> 17 #include <linux/irqdomain.h> 18 #include <linux/mbus.h> 19 #include <linux/slab.h> 20 #include <linux/platform_device.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_pci.h> 24 #include <linux/of_platform.h> 25 26 #include "../pci.h" 27 #include "../pci-bridge-emul.h" 28 29 /* 30 * PCIe unit register offsets. 31 */ 32 #define PCIE_DEV_ID_OFF 0x0000 33 #define PCIE_CMD_OFF 0x0004 34 #define PCIE_DEV_REV_OFF 0x0008 35 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) 36 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) 37 #define PCIE_SSDEV_ID_OFF 0x002c 38 #define PCIE_CAP_PCIEXP 0x0060 39 #define PCIE_CAP_PCIERR_OFF 0x0100 40 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) 41 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) 42 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) 43 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) 44 #define PCIE_WIN5_CTRL_OFF 0x1880 45 #define PCIE_WIN5_BASE_OFF 0x1884 46 #define PCIE_WIN5_REMAP_OFF 0x188c 47 #define PCIE_CONF_ADDR_OFF 0x18f8 48 #define PCIE_CONF_ADDR_EN 0x80000000 49 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) 50 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) 51 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) 52 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) 53 #define PCIE_CONF_ADDR(bus, devfn, where) \ 54 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ 55 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ 56 PCIE_CONF_ADDR_EN) 57 #define PCIE_CONF_DATA_OFF 0x18fc 58 #define PCIE_INT_CAUSE_OFF 0x1900 59 #define PCIE_INT_UNMASK_OFF 0x1910 60 #define PCIE_INT_INTX(i) BIT_U32(24 + (i)) 61 #define PCIE_INT_PM_PME BIT_U32(28) 62 #define PCIE_INT_ALL_MASK GENMASK_U32(31, 0) 63 #define PCIE_CTRL_OFF 0x1a00 64 #define PCIE_CTRL_X1_MODE 0x0001 65 #define PCIE_CTRL_RC_MODE BIT(1) 66 #define PCIE_CTRL_MASTER_HOT_RESET BIT(24) 67 #define PCIE_STAT_OFF 0x1a04 68 #define PCIE_STAT_BUS 0xff00 69 #define PCIE_STAT_DEV 0x1f0000 70 #define PCIE_STAT_LINK_DOWN BIT(0) 71 #define PCIE_SSPL_OFF 0x1a0c 72 #define PCIE_SSPL_VALUE_SHIFT 0 73 #define PCIE_SSPL_VALUE_MASK GENMASK(7, 0) 74 #define PCIE_SSPL_SCALE_SHIFT 8 75 #define PCIE_SSPL_SCALE_MASK GENMASK(9, 8) 76 #define PCIE_SSPL_ENABLE BIT(16) 77 #define PCIE_RC_RTSTA 0x1a14 78 #define PCIE_DEBUG_CTRL 0x1a60 79 #define PCIE_DEBUG_SOFT_RESET BIT(20) 80 81 struct mvebu_pcie_port; 82 83 /* Structure representing all PCIe interfaces */ 84 struct mvebu_pcie { 85 struct platform_device *pdev; 86 struct mvebu_pcie_port *ports; 87 struct resource io; 88 struct resource realio; 89 struct resource mem; 90 int nports; 91 }; 92 93 struct mvebu_pcie_window { 94 phys_addr_t base; 95 phys_addr_t remap; 96 size_t size; 97 }; 98 99 /* Structure representing one PCIe interface */ 100 struct mvebu_pcie_port { 101 char *name; 102 void __iomem *base; 103 u32 port; 104 u32 lane; 105 bool is_x4; 106 int devfn; 107 unsigned int mem_target; 108 unsigned int mem_attr; 109 unsigned int io_target; 110 unsigned int io_attr; 111 struct clk *clk; 112 struct gpio_desc *reset_gpio; 113 char *reset_name; 114 struct pci_bridge_emul bridge; 115 struct device_node *dn; 116 struct mvebu_pcie *pcie; 117 struct mvebu_pcie_window memwin; 118 struct mvebu_pcie_window iowin; 119 u32 saved_pcie_stat; 120 struct resource regs; 121 u8 slot_power_limit_value; 122 u8 slot_power_limit_scale; 123 struct irq_domain *intx_irq_domain; 124 raw_spinlock_t irq_lock; 125 int intx_irq; 126 }; 127 128 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) 129 { 130 writel(val, port->base + reg); 131 } 132 133 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg) 134 { 135 return readl(port->base + reg); 136 } 137 138 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port) 139 { 140 return port->io_target != -1 && port->io_attr != -1; 141 } 142 143 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port) 144 { 145 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); 146 } 147 148 static u8 mvebu_pcie_get_local_bus_nr(struct mvebu_pcie_port *port) 149 { 150 return (mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_BUS) >> 8; 151 } 152 153 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr) 154 { 155 u32 stat; 156 157 stat = mvebu_readl(port, PCIE_STAT_OFF); 158 stat &= ~PCIE_STAT_BUS; 159 stat |= nr << 8; 160 mvebu_writel(port, stat, PCIE_STAT_OFF); 161 } 162 163 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) 164 { 165 u32 stat; 166 167 stat = mvebu_readl(port, PCIE_STAT_OFF); 168 stat &= ~PCIE_STAT_DEV; 169 stat |= nr << 16; 170 mvebu_writel(port, stat, PCIE_STAT_OFF); 171 } 172 173 static void mvebu_pcie_disable_wins(struct mvebu_pcie_port *port) 174 { 175 int i; 176 177 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(0)); 178 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0)); 179 180 for (i = 1; i < 3; i++) { 181 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i)); 182 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i)); 183 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i)); 184 } 185 186 for (i = 0; i < 5; i++) { 187 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i)); 188 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i)); 189 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); 190 } 191 192 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF); 193 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF); 194 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF); 195 } 196 197 /* 198 * Setup PCIE BARs and Address Decode Wins: 199 * BAR[0] -> internal registers (needed for MSI) 200 * BAR[1] -> covers all DRAM banks 201 * BAR[2] -> Disabled 202 * WIN[0-3] -> DRAM bank[0-3] 203 */ 204 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) 205 { 206 const struct mbus_dram_target_info *dram; 207 u32 size; 208 int i; 209 210 dram = mv_mbus_dram_info(); 211 212 /* First, disable and clear BARs and windows. */ 213 mvebu_pcie_disable_wins(port); 214 215 /* Setup windows for DDR banks. Count total DDR size on the fly. */ 216 size = 0; 217 for (i = 0; i < dram->num_cs; i++) { 218 const struct mbus_dram_window *cs = dram->cs + i; 219 220 mvebu_writel(port, cs->base & 0xffff0000, 221 PCIE_WIN04_BASE_OFF(i)); 222 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i)); 223 mvebu_writel(port, 224 ((cs->size - 1) & 0xffff0000) | 225 (cs->mbus_attr << 8) | 226 (dram->mbus_dram_target_id << 4) | 1, 227 PCIE_WIN04_CTRL_OFF(i)); 228 229 size += cs->size; 230 } 231 232 /* Round up 'size' to the nearest power of two. */ 233 if ((size & (size - 1)) != 0) 234 size = 1 << fls(size); 235 236 /* Setup BAR[1] to all DRAM banks. */ 237 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); 238 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1)); 239 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, 240 PCIE_BAR_CTRL_OFF(1)); 241 242 /* 243 * Point BAR[0] to the device's internal registers. 244 */ 245 mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0)); 246 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0)); 247 } 248 249 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) 250 { 251 u32 ctrl, lnkcap, cmd, dev_rev, unmask, sspl; 252 253 /* Setup PCIe controller to Root Complex mode. */ 254 ctrl = mvebu_readl(port, PCIE_CTRL_OFF); 255 ctrl |= PCIE_CTRL_RC_MODE; 256 mvebu_writel(port, ctrl, PCIE_CTRL_OFF); 257 258 /* 259 * Set Maximum Link Width to X1 or X4 in Root Port's PCIe Link 260 * Capability register. This register is defined by PCIe specification 261 * as read-only but this mvebu controller has it as read-write and must 262 * be set to number of SerDes PCIe lanes (1 or 4). If this register is 263 * not set correctly then link with endpoint card is not established. 264 */ 265 lnkcap = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); 266 FIELD_MODIFY(PCI_EXP_LNKCAP_MLW, &lnkcap, port->is_x4 ? 4 : 1); 267 mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP); 268 269 /* Disable Root Bridge I/O space, memory space and bus mastering. */ 270 cmd = mvebu_readl(port, PCIE_CMD_OFF); 271 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 272 mvebu_writel(port, cmd, PCIE_CMD_OFF); 273 274 /* 275 * Change Class Code of PCI Bridge device to PCI Bridge (0x6004) 276 * because default value is Memory controller (0x5080). 277 * 278 * Note that this mvebu PCI Bridge does not have compliant Type 1 279 * Configuration Space. Header Type is reported as Type 0 and it 280 * has format of Type 0 config space. 281 * 282 * Moreover Type 0 BAR registers (ranges 0x10 - 0x28 and 0x30 - 0x34) 283 * have the same format in Marvell's specification as in PCIe 284 * specification, but their meaning is totally different and they do 285 * different things: they are aliased into internal mvebu registers 286 * (e.g. PCIE_BAR_LO_OFF) and these should not be changed or 287 * reconfigured by pci device drivers. 288 * 289 * Therefore driver uses emulation of PCI Bridge which emulates 290 * access to configuration space via internal mvebu registers or 291 * emulated configuration buffer. Driver access these PCI Bridge 292 * directly for simplification, but these registers can be accessed 293 * also via standard mvebu way for accessing PCI config space. 294 */ 295 dev_rev = mvebu_readl(port, PCIE_DEV_REV_OFF); 296 dev_rev &= ~0xffffff00; 297 dev_rev |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; 298 mvebu_writel(port, dev_rev, PCIE_DEV_REV_OFF); 299 300 /* Point PCIe unit MBUS decode windows to DRAM space. */ 301 mvebu_pcie_setup_wins(port); 302 303 /* 304 * Program Root Port to automatically send Set_Slot_Power_Limit 305 * PCIe Message when changing status from Dl_Down to Dl_Up and valid 306 * slot power limit was specified. 307 */ 308 sspl = mvebu_readl(port, PCIE_SSPL_OFF); 309 sspl &= ~(PCIE_SSPL_VALUE_MASK | PCIE_SSPL_SCALE_MASK | PCIE_SSPL_ENABLE); 310 if (port->slot_power_limit_value) { 311 sspl |= port->slot_power_limit_value << PCIE_SSPL_VALUE_SHIFT; 312 sspl |= port->slot_power_limit_scale << PCIE_SSPL_SCALE_SHIFT; 313 sspl |= PCIE_SSPL_ENABLE; 314 } 315 mvebu_writel(port, sspl, PCIE_SSPL_OFF); 316 317 /* Mask all interrupt sources. */ 318 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF); 319 320 /* Clear all interrupt causes. */ 321 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF); 322 323 /* Check if "intx" interrupt was specified in DT. */ 324 if (port->intx_irq > 0) 325 return; 326 327 /* 328 * Fallback code when "intx" interrupt was not specified in DT: 329 * Unmask all legacy INTx interrupts as driver does not provide a way 330 * for masking and unmasking of individual legacy INTx interrupts. 331 * Legacy INTx are reported via one shared GIC source and therefore 332 * kernel cannot distinguish which individual legacy INTx was triggered. 333 * These interrupts are shared, so it should not cause any issue. Just 334 * performance penalty as every PCIe interrupt handler needs to be 335 * called when some interrupt is triggered. 336 */ 337 unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); 338 unmask |= PCIE_INT_INTX(0) | PCIE_INT_INTX(1) | 339 PCIE_INT_INTX(2) | PCIE_INT_INTX(3); 340 mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); 341 } 342 343 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie, 344 struct pci_bus *bus, 345 int devfn); 346 347 static int mvebu_pcie_child_rd_conf(struct pci_bus *bus, u32 devfn, int where, 348 int size, u32 *val) 349 { 350 struct mvebu_pcie *pcie = bus->sysdata; 351 struct mvebu_pcie_port *port; 352 void __iomem *conf_data; 353 354 port = mvebu_pcie_find_port(pcie, bus, devfn); 355 if (!port) 356 return PCIBIOS_DEVICE_NOT_FOUND; 357 358 if (!mvebu_pcie_link_up(port)) 359 return PCIBIOS_DEVICE_NOT_FOUND; 360 361 conf_data = port->base + PCIE_CONF_DATA_OFF; 362 363 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 364 PCIE_CONF_ADDR_OFF); 365 366 switch (size) { 367 case 1: 368 *val = readb_relaxed(conf_data + (where & 3)); 369 break; 370 case 2: 371 *val = readw_relaxed(conf_data + (where & 2)); 372 break; 373 case 4: 374 *val = readl_relaxed(conf_data); 375 break; 376 default: 377 return PCIBIOS_BAD_REGISTER_NUMBER; 378 } 379 380 return PCIBIOS_SUCCESSFUL; 381 } 382 383 static int mvebu_pcie_child_wr_conf(struct pci_bus *bus, u32 devfn, 384 int where, int size, u32 val) 385 { 386 struct mvebu_pcie *pcie = bus->sysdata; 387 struct mvebu_pcie_port *port; 388 void __iomem *conf_data; 389 390 port = mvebu_pcie_find_port(pcie, bus, devfn); 391 if (!port) 392 return PCIBIOS_DEVICE_NOT_FOUND; 393 394 if (!mvebu_pcie_link_up(port)) 395 return PCIBIOS_DEVICE_NOT_FOUND; 396 397 conf_data = port->base + PCIE_CONF_DATA_OFF; 398 399 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), 400 PCIE_CONF_ADDR_OFF); 401 402 switch (size) { 403 case 1: 404 writeb(val, conf_data + (where & 3)); 405 break; 406 case 2: 407 writew(val, conf_data + (where & 2)); 408 break; 409 case 4: 410 writel(val, conf_data); 411 break; 412 default: 413 return PCIBIOS_BAD_REGISTER_NUMBER; 414 } 415 416 return PCIBIOS_SUCCESSFUL; 417 } 418 419 static struct pci_ops mvebu_pcie_child_ops = { 420 .read = mvebu_pcie_child_rd_conf, 421 .write = mvebu_pcie_child_wr_conf, 422 }; 423 424 /* 425 * Remove windows, starting from the largest ones to the smallest 426 * ones. 427 */ 428 static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port, 429 phys_addr_t base, size_t size) 430 { 431 while (size) { 432 size_t sz = 1 << (fls(size) - 1); 433 434 mvebu_mbus_del_window(base, sz); 435 base += sz; 436 size -= sz; 437 } 438 } 439 440 /* 441 * MBus windows can only have a power of two size, but PCI BARs do not 442 * have this constraint. Therefore, we have to split the PCI BAR into 443 * areas each having a power of two size. We start from the largest 444 * one (i.e highest order bit set in the size). 445 */ 446 static int mvebu_pcie_add_windows(struct mvebu_pcie_port *port, 447 unsigned int target, unsigned int attribute, 448 phys_addr_t base, size_t size, 449 phys_addr_t remap) 450 { 451 size_t size_mapped = 0; 452 453 while (size) { 454 size_t sz = 1 << (fls(size) - 1); 455 int ret; 456 457 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base, 458 sz, remap); 459 if (ret) { 460 phys_addr_t end = base + sz - 1; 461 462 dev_err(&port->pcie->pdev->dev, 463 "Could not create MBus window at [mem %pa-%pa]: %d\n", 464 &base, &end, ret); 465 mvebu_pcie_del_windows(port, base - size_mapped, 466 size_mapped); 467 return ret; 468 } 469 470 size -= sz; 471 size_mapped += sz; 472 base += sz; 473 if (remap != MVEBU_MBUS_NO_REMAP) 474 remap += sz; 475 } 476 477 return 0; 478 } 479 480 static int mvebu_pcie_set_window(struct mvebu_pcie_port *port, 481 unsigned int target, unsigned int attribute, 482 const struct mvebu_pcie_window *desired, 483 struct mvebu_pcie_window *cur) 484 { 485 int ret; 486 487 if (desired->base == cur->base && desired->remap == cur->remap && 488 desired->size == cur->size) 489 return 0; 490 491 if (cur->size != 0) { 492 mvebu_pcie_del_windows(port, cur->base, cur->size); 493 cur->size = 0; 494 cur->base = 0; 495 496 /* 497 * If something tries to change the window while it is enabled 498 * the change will not be done atomically. That would be 499 * difficult to do in the general case. 500 */ 501 } 502 503 if (desired->size == 0) 504 return 0; 505 506 ret = mvebu_pcie_add_windows(port, target, attribute, desired->base, 507 desired->size, desired->remap); 508 if (ret) { 509 cur->size = 0; 510 cur->base = 0; 511 return ret; 512 } 513 514 *cur = *desired; 515 return 0; 516 } 517 518 static int mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port) 519 { 520 struct mvebu_pcie_window desired = {}; 521 struct pci_bridge_emul_conf *conf = &port->bridge.conf; 522 523 /* Are the new iobase/iolimit values invalid? */ 524 if (conf->iolimit < conf->iobase || 525 le16_to_cpu(conf->iolimitupper) < le16_to_cpu(conf->iobaseupper)) 526 return mvebu_pcie_set_window(port, port->io_target, port->io_attr, 527 &desired, &port->iowin); 528 529 /* 530 * We read the PCI-to-PCI bridge emulated registers, and 531 * calculate the base address and size of the address decoding 532 * window to setup, according to the PCI-to-PCI bridge 533 * specifications. iobase is the bus address, port->iowin_base 534 * is the CPU address. 535 */ 536 desired.remap = ((conf->iobase & 0xF0) << 8) | 537 (le16_to_cpu(conf->iobaseupper) << 16); 538 desired.base = port->pcie->io.start + desired.remap; 539 desired.size = ((0xFFF | ((conf->iolimit & 0xF0) << 8) | 540 (le16_to_cpu(conf->iolimitupper) << 16)) - 541 desired.remap) + 542 1; 543 544 return mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired, 545 &port->iowin); 546 } 547 548 static int mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port) 549 { 550 struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP}; 551 struct pci_bridge_emul_conf *conf = &port->bridge.conf; 552 553 /* Are the new membase/memlimit values invalid? */ 554 if (le16_to_cpu(conf->memlimit) < le16_to_cpu(conf->membase)) 555 return mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, 556 &desired, &port->memwin); 557 558 /* 559 * We read the PCI-to-PCI bridge emulated registers, and 560 * calculate the base address and size of the address decoding 561 * window to setup, according to the PCI-to-PCI bridge 562 * specifications. 563 */ 564 desired.base = ((le16_to_cpu(conf->membase) & 0xFFF0) << 16); 565 desired.size = (((le16_to_cpu(conf->memlimit) & 0xFFF0) << 16) | 0xFFFFF) - 566 desired.base + 1; 567 568 return mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired, 569 &port->memwin); 570 } 571 572 static pci_bridge_emul_read_status_t 573 mvebu_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge, 574 int reg, u32 *value) 575 { 576 struct mvebu_pcie_port *port = bridge->data; 577 578 switch (reg) { 579 case PCI_COMMAND: 580 *value = mvebu_readl(port, PCIE_CMD_OFF); 581 break; 582 583 case PCI_PRIMARY_BUS: { 584 /* 585 * From the whole 32bit register we support reading from HW only 586 * secondary bus number which is mvebu local bus number. 587 * Other bits are retrieved only from emulated config buffer. 588 */ 589 __le32 *cfgspace = (__le32 *)&bridge->conf; 590 u32 val = le32_to_cpu(cfgspace[PCI_PRIMARY_BUS / 4]); 591 val &= ~0xff00; 592 val |= mvebu_pcie_get_local_bus_nr(port) << 8; 593 *value = val; 594 break; 595 } 596 597 case PCI_INTERRUPT_LINE: { 598 /* 599 * From the whole 32bit register we support reading from HW only 600 * one bit: PCI_BRIDGE_CTL_BUS_RESET. 601 * Other bits are retrieved only from emulated config buffer. 602 */ 603 __le32 *cfgspace = (__le32 *)&bridge->conf; 604 u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]); 605 if (mvebu_readl(port, PCIE_CTRL_OFF) & PCIE_CTRL_MASTER_HOT_RESET) 606 val |= PCI_BRIDGE_CTL_BUS_RESET << 16; 607 else 608 val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16); 609 *value = val; 610 break; 611 } 612 613 default: 614 return PCI_BRIDGE_EMUL_NOT_HANDLED; 615 } 616 617 return PCI_BRIDGE_EMUL_HANDLED; 618 } 619 620 static pci_bridge_emul_read_status_t 621 mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, 622 int reg, u32 *value) 623 { 624 struct mvebu_pcie_port *port = bridge->data; 625 626 switch (reg) { 627 case PCI_EXP_DEVCAP: 628 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP); 629 break; 630 631 case PCI_EXP_DEVCTL: 632 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); 633 break; 634 635 case PCI_EXP_LNKCAP: 636 /* 637 * PCIe requires that the Clock Power Management capability bit 638 * is hard-wired to zero for downstream ports but HW returns 1. 639 * Additionally enable Data Link Layer Link Active Reporting 640 * Capable bit as DL_Active indication is provided too. 641 */ 642 *value = (mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) & 643 ~PCI_EXP_LNKCAP_CLKPM) | PCI_EXP_LNKCAP_DLLLARC; 644 break; 645 646 case PCI_EXP_LNKCTL: 647 /* DL_Active indication is provided via PCIE_STAT_OFF */ 648 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL) | 649 (mvebu_pcie_link_up(port) ? 650 (PCI_EXP_LNKSTA_DLLLA << 16) : 0); 651 break; 652 653 case PCI_EXP_SLTCTL: { 654 u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl); 655 u16 slotsta = le16_to_cpu(bridge->pcie_conf.slotsta); 656 u32 val = 0; 657 /* 658 * When slot power limit was not specified in DT then 659 * ASPL_DISABLE bit is stored only in emulated config space. 660 * Otherwise reflect status of PCIE_SSPL_ENABLE bit in HW. 661 */ 662 if (!port->slot_power_limit_value) 663 val |= slotctl & PCI_EXP_SLTCTL_ASPL_DISABLE; 664 else if (!(mvebu_readl(port, PCIE_SSPL_OFF) & PCIE_SSPL_ENABLE)) 665 val |= PCI_EXP_SLTCTL_ASPL_DISABLE; 666 /* This callback is 32-bit and in high bits is slot status. */ 667 val |= slotsta << 16; 668 *value = val; 669 break; 670 } 671 672 case PCI_EXP_RTSTA: 673 *value = mvebu_readl(port, PCIE_RC_RTSTA); 674 break; 675 676 case PCI_EXP_DEVCAP2: 677 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP2); 678 break; 679 680 case PCI_EXP_DEVCTL2: 681 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2); 682 break; 683 684 case PCI_EXP_LNKCTL2: 685 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2); 686 break; 687 688 default: 689 return PCI_BRIDGE_EMUL_NOT_HANDLED; 690 } 691 692 return PCI_BRIDGE_EMUL_HANDLED; 693 } 694 695 static pci_bridge_emul_read_status_t 696 mvebu_pci_bridge_emul_ext_conf_read(struct pci_bridge_emul *bridge, 697 int reg, u32 *value) 698 { 699 struct mvebu_pcie_port *port = bridge->data; 700 701 switch (reg) { 702 case 0: 703 case PCI_ERR_UNCOR_STATUS: 704 case PCI_ERR_UNCOR_MASK: 705 case PCI_ERR_UNCOR_SEVER: 706 case PCI_ERR_COR_STATUS: 707 case PCI_ERR_COR_MASK: 708 case PCI_ERR_CAP: 709 case PCI_ERR_HEADER_LOG+0: 710 case PCI_ERR_HEADER_LOG+4: 711 case PCI_ERR_HEADER_LOG+8: 712 case PCI_ERR_HEADER_LOG+12: 713 case PCI_ERR_ROOT_COMMAND: 714 case PCI_ERR_ROOT_STATUS: 715 case PCI_ERR_ROOT_ERR_SRC: 716 *value = mvebu_readl(port, PCIE_CAP_PCIERR_OFF + reg); 717 break; 718 719 default: 720 return PCI_BRIDGE_EMUL_NOT_HANDLED; 721 } 722 723 return PCI_BRIDGE_EMUL_HANDLED; 724 } 725 726 static void 727 mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge, 728 int reg, u32 old, u32 new, u32 mask) 729 { 730 struct mvebu_pcie_port *port = bridge->data; 731 struct pci_bridge_emul_conf *conf = &bridge->conf; 732 733 switch (reg) { 734 case PCI_COMMAND: 735 mvebu_writel(port, new, PCIE_CMD_OFF); 736 break; 737 738 case PCI_IO_BASE: 739 if ((mask & 0xffff) && mvebu_has_ioport(port) && 740 mvebu_pcie_handle_iobase_change(port)) { 741 /* On error disable IO range */ 742 conf->iobase &= ~0xf0; 743 conf->iolimit &= ~0xf0; 744 conf->iobase |= 0xf0; 745 conf->iobaseupper = cpu_to_le16(0x0000); 746 conf->iolimitupper = cpu_to_le16(0x0000); 747 } 748 break; 749 750 case PCI_MEMORY_BASE: 751 if (mvebu_pcie_handle_membase_change(port)) { 752 /* On error disable mem range */ 753 conf->membase = cpu_to_le16(le16_to_cpu(conf->membase) & ~0xfff0); 754 conf->memlimit = cpu_to_le16(le16_to_cpu(conf->memlimit) & ~0xfff0); 755 conf->membase = cpu_to_le16(le16_to_cpu(conf->membase) | 0xfff0); 756 } 757 break; 758 759 case PCI_IO_BASE_UPPER16: 760 if (mvebu_has_ioport(port) && 761 mvebu_pcie_handle_iobase_change(port)) { 762 /* On error disable IO range */ 763 conf->iobase &= ~0xf0; 764 conf->iolimit &= ~0xf0; 765 conf->iobase |= 0xf0; 766 conf->iobaseupper = cpu_to_le16(0x0000); 767 conf->iolimitupper = cpu_to_le16(0x0000); 768 } 769 break; 770 771 case PCI_PRIMARY_BUS: 772 if (mask & 0xff00) 773 mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus); 774 break; 775 776 case PCI_INTERRUPT_LINE: 777 if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { 778 u32 ctrl = mvebu_readl(port, PCIE_CTRL_OFF); 779 if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16)) 780 ctrl |= PCIE_CTRL_MASTER_HOT_RESET; 781 else 782 ctrl &= ~PCIE_CTRL_MASTER_HOT_RESET; 783 mvebu_writel(port, ctrl, PCIE_CTRL_OFF); 784 } 785 break; 786 787 default: 788 break; 789 } 790 } 791 792 static void 793 mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, 794 int reg, u32 old, u32 new, u32 mask) 795 { 796 struct mvebu_pcie_port *port = bridge->data; 797 798 switch (reg) { 799 case PCI_EXP_DEVCTL: 800 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL); 801 break; 802 803 case PCI_EXP_LNKCTL: 804 /* 805 * PCIe requires that the Enable Clock Power Management bit 806 * is hard-wired to zero for downstream ports but HW allows 807 * to change it. 808 */ 809 new &= ~PCI_EXP_LNKCTL_CLKREQ_EN; 810 811 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL); 812 break; 813 814 case PCI_EXP_SLTCTL: 815 /* 816 * Allow to change PCIE_SSPL_ENABLE bit only when slot power 817 * limit was specified in DT and configured into HW. 818 */ 819 if ((mask & PCI_EXP_SLTCTL_ASPL_DISABLE) && 820 port->slot_power_limit_value) { 821 u32 sspl = mvebu_readl(port, PCIE_SSPL_OFF); 822 if (new & PCI_EXP_SLTCTL_ASPL_DISABLE) 823 sspl &= ~PCIE_SSPL_ENABLE; 824 else 825 sspl |= PCIE_SSPL_ENABLE; 826 mvebu_writel(port, sspl, PCIE_SSPL_OFF); 827 } 828 break; 829 830 case PCI_EXP_RTSTA: 831 /* 832 * PME Status bit in Root Status Register (PCIE_RC_RTSTA) 833 * is read-only and can be cleared only by writing 0b to the 834 * Interrupt Cause RW0C register (PCIE_INT_CAUSE_OFF). So 835 * clear PME via Interrupt Cause. 836 */ 837 if (new & PCI_EXP_RTSTA_PME) 838 mvebu_writel(port, ~PCIE_INT_PM_PME, PCIE_INT_CAUSE_OFF); 839 break; 840 841 case PCI_EXP_DEVCTL2: 842 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2); 843 break; 844 845 case PCI_EXP_LNKCTL2: 846 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2); 847 break; 848 849 default: 850 break; 851 } 852 } 853 854 static void 855 mvebu_pci_bridge_emul_ext_conf_write(struct pci_bridge_emul *bridge, 856 int reg, u32 old, u32 new, u32 mask) 857 { 858 struct mvebu_pcie_port *port = bridge->data; 859 860 switch (reg) { 861 /* These are W1C registers, so clear other bits */ 862 case PCI_ERR_UNCOR_STATUS: 863 case PCI_ERR_COR_STATUS: 864 case PCI_ERR_ROOT_STATUS: 865 new &= mask; 866 fallthrough; 867 868 case PCI_ERR_UNCOR_MASK: 869 case PCI_ERR_UNCOR_SEVER: 870 case PCI_ERR_COR_MASK: 871 case PCI_ERR_CAP: 872 case PCI_ERR_HEADER_LOG+0: 873 case PCI_ERR_HEADER_LOG+4: 874 case PCI_ERR_HEADER_LOG+8: 875 case PCI_ERR_HEADER_LOG+12: 876 case PCI_ERR_ROOT_COMMAND: 877 case PCI_ERR_ROOT_ERR_SRC: 878 mvebu_writel(port, new, PCIE_CAP_PCIERR_OFF + reg); 879 break; 880 881 default: 882 break; 883 } 884 } 885 886 static const struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = { 887 .read_base = mvebu_pci_bridge_emul_base_conf_read, 888 .write_base = mvebu_pci_bridge_emul_base_conf_write, 889 .read_pcie = mvebu_pci_bridge_emul_pcie_conf_read, 890 .write_pcie = mvebu_pci_bridge_emul_pcie_conf_write, 891 .read_ext = mvebu_pci_bridge_emul_ext_conf_read, 892 .write_ext = mvebu_pci_bridge_emul_ext_conf_write, 893 }; 894 895 /* 896 * Initialize the configuration space of the PCI-to-PCI bridge 897 * associated with the given PCIe interface. 898 */ 899 static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) 900 { 901 unsigned int bridge_flags = PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD; 902 struct pci_bridge_emul *bridge = &port->bridge; 903 u32 dev_id = mvebu_readl(port, PCIE_DEV_ID_OFF); 904 u32 dev_rev = mvebu_readl(port, PCIE_DEV_REV_OFF); 905 u32 ssdev_id = mvebu_readl(port, PCIE_SSDEV_ID_OFF); 906 u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP); 907 u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS); 908 909 bridge->conf.vendor = cpu_to_le16(dev_id & 0xffff); 910 bridge->conf.device = cpu_to_le16(dev_id >> 16); 911 bridge->conf.class_revision = cpu_to_le32(dev_rev & 0xff); 912 913 if (mvebu_has_ioport(port)) { 914 /* We support 32 bits I/O addressing */ 915 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; 916 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; 917 } else { 918 bridge_flags |= PCI_BRIDGE_EMUL_NO_IO_FORWARD; 919 } 920 921 /* 922 * Older mvebu hardware provides PCIe Capability structure only in 923 * version 1. New hardware provides it in version 2. 924 * Enable slot support which is emulated. 925 */ 926 bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver | PCI_EXP_FLAGS_SLOT); 927 928 /* 929 * Set Presence Detect State bit permanently as there is no support for 930 * unplugging PCIe card from the slot. Assume that PCIe card is always 931 * connected in slot. 932 * 933 * Set physical slot number to port+1 as mvebu ports are indexed from 934 * zero and zero value is reserved for ports within the same silicon 935 * as Root Port which is not mvebu case. 936 * 937 * Also set correct slot power limit. 938 */ 939 bridge->pcie_conf.slotcap = cpu_to_le32( 940 FIELD_PREP(PCI_EXP_SLTCAP_SPLV, port->slot_power_limit_value) | 941 FIELD_PREP(PCI_EXP_SLTCAP_SPLS, port->slot_power_limit_scale) | 942 FIELD_PREP(PCI_EXP_SLTCAP_PSN, port->port+1)); 943 bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS); 944 945 bridge->subsystem_vendor_id = ssdev_id & 0xffff; 946 bridge->subsystem_id = ssdev_id >> 16; 947 bridge->has_pcie = true; 948 bridge->pcie_start = PCIE_CAP_PCIEXP; 949 bridge->data = port; 950 bridge->ops = &mvebu_pci_bridge_emul_ops; 951 952 return pci_bridge_emul_init(bridge, bridge_flags); 953 } 954 955 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys) 956 { 957 return sys->private_data; 958 } 959 960 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie, 961 struct pci_bus *bus, 962 int devfn) 963 { 964 int i; 965 966 for (i = 0; i < pcie->nports; i++) { 967 struct mvebu_pcie_port *port = &pcie->ports[i]; 968 969 if (!port->base) 970 continue; 971 972 if (bus->number == 0 && port->devfn == devfn) 973 return port; 974 if (bus->number != 0 && 975 bus->number >= port->bridge.conf.secondary_bus && 976 bus->number <= port->bridge.conf.subordinate_bus) 977 return port; 978 } 979 980 return NULL; 981 } 982 983 /* PCI configuration space write function */ 984 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 985 int where, int size, u32 val) 986 { 987 struct mvebu_pcie *pcie = bus->sysdata; 988 struct mvebu_pcie_port *port; 989 990 port = mvebu_pcie_find_port(pcie, bus, devfn); 991 if (!port) 992 return PCIBIOS_DEVICE_NOT_FOUND; 993 994 return pci_bridge_emul_conf_write(&port->bridge, where, size, val); 995 } 996 997 /* PCI configuration space read function */ 998 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, 999 int size, u32 *val) 1000 { 1001 struct mvebu_pcie *pcie = bus->sysdata; 1002 struct mvebu_pcie_port *port; 1003 1004 port = mvebu_pcie_find_port(pcie, bus, devfn); 1005 if (!port) 1006 return PCIBIOS_DEVICE_NOT_FOUND; 1007 1008 return pci_bridge_emul_conf_read(&port->bridge, where, size, val); 1009 } 1010 1011 static struct pci_ops mvebu_pcie_ops = { 1012 .read = mvebu_pcie_rd_conf, 1013 .write = mvebu_pcie_wr_conf, 1014 }; 1015 1016 static void mvebu_pcie_intx_irq_mask(struct irq_data *d) 1017 { 1018 struct mvebu_pcie_port *port = d->domain->host_data; 1019 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1020 unsigned long flags; 1021 u32 unmask; 1022 1023 raw_spin_lock_irqsave(&port->irq_lock, flags); 1024 unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); 1025 unmask &= ~PCIE_INT_INTX(hwirq); 1026 mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); 1027 raw_spin_unlock_irqrestore(&port->irq_lock, flags); 1028 } 1029 1030 static void mvebu_pcie_intx_irq_unmask(struct irq_data *d) 1031 { 1032 struct mvebu_pcie_port *port = d->domain->host_data; 1033 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1034 unsigned long flags; 1035 u32 unmask; 1036 1037 raw_spin_lock_irqsave(&port->irq_lock, flags); 1038 unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); 1039 unmask |= PCIE_INT_INTX(hwirq); 1040 mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF); 1041 raw_spin_unlock_irqrestore(&port->irq_lock, flags); 1042 } 1043 1044 static struct irq_chip intx_irq_chip = { 1045 .name = "mvebu-INTx", 1046 .irq_mask = mvebu_pcie_intx_irq_mask, 1047 .irq_unmask = mvebu_pcie_intx_irq_unmask, 1048 }; 1049 1050 static int mvebu_pcie_intx_irq_map(struct irq_domain *h, 1051 unsigned int virq, irq_hw_number_t hwirq) 1052 { 1053 struct mvebu_pcie_port *port = h->host_data; 1054 1055 irq_set_status_flags(virq, IRQ_LEVEL); 1056 irq_set_chip_and_handler(virq, &intx_irq_chip, handle_level_irq); 1057 irq_set_chip_data(virq, port); 1058 1059 return 0; 1060 } 1061 1062 static const struct irq_domain_ops mvebu_pcie_intx_irq_domain_ops = { 1063 .map = mvebu_pcie_intx_irq_map, 1064 .xlate = irq_domain_xlate_onecell, 1065 }; 1066 1067 static int mvebu_pcie_init_irq_domain(struct mvebu_pcie_port *port) 1068 { 1069 struct device *dev = &port->pcie->pdev->dev; 1070 struct device_node *pcie_intc_node; 1071 1072 raw_spin_lock_init(&port->irq_lock); 1073 1074 pcie_intc_node = of_get_next_child(port->dn, NULL); 1075 if (!pcie_intc_node) { 1076 dev_err(dev, "No PCIe Intc node found for %s\n", port->name); 1077 return -ENODEV; 1078 } 1079 1080 port->intx_irq_domain = irq_domain_create_linear(of_fwnode_handle(pcie_intc_node), 1081 PCI_NUM_INTX, 1082 &mvebu_pcie_intx_irq_domain_ops, port); 1083 of_node_put(pcie_intc_node); 1084 if (!port->intx_irq_domain) { 1085 dev_err(dev, "Failed to get INTx IRQ domain for %s\n", port->name); 1086 return -ENOMEM; 1087 } 1088 1089 return 0; 1090 } 1091 1092 static void mvebu_pcie_irq_handler(struct irq_desc *desc) 1093 { 1094 struct mvebu_pcie_port *port = irq_desc_get_handler_data(desc); 1095 struct irq_chip *chip = irq_desc_get_chip(desc); 1096 struct device *dev = &port->pcie->pdev->dev; 1097 u32 cause, unmask, status; 1098 int i; 1099 1100 chained_irq_enter(chip, desc); 1101 1102 cause = mvebu_readl(port, PCIE_INT_CAUSE_OFF); 1103 unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF); 1104 status = cause & unmask; 1105 1106 /* Process legacy INTx interrupts */ 1107 for (i = 0; i < PCI_NUM_INTX; i++) { 1108 if (!(status & PCIE_INT_INTX(i))) 1109 continue; 1110 1111 if (generic_handle_domain_irq(port->intx_irq_domain, i) == -EINVAL) 1112 dev_err_ratelimited(dev, "unexpected INT%c IRQ\n", (char)i+'A'); 1113 } 1114 1115 chained_irq_exit(chip, desc); 1116 } 1117 1118 static int mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 1119 { 1120 /* Interrupt support on mvebu emulated bridges is not implemented yet */ 1121 if (dev->bus->number == 0) 1122 return 0; /* Proper return code 0 == NO_IRQ */ 1123 1124 return of_irq_parse_and_map_pci(dev, slot, pin); 1125 } 1126 1127 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev, 1128 const struct resource *res, 1129 resource_size_t start, 1130 resource_size_t size, 1131 resource_size_t align) 1132 { 1133 if (dev->bus->number != 0) 1134 return start; 1135 1136 /* 1137 * On the PCI-to-PCI bridge side, the I/O windows must have at 1138 * least a 64 KB size and the memory windows must have at 1139 * least a 1 MB size. Moreover, MBus windows need to have a 1140 * base address aligned on their size, and their size must be 1141 * a power of two. This means that if the BAR doesn't have a 1142 * power of two size, several MBus windows will actually be 1143 * created. We need to ensure that the biggest MBus window 1144 * (which will be the first one) is aligned on its size, which 1145 * explains the rounddown_pow_of_two() being done here. 1146 */ 1147 if (res->flags & IORESOURCE_IO) 1148 return round_up(start, max_t(resource_size_t, SZ_64K, 1149 rounddown_pow_of_two(size))); 1150 else if (res->flags & IORESOURCE_MEM) 1151 return round_up(start, max_t(resource_size_t, SZ_1M, 1152 rounddown_pow_of_two(size))); 1153 else 1154 return start; 1155 } 1156 1157 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev, 1158 struct device_node *np, 1159 struct mvebu_pcie_port *port) 1160 { 1161 int ret = 0; 1162 1163 ret = of_address_to_resource(np, 0, &port->regs); 1164 if (ret) 1165 return (void __iomem *)ERR_PTR(ret); 1166 1167 return devm_ioremap_resource(&pdev->dev, &port->regs); 1168 } 1169 1170 static int mvebu_get_tgt_attr(struct device_node *np, int devfn, 1171 unsigned long type, 1172 unsigned int *tgt, 1173 unsigned int *attr) 1174 { 1175 struct of_range range; 1176 struct of_range_parser parser; 1177 1178 *tgt = -1; 1179 *attr = -1; 1180 1181 if (of_pci_range_parser_init(&parser, np)) 1182 return -EINVAL; 1183 1184 for_each_of_range(&parser, &range) { 1185 u32 slot = upper_32_bits(range.bus_addr); 1186 1187 if (slot == PCI_SLOT(devfn) && 1188 type == (range.flags & IORESOURCE_TYPE_BITS)) { 1189 *tgt = (range.parent_bus_addr >> 56) & 0xFF; 1190 *attr = (range.parent_bus_addr >> 48) & 0xFF; 1191 return 0; 1192 } 1193 } 1194 1195 return -ENOENT; 1196 } 1197 1198 static int mvebu_pcie_suspend(struct device *dev) 1199 { 1200 struct mvebu_pcie *pcie; 1201 int i; 1202 1203 pcie = dev_get_drvdata(dev); 1204 for (i = 0; i < pcie->nports; i++) { 1205 struct mvebu_pcie_port *port = pcie->ports + i; 1206 if (!port->base) 1207 continue; 1208 port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF); 1209 } 1210 1211 return 0; 1212 } 1213 1214 static int mvebu_pcie_resume(struct device *dev) 1215 { 1216 struct mvebu_pcie *pcie; 1217 int i; 1218 1219 pcie = dev_get_drvdata(dev); 1220 for (i = 0; i < pcie->nports; i++) { 1221 struct mvebu_pcie_port *port = pcie->ports + i; 1222 if (!port->base) 1223 continue; 1224 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF); 1225 mvebu_pcie_setup_hw(port); 1226 } 1227 1228 return 0; 1229 } 1230 1231 static void mvebu_pcie_port_clk_put(void *data) 1232 { 1233 struct mvebu_pcie_port *port = data; 1234 1235 clk_put(port->clk); 1236 } 1237 1238 static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie, 1239 struct mvebu_pcie_port *port, struct device_node *child) 1240 { 1241 struct device *dev = &pcie->pdev->dev; 1242 u32 slot_power_limit; 1243 int ret; 1244 u32 num_lanes; 1245 1246 port->pcie = pcie; 1247 1248 if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) { 1249 dev_warn(dev, "ignoring %pOF, missing pcie-port property\n", 1250 child); 1251 goto skip; 1252 } 1253 1254 if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane)) 1255 port->lane = 0; 1256 1257 if (!of_property_read_u32(child, "num-lanes", &num_lanes) && num_lanes == 4) 1258 port->is_x4 = true; 1259 1260 port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port, 1261 port->lane); 1262 if (!port->name) { 1263 ret = -ENOMEM; 1264 goto err; 1265 } 1266 1267 port->devfn = of_pci_get_devfn(child); 1268 if (port->devfn < 0) 1269 goto skip; 1270 if (PCI_FUNC(port->devfn) != 0) { 1271 dev_err(dev, "%s: invalid function number, must be zero\n", 1272 port->name); 1273 goto skip; 1274 } 1275 1276 ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM, 1277 &port->mem_target, &port->mem_attr); 1278 if (ret < 0) { 1279 dev_err(dev, "%s: cannot get tgt/attr for mem window\n", 1280 port->name); 1281 goto skip; 1282 } 1283 1284 if (resource_size(&pcie->io) != 0) { 1285 mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO, 1286 &port->io_target, &port->io_attr); 1287 } else { 1288 port->io_target = -1; 1289 port->io_attr = -1; 1290 } 1291 1292 /* 1293 * Old DT bindings do not contain "intx" interrupt 1294 * so do not fail probing driver when interrupt does not exist. 1295 */ 1296 port->intx_irq = of_irq_get_byname(child, "intx"); 1297 if (port->intx_irq == -EPROBE_DEFER) { 1298 ret = port->intx_irq; 1299 goto err; 1300 } 1301 if (port->intx_irq <= 0) { 1302 dev_warn(dev, "%s: legacy INTx interrupts cannot be masked individually, " 1303 "%pOF does not contain intx interrupt\n", 1304 port->name, child); 1305 } 1306 1307 port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset", 1308 port->name); 1309 if (!port->reset_name) { 1310 ret = -ENOMEM; 1311 goto err; 1312 } 1313 1314 port->reset_gpio = devm_fwnode_gpiod_get(dev, of_fwnode_handle(child), 1315 "reset", GPIOD_OUT_HIGH, 1316 port->name); 1317 ret = PTR_ERR_OR_ZERO(port->reset_gpio); 1318 if (ret) { 1319 if (ret != -ENOENT) 1320 goto err; 1321 /* reset gpio is optional */ 1322 port->reset_gpio = NULL; 1323 devm_kfree(dev, port->reset_name); 1324 port->reset_name = NULL; 1325 } 1326 1327 slot_power_limit = of_pci_get_slot_power_limit(child, 1328 &port->slot_power_limit_value, 1329 &port->slot_power_limit_scale); 1330 if (slot_power_limit) 1331 dev_info(dev, "%s: Slot power limit %u.%uW\n", 1332 port->name, 1333 slot_power_limit / 1000, 1334 (slot_power_limit / 100) % 10); 1335 1336 port->clk = of_clk_get_by_name(child, NULL); 1337 if (IS_ERR(port->clk)) { 1338 dev_err(dev, "%s: cannot get clock\n", port->name); 1339 goto skip; 1340 } 1341 1342 ret = devm_add_action_or_reset(dev, mvebu_pcie_port_clk_put, port); 1343 if (ret < 0) 1344 goto err; 1345 1346 return 1; 1347 1348 skip: 1349 ret = 0; 1350 1351 /* In the case of skipping, we need to free these */ 1352 devm_kfree(dev, port->reset_name); 1353 port->reset_name = NULL; 1354 devm_kfree(dev, port->name); 1355 port->name = NULL; 1356 1357 err: 1358 return ret; 1359 } 1360 1361 /* 1362 * Power up a PCIe port. PCIe requires the refclk to be stable for 100µs 1363 * prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications 1364 * of the PCI Express Card Electromechanical Specification, 1.1. 1365 */ 1366 static int mvebu_pcie_powerup(struct mvebu_pcie_port *port) 1367 { 1368 int ret; 1369 1370 ret = clk_prepare_enable(port->clk); 1371 if (ret < 0) 1372 return ret; 1373 1374 if (port->reset_gpio) { 1375 u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000; 1376 1377 of_property_read_u32(port->dn, "reset-delay-us", 1378 &reset_udelay); 1379 1380 udelay(100); 1381 1382 gpiod_set_value_cansleep(port->reset_gpio, 0); 1383 msleep(reset_udelay / 1000); 1384 } 1385 1386 return 0; 1387 } 1388 1389 /* 1390 * Power down a PCIe port. Strictly, PCIe requires us to place the card 1391 * in D3hot state before asserting PERST#. 1392 */ 1393 static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port) 1394 { 1395 gpiod_set_value_cansleep(port->reset_gpio, 1); 1396 1397 clk_disable_unprepare(port->clk); 1398 } 1399 1400 /* 1401 * devm_of_pci_get_host_bridge_resources() only sets up translatable resources, 1402 * so we need extra resource setup parsing our special DT properties encoding 1403 * the MEM and IO apertures. 1404 */ 1405 static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie) 1406 { 1407 struct device *dev = &pcie->pdev->dev; 1408 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 1409 int ret; 1410 1411 /* Get the PCIe memory aperture */ 1412 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem); 1413 if (resource_size(&pcie->mem) == 0) { 1414 dev_err(dev, "invalid memory aperture size\n"); 1415 return -EINVAL; 1416 } 1417 1418 pcie->mem.name = "PCI MEM"; 1419 pci_add_resource(&bridge->windows, &pcie->mem); 1420 ret = devm_request_resource(dev, &iomem_resource, &pcie->mem); 1421 if (ret) 1422 return ret; 1423 1424 /* Get the PCIe IO aperture */ 1425 mvebu_mbus_get_pcie_io_aperture(&pcie->io); 1426 1427 if (resource_size(&pcie->io) != 0) { 1428 pcie->realio.flags = pcie->io.flags; 1429 pcie->realio.start = PCIBIOS_MIN_IO; 1430 pcie->realio.end = min_t(resource_size_t, 1431 IO_SPACE_LIMIT - SZ_64K, 1432 resource_size(&pcie->io) - 1); 1433 pcie->realio.name = "PCI I/O"; 1434 1435 ret = devm_pci_remap_iospace(dev, &pcie->realio, pcie->io.start); 1436 if (ret) 1437 return ret; 1438 1439 pci_add_resource(&bridge->windows, &pcie->realio); 1440 ret = devm_request_resource(dev, &ioport_resource, &pcie->realio); 1441 if (ret) 1442 return ret; 1443 } 1444 1445 return 0; 1446 } 1447 1448 static int mvebu_pcie_probe(struct platform_device *pdev) 1449 { 1450 struct device *dev = &pdev->dev; 1451 struct mvebu_pcie *pcie; 1452 struct pci_host_bridge *bridge; 1453 struct device_node *np = dev->of_node; 1454 struct device_node *child; 1455 int num, i, ret; 1456 1457 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct mvebu_pcie)); 1458 if (!bridge) 1459 return -ENOMEM; 1460 1461 pcie = pci_host_bridge_priv(bridge); 1462 pcie->pdev = pdev; 1463 platform_set_drvdata(pdev, pcie); 1464 1465 ret = mvebu_pcie_parse_request_resources(pcie); 1466 if (ret) 1467 return ret; 1468 1469 num = of_get_available_child_count(np); 1470 1471 pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL); 1472 if (!pcie->ports) 1473 return -ENOMEM; 1474 1475 i = 0; 1476 for_each_available_child_of_node(np, child) { 1477 struct mvebu_pcie_port *port = &pcie->ports[i]; 1478 1479 ret = mvebu_pcie_parse_port(pcie, port, child); 1480 if (ret < 0) { 1481 of_node_put(child); 1482 return ret; 1483 } else if (ret == 0) { 1484 continue; 1485 } 1486 1487 port->dn = child; 1488 i++; 1489 } 1490 pcie->nports = i; 1491 1492 for (i = 0; i < pcie->nports; i++) { 1493 struct mvebu_pcie_port *port = &pcie->ports[i]; 1494 int irq = port->intx_irq; 1495 1496 child = port->dn; 1497 if (!child) 1498 continue; 1499 1500 ret = mvebu_pcie_powerup(port); 1501 if (ret < 0) 1502 continue; 1503 1504 port->base = mvebu_pcie_map_registers(pdev, child, port); 1505 if (IS_ERR(port->base)) { 1506 dev_err(dev, "%s: cannot map registers\n", port->name); 1507 port->base = NULL; 1508 mvebu_pcie_powerdown(port); 1509 continue; 1510 } 1511 1512 ret = mvebu_pci_bridge_emul_init(port); 1513 if (ret < 0) { 1514 dev_err(dev, "%s: cannot init emulated bridge\n", 1515 port->name); 1516 devm_iounmap(dev, port->base); 1517 port->base = NULL; 1518 mvebu_pcie_powerdown(port); 1519 continue; 1520 } 1521 1522 if (irq > 0) { 1523 ret = mvebu_pcie_init_irq_domain(port); 1524 if (ret) { 1525 dev_err(dev, "%s: cannot init irq domain\n", 1526 port->name); 1527 pci_bridge_emul_cleanup(&port->bridge); 1528 devm_iounmap(dev, port->base); 1529 port->base = NULL; 1530 mvebu_pcie_powerdown(port); 1531 continue; 1532 } 1533 irq_set_chained_handler_and_data(irq, 1534 mvebu_pcie_irq_handler, 1535 port); 1536 } 1537 1538 /* 1539 * PCIe topology exported by mvebu hw is quite complicated. In 1540 * reality has something like N fully independent host bridges 1541 * where each host bridge has one PCIe Root Port (which acts as 1542 * PCI Bridge device). Each host bridge has its own independent 1543 * internal registers, independent access to PCI config space, 1544 * independent interrupt lines, independent window and memory 1545 * access configuration. But additionally there is some kind of 1546 * peer-to-peer support between PCIe devices behind different 1547 * host bridges limited just to forwarding of memory and I/O 1548 * transactions (forwarding of error messages and config cycles 1549 * is not supported). So we could say there are N independent 1550 * PCIe Root Complexes. 1551 * 1552 * For this kind of setup DT should have been structured into 1553 * N independent PCIe controllers / host bridges. But instead 1554 * structure in past was defined to put PCIe Root Ports of all 1555 * host bridges into one bus zero, like in classic multi-port 1556 * Root Complex setup with just one host bridge. 1557 * 1558 * This means that pci-mvebu.c driver provides "virtual" bus 0 1559 * on which registers all PCIe Root Ports (PCI Bridge devices) 1560 * specified in DT by their BDF addresses and virtually routes 1561 * PCI config access of each PCI bridge device to specific PCIe 1562 * host bridge. 1563 * 1564 * Normally PCI Bridge should choose between Type 0 and Type 1 1565 * config requests based on primary and secondary bus numbers 1566 * configured on the bridge itself. But because mvebu PCI Bridge 1567 * does not have registers for primary and secondary bus numbers 1568 * in its config space, it determinates type of config requests 1569 * via its own custom way. 1570 * 1571 * There are two options how mvebu determinate type of config 1572 * request. 1573 * 1574 * 1. If Secondary Bus Number Enable bit is not set or is not 1575 * available (applies for pre-XP PCIe controllers) then Type 0 1576 * is used if target bus number equals Local Bus Number (bits 1577 * [15:8] in register 0x1a04) and target device number differs 1578 * from Local Device Number (bits [20:16] in register 0x1a04). 1579 * Type 1 is used if target bus number differs from Local Bus 1580 * Number. And when target bus number equals Local Bus Number 1581 * and target device equals Local Device Number then request is 1582 * routed to Local PCI Bridge (PCIe Root Port). 1583 * 1584 * 2. If Secondary Bus Number Enable bit is set (bit 7 in 1585 * register 0x1a2c) then mvebu hw determinate type of config 1586 * request like compliant PCI Bridge based on primary bus number 1587 * which is configured via Local Bus Number (bits [15:8] in 1588 * register 0x1a04) and secondary bus number which is configured 1589 * via Secondary Bus Number (bits [7:0] in register 0x1a2c). 1590 * Local PCI Bridge (PCIe Root Port) is available on primary bus 1591 * as device with Local Device Number (bits [20:16] in register 1592 * 0x1a04). 1593 * 1594 * Secondary Bus Number Enable bit is disabled by default and 1595 * option 2. is not available on pre-XP PCIe controllers. Hence 1596 * this driver always use option 1. 1597 * 1598 * Basically it means that primary and secondary buses shares 1599 * one virtual number configured via Local Bus Number bits and 1600 * Local Device Number bits determinates if accessing primary 1601 * or secondary bus. Set Local Device Number to 1 and redirect 1602 * all writes of PCI Bridge Secondary Bus Number register to 1603 * Local Bus Number (bits [15:8] in register 0x1a04). 1604 * 1605 * So when accessing devices on buses behind secondary bus 1606 * number it would work correctly. And also when accessing 1607 * device 0 at secondary bus number via config space would be 1608 * correctly routed to secondary bus. Due to issues described 1609 * in mvebu_pcie_setup_hw(), PCI Bridges at primary bus (zero) 1610 * are not accessed directly via PCI config space but rarher 1611 * indirectly via kernel emulated PCI bridge driver. 1612 */ 1613 mvebu_pcie_setup_hw(port); 1614 mvebu_pcie_set_local_dev_nr(port, 1); 1615 mvebu_pcie_set_local_bus_nr(port, 0); 1616 } 1617 1618 bridge->sysdata = pcie; 1619 bridge->ops = &mvebu_pcie_ops; 1620 bridge->child_ops = &mvebu_pcie_child_ops; 1621 bridge->align_resource = mvebu_pcie_align_resource; 1622 bridge->map_irq = mvebu_pcie_map_irq; 1623 1624 return pci_host_probe(bridge); 1625 } 1626 1627 static void mvebu_pcie_remove(struct platform_device *pdev) 1628 { 1629 struct mvebu_pcie *pcie = platform_get_drvdata(pdev); 1630 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 1631 u32 cmd, sspl; 1632 int i; 1633 1634 /* Remove PCI bus with all devices. */ 1635 pci_lock_rescan_remove(); 1636 pci_stop_root_bus(bridge->bus); 1637 pci_remove_root_bus(bridge->bus); 1638 pci_unlock_rescan_remove(); 1639 1640 for (i = 0; i < pcie->nports; i++) { 1641 struct mvebu_pcie_port *port = &pcie->ports[i]; 1642 int irq = port->intx_irq; 1643 1644 if (!port->base) 1645 continue; 1646 1647 /* Disable Root Bridge I/O space, memory space and bus mastering. */ 1648 cmd = mvebu_readl(port, PCIE_CMD_OFF); 1649 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 1650 mvebu_writel(port, cmd, PCIE_CMD_OFF); 1651 1652 /* Mask all interrupt sources. */ 1653 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF); 1654 1655 /* Clear all interrupt causes. */ 1656 mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF); 1657 1658 if (irq > 0) 1659 irq_set_chained_handler_and_data(irq, NULL, NULL); 1660 1661 /* Remove IRQ domains. */ 1662 if (port->intx_irq_domain) 1663 irq_domain_remove(port->intx_irq_domain); 1664 1665 /* Free config space for emulated root bridge. */ 1666 pci_bridge_emul_cleanup(&port->bridge); 1667 1668 /* Disable sending Set_Slot_Power_Limit PCIe Message. */ 1669 sspl = mvebu_readl(port, PCIE_SSPL_OFF); 1670 sspl &= ~(PCIE_SSPL_VALUE_MASK | PCIE_SSPL_SCALE_MASK | PCIE_SSPL_ENABLE); 1671 mvebu_writel(port, sspl, PCIE_SSPL_OFF); 1672 1673 /* Disable and clear BARs and windows. */ 1674 mvebu_pcie_disable_wins(port); 1675 1676 /* Delete PCIe IO and MEM windows. */ 1677 if (port->iowin.size) 1678 mvebu_pcie_del_windows(port, port->iowin.base, port->iowin.size); 1679 if (port->memwin.size) 1680 mvebu_pcie_del_windows(port, port->memwin.base, port->memwin.size); 1681 1682 /* Power down card and disable clocks. Must be the last step. */ 1683 mvebu_pcie_powerdown(port); 1684 } 1685 } 1686 1687 static const struct of_device_id mvebu_pcie_of_match_table[] = { 1688 { .compatible = "marvell,armada-xp-pcie", }, 1689 { .compatible = "marvell,armada-370-pcie", }, 1690 { .compatible = "marvell,dove-pcie", }, 1691 { .compatible = "marvell,kirkwood-pcie", }, 1692 {}, 1693 }; 1694 MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table); 1695 1696 static const struct dev_pm_ops mvebu_pcie_pm_ops = { 1697 NOIRQ_SYSTEM_SLEEP_PM_OPS(mvebu_pcie_suspend, mvebu_pcie_resume) 1698 }; 1699 1700 static struct platform_driver mvebu_pcie_driver = { 1701 .driver = { 1702 .name = "mvebu-pcie", 1703 .of_match_table = mvebu_pcie_of_match_table, 1704 .pm = &mvebu_pcie_pm_ops, 1705 }, 1706 .probe = mvebu_pcie_probe, 1707 .remove = mvebu_pcie_remove, 1708 }; 1709 module_platform_driver(mvebu_pcie_driver); 1710 1711 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@bootlin.com>"); 1712 MODULE_AUTHOR("Pali Rohár <pali@kernel.org>"); 1713 MODULE_DESCRIPTION("Marvell EBU PCIe controller"); 1714 MODULE_LICENSE("GPL v2"); 1715