1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Xilinx 'Clocking Wizard' driver
4 *
5 * Copyright (C) 2013 - 2021 Xilinx
6 *
7 * Sören Brinkmann <soren.brinkmann@xilinx.com>
8 *
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/slab.h>
16 #include <linux/io.h>
17 #include <linux/of.h>
18 #include <linux/math64.h>
19 #include <linux/module.h>
20 #include <linux/overflow.h>
21 #include <linux/err.h>
22 #include <linux/iopoll.h>
23
24 #define WZRD_NUM_OUTPUTS 7
25 #define WZRD_ACLK_MAX_FREQ 250000000UL
26
27 #define WZRD_CLK_CFG_REG(v, n) (0x200 + 0x130 * (v) + 4 * (n))
28
29 #define WZRD_CLKOUT0_FRAC_EN BIT(18)
30 #define WZRD_CLKFBOUT_1 0
31 #define WZRD_CLKFBOUT_2 1
32 #define WZRD_CLKOUT0_1 2
33 #define WZRD_CLKOUT0_2 3
34 #define WZRD_DESKEW_2 20
35 #define WZRD_DIVCLK 21
36 #define WZRD_CLKFBOUT_4 51
37 #define WZRD_CLKFBOUT_3 48
38 #define WZRD_CP 18
39 #define WZRD_LOCK 27
40 #define WZRD_LOCK_REF_DLY 28
41 #define WZRD_RES 30
42 #define WZRD_DUTY_CYCLE 2
43 #define WZRD_O_DIV 4
44
45 #define WZRD_CLKFBOUT_FRAC_EN BIT(1)
46 #define WZRD_CLKFBOUT_PREDIV2 (BIT(11) | BIT(12) | BIT(9))
47 #define WZRD_MULT_PREDIV2 (BIT(10) | BIT(9) | BIT(12))
48 #define WZRD_CLKFBOUT_EDGE BIT(8)
49 #define WZRD_P5EN BIT(13)
50 #define WZRD_P5EN_SHIFT 13
51 #define WZRD_P5FEDGE BIT(15)
52 #define WZRD_DIVCLK_EDGE BIT(10)
53 #define WZRD_P5FEDGE_SHIFT 15
54 #define WZRD_CLKOUT0_PREDIV2 BIT(11)
55 #define WZRD_EDGE_SHIFT 8
56 #define WZRD_CP_MASK GENMASK(3, 0)
57 #define WZRD_RES_MASK GENMASK(4, 1)
58 #define WZRD_LOCK_FB_DLY_MASK GENMASK(14, 10)
59 #define WZRD_LOCK_REF_DLY_LOCK_REF_DLY_MASK GENMASK(14, 10)
60
61 #define WZRD_CLKFBOUT_MULT_SHIFT 8
62 #define WZRD_CLKFBOUT_MULT_MASK (0xff << WZRD_CLKFBOUT_MULT_SHIFT)
63 #define WZRD_CLKFBOUT_MULT_FRAC_MASK GENMASK(25, 16)
64 #define WZRD_CLKFBOUT_O_MASK GENMASK(7, 0)
65 #define WZRD_CLKFBOUT_L_SHIFT 0
66 #define WZRD_CLKFBOUT_H_SHIFT 8
67 #define WZRD_CLKFBOUT_L_MASK GENMASK(7, 0)
68 #define WZRD_CLKFBOUT_H_MASK GENMASK(15, 8)
69 #define WZRD_CLKFBOUT_FRAC_SHIFT 16
70 #define WZRD_CLKFBOUT_FRAC_MASK (0x3ff << WZRD_CLKFBOUT_FRAC_SHIFT)
71 #define WZRD_VERSAL_FRAC_MASK GENMASK(5, 0)
72 #define WZRD_DIVCLK_DIVIDE_SHIFT 0
73 #define WZRD_DIVCLK_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
74 #define WZRD_CLKOUT_DIVIDE_SHIFT 0
75 #define WZRD_CLKOUT_DIVIDE_WIDTH 8
76 #define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
77 #define WZRD_CLKOUT_FRAC_SHIFT 8
78 #define WZRD_CLKOUT_FRAC_MASK 0x3ff
79 #define WZRD_CLKOUT0_FRAC_MASK GENMASK(17, 8)
80
81 #define WZRD_DR_MAX_INT_DIV_VALUE 255
82 #define WZRD_DR_STATUS_REG_OFFSET 0x04
83 #define WZRD_DR_LOCK_BIT_MASK 0x00000001
84 #define WZRD_DR_INIT_REG_OFFSET 0x25C
85 #define WZRD_DR_INIT_VERSAL_OFFSET 0x14
86 #define WZRD_DR_DIV_TO_PHASE_OFFSET 4
87 #define WZRD_DR_BEGIN_DYNA_RECONF 0x03
88 #define WZRD_DR_BEGIN_DYNA_RECONF_5_2 0x07
89 #define WZRD_DR_BEGIN_DYNA_RECONF1_5_2 0x02
90
91 #define WZRD_USEC_POLL 10
92 #define WZRD_TIMEOUT_POLL 1000
93 #define WZRD_FRAC_GRADIENT 64
94 #define PREDIV2_MULT 2
95
96 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */
97 #define DIV_O 0x01
98 #define DIV_ALL 0x03
99
100 #define WZRD_M_MIN 2ULL
101 #define WZRD_M_MAX 128ULL
102 #define WZRD_D_MIN 1ULL
103 #define WZRD_D_MAX 106ULL
104 #define WZRD_VCO_MIN 800000000ULL
105 #define WZRD_VCO_MAX 1600000000ULL
106 #define WZRD_O_MIN 2ULL
107 #define WZRD_O_MAX 128ULL
108 #define VER_WZRD_M_MIN 4
109 #define VER_WZRD_M_MAX 432
110 #define VER_WZRD_D_MIN 1
111 #define VER_WZRD_D_MAX 123
112 #define VER_WZRD_VCO_MIN 2160000000ULL
113 #define VER_WZRD_VCO_MAX 4320000000ULL
114 #define VER_WZRD_O_MIN 2
115 #define VER_WZRD_O_MAX 511
116 #define WZRD_FRAC_POINTS 1000
117
118 /* Get the mask from width */
119 #define div_mask(width) ((1 << (width)) - 1)
120
121 /* Extract divider instance from clock hardware instance */
122 #define to_clk_wzrd_divider(_hw) container_of(_hw, struct clk_wzrd_divider, hw)
123
124 enum clk_wzrd_int_clks {
125 wzrd_clk_mul,
126 wzrd_clk_mul_div,
127 wzrd_clk_mul_frac,
128 wzrd_clk_int_max
129 };
130
131 /**
132 * struct clk_wzrd - Clock wizard private data structure
133 *
134 * @nb: Notifier block
135 * @base: Memory base
136 * @clk_in1: Handle to input clock 'clk_in1'
137 * @axi_clk: Handle to input clock 's_axi_aclk'
138 * @clks_internal: Internal clocks
139 * @speed_grade: Speed grade of the device
140 * @suspended: Flag indicating power state of the device
141 * @clk_data: Output clock data
142 */
143 struct clk_wzrd {
144 struct notifier_block nb;
145 void __iomem *base;
146 struct clk *clk_in1;
147 struct clk *axi_clk;
148 struct clk_hw *clks_internal[wzrd_clk_int_max];
149 unsigned int speed_grade;
150 bool suspended;
151 struct clk_hw_onecell_data clk_data;
152 };
153
154 /**
155 * struct clk_wzrd_divider - clock divider specific to clk_wzrd
156 *
157 * @hw: handle between common and hardware-specific interfaces
158 * @base: base address of register containing the divider
159 * @offset: offset address of register containing the divider
160 * @shift: shift to the divider bit field
161 * @width: width of the divider bit field
162 * @flags: clk_wzrd divider flags
163 * @table: array of value/divider pairs, last entry should have div = 0
164 * @m: value of the multiplier
165 * @m_frac: fractional value of the multiplier
166 * @d: value of the common divider
167 * @o: value of the leaf divider
168 * @o_frac: value of the fractional leaf divider
169 * @lock: register lock
170 */
171 struct clk_wzrd_divider {
172 struct clk_hw hw;
173 void __iomem *base;
174 u16 offset;
175 u8 shift;
176 u8 width;
177 u8 flags;
178 const struct clk_div_table *table;
179 u32 m;
180 u32 m_frac;
181 u32 d;
182 u32 o;
183 u32 o_frac;
184 spinlock_t *lock; /* divider lock */
185 };
186
187 struct versal_clk_data {
188 bool is_versal;
189 };
190
191 #define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb)
192
193 /* maximum frequencies for input/output clocks per speed grade */
194 static const unsigned long clk_wzrd_max_freq[] = {
195 800000000UL,
196 933000000UL,
197 1066000000UL
198 };
199
200 /* spin lock variable for clk_wzrd */
201 static DEFINE_SPINLOCK(clkwzrd_lock);
202
clk_wzrd_recalc_rate_ver(struct clk_hw * hw,unsigned long parent_rate)203 static unsigned long clk_wzrd_recalc_rate_ver(struct clk_hw *hw,
204 unsigned long parent_rate)
205 {
206 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
207 void __iomem *div_addr = divider->base + divider->offset;
208 u32 div, p5en, edge, prediv2, all;
209 unsigned int vall, valh;
210
211 edge = !!(readl(div_addr) & WZRD_CLKFBOUT_EDGE);
212 p5en = !!(readl(div_addr) & WZRD_P5EN);
213 prediv2 = !!(readl(div_addr) & WZRD_CLKOUT0_PREDIV2);
214 vall = readl(div_addr + 4) & WZRD_CLKFBOUT_L_MASK;
215 valh = readl(div_addr + 4) >> WZRD_CLKFBOUT_H_SHIFT;
216 all = valh + vall + edge;
217 if (!all)
218 all = 1;
219
220 if (prediv2)
221 div = 2 * all + prediv2 * p5en;
222 else
223 div = all;
224
225 return DIV_ROUND_UP_ULL((u64)parent_rate, div);
226 }
227
clk_wzrd_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)228 static unsigned long clk_wzrd_recalc_rate(struct clk_hw *hw,
229 unsigned long parent_rate)
230 {
231 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
232 void __iomem *div_addr = divider->base + divider->offset;
233 unsigned int val;
234
235 val = readl(div_addr) >> divider->shift;
236 val &= div_mask(divider->width);
237
238 return divider_recalc_rate(hw, parent_rate, val, divider->table,
239 divider->flags, divider->width);
240 }
241
clk_wzrd_ver_dynamic_reconfig(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)242 static int clk_wzrd_ver_dynamic_reconfig(struct clk_hw *hw, unsigned long rate,
243 unsigned long parent_rate)
244 {
245 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
246 void __iomem *div_addr = divider->base + divider->offset;
247 u32 value, regh, edged, p5en, p5fedge, regval, regval1;
248 unsigned long flags;
249 int err;
250
251 spin_lock_irqsave(divider->lock, flags);
252
253 value = DIV_ROUND_CLOSEST(parent_rate, rate);
254
255 regh = (value / 4);
256 regval1 = readl(div_addr);
257 regval1 |= WZRD_CLKFBOUT_PREDIV2;
258 regval1 = regval1 & ~(WZRD_CLKFBOUT_EDGE | WZRD_P5EN | WZRD_P5FEDGE);
259 if (value % 4 > 1) {
260 edged = 1;
261 regval1 |= (edged << WZRD_EDGE_SHIFT);
262 }
263 p5fedge = value % 2;
264 p5en = value % 2;
265 regval1 = regval1 | p5en << WZRD_P5EN_SHIFT | p5fedge << WZRD_P5FEDGE_SHIFT;
266 writel(regval1, div_addr);
267
268 regval = regh | regh << WZRD_CLKFBOUT_H_SHIFT;
269 writel(regval, div_addr + 4);
270 /* Check status register */
271 err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
272 value, value & WZRD_DR_LOCK_BIT_MASK,
273 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
274 if (err)
275 goto err_reconfig;
276
277 /* Initiate reconfiguration */
278 writel(WZRD_DR_BEGIN_DYNA_RECONF,
279 divider->base + WZRD_DR_INIT_VERSAL_OFFSET);
280
281 /* Check status register */
282 err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
283 value, value & WZRD_DR_LOCK_BIT_MASK,
284 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
285 err_reconfig:
286 spin_unlock_irqrestore(divider->lock, flags);
287 return err;
288 }
289
clk_wzrd_dynamic_reconfig(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)290 static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate,
291 unsigned long parent_rate)
292 {
293 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
294 void __iomem *div_addr = divider->base + divider->offset;
295 unsigned long flags;
296 u32 value;
297 int err;
298
299 spin_lock_irqsave(divider->lock, flags);
300
301 value = DIV_ROUND_CLOSEST(parent_rate, rate);
302
303 /* Cap the value to max */
304 min_t(u32, value, WZRD_DR_MAX_INT_DIV_VALUE);
305
306 /* Set divisor and clear phase offset */
307 writel(value, div_addr);
308 writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
309
310 /* Check status register */
311 err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
312 value, value & WZRD_DR_LOCK_BIT_MASK,
313 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
314 if (err)
315 goto err_reconfig;
316
317 /* Initiate reconfiguration */
318 writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2,
319 divider->base + WZRD_DR_INIT_REG_OFFSET);
320 writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2,
321 divider->base + WZRD_DR_INIT_REG_OFFSET);
322
323 /* Check status register */
324 err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
325 value, value & WZRD_DR_LOCK_BIT_MASK,
326 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
327 err_reconfig:
328 spin_unlock_irqrestore(divider->lock, flags);
329 return err;
330 }
331
clk_wzrd_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)332 static int clk_wzrd_determine_rate(struct clk_hw *hw,
333 struct clk_rate_request *req)
334 {
335 u8 div;
336
337 /*
338 * since we don't change parent rate we just round rate to closest
339 * achievable
340 */
341 div = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate);
342
343 req->rate = req->best_parent_rate / div;
344
345 return 0;
346 }
347
clk_wzrd_get_divisors_ver(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)348 static int clk_wzrd_get_divisors_ver(struct clk_hw *hw, unsigned long rate,
349 unsigned long parent_rate)
350 {
351 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
352 u64 vco_freq, freq, diff, vcomin, vcomax, best_diff = -1ULL;
353 u32 m, d, o;
354 u32 mmin, mmax, dmin, dmax, omin, omax;
355
356 mmin = VER_WZRD_M_MIN;
357 mmax = VER_WZRD_M_MAX;
358 dmin = VER_WZRD_D_MIN;
359 dmax = VER_WZRD_D_MAX;
360 omin = VER_WZRD_O_MIN;
361 omax = VER_WZRD_O_MAX;
362 vcomin = VER_WZRD_VCO_MIN;
363 vcomax = VER_WZRD_VCO_MAX;
364
365 for (m = mmin; m <= mmax; m++) {
366 for (d = dmin; d <= dmax; d++) {
367 vco_freq = DIV_ROUND_CLOSEST((parent_rate * m), d);
368 if (vco_freq < vcomin || vco_freq > vcomax)
369 continue;
370
371 o = DIV_ROUND_CLOSEST_ULL(vco_freq, rate);
372 if (o < omin || o > omax)
373 continue;
374 freq = DIV_ROUND_CLOSEST_ULL(vco_freq, o);
375 diff = abs(freq - rate);
376
377 if (diff < best_diff) {
378 best_diff = diff;
379 divider->m = m;
380 divider->d = d;
381 divider->o = o;
382 if (!diff)
383 return 0;
384 }
385 }
386 }
387 return 0;
388 }
389
clk_wzrd_get_divisors(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)390 static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate,
391 unsigned long parent_rate)
392 {
393 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
394 u64 vco_freq, freq, diff, vcomin, vcomax, best_diff = -1ULL;
395 u64 m, d, o;
396 u64 mmin, mmax, dmin, dmax, omin, omax, mdmin, mdmax;
397
398 mmin = WZRD_M_MIN << 3;
399 mmax = WZRD_M_MAX << 3;
400 dmin = WZRD_D_MIN;
401 dmax = WZRD_D_MAX;
402 omin = WZRD_O_MIN << 3;
403 omax = WZRD_O_MAX << 3;
404 vcomin = WZRD_VCO_MIN << 3;
405 vcomax = WZRD_VCO_MAX << 3;
406
407 for (m = mmin; m <= mmax; m++) {
408 mdmin = max(dmin, div64_u64(parent_rate * m + vcomax / 2, vcomax));
409 mdmax = min(dmax, div64_u64(parent_rate * m + vcomin / 2, vcomin));
410 for (d = mdmin; d <= mdmax; d++) {
411 vco_freq = DIV_ROUND_CLOSEST_ULL((parent_rate * m), d);
412 o = DIV_ROUND_CLOSEST_ULL(vco_freq, rate);
413 if (o < omin || o > omax)
414 continue;
415 freq = DIV_ROUND_CLOSEST_ULL(vco_freq, o);
416 diff = abs(freq - rate);
417 if (diff < best_diff) {
418 best_diff = diff;
419 divider->m = m >> 3;
420 divider->m_frac = (m - (divider->m << 3)) * 125;
421 divider->d = d;
422 divider->o = o >> 3;
423 divider->o_frac = (o - (divider->o << 3)) * 125;
424
425 if (!diff)
426 return 0;
427 }
428 }
429 }
430 return best_diff != -1ULL ? 0 : -EBUSY;
431 }
432
clk_wzrd_reconfig(struct clk_wzrd_divider * divider,void __iomem * div_addr)433 static int clk_wzrd_reconfig(struct clk_wzrd_divider *divider, void __iomem *div_addr)
434 {
435 u32 value;
436 int err;
437
438 /* Check status register */
439 err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
440 value & WZRD_DR_LOCK_BIT_MASK,
441 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
442 if (err)
443 return -ETIMEDOUT;
444
445 /* Initiate reconfiguration */
446 writel(WZRD_DR_BEGIN_DYNA_RECONF, div_addr);
447 /* Check status register */
448 return readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
449 value & WZRD_DR_LOCK_BIT_MASK,
450 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
451 }
452
453 struct wzrd_pll_filter {
454 u32 m_min;
455 u32 m_max;
456 u32 cp;
457 u32 res;
458 };
459
460 static const struct wzrd_pll_filter wzrd_cp_res_table[] = {
461 { 4, 4, 5, 15 },
462 { 5, 5, 6, 15 },
463 { 6, 6, 7, 15 },
464 { 7, 7, 13, 15 },
465 { 8, 8, 14, 15 },
466 { 9, 9, 15, 15 },
467 { 10, 10, 14, 7 },
468 { 11, 11, 15, 7 },
469 { 12, 13, 15, 11 },
470 { 14, 14, 15, 13 },
471 { 15, 15, 15, 3 },
472 { 16, 17, 14, 5 },
473 { 18, 19, 15, 5 },
474 { 20, 21, 15, 9 },
475 { 22, 23, 14, 14 },
476 { 24, 26, 15, 14 },
477 { 27, 28, 14, 1 },
478 { 29, 33, 15, 1 },
479 { 34, 37, 14, 6 },
480 { 38, 44, 15, 6 },
481 { 45, 57, 15, 10 },
482 { 58, 63, 13, 12 },
483 { 64, 70, 14, 12 },
484 { 71, 86, 15, 12 },
485 { 87, 94, 14, 2 },
486 { 95, 145, 15, 2 },
487 { 146, 163, 12, 4 },
488 { 164, 181, 13, 4 },
489 { 182, 200, 14, 4 },
490 { 201, 273, 15, 4 },
491 { 274, 300, 13, 8 },
492 { 301, 325, 14, 8 },
493 { 326, 432, 15, 8 },
494 };
495
496 struct wzrd_lock_timing {
497 u32 m_min;
498 u32 m_max;
499 u32 ref_dly;
500 u32 fb_dly;
501 u32 lock_cnt;
502 };
503
504 static const struct wzrd_lock_timing wzrd_lock_table[] = {
505 { 4, 4, 4, 4, 1000 },
506 { 5, 5, 6, 6, 1000 },
507 { 6, 8, 7, 7, 1000 },
508 { 9, 12, 8, 8, 1000 },
509 { 13, 13, 10, 10, 1000 },
510 { 14, 16, 13, 13, 1000 },
511 { 17, 17, 16, 16, 825 },
512 { 18, 18, 16, 16, 750 },
513 { 19, 20, 16, 16, 700 },
514 { 21, 21, 16, 16, 650 },
515 { 22, 23, 16, 16, 625 },
516 { 24, 24, 16, 16, 575 },
517 { 25, 25, 16, 16, 550 },
518 { 26, 28, 16, 16, 525 },
519 { 29, 30, 16, 16, 475 },
520 { 31, 31, 16, 16, 450 },
521 { 32, 33, 16, 16, 425 },
522 { 34, 36, 16, 16, 400 },
523 { 37, 37, 16, 16, 375 },
524 { 38, 40, 16, 16, 350 },
525 { 41, 43, 16, 16, 325 },
526 { 44, 47, 16, 16, 300 },
527 { 48, 51, 16, 16, 275 },
528 { 52, 205, 16, 16, 250 },
529 { 206, 432, 16, 16, 225 },
530 };
531
clk_wzrd_update_cp_res_lock(struct clk_wzrd_divider * divider,u32 m)532 static void clk_wzrd_update_cp_res_lock(struct clk_wzrd_divider *divider, u32 m)
533 {
534 u32 lock_ref_dly = 16, lock_fb_dly = 16, lock_cnt = 250, cp = 15, res = 15;
535 void __iomem *base = divider->base;
536 u32 reg;
537 int i;
538
539 for (i = 0; i < ARRAY_SIZE(wzrd_cp_res_table); i++) {
540 if (m >= wzrd_cp_res_table[i].m_min &&
541 m <= wzrd_cp_res_table[i].m_max) {
542 cp = wzrd_cp_res_table[i].cp;
543 res = wzrd_cp_res_table[i].res;
544 break;
545 }
546 }
547
548 for (i = 0; i < ARRAY_SIZE(wzrd_lock_table); i++) {
549 if (m >= wzrd_lock_table[i].m_min &&
550 m <= wzrd_lock_table[i].m_max) {
551 lock_ref_dly = wzrd_lock_table[i].ref_dly;
552 lock_fb_dly = wzrd_lock_table[i].fb_dly;
553 lock_cnt = wzrd_lock_table[i].lock_cnt;
554 break;
555 }
556 }
557
558 reg = readl(base + WZRD_CLK_CFG_REG(1, WZRD_CP));
559 reg &= ~WZRD_CP_MASK;
560 reg |= FIELD_PREP(WZRD_CP_MASK, cp);
561 writel(reg, base + WZRD_CLK_CFG_REG(1, WZRD_CP));
562
563 reg = readl(base + WZRD_CLK_CFG_REG(1, WZRD_RES));
564 reg &= ~WZRD_RES_MASK;
565 reg |= FIELD_PREP(WZRD_RES_MASK, res);
566 writel(reg, base + WZRD_CLK_CFG_REG(1, WZRD_RES));
567
568 reg = lock_cnt | FIELD_PREP(WZRD_LOCK_FB_DLY_MASK, lock_fb_dly);
569 writel(reg, base + WZRD_CLK_CFG_REG(1, WZRD_LOCK));
570
571 reg = readl(base + WZRD_CLK_CFG_REG(1, WZRD_LOCK_REF_DLY));
572 reg &= ~WZRD_LOCK_REF_DLY_LOCK_REF_DLY_MASK;
573 reg |= FIELD_PREP(WZRD_LOCK_REF_DLY_LOCK_REF_DLY_MASK, lock_ref_dly);
574 writel(reg, base + WZRD_CLK_CFG_REG(1, WZRD_LOCK_REF_DLY));
575 }
576
clk_wzrd_dynamic_ver_all_nolock(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)577 static int clk_wzrd_dynamic_ver_all_nolock(struct clk_hw *hw, unsigned long rate,
578 unsigned long parent_rate)
579 {
580 u32 regh, edged, p5en, p5fedge, value2, m, regval, regval1, value;
581 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
582 void __iomem *div_addr;
583 int err;
584
585 err = clk_wzrd_get_divisors_ver(hw, rate, parent_rate);
586 if (err)
587 return err;
588
589 writel(0, divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4));
590
591 m = divider->m;
592 edged = m % WZRD_DUTY_CYCLE;
593 regh = m / WZRD_DUTY_CYCLE;
594 regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,
595 WZRD_CLKFBOUT_1));
596 regval1 |= WZRD_MULT_PREDIV2;
597 if (edged)
598 regval1 = regval1 | WZRD_CLKFBOUT_EDGE;
599 else
600 regval1 = regval1 & ~WZRD_CLKFBOUT_EDGE;
601
602 writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
603 WZRD_CLKFBOUT_1));
604 regval1 = regh | regh << WZRD_CLKFBOUT_H_SHIFT;
605 writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
606 WZRD_CLKFBOUT_2));
607
608 clk_wzrd_update_cp_res_lock(divider, m);
609
610 value2 = divider->d;
611 edged = value2 % WZRD_DUTY_CYCLE;
612 regh = (value2 / WZRD_DUTY_CYCLE);
613 regval1 = FIELD_PREP(WZRD_DIVCLK_EDGE, edged);
614 writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
615 WZRD_DESKEW_2));
616 regval1 = regh | regh << WZRD_CLKFBOUT_H_SHIFT;
617 writel(regval1, divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));
618
619 value = divider->o;
620 regh = value / WZRD_O_DIV;
621 regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,
622 WZRD_CLKOUT0_1));
623 regval1 |= WZRD_CLKFBOUT_PREDIV2;
624 regval1 = regval1 & ~(WZRD_CLKFBOUT_EDGE | WZRD_P5EN | WZRD_P5FEDGE);
625
626 if (value % WZRD_O_DIV > 1) {
627 edged = 1;
628 regval1 |= edged << WZRD_CLKFBOUT_H_SHIFT;
629 }
630
631 p5fedge = value % WZRD_DUTY_CYCLE;
632 p5en = value % WZRD_DUTY_CYCLE;
633
634 regval1 = regval1 | FIELD_PREP(WZRD_P5EN, p5en) | FIELD_PREP(WZRD_P5FEDGE, p5fedge);
635 writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
636 WZRD_CLKOUT0_1));
637 regval = regh | regh << WZRD_CLKFBOUT_H_SHIFT;
638 writel(regval, divider->base + WZRD_CLK_CFG_REG(1,
639 WZRD_CLKOUT0_2));
640 div_addr = divider->base + WZRD_DR_INIT_VERSAL_OFFSET;
641
642 return clk_wzrd_reconfig(divider, div_addr);
643 }
644
clk_wzrd_dynamic_all_nolock(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)645 static int clk_wzrd_dynamic_all_nolock(struct clk_hw *hw, unsigned long rate,
646 unsigned long parent_rate)
647 {
648 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
649 void __iomem *div_addr;
650 u32 reg;
651 int err;
652
653 err = clk_wzrd_get_divisors(hw, rate, parent_rate);
654 if (err)
655 return err;
656
657 reg = FIELD_PREP(WZRD_CLKOUT_DIVIDE_MASK, divider->o) |
658 FIELD_PREP(WZRD_CLKOUT0_FRAC_MASK, divider->o_frac);
659
660 writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 2));
661 reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider->m) |
662 FIELD_PREP(WZRD_CLKFBOUT_MULT_FRAC_MASK, divider->m_frac) |
663 FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider->d);
664 writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 0));
665 writel(0, divider->base + WZRD_CLK_CFG_REG(0, 3));
666 div_addr = divider->base + WZRD_DR_INIT_REG_OFFSET;
667 return clk_wzrd_reconfig(divider, div_addr);
668 }
669
clk_wzrd_dynamic_all(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)670 static int clk_wzrd_dynamic_all(struct clk_hw *hw, unsigned long rate,
671 unsigned long parent_rate)
672 {
673 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
674 unsigned long flags;
675 int ret;
676
677 spin_lock_irqsave(divider->lock, flags);
678
679 ret = clk_wzrd_dynamic_all_nolock(hw, rate, parent_rate);
680
681 spin_unlock_irqrestore(divider->lock, flags);
682
683 return ret;
684 }
685
clk_wzrd_dynamic_all_ver(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)686 static int clk_wzrd_dynamic_all_ver(struct clk_hw *hw, unsigned long rate,
687 unsigned long parent_rate)
688 {
689 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
690 unsigned long flags;
691 int ret;
692
693 spin_lock_irqsave(divider->lock, flags);
694
695 ret = clk_wzrd_dynamic_ver_all_nolock(hw, rate, parent_rate);
696
697 spin_unlock_irqrestore(divider->lock, flags);
698
699 return ret;
700 }
701
clk_wzrd_recalc_rate_all(struct clk_hw * hw,unsigned long parent_rate)702 static unsigned long clk_wzrd_recalc_rate_all(struct clk_hw *hw,
703 unsigned long parent_rate)
704 {
705 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
706 u32 m, d, o, reg, f, mf;
707 u64 mul;
708
709 reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 0));
710 d = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg);
711 m = FIELD_GET(WZRD_CLKFBOUT_MULT_MASK, reg);
712 mf = FIELD_GET(WZRD_CLKFBOUT_MULT_FRAC_MASK, reg);
713 reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 2));
714 o = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg);
715 f = FIELD_GET(WZRD_CLKOUT0_FRAC_MASK, reg);
716
717 mul = m * 1000 + mf;
718 return DIV_ROUND_CLOSEST_ULL(parent_rate * mul, d * (o * 1000 + f));
719 }
720
clk_wzrd_recalc_rate_all_ver(struct clk_hw * hw,unsigned long parent_rate)721 static unsigned long clk_wzrd_recalc_rate_all_ver(struct clk_hw *hw,
722 unsigned long parent_rate)
723 {
724 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
725 u32 edged, div2, p5en, edge, prediv2, all, regl, regh, mult;
726 u32 div, reg;
727
728 edge = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_1)) &
729 WZRD_CLKFBOUT_EDGE);
730
731 reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_2));
732 regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg);
733 regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg);
734
735 mult = regl + regh + edge;
736 if (!mult)
737 mult = 1;
738
739 regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4)) &
740 WZRD_CLKFBOUT_FRAC_EN;
741 if (regl) {
742 regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_3))
743 & WZRD_VERSAL_FRAC_MASK;
744 mult = mult * WZRD_FRAC_GRADIENT + regl;
745 parent_rate = DIV_ROUND_CLOSEST((parent_rate * mult), WZRD_FRAC_GRADIENT);
746 } else {
747 parent_rate = parent_rate * mult;
748 }
749
750 /* O Calculation */
751 reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_1));
752 edged = FIELD_GET(WZRD_CLKFBOUT_EDGE, reg);
753 p5en = FIELD_GET(WZRD_P5EN, reg);
754 prediv2 = FIELD_GET(WZRD_CLKOUT0_PREDIV2, reg);
755
756 reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_2));
757 /* Low time */
758 regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg);
759 /* High time */
760 regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg);
761 all = regh + regl + edged;
762 if (!all)
763 all = 1;
764
765 if (prediv2)
766 div2 = PREDIV2_MULT * all + p5en;
767 else
768 div2 = all;
769
770 /* D calculation */
771 edged = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DESKEW_2)) &
772 WZRD_DIVCLK_EDGE);
773 reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));
774 /* Low time */
775 regl = FIELD_GET(WZRD_CLKFBOUT_L_MASK, reg);
776 /* High time */
777 regh = FIELD_GET(WZRD_CLKFBOUT_H_MASK, reg);
778 div = regl + regh + edged;
779 if (!div)
780 div = 1;
781
782 div = div * div2;
783 return divider_recalc_rate(hw, parent_rate, div, divider->table,
784 divider->flags, divider->width);
785 }
786
clk_wzrd_determine_rate_all(struct clk_hw * hw,struct clk_rate_request * req)787 static int clk_wzrd_determine_rate_all(struct clk_hw *hw,
788 struct clk_rate_request *req)
789 {
790 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
791 u32 m, d, o;
792 int err;
793
794 err = clk_wzrd_get_divisors(hw, req->rate, req->best_parent_rate);
795 if (err)
796 return err;
797
798 m = divider->m;
799 d = divider->d;
800 o = divider->o;
801
802 req->rate = mult_frac(req->best_parent_rate, m * 1000 + divider->m_frac,
803 d * (o * 1000 + divider->o_frac));
804 return 0;
805 }
806
clk_wzrd_ver_determine_rate_all(struct clk_hw * hw,struct clk_rate_request * req)807 static int clk_wzrd_ver_determine_rate_all(struct clk_hw *hw,
808 struct clk_rate_request *req)
809 {
810 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
811 unsigned long int_freq;
812 u32 m, d, o, div, f;
813 int err;
814
815 err = clk_wzrd_get_divisors_ver(hw, req->rate, req->best_parent_rate);
816 if (err)
817 return err;
818
819 m = divider->m;
820 d = divider->d;
821 o = divider->o;
822
823 div = d * o;
824 int_freq = divider_recalc_rate(hw, req->best_parent_rate * m, div,
825 divider->table,
826 divider->flags, divider->width);
827
828 if (req->rate > int_freq) {
829 f = DIV_ROUND_CLOSEST_ULL(req->rate * WZRD_FRAC_POINTS,
830 int_freq);
831 req->rate = DIV_ROUND_CLOSEST(int_freq * f, WZRD_FRAC_POINTS);
832 }
833 return 0;
834 }
835
836 static const struct clk_ops clk_wzrd_ver_divider_ops = {
837 .determine_rate = clk_wzrd_determine_rate,
838 .set_rate = clk_wzrd_ver_dynamic_reconfig,
839 .recalc_rate = clk_wzrd_recalc_rate_ver,
840 };
841
842 static const struct clk_ops clk_wzrd_ver_div_all_ops = {
843 .determine_rate = clk_wzrd_ver_determine_rate_all,
844 .set_rate = clk_wzrd_dynamic_all_ver,
845 .recalc_rate = clk_wzrd_recalc_rate_all_ver,
846 };
847
848 static const struct clk_ops clk_wzrd_clk_divider_ops = {
849 .determine_rate = clk_wzrd_determine_rate,
850 .set_rate = clk_wzrd_dynamic_reconfig,
851 .recalc_rate = clk_wzrd_recalc_rate,
852 };
853
854 static const struct clk_ops clk_wzrd_clk_div_all_ops = {
855 .determine_rate = clk_wzrd_determine_rate_all,
856 .set_rate = clk_wzrd_dynamic_all,
857 .recalc_rate = clk_wzrd_recalc_rate_all,
858 };
859
clk_wzrd_recalc_ratef(struct clk_hw * hw,unsigned long parent_rate)860 static unsigned long clk_wzrd_recalc_ratef(struct clk_hw *hw,
861 unsigned long parent_rate)
862 {
863 unsigned int val;
864 u32 div, frac;
865 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
866 void __iomem *div_addr = divider->base + divider->offset;
867
868 val = readl(div_addr);
869 div = val & div_mask(divider->width);
870 frac = (val >> WZRD_CLKOUT_FRAC_SHIFT) & WZRD_CLKOUT_FRAC_MASK;
871
872 return mult_frac(parent_rate, 1000, (div * 1000) + frac);
873 }
874
clk_wzrd_dynamic_reconfig_f(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)875 static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate,
876 unsigned long parent_rate)
877 {
878 int err;
879 u32 value, pre;
880 unsigned long rate_div, f, clockout0_div;
881 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
882 void __iomem *div_addr = divider->base + divider->offset;
883
884 rate_div = DIV_ROUND_DOWN_ULL(parent_rate * 1000, rate);
885 clockout0_div = rate_div / 1000;
886
887 pre = DIV_ROUND_CLOSEST((parent_rate * 1000), rate);
888 f = (u32)(pre - (clockout0_div * 1000));
889 f = f & WZRD_CLKOUT_FRAC_MASK;
890 f = f << WZRD_CLKOUT_DIVIDE_WIDTH;
891
892 value = (f | (clockout0_div & WZRD_CLKOUT_DIVIDE_MASK));
893
894 /* Set divisor and clear phase offset */
895 writel(value, div_addr);
896 writel(0x0, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
897
898 /* Check status register */
899 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
900 value & WZRD_DR_LOCK_BIT_MASK,
901 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
902 if (err)
903 return err;
904
905 /* Initiate reconfiguration */
906 writel(WZRD_DR_BEGIN_DYNA_RECONF_5_2,
907 divider->base + WZRD_DR_INIT_REG_OFFSET);
908 writel(WZRD_DR_BEGIN_DYNA_RECONF1_5_2,
909 divider->base + WZRD_DR_INIT_REG_OFFSET);
910
911 /* Check status register */
912 return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
913 value & WZRD_DR_LOCK_BIT_MASK,
914 WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
915 }
916
clk_wzrd_determine_rate_f(struct clk_hw * hw,struct clk_rate_request * req)917 static int clk_wzrd_determine_rate_f(struct clk_hw *hw,
918 struct clk_rate_request *req)
919 {
920 return 0;
921 }
922
923 static const struct clk_ops clk_wzrd_clk_divider_ops_f = {
924 .determine_rate = clk_wzrd_determine_rate_f,
925 .set_rate = clk_wzrd_dynamic_reconfig_f,
926 .recalc_rate = clk_wzrd_recalc_ratef,
927 };
928
clk_wzrd_register_divf(struct device * dev,const char * name,const char * parent_name,unsigned long flags,void __iomem * base,u16 offset,u8 shift,u8 width,u8 clk_divider_flags,u32 div_type,spinlock_t * lock)929 static struct clk_hw *clk_wzrd_register_divf(struct device *dev,
930 const char *name,
931 const char *parent_name,
932 unsigned long flags,
933 void __iomem *base, u16 offset,
934 u8 shift, u8 width,
935 u8 clk_divider_flags,
936 u32 div_type,
937 spinlock_t *lock)
938 {
939 struct clk_wzrd_divider *div;
940 struct clk_hw *hw;
941 struct clk_init_data init;
942 int ret;
943
944 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
945 if (!div)
946 return ERR_PTR(-ENOMEM);
947
948 init.name = name;
949
950 init.ops = &clk_wzrd_clk_divider_ops_f;
951
952 init.flags = flags;
953 init.parent_names = &parent_name;
954 init.num_parents = 1;
955
956 div->base = base;
957 div->offset = offset;
958 div->shift = shift;
959 div->width = width;
960 div->flags = clk_divider_flags;
961 div->lock = lock;
962 div->hw.init = &init;
963
964 hw = &div->hw;
965 ret = devm_clk_hw_register(dev, hw);
966 if (ret)
967 return ERR_PTR(ret);
968
969 return hw;
970 }
971
clk_wzrd_ver_register_divider(struct device * dev,const char * name,const char * parent_name,unsigned long flags,void __iomem * base,u16 offset,u8 shift,u8 width,u8 clk_divider_flags,u32 div_type,spinlock_t * lock)972 static struct clk_hw *clk_wzrd_ver_register_divider(struct device *dev,
973 const char *name,
974 const char *parent_name,
975 unsigned long flags,
976 void __iomem *base,
977 u16 offset,
978 u8 shift, u8 width,
979 u8 clk_divider_flags,
980 u32 div_type,
981 spinlock_t *lock)
982 {
983 struct clk_wzrd_divider *div;
984 struct clk_hw *hw;
985 struct clk_init_data init;
986 int ret;
987
988 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
989 if (!div)
990 return ERR_PTR(-ENOMEM);
991
992 init.name = name;
993 if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
994 init.ops = &clk_divider_ro_ops;
995 else if (div_type == DIV_O)
996 init.ops = &clk_wzrd_ver_divider_ops;
997 else
998 init.ops = &clk_wzrd_ver_div_all_ops;
999 init.flags = flags;
1000 init.parent_names = &parent_name;
1001 init.num_parents = 1;
1002
1003 div->base = base;
1004 div->offset = offset;
1005 div->shift = shift;
1006 div->width = width;
1007 div->flags = clk_divider_flags;
1008 div->lock = lock;
1009 div->hw.init = &init;
1010
1011 hw = &div->hw;
1012 ret = devm_clk_hw_register(dev, hw);
1013 if (ret)
1014 return ERR_PTR(ret);
1015
1016 return hw;
1017 }
1018
clk_wzrd_register_divider(struct device * dev,const char * name,const char * parent_name,unsigned long flags,void __iomem * base,u16 offset,u8 shift,u8 width,u8 clk_divider_flags,u32 div_type,spinlock_t * lock)1019 static struct clk_hw *clk_wzrd_register_divider(struct device *dev,
1020 const char *name,
1021 const char *parent_name,
1022 unsigned long flags,
1023 void __iomem *base, u16 offset,
1024 u8 shift, u8 width,
1025 u8 clk_divider_flags,
1026 u32 div_type,
1027 spinlock_t *lock)
1028 {
1029 struct clk_wzrd_divider *div;
1030 struct clk_hw *hw;
1031 struct clk_init_data init;
1032 int ret;
1033
1034 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
1035 if (!div)
1036 return ERR_PTR(-ENOMEM);
1037
1038 init.name = name;
1039 if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
1040 init.ops = &clk_divider_ro_ops;
1041 else if (div_type == DIV_O)
1042 init.ops = &clk_wzrd_clk_divider_ops;
1043 else
1044 init.ops = &clk_wzrd_clk_div_all_ops;
1045 init.flags = flags;
1046 init.parent_names = &parent_name;
1047 init.num_parents = 1;
1048
1049 div->base = base;
1050 div->offset = offset;
1051 div->shift = shift;
1052 div->width = width;
1053 div->flags = clk_divider_flags;
1054 div->lock = lock;
1055 div->hw.init = &init;
1056
1057 hw = &div->hw;
1058 ret = devm_clk_hw_register(dev, hw);
1059 if (ret)
1060 return ERR_PTR(ret);
1061
1062 return hw;
1063 }
1064
clk_wzrd_clk_notifier(struct notifier_block * nb,unsigned long event,void * data)1065 static int clk_wzrd_clk_notifier(struct notifier_block *nb, unsigned long event,
1066 void *data)
1067 {
1068 unsigned long max;
1069 struct clk_notifier_data *ndata = data;
1070 struct clk_wzrd *clk_wzrd = to_clk_wzrd(nb);
1071
1072 if (clk_wzrd->suspended)
1073 return NOTIFY_OK;
1074
1075 if (ndata->clk == clk_wzrd->clk_in1)
1076 max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1];
1077 else if (ndata->clk == clk_wzrd->axi_clk)
1078 max = WZRD_ACLK_MAX_FREQ;
1079 else
1080 return NOTIFY_DONE; /* should never happen */
1081
1082 switch (event) {
1083 case PRE_RATE_CHANGE:
1084 if (ndata->new_rate > max)
1085 return NOTIFY_BAD;
1086 return NOTIFY_OK;
1087 case POST_RATE_CHANGE:
1088 case ABORT_RATE_CHANGE:
1089 default:
1090 return NOTIFY_DONE;
1091 }
1092 }
1093
clk_wzrd_suspend(struct device * dev)1094 static int __maybe_unused clk_wzrd_suspend(struct device *dev)
1095 {
1096 struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
1097
1098 clk_disable_unprepare(clk_wzrd->axi_clk);
1099 clk_wzrd->suspended = true;
1100
1101 return 0;
1102 }
1103
clk_wzrd_resume(struct device * dev)1104 static int __maybe_unused clk_wzrd_resume(struct device *dev)
1105 {
1106 int ret;
1107 struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
1108
1109 ret = clk_prepare_enable(clk_wzrd->axi_clk);
1110 if (ret) {
1111 dev_err(dev, "unable to enable s_axi_aclk\n");
1112 return ret;
1113 }
1114
1115 clk_wzrd->suspended = false;
1116
1117 return 0;
1118 }
1119
1120 static SIMPLE_DEV_PM_OPS(clk_wzrd_dev_pm_ops, clk_wzrd_suspend,
1121 clk_wzrd_resume);
1122
1123 static const struct versal_clk_data versal_data = {
1124 .is_versal = true,
1125 };
1126
clk_wzrd_register_output_clocks(struct device * dev,int nr_outputs)1127 static int clk_wzrd_register_output_clocks(struct device *dev, int nr_outputs)
1128 {
1129 const char *clkout_name, *clk_name, *clk_mul_name;
1130 struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
1131 u32 regl, regh, edge, regld, reghd, edged, div;
1132 const struct versal_clk_data *data;
1133 unsigned long flags = 0;
1134 bool is_versal = false;
1135 void __iomem *ctrl_reg;
1136 u32 reg, reg_f, mult;
1137 int i;
1138
1139 data = device_get_match_data(dev);
1140 if (data)
1141 is_versal = data->is_versal;
1142
1143 clkout_name = devm_kasprintf(dev, GFP_KERNEL, "%s_out0", dev_name(dev));
1144 if (!clkout_name)
1145 return -ENOMEM;
1146
1147 if (is_versal) {
1148 if (nr_outputs == 1) {
1149 clk_wzrd->clk_data.hws[0] = clk_wzrd_ver_register_divider
1150 (dev, clkout_name,
1151 __clk_get_name(clk_wzrd->clk_in1), 0,
1152 clk_wzrd->base, WZRD_CLK_CFG_REG(is_versal, 3),
1153 WZRD_CLKOUT_DIVIDE_SHIFT,
1154 WZRD_CLKOUT_DIVIDE_WIDTH,
1155 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
1156 DIV_ALL, &clkwzrd_lock);
1157
1158 return 0;
1159 }
1160 /* register multiplier */
1161 edge = !!(readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0)) &
1162 BIT(8));
1163 regl = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 1)) &
1164 WZRD_CLKFBOUT_L_MASK) >> WZRD_CLKFBOUT_L_SHIFT;
1165 regh = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 1)) &
1166 WZRD_CLKFBOUT_H_MASK) >> WZRD_CLKFBOUT_H_SHIFT;
1167 mult = regl + regh + edge;
1168 if (!mult)
1169 mult = 1;
1170 mult = mult * WZRD_FRAC_GRADIENT;
1171
1172 regl = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 51)) &
1173 WZRD_CLKFBOUT_FRAC_EN;
1174 if (regl) {
1175 regl = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 48)) &
1176 WZRD_VERSAL_FRAC_MASK;
1177 mult = mult + regl;
1178 }
1179 div = 64;
1180 } else {
1181 if (nr_outputs == 1) {
1182 clk_wzrd->clk_data.hws[0] = clk_wzrd_register_divider
1183 (dev, clkout_name,
1184 __clk_get_name(clk_wzrd->clk_in1), 0,
1185 clk_wzrd->base, WZRD_CLK_CFG_REG(is_versal, 3),
1186 WZRD_CLKOUT_DIVIDE_SHIFT,
1187 WZRD_CLKOUT_DIVIDE_WIDTH,
1188 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
1189 DIV_ALL, &clkwzrd_lock);
1190
1191 return 0;
1192 }
1193 reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0));
1194 reg_f = reg & WZRD_CLKFBOUT_FRAC_MASK;
1195 reg_f = reg_f >> WZRD_CLKFBOUT_FRAC_SHIFT;
1196
1197 reg = reg & WZRD_CLKFBOUT_MULT_MASK;
1198 reg = reg >> WZRD_CLKFBOUT_MULT_SHIFT;
1199 mult = (reg * 1000) + reg_f;
1200 div = 1000;
1201 }
1202 clk_name = devm_kasprintf(dev, GFP_KERNEL, "%s_mul", dev_name(dev));
1203 if (!clk_name)
1204 return -ENOMEM;
1205 clk_wzrd->clks_internal[wzrd_clk_mul] = devm_clk_hw_register_fixed_factor
1206 (dev, clk_name,
1207 __clk_get_name(clk_wzrd->clk_in1),
1208 0, mult, div);
1209 if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) {
1210 dev_err(dev, "unable to register fixed-factor clock\n");
1211 return PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]);
1212 }
1213
1214 clk_name = devm_kasprintf(dev, GFP_KERNEL, "%s_mul_div", dev_name(dev));
1215 if (!clk_name)
1216 return -ENOMEM;
1217
1218 if (is_versal) {
1219 edged = !!(readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 20)) &
1220 BIT(10));
1221 regld = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 21)) &
1222 WZRD_CLKFBOUT_L_MASK) >> WZRD_CLKFBOUT_L_SHIFT;
1223 reghd = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 21)) &
1224 WZRD_CLKFBOUT_H_MASK) >> WZRD_CLKFBOUT_H_SHIFT;
1225 div = (regld + reghd + edged);
1226 if (!div)
1227 div = 1;
1228
1229 clk_mul_name = clk_hw_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]);
1230 clk_wzrd->clks_internal[wzrd_clk_mul_div] =
1231 devm_clk_hw_register_fixed_factor(dev, clk_name, clk_mul_name, 0, 1, div);
1232 } else {
1233 ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0);
1234 clk_wzrd->clks_internal[wzrd_clk_mul_div] = devm_clk_hw_register_divider
1235 (dev, clk_name,
1236 clk_hw_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]),
1237 flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED |
1238 CLK_DIVIDER_ALLOW_ZERO, &clkwzrd_lock);
1239 }
1240 if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) {
1241 dev_err(dev, "unable to register divider clock\n");
1242 return PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]);
1243 }
1244
1245 /* register div per output */
1246 for (i = nr_outputs - 1; i >= 0 ; i--) {
1247 clkout_name = devm_kasprintf(dev, GFP_KERNEL, "%s_out%d", dev_name(dev), i);
1248 if (!clkout_name)
1249 return -ENOMEM;
1250
1251 if (is_versal) {
1252 clk_wzrd->clk_data.hws[i] = clk_wzrd_ver_register_divider
1253 (dev,
1254 clkout_name, clk_name, 0,
1255 clk_wzrd->base,
1256 (WZRD_CLK_CFG_REG(is_versal, 2) + i * 8),
1257 WZRD_CLKOUT_DIVIDE_SHIFT,
1258 WZRD_CLKOUT_DIVIDE_WIDTH,
1259 CLK_DIVIDER_ONE_BASED |
1260 CLK_DIVIDER_ALLOW_ZERO,
1261 DIV_O, &clkwzrd_lock);
1262 } else {
1263 if (!i)
1264 clk_wzrd->clk_data.hws[i] = clk_wzrd_register_divf
1265 (dev, clkout_name, clk_name, flags, clk_wzrd->base,
1266 (WZRD_CLK_CFG_REG(is_versal, 2) + i * 12),
1267 WZRD_CLKOUT_DIVIDE_SHIFT,
1268 WZRD_CLKOUT_DIVIDE_WIDTH,
1269 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
1270 DIV_O, &clkwzrd_lock);
1271 else
1272 clk_wzrd->clk_data.hws[i] = clk_wzrd_register_divider
1273 (dev, clkout_name, clk_name, 0, clk_wzrd->base,
1274 (WZRD_CLK_CFG_REG(is_versal, 2) + i * 12),
1275 WZRD_CLKOUT_DIVIDE_SHIFT,
1276 WZRD_CLKOUT_DIVIDE_WIDTH,
1277 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
1278 DIV_O, &clkwzrd_lock);
1279 }
1280 if (IS_ERR(clk_wzrd->clk_data.hws[i])) {
1281 dev_err(dev, "unable to register divider clock\n");
1282 return PTR_ERR(clk_wzrd->clk_data.hws[i]);
1283 }
1284 }
1285
1286 return 0;
1287 }
1288
clk_wzrd_probe(struct platform_device * pdev)1289 static int clk_wzrd_probe(struct platform_device *pdev)
1290 {
1291 struct device_node *np = pdev->dev.of_node;
1292 struct clk_wzrd *clk_wzrd;
1293 unsigned long rate;
1294 int nr_outputs;
1295 int ret;
1296
1297 ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs);
1298 if (ret || nr_outputs > WZRD_NUM_OUTPUTS)
1299 return -EINVAL;
1300
1301 clk_wzrd = devm_kzalloc(&pdev->dev, struct_size(clk_wzrd, clk_data.hws, nr_outputs),
1302 GFP_KERNEL);
1303 if (!clk_wzrd)
1304 return -ENOMEM;
1305 platform_set_drvdata(pdev, clk_wzrd);
1306
1307 clk_wzrd->base = devm_platform_ioremap_resource(pdev, 0);
1308 if (IS_ERR(clk_wzrd->base))
1309 return PTR_ERR(clk_wzrd->base);
1310
1311 clk_wzrd->axi_clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
1312 if (IS_ERR(clk_wzrd->axi_clk))
1313 return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk),
1314 "s_axi_aclk not found\n");
1315 rate = clk_get_rate(clk_wzrd->axi_clk);
1316 if (rate > WZRD_ACLK_MAX_FREQ) {
1317 dev_err(&pdev->dev, "s_axi_aclk frequency (%lu) too high\n", rate);
1318 return -EINVAL;
1319 }
1320
1321 if (!of_property_present(np, "xlnx,static-config")) {
1322 ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade);
1323 if (!ret) {
1324 if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) {
1325 dev_warn(&pdev->dev, "invalid speed grade '%d'\n",
1326 clk_wzrd->speed_grade);
1327 clk_wzrd->speed_grade = 0;
1328 }
1329 }
1330
1331 clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1");
1332 if (IS_ERR(clk_wzrd->clk_in1))
1333 return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1),
1334 "clk_in1 not found\n");
1335
1336 ret = clk_wzrd_register_output_clocks(&pdev->dev, nr_outputs);
1337 if (ret)
1338 return ret;
1339
1340 clk_wzrd->clk_data.num = nr_outputs;
1341 ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get,
1342 &clk_wzrd->clk_data);
1343 if (ret) {
1344 dev_err(&pdev->dev, "unable to register clock provider\n");
1345 return ret;
1346 }
1347
1348 if (clk_wzrd->speed_grade) {
1349 clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier;
1350
1351 ret = devm_clk_notifier_register(&pdev->dev, clk_wzrd->clk_in1,
1352 &clk_wzrd->nb);
1353 if (ret)
1354 dev_warn(&pdev->dev,
1355 "unable to register clock notifier\n");
1356
1357 ret = devm_clk_notifier_register(&pdev->dev, clk_wzrd->axi_clk,
1358 &clk_wzrd->nb);
1359 if (ret)
1360 dev_warn(&pdev->dev,
1361 "unable to register clock notifier\n");
1362 }
1363 }
1364
1365 return 0;
1366 }
1367
1368 static const struct of_device_id clk_wzrd_ids[] = {
1369 { .compatible = "xlnx,versal-clk-wizard", .data = &versal_data },
1370 { .compatible = "xlnx,clocking-wizard" },
1371 { .compatible = "xlnx,clocking-wizard-v5.2" },
1372 { .compatible = "xlnx,clocking-wizard-v6.0" },
1373 { },
1374 };
1375 MODULE_DEVICE_TABLE(of, clk_wzrd_ids);
1376
1377 static struct platform_driver clk_wzrd_driver = {
1378 .driver = {
1379 .name = "clk-wizard",
1380 .of_match_table = clk_wzrd_ids,
1381 .pm = &clk_wzrd_dev_pm_ops,
1382 },
1383 .probe = clk_wzrd_probe,
1384 };
1385 module_platform_driver(clk_wzrd_driver);
1386
1387 MODULE_LICENSE("GPL");
1388 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com");
1389 MODULE_DESCRIPTION("Driver for the Xilinx Clocking Wizard IP core");
1390