1 // SPDX-License-Identifier: GPL-2.0-only
2 /* MCP23S08 SPI/I2C GPIO driver */
3
4 #include <linux/bitops.h>
5 #include <linux/kernel.h>
6 #include <linux/device.h>
7 #include <linux/mutex.h>
8 #include <linux/module.h>
9 #include <linux/export.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/seq_file.h>
13 #include <linux/slab.h>
14 #include <asm/byteorder.h>
15 #include <linux/interrupt.h>
16 #include <linux/regmap.h>
17 #include <linux/pinctrl/pinctrl.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20
21 #include "pinctrl-mcp23s08.h"
22
23 /* Registers are all 8 bits wide.
24 *
25 * The mcp23s17 has twice as many bits, and can be configured to work
26 * with either 16 bit registers or with two adjacent 8 bit banks.
27 */
28 #define MCP_IODIR 0x00 /* init/reset: all ones */
29 #define MCP_IPOL 0x01
30 #define MCP_GPINTEN 0x02
31 #define MCP_DEFVAL 0x03
32 #define MCP_INTCON 0x04
33 #define MCP_IOCON 0x05
34 # define IOCON_MIRROR (1 << 6)
35 # define IOCON_SEQOP (1 << 5)
36 # define IOCON_HAEN (1 << 3)
37 # define IOCON_ODR (1 << 2)
38 # define IOCON_INTPOL (1 << 1)
39 # define IOCON_INTCC (1)
40 #define MCP_GPPU 0x06
41 #define MCP_INTF 0x07
42 #define MCP_INTCAP 0x08
43 #define MCP_GPIO 0x09
44 #define MCP_OLAT 0x0a
45
46 static const struct regmap_range mcp23x08_volatile_range = {
47 .range_min = MCP_INTF,
48 .range_max = MCP_GPIO,
49 };
50
51 static const struct regmap_access_table mcp23x08_volatile_table = {
52 .yes_ranges = &mcp23x08_volatile_range,
53 .n_yes_ranges = 1,
54 };
55
56 static const struct regmap_range mcp23x08_precious_range = {
57 .range_min = MCP_GPIO,
58 .range_max = MCP_GPIO,
59 };
60
61 static const struct regmap_access_table mcp23x08_precious_table = {
62 .yes_ranges = &mcp23x08_precious_range,
63 .n_yes_ranges = 1,
64 };
65
66 const struct regmap_config mcp23x08_regmap = {
67 .reg_bits = 8,
68 .val_bits = 8,
69
70 .reg_stride = 1,
71 .volatile_table = &mcp23x08_volatile_table,
72 .precious_table = &mcp23x08_precious_table,
73 .num_reg_defaults_raw = MCP_OLAT + 1,
74 .cache_type = REGCACHE_MAPLE,
75 .max_register = MCP_OLAT,
76 .disable_locking = true, /* mcp->lock protects the regmap */
77 };
78 EXPORT_SYMBOL_GPL(mcp23x08_regmap);
79
80 static const struct regmap_range mcp23x17_volatile_range = {
81 .range_min = MCP_INTF << 1,
82 .range_max = MCP_GPIO << 1,
83 };
84
85 static const struct regmap_access_table mcp23x17_volatile_table = {
86 .yes_ranges = &mcp23x17_volatile_range,
87 .n_yes_ranges = 1,
88 };
89
90 static const struct regmap_range mcp23x17_precious_range = {
91 .range_min = MCP_INTCAP << 1,
92 .range_max = MCP_GPIO << 1,
93 };
94
95 static const struct regmap_access_table mcp23x17_precious_table = {
96 .yes_ranges = &mcp23x17_precious_range,
97 .n_yes_ranges = 1,
98 };
99
100 const struct regmap_config mcp23x17_regmap = {
101 .reg_bits = 8,
102 .val_bits = 16,
103
104 .reg_stride = 2,
105 .max_register = MCP_OLAT << 1,
106 .volatile_table = &mcp23x17_volatile_table,
107 .precious_table = &mcp23x17_precious_table,
108 .num_reg_defaults_raw = MCP_OLAT + 1,
109 .cache_type = REGCACHE_MAPLE,
110 .val_format_endian = REGMAP_ENDIAN_LITTLE,
111 .disable_locking = true, /* mcp->lock protects the regmap */
112 };
113 EXPORT_SYMBOL_GPL(mcp23x17_regmap);
114
mcp_read(struct mcp23s08 * mcp,unsigned int reg,unsigned int * val)115 static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
116 {
117 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
118 }
119
mcp_write(struct mcp23s08 * mcp,unsigned int reg,unsigned int val)120 static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
121 {
122 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
123 }
124
mcp_update_bits(struct mcp23s08 * mcp,unsigned int reg,unsigned int mask,unsigned int val)125 static int mcp_update_bits(struct mcp23s08 *mcp, unsigned int reg,
126 unsigned int mask, unsigned int val)
127 {
128 return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
129 mask, val);
130 }
131
mcp_set_bit(struct mcp23s08 * mcp,unsigned int reg,unsigned int pin,bool enabled)132 static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
133 unsigned int pin, bool enabled)
134 {
135 u16 mask = BIT(pin);
136 return mcp_update_bits(mcp, reg, mask, enabled ? mask : 0);
137 }
138
139 static const struct pinctrl_pin_desc mcp23x08_pins[] = {
140 PINCTRL_PIN(0, "gpio0"),
141 PINCTRL_PIN(1, "gpio1"),
142 PINCTRL_PIN(2, "gpio2"),
143 PINCTRL_PIN(3, "gpio3"),
144 PINCTRL_PIN(4, "gpio4"),
145 PINCTRL_PIN(5, "gpio5"),
146 PINCTRL_PIN(6, "gpio6"),
147 PINCTRL_PIN(7, "gpio7"),
148 };
149
150 static const struct pinctrl_pin_desc mcp23x17_pins[] = {
151 PINCTRL_PIN(0, "gpio0"),
152 PINCTRL_PIN(1, "gpio1"),
153 PINCTRL_PIN(2, "gpio2"),
154 PINCTRL_PIN(3, "gpio3"),
155 PINCTRL_PIN(4, "gpio4"),
156 PINCTRL_PIN(5, "gpio5"),
157 PINCTRL_PIN(6, "gpio6"),
158 PINCTRL_PIN(7, "gpio7"),
159 PINCTRL_PIN(8, "gpio8"),
160 PINCTRL_PIN(9, "gpio9"),
161 PINCTRL_PIN(10, "gpio10"),
162 PINCTRL_PIN(11, "gpio11"),
163 PINCTRL_PIN(12, "gpio12"),
164 PINCTRL_PIN(13, "gpio13"),
165 PINCTRL_PIN(14, "gpio14"),
166 PINCTRL_PIN(15, "gpio15"),
167 };
168
mcp_pinctrl_get_groups_count(struct pinctrl_dev * pctldev)169 static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
170 {
171 return 0;
172 }
173
mcp_pinctrl_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)174 static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
175 unsigned int group)
176 {
177 return NULL;
178 }
179
mcp_pinctrl_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)180 static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
181 unsigned int group,
182 const unsigned int **pins,
183 unsigned int *num_pins)
184 {
185 return -ENOTSUPP;
186 }
187
188 static const struct pinctrl_ops mcp_pinctrl_ops = {
189 .get_groups_count = mcp_pinctrl_get_groups_count,
190 .get_group_name = mcp_pinctrl_get_group_name,
191 .get_group_pins = mcp_pinctrl_get_group_pins,
192 #ifdef CONFIG_OF
193 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
194 .dt_free_map = pinconf_generic_dt_free_map,
195 #endif
196 };
197
mcp_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)198 static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
199 unsigned long *config)
200 {
201 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
202 enum pin_config_param param = pinconf_to_config_param(*config);
203 unsigned int data, status;
204 int ret;
205
206 switch (param) {
207 case PIN_CONFIG_BIAS_PULL_UP:
208 mutex_lock(&mcp->lock);
209 ret = mcp_read(mcp, MCP_GPPU, &data);
210 mutex_unlock(&mcp->lock);
211 if (ret < 0)
212 return ret;
213 status = (data & BIT(pin)) ? 1 : 0;
214 break;
215 default:
216 return -ENOTSUPP;
217 }
218
219 *config = 0;
220
221 return status ? 0 : -EINVAL;
222 }
223
mcp_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)224 static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
225 unsigned long *configs, unsigned int num_configs)
226 {
227 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
228 enum pin_config_param param;
229 u32 arg;
230 int ret = 0;
231 int i;
232
233 for (i = 0; i < num_configs; i++) {
234 param = pinconf_to_config_param(configs[i]);
235 arg = pinconf_to_config_argument(configs[i]);
236
237 switch (param) {
238 case PIN_CONFIG_BIAS_PULL_UP:
239 mutex_lock(&mcp->lock);
240 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
241 mutex_unlock(&mcp->lock);
242 break;
243 default:
244 dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
245 return -ENOTSUPP;
246 }
247 }
248
249 return ret;
250 }
251
252 static const struct pinconf_ops mcp_pinconf_ops = {
253 .pin_config_get = mcp_pinconf_get,
254 .pin_config_set = mcp_pinconf_set,
255 .is_generic = true,
256 };
257
258 /*----------------------------------------------------------------------*/
259
mcp23s08_direction_input(struct gpio_chip * chip,unsigned offset)260 static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
261 {
262 struct mcp23s08 *mcp = gpiochip_get_data(chip);
263 int status;
264
265 mutex_lock(&mcp->lock);
266 status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
267 mutex_unlock(&mcp->lock);
268
269 return status;
270 }
271
mcp23s08_get(struct gpio_chip * chip,unsigned offset)272 static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
273 {
274 struct mcp23s08 *mcp = gpiochip_get_data(chip);
275 int status, ret;
276
277 mutex_lock(&mcp->lock);
278
279 /* REVISIT reading this clears any IRQ ... */
280 ret = mcp_read(mcp, MCP_GPIO, &status);
281 if (ret < 0)
282 status = 0;
283 else {
284 mcp->cached_gpio = status;
285 status = !!(status & (1 << offset));
286 }
287
288 mutex_unlock(&mcp->lock);
289 return status;
290 }
291
mcp23s08_get_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)292 static int mcp23s08_get_multiple(struct gpio_chip *chip,
293 unsigned long *mask, unsigned long *bits)
294 {
295 struct mcp23s08 *mcp = gpiochip_get_data(chip);
296 unsigned int status;
297 int ret;
298
299 mutex_lock(&mcp->lock);
300
301 /* REVISIT reading this clears any IRQ ... */
302 ret = mcp_read(mcp, MCP_GPIO, &status);
303 if (ret < 0)
304 status = 0;
305 else {
306 mcp->cached_gpio = status;
307 *bits = status;
308 }
309
310 mutex_unlock(&mcp->lock);
311 return ret;
312 }
313
__mcp23s08_set(struct mcp23s08 * mcp,unsigned mask,bool value)314 static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
315 {
316 return mcp_update_bits(mcp, MCP_OLAT, mask, value ? mask : 0);
317 }
318
mcp23s08_set(struct gpio_chip * chip,unsigned int offset,int value)319 static int mcp23s08_set(struct gpio_chip *chip, unsigned int offset, int value)
320 {
321 struct mcp23s08 *mcp = gpiochip_get_data(chip);
322 unsigned mask = BIT(offset);
323 int ret;
324
325 mutex_lock(&mcp->lock);
326 ret = __mcp23s08_set(mcp, mask, !!value);
327 mutex_unlock(&mcp->lock);
328
329 return ret;
330 }
331
mcp23s08_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)332 static int mcp23s08_set_multiple(struct gpio_chip *chip,
333 unsigned long *mask, unsigned long *bits)
334 {
335 struct mcp23s08 *mcp = gpiochip_get_data(chip);
336 int ret;
337
338 mutex_lock(&mcp->lock);
339 ret = mcp_update_bits(mcp, MCP_OLAT, *mask, *bits);
340 mutex_unlock(&mcp->lock);
341
342 return ret;
343 }
344
345 static int
mcp23s08_direction_output(struct gpio_chip * chip,unsigned offset,int value)346 mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
347 {
348 struct mcp23s08 *mcp = gpiochip_get_data(chip);
349 unsigned mask = BIT(offset);
350 int status;
351
352 mutex_lock(&mcp->lock);
353 status = __mcp23s08_set(mcp, mask, value);
354 if (status == 0) {
355 status = mcp_update_bits(mcp, MCP_IODIR, mask, 0);
356 }
357 mutex_unlock(&mcp->lock);
358 return status;
359 }
360
361 /*----------------------------------------------------------------------*/
mcp23s08_irq(int irq,void * data)362 static irqreturn_t mcp23s08_irq(int irq, void *data)
363 {
364 struct mcp23s08 *mcp = data;
365 int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval, gpinten;
366 bool need_unmask = false;
367 unsigned long int enabled_interrupts;
368 unsigned int child_irq;
369 bool intf_set, intcap_changed, gpio_bit_changed,
370 defval_changed, gpio_set;
371
372 mutex_lock(&mcp->lock);
373 if (mcp_read(mcp, MCP_INTF, &intf))
374 goto unlock;
375
376 if (intf == 0) {
377 /* There is no interrupt pending */
378 goto unlock;
379 }
380
381 if (mcp_read(mcp, MCP_INTCON, &intcon))
382 goto unlock;
383
384 if (mcp_read(mcp, MCP_GPINTEN, &gpinten))
385 goto unlock;
386
387 if (mcp_read(mcp, MCP_DEFVAL, &defval))
388 goto unlock;
389
390 /* Mask level interrupts to avoid their immediate reactivation after clearing */
391 if (intcon) {
392 need_unmask = true;
393 if (mcp_write(mcp, MCP_GPINTEN, gpinten & ~intcon))
394 goto unlock;
395 }
396
397 if (mcp_read(mcp, MCP_INTCAP, &intcap))
398 goto unlock;
399
400 /* This clears the interrupt(configurable on S18) */
401 if (mcp_read(mcp, MCP_GPIO, &gpio))
402 goto unlock;
403
404 gpio_orig = mcp->cached_gpio;
405 mcp->cached_gpio = gpio;
406 mutex_unlock(&mcp->lock);
407
408 dev_dbg(mcp->chip.parent,
409 "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
410 intcap, intf, gpio_orig, gpio);
411
412 enabled_interrupts = gpinten;
413 for_each_set_bit(i, &enabled_interrupts, mcp->chip.ngpio) {
414 /*
415 * We must check all of the inputs with enabled interrupts
416 * on the chip, otherwise we may not notice a change
417 * on more than one pin.
418 *
419 * On at least the mcp23s17, INTCAP is only updated
420 * one byte at a time(INTCAPA and INTCAPB are
421 * not written to at the same time - only on a per-bank
422 * basis).
423 *
424 * INTF only contains the single bit that caused the
425 * interrupt per-bank. On the mcp23s17, there is
426 * INTFA and INTFB. If two pins are changed on the A
427 * side at the same time, INTF will only have one bit
428 * set. If one pin on the A side and one pin on the B
429 * side are changed at the same time, INTF will have
430 * two bits set. Thus, INTF can't be the only check
431 * to see if the input has changed.
432 */
433
434 intf_set = intf & BIT(i);
435 if (i < 8 && intf_set)
436 intcap_mask = 0x00FF;
437 else if (i >= 8 && intf_set)
438 intcap_mask = 0xFF00;
439 else
440 intcap_mask = 0x00;
441
442 intcap_changed = (intcap_mask &
443 (intcap & BIT(i))) !=
444 (intcap_mask & (BIT(i) & gpio_orig));
445 gpio_set = BIT(i) & gpio;
446 gpio_bit_changed = (BIT(i) & gpio_orig) !=
447 (BIT(i) & gpio);
448 defval_changed = (BIT(i) & intcon) &&
449 ((BIT(i) & gpio) !=
450 (BIT(i) & defval));
451
452 if (((gpio_bit_changed || intcap_changed) &&
453 (BIT(i) & mcp->irq_rise) && gpio_set) ||
454 ((gpio_bit_changed || intcap_changed) &&
455 (BIT(i) & mcp->irq_fall) && !gpio_set) ||
456 defval_changed) {
457 child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
458 handle_nested_irq(child_irq);
459 }
460 }
461
462 if (need_unmask) {
463 mutex_lock(&mcp->lock);
464 goto unlock;
465 }
466
467 return IRQ_HANDLED;
468
469 unlock:
470 if (need_unmask)
471 if (mcp_write(mcp, MCP_GPINTEN, gpinten))
472 dev_err(mcp->chip.parent, "can't unmask GPINTEN\n");
473
474 mutex_unlock(&mcp->lock);
475 return IRQ_HANDLED;
476 }
477
mcp23s08_irq_mask(struct irq_data * data)478 static void mcp23s08_irq_mask(struct irq_data *data)
479 {
480 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
481 struct mcp23s08 *mcp = gpiochip_get_data(gc);
482 unsigned int pos = irqd_to_hwirq(data);
483
484 mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
485 gpiochip_disable_irq(gc, pos);
486 }
487
mcp23s08_irq_unmask(struct irq_data * data)488 static void mcp23s08_irq_unmask(struct irq_data *data)
489 {
490 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
491 struct mcp23s08 *mcp = gpiochip_get_data(gc);
492 unsigned int pos = irqd_to_hwirq(data);
493
494 gpiochip_enable_irq(gc, pos);
495 mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
496 }
497
mcp23s08_irq_set_type(struct irq_data * data,unsigned int type)498 static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
499 {
500 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
501 struct mcp23s08 *mcp = gpiochip_get_data(gc);
502 unsigned int pos = irqd_to_hwirq(data);
503
504 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
505 mcp_set_bit(mcp, MCP_INTCON, pos, false);
506 mcp->irq_rise |= BIT(pos);
507 mcp->irq_fall |= BIT(pos);
508 } else if (type & IRQ_TYPE_EDGE_RISING) {
509 mcp_set_bit(mcp, MCP_INTCON, pos, false);
510 mcp->irq_rise |= BIT(pos);
511 mcp->irq_fall &= ~BIT(pos);
512 } else if (type & IRQ_TYPE_EDGE_FALLING) {
513 mcp_set_bit(mcp, MCP_INTCON, pos, false);
514 mcp->irq_rise &= ~BIT(pos);
515 mcp->irq_fall |= BIT(pos);
516 } else if (type & IRQ_TYPE_LEVEL_HIGH) {
517 mcp_set_bit(mcp, MCP_INTCON, pos, true);
518 mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
519 } else if (type & IRQ_TYPE_LEVEL_LOW) {
520 mcp_set_bit(mcp, MCP_INTCON, pos, true);
521 mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
522 } else
523 return -EINVAL;
524
525 return 0;
526 }
527
mcp23s08_irq_bus_lock(struct irq_data * data)528 static void mcp23s08_irq_bus_lock(struct irq_data *data)
529 {
530 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
531 struct mcp23s08 *mcp = gpiochip_get_data(gc);
532
533 mutex_lock(&mcp->lock);
534 regcache_cache_only(mcp->regmap, true);
535 }
536
mcp23s08_irq_bus_unlock(struct irq_data * data)537 static void mcp23s08_irq_bus_unlock(struct irq_data *data)
538 {
539 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
540 struct mcp23s08 *mcp = gpiochip_get_data(gc);
541
542 regcache_cache_only(mcp->regmap, false);
543 regcache_sync(mcp->regmap);
544
545 mutex_unlock(&mcp->lock);
546 }
547
mcp23s08_irq_setup(struct mcp23s08 * mcp)548 static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
549 {
550 struct gpio_chip *chip = &mcp->chip;
551 int err;
552 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
553
554 if (mcp->irq_active_high)
555 irqflags |= IRQF_TRIGGER_HIGH;
556 else
557 irqflags |= IRQF_TRIGGER_LOW;
558
559 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
560 mcp23s08_irq,
561 irqflags, dev_name(chip->parent), mcp);
562 if (err)
563 return err;
564
565 return 0;
566 }
567
mcp23s08_irq_print_chip(struct irq_data * d,struct seq_file * p)568 static void mcp23s08_irq_print_chip(struct irq_data *d, struct seq_file *p)
569 {
570 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
571 struct mcp23s08 *mcp = gpiochip_get_data(gc);
572
573 seq_puts(p, dev_name(mcp->dev));
574 }
575
576 static const struct irq_chip mcp23s08_irq_chip = {
577 .irq_mask = mcp23s08_irq_mask,
578 .irq_unmask = mcp23s08_irq_unmask,
579 .irq_set_type = mcp23s08_irq_set_type,
580 .irq_bus_lock = mcp23s08_irq_bus_lock,
581 .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
582 .irq_print_chip = mcp23s08_irq_print_chip,
583 .flags = IRQCHIP_IMMUTABLE,
584 GPIOCHIP_IRQ_RESOURCE_HELPERS,
585 };
586
587 /*----------------------------------------------------------------------*/
588
mcp23s08_probe_one(struct mcp23s08 * mcp,struct device * dev,unsigned int addr,unsigned int type,unsigned int base)589 int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
590 unsigned int addr, unsigned int type, unsigned int base)
591 {
592 int status, ret;
593 bool mirror = false;
594 bool open_drain = false;
595
596 mutex_init(&mcp->lock);
597
598 mcp->dev = dev;
599 mcp->addr = addr;
600
601 mcp->irq_active_high = false;
602
603 mcp->chip.direction_input = mcp23s08_direction_input;
604 mcp->chip.get = mcp23s08_get;
605 mcp->chip.get_multiple = mcp23s08_get_multiple;
606 mcp->chip.direction_output = mcp23s08_direction_output;
607 mcp->chip.set = mcp23s08_set;
608 mcp->chip.set_multiple = mcp23s08_set_multiple;
609
610 mcp->chip.base = base;
611 mcp->chip.can_sleep = true;
612 mcp->chip.parent = dev;
613 mcp->chip.owner = THIS_MODULE;
614
615 mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
616
617 /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
618 * and MCP_IOCON.HAEN = 1, so we work with all chips.
619 */
620
621 ret = mcp_read(mcp, MCP_IOCON, &status);
622 if (ret < 0)
623 return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
624
625 mcp->irq_controller =
626 device_property_read_bool(dev, "interrupt-controller");
627 if (mcp->irq && mcp->irq_controller) {
628 mcp->irq_active_high =
629 device_property_read_bool(dev,
630 "microchip,irq-active-high");
631
632 mirror = device_property_read_bool(dev, "microchip,irq-mirror");
633 open_drain = device_property_read_bool(dev, "drive-open-drain");
634 }
635
636 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
637 mcp->irq_active_high || open_drain) {
638 /* mcp23s17 has IOCON twice, make sure they are in sync */
639 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
640 status |= IOCON_HAEN | (IOCON_HAEN << 8);
641 if (mcp->irq_active_high)
642 status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
643 else
644 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
645
646 if (mirror)
647 status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
648
649 if (open_drain)
650 status |= IOCON_ODR | (IOCON_ODR << 8);
651
652 if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
653 status |= IOCON_INTCC | (IOCON_INTCC << 8);
654
655 ret = mcp_write(mcp, MCP_IOCON, status);
656 if (ret < 0)
657 return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
658 }
659
660 if (mcp->irq && mcp->irq_controller) {
661 struct gpio_irq_chip *girq = &mcp->chip.irq;
662
663 /*
664 * Disable all pin interrupts, to prevent the interrupt handler from
665 * calling nested handlers for any currently-enabled interrupts that
666 * do not (yet) have an actual handler.
667 */
668 ret = mcp_write(mcp, MCP_GPINTEN, 0);
669 if (ret < 0)
670 return dev_err_probe(dev, ret, "can't disable interrupts\n");
671
672 gpio_irq_chip_set_chip(girq, &mcp23s08_irq_chip);
673 /* This will let us handle the parent IRQ in the driver */
674 girq->parent_handler = NULL;
675 girq->num_parents = 0;
676 girq->parents = NULL;
677 girq->default_type = IRQ_TYPE_NONE;
678 girq->handler = handle_simple_irq;
679 girq->threaded = true;
680 }
681
682 ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
683 if (ret < 0)
684 return dev_err_probe(dev, ret, "can't add GPIO chip\n");
685
686 mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
687 mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
688 mcp->pinctrl_desc.npins = mcp->chip.ngpio;
689 if (mcp->pinctrl_desc.npins == 8)
690 mcp->pinctrl_desc.pins = mcp23x08_pins;
691 else if (mcp->pinctrl_desc.npins == 16)
692 mcp->pinctrl_desc.pins = mcp23x17_pins;
693 mcp->pinctrl_desc.owner = THIS_MODULE;
694
695 mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
696 if (IS_ERR(mcp->pctldev))
697 return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
698
699 if (mcp->irq) {
700 ret = mcp23s08_irq_setup(mcp);
701 if (ret)
702 return dev_err_probe(dev, ret, "can't setup IRQ\n");
703 }
704
705 return 0;
706 }
707 EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
708
709 MODULE_DESCRIPTION("MCP23S08 SPI/I2C GPIO driver");
710 MODULE_LICENSE("GPL");
711