1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7 #include "qla_gbl.h"
8
9 #include <linux/delay.h>
10 #include <linux/slab.h>
11 #include <linux/vmalloc.h>
12
13 #include "qla_devtbl.h"
14
15 #ifdef CONFIG_SPARC
16 #include <asm/prom.h>
17 #endif
18
19 #include "qla_target.h"
20
21 /*
22 * QLogic ISP2x00 Hardware Support Function Prototypes.
23 */
24 static int qla2x00_isp_firmware(scsi_qla_host_t *);
25 static int qla2x00_setup_chip(scsi_qla_host_t *);
26 static int qla2x00_fw_ready(scsi_qla_host_t *);
27 static int qla2x00_configure_hba(scsi_qla_host_t *);
28 static int qla2x00_configure_loop(scsi_qla_host_t *);
29 static int qla2x00_configure_local_loop(scsi_qla_host_t *);
30 static int qla2x00_configure_fabric(scsi_qla_host_t *);
31 static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
32 static int qla2x00_restart_isp(scsi_qla_host_t *);
33
34 static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
35 static int qla84xx_init_chip(scsi_qla_host_t *);
36 static int qla25xx_init_queues(struct qla_hw_data *);
37 static void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha,
38 struct event_arg *ea);
39 static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
40 struct event_arg *);
41 static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *);
42
43 /* SRB Extensions ---------------------------------------------------------- */
44
45 void
qla2x00_sp_timeout(struct timer_list * t)46 qla2x00_sp_timeout(struct timer_list *t)
47 {
48 srb_t *sp = timer_container_of(sp, t, u.iocb_cmd.timer);
49 struct srb_iocb *iocb;
50 scsi_qla_host_t *vha = sp->vha;
51
52 WARN_ON(irqs_disabled());
53 iocb = &sp->u.iocb_cmd;
54 iocb->timeout(sp);
55
56 /* ref: TMR */
57 kref_put(&sp->cmd_kref, qla2x00_sp_release);
58
59 if (vha && qla2x00_isp_reg_stat(vha->hw)) {
60 ql_log(ql_log_info, vha, 0x9008,
61 "PCI/Register disconnect.\n");
62 qla_pci_set_eeh_busy(vha);
63 }
64 }
65
qla2x00_sp_free(srb_t * sp)66 void qla2x00_sp_free(srb_t *sp)
67 {
68 struct srb_iocb *iocb = &sp->u.iocb_cmd;
69
70 timer_delete(&iocb->timer);
71 qla2x00_rel_sp(sp);
72 }
73
qla2xxx_rel_done_warning(srb_t * sp,int res)74 void qla2xxx_rel_done_warning(srb_t *sp, int res)
75 {
76 WARN_ONCE(1, "Calling done() of an already freed srb %p object\n", sp);
77 }
78
qla2xxx_rel_free_warning(srb_t * sp)79 void qla2xxx_rel_free_warning(srb_t *sp)
80 {
81 WARN_ONCE(1, "Calling free() of an already freed srb %p object\n", sp);
82 }
83
84 /* Asynchronous Login/Logout Routines -------------------------------------- */
85
86 unsigned long
qla2x00_get_async_timeout(struct scsi_qla_host * vha)87 qla2x00_get_async_timeout(struct scsi_qla_host *vha)
88 {
89 unsigned long tmo;
90 struct qla_hw_data *ha = vha->hw;
91
92 /* Firmware should use switch negotiated r_a_tov for timeout. */
93 tmo = ha->r_a_tov / 10 * 2;
94 if (IS_QLAFX00(ha)) {
95 tmo = FX00_DEF_RATOV * 2;
96 } else if (!IS_FWI2_CAPABLE(ha)) {
97 /*
98 * Except for earlier ISPs where the timeout is seeded from the
99 * initialization control block.
100 */
101 tmo = ha->login_timeout;
102 }
103 return tmo;
104 }
105
qla24xx_abort_iocb_timeout(void * data)106 static void qla24xx_abort_iocb_timeout(void *data)
107 {
108 srb_t *sp = data;
109 struct srb_iocb *abt = &sp->u.iocb_cmd;
110 struct qla_qpair *qpair = sp->qpair;
111 u32 handle;
112 unsigned long flags;
113 int sp_found = 0, cmdsp_found = 0;
114
115 if (sp->cmd_sp)
116 ql_dbg(ql_dbg_async, sp->vha, 0x507c,
117 "Abort timeout - cmd hdl=%x, cmd type=%x hdl=%x, type=%x\n",
118 sp->cmd_sp->handle, sp->cmd_sp->type,
119 sp->handle, sp->type);
120 else
121 ql_dbg(ql_dbg_async, sp->vha, 0x507c,
122 "Abort timeout 2 - hdl=%x, type=%x\n",
123 sp->handle, sp->type);
124
125 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
126 for (handle = 1; handle < qpair->req->num_outstanding_cmds; handle++) {
127 if (sp->cmd_sp && (qpair->req->outstanding_cmds[handle] ==
128 sp->cmd_sp)) {
129 qpair->req->outstanding_cmds[handle] = NULL;
130 cmdsp_found = 1;
131 qla_put_fw_resources(qpair, &sp->cmd_sp->iores);
132 }
133
134 /* removing the abort */
135 if (qpair->req->outstanding_cmds[handle] == sp) {
136 qpair->req->outstanding_cmds[handle] = NULL;
137 sp_found = 1;
138 qla_put_fw_resources(qpair, &sp->iores);
139 break;
140 }
141 }
142 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
143
144 if (cmdsp_found && sp->cmd_sp) {
145 /*
146 * This done function should take care of
147 * original command ref: INIT
148 */
149 sp->cmd_sp->done(sp->cmd_sp, QLA_OS_TIMER_EXPIRED);
150 }
151
152 if (sp_found) {
153 abt->u.abt.comp_status = cpu_to_le16(CS_TIMEOUT);
154 sp->done(sp, QLA_OS_TIMER_EXPIRED);
155 }
156 }
157
qla24xx_abort_sp_done(srb_t * sp,int res)158 static void qla24xx_abort_sp_done(srb_t *sp, int res)
159 {
160 struct srb_iocb *abt = &sp->u.iocb_cmd;
161 srb_t *orig_sp = sp->cmd_sp;
162
163 if (orig_sp)
164 qla_wait_nvme_release_cmd_kref(orig_sp);
165
166 if (sp->flags & SRB_WAKEUP_ON_COMP)
167 complete(&abt->u.abt.comp);
168 else
169 /* ref: INIT */
170 kref_put(&sp->cmd_kref, qla2x00_sp_release);
171 }
172
qla24xx_async_abort_cmd(srb_t * cmd_sp,bool wait)173 int qla24xx_async_abort_cmd(srb_t *cmd_sp, bool wait)
174 {
175 scsi_qla_host_t *vha = cmd_sp->vha;
176 struct srb_iocb *abt_iocb;
177 srb_t *sp;
178 int rval = QLA_FUNCTION_FAILED;
179
180 /* ref: INIT for ABTS command */
181 sp = qla2xxx_get_qpair_sp(cmd_sp->vha, cmd_sp->qpair, cmd_sp->fcport,
182 GFP_ATOMIC);
183 if (!sp)
184 return QLA_MEMORY_ALLOC_FAILED;
185
186 qla_vha_mark_busy(vha);
187 abt_iocb = &sp->u.iocb_cmd;
188 sp->type = SRB_ABT_CMD;
189 sp->name = "abort";
190 sp->qpair = cmd_sp->qpair;
191 sp->cmd_sp = cmd_sp;
192 if (wait)
193 sp->flags = SRB_WAKEUP_ON_COMP;
194
195 init_completion(&abt_iocb->u.abt.comp);
196 /* FW can send 2 x ABTS's timeout/20s */
197 qla2x00_init_async_sp(sp, 42, qla24xx_abort_sp_done);
198 sp->u.iocb_cmd.timeout = qla24xx_abort_iocb_timeout;
199
200 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
201 abt_iocb->u.abt.req_que_no = cpu_to_le16(cmd_sp->qpair->req->id);
202
203 ql_dbg(ql_dbg_async, vha, 0x507c,
204 "Abort command issued - hdl=%x, type=%x\n", cmd_sp->handle,
205 cmd_sp->type);
206
207 rval = qla2x00_start_sp(sp);
208 if (rval != QLA_SUCCESS) {
209 /* ref: INIT */
210 kref_put(&sp->cmd_kref, qla2x00_sp_release);
211 return rval;
212 }
213
214 if (wait) {
215 wait_for_completion(&abt_iocb->u.abt.comp);
216 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
217 QLA_SUCCESS : QLA_ERR_FROM_FW;
218 /* ref: INIT */
219 kref_put(&sp->cmd_kref, qla2x00_sp_release);
220 }
221
222 return rval;
223 }
224
225 void
qla2x00_async_iocb_timeout(void * data)226 qla2x00_async_iocb_timeout(void *data)
227 {
228 srb_t *sp = data;
229 fc_port_t *fcport = sp->fcport;
230 struct srb_iocb *lio = &sp->u.iocb_cmd;
231 int rc, h;
232 unsigned long flags;
233
234 if (fcport) {
235 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
236 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
237 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
238
239 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
240 } else {
241 pr_info("Async-%s timeout - hdl=%x.\n",
242 sp->name, sp->handle);
243 }
244
245 switch (sp->type) {
246 case SRB_LOGIN_CMD:
247 rc = qla24xx_async_abort_cmd(sp, false);
248 if (rc) {
249 /* Retry as needed. */
250 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
251 lio->u.logio.data[1] =
252 lio->u.logio.flags & SRB_LOGIN_RETRIED ?
253 QLA_LOGIO_LOGIN_RETRIED : 0;
254 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
255 for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
256 h++) {
257 if (sp->qpair->req->outstanding_cmds[h] ==
258 sp) {
259 sp->qpair->req->outstanding_cmds[h] =
260 NULL;
261 break;
262 }
263 }
264 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
265 sp->done(sp, QLA_FUNCTION_TIMEOUT);
266 }
267 break;
268 case SRB_LOGOUT_CMD:
269 case SRB_CT_PTHRU_CMD:
270 case SRB_MB_IOCB:
271 case SRB_NACK_PLOGI:
272 case SRB_NACK_PRLI:
273 case SRB_NACK_LOGO:
274 case SRB_CTRL_VP:
275 default:
276 rc = qla24xx_async_abort_cmd(sp, false);
277 if (rc) {
278 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
279 for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
280 h++) {
281 if (sp->qpair->req->outstanding_cmds[h] ==
282 sp) {
283 sp->qpair->req->outstanding_cmds[h] =
284 NULL;
285 break;
286 }
287 }
288 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
289 sp->done(sp, QLA_FUNCTION_TIMEOUT);
290 }
291 break;
292 }
293 }
294
qla2x00_async_login_sp_done(srb_t * sp,int res)295 static void qla2x00_async_login_sp_done(srb_t *sp, int res)
296 {
297 struct scsi_qla_host *vha = sp->vha;
298 struct srb_iocb *lio = &sp->u.iocb_cmd;
299 struct event_arg ea;
300
301 ql_dbg(ql_dbg_disc, vha, 0x20dd,
302 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
303
304 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
305
306 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
307 memset(&ea, 0, sizeof(ea));
308 ea.fcport = sp->fcport;
309 ea.data[0] = lio->u.logio.data[0];
310 ea.data[1] = lio->u.logio.data[1];
311 ea.iop[0] = lio->u.logio.iop[0];
312 ea.iop[1] = lio->u.logio.iop[1];
313 ea.sp = sp;
314 if (res)
315 ea.data[0] = MBS_COMMAND_ERROR;
316 qla24xx_handle_plogi_done_event(vha, &ea);
317 }
318
319 /* ref: INIT */
320 kref_put(&sp->cmd_kref, qla2x00_sp_release);
321 }
322
323 int
qla2x00_async_login(struct scsi_qla_host * vha,fc_port_t * fcport,uint16_t * data)324 qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
325 uint16_t *data)
326 {
327 srb_t *sp;
328 struct srb_iocb *lio;
329 int rval = QLA_FUNCTION_FAILED;
330
331 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) ||
332 fcport->loop_id == FC_NO_LOOP_ID) {
333 ql_log(ql_log_warn, vha, 0xffff,
334 "%s: %8phC - not sending command.\n",
335 __func__, fcport->port_name);
336 return rval;
337 }
338
339 /* ref: INIT */
340 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
341 if (!sp)
342 goto done;
343
344 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND);
345 fcport->flags |= FCF_ASYNC_SENT;
346 fcport->logout_completed = 0;
347
348 sp->type = SRB_LOGIN_CMD;
349 sp->name = "login";
350 sp->gen1 = fcport->rscn_gen;
351 sp->gen2 = fcport->login_gen;
352 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2,
353 qla2x00_async_login_sp_done);
354
355 lio = &sp->u.iocb_cmd;
356 if (N2N_TOPO(fcport->vha->hw) && fcport_is_bigger(fcport)) {
357 lio->u.logio.flags |= SRB_LOGIN_PRLI_ONLY;
358 } else {
359 if (vha->hw->flags.edif_enabled &&
360 DBELL_ACTIVE(vha)) {
361 lio->u.logio.flags |=
362 (SRB_LOGIN_FCSP | SRB_LOGIN_SKIP_PRLI);
363 } else {
364 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
365 }
366 }
367
368 if (NVME_TARGET(vha->hw, fcport))
369 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
370
371 rval = qla2x00_start_sp(sp);
372
373 ql_dbg(ql_dbg_disc, vha, 0x2072,
374 "Async-login - %8phC hdl=%x, loopid=%x portid=%06x retries=%d %s.\n",
375 fcport->port_name, sp->handle, fcport->loop_id,
376 fcport->d_id.b24, fcport->login_retry,
377 lio->u.logio.flags & SRB_LOGIN_FCSP ? "FCSP" : "");
378
379 if (rval != QLA_SUCCESS) {
380 fcport->flags |= FCF_LOGIN_NEEDED;
381 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
382 goto done_free_sp;
383 }
384
385 return rval;
386
387 done_free_sp:
388 /* ref: INIT */
389 kref_put(&sp->cmd_kref, qla2x00_sp_release);
390 fcport->flags &= ~FCF_ASYNC_SENT;
391 done:
392 fcport->flags &= ~FCF_ASYNC_ACTIVE;
393
394 /*
395 * async login failed. Could be due to iocb/exchange resource
396 * being low. Set state DELETED for re-login process to start again.
397 */
398 qla2x00_set_fcport_disc_state(fcport, DSC_DELETED);
399 return rval;
400 }
401
qla2x00_async_logout_sp_done(srb_t * sp,int res)402 static void qla2x00_async_logout_sp_done(srb_t *sp, int res)
403 {
404 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
405 sp->fcport->login_gen++;
406 qlt_logo_completion_handler(sp->fcport, sp->u.iocb_cmd.u.logio.data[0]);
407 /* ref: INIT */
408 kref_put(&sp->cmd_kref, qla2x00_sp_release);
409 }
410
411 int
qla2x00_async_logout(struct scsi_qla_host * vha,fc_port_t * fcport)412 qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
413 {
414 srb_t *sp;
415 int rval = QLA_FUNCTION_FAILED;
416
417 fcport->flags |= FCF_ASYNC_SENT;
418 /* ref: INIT */
419 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
420 if (!sp)
421 goto done;
422
423 sp->type = SRB_LOGOUT_CMD;
424 sp->name = "logout";
425 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2,
426 qla2x00_async_logout_sp_done);
427
428 ql_dbg(ql_dbg_disc, vha, 0x2070,
429 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC explicit %d.\n",
430 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
431 fcport->d_id.b.area, fcport->d_id.b.al_pa,
432 fcport->port_name, fcport->explicit_logout);
433
434 rval = qla2x00_start_sp(sp);
435 if (rval != QLA_SUCCESS)
436 goto done_free_sp;
437 return rval;
438
439 done_free_sp:
440 /* ref: INIT */
441 kref_put(&sp->cmd_kref, qla2x00_sp_release);
442 done:
443 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
444 return rval;
445 }
446
447 void
qla2x00_async_prlo_done(struct scsi_qla_host * vha,fc_port_t * fcport,uint16_t * data)448 qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport,
449 uint16_t *data)
450 {
451 fcport->flags &= ~FCF_ASYNC_ACTIVE;
452 /* Don't re-login in target mode */
453 if (!fcport->tgt_session)
454 qla2x00_mark_device_lost(vha, fcport, 1);
455 qlt_logo_completion_handler(fcport, data[0]);
456 }
457
qla2x00_async_prlo_sp_done(srb_t * sp,int res)458 static void qla2x00_async_prlo_sp_done(srb_t *sp, int res)
459 {
460 struct srb_iocb *lio = &sp->u.iocb_cmd;
461 struct scsi_qla_host *vha = sp->vha;
462
463 sp->fcport->flags &= ~FCF_ASYNC_ACTIVE;
464 if (!test_bit(UNLOADING, &vha->dpc_flags))
465 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport,
466 lio->u.logio.data);
467 /* ref: INIT */
468 kref_put(&sp->cmd_kref, qla2x00_sp_release);
469 }
470
471 int
qla2x00_async_prlo(struct scsi_qla_host * vha,fc_port_t * fcport)472 qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport)
473 {
474 srb_t *sp;
475 int rval;
476
477 rval = QLA_FUNCTION_FAILED;
478 /* ref: INIT */
479 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
480 if (!sp)
481 goto done;
482
483 sp->type = SRB_PRLO_CMD;
484 sp->name = "prlo";
485 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2,
486 qla2x00_async_prlo_sp_done);
487
488 ql_dbg(ql_dbg_disc, vha, 0x2070,
489 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
490 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
491 fcport->d_id.b.area, fcport->d_id.b.al_pa);
492
493 rval = qla2x00_start_sp(sp);
494 if (rval != QLA_SUCCESS)
495 goto done_free_sp;
496
497 return rval;
498
499 done_free_sp:
500 /* ref: INIT */
501 kref_put(&sp->cmd_kref, qla2x00_sp_release);
502 done:
503 fcport->flags &= ~FCF_ASYNC_ACTIVE;
504 return rval;
505 }
506
507 static
qla24xx_handle_adisc_event(scsi_qla_host_t * vha,struct event_arg * ea)508 void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea)
509 {
510 struct fc_port *fcport = ea->fcport;
511 unsigned long flags;
512
513 ql_dbg(ql_dbg_disc, vha, 0x20d2,
514 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n",
515 __func__, fcport->port_name, fcport->disc_state,
516 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2,
517 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id);
518
519 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n",
520 ea->data[0]);
521
522 if (ea->data[0] != MBS_COMMAND_COMPLETE) {
523 ql_dbg(ql_dbg_disc, vha, 0x2066,
524 "%s %8phC: adisc fail: post delete\n",
525 __func__, ea->fcport->port_name);
526
527 spin_lock_irqsave(&vha->work_lock, flags);
528 /* deleted = 0 & logout_on_delete = force fw cleanup */
529 if (fcport->deleted == QLA_SESS_DELETED)
530 fcport->deleted = 0;
531
532 fcport->logout_on_delete = 1;
533 spin_unlock_irqrestore(&vha->work_lock, flags);
534
535 qlt_schedule_sess_for_deletion(ea->fcport);
536 return;
537 }
538
539 if (ea->fcport->disc_state == DSC_DELETE_PEND)
540 return;
541
542 if (ea->sp->gen2 != ea->fcport->login_gen) {
543 /* target side must have changed it. */
544 ql_dbg(ql_dbg_disc, vha, 0x20d3,
545 "%s %8phC generation changed\n",
546 __func__, ea->fcport->port_name);
547 return;
548 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) {
549 qla_rscn_replay(fcport);
550 qlt_schedule_sess_for_deletion(fcport);
551 return;
552 }
553
554 __qla24xx_handle_gpdb_event(vha, ea);
555 }
556
qla_post_els_plogi_work(struct scsi_qla_host * vha,fc_port_t * fcport)557 static int qla_post_els_plogi_work(struct scsi_qla_host *vha, fc_port_t *fcport)
558 {
559 struct qla_work_evt *e;
560
561 e = qla2x00_alloc_work(vha, QLA_EVT_ELS_PLOGI);
562 if (!e)
563 return QLA_FUNCTION_FAILED;
564
565 e->u.fcport.fcport = fcport;
566 fcport->flags |= FCF_ASYNC_ACTIVE;
567 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND);
568 return qla2x00_post_work(vha, e);
569 }
570
qla2x00_async_adisc_sp_done(srb_t * sp,int res)571 static void qla2x00_async_adisc_sp_done(srb_t *sp, int res)
572 {
573 struct scsi_qla_host *vha = sp->vha;
574 struct event_arg ea;
575 struct srb_iocb *lio = &sp->u.iocb_cmd;
576
577 ql_dbg(ql_dbg_disc, vha, 0x2066,
578 "Async done-%s res %x %8phC\n",
579 sp->name, res, sp->fcport->port_name);
580
581 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
582
583 memset(&ea, 0, sizeof(ea));
584 ea.rc = res;
585 ea.data[0] = lio->u.logio.data[0];
586 ea.data[1] = lio->u.logio.data[1];
587 ea.iop[0] = lio->u.logio.iop[0];
588 ea.iop[1] = lio->u.logio.iop[1];
589 ea.fcport = sp->fcport;
590 ea.sp = sp;
591 if (res)
592 ea.data[0] = MBS_COMMAND_ERROR;
593
594 qla24xx_handle_adisc_event(vha, &ea);
595 /* ref: INIT */
596 kref_put(&sp->cmd_kref, qla2x00_sp_release);
597 }
598
599 int
qla2x00_async_adisc(struct scsi_qla_host * vha,fc_port_t * fcport,uint16_t * data)600 qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
601 uint16_t *data)
602 {
603 srb_t *sp;
604 struct srb_iocb *lio;
605 int rval = QLA_FUNCTION_FAILED;
606
607 if (IS_SESSION_DELETED(fcport)) {
608 ql_log(ql_log_warn, vha, 0xffff,
609 "%s: %8phC is being delete - not sending command.\n",
610 __func__, fcport->port_name);
611 fcport->flags &= ~FCF_ASYNC_ACTIVE;
612 return rval;
613 }
614
615 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
616 return rval;
617
618 fcport->flags |= FCF_ASYNC_SENT;
619 /* ref: INIT */
620 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
621 if (!sp)
622 goto done;
623
624 sp->type = SRB_ADISC_CMD;
625 sp->name = "adisc";
626 sp->gen1 = fcport->rscn_gen;
627 sp->gen2 = fcport->login_gen;
628 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2,
629 qla2x00_async_adisc_sp_done);
630
631 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) {
632 lio = &sp->u.iocb_cmd;
633 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
634 }
635
636 ql_dbg(ql_dbg_disc, vha, 0x206f,
637 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n",
638 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name);
639
640 rval = qla2x00_start_sp(sp);
641 if (rval != QLA_SUCCESS)
642 goto done_free_sp;
643
644 return rval;
645
646 done_free_sp:
647 /* ref: INIT */
648 kref_put(&sp->cmd_kref, qla2x00_sp_release);
649 done:
650 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
651 qla2x00_post_async_adisc_work(vha, fcport, data);
652 return rval;
653 }
654
qla2x00_is_reserved_id(scsi_qla_host_t * vha,uint16_t loop_id)655 static bool qla2x00_is_reserved_id(scsi_qla_host_t *vha, uint16_t loop_id)
656 {
657 struct qla_hw_data *ha = vha->hw;
658
659 if (IS_FWI2_CAPABLE(ha))
660 return loop_id > NPH_LAST_HANDLE;
661
662 return (loop_id > ha->max_loop_id && loop_id < SNS_FIRST_LOOP_ID) ||
663 loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST;
664 }
665
666 /**
667 * qla2x00_find_new_loop_id - scan through our port list and find a new usable loop ID
668 * @vha: adapter state pointer.
669 * @dev: port structure pointer.
670 *
671 * Returns:
672 * qla2x00 local function return status code.
673 *
674 * Context:
675 * Kernel context.
676 */
qla2x00_find_new_loop_id(scsi_qla_host_t * vha,fc_port_t * dev)677 static int qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
678 {
679 int rval;
680 struct qla_hw_data *ha = vha->hw;
681 unsigned long flags = 0;
682
683 rval = QLA_SUCCESS;
684
685 spin_lock_irqsave(&ha->vport_slock, flags);
686
687 dev->loop_id = find_first_zero_bit(ha->loop_id_map, LOOPID_MAP_SIZE);
688 if (dev->loop_id >= LOOPID_MAP_SIZE ||
689 qla2x00_is_reserved_id(vha, dev->loop_id)) {
690 dev->loop_id = FC_NO_LOOP_ID;
691 rval = QLA_FUNCTION_FAILED;
692 } else {
693 set_bit(dev->loop_id, ha->loop_id_map);
694 }
695 spin_unlock_irqrestore(&ha->vport_slock, flags);
696
697 if (rval == QLA_SUCCESS)
698 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
699 "Assigning new loopid=%x, portid=%x.\n",
700 dev->loop_id, dev->d_id.b24);
701 else
702 ql_log(ql_log_warn, dev->vha, 0x2087,
703 "No loop_id's available, portid=%x.\n",
704 dev->d_id.b24);
705
706 return rval;
707 }
708
qla2x00_clear_loop_id(fc_port_t * fcport)709 void qla2x00_clear_loop_id(fc_port_t *fcport)
710 {
711 struct qla_hw_data *ha = fcport->vha->hw;
712
713 if (fcport->loop_id == FC_NO_LOOP_ID ||
714 qla2x00_is_reserved_id(fcport->vha, fcport->loop_id))
715 return;
716
717 clear_bit(fcport->loop_id, ha->loop_id_map);
718 fcport->loop_id = FC_NO_LOOP_ID;
719 }
720
qla24xx_handle_gnl_done_event(scsi_qla_host_t * vha,struct event_arg * ea)721 static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
722 struct event_arg *ea)
723 {
724 fc_port_t *fcport, *conflict_fcport;
725 struct get_name_list_extended *e;
726 u16 i, n, found = 0, loop_id;
727 port_id_t id;
728 u64 wwn;
729 u16 data[2];
730 u8 current_login_state, nvme_cls;
731
732 fcport = ea->fcport;
733 ql_dbg(ql_dbg_disc, vha, 0xffff,
734 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d edif %d\n",
735 __func__, fcport->port_name, fcport->disc_state,
736 fcport->fw_login_state, ea->rc,
737 fcport->login_gen, fcport->last_login_gen,
738 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id, fcport->edif.enable);
739
740 if (fcport->disc_state == DSC_DELETE_PEND)
741 return;
742
743 if (ea->rc) { /* rval */
744 if (fcport->login_retry == 0) {
745 ql_dbg(ql_dbg_disc, vha, 0x20de,
746 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
747 fcport->port_name, fcport->login_retry);
748 }
749 return;
750 }
751
752 if (fcport->last_rscn_gen != fcport->rscn_gen) {
753 qla_rscn_replay(fcport);
754 qlt_schedule_sess_for_deletion(fcport);
755 return;
756 } else if (fcport->last_login_gen != fcport->login_gen) {
757 ql_dbg(ql_dbg_disc, vha, 0x20e0,
758 "%s %8phC login gen changed\n",
759 __func__, fcport->port_name);
760 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
761 return;
762 }
763
764 n = ea->data[0] / sizeof(struct get_name_list_extended);
765
766 ql_dbg(ql_dbg_disc, vha, 0x20e1,
767 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
768 __func__, __LINE__, fcport->port_name, n,
769 fcport->d_id.b.domain, fcport->d_id.b.area,
770 fcport->d_id.b.al_pa, fcport->loop_id);
771
772 for (i = 0; i < n; i++) {
773 e = &vha->gnl.l[i];
774 wwn = wwn_to_u64(e->port_name);
775 id.b.domain = e->port_id[2];
776 id.b.area = e->port_id[1];
777 id.b.al_pa = e->port_id[0];
778 id.b.rsvd_1 = 0;
779
780 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
781 continue;
782
783 if (IS_SW_RESV_ADDR(id))
784 continue;
785
786 found = 1;
787
788 loop_id = le16_to_cpu(e->nport_handle);
789 loop_id = (loop_id & 0x7fff);
790 nvme_cls = e->current_login_state >> 4;
791 current_login_state = e->current_login_state & 0xf;
792
793 if (PRLI_PHASE(nvme_cls)) {
794 current_login_state = nvme_cls;
795 fcport->fc4_type &= ~FS_FC4TYPE_FCP;
796 fcport->fc4_type |= FS_FC4TYPE_NVME;
797 } else if (PRLI_PHASE(current_login_state)) {
798 fcport->fc4_type |= FS_FC4TYPE_FCP;
799 fcport->fc4_type &= ~FS_FC4TYPE_NVME;
800 }
801
802 ql_dbg(ql_dbg_disc, vha, 0x20e2,
803 "%s found %8phC CLS [%x|%x] fc4_type %d ID[%06x|%06x] lid[%d|%d]\n",
804 __func__, fcport->port_name,
805 e->current_login_state, fcport->fw_login_state,
806 fcport->fc4_type, id.b24, fcport->d_id.b24,
807 loop_id, fcport->loop_id);
808
809 switch (fcport->disc_state) {
810 case DSC_DELETE_PEND:
811 case DSC_DELETED:
812 break;
813 default:
814 if ((id.b24 != fcport->d_id.b24 &&
815 fcport->d_id.b24 &&
816 fcport->loop_id != FC_NO_LOOP_ID) ||
817 (fcport->loop_id != FC_NO_LOOP_ID &&
818 fcport->loop_id != loop_id)) {
819 ql_dbg(ql_dbg_disc, vha, 0x20e3,
820 "%s %d %8phC post del sess\n",
821 __func__, __LINE__, fcport->port_name);
822 if (fcport->n2n_flag)
823 fcport->d_id.b24 = 0;
824 qlt_schedule_sess_for_deletion(fcport);
825 return;
826 }
827 break;
828 }
829
830 fcport->loop_id = loop_id;
831 if (fcport->n2n_flag)
832 fcport->d_id.b24 = id.b24;
833
834 wwn = wwn_to_u64(fcport->port_name);
835 qlt_find_sess_invalidate_other(vha, wwn,
836 id, loop_id, &conflict_fcport);
837
838 if (conflict_fcport) {
839 /*
840 * Another share fcport share the same loop_id &
841 * nport id. Conflict fcport needs to finish
842 * cleanup before this fcport can proceed to login.
843 */
844 conflict_fcport->conflict = fcport;
845 fcport->login_pause = 1;
846 }
847
848 switch (vha->hw->current_topology) {
849 default:
850 switch (current_login_state) {
851 case DSC_LS_PRLI_COMP:
852 ql_dbg(ql_dbg_disc,
853 vha, 0x20e4, "%s %d %8phC post gpdb\n",
854 __func__, __LINE__, fcport->port_name);
855
856 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
857 fcport->port_type = FCT_INITIATOR;
858 else
859 fcport->port_type = FCT_TARGET;
860 data[0] = data[1] = 0;
861 qla2x00_post_async_adisc_work(vha, fcport,
862 data);
863 break;
864 case DSC_LS_PLOGI_COMP:
865 if (vha->hw->flags.edif_enabled) {
866 /* check to see if App support Secure */
867 qla24xx_post_gpdb_work(vha, fcport, 0);
868 break;
869 }
870 fallthrough;
871 case DSC_LS_PORT_UNAVAIL:
872 default:
873 if (fcport->loop_id == FC_NO_LOOP_ID) {
874 qla2x00_find_new_loop_id(vha, fcport);
875 fcport->fw_login_state =
876 DSC_LS_PORT_UNAVAIL;
877 }
878 ql_dbg(ql_dbg_disc, vha, 0x20e5,
879 "%s %d %8phC\n", __func__, __LINE__,
880 fcport->port_name);
881 qla24xx_fcport_handle_login(vha, fcport);
882 break;
883 }
884 break;
885 case ISP_CFG_N:
886 fcport->fw_login_state = current_login_state;
887 fcport->d_id = id;
888 switch (current_login_state) {
889 case DSC_LS_PRLI_PEND:
890 /*
891 * In the middle of PRLI. Let it finish.
892 * Allow relogin code to recheck state again
893 * with GNL. Push disc_state back to DELETED
894 * so GNL can go out again
895 */
896 qla2x00_set_fcport_disc_state(fcport,
897 DSC_DELETED);
898 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
899 break;
900 case DSC_LS_PRLI_COMP:
901 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
902 fcport->port_type = FCT_INITIATOR;
903 else
904 fcport->port_type = FCT_TARGET;
905
906 data[0] = data[1] = 0;
907 qla2x00_post_async_adisc_work(vha, fcport,
908 data);
909 break;
910 case DSC_LS_PLOGI_COMP:
911 if (vha->hw->flags.edif_enabled &&
912 DBELL_ACTIVE(vha)) {
913 /* check to see if App support secure or not */
914 qla24xx_post_gpdb_work(vha, fcport, 0);
915 break;
916 }
917 if (fcport_is_bigger(fcport)) {
918 /* local adapter is smaller */
919 if (fcport->loop_id != FC_NO_LOOP_ID)
920 qla2x00_clear_loop_id(fcport);
921
922 fcport->loop_id = loop_id;
923 qla24xx_fcport_handle_login(vha,
924 fcport);
925 break;
926 }
927 fallthrough;
928 default:
929 if (fcport_is_smaller(fcport)) {
930 /* local adapter is bigger */
931 if (fcport->loop_id != FC_NO_LOOP_ID)
932 qla2x00_clear_loop_id(fcport);
933
934 fcport->loop_id = loop_id;
935 qla24xx_fcport_handle_login(vha,
936 fcport);
937 }
938 break;
939 }
940 break;
941 } /* switch (ha->current_topology) */
942 }
943
944 if (!found) {
945 switch (vha->hw->current_topology) {
946 case ISP_CFG_F:
947 case ISP_CFG_FL:
948 for (i = 0; i < n; i++) {
949 e = &vha->gnl.l[i];
950 id.b.domain = e->port_id[0];
951 id.b.area = e->port_id[1];
952 id.b.al_pa = e->port_id[2];
953 id.b.rsvd_1 = 0;
954 loop_id = le16_to_cpu(e->nport_handle);
955
956 if (fcport->d_id.b24 == id.b24) {
957 conflict_fcport =
958 qla2x00_find_fcport_by_wwpn(vha,
959 e->port_name, 0);
960 if (conflict_fcport) {
961 ql_dbg(ql_dbg_disc + ql_dbg_verbose,
962 vha, 0x20e5,
963 "%s %d %8phC post del sess\n",
964 __func__, __LINE__,
965 conflict_fcport->port_name);
966 qlt_schedule_sess_for_deletion
967 (conflict_fcport);
968 }
969 }
970 /*
971 * FW already picked this loop id for
972 * another fcport
973 */
974 if (fcport->loop_id == loop_id)
975 fcport->loop_id = FC_NO_LOOP_ID;
976 }
977 qla24xx_fcport_handle_login(vha, fcport);
978 break;
979 case ISP_CFG_N:
980 qla2x00_set_fcport_disc_state(fcport, DSC_DELETED);
981 if (time_after_eq(jiffies, fcport->dm_login_expire)) {
982 if (fcport->n2n_link_reset_cnt < 2) {
983 fcport->n2n_link_reset_cnt++;
984 /*
985 * remote port is not sending PLOGI.
986 * Reset link to kick start his state
987 * machine
988 */
989 set_bit(N2N_LINK_RESET,
990 &vha->dpc_flags);
991 } else {
992 if (fcport->n2n_chip_reset < 1) {
993 ql_log(ql_log_info, vha, 0x705d,
994 "Chip reset to bring laser down");
995 set_bit(ISP_ABORT_NEEDED,
996 &vha->dpc_flags);
997 fcport->n2n_chip_reset++;
998 } else {
999 ql_log(ql_log_info, vha, 0x705d,
1000 "Remote port %8ph is not coming back\n",
1001 fcport->port_name);
1002 fcport->scan_state = 0;
1003 }
1004 }
1005 qla2xxx_wake_dpc(vha);
1006 } else {
1007 /*
1008 * report port suppose to do PLOGI. Give him
1009 * more time. FW will catch it.
1010 */
1011 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1012 }
1013 break;
1014 case ISP_CFG_NL:
1015 qla24xx_fcport_handle_login(vha, fcport);
1016 break;
1017 default:
1018 break;
1019 }
1020 }
1021 } /* gnl_event */
1022
qla24xx_async_gnl_sp_done(srb_t * sp,int res)1023 static void qla24xx_async_gnl_sp_done(srb_t *sp, int res)
1024 {
1025 struct scsi_qla_host *vha = sp->vha;
1026 unsigned long flags;
1027 struct fc_port *fcport = NULL, *tf;
1028 u16 i, n = 0, loop_id;
1029 struct event_arg ea;
1030 struct get_name_list_extended *e;
1031 u64 wwn;
1032 struct list_head h;
1033 bool found = false;
1034
1035 ql_dbg(ql_dbg_disc, vha, 0x20e7,
1036 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
1037 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
1038 sp->u.iocb_cmd.u.mbx.in_mb[2]);
1039
1040
1041 sp->fcport->flags &= ~(FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE);
1042 memset(&ea, 0, sizeof(ea));
1043 ea.sp = sp;
1044 ea.rc = res;
1045
1046 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
1047 sizeof(struct get_name_list_extended)) {
1048 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
1049 sizeof(struct get_name_list_extended);
1050 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
1051 }
1052
1053 for (i = 0; i < n; i++) {
1054 e = &vha->gnl.l[i];
1055 loop_id = le16_to_cpu(e->nport_handle);
1056 /* mask out reserve bit */
1057 loop_id = (loop_id & 0x7fff);
1058 set_bit(loop_id, vha->hw->loop_id_map);
1059 wwn = wwn_to_u64(e->port_name);
1060
1061 ql_dbg(ql_dbg_disc, vha, 0x20e8,
1062 "%s %8phC %02x:%02x:%02x CLS %x/%x lid %x \n",
1063 __func__, &wwn, e->port_id[2], e->port_id[1],
1064 e->port_id[0], e->current_login_state, e->last_login_state,
1065 (loop_id & 0x7fff));
1066 }
1067
1068 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1069
1070 INIT_LIST_HEAD(&h);
1071 fcport = tf = NULL;
1072 if (!list_empty(&vha->gnl.fcports))
1073 list_splice_init(&vha->gnl.fcports, &h);
1074 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1075
1076 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
1077 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1078 list_del_init(&fcport->gnl_entry);
1079 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
1080 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1081 ea.fcport = fcport;
1082
1083 qla24xx_handle_gnl_done_event(vha, &ea);
1084 }
1085
1086 /* create new fcport if fw has knowledge of new sessions */
1087 for (i = 0; i < n; i++) {
1088 port_id_t id;
1089 u64 wwnn;
1090
1091 e = &vha->gnl.l[i];
1092 wwn = wwn_to_u64(e->port_name);
1093
1094 found = false;
1095 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) {
1096 if (!memcmp((u8 *)&wwn, fcport->port_name,
1097 WWN_SIZE)) {
1098 found = true;
1099 break;
1100 }
1101 }
1102
1103 id.b.domain = e->port_id[2];
1104 id.b.area = e->port_id[1];
1105 id.b.al_pa = e->port_id[0];
1106 id.b.rsvd_1 = 0;
1107
1108 if (!found && wwn && !IS_SW_RESV_ADDR(id)) {
1109 ql_dbg(ql_dbg_disc, vha, 0x2065,
1110 "%s %d %8phC %06x post new sess\n",
1111 __func__, __LINE__, (u8 *)&wwn, id.b24);
1112 wwnn = wwn_to_u64(e->node_name);
1113 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn,
1114 (u8 *)&wwnn, NULL, 0);
1115 }
1116 }
1117
1118 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1119 vha->gnl.sent = 0;
1120 if (!list_empty(&vha->gnl.fcports)) {
1121 /* retrigger gnl */
1122 list_for_each_entry_safe(fcport, tf, &vha->gnl.fcports,
1123 gnl_entry) {
1124 list_del_init(&fcport->gnl_entry);
1125 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
1126 if (qla24xx_post_gnl_work(vha, fcport) == QLA_SUCCESS)
1127 break;
1128 }
1129 }
1130 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1131
1132 /* ref: INIT */
1133 kref_put(&sp->cmd_kref, qla2x00_sp_release);
1134 }
1135
qla24xx_async_gnl(struct scsi_qla_host * vha,fc_port_t * fcport)1136 int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
1137 {
1138 srb_t *sp;
1139 int rval = QLA_FUNCTION_FAILED;
1140 unsigned long flags;
1141 u16 *mb;
1142
1143 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
1144 goto done;
1145
1146 ql_dbg(ql_dbg_disc, vha, 0x20d9,
1147 "Async-gnlist WWPN %8phC \n", fcport->port_name);
1148
1149 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1150 fcport->flags |= FCF_ASYNC_SENT;
1151 qla2x00_set_fcport_disc_state(fcport, DSC_GNL);
1152 fcport->last_rscn_gen = fcport->rscn_gen;
1153 fcport->last_login_gen = fcport->login_gen;
1154
1155 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
1156 if (vha->gnl.sent) {
1157 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1158 return QLA_SUCCESS;
1159 }
1160 vha->gnl.sent = 1;
1161 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1162
1163 /* ref: INIT */
1164 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1165 if (!sp)
1166 goto done;
1167
1168 sp->type = SRB_MB_IOCB;
1169 sp->name = "gnlist";
1170 sp->gen1 = fcport->rscn_gen;
1171 sp->gen2 = fcport->login_gen;
1172 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2,
1173 qla24xx_async_gnl_sp_done);
1174
1175 mb = sp->u.iocb_cmd.u.mbx.out_mb;
1176 mb[0] = MBC_PORT_NODE_NAME_LIST;
1177 mb[1] = BIT_2 | BIT_3;
1178 mb[2] = MSW(vha->gnl.ldma);
1179 mb[3] = LSW(vha->gnl.ldma);
1180 mb[6] = MSW(MSD(vha->gnl.ldma));
1181 mb[7] = LSW(MSD(vha->gnl.ldma));
1182 mb[8] = vha->gnl.size;
1183 mb[9] = vha->vp_idx;
1184
1185 ql_dbg(ql_dbg_disc, vha, 0x20da,
1186 "Async-%s - OUT WWPN %8phC hndl %x\n",
1187 sp->name, fcport->port_name, sp->handle);
1188
1189 rval = qla2x00_start_sp(sp);
1190 if (rval != QLA_SUCCESS)
1191 goto done_free_sp;
1192
1193 return rval;
1194
1195 done_free_sp:
1196 /*
1197 * use qla24xx_async_gnl_sp_done to purge all pending gnl request.
1198 * kref_put is call behind the scene.
1199 */
1200 sp->u.iocb_cmd.u.mbx.in_mb[0] = MBS_COMMAND_ERROR;
1201 qla24xx_async_gnl_sp_done(sp, QLA_COMMAND_ERROR);
1202 fcport->flags &= ~(FCF_ASYNC_SENT);
1203 done:
1204 fcport->flags &= ~(FCF_ASYNC_ACTIVE);
1205 return rval;
1206 }
1207
qla24xx_post_gnl_work(struct scsi_qla_host * vha,fc_port_t * fcport)1208 int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
1209 {
1210 struct qla_work_evt *e;
1211
1212 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
1213 if (!e)
1214 return QLA_FUNCTION_FAILED;
1215
1216 e->u.fcport.fcport = fcport;
1217 fcport->flags |= FCF_ASYNC_ACTIVE;
1218 return qla2x00_post_work(vha, e);
1219 }
1220
qla24xx_async_gpdb_sp_done(srb_t * sp,int res)1221 static void qla24xx_async_gpdb_sp_done(srb_t *sp, int res)
1222 {
1223 struct scsi_qla_host *vha = sp->vha;
1224 struct qla_hw_data *ha = vha->hw;
1225 fc_port_t *fcport = sp->fcport;
1226 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
1227 struct event_arg ea;
1228
1229 ql_dbg(ql_dbg_disc, vha, 0x20db,
1230 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
1231 sp->name, res, fcport->port_name, mb[1], mb[2]);
1232
1233 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
1234
1235 if (res == QLA_FUNCTION_TIMEOUT)
1236 goto done;
1237
1238 memset(&ea, 0, sizeof(ea));
1239 ea.fcport = fcport;
1240 ea.sp = sp;
1241
1242 qla24xx_handle_gpdb_event(vha, &ea);
1243
1244 done:
1245 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
1246 sp->u.iocb_cmd.u.mbx.in_dma);
1247
1248 kref_put(&sp->cmd_kref, qla2x00_sp_release);
1249 }
1250
qla24xx_post_prli_work(struct scsi_qla_host * vha,fc_port_t * fcport)1251 int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
1252 {
1253 struct qla_work_evt *e;
1254
1255 if (vha->host->active_mode == MODE_TARGET)
1256 return QLA_FUNCTION_FAILED;
1257
1258 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
1259 if (!e)
1260 return QLA_FUNCTION_FAILED;
1261
1262 e->u.fcport.fcport = fcport;
1263
1264 return qla2x00_post_work(vha, e);
1265 }
1266
qla2x00_async_prli_sp_done(srb_t * sp,int res)1267 static void qla2x00_async_prli_sp_done(srb_t *sp, int res)
1268 {
1269 struct scsi_qla_host *vha = sp->vha;
1270 struct srb_iocb *lio = &sp->u.iocb_cmd;
1271 struct event_arg ea;
1272
1273 ql_dbg(ql_dbg_disc, vha, 0x2129,
1274 "%s %8phC res %x\n", __func__,
1275 sp->fcport->port_name, res);
1276
1277 sp->fcport->flags &= ~FCF_ASYNC_SENT;
1278
1279 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
1280 memset(&ea, 0, sizeof(ea));
1281 ea.fcport = sp->fcport;
1282 ea.data[0] = lio->u.logio.data[0];
1283 ea.data[1] = lio->u.logio.data[1];
1284 ea.iop[0] = lio->u.logio.iop[0];
1285 ea.iop[1] = lio->u.logio.iop[1];
1286 ea.sp = sp;
1287 if (res == QLA_OS_TIMER_EXPIRED)
1288 ea.data[0] = QLA_OS_TIMER_EXPIRED;
1289 else if (res)
1290 ea.data[0] = MBS_COMMAND_ERROR;
1291
1292 qla24xx_handle_prli_done_event(vha, &ea);
1293 }
1294
1295 kref_put(&sp->cmd_kref, qla2x00_sp_release);
1296 }
1297
1298 int
qla24xx_async_prli(struct scsi_qla_host * vha,fc_port_t * fcport)1299 qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
1300 {
1301 srb_t *sp;
1302 struct srb_iocb *lio;
1303 int rval = QLA_FUNCTION_FAILED;
1304
1305 if (!vha->flags.online) {
1306 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n",
1307 __func__, __LINE__, fcport->port_name);
1308 return rval;
1309 }
1310
1311 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
1312 fcport->fw_login_state == DSC_LS_PRLI_PEND) &&
1313 qla_dual_mode_enabled(vha)) {
1314 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n",
1315 __func__, __LINE__, fcport->port_name);
1316 return rval;
1317 }
1318
1319 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1320 if (!sp)
1321 return rval;
1322
1323 fcport->flags |= FCF_ASYNC_SENT;
1324 fcport->logout_completed = 0;
1325
1326 sp->type = SRB_PRLI_CMD;
1327 sp->name = "prli";
1328 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2,
1329 qla2x00_async_prli_sp_done);
1330
1331 lio = &sp->u.iocb_cmd;
1332 lio->u.logio.flags = 0;
1333
1334 if (NVME_TARGET(vha->hw, fcport))
1335 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
1336
1337 ql_dbg(ql_dbg_disc, vha, 0x211b,
1338 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d fc4type %x priority %x %s.\n",
1339 fcport->port_name, sp->handle, fcport->loop_id, fcport->d_id.b24,
1340 fcport->login_retry, fcport->fc4_type, vha->hw->fc4_type_priority,
1341 NVME_TARGET(vha->hw, fcport) ? "nvme" : "fcp");
1342
1343 rval = qla2x00_start_sp(sp);
1344 if (rval != QLA_SUCCESS) {
1345 fcport->flags |= FCF_LOGIN_NEEDED;
1346 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1347 goto done_free_sp;
1348 }
1349
1350 return rval;
1351
1352 done_free_sp:
1353 /* ref: INIT */
1354 kref_put(&sp->cmd_kref, qla2x00_sp_release);
1355 fcport->flags &= ~FCF_ASYNC_SENT;
1356 return rval;
1357 }
1358
qla24xx_post_gpdb_work(struct scsi_qla_host * vha,fc_port_t * fcport,u8 opt)1359 int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
1360 {
1361 struct qla_work_evt *e;
1362
1363 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
1364 if (!e)
1365 return QLA_FUNCTION_FAILED;
1366
1367 e->u.fcport.fcport = fcport;
1368 e->u.fcport.opt = opt;
1369 fcport->flags |= FCF_ASYNC_ACTIVE;
1370 return qla2x00_post_work(vha, e);
1371 }
1372
qla24xx_async_gpdb(struct scsi_qla_host * vha,fc_port_t * fcport,u8 opt)1373 int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
1374 {
1375 srb_t *sp;
1376 struct srb_iocb *mbx;
1377 int rval = QLA_FUNCTION_FAILED;
1378 u16 *mb;
1379 dma_addr_t pd_dma;
1380 struct port_database_24xx *pd;
1381 struct qla_hw_data *ha = vha->hw;
1382
1383 if (IS_SESSION_DELETED(fcport)) {
1384 ql_log(ql_log_warn, vha, 0xffff,
1385 "%s: %8phC is being delete - not sending command.\n",
1386 __func__, fcport->port_name);
1387 fcport->flags &= ~FCF_ASYNC_ACTIVE;
1388 return rval;
1389 }
1390
1391 if (!vha->flags.online || fcport->flags & FCF_ASYNC_SENT) {
1392 ql_log(ql_log_warn, vha, 0xffff,
1393 "%s: %8phC online %d flags %x - not sending command.\n",
1394 __func__, fcport->port_name, vha->flags.online, fcport->flags);
1395 goto done;
1396 }
1397
1398 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1399 if (!sp)
1400 goto done;
1401
1402 qla2x00_set_fcport_disc_state(fcport, DSC_GPDB);
1403
1404 fcport->flags |= FCF_ASYNC_SENT;
1405 sp->type = SRB_MB_IOCB;
1406 sp->name = "gpdb";
1407 sp->gen1 = fcport->rscn_gen;
1408 sp->gen2 = fcport->login_gen;
1409 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2,
1410 qla24xx_async_gpdb_sp_done);
1411
1412 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1413 if (pd == NULL) {
1414 ql_log(ql_log_warn, vha, 0xd043,
1415 "Failed to allocate port database structure.\n");
1416 goto done_free_sp;
1417 }
1418
1419 mb = sp->u.iocb_cmd.u.mbx.out_mb;
1420 mb[0] = MBC_GET_PORT_DATABASE;
1421 mb[1] = fcport->loop_id;
1422 mb[2] = MSW(pd_dma);
1423 mb[3] = LSW(pd_dma);
1424 mb[6] = MSW(MSD(pd_dma));
1425 mb[7] = LSW(MSD(pd_dma));
1426 mb[9] = vha->vp_idx;
1427 mb[10] = opt;
1428
1429 mbx = &sp->u.iocb_cmd;
1430 mbx->u.mbx.in = (void *)pd;
1431 mbx->u.mbx.in_dma = pd_dma;
1432
1433 ql_dbg(ql_dbg_disc, vha, 0x20dc,
1434 "Async-%s %8phC hndl %x opt %x\n",
1435 sp->name, fcport->port_name, sp->handle, opt);
1436
1437 rval = qla2x00_start_sp(sp);
1438 if (rval != QLA_SUCCESS)
1439 goto done_free_sp;
1440 return rval;
1441
1442 done_free_sp:
1443 if (pd)
1444 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1445
1446 kref_put(&sp->cmd_kref, qla2x00_sp_release);
1447 fcport->flags &= ~FCF_ASYNC_SENT;
1448 done:
1449 fcport->flags &= ~FCF_ASYNC_ACTIVE;
1450 qla24xx_post_gpdb_work(vha, fcport, opt);
1451 return rval;
1452 }
1453
1454 static
__qla24xx_handle_gpdb_event(scsi_qla_host_t * vha,struct event_arg * ea)1455 void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
1456 {
1457 unsigned long flags;
1458
1459 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1460 ea->fcport->login_gen++;
1461 ea->fcport->logout_on_delete = 1;
1462
1463 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
1464 vha->fcport_count++;
1465 ea->fcport->login_succ = 1;
1466
1467 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1468 qla24xx_sched_upd_fcport(ea->fcport);
1469 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1470 } else if (ea->fcport->login_succ) {
1471 /*
1472 * We have an existing session. A late RSCN delivery
1473 * must have triggered the session to be re-validate.
1474 * Session is still valid.
1475 */
1476 ql_dbg(ql_dbg_disc, vha, 0x20d6,
1477 "%s %d %8phC session revalidate success\n",
1478 __func__, __LINE__, ea->fcport->port_name);
1479 qla2x00_set_fcport_disc_state(ea->fcport, DSC_LOGIN_COMPLETE);
1480 }
1481 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1482 }
1483
qla_chk_secure_login(scsi_qla_host_t * vha,fc_port_t * fcport,struct port_database_24xx * pd)1484 static int qla_chk_secure_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1485 struct port_database_24xx *pd)
1486 {
1487 int rc = 0;
1488
1489 if (pd->secure_login) {
1490 ql_dbg(ql_dbg_disc, vha, 0x104d,
1491 "Secure Login established on %8phC\n",
1492 fcport->port_name);
1493 fcport->flags |= FCF_FCSP_DEVICE;
1494 } else {
1495 ql_dbg(ql_dbg_disc, vha, 0x104d,
1496 "non-Secure Login %8phC",
1497 fcport->port_name);
1498 fcport->flags &= ~FCF_FCSP_DEVICE;
1499 }
1500 if (vha->hw->flags.edif_enabled) {
1501 if (fcport->flags & FCF_FCSP_DEVICE) {
1502 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_AUTH_PEND);
1503 /* Start edif prli timer & ring doorbell for app */
1504 fcport->edif.rx_sa_set = 0;
1505 fcport->edif.tx_sa_set = 0;
1506 fcport->edif.rx_sa_pending = 0;
1507 fcport->edif.tx_sa_pending = 0;
1508
1509 qla2x00_post_aen_work(vha, FCH_EVT_PORT_ONLINE,
1510 fcport->d_id.b24);
1511
1512 if (DBELL_ACTIVE(vha)) {
1513 ql_dbg(ql_dbg_disc, vha, 0x20ef,
1514 "%s %d %8phC EDIF: post DB_AUTH: AUTH needed\n",
1515 __func__, __LINE__, fcport->port_name);
1516 fcport->edif.app_sess_online = 1;
1517
1518 qla_edb_eventcreate(vha, VND_CMD_AUTH_STATE_NEEDED,
1519 fcport->d_id.b24, 0, fcport);
1520 }
1521
1522 rc = 1;
1523 } else if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
1524 ql_dbg(ql_dbg_disc, vha, 0x2117,
1525 "%s %d %8phC post prli\n",
1526 __func__, __LINE__, fcport->port_name);
1527 qla24xx_post_prli_work(vha, fcport);
1528 rc = 1;
1529 }
1530 }
1531 return rc;
1532 }
1533
1534 static
qla24xx_handle_gpdb_event(scsi_qla_host_t * vha,struct event_arg * ea)1535 void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
1536 {
1537 fc_port_t *fcport = ea->fcport;
1538 struct port_database_24xx *pd;
1539 struct srb *sp = ea->sp;
1540 uint8_t ls;
1541
1542 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
1543
1544 fcport->flags &= ~FCF_ASYNC_SENT;
1545
1546 ql_dbg(ql_dbg_disc, vha, 0x20d2,
1547 "%s %8phC DS %d LS %x fc4_type %x rc %x\n", __func__,
1548 fcport->port_name, fcport->disc_state, pd->current_login_state,
1549 fcport->fc4_type, ea->rc);
1550
1551 if (fcport->disc_state == DSC_DELETE_PEND) {
1552 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC\n",
1553 __func__, __LINE__, fcport->port_name);
1554 return;
1555 }
1556
1557 if (NVME_TARGET(vha->hw, fcport))
1558 ls = pd->current_login_state >> 4;
1559 else
1560 ls = pd->current_login_state & 0xf;
1561
1562 if (ea->sp->gen2 != fcport->login_gen) {
1563 /* target side must have changed it. */
1564
1565 ql_dbg(ql_dbg_disc, vha, 0x20d3,
1566 "%s %8phC generation changed\n",
1567 __func__, fcport->port_name);
1568 return;
1569 } else if (ea->sp->gen1 != fcport->rscn_gen) {
1570 qla_rscn_replay(fcport);
1571 qlt_schedule_sess_for_deletion(fcport);
1572 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC, ls %x\n",
1573 __func__, __LINE__, fcport->port_name, ls);
1574 return;
1575 }
1576
1577 switch (ls) {
1578 case PDS_PRLI_COMPLETE:
1579 __qla24xx_parse_gpdb(vha, fcport, pd);
1580 break;
1581 case PDS_PLOGI_COMPLETE:
1582 if (qla_chk_secure_login(vha, fcport, pd)) {
1583 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC, ls %x\n",
1584 __func__, __LINE__, fcport->port_name, ls);
1585 return;
1586 }
1587 fallthrough;
1588 case PDS_PLOGI_PENDING:
1589 case PDS_PRLI_PENDING:
1590 case PDS_PRLI2_PENDING:
1591 /* Set discovery state back to GNL to Relogin attempt */
1592 if (qla_dual_mode_enabled(vha) ||
1593 qla_ini_mode_enabled(vha)) {
1594 qla2x00_set_fcport_disc_state(fcport, DSC_GNL);
1595 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1596 }
1597 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC, ls %x\n",
1598 __func__, __LINE__, fcport->port_name, ls);
1599 return;
1600 case PDS_LOGO_PENDING:
1601 case PDS_PORT_UNAVAILABLE:
1602 default:
1603 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
1604 __func__, __LINE__, fcport->port_name);
1605 qlt_schedule_sess_for_deletion(fcport);
1606 return;
1607 }
1608 __qla24xx_handle_gpdb_event(vha, ea);
1609 } /* gpdb event */
1610
qla_chk_n2n_b4_login(struct scsi_qla_host * vha,fc_port_t * fcport)1611 static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1612 {
1613 u8 login = 0;
1614 int rc;
1615
1616 ql_dbg(ql_dbg_disc, vha, 0x307b,
1617 "%s %8phC DS %d LS %d lid %d retries=%d\n",
1618 __func__, fcport->port_name, fcport->disc_state,
1619 fcport->fw_login_state, fcport->loop_id, fcport->login_retry);
1620
1621 if (qla_tgt_mode_enabled(vha))
1622 return;
1623
1624 if (qla_dual_mode_enabled(vha)) {
1625 if (N2N_TOPO(vha->hw)) {
1626 u64 mywwn, wwn;
1627
1628 mywwn = wwn_to_u64(vha->port_name);
1629 wwn = wwn_to_u64(fcport->port_name);
1630 if (mywwn > wwn)
1631 login = 1;
1632 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1633 && time_after_eq(jiffies,
1634 fcport->plogi_nack_done_deadline))
1635 login = 1;
1636 } else {
1637 login = 1;
1638 }
1639 } else {
1640 /* initiator mode */
1641 login = 1;
1642 }
1643
1644 if (login && fcport->login_retry) {
1645 fcport->login_retry--;
1646 if (fcport->loop_id == FC_NO_LOOP_ID) {
1647 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
1648 rc = qla2x00_find_new_loop_id(vha, fcport);
1649 if (rc) {
1650 ql_dbg(ql_dbg_disc, vha, 0x20e6,
1651 "%s %d %8phC post del sess - out of loopid\n",
1652 __func__, __LINE__, fcport->port_name);
1653 fcport->scan_state = 0;
1654 qlt_schedule_sess_for_deletion(fcport);
1655 return;
1656 }
1657 }
1658 ql_dbg(ql_dbg_disc, vha, 0x20bf,
1659 "%s %d %8phC post login\n",
1660 __func__, __LINE__, fcport->port_name);
1661 qla2x00_post_async_login_work(vha, fcport, NULL);
1662 }
1663 }
1664
qla24xx_fcport_handle_login(struct scsi_qla_host * vha,fc_port_t * fcport)1665 int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1666 {
1667 u16 data[2];
1668 u16 sec;
1669
1670 ql_dbg(ql_dbg_disc, vha, 0x20d8,
1671 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d lid %d scan %d fc4type %x\n",
1672 __func__, fcport->port_name, fcport->disc_state,
1673 fcport->fw_login_state, fcport->login_pause, fcport->flags,
1674 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
1675 fcport->login_gen, fcport->loop_id, fcport->scan_state,
1676 fcport->fc4_type);
1677
1678 if (fcport->scan_state != QLA_FCPORT_FOUND ||
1679 fcport->disc_state == DSC_DELETE_PEND)
1680 return 0;
1681
1682 if ((fcport->loop_id != FC_NO_LOOP_ID) &&
1683 qla_dual_mode_enabled(vha) &&
1684 ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1685 (fcport->fw_login_state == DSC_LS_PRLI_PEND)))
1686 return 0;
1687
1688 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP &&
1689 !N2N_TOPO(vha->hw)) {
1690 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1691 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1692 return 0;
1693 }
1694 }
1695
1696 /* Target won't initiate port login if fabric is present */
1697 if (vha->host->active_mode == MODE_TARGET && !N2N_TOPO(vha->hw))
1698 return 0;
1699
1700 if (fcport->flags & (FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE)) {
1701 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1702 return 0;
1703 }
1704
1705 switch (fcport->disc_state) {
1706 case DSC_DELETED:
1707 switch (vha->hw->current_topology) {
1708 case ISP_CFG_N:
1709 if (fcport_is_smaller(fcport)) {
1710 /* this adapter is bigger */
1711 if (fcport->login_retry) {
1712 if (fcport->loop_id == FC_NO_LOOP_ID) {
1713 qla2x00_find_new_loop_id(vha,
1714 fcport);
1715 fcport->fw_login_state =
1716 DSC_LS_PORT_UNAVAIL;
1717 }
1718 fcport->login_retry--;
1719 qla_post_els_plogi_work(vha, fcport);
1720 } else {
1721 ql_log(ql_log_info, vha, 0x705d,
1722 "Unable to reach remote port %8phC",
1723 fcport->port_name);
1724 }
1725 } else {
1726 qla24xx_post_gnl_work(vha, fcport);
1727 }
1728 break;
1729 default:
1730 if (fcport->loop_id == FC_NO_LOOP_ID) {
1731 ql_dbg(ql_dbg_disc, vha, 0x20bd,
1732 "%s %d %8phC post gnl\n",
1733 __func__, __LINE__, fcport->port_name);
1734 qla24xx_post_gnl_work(vha, fcport);
1735 } else {
1736 qla_chk_n2n_b4_login(vha, fcport);
1737 }
1738 break;
1739 }
1740 break;
1741
1742 case DSC_GNL:
1743 switch (vha->hw->current_topology) {
1744 case ISP_CFG_N:
1745 if ((fcport->current_login_state & 0xf) == 0x6) {
1746 ql_dbg(ql_dbg_disc, vha, 0x2118,
1747 "%s %d %8phC post GPDB work\n",
1748 __func__, __LINE__, fcport->port_name);
1749 fcport->chip_reset =
1750 vha->hw->base_qpair->chip_reset;
1751 qla24xx_post_gpdb_work(vha, fcport, 0);
1752 } else {
1753 ql_dbg(ql_dbg_disc, vha, 0x2118,
1754 "%s %d %8phC post %s PRLI\n",
1755 __func__, __LINE__, fcport->port_name,
1756 NVME_TARGET(vha->hw, fcport) ? "NVME" :
1757 "FC");
1758 qla24xx_post_prli_work(vha, fcport);
1759 }
1760 break;
1761 default:
1762 if (fcport->login_pause) {
1763 ql_dbg(ql_dbg_disc, vha, 0x20d8,
1764 "%s %d %8phC exit\n",
1765 __func__, __LINE__,
1766 fcport->port_name);
1767 fcport->last_rscn_gen = fcport->rscn_gen;
1768 fcport->last_login_gen = fcport->login_gen;
1769 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1770 break;
1771 }
1772 qla_chk_n2n_b4_login(vha, fcport);
1773 break;
1774 }
1775 break;
1776
1777 case DSC_LOGIN_FAILED:
1778 if (N2N_TOPO(vha->hw))
1779 qla_chk_n2n_b4_login(vha, fcport);
1780 else
1781 qlt_schedule_sess_for_deletion(fcport);
1782 break;
1783
1784 case DSC_LOGIN_COMPLETE:
1785 /* recheck login state */
1786 data[0] = data[1] = 0;
1787 qla2x00_post_async_adisc_work(vha, fcport, data);
1788 break;
1789
1790 case DSC_LOGIN_PEND:
1791 if (vha->hw->flags.edif_enabled)
1792 break;
1793
1794 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
1795 ql_dbg(ql_dbg_disc, vha, 0x2118,
1796 "%s %d %8phC post %s PRLI\n",
1797 __func__, __LINE__, fcport->port_name,
1798 NVME_TARGET(vha->hw, fcport) ? "NVME" : "FC");
1799 qla24xx_post_prli_work(vha, fcport);
1800 }
1801 break;
1802
1803 case DSC_UPD_FCPORT:
1804 sec = jiffies_to_msecs(jiffies -
1805 fcport->jiffies_at_registration)/1000;
1806 if (fcport->sec_since_registration < sec && sec &&
1807 !(sec % 60)) {
1808 fcport->sec_since_registration = sec;
1809 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
1810 "%s %8phC - Slow Rport registration(%d Sec)\n",
1811 __func__, fcport->port_name, sec);
1812 }
1813
1814 if (fcport->next_disc_state != DSC_DELETE_PEND)
1815 fcport->next_disc_state = DSC_ADISC;
1816 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1817 break;
1818
1819 default:
1820 break;
1821 }
1822
1823 return 0;
1824 }
1825
qla24xx_post_newsess_work(struct scsi_qla_host * vha,port_id_t * id,u8 * port_name,u8 * node_name,void * pla,u8 fc4_type)1826 int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
1827 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type)
1828 {
1829 struct qla_work_evt *e;
1830
1831 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
1832 if (!e)
1833 return QLA_FUNCTION_FAILED;
1834
1835 e->u.new_sess.id = *id;
1836 e->u.new_sess.pla = pla;
1837 e->u.new_sess.fc4_type = fc4_type;
1838 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
1839 if (node_name)
1840 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE);
1841
1842 return qla2x00_post_work(vha, e);
1843 }
1844
qla_rscn_gen_tick(scsi_qla_host_t * vha,u32 * ret_rscn_gen)1845 static void qla_rscn_gen_tick(scsi_qla_host_t *vha, u32 *ret_rscn_gen)
1846 {
1847 *ret_rscn_gen = atomic_inc_return(&vha->rscn_gen);
1848 /* memory barrier */
1849 wmb();
1850 }
1851
qla2x00_handle_rscn(scsi_qla_host_t * vha,struct event_arg * ea)1852 void qla2x00_handle_rscn(scsi_qla_host_t *vha, struct event_arg *ea)
1853 {
1854 fc_port_t *fcport;
1855 unsigned long flags;
1856 u32 rscn_gen;
1857
1858 switch (ea->id.b.rsvd_1) {
1859 case RSCN_PORT_ADDR:
1860 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1);
1861 if (fcport) {
1862 if (vha->hw->flags.edif_enabled && DBELL_ACTIVE(vha)) {
1863 /*
1864 * On ipsec start by remote port, Target port
1865 * may use RSCN to trigger initiator to
1866 * relogin. If driver is already in the
1867 * process of a relogin, then ignore the RSCN
1868 * and allow the current relogin to continue.
1869 * This reduces thrashing of the connection.
1870 */
1871 if (atomic_read(&fcport->state) == FCS_ONLINE) {
1872 /*
1873 * If state = online, then set scan_needed=1 to do relogin.
1874 * Otherwise we're already in the middle of a relogin
1875 */
1876 fcport->scan_needed = 1;
1877 qla_rscn_gen_tick(vha, &fcport->rscn_gen);
1878 }
1879 } else {
1880 fcport->scan_needed = 1;
1881 qla_rscn_gen_tick(vha, &fcport->rscn_gen);
1882 }
1883 }
1884 break;
1885 case RSCN_AREA_ADDR:
1886 qla_rscn_gen_tick(vha, &rscn_gen);
1887 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1888 if (fcport->flags & FCF_FCP2_DEVICE &&
1889 atomic_read(&fcport->state) == FCS_ONLINE)
1890 continue;
1891
1892 if ((ea->id.b24 & 0xffff00) == (fcport->d_id.b24 & 0xffff00)) {
1893 fcport->scan_needed = 1;
1894 fcport->rscn_gen = rscn_gen;
1895 }
1896 }
1897 break;
1898 case RSCN_DOM_ADDR:
1899 qla_rscn_gen_tick(vha, &rscn_gen);
1900 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1901 if (fcport->flags & FCF_FCP2_DEVICE &&
1902 atomic_read(&fcport->state) == FCS_ONLINE)
1903 continue;
1904
1905 if ((ea->id.b24 & 0xff0000) == (fcport->d_id.b24 & 0xff0000)) {
1906 fcport->scan_needed = 1;
1907 fcport->rscn_gen = rscn_gen;
1908 }
1909 }
1910 break;
1911 case RSCN_FAB_ADDR:
1912 default:
1913 qla_rscn_gen_tick(vha, &rscn_gen);
1914 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1915 if (fcport->flags & FCF_FCP2_DEVICE &&
1916 atomic_read(&fcport->state) == FCS_ONLINE)
1917 continue;
1918
1919 fcport->scan_needed = 1;
1920 fcport->rscn_gen = rscn_gen;
1921 }
1922 break;
1923 }
1924
1925 spin_lock_irqsave(&vha->work_lock, flags);
1926 if (vha->scan.scan_flags == 0) {
1927 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s: schedule\n", __func__);
1928 vha->scan.scan_flags |= SF_QUEUED;
1929 vha->scan.rscn_gen_start = atomic_read(&vha->rscn_gen);
1930 schedule_delayed_work(&vha->scan.scan_work, 5);
1931 }
1932 spin_unlock_irqrestore(&vha->work_lock, flags);
1933 }
1934
qla24xx_handle_relogin_event(scsi_qla_host_t * vha,struct event_arg * ea)1935 void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1936 struct event_arg *ea)
1937 {
1938 fc_port_t *fcport = ea->fcport;
1939
1940 if (test_bit(UNLOADING, &vha->dpc_flags))
1941 return;
1942
1943 ql_dbg(ql_dbg_disc, vha, 0x2102,
1944 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1945 __func__, fcport->port_name, fcport->disc_state,
1946 fcport->fw_login_state, fcport->login_pause,
1947 fcport->deleted, fcport->conflict,
1948 fcport->last_rscn_gen, fcport->rscn_gen,
1949 fcport->last_login_gen, fcport->login_gen,
1950 fcport->flags);
1951
1952 if (fcport->last_rscn_gen != fcport->rscn_gen) {
1953 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gnl\n",
1954 __func__, __LINE__, fcport->port_name);
1955 qla24xx_post_gnl_work(vha, fcport);
1956 return;
1957 }
1958
1959 qla24xx_fcport_handle_login(vha, fcport);
1960 }
1961
qla_handle_els_plogi_done(scsi_qla_host_t * vha,struct event_arg * ea)1962 void qla_handle_els_plogi_done(scsi_qla_host_t *vha,
1963 struct event_arg *ea)
1964 {
1965 if (N2N_TOPO(vha->hw) && fcport_is_smaller(ea->fcport) &&
1966 vha->hw->flags.edif_enabled) {
1967 /* check to see if App support Secure */
1968 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1969 return;
1970 }
1971
1972 /* for pure Target Mode, PRLI will not be initiated */
1973 if (vha->host->active_mode == MODE_TARGET)
1974 return;
1975
1976 ql_dbg(ql_dbg_disc, vha, 0x2118,
1977 "%s %d %8phC post PRLI\n",
1978 __func__, __LINE__, ea->fcport->port_name);
1979 qla24xx_post_prli_work(vha, ea->fcport);
1980 }
1981
1982 /*
1983 * RSCN(s) came in for this fcport, but the RSCN(s) was not able
1984 * to be consumed by the fcport
1985 */
qla_rscn_replay(fc_port_t * fcport)1986 void qla_rscn_replay(fc_port_t *fcport)
1987 {
1988 struct event_arg ea;
1989
1990 switch (fcport->disc_state) {
1991 case DSC_DELETE_PEND:
1992 return;
1993 default:
1994 break;
1995 }
1996
1997 if (fcport->scan_needed) {
1998 memset(&ea, 0, sizeof(ea));
1999 ea.id = fcport->d_id;
2000 ea.id.b.rsvd_1 = RSCN_PORT_ADDR;
2001 qla2x00_handle_rscn(fcport->vha, &ea);
2002 }
2003 }
2004
2005 static void
qla2x00_tmf_iocb_timeout(void * data)2006 qla2x00_tmf_iocb_timeout(void *data)
2007 {
2008 srb_t *sp = data;
2009 struct srb_iocb *tmf = &sp->u.iocb_cmd;
2010 int rc, h;
2011 unsigned long flags;
2012
2013 if (sp->type == SRB_MARKER)
2014 rc = QLA_FUNCTION_FAILED;
2015 else
2016 rc = qla24xx_async_abort_cmd(sp, false);
2017
2018 if (rc) {
2019 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
2020 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; h++) {
2021 if (sp->qpair->req->outstanding_cmds[h] == sp) {
2022 sp->qpair->req->outstanding_cmds[h] = NULL;
2023 qla_put_fw_resources(sp->qpair, &sp->iores);
2024 break;
2025 }
2026 }
2027 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
2028 tmf->u.tmf.comp_status = cpu_to_le16(CS_TIMEOUT);
2029 tmf->u.tmf.data = QLA_FUNCTION_FAILED;
2030 complete(&tmf->u.tmf.comp);
2031 }
2032 }
2033
qla_marker_sp_done(srb_t * sp,int res)2034 static void qla_marker_sp_done(srb_t *sp, int res)
2035 {
2036 struct srb_iocb *tmf = &sp->u.iocb_cmd;
2037
2038 if (res != QLA_SUCCESS)
2039 ql_dbg(ql_dbg_taskm, sp->vha, 0x8004,
2040 "Async-marker fail hdl=%x portid=%06x ctrl=%x lun=%lld qp=%d.\n",
2041 sp->handle, sp->fcport->d_id.b24, sp->u.iocb_cmd.u.tmf.flags,
2042 sp->u.iocb_cmd.u.tmf.lun, sp->qpair->id);
2043
2044 sp->u.iocb_cmd.u.tmf.data = res;
2045 complete(&tmf->u.tmf.comp);
2046 }
2047
2048 #define START_SP_W_RETRIES(_sp, _rval, _chip_gen, _login_gen) \
2049 {\
2050 int cnt = 5; \
2051 do { \
2052 if (_chip_gen != sp->vha->hw->chip_reset || _login_gen != sp->fcport->login_gen) {\
2053 _rval = -EINVAL; \
2054 break; \
2055 } \
2056 _rval = qla2x00_start_sp(_sp); \
2057 if (_rval == -EAGAIN) \
2058 msleep(1); \
2059 else \
2060 break; \
2061 cnt--; \
2062 } while (cnt); \
2063 }
2064
2065 /**
2066 * qla26xx_marker: send marker IOCB and wait for the completion of it.
2067 * @arg: pointer to argument list.
2068 * It is assume caller will provide an fcport pointer and modifier
2069 */
2070 static int
qla26xx_marker(struct tmf_arg * arg)2071 qla26xx_marker(struct tmf_arg *arg)
2072 {
2073 struct scsi_qla_host *vha = arg->vha;
2074 struct srb_iocb *tm_iocb;
2075 srb_t *sp;
2076 int rval = QLA_FUNCTION_FAILED;
2077 fc_port_t *fcport = arg->fcport;
2078 u32 chip_gen, login_gen;
2079
2080 if (TMF_NOT_READY(arg->fcport)) {
2081 ql_dbg(ql_dbg_taskm, vha, 0x8039,
2082 "FC port not ready for marker loop-id=%x portid=%06x modifier=%x lun=%lld qp=%d.\n",
2083 fcport->loop_id, fcport->d_id.b24,
2084 arg->modifier, arg->lun, arg->qpair->id);
2085 return QLA_SUSPENDED;
2086 }
2087
2088 chip_gen = vha->hw->chip_reset;
2089 login_gen = fcport->login_gen;
2090
2091 /* ref: INIT */
2092 sp = qla2xxx_get_qpair_sp(vha, arg->qpair, fcport, GFP_KERNEL);
2093 if (!sp)
2094 goto done;
2095
2096 sp->type = SRB_MARKER;
2097 sp->name = "marker";
2098 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha), qla_marker_sp_done);
2099 sp->u.iocb_cmd.timeout = qla2x00_tmf_iocb_timeout;
2100
2101 tm_iocb = &sp->u.iocb_cmd;
2102 init_completion(&tm_iocb->u.tmf.comp);
2103 tm_iocb->u.tmf.modifier = arg->modifier;
2104 tm_iocb->u.tmf.lun = arg->lun;
2105 tm_iocb->u.tmf.loop_id = fcport->loop_id;
2106 tm_iocb->u.tmf.vp_index = vha->vp_idx;
2107
2108 START_SP_W_RETRIES(sp, rval, chip_gen, login_gen);
2109
2110 ql_dbg(ql_dbg_taskm, vha, 0x8006,
2111 "Async-marker hdl=%x loop-id=%x portid=%06x modifier=%x lun=%lld qp=%d rval %d.\n",
2112 sp->handle, fcport->loop_id, fcport->d_id.b24,
2113 arg->modifier, arg->lun, sp->qpair->id, rval);
2114
2115 if (rval != QLA_SUCCESS) {
2116 ql_log(ql_log_warn, vha, 0x8031,
2117 "Marker IOCB send failure (%x).\n", rval);
2118 goto done_free_sp;
2119 }
2120
2121 wait_for_completion(&tm_iocb->u.tmf.comp);
2122 rval = tm_iocb->u.tmf.data;
2123
2124 if (rval != QLA_SUCCESS) {
2125 ql_log(ql_log_warn, vha, 0x8019,
2126 "Marker failed hdl=%x loop-id=%x portid=%06x modifier=%x lun=%lld qp=%d rval %d.\n",
2127 sp->handle, fcport->loop_id, fcport->d_id.b24,
2128 arg->modifier, arg->lun, sp->qpair->id, rval);
2129 }
2130
2131 done_free_sp:
2132 /* ref: INIT */
2133 kref_put(&sp->cmd_kref, qla2x00_sp_release);
2134 done:
2135 return rval;
2136 }
2137
qla2x00_tmf_sp_done(srb_t * sp,int res)2138 static void qla2x00_tmf_sp_done(srb_t *sp, int res)
2139 {
2140 struct srb_iocb *tmf = &sp->u.iocb_cmd;
2141
2142 if (res)
2143 tmf->u.tmf.data = res;
2144 complete(&tmf->u.tmf.comp);
2145 }
2146
qla_tmf_wait(struct tmf_arg * arg)2147 static int qla_tmf_wait(struct tmf_arg *arg)
2148 {
2149 /* there are only 2 types of error handling that reaches here, lun or target reset */
2150 if (arg->flags & (TCF_LUN_RESET | TCF_ABORT_TASK_SET | TCF_CLEAR_TASK_SET))
2151 return qla2x00_eh_wait_for_pending_commands(arg->vha,
2152 arg->fcport->d_id.b24, arg->lun, WAIT_LUN);
2153 else
2154 return qla2x00_eh_wait_for_pending_commands(arg->vha,
2155 arg->fcport->d_id.b24, arg->lun, WAIT_TARGET);
2156 }
2157
2158 static int
__qla2x00_async_tm_cmd(struct tmf_arg * arg)2159 __qla2x00_async_tm_cmd(struct tmf_arg *arg)
2160 {
2161 struct scsi_qla_host *vha = arg->vha;
2162 struct srb_iocb *tm_iocb;
2163 srb_t *sp;
2164 int rval = QLA_FUNCTION_FAILED;
2165 fc_port_t *fcport = arg->fcport;
2166 u32 chip_gen, login_gen;
2167 u64 jif;
2168
2169 if (TMF_NOT_READY(arg->fcport)) {
2170 ql_dbg(ql_dbg_taskm, vha, 0x8032,
2171 "FC port not ready for TM command loop-id=%x portid=%06x modifier=%x lun=%lld qp=%d.\n",
2172 fcport->loop_id, fcport->d_id.b24,
2173 arg->modifier, arg->lun, arg->qpair->id);
2174 return QLA_SUSPENDED;
2175 }
2176
2177 chip_gen = vha->hw->chip_reset;
2178 login_gen = fcport->login_gen;
2179
2180 /* ref: INIT */
2181 sp = qla2xxx_get_qpair_sp(vha, arg->qpair, fcport, GFP_KERNEL);
2182 if (!sp)
2183 goto done;
2184
2185 qla_vha_mark_busy(vha);
2186 sp->type = SRB_TM_CMD;
2187 sp->name = "tmf";
2188 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha),
2189 qla2x00_tmf_sp_done);
2190 sp->u.iocb_cmd.timeout = qla2x00_tmf_iocb_timeout;
2191
2192 tm_iocb = &sp->u.iocb_cmd;
2193 init_completion(&tm_iocb->u.tmf.comp);
2194 tm_iocb->u.tmf.flags = arg->flags;
2195 tm_iocb->u.tmf.lun = arg->lun;
2196
2197 START_SP_W_RETRIES(sp, rval, chip_gen, login_gen);
2198
2199 ql_dbg(ql_dbg_taskm, vha, 0x802f,
2200 "Async-tmf hdl=%x loop-id=%x portid=%06x ctrl=%x lun=%lld qp=%d rval=%x.\n",
2201 sp->handle, fcport->loop_id, fcport->d_id.b24,
2202 arg->flags, arg->lun, sp->qpair->id, rval);
2203
2204 if (rval != QLA_SUCCESS)
2205 goto done_free_sp;
2206 wait_for_completion(&tm_iocb->u.tmf.comp);
2207
2208 rval = tm_iocb->u.tmf.data;
2209
2210 if (rval != QLA_SUCCESS) {
2211 ql_log(ql_log_warn, vha, 0x8030,
2212 "TM IOCB failed (%x).\n", rval);
2213 }
2214
2215 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
2216 jif = jiffies;
2217 if (qla_tmf_wait(arg)) {
2218 ql_log(ql_log_info, vha, 0x803e,
2219 "Waited %u ms Nexus=%ld:%06x:%llu.\n",
2220 jiffies_to_msecs(jiffies - jif), vha->host_no,
2221 fcport->d_id.b24, arg->lun);
2222 }
2223
2224 if (chip_gen == vha->hw->chip_reset && login_gen == fcport->login_gen) {
2225 rval = qla26xx_marker(arg);
2226 } else {
2227 ql_log(ql_log_info, vha, 0x803e,
2228 "Skip Marker due to disruption. Nexus=%ld:%06x:%llu.\n",
2229 vha->host_no, fcport->d_id.b24, arg->lun);
2230 rval = QLA_FUNCTION_FAILED;
2231 }
2232 }
2233 if (tm_iocb->u.tmf.data)
2234 rval = tm_iocb->u.tmf.data;
2235
2236 done_free_sp:
2237 /* ref: INIT */
2238 kref_put(&sp->cmd_kref, qla2x00_sp_release);
2239 done:
2240 return rval;
2241 }
2242
qla_put_tmf(struct tmf_arg * arg)2243 static void qla_put_tmf(struct tmf_arg *arg)
2244 {
2245 struct scsi_qla_host *vha = arg->vha;
2246 struct qla_hw_data *ha = vha->hw;
2247 unsigned long flags;
2248
2249 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
2250 ha->active_tmf--;
2251 list_del(&arg->tmf_elem);
2252 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
2253 }
2254
2255 static
qla_get_tmf(struct tmf_arg * arg)2256 int qla_get_tmf(struct tmf_arg *arg)
2257 {
2258 struct scsi_qla_host *vha = arg->vha;
2259 struct qla_hw_data *ha = vha->hw;
2260 unsigned long flags;
2261 fc_port_t *fcport = arg->fcport;
2262 int rc = 0;
2263 struct tmf_arg *t;
2264
2265 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
2266 list_for_each_entry(t, &ha->tmf_active, tmf_elem) {
2267 if (t->fcport == arg->fcport && t->lun == arg->lun) {
2268 /* reject duplicate TMF */
2269 ql_log(ql_log_warn, vha, 0x802c,
2270 "found duplicate TMF. Nexus=%ld:%06x:%llu.\n",
2271 vha->host_no, fcport->d_id.b24, arg->lun);
2272 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
2273 return -EINVAL;
2274 }
2275 }
2276
2277 list_add_tail(&arg->tmf_elem, &ha->tmf_pending);
2278 while (ha->active_tmf >= MAX_ACTIVE_TMF) {
2279 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
2280
2281 msleep(1);
2282
2283 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
2284 if (TMF_NOT_READY(fcport)) {
2285 ql_log(ql_log_warn, vha, 0x802c,
2286 "Unable to acquire TM resource due to disruption.\n");
2287 rc = EIO;
2288 break;
2289 }
2290 if (ha->active_tmf < MAX_ACTIVE_TMF &&
2291 list_is_first(&arg->tmf_elem, &ha->tmf_pending))
2292 break;
2293 }
2294
2295 list_del(&arg->tmf_elem);
2296
2297 if (!rc) {
2298 ha->active_tmf++;
2299 list_add_tail(&arg->tmf_elem, &ha->tmf_active);
2300 }
2301
2302 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
2303
2304 return rc;
2305 }
2306
2307 int
qla2x00_async_tm_cmd(fc_port_t * fcport,uint32_t flags,uint64_t lun,uint32_t tag)2308 qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint64_t lun,
2309 uint32_t tag)
2310 {
2311 struct scsi_qla_host *vha = fcport->vha;
2312 struct tmf_arg a;
2313 int rval = QLA_SUCCESS;
2314
2315 if (TMF_NOT_READY(fcport))
2316 return QLA_SUSPENDED;
2317
2318 a.vha = fcport->vha;
2319 a.fcport = fcport;
2320 a.lun = lun;
2321 a.flags = flags;
2322 INIT_LIST_HEAD(&a.tmf_elem);
2323
2324 if (flags & (TCF_LUN_RESET|TCF_ABORT_TASK_SET|TCF_CLEAR_TASK_SET|TCF_CLEAR_ACA)) {
2325 a.modifier = MK_SYNC_ID_LUN;
2326 } else {
2327 a.modifier = MK_SYNC_ID;
2328 }
2329
2330 if (qla_get_tmf(&a))
2331 return QLA_FUNCTION_FAILED;
2332
2333 a.qpair = vha->hw->base_qpair;
2334 rval = __qla2x00_async_tm_cmd(&a);
2335
2336 qla_put_tmf(&a);
2337 return rval;
2338 }
2339
2340 int
qla24xx_async_abort_command(srb_t * sp)2341 qla24xx_async_abort_command(srb_t *sp)
2342 {
2343 unsigned long flags = 0;
2344
2345 uint32_t handle;
2346 fc_port_t *fcport = sp->fcport;
2347 struct qla_qpair *qpair = sp->qpair;
2348 struct scsi_qla_host *vha = fcport->vha;
2349 struct req_que *req = qpair->req;
2350
2351 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
2352 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
2353 if (req->outstanding_cmds[handle] == sp)
2354 break;
2355 }
2356 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
2357
2358 if (handle == req->num_outstanding_cmds) {
2359 /* Command not found. */
2360 return QLA_ERR_NOT_FOUND;
2361 }
2362 if (sp->type == SRB_FXIOCB_DCMD)
2363 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
2364 FXDISC_ABORT_IOCTL);
2365
2366 return qla24xx_async_abort_cmd(sp, true);
2367 }
2368
2369 static void
qla24xx_handle_prli_done_event(struct scsi_qla_host * vha,struct event_arg * ea)2370 qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
2371 {
2372 struct srb *sp;
2373 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n",
2374 ea->data[0]);
2375
2376 switch (ea->data[0]) {
2377 case MBS_COMMAND_COMPLETE:
2378 ql_dbg(ql_dbg_disc, vha, 0x2118,
2379 "%s %d %8phC post gpdb\n",
2380 __func__, __LINE__, ea->fcport->port_name);
2381
2382 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
2383 ea->fcport->logout_on_delete = 1;
2384 ea->fcport->nvme_prli_service_param = ea->iop[0];
2385 if (ea->iop[0] & NVME_PRLI_SP_FIRST_BURST)
2386 ea->fcport->nvme_first_burst_size =
2387 (ea->iop[1] & 0xffff) * 512;
2388 else
2389 ea->fcport->nvme_first_burst_size = 0;
2390 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
2391 break;
2392 default:
2393 sp = ea->sp;
2394 ql_dbg(ql_dbg_disc, vha, 0x2118,
2395 "%s %d %8phC priority %s, fc4type %x prev try %s\n",
2396 __func__, __LINE__, ea->fcport->port_name,
2397 vha->hw->fc4_type_priority == FC4_PRIORITY_FCP ?
2398 "FCP" : "NVMe", ea->fcport->fc4_type,
2399 (sp->u.iocb_cmd.u.logio.flags & SRB_LOGIN_NVME_PRLI) ?
2400 "NVME" : "FCP");
2401
2402 if (NVME_FCP_TARGET(ea->fcport)) {
2403 if (sp->u.iocb_cmd.u.logio.flags & SRB_LOGIN_NVME_PRLI)
2404 ea->fcport->do_prli_nvme = 0;
2405 else
2406 ea->fcport->do_prli_nvme = 1;
2407 } else {
2408 ea->fcport->do_prli_nvme = 0;
2409 }
2410
2411 if (N2N_TOPO(vha->hw)) {
2412 if (ea->fcport->n2n_link_reset_cnt ==
2413 vha->hw->login_retry_count &&
2414 ea->fcport->flags & FCF_FCSP_DEVICE) {
2415 /* remote authentication app just started */
2416 ea->fcport->n2n_link_reset_cnt = 0;
2417 }
2418
2419 if (ea->fcport->n2n_link_reset_cnt <
2420 vha->hw->login_retry_count) {
2421 ea->fcport->n2n_link_reset_cnt++;
2422 vha->relogin_jif = jiffies + 2 * HZ;
2423 /*
2424 * PRLI failed. Reset link to kick start
2425 * state machine
2426 */
2427 set_bit(N2N_LINK_RESET, &vha->dpc_flags);
2428 qla2xxx_wake_dpc(vha);
2429 } else {
2430 ql_log(ql_log_warn, vha, 0x2119,
2431 "%s %d %8phC Unable to reconnect\n",
2432 __func__, __LINE__,
2433 ea->fcport->port_name);
2434 }
2435 } else {
2436 /*
2437 * switch connect. login failed. Take connection down
2438 * and allow relogin to retrigger
2439 */
2440 ea->fcport->flags &= ~FCF_ASYNC_SENT;
2441 ea->fcport->keep_nport_handle = 0;
2442 ea->fcport->logout_on_delete = 1;
2443 qlt_schedule_sess_for_deletion(ea->fcport);
2444 }
2445 break;
2446 }
2447 }
2448
2449 void
qla24xx_handle_plogi_done_event(struct scsi_qla_host * vha,struct event_arg * ea)2450 qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
2451 {
2452 port_id_t cid; /* conflict Nport id */
2453 u16 lid;
2454 struct fc_port *conflict_fcport;
2455 unsigned long flags;
2456 struct fc_port *fcport = ea->fcport;
2457
2458 ql_dbg(ql_dbg_disc, vha, 0xffff,
2459 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n",
2460 __func__, fcport->port_name, fcport->disc_state,
2461 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen,
2462 ea->sp->gen1, fcport->rscn_gen,
2463 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]);
2464
2465 if (fcport->fw_login_state == DSC_LS_PLOGI_PEND) {
2466 ql_dbg(ql_dbg_disc, vha, 0x20ea,
2467 "%s %d %8phC Remote is trying to login\n",
2468 __func__, __LINE__, fcport->port_name);
2469 /*
2470 * If we get here, there is port thats already logged in,
2471 * but it's state has not moved ahead. Recheck with FW on
2472 * what state it is in and proceed ahead
2473 */
2474 if (!N2N_TOPO(vha->hw)) {
2475 fcport->fw_login_state = DSC_LS_PRLI_COMP;
2476 qla24xx_post_gpdb_work(vha, fcport, 0);
2477 }
2478 return;
2479 }
2480
2481 if (fcport->fw_login_state == DSC_LS_PRLI_PEND) {
2482 ql_dbg(ql_dbg_disc, vha, 0x20ea,
2483 "%s %d %8phC Remote is trying to login\n",
2484 __func__, __LINE__, fcport->port_name);
2485 return;
2486 }
2487
2488 if ((fcport->disc_state == DSC_DELETE_PEND) ||
2489 (fcport->disc_state == DSC_DELETED)) {
2490 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2491 return;
2492 }
2493
2494 if (ea->sp->gen2 != fcport->login_gen) {
2495 /* target side must have changed it. */
2496 ql_dbg(ql_dbg_disc, vha, 0x20d3,
2497 "%s %8phC generation changed\n",
2498 __func__, fcport->port_name);
2499 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2500 return;
2501 } else if (ea->sp->gen1 != fcport->rscn_gen) {
2502 ql_dbg(ql_dbg_disc, vha, 0x20d3,
2503 "%s %8phC RSCN generation changed\n",
2504 __func__, fcport->port_name);
2505 qla_rscn_replay(fcport);
2506 qlt_schedule_sess_for_deletion(fcport);
2507 return;
2508 }
2509
2510 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n",
2511 ea->data[0]);
2512
2513 switch (ea->data[0]) {
2514 case MBS_COMMAND_COMPLETE:
2515 /*
2516 * Driver must validate login state - If PRLI not complete,
2517 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
2518 * requests.
2519 */
2520 if (vha->hw->flags.edif_enabled) {
2521 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
2522 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
2523 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
2524 ea->fcport->logout_on_delete = 1;
2525 ea->fcport->send_els_logo = 0;
2526 ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP;
2527 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
2528
2529 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
2530 } else {
2531 if (NVME_TARGET(vha->hw, fcport)) {
2532 ql_dbg(ql_dbg_disc, vha, 0x2117,
2533 "%s %d %8phC post prli\n",
2534 __func__, __LINE__, fcport->port_name);
2535 qla24xx_post_prli_work(vha, fcport);
2536 } else {
2537 ql_dbg(ql_dbg_disc, vha, 0x20ea,
2538 "%s %d %8phC LoopID 0x%x in use with %06x. post gpdb\n",
2539 __func__, __LINE__, fcport->port_name,
2540 fcport->loop_id, fcport->d_id.b24);
2541
2542 set_bit(fcport->loop_id, vha->hw->loop_id_map);
2543 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
2544 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
2545 fcport->logout_on_delete = 1;
2546 fcport->send_els_logo = 0;
2547 fcport->fw_login_state = DSC_LS_PRLI_COMP;
2548 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
2549
2550 qla24xx_post_gpdb_work(vha, fcport, 0);
2551 }
2552 }
2553 break;
2554 case MBS_COMMAND_ERROR:
2555 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
2556 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
2557
2558 qlt_schedule_sess_for_deletion(ea->fcport);
2559 break;
2560 case MBS_LOOP_ID_USED:
2561 /* data[1] = IO PARAM 1 = nport ID */
2562 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
2563 cid.b.area = (ea->iop[1] >> 8) & 0xff;
2564 cid.b.al_pa = ea->iop[1] & 0xff;
2565 cid.b.rsvd_1 = 0;
2566
2567 ql_dbg(ql_dbg_disc, vha, 0x20ec,
2568 "%s %d %8phC lid %#x in use with pid %06x post gnl\n",
2569 __func__, __LINE__, ea->fcport->port_name,
2570 ea->fcport->loop_id, cid.b24);
2571
2572 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
2573 ea->fcport->loop_id = FC_NO_LOOP_ID;
2574 qla24xx_post_gnl_work(vha, ea->fcport);
2575 break;
2576 case MBS_PORT_ID_USED:
2577 lid = ea->iop[1] & 0xffff;
2578 qlt_find_sess_invalidate_other(vha,
2579 wwn_to_u64(ea->fcport->port_name),
2580 ea->fcport->d_id, lid, &conflict_fcport);
2581
2582 if (conflict_fcport) {
2583 /*
2584 * Another fcport share the same loop_id/nport id.
2585 * Conflict fcport needs to finish cleanup before this
2586 * fcport can proceed to login.
2587 */
2588 conflict_fcport->conflict = ea->fcport;
2589 ea->fcport->login_pause = 1;
2590
2591 ql_dbg(ql_dbg_disc, vha, 0x20ed,
2592 "%s %d %8phC NPortId %06x inuse with loopid 0x%x.\n",
2593 __func__, __LINE__, ea->fcport->port_name,
2594 ea->fcport->d_id.b24, lid);
2595 } else {
2596 ql_dbg(ql_dbg_disc, vha, 0x20ed,
2597 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n",
2598 __func__, __LINE__, ea->fcport->port_name,
2599 ea->fcport->d_id.b24, lid);
2600
2601 qla2x00_clear_loop_id(ea->fcport);
2602 set_bit(lid, vha->hw->loop_id_map);
2603 ea->fcport->loop_id = lid;
2604 ea->fcport->keep_nport_handle = 0;
2605 ea->fcport->logout_on_delete = 1;
2606 qlt_schedule_sess_for_deletion(ea->fcport);
2607 }
2608 break;
2609 }
2610 return;
2611 }
2612
2613 /****************************************************************************/
2614 /* QLogic ISP2x00 Hardware Support Functions. */
2615 /****************************************************************************/
2616
2617 static int
qla83xx_nic_core_fw_load(scsi_qla_host_t * vha)2618 qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
2619 {
2620 int rval = QLA_SUCCESS;
2621 struct qla_hw_data *ha = vha->hw;
2622 uint32_t idc_major_ver, idc_minor_ver;
2623 uint16_t config[4];
2624
2625 qla83xx_idc_lock(vha, 0);
2626
2627 /* SV: TODO: Assign initialization timeout from
2628 * flash-info / other param
2629 */
2630 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
2631 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
2632
2633 /* Set our fcoe function presence */
2634 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
2635 ql_dbg(ql_dbg_p3p, vha, 0xb077,
2636 "Error while setting DRV-Presence.\n");
2637 rval = QLA_FUNCTION_FAILED;
2638 goto exit;
2639 }
2640
2641 /* Decide the reset ownership */
2642 qla83xx_reset_ownership(vha);
2643
2644 /*
2645 * On first protocol driver load:
2646 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
2647 * register.
2648 * Others: Check compatibility with current IDC Major version.
2649 */
2650 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
2651 if (ha->flags.nic_core_reset_owner) {
2652 /* Set IDC Major version */
2653 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
2654 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
2655
2656 /* Clearing IDC-Lock-Recovery register */
2657 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
2658 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
2659 /*
2660 * Clear further IDC participation if we are not compatible with
2661 * the current IDC Major Version.
2662 */
2663 ql_log(ql_log_warn, vha, 0xb07d,
2664 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
2665 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
2666 __qla83xx_clear_drv_presence(vha);
2667 rval = QLA_FUNCTION_FAILED;
2668 goto exit;
2669 }
2670 /* Each function sets its supported Minor version. */
2671 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
2672 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
2673 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
2674
2675 if (ha->flags.nic_core_reset_owner) {
2676 memset(config, 0, sizeof(config));
2677 if (!qla81xx_get_port_config(vha, config))
2678 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
2679 QLA8XXX_DEV_READY);
2680 }
2681
2682 rval = qla83xx_idc_state_handler(vha);
2683
2684 exit:
2685 qla83xx_idc_unlock(vha, 0);
2686
2687 return rval;
2688 }
2689
qla_enable_fce_trace(scsi_qla_host_t * vha)2690 void qla_enable_fce_trace(scsi_qla_host_t *vha)
2691 {
2692 int rval;
2693 struct qla_hw_data *ha = vha->hw;
2694
2695 if (ha->fce) {
2696 ha->flags.fce_enabled = 1;
2697 memset(ha->fce, 0, fce_calc_size(ha->fce_bufs));
2698 rval = qla2x00_enable_fce_trace(vha,
2699 ha->fce_dma, ha->fce_bufs, ha->fce_mb, &ha->fce_bufs);
2700
2701 if (rval) {
2702 ql_log(ql_log_warn, vha, 0x8033,
2703 "Unable to reinitialize FCE (%d).\n", rval);
2704 ha->flags.fce_enabled = 0;
2705 }
2706 }
2707 }
2708
qla_enable_eft_trace(scsi_qla_host_t * vha)2709 static void qla_enable_eft_trace(scsi_qla_host_t *vha)
2710 {
2711 int rval;
2712 struct qla_hw_data *ha = vha->hw;
2713
2714 if (ha->eft) {
2715 memset(ha->eft, 0, EFT_SIZE);
2716 rval = qla2x00_enable_eft_trace(vha, ha->eft_dma, EFT_NUM_BUFFERS);
2717
2718 if (rval) {
2719 ql_log(ql_log_warn, vha, 0x8034,
2720 "Unable to reinitialize EFT (%d).\n", rval);
2721 }
2722 }
2723 }
2724 /*
2725 * qla2x00_initialize_adapter
2726 * Initialize board.
2727 *
2728 * Input:
2729 * ha = adapter block pointer.
2730 *
2731 * Returns:
2732 * 0 = success
2733 */
2734 int
qla2x00_initialize_adapter(scsi_qla_host_t * vha)2735 qla2x00_initialize_adapter(scsi_qla_host_t *vha)
2736 {
2737 int rval;
2738 struct qla_hw_data *ha = vha->hw;
2739 struct req_que *req = ha->req_q_map[0];
2740 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2741
2742 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
2743 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
2744
2745 /* Clear adapter flags. */
2746 vha->flags.online = 0;
2747 ha->flags.chip_reset_done = 0;
2748 vha->flags.reset_active = 0;
2749 ha->flags.pci_channel_io_perm_failure = 0;
2750 ha->flags.eeh_busy = 0;
2751 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
2752 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2753 atomic_set(&vha->loop_state, LOOP_DOWN);
2754 vha->device_flags = DFLG_NO_CABLE;
2755 vha->dpc_flags = 0;
2756 vha->flags.management_server_logged_in = 0;
2757 vha->marker_needed = 0;
2758 ha->isp_abort_cnt = 0;
2759 ha->beacon_blink_led = 0;
2760
2761 set_bit(0, ha->req_qid_map);
2762 set_bit(0, ha->rsp_qid_map);
2763
2764 ql_dbg(ql_dbg_init, vha, 0x0040,
2765 "Configuring PCI space...\n");
2766 rval = ha->isp_ops->pci_config(vha);
2767 if (rval) {
2768 ql_log(ql_log_warn, vha, 0x0044,
2769 "Unable to configure PCI space.\n");
2770 return (rval);
2771 }
2772
2773 ha->isp_ops->reset_chip(vha);
2774
2775 /* Check for secure flash support */
2776 if (IS_QLA28XX(ha)) {
2777 if (rd_reg_word(®->mailbox12) & BIT_0)
2778 ha->flags.secure_adapter = 1;
2779 ql_log(ql_log_info, vha, 0xffff, "Secure Adapter: %s\n",
2780 (ha->flags.secure_adapter) ? "Yes" : "No");
2781 }
2782
2783
2784 rval = qla2xxx_get_flash_info(vha);
2785 if (rval) {
2786 ql_log(ql_log_fatal, vha, 0x004f,
2787 "Unable to validate FLASH data.\n");
2788 return rval;
2789 }
2790
2791 if (IS_QLA8044(ha)) {
2792 qla8044_read_reset_template(vha);
2793
2794 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
2795 * If DONRESET_BIT0 is set, drivers should not set dev_state
2796 * to NEED_RESET. But if NEED_RESET is set, drivers should
2797 * should honor the reset. */
2798 if (ql2xdontresethba == 1)
2799 qla8044_set_idc_dontreset(vha);
2800 }
2801
2802 ha->isp_ops->get_flash_version(vha, req->ring);
2803 ql_dbg(ql_dbg_init, vha, 0x0061,
2804 "Configure NVRAM parameters...\n");
2805
2806 /* Let priority default to FCP, can be overridden by nvram_config */
2807 ha->fc4_type_priority = FC4_PRIORITY_FCP;
2808
2809 ha->isp_ops->nvram_config(vha);
2810
2811 if (ha->fc4_type_priority != FC4_PRIORITY_FCP &&
2812 ha->fc4_type_priority != FC4_PRIORITY_NVME)
2813 ha->fc4_type_priority = FC4_PRIORITY_FCP;
2814
2815 ql_log(ql_log_info, vha, 0xffff, "FC4 priority set to %s\n",
2816 ha->fc4_type_priority == FC4_PRIORITY_FCP ? "FCP" : "NVMe");
2817
2818 if (ha->flags.disable_serdes) {
2819 /* Mask HBA via NVRAM settings? */
2820 ql_log(ql_log_info, vha, 0x0077,
2821 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
2822 return QLA_FUNCTION_FAILED;
2823 }
2824
2825 ql_dbg(ql_dbg_init, vha, 0x0078,
2826 "Verifying loaded RISC code...\n");
2827
2828 /* If smartsan enabled then require fdmi and rdp enabled */
2829 if (ql2xsmartsan) {
2830 ql2xfdmienable = 1;
2831 ql2xrdpenable = 1;
2832 }
2833
2834 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
2835 rval = ha->isp_ops->chip_diag(vha);
2836 if (rval)
2837 return (rval);
2838 rval = qla2x00_setup_chip(vha);
2839 if (rval)
2840 return (rval);
2841 }
2842
2843 if (IS_QLA84XX(ha)) {
2844 ha->cs84xx = qla84xx_get_chip(vha);
2845 if (!ha->cs84xx) {
2846 ql_log(ql_log_warn, vha, 0x00d0,
2847 "Unable to configure ISP84XX.\n");
2848 return QLA_FUNCTION_FAILED;
2849 }
2850 }
2851
2852 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2853 rval = qla2x00_init_rings(vha);
2854
2855 /* No point in continuing if firmware initialization failed. */
2856 if (rval != QLA_SUCCESS)
2857 return rval;
2858
2859 ha->flags.chip_reset_done = 1;
2860
2861 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
2862 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
2863 rval = qla84xx_init_chip(vha);
2864 if (rval != QLA_SUCCESS) {
2865 ql_log(ql_log_warn, vha, 0x00d4,
2866 "Unable to initialize ISP84XX.\n");
2867 qla84xx_put_chip(vha);
2868 }
2869 }
2870
2871 /* Load the NIC Core f/w if we are the first protocol driver. */
2872 if (IS_QLA8031(ha)) {
2873 rval = qla83xx_nic_core_fw_load(vha);
2874 if (rval)
2875 ql_log(ql_log_warn, vha, 0x0124,
2876 "Error in initializing NIC Core f/w.\n");
2877 }
2878
2879 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
2880 qla24xx_read_fcp_prio_cfg(vha);
2881
2882 if (IS_P3P_TYPE(ha))
2883 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
2884 else
2885 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
2886
2887 return (rval);
2888 }
2889
2890 /**
2891 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
2892 * @vha: HA context
2893 *
2894 * Returns 0 on success.
2895 */
2896 int
qla2100_pci_config(scsi_qla_host_t * vha)2897 qla2100_pci_config(scsi_qla_host_t *vha)
2898 {
2899 uint16_t w;
2900 unsigned long flags;
2901 struct qla_hw_data *ha = vha->hw;
2902 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2903
2904 pci_set_master(ha->pdev);
2905 pci_try_set_mwi(ha->pdev);
2906
2907 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2908 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2909 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2910
2911 pci_disable_rom(ha->pdev);
2912
2913 /* Get PCI bus information. */
2914 spin_lock_irqsave(&ha->hardware_lock, flags);
2915 ha->pci_attr = rd_reg_word(®->ctrl_status);
2916 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2917
2918 return QLA_SUCCESS;
2919 }
2920
2921 /**
2922 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
2923 * @vha: HA context
2924 *
2925 * Returns 0 on success.
2926 */
2927 int
qla2300_pci_config(scsi_qla_host_t * vha)2928 qla2300_pci_config(scsi_qla_host_t *vha)
2929 {
2930 uint16_t w;
2931 unsigned long flags = 0;
2932 uint32_t cnt;
2933 struct qla_hw_data *ha = vha->hw;
2934 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2935
2936 pci_set_master(ha->pdev);
2937 pci_try_set_mwi(ha->pdev);
2938
2939 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2940 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2941
2942 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2943 w &= ~PCI_COMMAND_INTX_DISABLE;
2944 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2945
2946 /*
2947 * If this is a 2300 card and not 2312, reset the
2948 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
2949 * the 2310 also reports itself as a 2300 so we need to get the
2950 * fb revision level -- a 6 indicates it really is a 2300 and
2951 * not a 2310.
2952 */
2953 if (IS_QLA2300(ha)) {
2954 spin_lock_irqsave(&ha->hardware_lock, flags);
2955
2956 /* Pause RISC. */
2957 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC);
2958 for (cnt = 0; cnt < 30000; cnt++) {
2959 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0)
2960 break;
2961
2962 udelay(10);
2963 }
2964
2965 /* Select FPM registers. */
2966 wrt_reg_word(®->ctrl_status, 0x20);
2967 rd_reg_word(®->ctrl_status);
2968
2969 /* Get the fb rev level */
2970 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
2971
2972 if (ha->fb_rev == FPM_2300)
2973 pci_clear_mwi(ha->pdev);
2974
2975 /* Deselect FPM registers. */
2976 wrt_reg_word(®->ctrl_status, 0x0);
2977 rd_reg_word(®->ctrl_status);
2978
2979 /* Release RISC module. */
2980 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
2981 for (cnt = 0; cnt < 30000; cnt++) {
2982 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0)
2983 break;
2984
2985 udelay(10);
2986 }
2987
2988 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2989 }
2990
2991 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2992
2993 pci_disable_rom(ha->pdev);
2994
2995 /* Get PCI bus information. */
2996 spin_lock_irqsave(&ha->hardware_lock, flags);
2997 ha->pci_attr = rd_reg_word(®->ctrl_status);
2998 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2999
3000 return QLA_SUCCESS;
3001 }
3002
3003 /**
3004 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
3005 * @vha: HA context
3006 *
3007 * Returns 0 on success.
3008 */
3009 int
qla24xx_pci_config(scsi_qla_host_t * vha)3010 qla24xx_pci_config(scsi_qla_host_t *vha)
3011 {
3012 uint16_t w;
3013 unsigned long flags = 0;
3014 struct qla_hw_data *ha = vha->hw;
3015 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
3016
3017 pci_set_master(ha->pdev);
3018 pci_try_set_mwi(ha->pdev);
3019
3020 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
3021 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
3022 w &= ~PCI_COMMAND_INTX_DISABLE;
3023 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
3024
3025 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
3026
3027 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
3028 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
3029 pcix_set_mmrbc(ha->pdev, 2048);
3030
3031 /* PCIe -- adjust Maximum Read Request Size (2048). */
3032 if (pci_is_pcie(ha->pdev))
3033 pcie_set_readrq(ha->pdev, 4096);
3034
3035 pci_disable_rom(ha->pdev);
3036
3037 ha->chip_revision = ha->pdev->revision;
3038
3039 /* Get PCI bus information. */
3040 spin_lock_irqsave(&ha->hardware_lock, flags);
3041 ha->pci_attr = rd_reg_dword(®->ctrl_status);
3042 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3043
3044 return QLA_SUCCESS;
3045 }
3046
3047 /**
3048 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
3049 * @vha: HA context
3050 *
3051 * Returns 0 on success.
3052 */
3053 int
qla25xx_pci_config(scsi_qla_host_t * vha)3054 qla25xx_pci_config(scsi_qla_host_t *vha)
3055 {
3056 uint16_t w;
3057 struct qla_hw_data *ha = vha->hw;
3058
3059 pci_set_master(ha->pdev);
3060 pci_try_set_mwi(ha->pdev);
3061
3062 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
3063 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
3064 w &= ~PCI_COMMAND_INTX_DISABLE;
3065 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
3066
3067 /* PCIe -- adjust Maximum Read Request Size (2048). */
3068 if (pci_is_pcie(ha->pdev))
3069 pcie_set_readrq(ha->pdev, 4096);
3070
3071 pci_disable_rom(ha->pdev);
3072
3073 ha->chip_revision = ha->pdev->revision;
3074
3075 return QLA_SUCCESS;
3076 }
3077
3078 /**
3079 * qla2x00_isp_firmware() - Choose firmware image.
3080 * @vha: HA context
3081 *
3082 * Returns 0 on success.
3083 */
3084 static int
qla2x00_isp_firmware(scsi_qla_host_t * vha)3085 qla2x00_isp_firmware(scsi_qla_host_t *vha)
3086 {
3087 int rval;
3088 uint16_t loop_id, topo, sw_cap;
3089 uint8_t domain, area, al_pa;
3090 struct qla_hw_data *ha = vha->hw;
3091
3092 /* Assume loading risc code */
3093 rval = QLA_FUNCTION_FAILED;
3094
3095 if (ha->flags.disable_risc_code_load) {
3096 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
3097
3098 /* Verify checksum of loaded RISC code. */
3099 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
3100 if (rval == QLA_SUCCESS) {
3101 /* And, verify we are not in ROM code. */
3102 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
3103 &area, &domain, &topo, &sw_cap);
3104 }
3105 }
3106
3107 if (rval)
3108 ql_dbg(ql_dbg_init, vha, 0x007a,
3109 "**** Load RISC code ****.\n");
3110
3111 return (rval);
3112 }
3113
3114 /**
3115 * qla2x00_reset_chip() - Reset ISP chip.
3116 * @vha: HA context
3117 *
3118 * Returns 0 on success.
3119 */
3120 int
qla2x00_reset_chip(scsi_qla_host_t * vha)3121 qla2x00_reset_chip(scsi_qla_host_t *vha)
3122 {
3123 unsigned long flags = 0;
3124 struct qla_hw_data *ha = vha->hw;
3125 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3126 uint32_t cnt;
3127 uint16_t cmd;
3128 int rval = QLA_FUNCTION_FAILED;
3129
3130 if (unlikely(pci_channel_offline(ha->pdev)))
3131 return rval;
3132
3133 ha->isp_ops->disable_intrs(ha);
3134
3135 spin_lock_irqsave(&ha->hardware_lock, flags);
3136
3137 /* Turn off master enable */
3138 cmd = 0;
3139 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
3140 cmd &= ~PCI_COMMAND_MASTER;
3141 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
3142
3143 if (!IS_QLA2100(ha)) {
3144 /* Pause RISC. */
3145 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC);
3146 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
3147 for (cnt = 0; cnt < 30000; cnt++) {
3148 if ((rd_reg_word(®->hccr) &
3149 HCCR_RISC_PAUSE) != 0)
3150 break;
3151 udelay(100);
3152 }
3153 } else {
3154 rd_reg_word(®->hccr); /* PCI Posting. */
3155 udelay(10);
3156 }
3157
3158 /* Select FPM registers. */
3159 wrt_reg_word(®->ctrl_status, 0x20);
3160 rd_reg_word(®->ctrl_status); /* PCI Posting. */
3161
3162 /* FPM Soft Reset. */
3163 wrt_reg_word(®->fpm_diag_config, 0x100);
3164 rd_reg_word(®->fpm_diag_config); /* PCI Posting. */
3165
3166 /* Toggle Fpm Reset. */
3167 if (!IS_QLA2200(ha)) {
3168 wrt_reg_word(®->fpm_diag_config, 0x0);
3169 rd_reg_word(®->fpm_diag_config); /* PCI Posting. */
3170 }
3171
3172 /* Select frame buffer registers. */
3173 wrt_reg_word(®->ctrl_status, 0x10);
3174 rd_reg_word(®->ctrl_status); /* PCI Posting. */
3175
3176 /* Reset frame buffer FIFOs. */
3177 if (IS_QLA2200(ha)) {
3178 WRT_FB_CMD_REG(ha, reg, 0xa000);
3179 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
3180 } else {
3181 WRT_FB_CMD_REG(ha, reg, 0x00fc);
3182
3183 /* Read back fb_cmd until zero or 3 seconds max */
3184 for (cnt = 0; cnt < 3000; cnt++) {
3185 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
3186 break;
3187 udelay(100);
3188 }
3189 }
3190
3191 /* Select RISC module registers. */
3192 wrt_reg_word(®->ctrl_status, 0);
3193 rd_reg_word(®->ctrl_status); /* PCI Posting. */
3194
3195 /* Reset RISC processor. */
3196 wrt_reg_word(®->hccr, HCCR_RESET_RISC);
3197 rd_reg_word(®->hccr); /* PCI Posting. */
3198
3199 /* Release RISC processor. */
3200 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
3201 rd_reg_word(®->hccr); /* PCI Posting. */
3202 }
3203
3204 wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT);
3205 wrt_reg_word(®->hccr, HCCR_CLR_HOST_INT);
3206
3207 /* Reset ISP chip. */
3208 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
3209
3210 /* Wait for RISC to recover from reset. */
3211 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
3212 /*
3213 * It is necessary to for a delay here since the card doesn't
3214 * respond to PCI reads during a reset. On some architectures
3215 * this will result in an MCA.
3216 */
3217 udelay(20);
3218 for (cnt = 30000; cnt; cnt--) {
3219 if ((rd_reg_word(®->ctrl_status) &
3220 CSR_ISP_SOFT_RESET) == 0)
3221 break;
3222 udelay(100);
3223 }
3224 } else
3225 udelay(10);
3226
3227 /* Reset RISC processor. */
3228 wrt_reg_word(®->hccr, HCCR_RESET_RISC);
3229
3230 wrt_reg_word(®->semaphore, 0);
3231
3232 /* Release RISC processor. */
3233 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
3234 rd_reg_word(®->hccr); /* PCI Posting. */
3235
3236 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
3237 for (cnt = 0; cnt < 30000; cnt++) {
3238 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
3239 break;
3240
3241 udelay(100);
3242 }
3243 } else
3244 udelay(100);
3245
3246 /* Turn on master enable */
3247 cmd |= PCI_COMMAND_MASTER;
3248 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
3249
3250 /* Disable RISC pause on FPM parity error. */
3251 if (!IS_QLA2100(ha)) {
3252 wrt_reg_word(®->hccr, HCCR_DISABLE_PARITY_PAUSE);
3253 rd_reg_word(®->hccr); /* PCI Posting. */
3254 }
3255
3256 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3257
3258 return QLA_SUCCESS;
3259 }
3260
3261 /**
3262 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
3263 * @vha: HA context
3264 *
3265 * Returns 0 on success.
3266 */
3267 static int
qla81xx_reset_mpi(scsi_qla_host_t * vha)3268 qla81xx_reset_mpi(scsi_qla_host_t *vha)
3269 {
3270 uint16_t mb[4] = {0x1010, 0, 1, 0};
3271
3272 if (!IS_QLA81XX(vha->hw))
3273 return QLA_SUCCESS;
3274
3275 return qla81xx_write_mpi_register(vha, mb);
3276 }
3277
3278 static int
qla_chk_risc_recovery(scsi_qla_host_t * vha)3279 qla_chk_risc_recovery(scsi_qla_host_t *vha)
3280 {
3281 struct qla_hw_data *ha = vha->hw;
3282 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
3283 __le16 __iomem *mbptr = ®->mailbox0;
3284 int i;
3285 u16 mb[32];
3286 int rc = QLA_SUCCESS;
3287
3288 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
3289 return rc;
3290
3291 /* this check is only valid after RISC reset */
3292 mb[0] = rd_reg_word(mbptr);
3293 mbptr++;
3294 if (mb[0] == 0xf) {
3295 rc = QLA_FUNCTION_FAILED;
3296
3297 for (i = 1; i < 32; i++) {
3298 mb[i] = rd_reg_word(mbptr);
3299 mbptr++;
3300 }
3301
3302 ql_log(ql_log_warn, vha, 0x1015,
3303 "RISC reset failed. mb[0-7] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n",
3304 mb[0], mb[1], mb[2], mb[3], mb[4], mb[5], mb[6], mb[7]);
3305 ql_log(ql_log_warn, vha, 0x1015,
3306 "RISC reset failed. mb[8-15] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n",
3307 mb[8], mb[9], mb[10], mb[11], mb[12], mb[13], mb[14],
3308 mb[15]);
3309 ql_log(ql_log_warn, vha, 0x1015,
3310 "RISC reset failed. mb[16-23] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n",
3311 mb[16], mb[17], mb[18], mb[19], mb[20], mb[21], mb[22],
3312 mb[23]);
3313 ql_log(ql_log_warn, vha, 0x1015,
3314 "RISC reset failed. mb[24-31] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n",
3315 mb[24], mb[25], mb[26], mb[27], mb[28], mb[29], mb[30],
3316 mb[31]);
3317 }
3318 return rc;
3319 }
3320
3321 /**
3322 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
3323 * @vha: HA context
3324 *
3325 * Returns 0 on success.
3326 */
3327 static inline int
qla24xx_reset_risc(scsi_qla_host_t * vha)3328 qla24xx_reset_risc(scsi_qla_host_t *vha)
3329 {
3330 unsigned long flags = 0;
3331 struct qla_hw_data *ha = vha->hw;
3332 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
3333 uint32_t cnt;
3334 uint16_t wd;
3335 static int abts_cnt; /* ISP abort retry counts */
3336 int rval = QLA_SUCCESS;
3337 int print = 1;
3338
3339 spin_lock_irqsave(&ha->hardware_lock, flags);
3340
3341 /* Reset RISC. */
3342 wrt_reg_dword(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
3343 for (cnt = 0; cnt < 30000; cnt++) {
3344 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
3345 break;
3346
3347 udelay(10);
3348 }
3349
3350 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE))
3351 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
3352
3353 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
3354 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
3355 rd_reg_dword(®->hccr),
3356 rd_reg_dword(®->ctrl_status),
3357 (rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE));
3358
3359 wrt_reg_dword(®->ctrl_status,
3360 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
3361 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
3362
3363 udelay(100);
3364
3365 /* Wait for firmware to complete NVRAM accesses. */
3366 rd_reg_word(®->mailbox0);
3367 for (cnt = 10000; rd_reg_word(®->mailbox0) != 0 &&
3368 rval == QLA_SUCCESS; cnt--) {
3369 barrier();
3370 if (cnt)
3371 udelay(5);
3372 else
3373 rval = QLA_FUNCTION_TIMEOUT;
3374 }
3375
3376 if (rval == QLA_SUCCESS)
3377 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
3378
3379 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
3380 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
3381 rd_reg_dword(®->hccr),
3382 rd_reg_word(®->mailbox0));
3383
3384 /* Wait for soft-reset to complete. */
3385 rd_reg_dword(®->ctrl_status);
3386 for (cnt = 0; cnt < 60; cnt++) {
3387 barrier();
3388 if ((rd_reg_dword(®->ctrl_status) &
3389 CSRX_ISP_SOFT_RESET) == 0)
3390 break;
3391
3392 udelay(5);
3393 }
3394 if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET))
3395 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
3396
3397 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
3398 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
3399 rd_reg_dword(®->hccr),
3400 rd_reg_dword(®->ctrl_status));
3401
3402 /* If required, do an MPI FW reset now */
3403 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
3404 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
3405 if (++abts_cnt < 5) {
3406 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3407 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
3408 } else {
3409 /*
3410 * We exhausted the ISP abort retries. We have to
3411 * set the board offline.
3412 */
3413 abts_cnt = 0;
3414 vha->flags.online = 0;
3415 }
3416 }
3417 }
3418
3419 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET);
3420 rd_reg_dword(®->hccr);
3421
3422 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE);
3423 rd_reg_dword(®->hccr);
3424
3425 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_RESET);
3426 mdelay(10);
3427 rd_reg_dword(®->hccr);
3428
3429 wd = rd_reg_word(®->mailbox0);
3430 for (cnt = 300; wd != 0 && rval == QLA_SUCCESS; cnt--) {
3431 barrier();
3432 if (cnt) {
3433 mdelay(1);
3434 if (print && qla_chk_risc_recovery(vha))
3435 print = 0;
3436
3437 wd = rd_reg_word(®->mailbox0);
3438 } else {
3439 rval = QLA_FUNCTION_TIMEOUT;
3440
3441 ql_log(ql_log_warn, vha, 0x015e,
3442 "RISC reset timeout\n");
3443 }
3444 }
3445
3446 if (rval == QLA_SUCCESS)
3447 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
3448
3449 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
3450 "Host Risc 0x%x, mailbox0 0x%x\n",
3451 rd_reg_dword(®->hccr),
3452 rd_reg_word(®->mailbox0));
3453
3454 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3455
3456 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
3457 "Driver in %s mode\n",
3458 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
3459
3460 if (IS_NOPOLLING_TYPE(ha))
3461 ha->isp_ops->enable_intrs(ha);
3462
3463 return rval;
3464 }
3465
3466 static void
qla25xx_read_risc_sema_reg(scsi_qla_host_t * vha,uint32_t * data)3467 qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
3468 {
3469 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
3470
3471 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET);
3472 *data = rd_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET);
3473 }
3474
3475 static void
qla25xx_write_risc_sema_reg(scsi_qla_host_t * vha,uint32_t data)3476 qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
3477 {
3478 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
3479
3480 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET);
3481 wrt_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET, data);
3482 }
3483
3484 static void
qla25xx_manipulate_risc_semaphore(scsi_qla_host_t * vha)3485 qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
3486 {
3487 uint32_t wd32 = 0;
3488 uint delta_msec = 100;
3489 uint elapsed_msec = 0;
3490 uint timeout_msec;
3491 ulong n;
3492
3493 if (vha->hw->pdev->subsystem_device != 0x0175 &&
3494 vha->hw->pdev->subsystem_device != 0x0240)
3495 return;
3496
3497 wrt_reg_dword(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
3498 udelay(100);
3499
3500 attempt:
3501 timeout_msec = TIMEOUT_SEMAPHORE;
3502 n = timeout_msec / delta_msec;
3503 while (n--) {
3504 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
3505 qla25xx_read_risc_sema_reg(vha, &wd32);
3506 if (wd32 & RISC_SEMAPHORE)
3507 break;
3508 msleep(delta_msec);
3509 elapsed_msec += delta_msec;
3510 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
3511 goto force;
3512 }
3513
3514 if (!(wd32 & RISC_SEMAPHORE))
3515 goto force;
3516
3517 if (!(wd32 & RISC_SEMAPHORE_FORCE))
3518 goto acquired;
3519
3520 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
3521 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
3522 n = timeout_msec / delta_msec;
3523 while (n--) {
3524 qla25xx_read_risc_sema_reg(vha, &wd32);
3525 if (!(wd32 & RISC_SEMAPHORE_FORCE))
3526 break;
3527 msleep(delta_msec);
3528 elapsed_msec += delta_msec;
3529 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
3530 goto force;
3531 }
3532
3533 if (wd32 & RISC_SEMAPHORE_FORCE)
3534 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
3535
3536 goto attempt;
3537
3538 force:
3539 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
3540
3541 acquired:
3542 return;
3543 }
3544
3545 /**
3546 * qla24xx_reset_chip() - Reset ISP24xx chip.
3547 * @vha: HA context
3548 *
3549 * Returns 0 on success.
3550 */
3551 int
qla24xx_reset_chip(scsi_qla_host_t * vha)3552 qla24xx_reset_chip(scsi_qla_host_t *vha)
3553 {
3554 struct qla_hw_data *ha = vha->hw;
3555 int rval = QLA_FUNCTION_FAILED;
3556
3557 if (pci_channel_offline(ha->pdev) &&
3558 ha->flags.pci_channel_io_perm_failure) {
3559 return rval;
3560 }
3561
3562 ha->isp_ops->disable_intrs(ha);
3563
3564 qla25xx_manipulate_risc_semaphore(vha);
3565
3566 /* Perform RISC reset. */
3567 rval = qla24xx_reset_risc(vha);
3568
3569 return rval;
3570 }
3571
3572 /**
3573 * qla2x00_chip_diag() - Test chip for proper operation.
3574 * @vha: HA context
3575 *
3576 * Returns 0 on success.
3577 */
3578 int
qla2x00_chip_diag(scsi_qla_host_t * vha)3579 qla2x00_chip_diag(scsi_qla_host_t *vha)
3580 {
3581 int rval;
3582 struct qla_hw_data *ha = vha->hw;
3583 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3584 unsigned long flags = 0;
3585 uint16_t data;
3586 uint32_t cnt;
3587 uint16_t mb[5];
3588 struct req_que *req = ha->req_q_map[0];
3589
3590 /* Assume a failed state */
3591 rval = QLA_FUNCTION_FAILED;
3592
3593 ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n",
3594 ®->flash_address);
3595
3596 spin_lock_irqsave(&ha->hardware_lock, flags);
3597
3598 /* Reset ISP chip. */
3599 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
3600
3601 /*
3602 * We need to have a delay here since the card will not respond while
3603 * in reset causing an MCA on some architectures.
3604 */
3605 udelay(20);
3606 data = qla2x00_debounce_register(®->ctrl_status);
3607 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
3608 udelay(5);
3609 data = rd_reg_word(®->ctrl_status);
3610 barrier();
3611 }
3612
3613 if (!cnt)
3614 goto chip_diag_failed;
3615
3616 ql_dbg(ql_dbg_init, vha, 0x007c,
3617 "Reset register cleared by chip reset.\n");
3618
3619 /* Reset RISC processor. */
3620 wrt_reg_word(®->hccr, HCCR_RESET_RISC);
3621 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
3622
3623 /* Workaround for QLA2312 PCI parity error */
3624 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
3625 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
3626 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
3627 udelay(5);
3628 data = RD_MAILBOX_REG(ha, reg, 0);
3629 barrier();
3630 }
3631 } else
3632 udelay(10);
3633
3634 if (!cnt)
3635 goto chip_diag_failed;
3636
3637 /* Check product ID of chip */
3638 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
3639
3640 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
3641 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
3642 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
3643 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
3644 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
3645 mb[3] != PROD_ID_3) {
3646 ql_log(ql_log_warn, vha, 0x0062,
3647 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
3648 mb[1], mb[2], mb[3]);
3649
3650 goto chip_diag_failed;
3651 }
3652 ha->product_id[0] = mb[1];
3653 ha->product_id[1] = mb[2];
3654 ha->product_id[2] = mb[3];
3655 ha->product_id[3] = mb[4];
3656
3657 /* Adjust fw RISC transfer size */
3658 if (req->length > 1024)
3659 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
3660 else
3661 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
3662 req->length;
3663
3664 if (IS_QLA2200(ha) &&
3665 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
3666 /* Limit firmware transfer size with a 2200A */
3667 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
3668
3669 ha->device_type |= DT_ISP2200A;
3670 ha->fw_transfer_size = 128;
3671 }
3672
3673 /* Wrap Incoming Mailboxes Test. */
3674 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3675
3676 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
3677 rval = qla2x00_mbx_reg_test(vha);
3678 if (rval)
3679 ql_log(ql_log_warn, vha, 0x0080,
3680 "Failed mailbox send register test.\n");
3681 else
3682 /* Flag a successful rval */
3683 rval = QLA_SUCCESS;
3684 spin_lock_irqsave(&ha->hardware_lock, flags);
3685
3686 chip_diag_failed:
3687 if (rval)
3688 ql_log(ql_log_info, vha, 0x0081,
3689 "Chip diagnostics **** FAILED ****.\n");
3690
3691 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3692
3693 return (rval);
3694 }
3695
3696 /**
3697 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
3698 * @vha: HA context
3699 *
3700 * Returns 0 on success.
3701 */
3702 int
qla24xx_chip_diag(scsi_qla_host_t * vha)3703 qla24xx_chip_diag(scsi_qla_host_t *vha)
3704 {
3705 int rval;
3706 struct qla_hw_data *ha = vha->hw;
3707 struct req_que *req = ha->req_q_map[0];
3708
3709 if (IS_P3P_TYPE(ha))
3710 return QLA_SUCCESS;
3711
3712 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
3713
3714 rval = qla2x00_mbx_reg_test(vha);
3715 if (rval) {
3716 ql_log(ql_log_warn, vha, 0x0082,
3717 "Failed mailbox send register test.\n");
3718 } else {
3719 /* Flag a successful rval */
3720 rval = QLA_SUCCESS;
3721 }
3722
3723 return rval;
3724 }
3725
qla2x00_alloc_fce_trace(scsi_qla_host_t * vha)3726 int qla2x00_alloc_fce_trace(scsi_qla_host_t *vha)
3727 {
3728 dma_addr_t tc_dma;
3729 void *tc;
3730 struct qla_hw_data *ha = vha->hw;
3731
3732 if (!IS_FWI2_CAPABLE(ha))
3733 return -EINVAL;
3734
3735 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
3736 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
3737 return -EINVAL;
3738
3739 if (ha->fce) {
3740 ql_dbg(ql_dbg_init, vha, 0x00bd,
3741 "%s: FCE Mem is already allocated.\n",
3742 __func__);
3743 return -EIO;
3744 }
3745
3746 /* Allocate memory for Fibre Channel Event Buffer. */
3747 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
3748 GFP_KERNEL);
3749 if (!tc) {
3750 ql_log(ql_log_warn, vha, 0x00be,
3751 "Unable to allocate (%d KB) for FCE.\n",
3752 FCE_SIZE / 1024);
3753 return -ENOMEM;
3754 }
3755
3756 ql_dbg(ql_dbg_init, vha, 0x00c0,
3757 "Allocated (%d KB) for FCE...\n", FCE_SIZE / 1024);
3758
3759 ha->fce_dma = tc_dma;
3760 ha->fce = tc;
3761 ha->fce_bufs = FCE_NUM_BUFFERS;
3762 return 0;
3763 }
3764
qla2x00_free_fce_trace(struct qla_hw_data * ha)3765 void qla2x00_free_fce_trace(struct qla_hw_data *ha)
3766 {
3767 if (!ha->fce)
3768 return;
3769 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, ha->fce_dma);
3770 ha->fce = NULL;
3771 ha->fce_dma = 0;
3772 }
3773
3774 static void
qla2x00_alloc_eft_trace(scsi_qla_host_t * vha)3775 qla2x00_alloc_eft_trace(scsi_qla_host_t *vha)
3776 {
3777 dma_addr_t tc_dma;
3778 void *tc;
3779 struct qla_hw_data *ha = vha->hw;
3780
3781 if (!IS_FWI2_CAPABLE(ha))
3782 return;
3783
3784 if (ha->eft) {
3785 ql_dbg(ql_dbg_init, vha, 0x00bd,
3786 "%s: EFT Mem is already allocated.\n",
3787 __func__);
3788 return;
3789 }
3790
3791 /* Allocate memory for Extended Trace Buffer. */
3792 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
3793 GFP_KERNEL);
3794 if (!tc) {
3795 ql_log(ql_log_warn, vha, 0x00c1,
3796 "Unable to allocate (%d KB) for EFT.\n",
3797 EFT_SIZE / 1024);
3798 return;
3799 }
3800
3801 ql_dbg(ql_dbg_init, vha, 0x00c3,
3802 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
3803
3804 ha->eft_dma = tc_dma;
3805 ha->eft = tc;
3806 }
3807
3808 void
qla2x00_alloc_fw_dump(scsi_qla_host_t * vha)3809 qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
3810 {
3811 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
3812 eft_size, fce_size, mq_size;
3813 struct qla_hw_data *ha = vha->hw;
3814 struct req_que *req = ha->req_q_map[0];
3815 struct rsp_que *rsp = ha->rsp_q_map[0];
3816 struct qla2xxx_fw_dump *fw_dump;
3817
3818 if (ha->fw_dump) {
3819 ql_dbg(ql_dbg_init, vha, 0x00bd,
3820 "Firmware dump already allocated.\n");
3821 return;
3822 }
3823
3824 ha->fw_dumped = 0;
3825 ha->fw_dump_cap_flags = 0;
3826 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
3827 req_q_size = rsp_q_size = 0;
3828
3829 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3830 fixed_size = sizeof(struct qla2100_fw_dump);
3831 } else if (IS_QLA23XX(ha)) {
3832 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
3833 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
3834 sizeof(uint16_t);
3835 } else if (IS_FWI2_CAPABLE(ha)) {
3836 if (IS_QLA83XX(ha))
3837 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
3838 else if (IS_QLA81XX(ha))
3839 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
3840 else if (IS_QLA25XX(ha))
3841 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
3842 else
3843 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
3844
3845 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
3846 sizeof(uint32_t);
3847 if (ha->mqenable) {
3848 if (!IS_QLA83XX(ha))
3849 mq_size = sizeof(struct qla2xxx_mq_chain);
3850 /*
3851 * Allocate maximum buffer size for all queues - Q0.
3852 * Resizing must be done at end-of-dump processing.
3853 */
3854 mq_size += (ha->max_req_queues - 1) *
3855 (req->length * sizeof(request_t));
3856 mq_size += (ha->max_rsp_queues - 1) *
3857 (rsp->length * sizeof(response_t));
3858 }
3859 if (ha->tgt.atio_ring)
3860 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
3861
3862 if (ha->fce) {
3863 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
3864 ha->flags.fce_dump_buf_alloced = 1;
3865 }
3866 qla2x00_alloc_eft_trace(vha);
3867 if (ha->eft)
3868 eft_size = EFT_SIZE;
3869 }
3870
3871 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
3872 struct fwdt *fwdt = ha->fwdt;
3873 uint j;
3874
3875 for (j = 0; j < 2; j++, fwdt++) {
3876 if (!fwdt->template) {
3877 ql_dbg(ql_dbg_init, vha, 0x00ba,
3878 "-> fwdt%u no template\n", j);
3879 continue;
3880 }
3881 ql_dbg(ql_dbg_init, vha, 0x00fa,
3882 "-> fwdt%u calculating fwdump size...\n", j);
3883 fwdt->dump_size = qla27xx_fwdt_calculate_dump_size(
3884 vha, fwdt->template);
3885 ql_dbg(ql_dbg_init, vha, 0x00fa,
3886 "-> fwdt%u calculated fwdump size = %#lx bytes\n",
3887 j, fwdt->dump_size);
3888 dump_size += fwdt->dump_size;
3889 }
3890 /* Add space for spare MPI fw dump. */
3891 dump_size += ha->fwdt[1].dump_size;
3892 } else {
3893 req_q_size = req->length * sizeof(request_t);
3894 rsp_q_size = rsp->length * sizeof(response_t);
3895 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
3896 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size
3897 + eft_size;
3898 ha->chain_offset = dump_size;
3899 dump_size += mq_size + fce_size;
3900 if (ha->exchoffld_buf)
3901 dump_size += sizeof(struct qla2xxx_offld_chain) +
3902 ha->exchoffld_size;
3903 if (ha->exlogin_buf)
3904 dump_size += sizeof(struct qla2xxx_offld_chain) +
3905 ha->exlogin_size;
3906 }
3907
3908 if (!ha->fw_dump_len || dump_size > ha->fw_dump_alloc_len) {
3909
3910 ql_dbg(ql_dbg_init, vha, 0x00c5,
3911 "%s dump_size %d fw_dump_len %d fw_dump_alloc_len %d\n",
3912 __func__, dump_size, ha->fw_dump_len,
3913 ha->fw_dump_alloc_len);
3914
3915 fw_dump = vmalloc(dump_size);
3916 if (!fw_dump) {
3917 ql_log(ql_log_warn, vha, 0x00c4,
3918 "Unable to allocate (%d KB) for firmware dump.\n",
3919 dump_size / 1024);
3920 } else {
3921 mutex_lock(&ha->optrom_mutex);
3922 if (ha->fw_dumped) {
3923 memcpy(fw_dump, ha->fw_dump, ha->fw_dump_len);
3924 vfree(ha->fw_dump);
3925 ha->fw_dump = fw_dump;
3926 ha->fw_dump_alloc_len = dump_size;
3927 ql_dbg(ql_dbg_init, vha, 0x00c5,
3928 "Re-Allocated (%d KB) and save firmware dump.\n",
3929 dump_size / 1024);
3930 } else {
3931 vfree(ha->fw_dump);
3932 ha->fw_dump = fw_dump;
3933
3934 ha->fw_dump_len = ha->fw_dump_alloc_len =
3935 dump_size;
3936 ql_dbg(ql_dbg_init, vha, 0x00c5,
3937 "Allocated (%d KB) for firmware dump.\n",
3938 dump_size / 1024);
3939
3940 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
3941 ha->mpi_fw_dump = (char *)fw_dump +
3942 ha->fwdt[1].dump_size;
3943 mutex_unlock(&ha->optrom_mutex);
3944 return;
3945 }
3946
3947 ha->fw_dump->signature[0] = 'Q';
3948 ha->fw_dump->signature[1] = 'L';
3949 ha->fw_dump->signature[2] = 'G';
3950 ha->fw_dump->signature[3] = 'C';
3951 ha->fw_dump->version = htonl(1);
3952
3953 ha->fw_dump->fixed_size = htonl(fixed_size);
3954 ha->fw_dump->mem_size = htonl(mem_size);
3955 ha->fw_dump->req_q_size = htonl(req_q_size);
3956 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
3957
3958 ha->fw_dump->eft_size = htonl(eft_size);
3959 ha->fw_dump->eft_addr_l =
3960 htonl(LSD(ha->eft_dma));
3961 ha->fw_dump->eft_addr_h =
3962 htonl(MSD(ha->eft_dma));
3963
3964 ha->fw_dump->header_size =
3965 htonl(offsetof
3966 (struct qla2xxx_fw_dump, isp));
3967 }
3968 mutex_unlock(&ha->optrom_mutex);
3969 }
3970 }
3971 }
3972
3973 static int
qla81xx_mpi_sync(scsi_qla_host_t * vha)3974 qla81xx_mpi_sync(scsi_qla_host_t *vha)
3975 {
3976 #define MPS_MASK 0xe0
3977 int rval;
3978 uint16_t dc;
3979 uint32_t dw;
3980
3981 if (!IS_QLA81XX(vha->hw))
3982 return QLA_SUCCESS;
3983
3984 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
3985 if (rval != QLA_SUCCESS) {
3986 ql_log(ql_log_warn, vha, 0x0105,
3987 "Unable to acquire semaphore.\n");
3988 goto done;
3989 }
3990
3991 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
3992 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
3993 if (rval != QLA_SUCCESS) {
3994 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
3995 goto done_release;
3996 }
3997
3998 dc &= MPS_MASK;
3999 if (dc == (dw & MPS_MASK))
4000 goto done_release;
4001
4002 dw &= ~MPS_MASK;
4003 dw |= dc;
4004 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
4005 if (rval != QLA_SUCCESS) {
4006 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
4007 }
4008
4009 done_release:
4010 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
4011 if (rval != QLA_SUCCESS) {
4012 ql_log(ql_log_warn, vha, 0x006d,
4013 "Unable to release semaphore.\n");
4014 }
4015
4016 done:
4017 return rval;
4018 }
4019
4020 int
qla2x00_alloc_outstanding_cmds(struct qla_hw_data * ha,struct req_que * req)4021 qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
4022 {
4023 /* Don't try to reallocate the array */
4024 if (req->outstanding_cmds)
4025 return QLA_SUCCESS;
4026
4027 if (!IS_FWI2_CAPABLE(ha))
4028 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
4029 else {
4030 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
4031 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
4032 else
4033 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
4034 }
4035
4036 req->outstanding_cmds = kzalloc_objs(srb_t *, req->num_outstanding_cmds);
4037
4038 if (!req->outstanding_cmds) {
4039 /*
4040 * Try to allocate a minimal size just so we can get through
4041 * initialization.
4042 */
4043 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
4044 req->outstanding_cmds = kzalloc_objs(srb_t *,
4045 req->num_outstanding_cmds);
4046
4047 if (!req->outstanding_cmds) {
4048 ql_log(ql_log_fatal, NULL, 0x0126,
4049 "Failed to allocate memory for "
4050 "outstanding_cmds for req_que %p.\n", req);
4051 req->num_outstanding_cmds = 0;
4052 return QLA_FUNCTION_FAILED;
4053 }
4054 }
4055
4056 return QLA_SUCCESS;
4057 }
4058
4059 #define PRINT_FIELD(_field, _flag, _str) { \
4060 if (a0->_field & _flag) {\
4061 if (p) {\
4062 strcat(ptr, "|");\
4063 ptr++;\
4064 leftover--;\
4065 } \
4066 len = snprintf(ptr, leftover, "%s", _str); \
4067 p = 1;\
4068 leftover -= len;\
4069 ptr += len; \
4070 } \
4071 }
4072
qla2xxx_print_sfp_info(struct scsi_qla_host * vha)4073 static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
4074 {
4075 #define STR_LEN 64
4076 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
4077 u8 str[STR_LEN], *ptr, p;
4078 int leftover, len;
4079
4080 ql_dbg(ql_dbg_init, vha, 0x015a,
4081 "SFP: %.*s -> %.*s ->%s%s%s%s%s%s%s\n",
4082 (int)sizeof(a0->vendor_name), a0->vendor_name,
4083 (int)sizeof(a0->vendor_pn), a0->vendor_pn,
4084 a0->fc_sp_cc10 & FC_SP_2 ? a0->fiber_channel_speed2 & FC_SP_64 ?
4085 " 64G" : "" : "",
4086 a0->fc_sp_cc10 & FC_SP_32 ? " 32G" : "",
4087 a0->fc_sp_cc10 & FC_SP_16 ? " 16G" : "",
4088 a0->fc_sp_cc10 & FC_SP_8 ? " 8G" : "",
4089 a0->fc_sp_cc10 & FC_SP_4 ? " 4G" : "",
4090 a0->fc_sp_cc10 & FC_SP_2 ? " 2G" : "",
4091 a0->fc_sp_cc10 & FC_SP_1 ? " 1G" : "");
4092
4093 if (!(ql2xextended_error_logging & ql_dbg_verbose))
4094 return;
4095
4096 memset(str, 0, STR_LEN);
4097 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
4098 ql_dbg(ql_dbg_init, vha, 0x015a,
4099 "SFP MFG Name: %s\n", str);
4100
4101 memset(str, 0, STR_LEN);
4102 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
4103 ql_dbg(ql_dbg_init, vha, 0x015c,
4104 "SFP Part Name: %s\n", str);
4105
4106 /* media */
4107 memset(str, 0, STR_LEN);
4108 ptr = str;
4109 leftover = STR_LEN;
4110 p = len = 0;
4111 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
4112 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
4113 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
4114 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
4115 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
4116 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
4117 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
4118 ql_dbg(ql_dbg_init, vha, 0x0160,
4119 "SFP Media: %s\n", str);
4120
4121 /* link length */
4122 memset(str, 0, STR_LEN);
4123 ptr = str;
4124 leftover = STR_LEN;
4125 p = len = 0;
4126 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
4127 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
4128 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
4129 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
4130 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
4131 ql_dbg(ql_dbg_init, vha, 0x0196,
4132 "SFP Link Length: %s\n", str);
4133
4134 memset(str, 0, STR_LEN);
4135 ptr = str;
4136 leftover = STR_LEN;
4137 p = len = 0;
4138 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
4139 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
4140 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
4141 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
4142 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
4143 ql_dbg(ql_dbg_init, vha, 0x016e,
4144 "SFP FC Link Tech: %s\n", str);
4145
4146 if (a0->length_km)
4147 ql_dbg(ql_dbg_init, vha, 0x016f,
4148 "SFP Distant: %d km\n", a0->length_km);
4149 if (a0->length_100m)
4150 ql_dbg(ql_dbg_init, vha, 0x0170,
4151 "SFP Distant: %d m\n", a0->length_100m*100);
4152 if (a0->length_50um_10m)
4153 ql_dbg(ql_dbg_init, vha, 0x0189,
4154 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
4155 if (a0->length_62um_10m)
4156 ql_dbg(ql_dbg_init, vha, 0x018a,
4157 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
4158 if (a0->length_om4_10m)
4159 ql_dbg(ql_dbg_init, vha, 0x0194,
4160 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
4161 if (a0->length_om3_10m)
4162 ql_dbg(ql_dbg_init, vha, 0x0195,
4163 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
4164 }
4165
4166
4167 /**
4168 * qla24xx_detect_sfp()
4169 *
4170 * @vha: adapter state pointer.
4171 *
4172 * @return
4173 * 0 -- Configure firmware to use short-range settings -- normal
4174 * buffer-to-buffer credits.
4175 *
4176 * 1 -- Configure firmware to use long-range settings -- extra
4177 * buffer-to-buffer credits should be allocated with
4178 * ha->lr_distance containing distance settings from NVRAM or SFP
4179 * (if supported).
4180 */
4181 int
qla24xx_detect_sfp(scsi_qla_host_t * vha)4182 qla24xx_detect_sfp(scsi_qla_host_t *vha)
4183 {
4184 int rc, used_nvram;
4185 struct sff_8247_a0 *a;
4186 struct qla_hw_data *ha = vha->hw;
4187 struct nvram_81xx *nv = ha->nvram;
4188 #define LR_DISTANCE_UNKNOWN 2
4189 static const char * const types[] = { "Short", "Long" };
4190 static const char * const lengths[] = { "(10km)", "(5km)", "" };
4191 u8 ll = 0;
4192
4193 /* Seed with NVRAM settings. */
4194 used_nvram = 0;
4195 ha->flags.lr_detected = 0;
4196 if (IS_BPM_RANGE_CAPABLE(ha) &&
4197 (nv->enhanced_features & NEF_LR_DIST_ENABLE)) {
4198 used_nvram = 1;
4199 ha->flags.lr_detected = 1;
4200 ha->lr_distance =
4201 (nv->enhanced_features >> LR_DIST_NV_POS)
4202 & LR_DIST_NV_MASK;
4203 }
4204
4205 if (!IS_BPM_ENABLED(vha))
4206 goto out;
4207 /* Determine SR/LR capabilities of SFP/Transceiver. */
4208 rc = qla2x00_read_sfp_dev(vha, NULL, 0);
4209 if (rc)
4210 goto out;
4211
4212 used_nvram = 0;
4213 a = (struct sff_8247_a0 *)vha->hw->sfp_data;
4214 qla2xxx_print_sfp_info(vha);
4215
4216 ha->flags.lr_detected = 0;
4217 ll = a->fc_ll_cc7;
4218 if (ll & FC_LL_VL || ll & FC_LL_L) {
4219 /* Long range, track length. */
4220 ha->flags.lr_detected = 1;
4221
4222 if (a->length_km > 5 || a->length_100m > 50)
4223 ha->lr_distance = LR_DISTANCE_10K;
4224 else
4225 ha->lr_distance = LR_DISTANCE_5K;
4226 }
4227
4228 out:
4229 ql_dbg(ql_dbg_async, vha, 0x507b,
4230 "SFP detect: %s-Range SFP %s (nvr=%x ll=%x lr=%x lrd=%x).\n",
4231 types[ha->flags.lr_detected],
4232 ha->flags.lr_detected ? lengths[ha->lr_distance] :
4233 lengths[LR_DISTANCE_UNKNOWN],
4234 used_nvram, ll, ha->flags.lr_detected, ha->lr_distance);
4235 return ha->flags.lr_detected;
4236 }
4237
__qla_adjust_iocb_limit(struct qla_qpair * qpair)4238 static void __qla_adjust_iocb_limit(struct qla_qpair *qpair)
4239 {
4240 u8 num_qps;
4241 u16 limit;
4242 struct qla_hw_data *ha = qpair->vha->hw;
4243
4244 num_qps = ha->num_qpairs + 1;
4245 limit = (ha->orig_fw_iocb_count * QLA_IOCB_PCT_LIMIT) / 100;
4246
4247 qpair->fwres.iocbs_total = ha->orig_fw_iocb_count;
4248 qpair->fwres.iocbs_limit = limit;
4249 qpair->fwres.iocbs_qp_limit = limit / num_qps;
4250
4251 qpair->fwres.exch_total = ha->orig_fw_xcb_count;
4252 qpair->fwres.exch_limit = (ha->orig_fw_xcb_count *
4253 QLA_IOCB_PCT_LIMIT) / 100;
4254 }
4255
qla_init_iocb_limit(scsi_qla_host_t * vha)4256 void qla_init_iocb_limit(scsi_qla_host_t *vha)
4257 {
4258 u8 i;
4259 struct qla_hw_data *ha = vha->hw;
4260
4261 __qla_adjust_iocb_limit(ha->base_qpair);
4262 ha->base_qpair->fwres.iocbs_used = 0;
4263 ha->base_qpair->fwres.exch_used = 0;
4264
4265 for (i = 0; i < ha->max_qpairs; i++) {
4266 if (ha->queue_pair_map[i]) {
4267 __qla_adjust_iocb_limit(ha->queue_pair_map[i]);
4268 ha->queue_pair_map[i]->fwres.iocbs_used = 0;
4269 ha->queue_pair_map[i]->fwres.exch_used = 0;
4270 }
4271 }
4272
4273 ha->fwres.iocb_total = ha->orig_fw_iocb_count;
4274 ha->fwres.iocb_limit = (ha->orig_fw_iocb_count * QLA_IOCB_PCT_LIMIT) / 100;
4275 ha->fwres.exch_total = ha->orig_fw_xcb_count;
4276 ha->fwres.exch_limit = (ha->orig_fw_xcb_count * QLA_IOCB_PCT_LIMIT) / 100;
4277
4278 atomic_set(&ha->fwres.iocb_used, 0);
4279 atomic_set(&ha->fwres.exch_used, 0);
4280 }
4281
qla_adjust_iocb_limit(scsi_qla_host_t * vha)4282 void qla_adjust_iocb_limit(scsi_qla_host_t *vha)
4283 {
4284 u8 i;
4285 struct qla_hw_data *ha = vha->hw;
4286
4287 __qla_adjust_iocb_limit(ha->base_qpair);
4288
4289 for (i = 0; i < ha->max_qpairs; i++) {
4290 if (ha->queue_pair_map[i])
4291 __qla_adjust_iocb_limit(ha->queue_pair_map[i]);
4292 }
4293 }
4294
4295 /**
4296 * qla2x00_setup_chip() - Load and start RISC firmware.
4297 * @vha: HA context
4298 *
4299 * Returns 0 on success.
4300 */
4301 static int
qla2x00_setup_chip(scsi_qla_host_t * vha)4302 qla2x00_setup_chip(scsi_qla_host_t *vha)
4303 {
4304 int rval;
4305 uint32_t srisc_address = 0;
4306 struct qla_hw_data *ha = vha->hw;
4307 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4308 unsigned long flags;
4309 int done_once = 0;
4310
4311 if (IS_P3P_TYPE(ha)) {
4312 rval = ha->isp_ops->load_risc(vha, &srisc_address);
4313 if (rval == QLA_SUCCESS) {
4314 qla2x00_stop_firmware(vha);
4315 goto enable_82xx_npiv;
4316 } else
4317 goto failed;
4318 }
4319
4320 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
4321 /* Disable SRAM, Instruction RAM and GP RAM parity. */
4322 spin_lock_irqsave(&ha->hardware_lock, flags);
4323 wrt_reg_word(®->hccr, (HCCR_ENABLE_PARITY + 0x0));
4324 rd_reg_word(®->hccr);
4325 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4326 }
4327
4328 qla81xx_mpi_sync(vha);
4329
4330 execute_fw_with_lr:
4331 /* Load firmware sequences */
4332 rval = ha->isp_ops->load_risc(vha, &srisc_address);
4333 if (rval == QLA_SUCCESS) {
4334 ql_dbg(ql_dbg_init, vha, 0x00c9,
4335 "Verifying Checksum of loaded RISC code.\n");
4336
4337 rval = qla2x00_verify_checksum(vha, srisc_address);
4338 if (rval == QLA_SUCCESS) {
4339 /* Start firmware execution. */
4340 ql_dbg(ql_dbg_init, vha, 0x00ca,
4341 "Starting firmware.\n");
4342
4343 if (ql2xexlogins)
4344 ha->flags.exlogins_enabled = 1;
4345
4346 if (qla_is_exch_offld_enabled(vha))
4347 ha->flags.exchoffld_enabled = 1;
4348
4349 rval = qla2x00_execute_fw(vha, srisc_address);
4350 /* Retrieve firmware information. */
4351 if (rval == QLA_SUCCESS) {
4352 /* Enable BPM support? */
4353 if (!done_once++ && qla24xx_detect_sfp(vha)) {
4354 ql_dbg(ql_dbg_init, vha, 0x00ca,
4355 "Re-starting firmware -- BPM.\n");
4356 /* Best-effort - re-init. */
4357 ha->isp_ops->reset_chip(vha);
4358 ha->isp_ops->chip_diag(vha);
4359 goto execute_fw_with_lr;
4360 }
4361
4362 if (IS_ZIO_THRESHOLD_CAPABLE(ha))
4363 qla27xx_set_zio_threshold(vha,
4364 ha->last_zio_threshold);
4365
4366 rval = qla2x00_set_exlogins_buffer(vha);
4367 if (rval != QLA_SUCCESS)
4368 goto failed;
4369
4370 rval = qla2x00_set_exchoffld_buffer(vha);
4371 if (rval != QLA_SUCCESS)
4372 goto failed;
4373
4374 enable_82xx_npiv:
4375 if (IS_P3P_TYPE(ha))
4376 qla82xx_check_md_needed(vha);
4377 else
4378 rval = qla2x00_get_fw_version(vha);
4379 if (rval != QLA_SUCCESS)
4380 goto failed;
4381 ha->flags.npiv_supported = 0;
4382 if (IS_QLA2XXX_MIDTYPE(ha) &&
4383 (ha->fw_attributes & BIT_2)) {
4384 ha->flags.npiv_supported = 1;
4385 if ((!ha->max_npiv_vports) ||
4386 ((ha->max_npiv_vports + 1) %
4387 MIN_MULTI_ID_FABRIC))
4388 ha->max_npiv_vports =
4389 MIN_MULTI_ID_FABRIC - 1;
4390 }
4391 qlt_config_nvram_with_fw_version(vha);
4392 qla2x00_get_resource_cnts(vha);
4393 qla_init_iocb_limit(vha);
4394
4395 /*
4396 * Allocate the array of outstanding commands
4397 * now that we know the firmware resources.
4398 */
4399 rval = qla2x00_alloc_outstanding_cmds(ha,
4400 vha->req);
4401 if (rval != QLA_SUCCESS)
4402 goto failed;
4403
4404 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha)))
4405 qla2x00_alloc_fw_dump(vha);
4406
4407 qla_enable_fce_trace(vha);
4408 qla_enable_eft_trace(vha);
4409 } else {
4410 goto failed;
4411 }
4412 } else {
4413 ql_log(ql_log_fatal, vha, 0x00cd,
4414 "ISP Firmware failed checksum.\n");
4415 goto failed;
4416 }
4417
4418 /* Enable PUREX PASSTHRU */
4419 if (ql2xrdpenable || ha->flags.scm_supported_f ||
4420 ha->flags.edif_enabled)
4421 qla25xx_set_els_cmds_supported(vha);
4422 } else
4423 goto failed;
4424
4425 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
4426 /* Enable proper parity. */
4427 spin_lock_irqsave(&ha->hardware_lock, flags);
4428 if (IS_QLA2300(ha))
4429 /* SRAM parity */
4430 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x1);
4431 else
4432 /* SRAM, Instruction RAM and GP RAM parity */
4433 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x7);
4434 rd_reg_word(®->hccr);
4435 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4436 }
4437
4438 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
4439 ha->flags.fac_supported = 1;
4440 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
4441 uint32_t size;
4442
4443 rval = qla81xx_fac_get_sector_size(vha, &size);
4444 if (rval == QLA_SUCCESS) {
4445 ha->flags.fac_supported = 1;
4446 ha->fdt_block_size = size << 2;
4447 } else {
4448 ql_log(ql_log_warn, vha, 0x00ce,
4449 "Unsupported FAC firmware (%d.%02d.%02d).\n",
4450 ha->fw_major_version, ha->fw_minor_version,
4451 ha->fw_subminor_version);
4452
4453 if (IS_QLA83XX(ha)) {
4454 ha->flags.fac_supported = 0;
4455 rval = QLA_SUCCESS;
4456 }
4457 }
4458 }
4459 failed:
4460 if (rval) {
4461 ql_log(ql_log_fatal, vha, 0x00cf,
4462 "Setup chip ****FAILED****.\n");
4463 }
4464
4465 return (rval);
4466 }
4467
4468 /**
4469 * qla2x00_init_response_q_entries() - Initializes response queue entries.
4470 * @rsp: response queue
4471 *
4472 * Beginning of request ring has initialization control block already built
4473 * by nvram config routine.
4474 *
4475 * Returns 0 on success.
4476 */
4477 void
qla2x00_init_response_q_entries(struct rsp_que * rsp)4478 qla2x00_init_response_q_entries(struct rsp_que *rsp)
4479 {
4480 uint16_t cnt;
4481 response_t *pkt;
4482
4483 rsp->ring_ptr = rsp->ring;
4484 rsp->ring_index = 0;
4485 rsp->status_srb = NULL;
4486 pkt = rsp->ring_ptr;
4487 for (cnt = 0; cnt < rsp->length; cnt++) {
4488 pkt->signature = RESPONSE_PROCESSED;
4489 pkt++;
4490 }
4491 }
4492
4493 /**
4494 * qla2x00_update_fw_options() - Read and process firmware options.
4495 * @vha: HA context
4496 *
4497 * Returns 0 on success.
4498 */
4499 void
qla2x00_update_fw_options(scsi_qla_host_t * vha)4500 qla2x00_update_fw_options(scsi_qla_host_t *vha)
4501 {
4502 uint16_t swing, emphasis, tx_sens, rx_sens;
4503 struct qla_hw_data *ha = vha->hw;
4504
4505 memset(ha->fw_options, 0, sizeof(ha->fw_options));
4506 qla2x00_get_fw_options(vha, ha->fw_options);
4507
4508 if (IS_QLA2100(ha) || IS_QLA2200(ha))
4509 return;
4510
4511 /* Serial Link options. */
4512 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
4513 "Serial link options.\n");
4514 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
4515 ha->fw_seriallink_options, sizeof(ha->fw_seriallink_options));
4516
4517 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
4518 if (ha->fw_seriallink_options[3] & BIT_2) {
4519 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
4520
4521 /* 1G settings */
4522 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
4523 emphasis = (ha->fw_seriallink_options[2] &
4524 (BIT_4 | BIT_3)) >> 3;
4525 tx_sens = ha->fw_seriallink_options[0] &
4526 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4527 rx_sens = (ha->fw_seriallink_options[0] &
4528 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
4529 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
4530 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
4531 if (rx_sens == 0x0)
4532 rx_sens = 0x3;
4533 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
4534 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
4535 ha->fw_options[10] |= BIT_5 |
4536 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
4537 (tx_sens & (BIT_1 | BIT_0));
4538
4539 /* 2G settings */
4540 swing = (ha->fw_seriallink_options[2] &
4541 (BIT_7 | BIT_6 | BIT_5)) >> 5;
4542 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
4543 tx_sens = ha->fw_seriallink_options[1] &
4544 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4545 rx_sens = (ha->fw_seriallink_options[1] &
4546 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
4547 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
4548 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
4549 if (rx_sens == 0x0)
4550 rx_sens = 0x3;
4551 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
4552 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
4553 ha->fw_options[11] |= BIT_5 |
4554 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
4555 (tx_sens & (BIT_1 | BIT_0));
4556 }
4557
4558 /* FCP2 options. */
4559 /* Return command IOCBs without waiting for an ABTS to complete. */
4560 ha->fw_options[3] |= BIT_13;
4561
4562 /* LED scheme. */
4563 if (ha->flags.enable_led_scheme)
4564 ha->fw_options[2] |= BIT_12;
4565
4566 /* Detect ISP6312. */
4567 if (IS_QLA6312(ha))
4568 ha->fw_options[2] |= BIT_13;
4569
4570 /* Set Retry FLOGI in case of P2P connection */
4571 if (ha->operating_mode == P2P) {
4572 ha->fw_options[2] |= BIT_3;
4573 ql_dbg(ql_dbg_disc, vha, 0x2100,
4574 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
4575 __func__, ha->fw_options[2]);
4576 }
4577
4578 /* Update firmware options. */
4579 qla2x00_set_fw_options(vha, ha->fw_options);
4580 }
4581
4582 void
qla24xx_update_fw_options(scsi_qla_host_t * vha)4583 qla24xx_update_fw_options(scsi_qla_host_t *vha)
4584 {
4585 int rval;
4586 struct qla_hw_data *ha = vha->hw;
4587
4588 if (IS_P3P_TYPE(ha))
4589 return;
4590
4591 /* Hold status IOCBs until ABTS response received. */
4592 if (ql2xfwholdabts)
4593 ha->fw_options[3] |= BIT_12;
4594
4595 /* Set Retry FLOGI in case of P2P connection */
4596 if (ha->operating_mode == P2P) {
4597 ha->fw_options[2] |= BIT_3;
4598 ql_dbg(ql_dbg_disc, vha, 0x2101,
4599 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
4600 __func__, ha->fw_options[2]);
4601 }
4602
4603 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
4604 if (ql2xmvasynctoatio && !ha->flags.edif_enabled &&
4605 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
4606 if (qla_tgt_mode_enabled(vha) ||
4607 qla_dual_mode_enabled(vha))
4608 ha->fw_options[2] |= BIT_11;
4609 else
4610 ha->fw_options[2] &= ~BIT_11;
4611 }
4612
4613 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
4614 IS_QLA28XX(ha)) {
4615 /*
4616 * Tell FW to track each exchange to prevent
4617 * driver from using stale exchange.
4618 */
4619 if (qla_tgt_mode_enabled(vha) ||
4620 qla_dual_mode_enabled(vha))
4621 ha->fw_options[2] |= BIT_4;
4622 else
4623 ha->fw_options[2] &= ~(BIT_4);
4624
4625 /* Reserve 1/2 of emergency exchanges for ELS.*/
4626 if (qla2xuseresexchforels)
4627 ha->fw_options[2] |= BIT_8;
4628 else
4629 ha->fw_options[2] &= ~BIT_8;
4630
4631 /*
4632 * N2N: set Secure=1 for PLOGI ACC and
4633 * fw shal not send PRLI after PLOGI Acc
4634 */
4635 if (ha->flags.edif_enabled &&
4636 DBELL_ACTIVE(vha)) {
4637 ha->fw_options[3] |= BIT_15;
4638 ha->flags.n2n_fw_acc_sec = 1;
4639 } else {
4640 ha->fw_options[3] &= ~BIT_15;
4641 ha->flags.n2n_fw_acc_sec = 0;
4642 }
4643 }
4644
4645 if (ql2xrdpenable || ha->flags.scm_supported_f ||
4646 ha->flags.edif_enabled)
4647 ha->fw_options[1] |= ADD_FO1_ENABLE_PUREX_IOCB;
4648
4649 /* Enable Async 8130/8131 events -- transceiver insertion/removal */
4650 if (IS_BPM_RANGE_CAPABLE(ha))
4651 ha->fw_options[3] |= BIT_10;
4652
4653 ql_dbg(ql_dbg_init, vha, 0x00e8,
4654 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
4655 __func__, ha->fw_options[1], ha->fw_options[2],
4656 ha->fw_options[3], vha->host->active_mode);
4657
4658 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
4659 qla2x00_set_fw_options(vha, ha->fw_options);
4660
4661 /* Update Serial Link options. */
4662 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
4663 return;
4664
4665 rval = qla2x00_set_serdes_params(vha,
4666 le16_to_cpu(ha->fw_seriallink_options24[1]),
4667 le16_to_cpu(ha->fw_seriallink_options24[2]),
4668 le16_to_cpu(ha->fw_seriallink_options24[3]));
4669 if (rval != QLA_SUCCESS) {
4670 ql_log(ql_log_warn, vha, 0x0104,
4671 "Unable to update Serial Link options (%x).\n", rval);
4672 }
4673 }
4674
4675 void
qla2x00_config_rings(struct scsi_qla_host * vha)4676 qla2x00_config_rings(struct scsi_qla_host *vha)
4677 {
4678 struct qla_hw_data *ha = vha->hw;
4679 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4680 struct req_que *req = ha->req_q_map[0];
4681 struct rsp_que *rsp = ha->rsp_q_map[0];
4682
4683 /* Setup ring parameters in initialization control block. */
4684 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
4685 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
4686 ha->init_cb->request_q_length = cpu_to_le16(req->length);
4687 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
4688 put_unaligned_le64(req->dma, &ha->init_cb->request_q_address);
4689 put_unaligned_le64(rsp->dma, &ha->init_cb->response_q_address);
4690
4691 wrt_reg_word(ISP_REQ_Q_IN(ha, reg), 0);
4692 wrt_reg_word(ISP_REQ_Q_OUT(ha, reg), 0);
4693 wrt_reg_word(ISP_RSP_Q_IN(ha, reg), 0);
4694 wrt_reg_word(ISP_RSP_Q_OUT(ha, reg), 0);
4695 rd_reg_word(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
4696 }
4697
4698 void
qla24xx_config_rings(struct scsi_qla_host * vha)4699 qla24xx_config_rings(struct scsi_qla_host *vha)
4700 {
4701 struct qla_hw_data *ha = vha->hw;
4702 device_reg_t *reg = ISP_QUE_REG(ha, 0);
4703 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
4704 struct qla_msix_entry *msix;
4705 struct init_cb_24xx *icb;
4706 uint16_t rid = 0;
4707 struct req_que *req = ha->req_q_map[0];
4708 struct rsp_que *rsp = ha->rsp_q_map[0];
4709
4710 /* Setup ring parameters in initialization control block. */
4711 icb = (struct init_cb_24xx *)ha->init_cb;
4712 icb->request_q_outpointer = cpu_to_le16(0);
4713 icb->response_q_inpointer = cpu_to_le16(0);
4714 icb->request_q_length = cpu_to_le16(req->length);
4715 icb->response_q_length = cpu_to_le16(rsp->length);
4716 put_unaligned_le64(req->dma, &icb->request_q_address);
4717 put_unaligned_le64(rsp->dma, &icb->response_q_address);
4718
4719 /* Setup ATIO queue dma pointers for target mode */
4720 icb->atio_q_inpointer = cpu_to_le16(0);
4721 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
4722 put_unaligned_le64(ha->tgt.atio_dma, &icb->atio_q_address);
4723
4724 if (IS_SHADOW_REG_CAPABLE(ha))
4725 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
4726
4727 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
4728 IS_QLA28XX(ha)) {
4729 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
4730 icb->rid = cpu_to_le16(rid);
4731 if (ha->flags.msix_enabled) {
4732 msix = &ha->msix_entries[1];
4733 ql_dbg(ql_dbg_init, vha, 0x0019,
4734 "Registering vector 0x%x for base que.\n",
4735 msix->entry);
4736 icb->msix = cpu_to_le16(msix->entry);
4737 }
4738 /* Use alternate PCI bus number */
4739 if (MSB(rid))
4740 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
4741 /* Use alternate PCI devfn */
4742 if (LSB(rid))
4743 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
4744
4745 /* Use Disable MSIX Handshake mode for capable adapters */
4746 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
4747 (ha->flags.msix_enabled)) {
4748 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
4749 ha->flags.disable_msix_handshake = 1;
4750 ql_dbg(ql_dbg_init, vha, 0x00fe,
4751 "MSIX Handshake Disable Mode turned on.\n");
4752 } else {
4753 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
4754 }
4755 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
4756
4757 wrt_reg_dword(®->isp25mq.req_q_in, 0);
4758 wrt_reg_dword(®->isp25mq.req_q_out, 0);
4759 wrt_reg_dword(®->isp25mq.rsp_q_in, 0);
4760 wrt_reg_dword(®->isp25mq.rsp_q_out, 0);
4761 } else {
4762 wrt_reg_dword(®->isp24.req_q_in, 0);
4763 wrt_reg_dword(®->isp24.req_q_out, 0);
4764 wrt_reg_dword(®->isp24.rsp_q_in, 0);
4765 wrt_reg_dword(®->isp24.rsp_q_out, 0);
4766 }
4767
4768 qlt_24xx_config_rings(vha);
4769
4770 /* If the user has configured the speed, set it here */
4771 if (ha->set_data_rate) {
4772 ql_dbg(ql_dbg_init, vha, 0x00fd,
4773 "Speed set by user : %s Gbps \n",
4774 qla2x00_get_link_speed_str(ha, ha->set_data_rate));
4775 icb->firmware_options_3 = cpu_to_le32(ha->set_data_rate << 13);
4776 }
4777
4778 /* PCI posting */
4779 rd_reg_word(&ioreg->hccr);
4780 }
4781
4782 /**
4783 * qla2x00_init_rings() - Initializes firmware.
4784 * @vha: HA context
4785 *
4786 * Beginning of request ring has initialization control block already built
4787 * by nvram config routine.
4788 *
4789 * Returns 0 on success.
4790 */
4791 int
qla2x00_init_rings(scsi_qla_host_t * vha)4792 qla2x00_init_rings(scsi_qla_host_t *vha)
4793 {
4794 int rval;
4795 unsigned long flags = 0;
4796 int cnt, que;
4797 struct qla_hw_data *ha = vha->hw;
4798 struct req_que *req;
4799 struct rsp_que *rsp;
4800 struct mid_init_cb_24xx *mid_init_cb =
4801 (struct mid_init_cb_24xx *) ha->init_cb;
4802
4803 spin_lock_irqsave(&ha->hardware_lock, flags);
4804
4805 /* Clear outstanding commands array. */
4806 for (que = 0; que < ha->max_req_queues; que++) {
4807 req = ha->req_q_map[que];
4808 if (!req || !test_bit(que, ha->req_qid_map))
4809 continue;
4810 req->out_ptr = (uint16_t *)(req->ring + req->length);
4811 *req->out_ptr = 0;
4812 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
4813 req->outstanding_cmds[cnt] = NULL;
4814
4815 req->current_outstanding_cmd = 1;
4816
4817 /* Initialize firmware. */
4818 req->ring_ptr = req->ring;
4819 req->ring_index = 0;
4820 req->cnt = req->length;
4821 }
4822
4823 for (que = 0; que < ha->max_rsp_queues; que++) {
4824 rsp = ha->rsp_q_map[que];
4825 if (!rsp || !test_bit(que, ha->rsp_qid_map))
4826 continue;
4827 rsp->in_ptr = (uint16_t *)(rsp->ring + rsp->length);
4828 *rsp->in_ptr = 0;
4829 /* Initialize response queue entries */
4830 if (IS_QLAFX00(ha))
4831 qlafx00_init_response_q_entries(rsp);
4832 else
4833 qla2x00_init_response_q_entries(rsp);
4834 }
4835
4836 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
4837 ha->tgt.atio_ring_index = 0;
4838 /* Initialize ATIO queue entries */
4839 qlt_init_atio_q_entries(vha);
4840
4841 ha->isp_ops->config_rings(vha);
4842
4843 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4844
4845 if (IS_QLAFX00(ha)) {
4846 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
4847 goto next_check;
4848 }
4849
4850 /* Update any ISP specific firmware options before initialization. */
4851 ha->isp_ops->update_fw_options(vha);
4852
4853 ql_dbg(ql_dbg_init, vha, 0x00d1,
4854 "Issue init firmware FW opt 1-3= %08x %08x %08x.\n",
4855 le32_to_cpu(mid_init_cb->init_cb.firmware_options_1),
4856 le32_to_cpu(mid_init_cb->init_cb.firmware_options_2),
4857 le32_to_cpu(mid_init_cb->init_cb.firmware_options_3));
4858
4859 if (ha->flags.npiv_supported) {
4860 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
4861 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
4862 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
4863 }
4864
4865 if (IS_FWI2_CAPABLE(ha)) {
4866 mid_init_cb->options = cpu_to_le16(BIT_1);
4867 mid_init_cb->init_cb.execution_throttle =
4868 cpu_to_le16(ha->cur_fw_xcb_count);
4869 ha->flags.dport_enabled =
4870 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) &
4871 BIT_7) != 0;
4872 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
4873 (ha->flags.dport_enabled) ? "enabled" : "disabled");
4874 /* FA-WWPN Status */
4875 ha->flags.fawwpn_enabled =
4876 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) &
4877 BIT_6) != 0;
4878 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
4879 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
4880 /* Init_cb will be reused for other command(s). Save a backup copy of port_name */
4881 memcpy(ha->port_name, ha->init_cb->port_name, WWN_SIZE);
4882 }
4883
4884 /* ELS pass through payload is limit by frame size. */
4885 if (ha->flags.edif_enabled)
4886 mid_init_cb->init_cb.frame_payload_size = cpu_to_le16(ELS_MAX_PAYLOAD);
4887
4888 QLA_FW_STARTED(ha);
4889 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
4890 next_check:
4891 if (rval) {
4892 QLA_FW_STOPPED(ha);
4893 ql_log(ql_log_fatal, vha, 0x00d2,
4894 "Init Firmware **** FAILED ****.\n");
4895 } else {
4896 ql_dbg(ql_dbg_init, vha, 0x00d3,
4897 "Init Firmware -- success.\n");
4898 vha->u_ql2xexchoffld = vha->u_ql2xiniexchg = 0;
4899 }
4900
4901 return (rval);
4902 }
4903
4904 /**
4905 * qla2x00_fw_ready() - Waits for firmware ready.
4906 * @vha: HA context
4907 *
4908 * Returns 0 on success.
4909 */
4910 static int
qla2x00_fw_ready(scsi_qla_host_t * vha)4911 qla2x00_fw_ready(scsi_qla_host_t *vha)
4912 {
4913 int rval;
4914 unsigned long wtime, mtime, cs84xx_time;
4915 uint16_t min_wait; /* Minimum wait time if loop is down */
4916 uint16_t wait_time; /* Wait time if loop is coming ready */
4917 uint16_t state[6];
4918 struct qla_hw_data *ha = vha->hw;
4919
4920 if (IS_QLAFX00(vha->hw))
4921 return qlafx00_fw_ready(vha);
4922
4923 /* Time to wait for loop down */
4924 if (IS_P3P_TYPE(ha))
4925 min_wait = 30;
4926 else
4927 min_wait = 20;
4928
4929 /*
4930 * Firmware should take at most one RATOV to login, plus 5 seconds for
4931 * our own processing.
4932 */
4933 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
4934 wait_time = min_wait;
4935 }
4936
4937 /* Min wait time if loop down */
4938 mtime = jiffies + (min_wait * HZ);
4939
4940 /* wait time before firmware ready */
4941 wtime = jiffies + (wait_time * HZ);
4942
4943 /* Wait for ISP to finish LIP */
4944 if (!vha->flags.init_done)
4945 ql_log(ql_log_info, vha, 0x801e,
4946 "Waiting for LIP to complete.\n");
4947
4948 do {
4949 memset(state, -1, sizeof(state));
4950 rval = qla2x00_get_firmware_state(vha, state);
4951 if (rval == QLA_SUCCESS) {
4952 if (state[0] < FSTATE_LOSS_OF_SYNC) {
4953 vha->device_flags &= ~DFLG_NO_CABLE;
4954 }
4955 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
4956 ql_dbg(ql_dbg_taskm, vha, 0x801f,
4957 "fw_state=%x 84xx=%x.\n", state[0],
4958 state[2]);
4959 if ((state[2] & FSTATE_LOGGED_IN) &&
4960 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
4961 ql_dbg(ql_dbg_taskm, vha, 0x8028,
4962 "Sending verify iocb.\n");
4963
4964 cs84xx_time = jiffies;
4965 rval = qla84xx_init_chip(vha);
4966 if (rval != QLA_SUCCESS) {
4967 ql_log(ql_log_warn,
4968 vha, 0x8007,
4969 "Init chip failed.\n");
4970 break;
4971 }
4972
4973 /* Add time taken to initialize. */
4974 cs84xx_time = jiffies - cs84xx_time;
4975 wtime += cs84xx_time;
4976 mtime += cs84xx_time;
4977 ql_dbg(ql_dbg_taskm, vha, 0x8008,
4978 "Increasing wait time by %ld. "
4979 "New time %ld.\n", cs84xx_time,
4980 wtime);
4981 }
4982 } else if (state[0] == FSTATE_READY) {
4983 ql_dbg(ql_dbg_taskm, vha, 0x8037,
4984 "F/W Ready - OK.\n");
4985
4986 qla2x00_get_retry_cnt(vha, &ha->retry_count,
4987 &ha->login_timeout, &ha->r_a_tov);
4988
4989 rval = QLA_SUCCESS;
4990 break;
4991 }
4992
4993 rval = QLA_FUNCTION_FAILED;
4994
4995 if (atomic_read(&vha->loop_down_timer) &&
4996 state[0] != FSTATE_READY) {
4997 /* Loop down. Timeout on min_wait for states
4998 * other than Wait for Login.
4999 */
5000 if (time_after_eq(jiffies, mtime)) {
5001 ql_log(ql_log_info, vha, 0x8038,
5002 "Cable is unplugged...\n");
5003
5004 vha->device_flags |= DFLG_NO_CABLE;
5005 break;
5006 }
5007 }
5008 } else {
5009 /* Mailbox cmd failed. Timeout on min_wait. */
5010 if (time_after_eq(jiffies, mtime) ||
5011 ha->flags.isp82xx_fw_hung)
5012 break;
5013 }
5014
5015 if (time_after_eq(jiffies, wtime))
5016 break;
5017
5018 /* Delay for a while */
5019 msleep(500);
5020 } while (1);
5021
5022 ql_dbg(ql_dbg_taskm, vha, 0x803a,
5023 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
5024 state[1], state[2], state[3], state[4], state[5], jiffies);
5025
5026 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
5027 ql_log(ql_log_warn, vha, 0x803b,
5028 "Firmware ready **** FAILED ****.\n");
5029 }
5030
5031 return (rval);
5032 }
5033
5034 /*
5035 * qla2x00_configure_hba
5036 * Setup adapter context.
5037 *
5038 * Input:
5039 * ha = adapter state pointer.
5040 *
5041 * Returns:
5042 * 0 = success
5043 *
5044 * Context:
5045 * Kernel context.
5046 */
5047 static int
qla2x00_configure_hba(scsi_qla_host_t * vha)5048 qla2x00_configure_hba(scsi_qla_host_t *vha)
5049 {
5050 int rval;
5051 uint16_t loop_id;
5052 uint16_t topo;
5053 uint16_t sw_cap;
5054 uint8_t al_pa;
5055 uint8_t area;
5056 uint8_t domain;
5057 char connect_type[22];
5058 struct qla_hw_data *ha = vha->hw;
5059 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5060 port_id_t id;
5061 unsigned long flags;
5062
5063 /* Get host addresses. */
5064 rval = qla2x00_get_adapter_id(vha,
5065 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
5066 if (rval != QLA_SUCCESS) {
5067 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
5068 IS_CNA_CAPABLE(ha) ||
5069 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
5070 ql_dbg(ql_dbg_disc, vha, 0x2008,
5071 "Loop is in a transition state.\n");
5072 } else {
5073 ql_log(ql_log_warn, vha, 0x2009,
5074 "Unable to get host loop ID.\n");
5075 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
5076 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
5077 ql_log(ql_log_warn, vha, 0x1151,
5078 "Doing link init.\n");
5079 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
5080 return rval;
5081 }
5082 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
5083 }
5084 return (rval);
5085 }
5086
5087 if (topo == 4) {
5088 ql_log(ql_log_info, vha, 0x200a,
5089 "Cannot get topology - retrying.\n");
5090 return (QLA_FUNCTION_FAILED);
5091 }
5092
5093 vha->loop_id = loop_id;
5094
5095 /* initialize */
5096 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
5097 ha->operating_mode = LOOP;
5098
5099 switch (topo) {
5100 case 0:
5101 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
5102 ha->switch_cap = 0;
5103 ha->current_topology = ISP_CFG_NL;
5104 strcpy(connect_type, "(Loop)");
5105 break;
5106
5107 case 1:
5108 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
5109 ha->switch_cap = sw_cap;
5110 ha->current_topology = ISP_CFG_FL;
5111 strcpy(connect_type, "(FL_Port)");
5112 break;
5113
5114 case 2:
5115 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
5116 ha->switch_cap = 0;
5117 ha->operating_mode = P2P;
5118 ha->current_topology = ISP_CFG_N;
5119 strcpy(connect_type, "(N_Port-to-N_Port)");
5120 break;
5121
5122 case 3:
5123 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
5124 ha->switch_cap = sw_cap;
5125 ha->operating_mode = P2P;
5126 ha->current_topology = ISP_CFG_F;
5127 strcpy(connect_type, "(F_Port)");
5128 break;
5129
5130 default:
5131 ql_dbg(ql_dbg_disc, vha, 0x200f,
5132 "HBA in unknown topology %x, using NL.\n", topo);
5133 ha->switch_cap = 0;
5134 ha->current_topology = ISP_CFG_NL;
5135 strcpy(connect_type, "(Loop)");
5136 break;
5137 }
5138
5139 /* Save Host port and loop ID. */
5140 /* byte order - Big Endian */
5141 id.b.domain = domain;
5142 id.b.area = area;
5143 id.b.al_pa = al_pa;
5144 id.b.rsvd_1 = 0;
5145 spin_lock_irqsave(&ha->hardware_lock, flags);
5146 if (vha->hw->flags.edif_enabled) {
5147 if (topo != 2)
5148 qla_update_host_map(vha, id);
5149 } else if (!(topo == 2 && ha->flags.n2n_bigger))
5150 qla_update_host_map(vha, id);
5151 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5152
5153 if (!vha->flags.init_done)
5154 ql_log(ql_log_info, vha, 0x2010,
5155 "Topology - %s, Host Loop address 0x%x.\n",
5156 connect_type, vha->loop_id);
5157
5158 return(rval);
5159 }
5160
5161 inline void
qla2x00_set_model_info(scsi_qla_host_t * vha,uint8_t * model,size_t len,const char * def)5162 qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
5163 const char *def)
5164 {
5165 char *st, *en;
5166 uint16_t index;
5167 uint64_t zero[2] = { 0 };
5168 struct qla_hw_data *ha = vha->hw;
5169 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
5170 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
5171
5172 if (len > sizeof(zero))
5173 len = sizeof(zero);
5174 if (memcmp(model, &zero, len) != 0) {
5175 memcpy(ha->model_number, model, len);
5176 st = en = ha->model_number;
5177 en += len - 1;
5178 while (en > st) {
5179 if (*en != 0x20 && *en != 0x00)
5180 break;
5181 *en-- = '\0';
5182 }
5183
5184 index = (ha->pdev->subsystem_device & 0xff);
5185 if (use_tbl &&
5186 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
5187 index < QLA_MODEL_NAMES)
5188 strscpy(ha->model_desc,
5189 qla2x00_model_name[index * 2 + 1],
5190 sizeof(ha->model_desc));
5191 } else {
5192 index = (ha->pdev->subsystem_device & 0xff);
5193 if (use_tbl &&
5194 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
5195 index < QLA_MODEL_NAMES) {
5196 strscpy(ha->model_number,
5197 qla2x00_model_name[index * 2],
5198 sizeof(ha->model_number));
5199 strscpy(ha->model_desc,
5200 qla2x00_model_name[index * 2 + 1],
5201 sizeof(ha->model_desc));
5202 } else {
5203 strscpy(ha->model_number, def,
5204 sizeof(ha->model_number));
5205 }
5206 }
5207 if (IS_FWI2_CAPABLE(ha))
5208 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
5209 sizeof(ha->model_desc));
5210 }
5211
5212 /* On sparc systems, obtain port and node WWN from firmware
5213 * properties.
5214 */
qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t * vha,nvram_t * nv)5215 static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
5216 {
5217 #ifdef CONFIG_SPARC
5218 struct qla_hw_data *ha = vha->hw;
5219 struct pci_dev *pdev = ha->pdev;
5220 struct device_node *dp = pci_device_to_OF_node(pdev);
5221 const u8 *val;
5222 int len;
5223
5224 val = of_get_property(dp, "port-wwn", &len);
5225 if (val && len >= WWN_SIZE)
5226 memcpy(nv->port_name, val, WWN_SIZE);
5227
5228 val = of_get_property(dp, "node-wwn", &len);
5229 if (val && len >= WWN_SIZE)
5230 memcpy(nv->node_name, val, WWN_SIZE);
5231 #endif
5232 }
5233
5234 /*
5235 * NVRAM configuration for ISP 2xxx
5236 *
5237 * Input:
5238 * ha = adapter block pointer.
5239 *
5240 * Output:
5241 * initialization control block in response_ring
5242 * host adapters parameters in host adapter block
5243 *
5244 * Returns:
5245 * 0 = success.
5246 */
5247 int
qla2x00_nvram_config(scsi_qla_host_t * vha)5248 qla2x00_nvram_config(scsi_qla_host_t *vha)
5249 {
5250 int rval;
5251 uint8_t chksum = 0;
5252 uint16_t cnt;
5253 uint8_t *dptr1, *dptr2;
5254 struct qla_hw_data *ha = vha->hw;
5255 init_cb_t *icb = ha->init_cb;
5256 nvram_t *nv = ha->nvram;
5257 uint8_t *ptr = ha->nvram;
5258 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5259
5260 rval = QLA_SUCCESS;
5261
5262 /* Determine NVRAM starting address. */
5263 ha->nvram_size = sizeof(*nv);
5264 ha->nvram_base = 0;
5265 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
5266 if ((rd_reg_word(®->ctrl_status) >> 14) == 1)
5267 ha->nvram_base = 0x80;
5268
5269 /* Get NVRAM data and calculate checksum. */
5270 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
5271 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
5272 chksum += *ptr++;
5273
5274 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
5275 "Contents of NVRAM.\n");
5276 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
5277 nv, ha->nvram_size);
5278
5279 /* Bad NVRAM data, set defaults parameters. */
5280 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
5281 nv->nvram_version < 1) {
5282 /* Reset NVRAM data. */
5283 ql_log(ql_log_warn, vha, 0x0064,
5284 "Inconsistent NVRAM detected: checksum=%#x id=%.4s version=%#x.\n",
5285 chksum, nv->id, nv->nvram_version);
5286 ql_log(ql_log_warn, vha, 0x0065,
5287 "Falling back to "
5288 "functioning (yet invalid -- WWPN) defaults.\n");
5289
5290 /*
5291 * Set default initialization control block.
5292 */
5293 memset(nv, 0, ha->nvram_size);
5294 nv->parameter_block_version = ICB_VERSION;
5295
5296 if (IS_QLA23XX(ha)) {
5297 nv->firmware_options[0] = BIT_2 | BIT_1;
5298 nv->firmware_options[1] = BIT_7 | BIT_5;
5299 nv->add_firmware_options[0] = BIT_5;
5300 nv->add_firmware_options[1] = BIT_5 | BIT_4;
5301 nv->frame_payload_size = cpu_to_le16(2048);
5302 nv->special_options[1] = BIT_7;
5303 } else if (IS_QLA2200(ha)) {
5304 nv->firmware_options[0] = BIT_2 | BIT_1;
5305 nv->firmware_options[1] = BIT_7 | BIT_5;
5306 nv->add_firmware_options[0] = BIT_5;
5307 nv->add_firmware_options[1] = BIT_5 | BIT_4;
5308 nv->frame_payload_size = cpu_to_le16(1024);
5309 } else if (IS_QLA2100(ha)) {
5310 nv->firmware_options[0] = BIT_3 | BIT_1;
5311 nv->firmware_options[1] = BIT_5;
5312 nv->frame_payload_size = cpu_to_le16(1024);
5313 }
5314
5315 nv->max_iocb_allocation = cpu_to_le16(256);
5316 nv->execution_throttle = cpu_to_le16(16);
5317 nv->retry_count = 8;
5318 nv->retry_delay = 1;
5319
5320 nv->port_name[0] = 33;
5321 nv->port_name[3] = 224;
5322 nv->port_name[4] = 139;
5323
5324 qla2xxx_nvram_wwn_from_ofw(vha, nv);
5325
5326 nv->login_timeout = 4;
5327
5328 /*
5329 * Set default host adapter parameters
5330 */
5331 nv->host_p[1] = BIT_2;
5332 nv->reset_delay = 5;
5333 nv->port_down_retry_count = 8;
5334 nv->max_luns_per_target = cpu_to_le16(8);
5335 nv->link_down_timeout = 60;
5336
5337 rval = 1;
5338 }
5339
5340 /* Reset Initialization control block */
5341 memset(icb, 0, ha->init_cb_size);
5342
5343 /*
5344 * Setup driver NVRAM options.
5345 */
5346 nv->firmware_options[0] |= (BIT_6 | BIT_1);
5347 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
5348 nv->firmware_options[1] |= (BIT_5 | BIT_0);
5349 nv->firmware_options[1] &= ~BIT_4;
5350
5351 if (IS_QLA23XX(ha)) {
5352 nv->firmware_options[0] |= BIT_2;
5353 nv->firmware_options[0] &= ~BIT_3;
5354 nv->special_options[0] &= ~BIT_6;
5355 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
5356
5357 if (IS_QLA2300(ha)) {
5358 if (ha->fb_rev == FPM_2310) {
5359 strcpy(ha->model_number, "QLA2310");
5360 } else {
5361 strcpy(ha->model_number, "QLA2300");
5362 }
5363 } else {
5364 qla2x00_set_model_info(vha, nv->model_number,
5365 sizeof(nv->model_number), "QLA23xx");
5366 }
5367 } else if (IS_QLA2200(ha)) {
5368 nv->firmware_options[0] |= BIT_2;
5369 /*
5370 * 'Point-to-point preferred, else loop' is not a safe
5371 * connection mode setting.
5372 */
5373 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
5374 (BIT_5 | BIT_4)) {
5375 /* Force 'loop preferred, else point-to-point'. */
5376 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
5377 nv->add_firmware_options[0] |= BIT_5;
5378 }
5379 strcpy(ha->model_number, "QLA22xx");
5380 } else /*if (IS_QLA2100(ha))*/ {
5381 strcpy(ha->model_number, "QLA2100");
5382 }
5383
5384 /*
5385 * Copy over NVRAM RISC parameter block to initialization control block.
5386 */
5387 dptr1 = (uint8_t *)icb;
5388 dptr2 = (uint8_t *)&nv->parameter_block_version;
5389 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
5390 while (cnt--)
5391 *dptr1++ = *dptr2++;
5392
5393 /* Copy 2nd half. */
5394 dptr1 = (uint8_t *)icb->add_firmware_options;
5395 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
5396 while (cnt--)
5397 *dptr1++ = *dptr2++;
5398 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
5399 /* Use alternate WWN? */
5400 if (nv->host_p[1] & BIT_7) {
5401 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5402 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5403 }
5404
5405 /* Prepare nodename */
5406 if ((icb->firmware_options[1] & BIT_6) == 0) {
5407 /*
5408 * Firmware will apply the following mask if the nodename was
5409 * not provided.
5410 */
5411 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5412 icb->node_name[0] &= 0xF0;
5413 }
5414
5415 /*
5416 * Set host adapter parameters.
5417 */
5418
5419 /*
5420 * BIT_7 in the host-parameters section allows for modification to
5421 * internal driver logging.
5422 */
5423 if (nv->host_p[0] & BIT_7)
5424 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
5425 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
5426 /* Always load RISC code on non ISP2[12]00 chips. */
5427 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
5428 ha->flags.disable_risc_code_load = 0;
5429 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
5430 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
5431 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
5432 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
5433 ha->flags.disable_serdes = 0;
5434
5435 ha->operating_mode =
5436 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
5437
5438 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
5439 sizeof(ha->fw_seriallink_options));
5440
5441 /* save HBA serial number */
5442 ha->serial0 = icb->port_name[5];
5443 ha->serial1 = icb->port_name[6];
5444 ha->serial2 = icb->port_name[7];
5445 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5446 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5447
5448 icb->execution_throttle = cpu_to_le16(0xFFFF);
5449
5450 ha->retry_count = nv->retry_count;
5451
5452 /* Set minimum login_timeout to 4 seconds. */
5453 if (nv->login_timeout != ql2xlogintimeout)
5454 nv->login_timeout = ql2xlogintimeout;
5455 if (nv->login_timeout < 4)
5456 nv->login_timeout = 4;
5457 ha->login_timeout = nv->login_timeout;
5458
5459 /* Set minimum RATOV to 100 tenths of a second. */
5460 ha->r_a_tov = 100;
5461
5462 ha->loop_reset_delay = nv->reset_delay;
5463
5464 /* Link Down Timeout = 0:
5465 *
5466 * When Port Down timer expires we will start returning
5467 * I/O's to OS with "DID_NO_CONNECT".
5468 *
5469 * Link Down Timeout != 0:
5470 *
5471 * The driver waits for the link to come up after link down
5472 * before returning I/Os to OS with "DID_NO_CONNECT".
5473 */
5474 if (nv->link_down_timeout == 0) {
5475 ha->loop_down_abort_time =
5476 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5477 } else {
5478 ha->link_down_timeout = nv->link_down_timeout;
5479 ha->loop_down_abort_time =
5480 (LOOP_DOWN_TIME - ha->link_down_timeout);
5481 }
5482
5483 /*
5484 * Need enough time to try and get the port back.
5485 */
5486 ha->port_down_retry_count = nv->port_down_retry_count;
5487 if (qlport_down_retry)
5488 ha->port_down_retry_count = qlport_down_retry;
5489 /* Set login_retry_count */
5490 ha->login_retry_count = nv->retry_count;
5491 if (ha->port_down_retry_count == nv->port_down_retry_count &&
5492 ha->port_down_retry_count > 3)
5493 ha->login_retry_count = ha->port_down_retry_count;
5494 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5495 ha->login_retry_count = ha->port_down_retry_count;
5496 if (ql2xloginretrycount)
5497 ha->login_retry_count = ql2xloginretrycount;
5498
5499 icb->lun_enables = cpu_to_le16(0);
5500 icb->command_resource_count = 0;
5501 icb->immediate_notify_resource_count = 0;
5502 icb->timeout = cpu_to_le16(0);
5503
5504 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5505 /* Enable RIO */
5506 icb->firmware_options[0] &= ~BIT_3;
5507 icb->add_firmware_options[0] &=
5508 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
5509 icb->add_firmware_options[0] |= BIT_2;
5510 icb->response_accumulation_timer = 3;
5511 icb->interrupt_delay_timer = 5;
5512
5513 vha->flags.process_response_queue = 1;
5514 } else {
5515 /* Enable ZIO. */
5516 if (!vha->flags.init_done) {
5517 ha->zio_mode = icb->add_firmware_options[0] &
5518 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5519 ha->zio_timer = icb->interrupt_delay_timer ?
5520 icb->interrupt_delay_timer : 2;
5521 }
5522 icb->add_firmware_options[0] &=
5523 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
5524 vha->flags.process_response_queue = 0;
5525 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5526 ha->zio_mode = QLA_ZIO_MODE_6;
5527
5528 ql_log(ql_log_info, vha, 0x0068,
5529 "ZIO mode %d enabled; timer delay (%d us).\n",
5530 ha->zio_mode, ha->zio_timer * 100);
5531
5532 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
5533 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
5534 vha->flags.process_response_queue = 1;
5535 }
5536 }
5537
5538 if (rval) {
5539 ql_log(ql_log_warn, vha, 0x0069,
5540 "NVRAM configuration failed.\n");
5541 }
5542 return (rval);
5543 }
5544
qla2x00_set_fcport_state(fc_port_t * fcport,int state)5545 void qla2x00_set_fcport_state(fc_port_t *fcport, int state)
5546 {
5547 int old_state;
5548
5549 old_state = atomic_read(&fcport->state);
5550 atomic_set(&fcport->state, state);
5551
5552 /* Don't print state transitions during initial allocation of fcport */
5553 if (old_state && old_state != state) {
5554 ql_dbg(ql_dbg_disc, fcport->vha, 0x207d,
5555 "FCPort %8phC state transitioned from %s to %s - portid=%02x%02x%02x.\n",
5556 fcport->port_name, port_state_str[old_state],
5557 port_state_str[state], fcport->d_id.b.domain,
5558 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5559 }
5560 }
5561
5562 /**
5563 * qla2x00_alloc_fcport() - Allocate a generic fcport.
5564 * @vha: HA context
5565 * @flags: allocation flags
5566 *
5567 * Returns a pointer to the allocated fcport, or NULL, if none available.
5568 */
5569 fc_port_t *
qla2x00_alloc_fcport(scsi_qla_host_t * vha,gfp_t flags)5570 qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
5571 {
5572 fc_port_t *fcport;
5573
5574 fcport = kzalloc_obj(fc_port_t, flags);
5575 if (!fcport)
5576 return NULL;
5577
5578 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
5579 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
5580 flags);
5581 if (!fcport->ct_desc.ct_sns) {
5582 ql_log(ql_log_warn, vha, 0xd049,
5583 "Failed to allocate ct_sns request.\n");
5584 kfree(fcport);
5585 return NULL;
5586 }
5587
5588 /* Setup fcport template structure. */
5589 fcport->vha = vha;
5590 fcport->port_type = FCT_UNKNOWN;
5591 fcport->loop_id = FC_NO_LOOP_ID;
5592 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
5593 fcport->supported_classes = FC_COS_UNSPECIFIED;
5594 fcport->fp_speed = PORT_SPEED_UNKNOWN;
5595
5596 fcport->disc_state = DSC_DELETED;
5597 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
5598 fcport->deleted = QLA_SESS_DELETED;
5599 fcport->login_retry = vha->hw->login_retry_count;
5600 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5601 fcport->logout_on_delete = 1;
5602 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME;
5603 fcport->tgt_short_link_down_cnt = 0;
5604 fcport->dev_loss_tmo = 0;
5605
5606 if (!fcport->ct_desc.ct_sns) {
5607 ql_log(ql_log_warn, vha, 0xd049,
5608 "Failed to allocate ct_sns request.\n");
5609 kfree(fcport);
5610 return NULL;
5611 }
5612
5613 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
5614 INIT_WORK(&fcport->free_work, qlt_free_session_done);
5615 INIT_WORK(&fcport->reg_work, qla_register_fcport_fn);
5616 INIT_LIST_HEAD(&fcport->gnl_entry);
5617 INIT_LIST_HEAD(&fcport->list);
5618 INIT_LIST_HEAD(&fcport->unsol_ctx_head);
5619
5620 INIT_LIST_HEAD(&fcport->sess_cmd_list);
5621 spin_lock_init(&fcport->sess_cmd_lock);
5622
5623 spin_lock_init(&fcport->edif.sa_list_lock);
5624 INIT_LIST_HEAD(&fcport->edif.tx_sa_list);
5625 INIT_LIST_HEAD(&fcport->edif.rx_sa_list);
5626
5627 spin_lock_init(&fcport->edif.indx_list_lock);
5628 INIT_LIST_HEAD(&fcport->edif.edif_indx_list);
5629
5630 return fcport;
5631 }
5632
5633 void
qla2x00_free_fcport(fc_port_t * fcport)5634 qla2x00_free_fcport(fc_port_t *fcport)
5635 {
5636 if (fcport->ct_desc.ct_sns) {
5637 dma_free_coherent(&fcport->vha->hw->pdev->dev,
5638 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
5639 fcport->ct_desc.ct_sns_dma);
5640
5641 fcport->ct_desc.ct_sns = NULL;
5642 }
5643
5644 qla_edif_flush_sa_ctl_lists(fcport);
5645 list_del(&fcport->list);
5646 qla2x00_clear_loop_id(fcport);
5647
5648 qla_edif_list_del(fcport);
5649
5650 kfree(fcport);
5651 }
5652
qla_get_login_template(scsi_qla_host_t * vha)5653 static void qla_get_login_template(scsi_qla_host_t *vha)
5654 {
5655 struct qla_hw_data *ha = vha->hw;
5656 int rval;
5657 u32 *bp, sz;
5658 __be32 *q;
5659
5660 memset(ha->init_cb, 0, ha->init_cb_size);
5661 sz = min_t(int, sizeof(struct fc_els_flogi), ha->init_cb_size);
5662 rval = qla24xx_get_port_login_templ(vha, ha->init_cb_dma,
5663 ha->init_cb, sz);
5664 if (rval != QLA_SUCCESS) {
5665 ql_dbg(ql_dbg_init, vha, 0x00d1,
5666 "PLOGI ELS param read fail.\n");
5667 return;
5668 }
5669 q = (__be32 *)&ha->plogi_els_payld.fl_csp;
5670
5671 bp = (uint32_t *)ha->init_cb;
5672 cpu_to_be32_array(q, bp, sz / 4);
5673 ha->flags.plogi_template_valid = 1;
5674 }
5675
5676 /*
5677 * qla2x00_configure_loop
5678 * Updates Fibre Channel Device Database with what is actually on loop.
5679 *
5680 * Input:
5681 * ha = adapter block pointer.
5682 *
5683 * Returns:
5684 * 0 = success.
5685 * 1 = error.
5686 * 2 = database was full and device was not configured.
5687 */
5688 static int
qla2x00_configure_loop(scsi_qla_host_t * vha)5689 qla2x00_configure_loop(scsi_qla_host_t *vha)
5690 {
5691 int rval;
5692 unsigned long flags, save_flags;
5693 struct qla_hw_data *ha = vha->hw;
5694
5695 rval = QLA_SUCCESS;
5696
5697 /* Get Initiator ID */
5698 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
5699 rval = qla2x00_configure_hba(vha);
5700 if (rval != QLA_SUCCESS) {
5701 ql_dbg(ql_dbg_disc, vha, 0x2013,
5702 "Unable to configure HBA.\n");
5703 return (rval);
5704 }
5705 }
5706
5707 save_flags = flags = vha->dpc_flags;
5708 ql_dbg(ql_dbg_disc, vha, 0x2014,
5709 "Configure loop -- dpc flags = 0x%lx.\n", flags);
5710
5711 /*
5712 * If we have both an RSCN and PORT UPDATE pending then handle them
5713 * both at the same time.
5714 */
5715 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5716 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
5717
5718 qla2x00_get_data_rate(vha);
5719 qla_get_login_template(vha);
5720
5721 /* Determine what we need to do */
5722 if ((ha->current_topology == ISP_CFG_FL ||
5723 ha->current_topology == ISP_CFG_F) &&
5724 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
5725
5726 set_bit(RSCN_UPDATE, &flags);
5727 clear_bit(LOCAL_LOOP_UPDATE, &flags);
5728
5729 } else if (ha->current_topology == ISP_CFG_NL ||
5730 ha->current_topology == ISP_CFG_N) {
5731 clear_bit(RSCN_UPDATE, &flags);
5732 set_bit(LOCAL_LOOP_UPDATE, &flags);
5733 } else if (!vha->flags.online ||
5734 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
5735 set_bit(RSCN_UPDATE, &flags);
5736 set_bit(LOCAL_LOOP_UPDATE, &flags);
5737 }
5738
5739 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
5740 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
5741 ql_dbg(ql_dbg_disc, vha, 0x2015,
5742 "Loop resync needed, failing.\n");
5743 rval = QLA_FUNCTION_FAILED;
5744 } else
5745 rval = qla2x00_configure_local_loop(vha);
5746 }
5747
5748 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
5749 if (LOOP_TRANSITION(vha)) {
5750 ql_dbg(ql_dbg_disc, vha, 0x2099,
5751 "Needs RSCN update and loop transition.\n");
5752 rval = QLA_FUNCTION_FAILED;
5753 }
5754 else
5755 rval = qla2x00_configure_fabric(vha);
5756 }
5757
5758 if (rval == QLA_SUCCESS) {
5759 if (atomic_read(&vha->loop_down_timer) ||
5760 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
5761 rval = QLA_FUNCTION_FAILED;
5762 } else {
5763 atomic_set(&vha->loop_state, LOOP_READY);
5764 ql_dbg(ql_dbg_disc, vha, 0x2069,
5765 "LOOP READY.\n");
5766 ha->flags.fw_init_done = 1;
5767
5768 /*
5769 * use link up to wake up app to get ready for
5770 * authentication.
5771 */
5772 if (ha->flags.edif_enabled && DBELL_INACTIVE(vha))
5773 qla2x00_post_aen_work(vha, FCH_EVT_LINKUP,
5774 ha->link_data_rate);
5775
5776 /*
5777 * Process any ATIO queue entries that came in
5778 * while we weren't online.
5779 */
5780 if (qla_tgt_mode_enabled(vha) ||
5781 qla_dual_mode_enabled(vha)) {
5782 spin_lock_irqsave(&ha->tgt.atio_lock, flags);
5783 qlt_24xx_process_atio_queue(vha, 0);
5784 spin_unlock_irqrestore(&ha->tgt.atio_lock,
5785 flags);
5786 }
5787 }
5788 }
5789
5790 if (rval) {
5791 ql_dbg(ql_dbg_disc, vha, 0x206a,
5792 "%s *** FAILED ***.\n", __func__);
5793 } else {
5794 ql_dbg(ql_dbg_disc, vha, 0x206b,
5795 "%s: exiting normally. local port wwpn %8phN id %06x)\n",
5796 __func__, vha->port_name, vha->d_id.b24);
5797 }
5798
5799 /* Restore state if a resync event occurred during processing */
5800 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
5801 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
5802 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5803 if (test_bit(RSCN_UPDATE, &save_flags)) {
5804 set_bit(RSCN_UPDATE, &vha->dpc_flags);
5805 }
5806 }
5807
5808 return (rval);
5809 }
5810
qla2x00_configure_n2n_loop(scsi_qla_host_t * vha)5811 static int qla2x00_configure_n2n_loop(scsi_qla_host_t *vha)
5812 {
5813 unsigned long flags;
5814 fc_port_t *fcport;
5815
5816 ql_dbg(ql_dbg_disc, vha, 0x206a, "%s %d.\n", __func__, __LINE__);
5817
5818 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags))
5819 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5820
5821 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5822 if (fcport->n2n_flag) {
5823 qla24xx_fcport_handle_login(vha, fcport);
5824 return QLA_SUCCESS;
5825 }
5826 }
5827
5828 spin_lock_irqsave(&vha->work_lock, flags);
5829 vha->scan.scan_retry++;
5830 spin_unlock_irqrestore(&vha->work_lock, flags);
5831
5832 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) {
5833 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5834 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5835 }
5836 return QLA_FUNCTION_FAILED;
5837 }
5838
5839 static void
qla_reinitialize_link(scsi_qla_host_t * vha)5840 qla_reinitialize_link(scsi_qla_host_t *vha)
5841 {
5842 int rval;
5843
5844 atomic_set(&vha->loop_state, LOOP_DOWN);
5845 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
5846 rval = qla2x00_full_login_lip(vha);
5847 if (rval == QLA_SUCCESS) {
5848 ql_dbg(ql_dbg_disc, vha, 0xd050, "Link reinitialized\n");
5849 } else {
5850 ql_dbg(ql_dbg_disc, vha, 0xd051,
5851 "Link reinitialization failed (%d)\n", rval);
5852 }
5853 }
5854
5855 /*
5856 * qla2x00_configure_local_loop
5857 * Updates Fibre Channel Device Database with local loop devices.
5858 *
5859 * Input:
5860 * ha = adapter block pointer.
5861 *
5862 * Returns:
5863 * 0 = success.
5864 */
5865 static int
qla2x00_configure_local_loop(scsi_qla_host_t * vha)5866 qla2x00_configure_local_loop(scsi_qla_host_t *vha)
5867 {
5868 int rval, rval2;
5869 int found;
5870 fc_port_t *fcport, *new_fcport;
5871 uint16_t index;
5872 uint16_t entries;
5873 struct gid_list_info *gid;
5874 uint16_t loop_id;
5875 uint8_t domain, area, al_pa;
5876 struct qla_hw_data *ha = vha->hw;
5877 unsigned long flags;
5878
5879 /* Inititae N2N login. */
5880 if (N2N_TOPO(ha))
5881 return qla2x00_configure_n2n_loop(vha);
5882
5883 new_fcport = NULL;
5884 entries = MAX_FIBRE_DEVICES_LOOP;
5885
5886 /* Get list of logged in devices. */
5887 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
5888 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
5889 &entries);
5890 if (rval != QLA_SUCCESS)
5891 goto err;
5892
5893 ql_dbg(ql_dbg_disc, vha, 0x2011,
5894 "Entries in ID list (%d).\n", entries);
5895 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
5896 ha->gid_list, entries * sizeof(*ha->gid_list));
5897
5898 if (entries == 0) {
5899 spin_lock_irqsave(&vha->work_lock, flags);
5900 vha->scan.scan_retry++;
5901 spin_unlock_irqrestore(&vha->work_lock, flags);
5902
5903 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) {
5904 u8 loop_map_entries = 0;
5905 int rc;
5906
5907 rc = qla2x00_get_fcal_position_map(vha, NULL,
5908 &loop_map_entries);
5909 if (rc == QLA_SUCCESS && loop_map_entries > 1) {
5910 /*
5911 * There are devices that are still not logged
5912 * in. Reinitialize to give them a chance.
5913 */
5914 qla_reinitialize_link(vha);
5915 return QLA_FUNCTION_FAILED;
5916 }
5917 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5918 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5919 }
5920 } else {
5921 vha->scan.scan_retry = 0;
5922 }
5923
5924 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5925 fcport->scan_state = QLA_FCPORT_SCAN;
5926 }
5927
5928 /* Allocate temporary fcport for any new fcports discovered. */
5929 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5930 if (new_fcport == NULL) {
5931 ql_log(ql_log_warn, vha, 0x2012,
5932 "Memory allocation failed for fcport.\n");
5933 rval = QLA_MEMORY_ALLOC_FAILED;
5934 goto err;
5935 }
5936 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
5937
5938 /* Add devices to port list. */
5939 gid = ha->gid_list;
5940 for (index = 0; index < entries; index++) {
5941 domain = gid->domain;
5942 area = gid->area;
5943 al_pa = gid->al_pa;
5944 if (IS_QLA2100(ha) || IS_QLA2200(ha))
5945 loop_id = gid->loop_id_2100;
5946 else
5947 loop_id = le16_to_cpu(gid->loop_id);
5948 gid = (void *)gid + ha->gid_list_info_size;
5949
5950 /* Bypass reserved domain fields. */
5951 if ((domain & 0xf0) == 0xf0)
5952 continue;
5953
5954 /* Bypass if not same domain and area of adapter. */
5955 if (area && domain && ((area != vha->d_id.b.area) ||
5956 (domain != vha->d_id.b.domain)) &&
5957 (ha->current_topology == ISP_CFG_NL))
5958 continue;
5959
5960
5961 /* Bypass invalid local loop ID. */
5962 if (loop_id > LAST_LOCAL_LOOP_ID)
5963 continue;
5964
5965 memset(new_fcport->port_name, 0, WWN_SIZE);
5966
5967 /* Fill in member data. */
5968 new_fcport->d_id.b.domain = domain;
5969 new_fcport->d_id.b.area = area;
5970 new_fcport->d_id.b.al_pa = al_pa;
5971 new_fcport->loop_id = loop_id;
5972 new_fcport->scan_state = QLA_FCPORT_FOUND;
5973
5974 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
5975 if (rval2 != QLA_SUCCESS) {
5976 ql_dbg(ql_dbg_disc, vha, 0x2097,
5977 "Failed to retrieve fcport information "
5978 "-- get_port_database=%x, loop_id=0x%04x.\n",
5979 rval2, new_fcport->loop_id);
5980 /* Skip retry if N2N */
5981 if (ha->current_topology != ISP_CFG_N) {
5982 ql_dbg(ql_dbg_disc, vha, 0x2105,
5983 "Scheduling resync.\n");
5984 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5985 continue;
5986 }
5987 }
5988
5989 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5990 /* Check for matching device in port list. */
5991 found = 0;
5992 fcport = NULL;
5993 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5994 if (memcmp(new_fcport->port_name, fcport->port_name,
5995 WWN_SIZE))
5996 continue;
5997
5998 fcport->flags &= ~FCF_FABRIC_DEVICE;
5999 fcport->loop_id = new_fcport->loop_id;
6000 fcport->port_type = new_fcport->port_type;
6001 fcport->d_id.b24 = new_fcport->d_id.b24;
6002 memcpy(fcport->node_name, new_fcport->node_name,
6003 WWN_SIZE);
6004 fcport->scan_state = QLA_FCPORT_FOUND;
6005 if (fcport->login_retry == 0) {
6006 fcport->login_retry = vha->hw->login_retry_count;
6007 ql_dbg(ql_dbg_disc, vha, 0x2135,
6008 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
6009 fcport->port_name, fcport->loop_id,
6010 fcport->login_retry);
6011 }
6012 found++;
6013 break;
6014 }
6015
6016 if (!found) {
6017 /* New device, add to fcports list. */
6018 list_add_tail(&new_fcport->list, &vha->vp_fcports);
6019
6020 /* Allocate a new replacement fcport. */
6021 fcport = new_fcport;
6022
6023 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
6024
6025 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
6026
6027 if (new_fcport == NULL) {
6028 ql_log(ql_log_warn, vha, 0xd031,
6029 "Failed to allocate memory for fcport.\n");
6030 rval = QLA_MEMORY_ALLOC_FAILED;
6031 goto err;
6032 }
6033 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
6034 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
6035 }
6036
6037 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
6038
6039 /* Base iIDMA settings on HBA port speed. */
6040 fcport->fp_speed = ha->link_data_rate;
6041 }
6042
6043 list_for_each_entry(fcport, &vha->vp_fcports, list) {
6044 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
6045 break;
6046
6047 if (fcport->scan_state == QLA_FCPORT_SCAN) {
6048 if ((qla_dual_mode_enabled(vha) ||
6049 qla_ini_mode_enabled(vha)) &&
6050 atomic_read(&fcport->state) == FCS_ONLINE) {
6051 qla2x00_mark_device_lost(vha, fcport,
6052 ql2xplogiabsentdevice);
6053 if (fcport->loop_id != FC_NO_LOOP_ID &&
6054 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
6055 fcport->port_type != FCT_INITIATOR &&
6056 fcport->port_type != FCT_BROADCAST) {
6057 ql_dbg(ql_dbg_disc, vha, 0x20f0,
6058 "%s %d %8phC post del sess\n",
6059 __func__, __LINE__,
6060 fcport->port_name);
6061
6062 qlt_schedule_sess_for_deletion(fcport);
6063 continue;
6064 }
6065 }
6066 }
6067
6068 if (fcport->scan_state == QLA_FCPORT_FOUND)
6069 qla24xx_fcport_handle_login(vha, fcport);
6070 }
6071
6072 qla2x00_free_fcport(new_fcport);
6073
6074 return rval;
6075
6076 err:
6077 ql_dbg(ql_dbg_disc, vha, 0x2098,
6078 "Configure local loop error exit: rval=%x.\n", rval);
6079 return rval;
6080 }
6081
6082 static void
qla2x00_iidma_fcport(scsi_qla_host_t * vha,fc_port_t * fcport)6083 qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
6084 {
6085 int rval;
6086 uint16_t mb[MAILBOX_REGISTER_COUNT];
6087 struct qla_hw_data *ha = vha->hw;
6088
6089 if (!IS_IIDMA_CAPABLE(ha))
6090 return;
6091
6092 if (atomic_read(&fcport->state) != FCS_ONLINE)
6093 return;
6094
6095 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
6096 fcport->fp_speed > ha->link_data_rate ||
6097 !ha->flags.gpsc_supported)
6098 return;
6099
6100 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
6101 mb);
6102 if (rval != QLA_SUCCESS) {
6103 ql_dbg(ql_dbg_disc, vha, 0x2004,
6104 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
6105 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
6106 } else {
6107 ql_dbg(ql_dbg_disc, vha, 0x2005,
6108 "iIDMA adjusted to %s GB/s (%X) on %8phN.\n",
6109 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
6110 fcport->fp_speed, fcport->port_name);
6111 }
6112 }
6113
qla_do_iidma_work(struct scsi_qla_host * vha,fc_port_t * fcport)6114 void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
6115 {
6116 qla2x00_iidma_fcport(vha, fcport);
6117 qla24xx_update_fcport_fcp_prio(vha, fcport);
6118 }
6119
qla_post_iidma_work(struct scsi_qla_host * vha,fc_port_t * fcport)6120 int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
6121 {
6122 struct qla_work_evt *e;
6123
6124 e = qla2x00_alloc_work(vha, QLA_EVT_IIDMA);
6125 if (!e)
6126 return QLA_FUNCTION_FAILED;
6127
6128 e->u.fcport.fcport = fcport;
6129 return qla2x00_post_work(vha, e);
6130 }
6131
6132 /* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
6133 static void
qla2x00_reg_remote_port(scsi_qla_host_t * vha,fc_port_t * fcport)6134 qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
6135 {
6136 struct fc_rport_identifiers rport_ids;
6137 struct fc_rport *rport;
6138 unsigned long flags;
6139
6140 if (atomic_read(&fcport->state) == FCS_ONLINE)
6141 return;
6142
6143 rport_ids.node_name = wwn_to_u64(fcport->node_name);
6144 rport_ids.port_name = wwn_to_u64(fcport->port_name);
6145 rport_ids.port_id = fcport->d_id.b.domain << 16 |
6146 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
6147 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
6148 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
6149 if (!rport) {
6150 ql_log(ql_log_warn, vha, 0x2006,
6151 "Unable to allocate fc remote port.\n");
6152 return;
6153 }
6154
6155 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
6156 *((fc_port_t **)rport->dd_data) = fcport;
6157 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
6158 fcport->dev_loss_tmo = rport->dev_loss_tmo;
6159
6160 rport->supported_classes = fcport->supported_classes;
6161
6162 rport_ids.roles = FC_PORT_ROLE_UNKNOWN;
6163 if (fcport->port_type == FCT_INITIATOR)
6164 rport_ids.roles |= FC_PORT_ROLE_FCP_INITIATOR;
6165 if (fcport->port_type == FCT_TARGET)
6166 rport_ids.roles |= FC_PORT_ROLE_FCP_TARGET;
6167 if (fcport->port_type & FCT_NVME_INITIATOR)
6168 rport_ids.roles |= FC_PORT_ROLE_NVME_INITIATOR;
6169 if (fcport->port_type & FCT_NVME_TARGET)
6170 rport_ids.roles |= FC_PORT_ROLE_NVME_TARGET;
6171 if (fcport->port_type & FCT_NVME_DISCOVERY)
6172 rport_ids.roles |= FC_PORT_ROLE_NVME_DISCOVERY;
6173
6174 fc_remote_port_rolechg(rport, rport_ids.roles);
6175
6176 ql_dbg(ql_dbg_disc, vha, 0x20ee,
6177 "%s: %8phN. rport %ld:0:%d (%p) is %s mode\n",
6178 __func__, fcport->port_name, vha->host_no,
6179 rport->scsi_target_id, rport,
6180 (fcport->port_type == FCT_TARGET) ? "tgt" :
6181 ((fcport->port_type & FCT_NVME) ? "nvme" : "ini"));
6182 }
6183
6184 /*
6185 * qla2x00_update_fcport
6186 * Updates device on list.
6187 *
6188 * Input:
6189 * ha = adapter block pointer.
6190 * fcport = port structure pointer.
6191 *
6192 * Return:
6193 * 0 - Success
6194 * BIT_0 - error
6195 *
6196 * Context:
6197 * Kernel context.
6198 */
6199 void
qla2x00_update_fcport(scsi_qla_host_t * vha,fc_port_t * fcport)6200 qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
6201 {
6202 unsigned long flags;
6203
6204 if (IS_SW_RESV_ADDR(fcport->d_id))
6205 return;
6206
6207 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n",
6208 __func__, fcport->port_name);
6209
6210 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
6211 fcport->login_retry = vha->hw->login_retry_count;
6212 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6213
6214 spin_lock_irqsave(&vha->work_lock, flags);
6215 fcport->deleted = 0;
6216 spin_unlock_irqrestore(&vha->work_lock, flags);
6217
6218 if (vha->hw->current_topology == ISP_CFG_NL)
6219 fcport->logout_on_delete = 0;
6220 else
6221 fcport->logout_on_delete = 1;
6222 fcport->n2n_chip_reset = fcport->n2n_link_reset_cnt = 0;
6223
6224 if (fcport->tgt_link_down_time < fcport->dev_loss_tmo) {
6225 fcport->tgt_short_link_down_cnt++;
6226 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME;
6227 }
6228
6229 switch (vha->hw->current_topology) {
6230 case ISP_CFG_N:
6231 case ISP_CFG_NL:
6232 fcport->keep_nport_handle = 1;
6233 break;
6234 default:
6235 break;
6236 }
6237
6238 qla2x00_iidma_fcport(vha, fcport);
6239
6240 qla2x00_dfs_create_rport(vha, fcport);
6241
6242 qla24xx_update_fcport_fcp_prio(vha, fcport);
6243
6244 switch (vha->host->active_mode) {
6245 case MODE_INITIATOR:
6246 qla2x00_reg_remote_port(vha, fcport);
6247 break;
6248 case MODE_TARGET:
6249 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
6250 !vha->vha_tgt.qla_tgt->tgt_stopped)
6251 qlt_fc_port_added(vha, fcport);
6252 break;
6253 case MODE_DUAL:
6254 qla2x00_reg_remote_port(vha, fcport);
6255 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
6256 !vha->vha_tgt.qla_tgt->tgt_stopped)
6257 qlt_fc_port_added(vha, fcport);
6258 break;
6259 default:
6260 break;
6261 }
6262
6263 if (NVME_TARGET(vha->hw, fcport))
6264 qla_nvme_register_remote(vha, fcport);
6265
6266 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
6267
6268 if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) {
6269 if (fcport->id_changed) {
6270 fcport->id_changed = 0;
6271 ql_dbg(ql_dbg_disc, vha, 0x20d7,
6272 "%s %d %8phC post gfpnid fcp_cnt %d\n",
6273 __func__, __LINE__, fcport->port_name,
6274 vha->fcport_count);
6275 qla24xx_post_gfpnid_work(vha, fcport);
6276 } else {
6277 ql_dbg(ql_dbg_disc, vha, 0x20d7,
6278 "%s %d %8phC post gpsc fcp_cnt %d\n",
6279 __func__, __LINE__, fcport->port_name,
6280 vha->fcport_count);
6281 qla24xx_post_gpsc_work(vha, fcport);
6282 }
6283 }
6284
6285 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE);
6286 }
6287
qla_register_fcport_fn(struct work_struct * work)6288 void qla_register_fcport_fn(struct work_struct *work)
6289 {
6290 fc_port_t *fcport = container_of(work, struct fc_port, reg_work);
6291 u32 rscn_gen = fcport->rscn_gen;
6292 u16 data[2];
6293
6294 if (IS_SW_RESV_ADDR(fcport->d_id))
6295 return;
6296
6297 qla2x00_update_fcport(fcport->vha, fcport);
6298
6299 ql_dbg(ql_dbg_disc, fcport->vha, 0x911e,
6300 "%s rscn gen %d/%d next DS %d\n", __func__,
6301 rscn_gen, fcport->rscn_gen, fcport->next_disc_state);
6302
6303 if (rscn_gen != fcport->rscn_gen) {
6304 /* RSCN(s) came in while registration */
6305 switch (fcport->next_disc_state) {
6306 case DSC_DELETE_PEND:
6307 qlt_schedule_sess_for_deletion(fcport);
6308 break;
6309 case DSC_ADISC:
6310 data[0] = data[1] = 0;
6311 qla2x00_post_async_adisc_work(fcport->vha, fcport,
6312 data);
6313 break;
6314 default:
6315 break;
6316 }
6317 }
6318 }
6319
6320 /*
6321 * qla2x00_configure_fabric
6322 * Setup SNS devices with loop ID's.
6323 *
6324 * Input:
6325 * ha = adapter block pointer.
6326 *
6327 * Returns:
6328 * 0 = success.
6329 * BIT_0 = error
6330 */
6331 static int
qla2x00_configure_fabric(scsi_qla_host_t * vha)6332 qla2x00_configure_fabric(scsi_qla_host_t *vha)
6333 {
6334 int rval;
6335 fc_port_t *fcport;
6336 uint16_t mb[MAILBOX_REGISTER_COUNT];
6337 uint16_t loop_id;
6338 struct qla_hw_data *ha = vha->hw;
6339 int discovery_gen;
6340
6341 /* If FL port exists, then SNS is present */
6342 if (IS_FWI2_CAPABLE(ha))
6343 loop_id = NPH_F_PORT;
6344 else
6345 loop_id = SNS_FL_PORT;
6346 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
6347 if (rval != QLA_SUCCESS) {
6348 ql_dbg(ql_dbg_disc, vha, 0x20a0,
6349 "MBX_GET_PORT_NAME failed, No FL Port.\n");
6350
6351 vha->device_flags &= ~SWITCH_FOUND;
6352 return (QLA_SUCCESS);
6353 }
6354 vha->device_flags |= SWITCH_FOUND;
6355
6356 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_port_name, 0);
6357 if (rval != QLA_SUCCESS)
6358 ql_dbg(ql_dbg_disc, vha, 0x20ff,
6359 "Failed to get Fabric Port Name\n");
6360
6361 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
6362 rval = qla2x00_send_change_request(vha, 0x3, 0);
6363 if (rval != QLA_SUCCESS)
6364 ql_log(ql_log_warn, vha, 0x121,
6365 "Failed to enable receiving of RSCN requests: 0x%x.\n",
6366 rval);
6367 }
6368
6369 do {
6370 qla2x00_mgmt_svr_login(vha);
6371
6372 /* Ensure we are logged into the SNS. */
6373 loop_id = NPH_SNS_LID(ha);
6374 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
6375 0xfc, mb, BIT_1|BIT_0);
6376 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
6377 ql_dbg(ql_dbg_disc, vha, 0x20a1,
6378 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
6379 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
6380 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
6381 return rval;
6382 }
6383
6384 /* FDMI support. */
6385 if (ql2xfdmienable &&
6386 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
6387 qla2x00_fdmi_register(vha);
6388
6389 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
6390 if (qla2x00_rft_id(vha)) {
6391 /* EMPTY */
6392 ql_dbg(ql_dbg_disc, vha, 0x20a2,
6393 "Register FC-4 TYPE failed.\n");
6394 if (test_bit(LOOP_RESYNC_NEEDED,
6395 &vha->dpc_flags))
6396 break;
6397 }
6398 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
6399 /* EMPTY */
6400 ql_dbg(ql_dbg_disc, vha, 0x209a,
6401 "Register FC-4 Features failed.\n");
6402 if (test_bit(LOOP_RESYNC_NEEDED,
6403 &vha->dpc_flags))
6404 break;
6405 }
6406 if (vha->flags.nvme_enabled) {
6407 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
6408 ql_dbg(ql_dbg_disc, vha, 0x2049,
6409 "Register NVME FC Type Features failed.\n");
6410 }
6411 }
6412 if (qla2x00_rnn_id(vha)) {
6413 /* EMPTY */
6414 ql_dbg(ql_dbg_disc, vha, 0x2104,
6415 "Register Node Name failed.\n");
6416 if (test_bit(LOOP_RESYNC_NEEDED,
6417 &vha->dpc_flags))
6418 break;
6419 } else if (qla2x00_rsnn_nn(vha)) {
6420 /* EMPTY */
6421 ql_dbg(ql_dbg_disc, vha, 0x209b,
6422 "Register Symbolic Node Name failed.\n");
6423 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
6424 break;
6425 }
6426 }
6427
6428
6429 /* Mark the time right before querying FW for connected ports.
6430 * This process is long, asynchronous and by the time it's done,
6431 * collected information might not be accurate anymore. E.g.
6432 * disconnected port might have re-connected and a brand new
6433 * session has been created. In this case session's generation
6434 * will be newer than discovery_gen. */
6435 qlt_do_generation_tick(vha, &discovery_gen);
6436
6437 if (USE_ASYNC_SCAN(ha)) {
6438 /* start of scan begins here */
6439 vha->scan.rscn_gen_end = atomic_read(&vha->rscn_gen);
6440 qla_fab_scan_start(vha);
6441 } else {
6442 list_for_each_entry(fcport, &vha->vp_fcports, list)
6443 fcport->scan_state = QLA_FCPORT_SCAN;
6444
6445 rval = qla2x00_find_all_fabric_devs(vha);
6446 }
6447 if (rval != QLA_SUCCESS)
6448 break;
6449 } while (0);
6450
6451 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
6452 qla_nvme_register_hba(vha);
6453
6454 if (rval)
6455 ql_dbg(ql_dbg_disc, vha, 0x2068,
6456 "Configure fabric error exit rval=%d.\n", rval);
6457
6458 return (rval);
6459 }
6460
6461 /*
6462 * qla2x00_find_all_fabric_devs
6463 *
6464 * Input:
6465 * ha = adapter block pointer.
6466 * dev = database device entry pointer.
6467 *
6468 * Returns:
6469 * 0 = success.
6470 *
6471 * Context:
6472 * Kernel context.
6473 */
6474 static int
qla2x00_find_all_fabric_devs(scsi_qla_host_t * vha)6475 qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
6476 {
6477 int rval;
6478 uint16_t loop_id;
6479 fc_port_t *fcport, *new_fcport;
6480 int found;
6481
6482 sw_info_t *swl;
6483 int swl_idx;
6484 int first_dev, last_dev;
6485 port_id_t wrap = {}, nxt_d_id;
6486 struct qla_hw_data *ha = vha->hw;
6487 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6488 unsigned long flags;
6489
6490 rval = QLA_SUCCESS;
6491
6492 /* Try GID_PT to get device list, else GAN. */
6493 if (!ha->swl)
6494 ha->swl = kzalloc_objs(sw_info_t, ha->max_fibre_devices);
6495 swl = ha->swl;
6496 if (!swl) {
6497 /*EMPTY*/
6498 ql_dbg(ql_dbg_disc, vha, 0x209c,
6499 "GID_PT allocations failed, fallback on GA_NXT.\n");
6500 } else {
6501 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
6502 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
6503 swl = NULL;
6504 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
6505 return rval;
6506 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
6507 swl = NULL;
6508 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
6509 return rval;
6510 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
6511 swl = NULL;
6512 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
6513 return rval;
6514 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
6515 swl = NULL;
6516 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
6517 return rval;
6518 }
6519
6520 /* If other queries succeeded probe for FC-4 type */
6521 if (swl) {
6522 qla2x00_gff_id(vha, swl);
6523 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
6524 return rval;
6525 }
6526 }
6527 swl_idx = 0;
6528
6529 /* Allocate temporary fcport for any new fcports discovered. */
6530 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
6531 if (new_fcport == NULL) {
6532 ql_log(ql_log_warn, vha, 0x209d,
6533 "Failed to allocate memory for fcport.\n");
6534 return (QLA_MEMORY_ALLOC_FAILED);
6535 }
6536 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
6537 /* Set start port ID scan at adapter ID. */
6538 first_dev = 1;
6539 last_dev = 0;
6540
6541 /* Starting free loop ID. */
6542 loop_id = ha->min_external_loopid;
6543 for (; loop_id <= ha->max_loop_id; loop_id++) {
6544 if (qla2x00_is_reserved_id(vha, loop_id))
6545 continue;
6546
6547 if (ha->current_topology == ISP_CFG_FL &&
6548 (atomic_read(&vha->loop_down_timer) ||
6549 LOOP_TRANSITION(vha))) {
6550 atomic_set(&vha->loop_down_timer, 0);
6551 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
6552 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
6553 break;
6554 }
6555
6556 if (swl != NULL) {
6557 if (last_dev) {
6558 wrap.b24 = new_fcport->d_id.b24;
6559 } else {
6560 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
6561 memcpy(new_fcport->node_name,
6562 swl[swl_idx].node_name, WWN_SIZE);
6563 memcpy(new_fcport->port_name,
6564 swl[swl_idx].port_name, WWN_SIZE);
6565 memcpy(new_fcport->fabric_port_name,
6566 swl[swl_idx].fabric_port_name, WWN_SIZE);
6567 new_fcport->fp_speed = swl[swl_idx].fp_speed;
6568 new_fcport->fc4_type = swl[swl_idx].fc4_type;
6569
6570 new_fcport->nvme_flag = 0;
6571 if (vha->flags.nvme_enabled &&
6572 swl[swl_idx].fc4_type & FS_FC4TYPE_NVME) {
6573 ql_log(ql_log_info, vha, 0x2131,
6574 "FOUND: NVME port %8phC as FC Type 28h\n",
6575 new_fcport->port_name);
6576 }
6577
6578 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
6579 last_dev = 1;
6580 }
6581 swl_idx++;
6582 }
6583 } else {
6584 /* Send GA_NXT to the switch */
6585 rval = qla2x00_ga_nxt(vha, new_fcport);
6586 if (rval != QLA_SUCCESS) {
6587 ql_log(ql_log_warn, vha, 0x209e,
6588 "SNS scan failed -- assuming "
6589 "zero-entry result.\n");
6590 rval = QLA_SUCCESS;
6591 break;
6592 }
6593 }
6594
6595 /* If wrap on switch device list, exit. */
6596 if (first_dev) {
6597 wrap.b24 = new_fcport->d_id.b24;
6598 first_dev = 0;
6599 } else if (new_fcport->d_id.b24 == wrap.b24) {
6600 ql_dbg(ql_dbg_disc, vha, 0x209f,
6601 "Device wrap (%02x%02x%02x).\n",
6602 new_fcport->d_id.b.domain,
6603 new_fcport->d_id.b.area,
6604 new_fcport->d_id.b.al_pa);
6605 break;
6606 }
6607
6608 /* Bypass if same physical adapter. */
6609 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
6610 continue;
6611
6612 /* Bypass virtual ports of the same host. */
6613 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
6614 continue;
6615
6616 /* Bypass if same domain and area of adapter. */
6617 if (((new_fcport->d_id.b24 & 0xffff00) ==
6618 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
6619 ISP_CFG_FL)
6620 continue;
6621
6622 /* Bypass reserved domain fields. */
6623 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
6624 continue;
6625
6626 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
6627 if (ql2xgffidenable &&
6628 (!(new_fcport->fc4_type & FS_FC4TYPE_FCP) &&
6629 new_fcport->fc4_type != 0))
6630 continue;
6631
6632 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
6633
6634 /* Locate matching device in database. */
6635 found = 0;
6636 list_for_each_entry(fcport, &vha->vp_fcports, list) {
6637 if (memcmp(new_fcport->port_name, fcport->port_name,
6638 WWN_SIZE))
6639 continue;
6640
6641 fcport->scan_state = QLA_FCPORT_FOUND;
6642
6643 found++;
6644
6645 /* Update port state. */
6646 memcpy(fcport->fabric_port_name,
6647 new_fcport->fabric_port_name, WWN_SIZE);
6648 fcport->fp_speed = new_fcport->fp_speed;
6649
6650 /*
6651 * If address the same and state FCS_ONLINE
6652 * (or in target mode), nothing changed.
6653 */
6654 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
6655 (atomic_read(&fcport->state) == FCS_ONLINE ||
6656 (vha->host->active_mode == MODE_TARGET))) {
6657 break;
6658 }
6659
6660 if (fcport->login_retry == 0)
6661 fcport->login_retry =
6662 vha->hw->login_retry_count;
6663 /*
6664 * If device was not a fabric device before.
6665 */
6666 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
6667 fcport->d_id.b24 = new_fcport->d_id.b24;
6668 qla2x00_clear_loop_id(fcport);
6669 fcport->flags |= (FCF_FABRIC_DEVICE |
6670 FCF_LOGIN_NEEDED);
6671 break;
6672 }
6673
6674 /*
6675 * Port ID changed or device was marked to be updated;
6676 * Log it out if still logged in and mark it for
6677 * relogin later.
6678 */
6679 if (qla_tgt_mode_enabled(base_vha)) {
6680 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
6681 "port changed FC ID, %8phC"
6682 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
6683 fcport->port_name,
6684 fcport->d_id.b.domain,
6685 fcport->d_id.b.area,
6686 fcport->d_id.b.al_pa,
6687 fcport->loop_id,
6688 new_fcport->d_id.b.domain,
6689 new_fcport->d_id.b.area,
6690 new_fcport->d_id.b.al_pa);
6691 fcport->d_id.b24 = new_fcport->d_id.b24;
6692 break;
6693 }
6694
6695 fcport->d_id.b24 = new_fcport->d_id.b24;
6696 fcport->flags |= FCF_LOGIN_NEEDED;
6697 break;
6698 }
6699
6700 if (found && NVME_TARGET(vha->hw, fcport)) {
6701 if (fcport->disc_state == DSC_DELETE_PEND) {
6702 qla2x00_set_fcport_disc_state(fcport, DSC_GNL);
6703 vha->fcport_count--;
6704 fcport->login_succ = 0;
6705 }
6706 }
6707
6708 if (found) {
6709 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
6710 continue;
6711 }
6712 /* If device was not in our fcports list, then add it. */
6713 new_fcport->scan_state = QLA_FCPORT_FOUND;
6714 list_add_tail(&new_fcport->list, &vha->vp_fcports);
6715
6716 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
6717
6718
6719 /* Allocate a new replacement fcport. */
6720 nxt_d_id.b24 = new_fcport->d_id.b24;
6721 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
6722 if (new_fcport == NULL) {
6723 ql_log(ql_log_warn, vha, 0xd032,
6724 "Memory allocation failed for fcport.\n");
6725 return (QLA_MEMORY_ALLOC_FAILED);
6726 }
6727 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
6728 new_fcport->d_id.b24 = nxt_d_id.b24;
6729 }
6730
6731 qla2x00_free_fcport(new_fcport);
6732
6733 /*
6734 * Logout all previous fabric dev marked lost, except FCP2 devices.
6735 */
6736 list_for_each_entry(fcport, &vha->vp_fcports, list) {
6737 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
6738 break;
6739
6740 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
6741 continue;
6742
6743 if (fcport->scan_state == QLA_FCPORT_SCAN) {
6744 if ((qla_dual_mode_enabled(vha) ||
6745 qla_ini_mode_enabled(vha)) &&
6746 atomic_read(&fcport->state) == FCS_ONLINE) {
6747 qla2x00_mark_device_lost(vha, fcport,
6748 ql2xplogiabsentdevice);
6749 if (fcport->loop_id != FC_NO_LOOP_ID &&
6750 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
6751 fcport->port_type != FCT_INITIATOR &&
6752 fcport->port_type != FCT_BROADCAST) {
6753 ql_dbg(ql_dbg_disc, vha, 0x20f0,
6754 "%s %d %8phC post del sess\n",
6755 __func__, __LINE__,
6756 fcport->port_name);
6757 qlt_schedule_sess_for_deletion(fcport);
6758 continue;
6759 }
6760 }
6761 }
6762
6763 if (fcport->scan_state == QLA_FCPORT_FOUND &&
6764 (fcport->flags & FCF_LOGIN_NEEDED) != 0)
6765 qla24xx_fcport_handle_login(vha, fcport);
6766 }
6767 return (rval);
6768 }
6769
6770 /* FW does not set aside Loop id for MGMT Server/FFFFFAh */
6771 int
qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t * vha)6772 qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *vha)
6773 {
6774 int loop_id = FC_NO_LOOP_ID;
6775 int lid = NPH_MGMT_SERVER - vha->vp_idx;
6776 unsigned long flags;
6777 struct qla_hw_data *ha = vha->hw;
6778
6779 if (vha->vp_idx == 0) {
6780 set_bit(NPH_MGMT_SERVER, ha->loop_id_map);
6781 return NPH_MGMT_SERVER;
6782 }
6783
6784 /* pick id from high and work down to low */
6785 spin_lock_irqsave(&ha->vport_slock, flags);
6786 for (; lid > 0; lid--) {
6787 if (!test_bit(lid, vha->hw->loop_id_map)) {
6788 set_bit(lid, vha->hw->loop_id_map);
6789 loop_id = lid;
6790 break;
6791 }
6792 }
6793 spin_unlock_irqrestore(&ha->vport_slock, flags);
6794
6795 return loop_id;
6796 }
6797
6798 /*
6799 * qla2x00_fabric_login
6800 * Issue fabric login command.
6801 *
6802 * Input:
6803 * ha = adapter block pointer.
6804 * device = pointer to FC device type structure.
6805 *
6806 * Returns:
6807 * 0 - Login successfully
6808 * 1 - Login failed
6809 * 2 - Initiator device
6810 * 3 - Fatal error
6811 */
6812 int
qla2x00_fabric_login(scsi_qla_host_t * vha,fc_port_t * fcport,uint16_t * next_loopid)6813 qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
6814 uint16_t *next_loopid)
6815 {
6816 int rval;
6817 int retry;
6818 uint16_t tmp_loopid;
6819 uint16_t mb[MAILBOX_REGISTER_COUNT];
6820 struct qla_hw_data *ha = vha->hw;
6821
6822 retry = 0;
6823 tmp_loopid = 0;
6824
6825 for (;;) {
6826 ql_dbg(ql_dbg_disc, vha, 0x2000,
6827 "Trying Fabric Login w/loop id 0x%04x for port "
6828 "%02x%02x%02x.\n",
6829 fcport->loop_id, fcport->d_id.b.domain,
6830 fcport->d_id.b.area, fcport->d_id.b.al_pa);
6831
6832 /* Login fcport on switch. */
6833 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
6834 fcport->d_id.b.domain, fcport->d_id.b.area,
6835 fcport->d_id.b.al_pa, mb, BIT_0);
6836 if (rval != QLA_SUCCESS) {
6837 return rval;
6838 }
6839 if (mb[0] == MBS_PORT_ID_USED) {
6840 /*
6841 * Device has another loop ID. The firmware team
6842 * recommends the driver perform an implicit login with
6843 * the specified ID again. The ID we just used is save
6844 * here so we return with an ID that can be tried by
6845 * the next login.
6846 */
6847 retry++;
6848 tmp_loopid = fcport->loop_id;
6849 fcport->loop_id = mb[1];
6850
6851 ql_dbg(ql_dbg_disc, vha, 0x2001,
6852 "Fabric Login: port in use - next loop "
6853 "id=0x%04x, port id= %02x%02x%02x.\n",
6854 fcport->loop_id, fcport->d_id.b.domain,
6855 fcport->d_id.b.area, fcport->d_id.b.al_pa);
6856
6857 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
6858 /*
6859 * Login succeeded.
6860 */
6861 if (retry) {
6862 /* A retry occurred before. */
6863 *next_loopid = tmp_loopid;
6864 } else {
6865 /*
6866 * No retry occurred before. Just increment the
6867 * ID value for next login.
6868 */
6869 *next_loopid = (fcport->loop_id + 1);
6870 }
6871
6872 if (mb[1] & BIT_0) {
6873 fcport->port_type = FCT_INITIATOR;
6874 } else {
6875 fcport->port_type = FCT_TARGET;
6876 if (mb[1] & BIT_1) {
6877 fcport->flags |= FCF_FCP2_DEVICE;
6878 }
6879 }
6880
6881 if (mb[10] & BIT_0)
6882 fcport->supported_classes |= FC_COS_CLASS2;
6883 if (mb[10] & BIT_1)
6884 fcport->supported_classes |= FC_COS_CLASS3;
6885
6886 if (IS_FWI2_CAPABLE(ha)) {
6887 if (mb[10] & BIT_7)
6888 fcport->flags |=
6889 FCF_CONF_COMP_SUPPORTED;
6890 }
6891
6892 rval = QLA_SUCCESS;
6893 break;
6894 } else if (mb[0] == MBS_LOOP_ID_USED) {
6895 /*
6896 * Loop ID already used, try next loop ID.
6897 */
6898 fcport->loop_id++;
6899 rval = qla2x00_find_new_loop_id(vha, fcport);
6900 if (rval != QLA_SUCCESS) {
6901 /* Ran out of loop IDs to use */
6902 break;
6903 }
6904 } else if (mb[0] == MBS_COMMAND_ERROR) {
6905 /*
6906 * Firmware possibly timed out during login. If NO
6907 * retries are left to do then the device is declared
6908 * dead.
6909 */
6910 *next_loopid = fcport->loop_id;
6911 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
6912 fcport->d_id.b.domain, fcport->d_id.b.area,
6913 fcport->d_id.b.al_pa);
6914 qla2x00_mark_device_lost(vha, fcport, 1);
6915
6916 rval = 1;
6917 break;
6918 } else {
6919 /*
6920 * unrecoverable / not handled error
6921 */
6922 ql_dbg(ql_dbg_disc, vha, 0x2002,
6923 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
6924 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
6925 fcport->d_id.b.area, fcport->d_id.b.al_pa,
6926 fcport->loop_id, jiffies);
6927
6928 *next_loopid = fcport->loop_id;
6929 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
6930 fcport->d_id.b.domain, fcport->d_id.b.area,
6931 fcport->d_id.b.al_pa);
6932 qla2x00_clear_loop_id(fcport);
6933 fcport->login_retry = 0;
6934
6935 rval = 3;
6936 break;
6937 }
6938 }
6939
6940 return (rval);
6941 }
6942
6943 /*
6944 * qla2x00_local_device_login
6945 * Issue local device login command.
6946 *
6947 * Input:
6948 * ha = adapter block pointer.
6949 * loop_id = loop id of device to login to.
6950 *
6951 * Returns (Where's the #define!!!!):
6952 * 0 - Login successfully
6953 * 1 - Login failed
6954 * 3 - Fatal error
6955 */
6956 int
qla2x00_local_device_login(scsi_qla_host_t * vha,fc_port_t * fcport)6957 qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
6958 {
6959 int rval;
6960 uint16_t mb[MAILBOX_REGISTER_COUNT];
6961
6962 memset(mb, 0, sizeof(mb));
6963 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
6964 if (rval == QLA_SUCCESS) {
6965 /* Interrogate mailbox registers for any errors */
6966 if (mb[0] == MBS_COMMAND_ERROR)
6967 rval = 1;
6968 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
6969 /* device not in PCB table */
6970 rval = 3;
6971 }
6972
6973 return (rval);
6974 }
6975
6976 /*
6977 * qla2x00_loop_resync
6978 * Resync with fibre channel devices.
6979 *
6980 * Input:
6981 * ha = adapter block pointer.
6982 *
6983 * Returns:
6984 * 0 = success
6985 */
6986 int
qla2x00_loop_resync(scsi_qla_host_t * vha)6987 qla2x00_loop_resync(scsi_qla_host_t *vha)
6988 {
6989 int rval = QLA_SUCCESS;
6990 uint32_t wait_time;
6991
6992 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6993 if (vha->flags.online) {
6994 if (!(rval = qla2x00_fw_ready(vha))) {
6995 /* Wait at most MAX_TARGET RSCNs for a stable link. */
6996 wait_time = 256;
6997 do {
6998 if (!IS_QLAFX00(vha->hw)) {
6999 /*
7000 * Issue a marker after FW becomes
7001 * ready.
7002 */
7003 qla2x00_marker(vha, vha->hw->base_qpair,
7004 0, 0, MK_SYNC_ALL);
7005 vha->marker_needed = 0;
7006 }
7007
7008 /* Remap devices on Loop. */
7009 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
7010
7011 if (IS_QLAFX00(vha->hw))
7012 qlafx00_configure_devices(vha);
7013 else
7014 qla2x00_configure_loop(vha);
7015
7016 wait_time--;
7017 } while (!atomic_read(&vha->loop_down_timer) &&
7018 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
7019 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
7020 &vha->dpc_flags)));
7021 }
7022 }
7023
7024 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
7025 return (QLA_FUNCTION_FAILED);
7026
7027 if (rval)
7028 ql_dbg(ql_dbg_disc, vha, 0x206c,
7029 "%s *** FAILED ***.\n", __func__);
7030
7031 return (rval);
7032 }
7033
7034 /*
7035 * qla2x00_perform_loop_resync
7036 * Description: This function will set the appropriate flags and call
7037 * qla2x00_loop_resync. If successful loop will be resynced
7038 * Arguments : scsi_qla_host_t pointer
7039 * returm : Success or Failure
7040 */
7041
qla2x00_perform_loop_resync(scsi_qla_host_t * ha)7042 int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
7043 {
7044 int32_t rval = 0;
7045
7046 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
7047 /*Configure the flags so that resync happens properly*/
7048 atomic_set(&ha->loop_down_timer, 0);
7049 if (!(ha->device_flags & DFLG_NO_CABLE)) {
7050 atomic_set(&ha->loop_state, LOOP_UP);
7051 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
7052 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
7053 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
7054
7055 rval = qla2x00_loop_resync(ha);
7056 } else
7057 atomic_set(&ha->loop_state, LOOP_DEAD);
7058
7059 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
7060 }
7061
7062 return rval;
7063 }
7064
7065 /* Assumes idc_lock always held on entry */
7066 void
qla83xx_reset_ownership(scsi_qla_host_t * vha)7067 qla83xx_reset_ownership(scsi_qla_host_t *vha)
7068 {
7069 struct qla_hw_data *ha = vha->hw;
7070 uint32_t drv_presence, drv_presence_mask;
7071 uint32_t dev_part_info1, dev_part_info2, class_type;
7072 uint32_t class_type_mask = 0x3;
7073 uint16_t fcoe_other_function = 0xffff, i;
7074
7075 if (IS_QLA8044(ha)) {
7076 drv_presence = qla8044_rd_direct(vha,
7077 QLA8044_CRB_DRV_ACTIVE_INDEX);
7078 dev_part_info1 = qla8044_rd_direct(vha,
7079 QLA8044_CRB_DEV_PART_INFO_INDEX);
7080 dev_part_info2 = qla8044_rd_direct(vha,
7081 QLA8044_CRB_DEV_PART_INFO2);
7082 } else {
7083 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
7084 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
7085 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
7086 }
7087 for (i = 0; i < 8; i++) {
7088 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
7089 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
7090 (i != ha->portnum)) {
7091 fcoe_other_function = i;
7092 break;
7093 }
7094 }
7095 if (fcoe_other_function == 0xffff) {
7096 for (i = 0; i < 8; i++) {
7097 class_type = ((dev_part_info2 >> (i * 4)) &
7098 class_type_mask);
7099 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
7100 ((i + 8) != ha->portnum)) {
7101 fcoe_other_function = i + 8;
7102 break;
7103 }
7104 }
7105 }
7106 /*
7107 * Prepare drv-presence mask based on fcoe functions present.
7108 * However consider only valid physical fcoe function numbers (0-15).
7109 */
7110 drv_presence_mask = ~((1 << (ha->portnum)) |
7111 ((fcoe_other_function == 0xffff) ?
7112 0 : (1 << (fcoe_other_function))));
7113
7114 /* We are the reset owner iff:
7115 * - No other protocol drivers present.
7116 * - This is the lowest among fcoe functions. */
7117 if (!(drv_presence & drv_presence_mask) &&
7118 (ha->portnum < fcoe_other_function)) {
7119 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
7120 "This host is Reset owner.\n");
7121 ha->flags.nic_core_reset_owner = 1;
7122 }
7123 }
7124
7125 static int
__qla83xx_set_drv_ack(scsi_qla_host_t * vha)7126 __qla83xx_set_drv_ack(scsi_qla_host_t *vha)
7127 {
7128 int rval = QLA_SUCCESS;
7129 struct qla_hw_data *ha = vha->hw;
7130 uint32_t drv_ack;
7131
7132 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
7133 if (rval == QLA_SUCCESS) {
7134 drv_ack |= (1 << ha->portnum);
7135 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
7136 }
7137
7138 return rval;
7139 }
7140
7141 static int
__qla83xx_clear_drv_ack(scsi_qla_host_t * vha)7142 __qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
7143 {
7144 int rval = QLA_SUCCESS;
7145 struct qla_hw_data *ha = vha->hw;
7146 uint32_t drv_ack;
7147
7148 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
7149 if (rval == QLA_SUCCESS) {
7150 drv_ack &= ~(1 << ha->portnum);
7151 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
7152 }
7153
7154 return rval;
7155 }
7156
7157 /* Assumes idc-lock always held on entry */
7158 void
qla83xx_idc_audit(scsi_qla_host_t * vha,int audit_type)7159 qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
7160 {
7161 struct qla_hw_data *ha = vha->hw;
7162 uint32_t idc_audit_reg = 0, duration_secs = 0;
7163
7164 switch (audit_type) {
7165 case IDC_AUDIT_TIMESTAMP:
7166 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
7167 idc_audit_reg = (ha->portnum) |
7168 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
7169 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
7170 break;
7171
7172 case IDC_AUDIT_COMPLETION:
7173 duration_secs = ((jiffies_to_msecs(jiffies) -
7174 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
7175 idc_audit_reg = (ha->portnum) |
7176 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
7177 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
7178 break;
7179
7180 default:
7181 ql_log(ql_log_warn, vha, 0xb078,
7182 "Invalid audit type specified.\n");
7183 break;
7184 }
7185 }
7186
7187 /* Assumes idc_lock always held on entry */
7188 static int
qla83xx_initiating_reset(scsi_qla_host_t * vha)7189 qla83xx_initiating_reset(scsi_qla_host_t *vha)
7190 {
7191 struct qla_hw_data *ha = vha->hw;
7192 uint32_t idc_control, dev_state;
7193
7194 __qla83xx_get_idc_control(vha, &idc_control);
7195 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
7196 ql_log(ql_log_info, vha, 0xb080,
7197 "NIC Core reset has been disabled. idc-control=0x%x\n",
7198 idc_control);
7199 return QLA_FUNCTION_FAILED;
7200 }
7201
7202 /* Set NEED-RESET iff in READY state and we are the reset-owner */
7203 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
7204 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
7205 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
7206 QLA8XXX_DEV_NEED_RESET);
7207 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
7208 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
7209 } else {
7210 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n",
7211 qdev_state(dev_state));
7212
7213 /* SV: XXX: Is timeout required here? */
7214 /* Wait for IDC state change READY -> NEED_RESET */
7215 while (dev_state == QLA8XXX_DEV_READY) {
7216 qla83xx_idc_unlock(vha, 0);
7217 msleep(200);
7218 qla83xx_idc_lock(vha, 0);
7219 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
7220 }
7221 }
7222
7223 /* Send IDC ack by writing to drv-ack register */
7224 __qla83xx_set_drv_ack(vha);
7225
7226 return QLA_SUCCESS;
7227 }
7228
7229 int
__qla83xx_set_idc_control(scsi_qla_host_t * vha,uint32_t idc_control)7230 __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
7231 {
7232 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
7233 }
7234
7235 int
__qla83xx_get_idc_control(scsi_qla_host_t * vha,uint32_t * idc_control)7236 __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
7237 {
7238 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
7239 }
7240
7241 static int
qla83xx_check_driver_presence(scsi_qla_host_t * vha)7242 qla83xx_check_driver_presence(scsi_qla_host_t *vha)
7243 {
7244 uint32_t drv_presence = 0;
7245 struct qla_hw_data *ha = vha->hw;
7246
7247 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
7248 if (drv_presence & (1 << ha->portnum))
7249 return QLA_SUCCESS;
7250 else
7251 return QLA_TEST_FAILED;
7252 }
7253
7254 int
qla83xx_nic_core_reset(scsi_qla_host_t * vha)7255 qla83xx_nic_core_reset(scsi_qla_host_t *vha)
7256 {
7257 int rval = QLA_SUCCESS;
7258 struct qla_hw_data *ha = vha->hw;
7259
7260 ql_dbg(ql_dbg_p3p, vha, 0xb058,
7261 "Entered %s().\n", __func__);
7262
7263 if (vha->device_flags & DFLG_DEV_FAILED) {
7264 ql_log(ql_log_warn, vha, 0xb059,
7265 "Device in unrecoverable FAILED state.\n");
7266 return QLA_FUNCTION_FAILED;
7267 }
7268
7269 qla83xx_idc_lock(vha, 0);
7270
7271 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
7272 ql_log(ql_log_warn, vha, 0xb05a,
7273 "Function=0x%x has been removed from IDC participation.\n",
7274 ha->portnum);
7275 rval = QLA_FUNCTION_FAILED;
7276 goto exit;
7277 }
7278
7279 qla83xx_reset_ownership(vha);
7280
7281 rval = qla83xx_initiating_reset(vha);
7282
7283 /*
7284 * Perform reset if we are the reset-owner,
7285 * else wait till IDC state changes to READY/FAILED.
7286 */
7287 if (rval == QLA_SUCCESS) {
7288 rval = qla83xx_idc_state_handler(vha);
7289
7290 if (rval == QLA_SUCCESS)
7291 ha->flags.nic_core_hung = 0;
7292 __qla83xx_clear_drv_ack(vha);
7293 }
7294
7295 exit:
7296 qla83xx_idc_unlock(vha, 0);
7297
7298 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
7299
7300 return rval;
7301 }
7302
7303 int
qla2xxx_mctp_dump(scsi_qla_host_t * vha)7304 qla2xxx_mctp_dump(scsi_qla_host_t *vha)
7305 {
7306 struct qla_hw_data *ha = vha->hw;
7307 int rval = QLA_FUNCTION_FAILED;
7308
7309 if (!IS_MCTP_CAPABLE(ha)) {
7310 /* This message can be removed from the final version */
7311 ql_log(ql_log_info, vha, 0x506d,
7312 "This board is not MCTP capable\n");
7313 return rval;
7314 }
7315
7316 if (!ha->mctp_dump) {
7317 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
7318 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
7319
7320 if (!ha->mctp_dump) {
7321 ql_log(ql_log_warn, vha, 0x506e,
7322 "Failed to allocate memory for mctp dump\n");
7323 return rval;
7324 }
7325 }
7326
7327 #define MCTP_DUMP_STR_ADDR 0x00000000
7328 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
7329 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
7330 if (rval != QLA_SUCCESS) {
7331 ql_log(ql_log_warn, vha, 0x506f,
7332 "Failed to capture mctp dump\n");
7333 } else {
7334 ql_log(ql_log_info, vha, 0x5070,
7335 "Mctp dump capture for host (%ld/%p).\n",
7336 vha->host_no, ha->mctp_dump);
7337 ha->mctp_dumped = 1;
7338 }
7339
7340 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
7341 ha->flags.nic_core_reset_hdlr_active = 1;
7342 rval = qla83xx_restart_nic_firmware(vha);
7343 if (rval)
7344 /* NIC Core reset failed. */
7345 ql_log(ql_log_warn, vha, 0x5071,
7346 "Failed to restart nic firmware\n");
7347 else
7348 ql_dbg(ql_dbg_p3p, vha, 0xb084,
7349 "Restarted NIC firmware successfully.\n");
7350 ha->flags.nic_core_reset_hdlr_active = 0;
7351 }
7352
7353 return rval;
7354
7355 }
7356
7357 /*
7358 * qla2x00_quiesce_io
7359 * Description: This function will block the new I/Os
7360 * Its not aborting any I/Os as context
7361 * is not destroyed during quiescence
7362 * Arguments: scsi_qla_host_t
7363 * return : void
7364 */
7365 void
qla2x00_quiesce_io(scsi_qla_host_t * vha)7366 qla2x00_quiesce_io(scsi_qla_host_t *vha)
7367 {
7368 struct qla_hw_data *ha = vha->hw;
7369 struct scsi_qla_host *vp, *tvp;
7370 unsigned long flags;
7371
7372 ql_dbg(ql_dbg_dpc, vha, 0x401d,
7373 "Quiescing I/O - ha=%p.\n", ha);
7374
7375 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
7376 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
7377 atomic_set(&vha->loop_state, LOOP_DOWN);
7378 qla2x00_mark_all_devices_lost(vha);
7379
7380 spin_lock_irqsave(&ha->vport_slock, flags);
7381 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7382 atomic_inc(&vp->vref_count);
7383 spin_unlock_irqrestore(&ha->vport_slock, flags);
7384
7385 qla2x00_mark_all_devices_lost(vp);
7386
7387 spin_lock_irqsave(&ha->vport_slock, flags);
7388 atomic_dec(&vp->vref_count);
7389 }
7390 spin_unlock_irqrestore(&ha->vport_slock, flags);
7391 } else {
7392 if (!atomic_read(&vha->loop_down_timer))
7393 atomic_set(&vha->loop_down_timer,
7394 LOOP_DOWN_TIME);
7395 }
7396 /* Wait for pending cmds to complete */
7397 WARN_ON_ONCE(qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST)
7398 != QLA_SUCCESS);
7399 }
7400
7401 void
qla2x00_abort_isp_cleanup(scsi_qla_host_t * vha)7402 qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
7403 {
7404 struct qla_hw_data *ha = vha->hw;
7405 struct scsi_qla_host *vp, *tvp;
7406 unsigned long flags;
7407 fc_port_t *fcport;
7408 u16 i;
7409
7410 /* For ISP82XX, driver waits for completion of the commands.
7411 * online flag should be set.
7412 */
7413 if (!(IS_P3P_TYPE(ha)))
7414 vha->flags.online = 0;
7415 ha->flags.chip_reset_done = 0;
7416 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
7417 vha->qla_stats.total_isp_aborts++;
7418
7419 ql_log(ql_log_info, vha, 0x00af,
7420 "Performing ISP error recovery - ha=%p.\n", ha);
7421
7422 ha->flags.purge_mbox = 1;
7423 /* For ISP82XX, reset_chip is just disabling interrupts.
7424 * Driver waits for the completion of the commands.
7425 * the interrupts need to be enabled.
7426 */
7427 if (!(IS_P3P_TYPE(ha)))
7428 ha->isp_ops->reset_chip(vha);
7429
7430 ha->link_data_rate = PORT_SPEED_UNKNOWN;
7431 SAVE_TOPO(ha);
7432 ha->flags.rida_fmt2 = 0;
7433 ha->flags.n2n_ae = 0;
7434 ha->flags.lip_ae = 0;
7435 ha->current_topology = 0;
7436 QLA_FW_STOPPED(ha);
7437 ha->flags.fw_init_done = 0;
7438 ha->chip_reset++;
7439 ha->base_qpair->chip_reset = ha->chip_reset;
7440 ha->base_qpair->cmd_cnt = ha->base_qpair->cmd_completion_cnt = 0;
7441 ha->base_qpair->prev_completion_cnt = 0;
7442 for (i = 0; i < ha->max_qpairs; i++) {
7443 if (ha->queue_pair_map[i]) {
7444 ha->queue_pair_map[i]->chip_reset =
7445 ha->base_qpair->chip_reset;
7446 ha->queue_pair_map[i]->cmd_cnt =
7447 ha->queue_pair_map[i]->cmd_completion_cnt = 0;
7448 ha->base_qpair->prev_completion_cnt = 0;
7449 }
7450 }
7451
7452 /* purge MBox commands */
7453 spin_lock_irqsave(&ha->hardware_lock, flags);
7454 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) {
7455 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
7456 complete(&ha->mbx_intr_comp);
7457 }
7458 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7459
7460 i = 0;
7461 while (atomic_read(&ha->num_pend_mbx_stage2) ||
7462 atomic_read(&ha->num_pend_mbx_stage1)) {
7463 msleep(20);
7464 i++;
7465 if (i > 50)
7466 break;
7467 }
7468 ha->flags.purge_mbox = 0;
7469
7470 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
7471 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
7472 atomic_set(&vha->loop_state, LOOP_DOWN);
7473 qla2x00_mark_all_devices_lost(vha);
7474
7475 spin_lock_irqsave(&ha->vport_slock, flags);
7476 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7477 atomic_inc(&vp->vref_count);
7478 spin_unlock_irqrestore(&ha->vport_slock, flags);
7479
7480 qla2x00_mark_all_devices_lost(vp);
7481
7482 spin_lock_irqsave(&ha->vport_slock, flags);
7483 atomic_dec(&vp->vref_count);
7484 }
7485 spin_unlock_irqrestore(&ha->vport_slock, flags);
7486 } else {
7487 if (!atomic_read(&vha->loop_down_timer))
7488 atomic_set(&vha->loop_down_timer,
7489 LOOP_DOWN_TIME);
7490 }
7491
7492 /* Clear all async request states across all VPs. */
7493 list_for_each_entry(fcport, &vha->vp_fcports, list) {
7494 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7495 fcport->scan_state = 0;
7496 }
7497 spin_lock_irqsave(&ha->vport_slock, flags);
7498 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7499 atomic_inc(&vp->vref_count);
7500 spin_unlock_irqrestore(&ha->vport_slock, flags);
7501
7502 list_for_each_entry(fcport, &vp->vp_fcports, list)
7503 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7504
7505 spin_lock_irqsave(&ha->vport_slock, flags);
7506 atomic_dec(&vp->vref_count);
7507 }
7508 spin_unlock_irqrestore(&ha->vport_slock, flags);
7509
7510 /* Make sure for ISP 82XX IO DMA is complete */
7511 if (IS_P3P_TYPE(ha)) {
7512 qla82xx_chip_reset_cleanup(vha);
7513 ql_log(ql_log_info, vha, 0x00b4,
7514 "Done chip reset cleanup.\n");
7515
7516 /* Done waiting for pending commands. Reset online flag */
7517 vha->flags.online = 0;
7518 }
7519
7520 /* Requeue all commands in outstanding command list. */
7521 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
7522 /* memory barrier */
7523 wmb();
7524 }
7525
7526 /*
7527 * qla2x00_abort_isp
7528 * Resets ISP and aborts all outstanding commands.
7529 *
7530 * Input:
7531 * ha = adapter block pointer.
7532 *
7533 * Returns:
7534 * 0 = success
7535 */
7536 int
qla2x00_abort_isp(scsi_qla_host_t * vha)7537 qla2x00_abort_isp(scsi_qla_host_t *vha)
7538 {
7539 uint8_t status = 0;
7540 struct qla_hw_data *ha = vha->hw;
7541 struct scsi_qla_host *vp, *tvp;
7542 struct req_que *req = ha->req_q_map[0];
7543 unsigned long flags;
7544 fc_port_t *fcport;
7545
7546 if (vha->flags.online) {
7547 qla2x00_abort_isp_cleanup(vha);
7548
7549 vha->dport_status |= DPORT_DIAG_CHIP_RESET_IN_PROGRESS;
7550 vha->dport_status &= ~DPORT_DIAG_IN_PROGRESS;
7551
7552 if (vha->hw->flags.port_isolated)
7553 return status;
7554
7555 if (qla2x00_isp_reg_stat(ha)) {
7556 ql_log(ql_log_info, vha, 0x803f,
7557 "ISP Abort - ISP reg disconnect, exiting.\n");
7558 return status;
7559 }
7560
7561 if (test_and_clear_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags)) {
7562 ha->flags.chip_reset_done = 1;
7563 vha->flags.online = 1;
7564 status = 0;
7565 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7566 return status;
7567 }
7568
7569 if (IS_QLA8031(ha)) {
7570 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
7571 "Clearing fcoe driver presence.\n");
7572 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
7573 ql_dbg(ql_dbg_p3p, vha, 0xb073,
7574 "Error while clearing DRV-Presence.\n");
7575 }
7576
7577 if (unlikely(pci_channel_offline(ha->pdev) &&
7578 ha->flags.pci_channel_io_perm_failure)) {
7579 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7580 status = 0;
7581 return status;
7582 }
7583
7584 switch (vha->qlini_mode) {
7585 case QLA2XXX_INI_MODE_DISABLED:
7586 if (!qla_tgt_mode_enabled(vha))
7587 return 0;
7588 break;
7589 case QLA2XXX_INI_MODE_DUAL:
7590 if (!qla_dual_mode_enabled(vha) &&
7591 !qla_ini_mode_enabled(vha))
7592 return 0;
7593 break;
7594 case QLA2XXX_INI_MODE_ENABLED:
7595 default:
7596 break;
7597 }
7598
7599 ha->isp_ops->get_flash_version(vha, req->ring);
7600
7601 if (qla2x00_isp_reg_stat(ha)) {
7602 ql_log(ql_log_info, vha, 0x803f,
7603 "ISP Abort - ISP reg disconnect pre nvram config, exiting.\n");
7604 return status;
7605 }
7606 ha->isp_ops->nvram_config(vha);
7607
7608 if (qla2x00_isp_reg_stat(ha)) {
7609 ql_log(ql_log_info, vha, 0x803f,
7610 "ISP Abort - ISP reg disconnect post nvmram config, exiting.\n");
7611 return status;
7612 }
7613
7614 /* User may have updated [fcp|nvme] prefer in flash */
7615 list_for_each_entry(fcport, &vha->vp_fcports, list) {
7616 if (NVME_PRIORITY(ha, fcport))
7617 fcport->do_prli_nvme = 1;
7618 else
7619 fcport->do_prli_nvme = 0;
7620 }
7621
7622 if (!qla2x00_restart_isp(vha)) {
7623 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7624
7625 if (!atomic_read(&vha->loop_down_timer)) {
7626 /*
7627 * Issue marker command only when we are going
7628 * to start the I/O .
7629 */
7630 vha->marker_needed = 1;
7631 }
7632
7633 vha->flags.online = 1;
7634
7635 ha->isp_ops->enable_intrs(ha);
7636
7637 ha->isp_abort_cnt = 0;
7638 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7639
7640 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
7641 qla2x00_get_fw_version(vha);
7642
7643 } else { /* failed the ISP abort */
7644 vha->flags.online = 1;
7645 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
7646 if (ha->isp_abort_cnt == 0) {
7647 ql_log(ql_log_fatal, vha, 0x8035,
7648 "ISP error recover failed - "
7649 "board disabled.\n");
7650 /*
7651 * The next call disables the board
7652 * completely.
7653 */
7654 qla2x00_abort_isp_cleanup(vha);
7655 vha->flags.online = 0;
7656 clear_bit(ISP_ABORT_RETRY,
7657 &vha->dpc_flags);
7658 status = 0;
7659 } else { /* schedule another ISP abort */
7660 ha->isp_abort_cnt--;
7661 ql_dbg(ql_dbg_taskm, vha, 0x8020,
7662 "ISP abort - retry remaining %d.\n",
7663 ha->isp_abort_cnt);
7664 status = 1;
7665 }
7666 } else {
7667 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7668 ql_dbg(ql_dbg_taskm, vha, 0x8021,
7669 "ISP error recovery - retrying (%d) "
7670 "more times.\n", ha->isp_abort_cnt);
7671 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7672 status = 1;
7673 }
7674 }
7675
7676 }
7677
7678 if (vha->hw->flags.port_isolated) {
7679 qla2x00_abort_isp_cleanup(vha);
7680 return status;
7681 }
7682
7683 if (!status) {
7684 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
7685 qla2x00_configure_hba(vha);
7686 spin_lock_irqsave(&ha->vport_slock, flags);
7687 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7688 if (vp->vp_idx) {
7689 atomic_inc(&vp->vref_count);
7690 spin_unlock_irqrestore(&ha->vport_slock, flags);
7691
7692 /* User may have updated [fcp|nvme] prefer in flash */
7693 list_for_each_entry(fcport, &vp->vp_fcports, list) {
7694 if (NVME_PRIORITY(ha, fcport))
7695 fcport->do_prli_nvme = 1;
7696 else
7697 fcport->do_prli_nvme = 0;
7698 }
7699
7700 qla2x00_vp_abort_isp(vp);
7701
7702 spin_lock_irqsave(&ha->vport_slock, flags);
7703 atomic_dec(&vp->vref_count);
7704 }
7705 }
7706 spin_unlock_irqrestore(&ha->vport_slock, flags);
7707
7708 if (IS_QLA8031(ha)) {
7709 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
7710 "Setting back fcoe driver presence.\n");
7711 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
7712 ql_dbg(ql_dbg_p3p, vha, 0xb074,
7713 "Error while setting DRV-Presence.\n");
7714 }
7715 } else {
7716 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
7717 __func__);
7718 }
7719
7720 return(status);
7721 }
7722
7723 /*
7724 * qla2x00_restart_isp
7725 * restarts the ISP after a reset
7726 *
7727 * Input:
7728 * ha = adapter block pointer.
7729 *
7730 * Returns:
7731 * 0 = success
7732 */
7733 static int
qla2x00_restart_isp(scsi_qla_host_t * vha)7734 qla2x00_restart_isp(scsi_qla_host_t *vha)
7735 {
7736 int status;
7737 struct qla_hw_data *ha = vha->hw;
7738
7739 /* If firmware needs to be loaded */
7740 if (qla2x00_isp_firmware(vha)) {
7741 vha->flags.online = 0;
7742 status = ha->isp_ops->chip_diag(vha);
7743 if (status)
7744 return status;
7745 status = qla2x00_setup_chip(vha);
7746 if (status)
7747 return status;
7748 }
7749
7750 status = qla2x00_init_rings(vha);
7751 if (status)
7752 return status;
7753
7754 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7755 ha->flags.chip_reset_done = 1;
7756
7757 /* Initialize the queues in use */
7758 qla25xx_init_queues(ha);
7759
7760 status = qla2x00_fw_ready(vha);
7761 if (status) {
7762 /* if no cable then assume it's good */
7763 return vha->device_flags & DFLG_NO_CABLE ? 0 : status;
7764 }
7765
7766 /* Issue a marker after FW becomes ready. */
7767 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
7768 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
7769
7770 return 0;
7771 }
7772
7773 static int
qla25xx_init_queues(struct qla_hw_data * ha)7774 qla25xx_init_queues(struct qla_hw_data *ha)
7775 {
7776 struct rsp_que *rsp = NULL;
7777 struct req_que *req = NULL;
7778 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7779 int ret = -1;
7780 int i;
7781
7782 for (i = 1; i < ha->max_rsp_queues; i++) {
7783 rsp = ha->rsp_q_map[i];
7784 if (rsp && test_bit(i, ha->rsp_qid_map)) {
7785 rsp->options &= ~BIT_0;
7786 ret = qla25xx_init_rsp_que(base_vha, rsp);
7787 if (ret != QLA_SUCCESS)
7788 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
7789 "%s Rsp que: %d init failed.\n",
7790 __func__, rsp->id);
7791 else
7792 ql_dbg(ql_dbg_init, base_vha, 0x0100,
7793 "%s Rsp que: %d inited.\n",
7794 __func__, rsp->id);
7795 }
7796 }
7797 for (i = 1; i < ha->max_req_queues; i++) {
7798 req = ha->req_q_map[i];
7799 if (req && test_bit(i, ha->req_qid_map)) {
7800 /* Clear outstanding commands array. */
7801 req->options &= ~BIT_0;
7802 ret = qla25xx_init_req_que(base_vha, req);
7803 if (ret != QLA_SUCCESS)
7804 ql_dbg(ql_dbg_init, base_vha, 0x0101,
7805 "%s Req que: %d init failed.\n",
7806 __func__, req->id);
7807 else
7808 ql_dbg(ql_dbg_init, base_vha, 0x0102,
7809 "%s Req que: %d inited.\n",
7810 __func__, req->id);
7811 }
7812 }
7813 return ret;
7814 }
7815
7816 /*
7817 * qla2x00_reset_adapter
7818 * Reset adapter.
7819 *
7820 * Input:
7821 * ha = adapter block pointer.
7822 */
7823 int
qla2x00_reset_adapter(scsi_qla_host_t * vha)7824 qla2x00_reset_adapter(scsi_qla_host_t *vha)
7825 {
7826 unsigned long flags = 0;
7827 struct qla_hw_data *ha = vha->hw;
7828 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7829
7830 vha->flags.online = 0;
7831 ha->isp_ops->disable_intrs(ha);
7832
7833 spin_lock_irqsave(&ha->hardware_lock, flags);
7834 wrt_reg_word(®->hccr, HCCR_RESET_RISC);
7835 rd_reg_word(®->hccr); /* PCI Posting. */
7836 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
7837 rd_reg_word(®->hccr); /* PCI Posting. */
7838 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7839
7840 return QLA_SUCCESS;
7841 }
7842
7843 int
qla24xx_reset_adapter(scsi_qla_host_t * vha)7844 qla24xx_reset_adapter(scsi_qla_host_t *vha)
7845 {
7846 unsigned long flags = 0;
7847 struct qla_hw_data *ha = vha->hw;
7848 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
7849
7850 if (IS_P3P_TYPE(ha))
7851 return QLA_SUCCESS;
7852
7853 vha->flags.online = 0;
7854 ha->isp_ops->disable_intrs(ha);
7855
7856 spin_lock_irqsave(&ha->hardware_lock, flags);
7857 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET);
7858 rd_reg_dword(®->hccr);
7859 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE);
7860 rd_reg_dword(®->hccr);
7861 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7862
7863 if (IS_NOPOLLING_TYPE(ha))
7864 ha->isp_ops->enable_intrs(ha);
7865
7866 return QLA_SUCCESS;
7867 }
7868
7869 /* On sparc systems, obtain port and node WWN from firmware
7870 * properties.
7871 */
qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t * vha,struct nvram_24xx * nv)7872 static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
7873 struct nvram_24xx *nv)
7874 {
7875 #ifdef CONFIG_SPARC
7876 struct qla_hw_data *ha = vha->hw;
7877 struct pci_dev *pdev = ha->pdev;
7878 struct device_node *dp = pci_device_to_OF_node(pdev);
7879 const u8 *val;
7880 int len;
7881
7882 val = of_get_property(dp, "port-wwn", &len);
7883 if (val && len >= WWN_SIZE)
7884 memcpy(nv->port_name, val, WWN_SIZE);
7885
7886 val = of_get_property(dp, "node-wwn", &len);
7887 if (val && len >= WWN_SIZE)
7888 memcpy(nv->node_name, val, WWN_SIZE);
7889 #endif
7890 }
7891
7892 int
qla24xx_nvram_config(scsi_qla_host_t * vha)7893 qla24xx_nvram_config(scsi_qla_host_t *vha)
7894 {
7895 int rval;
7896 struct init_cb_24xx *icb;
7897 struct nvram_24xx *nv;
7898 __le32 *dptr;
7899 uint8_t *dptr1, *dptr2;
7900 uint32_t chksum;
7901 uint16_t cnt;
7902 struct qla_hw_data *ha = vha->hw;
7903
7904 rval = QLA_SUCCESS;
7905 icb = (struct init_cb_24xx *)ha->init_cb;
7906 nv = ha->nvram;
7907
7908 /* Determine NVRAM starting address. */
7909 if (ha->port_no == 0) {
7910 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
7911 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
7912 } else {
7913 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
7914 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
7915 }
7916
7917 ha->nvram_size = sizeof(*nv);
7918 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7919
7920 /* Get VPD data into cache */
7921 ha->vpd = ha->nvram + VPD_OFFSET;
7922 ha->isp_ops->read_nvram(vha, ha->vpd,
7923 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
7924
7925 /* Get NVRAM data into cache and calculate checksum. */
7926 dptr = (__force __le32 *)nv;
7927 ha->isp_ops->read_nvram(vha, dptr, ha->nvram_base, ha->nvram_size);
7928 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
7929 chksum += le32_to_cpu(*dptr);
7930
7931 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
7932 "Contents of NVRAM\n");
7933 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
7934 nv, ha->nvram_size);
7935
7936 /* Bad NVRAM data, set defaults parameters. */
7937 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
7938 le16_to_cpu(nv->nvram_version) < ICB_VERSION) {
7939 /* Reset NVRAM data. */
7940 ql_log(ql_log_warn, vha, 0x006b,
7941 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n",
7942 chksum, nv->id, nv->nvram_version);
7943 ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, sizeof(*nv));
7944 ql_log(ql_log_warn, vha, 0x006c,
7945 "Falling back to functioning (yet invalid -- WWPN) "
7946 "defaults.\n");
7947
7948 /*
7949 * Set default initialization control block.
7950 */
7951 memset(nv, 0, ha->nvram_size);
7952 nv->nvram_version = cpu_to_le16(ICB_VERSION);
7953 nv->version = cpu_to_le16(ICB_VERSION);
7954 nv->frame_payload_size = cpu_to_le16(2048);
7955 nv->execution_throttle = cpu_to_le16(0xFFFF);
7956 nv->exchange_count = cpu_to_le16(0);
7957 nv->hard_address = cpu_to_le16(124);
7958 nv->port_name[0] = 0x21;
7959 nv->port_name[1] = 0x00 + ha->port_no + 1;
7960 nv->port_name[2] = 0x00;
7961 nv->port_name[3] = 0xe0;
7962 nv->port_name[4] = 0x8b;
7963 nv->port_name[5] = 0x1c;
7964 nv->port_name[6] = 0x55;
7965 nv->port_name[7] = 0x86;
7966 nv->node_name[0] = 0x20;
7967 nv->node_name[1] = 0x00;
7968 nv->node_name[2] = 0x00;
7969 nv->node_name[3] = 0xe0;
7970 nv->node_name[4] = 0x8b;
7971 nv->node_name[5] = 0x1c;
7972 nv->node_name[6] = 0x55;
7973 nv->node_name[7] = 0x86;
7974 qla24xx_nvram_wwn_from_ofw(vha, nv);
7975 nv->login_retry_count = cpu_to_le16(8);
7976 nv->interrupt_delay_timer = cpu_to_le16(0);
7977 nv->login_timeout = cpu_to_le16(0);
7978 nv->firmware_options_1 =
7979 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7980 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7981 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7982 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7983 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7984 nv->efi_parameters = cpu_to_le32(0);
7985 nv->reset_delay = 5;
7986 nv->max_luns_per_target = cpu_to_le16(128);
7987 nv->port_down_retry_count = cpu_to_le16(30);
7988 nv->link_down_timeout = cpu_to_le16(30);
7989
7990 rval = 1;
7991 }
7992
7993 if (qla_tgt_mode_enabled(vha)) {
7994 /* Don't enable full login after initial LIP */
7995 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
7996 /* Don't enable LIP full login for initiator */
7997 nv->host_p &= cpu_to_le32(~BIT_10);
7998 }
7999
8000 qlt_24xx_config_nvram_stage1(vha, nv);
8001
8002 /* Reset Initialization control block */
8003 memset(icb, 0, ha->init_cb_size);
8004
8005 /* Copy 1st segment. */
8006 dptr1 = (uint8_t *)icb;
8007 dptr2 = (uint8_t *)&nv->version;
8008 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
8009 while (cnt--)
8010 *dptr1++ = *dptr2++;
8011
8012 icb->login_retry_count = nv->login_retry_count;
8013 icb->link_down_on_nos = nv->link_down_on_nos;
8014
8015 /* Copy 2nd segment. */
8016 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
8017 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
8018 cnt = (uint8_t *)&icb->reserved_3 -
8019 (uint8_t *)&icb->interrupt_delay_timer;
8020 while (cnt--)
8021 *dptr1++ = *dptr2++;
8022 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
8023 /*
8024 * Setup driver NVRAM options.
8025 */
8026 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
8027 "QLA2462");
8028
8029 qlt_24xx_config_nvram_stage2(vha, icb);
8030
8031 if (nv->host_p & cpu_to_le32(BIT_15)) {
8032 /* Use alternate WWN? */
8033 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
8034 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
8035 }
8036
8037 /* Prepare nodename */
8038 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
8039 /*
8040 * Firmware will apply the following mask if the nodename was
8041 * not provided.
8042 */
8043 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
8044 icb->node_name[0] &= 0xF0;
8045 }
8046
8047 /* Set host adapter parameters. */
8048 ha->flags.disable_risc_code_load = 0;
8049 ha->flags.enable_lip_reset = 0;
8050 ha->flags.enable_lip_full_login =
8051 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0;
8052 ha->flags.enable_target_reset =
8053 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0;
8054 ha->flags.enable_led_scheme = 0;
8055 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0;
8056
8057 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
8058 (BIT_6 | BIT_5 | BIT_4)) >> 4;
8059
8060 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
8061 sizeof(ha->fw_seriallink_options24));
8062
8063 /* save HBA serial number */
8064 ha->serial0 = icb->port_name[5];
8065 ha->serial1 = icb->port_name[6];
8066 ha->serial2 = icb->port_name[7];
8067 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
8068 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
8069
8070 icb->execution_throttle = cpu_to_le16(0xFFFF);
8071
8072 ha->retry_count = le16_to_cpu(nv->login_retry_count);
8073
8074 /* Set minimum login_timeout to 4 seconds. */
8075 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
8076 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
8077 if (le16_to_cpu(nv->login_timeout) < 4)
8078 nv->login_timeout = cpu_to_le16(4);
8079 ha->login_timeout = le16_to_cpu(nv->login_timeout);
8080
8081 /* Set minimum RATOV to 100 tenths of a second. */
8082 ha->r_a_tov = 100;
8083
8084 ha->loop_reset_delay = nv->reset_delay;
8085
8086 /* Link Down Timeout = 0:
8087 *
8088 * When Port Down timer expires we will start returning
8089 * I/O's to OS with "DID_NO_CONNECT".
8090 *
8091 * Link Down Timeout != 0:
8092 *
8093 * The driver waits for the link to come up after link down
8094 * before returning I/Os to OS with "DID_NO_CONNECT".
8095 */
8096 if (le16_to_cpu(nv->link_down_timeout) == 0) {
8097 ha->loop_down_abort_time =
8098 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
8099 } else {
8100 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
8101 ha->loop_down_abort_time =
8102 (LOOP_DOWN_TIME - ha->link_down_timeout);
8103 }
8104
8105 /* Need enough time to try and get the port back. */
8106 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
8107 if (qlport_down_retry)
8108 ha->port_down_retry_count = qlport_down_retry;
8109
8110 /* Set login_retry_count */
8111 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
8112 if (ha->port_down_retry_count ==
8113 le16_to_cpu(nv->port_down_retry_count) &&
8114 ha->port_down_retry_count > 3)
8115 ha->login_retry_count = ha->port_down_retry_count;
8116 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
8117 ha->login_retry_count = ha->port_down_retry_count;
8118 if (ql2xloginretrycount)
8119 ha->login_retry_count = ql2xloginretrycount;
8120
8121 /* N2N: driver will initiate Login instead of FW */
8122 icb->firmware_options_3 |= cpu_to_le32(BIT_8);
8123
8124 /* Enable ZIO. */
8125 if (!vha->flags.init_done) {
8126 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
8127 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
8128 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
8129 le16_to_cpu(icb->interrupt_delay_timer) : 2;
8130 }
8131 icb->firmware_options_2 &= cpu_to_le32(
8132 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
8133 if (ha->zio_mode != QLA_ZIO_DISABLED) {
8134 ha->zio_mode = QLA_ZIO_MODE_6;
8135
8136 ql_log(ql_log_info, vha, 0x006f,
8137 "ZIO mode %d enabled; timer delay (%d us).\n",
8138 ha->zio_mode, ha->zio_timer * 100);
8139
8140 icb->firmware_options_2 |= cpu_to_le32(
8141 (uint32_t)ha->zio_mode);
8142 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
8143 }
8144
8145 if (rval) {
8146 ql_log(ql_log_warn, vha, 0x0070,
8147 "NVRAM configuration failed.\n");
8148 }
8149 return (rval);
8150 }
8151
8152 static void
qla27xx_print_image(struct scsi_qla_host * vha,char * name,struct qla27xx_image_status * image_status)8153 qla27xx_print_image(struct scsi_qla_host *vha, char *name,
8154 struct qla27xx_image_status *image_status)
8155 {
8156 ql_dbg(ql_dbg_init, vha, 0x018b,
8157 "%s %s: mask=%#02x gen=%#04x ver=%u.%u map=%#01x sum=%#08x sig=%#08x\n",
8158 name, "status",
8159 image_status->image_status_mask,
8160 le16_to_cpu(image_status->generation),
8161 image_status->ver_major,
8162 image_status->ver_minor,
8163 image_status->bitmap,
8164 le32_to_cpu(image_status->checksum),
8165 le32_to_cpu(image_status->signature));
8166 }
8167
8168 static bool
qla28xx_check_aux_image_status_signature(struct qla27xx_image_status * image_status)8169 qla28xx_check_aux_image_status_signature(
8170 struct qla27xx_image_status *image_status)
8171 {
8172 ulong signature = le32_to_cpu(image_status->signature);
8173
8174 return signature != QLA28XX_AUX_IMG_STATUS_SIGN;
8175 }
8176
8177 static bool
qla27xx_check_image_status_signature(struct qla27xx_image_status * image_status)8178 qla27xx_check_image_status_signature(struct qla27xx_image_status *image_status)
8179 {
8180 ulong signature = le32_to_cpu(image_status->signature);
8181
8182 return
8183 signature != QLA27XX_IMG_STATUS_SIGN &&
8184 signature != QLA28XX_IMG_STATUS_SIGN;
8185 }
8186
8187 static ulong
qla27xx_image_status_checksum(struct qla27xx_image_status * image_status)8188 qla27xx_image_status_checksum(struct qla27xx_image_status *image_status)
8189 {
8190 __le32 *p = (__force __le32 *)image_status;
8191 uint n = sizeof(*image_status) / sizeof(*p);
8192 uint32_t sum = 0;
8193
8194 for ( ; n--; p++)
8195 sum += le32_to_cpup(p);
8196
8197 return sum;
8198 }
8199
8200 static inline uint
qla28xx_component_bitmask(struct qla27xx_image_status * aux,uint bitmask)8201 qla28xx_component_bitmask(struct qla27xx_image_status *aux, uint bitmask)
8202 {
8203 return aux->bitmap & bitmask ?
8204 QLA27XX_SECONDARY_IMAGE : QLA27XX_PRIMARY_IMAGE;
8205 }
8206
8207 static void
qla28xx_component_status(struct active_regions * active_regions,struct qla27xx_image_status * aux)8208 qla28xx_component_status(
8209 struct active_regions *active_regions, struct qla27xx_image_status *aux)
8210 {
8211 active_regions->aux.board_config =
8212 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_BOARD_CONFIG);
8213
8214 active_regions->aux.vpd_nvram =
8215 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_VPD_NVRAM);
8216
8217 active_regions->aux.npiv_config_0_1 =
8218 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_0_1);
8219
8220 active_regions->aux.npiv_config_2_3 =
8221 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_2_3);
8222
8223 active_regions->aux.nvme_params =
8224 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NVME_PARAMS);
8225 }
8226
8227 static int
qla27xx_compare_image_generation(struct qla27xx_image_status * pri_image_status,struct qla27xx_image_status * sec_image_status)8228 qla27xx_compare_image_generation(
8229 struct qla27xx_image_status *pri_image_status,
8230 struct qla27xx_image_status *sec_image_status)
8231 {
8232 /* calculate generation delta as uint16 (this accounts for wrap) */
8233 int16_t delta =
8234 le16_to_cpu(pri_image_status->generation) -
8235 le16_to_cpu(sec_image_status->generation);
8236
8237 ql_dbg(ql_dbg_init, NULL, 0x0180, "generation delta = %d\n", delta);
8238
8239 return delta;
8240 }
8241
8242 void
qla28xx_get_aux_images(struct scsi_qla_host * vha,struct active_regions * active_regions)8243 qla28xx_get_aux_images(
8244 struct scsi_qla_host *vha, struct active_regions *active_regions)
8245 {
8246 struct qla_hw_data *ha = vha->hw;
8247 struct qla27xx_image_status pri_aux_image_status, sec_aux_image_status;
8248 bool valid_pri_image = false, valid_sec_image = false;
8249 bool active_pri_image = false, active_sec_image = false;
8250 int rc;
8251
8252 if (!ha->flt_region_aux_img_status_pri) {
8253 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary aux image not addressed\n");
8254 goto check_sec_image;
8255 }
8256
8257 rc = qla24xx_read_flash_data(vha, (uint32_t *)&pri_aux_image_status,
8258 ha->flt_region_aux_img_status_pri,
8259 sizeof(pri_aux_image_status) >> 2);
8260 if (rc) {
8261 ql_log(ql_log_info, vha, 0x01a1,
8262 "Unable to read Primary aux image(%x).\n", rc);
8263 goto check_sec_image;
8264 }
8265 qla27xx_print_image(vha, "Primary aux image", &pri_aux_image_status);
8266
8267 if (qla28xx_check_aux_image_status_signature(&pri_aux_image_status)) {
8268 ql_dbg(ql_dbg_init, vha, 0x018b,
8269 "Primary aux image signature (%#x) not valid\n",
8270 le32_to_cpu(pri_aux_image_status.signature));
8271 goto check_sec_image;
8272 }
8273
8274 if (qla27xx_image_status_checksum(&pri_aux_image_status)) {
8275 ql_dbg(ql_dbg_init, vha, 0x018c,
8276 "Primary aux image checksum failed\n");
8277 goto check_sec_image;
8278 }
8279
8280 valid_pri_image = true;
8281
8282 if (pri_aux_image_status.image_status_mask & 1) {
8283 ql_dbg(ql_dbg_init, vha, 0x018d,
8284 "Primary aux image is active\n");
8285 active_pri_image = true;
8286 }
8287
8288 check_sec_image:
8289 if (!ha->flt_region_aux_img_status_sec) {
8290 ql_dbg(ql_dbg_init, vha, 0x018a,
8291 "Secondary aux image not addressed\n");
8292 goto check_valid_image;
8293 }
8294
8295 rc = qla24xx_read_flash_data(vha, (uint32_t *)&sec_aux_image_status,
8296 ha->flt_region_aux_img_status_sec,
8297 sizeof(sec_aux_image_status) >> 2);
8298 if (rc) {
8299 ql_log(ql_log_info, vha, 0x01a2,
8300 "Unable to read Secondary aux image(%x).\n", rc);
8301 goto check_valid_image;
8302 }
8303
8304 qla27xx_print_image(vha, "Secondary aux image", &sec_aux_image_status);
8305
8306 if (qla28xx_check_aux_image_status_signature(&sec_aux_image_status)) {
8307 ql_dbg(ql_dbg_init, vha, 0x018b,
8308 "Secondary aux image signature (%#x) not valid\n",
8309 le32_to_cpu(sec_aux_image_status.signature));
8310 goto check_valid_image;
8311 }
8312
8313 if (qla27xx_image_status_checksum(&sec_aux_image_status)) {
8314 ql_dbg(ql_dbg_init, vha, 0x018c,
8315 "Secondary aux image checksum failed\n");
8316 goto check_valid_image;
8317 }
8318
8319 valid_sec_image = true;
8320
8321 if (sec_aux_image_status.image_status_mask & 1) {
8322 ql_dbg(ql_dbg_init, vha, 0x018d,
8323 "Secondary aux image is active\n");
8324 active_sec_image = true;
8325 }
8326
8327 check_valid_image:
8328 if (valid_pri_image && active_pri_image &&
8329 valid_sec_image && active_sec_image) {
8330 if (qla27xx_compare_image_generation(&pri_aux_image_status,
8331 &sec_aux_image_status) >= 0) {
8332 qla28xx_component_status(active_regions,
8333 &pri_aux_image_status);
8334 } else {
8335 qla28xx_component_status(active_regions,
8336 &sec_aux_image_status);
8337 }
8338 } else if (valid_pri_image && active_pri_image) {
8339 qla28xx_component_status(active_regions, &pri_aux_image_status);
8340 } else if (valid_sec_image && active_sec_image) {
8341 qla28xx_component_status(active_regions, &sec_aux_image_status);
8342 }
8343
8344 ql_dbg(ql_dbg_init, vha, 0x018f,
8345 "aux images active: BCFG=%u VPD/NVR=%u NPIV0/1=%u NPIV2/3=%u, NVME=%u\n",
8346 active_regions->aux.board_config,
8347 active_regions->aux.vpd_nvram,
8348 active_regions->aux.npiv_config_0_1,
8349 active_regions->aux.npiv_config_2_3,
8350 active_regions->aux.nvme_params);
8351 }
8352
8353 void
qla27xx_get_active_image(struct scsi_qla_host * vha,struct active_regions * active_regions)8354 qla27xx_get_active_image(struct scsi_qla_host *vha,
8355 struct active_regions *active_regions)
8356 {
8357 struct qla_hw_data *ha = vha->hw;
8358 struct qla27xx_image_status pri_image_status, sec_image_status;
8359 bool valid_pri_image = false, valid_sec_image = false;
8360 bool active_pri_image = false, active_sec_image = false;
8361 int rc;
8362
8363 if (!ha->flt_region_img_status_pri) {
8364 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary image not addressed\n");
8365 goto check_sec_image;
8366 }
8367
8368 if (qla24xx_read_flash_data(vha, (uint32_t *)&pri_image_status,
8369 ha->flt_region_img_status_pri, sizeof(pri_image_status) >> 2) !=
8370 QLA_SUCCESS) {
8371 WARN_ON_ONCE(true);
8372 goto check_sec_image;
8373 }
8374 qla27xx_print_image(vha, "Primary image", &pri_image_status);
8375
8376 if (qla27xx_check_image_status_signature(&pri_image_status)) {
8377 ql_dbg(ql_dbg_init, vha, 0x018b,
8378 "Primary image signature (%#x) not valid\n",
8379 le32_to_cpu(pri_image_status.signature));
8380 goto check_sec_image;
8381 }
8382
8383 if (qla27xx_image_status_checksum(&pri_image_status)) {
8384 ql_dbg(ql_dbg_init, vha, 0x018c,
8385 "Primary image checksum failed\n");
8386 goto check_sec_image;
8387 }
8388
8389 valid_pri_image = true;
8390
8391 if (pri_image_status.image_status_mask & 1) {
8392 ql_dbg(ql_dbg_init, vha, 0x018d,
8393 "Primary image is active\n");
8394 active_pri_image = true;
8395 }
8396
8397 check_sec_image:
8398 if (!ha->flt_region_img_status_sec) {
8399 ql_dbg(ql_dbg_init, vha, 0x018a, "Secondary image not addressed\n");
8400 goto check_valid_image;
8401 }
8402
8403 rc = qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
8404 ha->flt_region_img_status_sec, sizeof(sec_image_status) >> 2);
8405 if (rc) {
8406 ql_log(ql_log_info, vha, 0x01a3,
8407 "Unable to read Secondary image status(%x).\n", rc);
8408 goto check_valid_image;
8409 }
8410
8411 qla27xx_print_image(vha, "Secondary image", &sec_image_status);
8412
8413 if (qla27xx_check_image_status_signature(&sec_image_status)) {
8414 ql_dbg(ql_dbg_init, vha, 0x018b,
8415 "Secondary image signature (%#x) not valid\n",
8416 le32_to_cpu(sec_image_status.signature));
8417 goto check_valid_image;
8418 }
8419
8420 if (qla27xx_image_status_checksum(&sec_image_status)) {
8421 ql_dbg(ql_dbg_init, vha, 0x018c,
8422 "Secondary image checksum failed\n");
8423 goto check_valid_image;
8424 }
8425
8426 valid_sec_image = true;
8427
8428 if (sec_image_status.image_status_mask & 1) {
8429 ql_dbg(ql_dbg_init, vha, 0x018d,
8430 "Secondary image is active\n");
8431 active_sec_image = true;
8432 }
8433
8434 check_valid_image:
8435 if (valid_pri_image && active_pri_image)
8436 active_regions->global = QLA27XX_PRIMARY_IMAGE;
8437
8438 if (valid_sec_image && active_sec_image) {
8439 if (!active_regions->global ||
8440 qla27xx_compare_image_generation(
8441 &pri_image_status, &sec_image_status) < 0) {
8442 active_regions->global = QLA27XX_SECONDARY_IMAGE;
8443 }
8444 }
8445
8446 ql_dbg(ql_dbg_init, vha, 0x018f, "active image %s (%u)\n",
8447 active_regions->global == QLA27XX_DEFAULT_IMAGE ?
8448 "default (boot/fw)" :
8449 active_regions->global == QLA27XX_PRIMARY_IMAGE ?
8450 "primary" :
8451 active_regions->global == QLA27XX_SECONDARY_IMAGE ?
8452 "secondary" : "invalid",
8453 active_regions->global);
8454 }
8455
qla24xx_risc_firmware_invalid(uint32_t * dword)8456 bool qla24xx_risc_firmware_invalid(uint32_t *dword)
8457 {
8458 return
8459 !(dword[4] | dword[5] | dword[6] | dword[7]) ||
8460 !(~dword[4] | ~dword[5] | ~dword[6] | ~dword[7]);
8461 }
8462
8463 static int
qla28xx_get_srisc_addr(scsi_qla_host_t * vha,uint32_t * srisc_addr,uint32_t faddr)8464 qla28xx_get_srisc_addr(scsi_qla_host_t *vha, uint32_t *srisc_addr,
8465 uint32_t faddr)
8466 {
8467 struct qla_hw_data *ha = vha->hw;
8468 struct req_que *req = ha->req_q_map[0];
8469 uint32_t *dcode;
8470 int rval;
8471
8472 *srisc_addr = 0;
8473 dcode = (uint32_t *)req->ring;
8474
8475 rval = qla24xx_read_flash_data(vha, dcode, faddr, 10);
8476 if (rval) {
8477 ql_log(ql_log_fatal, vha, 0x01aa,
8478 "-> Failed to read flash addr + size .\n");
8479 return QLA_FUNCTION_FAILED;
8480 }
8481
8482 *srisc_addr = be32_to_cpu((__force __be32)dcode[2]);
8483 return QLA_SUCCESS;
8484 }
8485
8486 static int
qla28xx_load_fw_template(scsi_qla_host_t * vha,uint32_t faddr)8487 qla28xx_load_fw_template(scsi_qla_host_t *vha, uint32_t faddr)
8488 {
8489 struct qla_hw_data *ha = vha->hw;
8490 struct fwdt *fwdt = ha->fwdt;
8491 struct req_que *req = ha->req_q_map[0];
8492 uint32_t risc_size, risc_attr = 0;
8493 uint templates, segments, fragment;
8494 uint32_t *dcode;
8495 ulong dlen;
8496 int rval;
8497 uint j;
8498
8499 dcode = (uint32_t *)req->ring;
8500 segments = FA_RISC_CODE_SEGMENTS;
8501
8502 for (j = 0; j < segments; j++) {
8503 rval = qla24xx_read_flash_data(vha, dcode, faddr, 10);
8504 if (rval) {
8505 ql_log(ql_log_fatal, vha, 0x01a1,
8506 "-> Failed to read flash addr + size .\n");
8507 return QLA_FUNCTION_FAILED;
8508 }
8509
8510 risc_size = be32_to_cpu((__force __be32)dcode[3]);
8511
8512 if (risc_attr == 0)
8513 risc_attr = be32_to_cpu((__force __be32)dcode[9]);
8514
8515 dlen = ha->fw_transfer_size >> 2;
8516 for (fragment = 0; fragment < risc_size; fragment++) {
8517 if (dlen > risc_size)
8518 dlen = risc_size;
8519
8520 faddr += dlen;
8521 risc_size -= dlen;
8522 }
8523 }
8524
8525 templates = (risc_attr & BIT_9) ? 2 : 1;
8526
8527 ql_dbg(ql_dbg_init, vha, 0x01a1, "-> templates = %u\n", templates);
8528
8529 for (j = 0; j < templates; j++, fwdt++) {
8530 vfree(fwdt->template);
8531 fwdt->template = NULL;
8532 fwdt->length = 0;
8533
8534 dcode = (uint32_t *)req->ring;
8535
8536 rval = qla24xx_read_flash_data(vha, dcode, faddr, 7);
8537 if (rval) {
8538 ql_log(ql_log_fatal, vha, 0x01a2,
8539 "-> Unable to read template size.\n");
8540 goto failed;
8541 }
8542
8543 risc_size = be32_to_cpu((__force __be32)dcode[2]);
8544 ql_dbg(ql_dbg_init, vha, 0x01a3,
8545 "-> fwdt%u template array at %#x (%#x dwords)\n",
8546 j, faddr, risc_size);
8547 if (!risc_size || !~risc_size) {
8548 ql_dbg(ql_dbg_init, vha, 0x01a4,
8549 "-> fwdt%u failed to read array\n", j);
8550 goto failed;
8551 }
8552
8553 /* skip header and ignore checksum */
8554 faddr += 7;
8555 risc_size -= 8;
8556
8557 ql_dbg(ql_dbg_init, vha, 0x01a5,
8558 "-> fwdt%u template allocate template %#x words...\n",
8559 j, risc_size);
8560 fwdt->template = vmalloc(risc_size * sizeof(*dcode));
8561 if (!fwdt->template) {
8562 ql_log(ql_log_warn, vha, 0x01a6,
8563 "-> fwdt%u failed allocate template.\n", j);
8564 goto failed;
8565 }
8566
8567 dcode = fwdt->template;
8568 rval = qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
8569
8570 if (rval || !qla27xx_fwdt_template_valid(dcode)) {
8571 ql_log(ql_log_warn, vha, 0x01a7,
8572 "-> fwdt%u failed template validate (rval %x)\n",
8573 j, rval);
8574 goto failed;
8575 }
8576
8577 dlen = qla27xx_fwdt_template_size(dcode);
8578 ql_dbg(ql_dbg_init, vha, 0x01a7,
8579 "-> fwdt%u template size %#lx bytes (%#lx words)\n",
8580 j, dlen, dlen / sizeof(*dcode));
8581 if (dlen > risc_size * sizeof(*dcode)) {
8582 ql_log(ql_log_warn, vha, 0x01a8,
8583 "-> fwdt%u template exceeds array (%-lu bytes)\n",
8584 j, dlen - risc_size * sizeof(*dcode));
8585 goto failed;
8586 }
8587
8588 fwdt->length = dlen;
8589 ql_dbg(ql_dbg_init, vha, 0x01a9,
8590 "-> fwdt%u loaded template ok\n", j);
8591
8592 faddr += risc_size + 1;
8593 }
8594
8595 return QLA_SUCCESS;
8596
8597 failed:
8598 vfree(fwdt->template);
8599 fwdt->template = NULL;
8600 fwdt->length = 0;
8601
8602 return QLA_SUCCESS;
8603 }
8604
8605 static int
qla24xx_load_risc_flash(scsi_qla_host_t * vha,uint32_t * srisc_addr,uint32_t faddr)8606 qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
8607 uint32_t faddr)
8608 {
8609 int rval;
8610 uint templates, segments, fragment;
8611 ulong i;
8612 uint j;
8613 ulong dlen;
8614 uint32_t *dcode;
8615 uint32_t risc_addr, risc_size, risc_attr = 0;
8616 struct qla_hw_data *ha = vha->hw;
8617 struct req_que *req = ha->req_q_map[0];
8618 struct fwdt *fwdt = ha->fwdt;
8619
8620 ql_dbg(ql_dbg_init, vha, 0x008b,
8621 "FW: Loading firmware from flash (%x).\n", faddr);
8622
8623 dcode = (uint32_t *)req->ring;
8624 rval = qla24xx_read_flash_data(vha, dcode, faddr, 8);
8625 if (rval || qla24xx_risc_firmware_invalid(dcode)) {
8626 ql_log(ql_log_fatal, vha, 0x008c,
8627 "Unable to verify the integrity of flash firmware image (rval %x).\n", rval);
8628 ql_log(ql_log_fatal, vha, 0x008d,
8629 "Firmware data: %08x %08x %08x %08x.\n",
8630 dcode[0], dcode[1], dcode[2], dcode[3]);
8631
8632 return QLA_FUNCTION_FAILED;
8633 }
8634
8635 dcode = (uint32_t *)req->ring;
8636 *srisc_addr = 0;
8637 segments = FA_RISC_CODE_SEGMENTS;
8638 for (j = 0; j < segments; j++) {
8639 ql_dbg(ql_dbg_init, vha, 0x008d,
8640 "-> Loading segment %u...\n", j);
8641 rval = qla24xx_read_flash_data(vha, dcode, faddr, 10);
8642 if (rval) {
8643 ql_log(ql_log_fatal, vha, 0x016a,
8644 "-> Unable to read segment addr + size .\n");
8645 return QLA_FUNCTION_FAILED;
8646 }
8647 risc_addr = be32_to_cpu((__force __be32)dcode[2]);
8648 risc_size = be32_to_cpu((__force __be32)dcode[3]);
8649 if (!*srisc_addr) {
8650 *srisc_addr = risc_addr;
8651 risc_attr = be32_to_cpu((__force __be32)dcode[9]);
8652 }
8653
8654 dlen = ha->fw_transfer_size >> 2;
8655 for (fragment = 0; risc_size; fragment++) {
8656 if (dlen > risc_size)
8657 dlen = risc_size;
8658
8659 ql_dbg(ql_dbg_init, vha, 0x008e,
8660 "-> Loading fragment %u: %#x <- %#x (%#lx dwords)...\n",
8661 fragment, risc_addr, faddr, dlen);
8662 rval = qla24xx_read_flash_data(vha, dcode, faddr, dlen);
8663 if (rval) {
8664 ql_log(ql_log_fatal, vha, 0x016b,
8665 "-> Unable to read fragment(faddr %#x dlen %#lx).\n",
8666 faddr, dlen);
8667 return QLA_FUNCTION_FAILED;
8668 }
8669 for (i = 0; i < dlen; i++)
8670 dcode[i] = swab32(dcode[i]);
8671
8672 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen);
8673 if (rval) {
8674 ql_log(ql_log_fatal, vha, 0x008f,
8675 "-> Failed load firmware fragment %u.\n",
8676 fragment);
8677 return QLA_FUNCTION_FAILED;
8678 }
8679
8680 faddr += dlen;
8681 risc_addr += dlen;
8682 risc_size -= dlen;
8683 }
8684 }
8685
8686 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
8687 return QLA_SUCCESS;
8688
8689 templates = (risc_attr & BIT_9) ? 2 : 1;
8690 ql_dbg(ql_dbg_init, vha, 0x0160, "-> templates = %u\n", templates);
8691 for (j = 0; j < templates; j++, fwdt++) {
8692 vfree(fwdt->template);
8693 fwdt->template = NULL;
8694 fwdt->length = 0;
8695
8696 dcode = (uint32_t *)req->ring;
8697
8698 rval = qla24xx_read_flash_data(vha, dcode, faddr, 7);
8699 if (rval) {
8700 ql_log(ql_log_fatal, vha, 0x016c,
8701 "-> Unable to read template size.\n");
8702 goto failed;
8703 }
8704
8705 risc_size = be32_to_cpu((__force __be32)dcode[2]);
8706 ql_dbg(ql_dbg_init, vha, 0x0161,
8707 "-> fwdt%u template array at %#x (%#x dwords)\n",
8708 j, faddr, risc_size);
8709 if (!risc_size || !~risc_size) {
8710 ql_dbg(ql_dbg_init, vha, 0x0162,
8711 "-> fwdt%u failed to read array\n", j);
8712 goto failed;
8713 }
8714
8715 /* skip header and ignore checksum */
8716 faddr += 7;
8717 risc_size -= 8;
8718
8719 ql_dbg(ql_dbg_init, vha, 0x0163,
8720 "-> fwdt%u template allocate template %#x words...\n",
8721 j, risc_size);
8722 fwdt->template = vmalloc_array(risc_size, sizeof(*dcode));
8723 if (!fwdt->template) {
8724 ql_log(ql_log_warn, vha, 0x0164,
8725 "-> fwdt%u failed allocate template.\n", j);
8726 goto failed;
8727 }
8728
8729 dcode = fwdt->template;
8730 rval = qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
8731
8732 if (rval || !qla27xx_fwdt_template_valid(dcode)) {
8733 ql_log(ql_log_warn, vha, 0x0165,
8734 "-> fwdt%u failed template validate (rval %x)\n",
8735 j, rval);
8736 goto failed;
8737 }
8738
8739 dlen = qla27xx_fwdt_template_size(dcode);
8740 ql_dbg(ql_dbg_init, vha, 0x0166,
8741 "-> fwdt%u template size %#lx bytes (%#lx words)\n",
8742 j, dlen, dlen / sizeof(*dcode));
8743 if (dlen > risc_size * sizeof(*dcode)) {
8744 ql_log(ql_log_warn, vha, 0x0167,
8745 "-> fwdt%u template exceeds array (%-lu bytes)\n",
8746 j, dlen - risc_size * sizeof(*dcode));
8747 goto failed;
8748 }
8749
8750 fwdt->length = dlen;
8751 ql_dbg(ql_dbg_init, vha, 0x0168,
8752 "-> fwdt%u loaded template ok\n", j);
8753
8754 faddr += risc_size + 1;
8755 }
8756
8757 return QLA_SUCCESS;
8758
8759 failed:
8760 vfree(fwdt->template);
8761 fwdt->template = NULL;
8762 fwdt->length = 0;
8763
8764 return QLA_SUCCESS;
8765 }
8766
8767 int
qla2x00_load_risc(scsi_qla_host_t * vha,uint32_t * srisc_addr)8768 qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8769 {
8770 int rval;
8771 int i, fragment;
8772 uint16_t *wcode;
8773 __be16 *fwcode;
8774 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
8775 struct fw_blob *blob;
8776 struct qla_hw_data *ha = vha->hw;
8777 struct req_que *req = ha->req_q_map[0];
8778
8779 /* Load firmware blob. */
8780 blob = qla2x00_request_firmware(vha);
8781 if (!blob) {
8782 ql_log(ql_log_info, vha, 0x0083,
8783 "Firmware image unavailable.\n");
8784 return QLA_FUNCTION_FAILED;
8785 }
8786
8787 rval = QLA_SUCCESS;
8788
8789 wcode = (uint16_t *)req->ring;
8790 *srisc_addr = 0;
8791 fwcode = (__force __be16 *)blob->fw->data;
8792 fwclen = 0;
8793
8794 /* Validate firmware image by checking version. */
8795 if (blob->fw->size < 8 * sizeof(uint16_t)) {
8796 ql_log(ql_log_fatal, vha, 0x0085,
8797 "Unable to verify integrity of firmware image (%zd).\n",
8798 blob->fw->size);
8799 goto fail_fw_integrity;
8800 }
8801 for (i = 0; i < 4; i++)
8802 wcode[i] = be16_to_cpu(fwcode[i + 4]);
8803 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
8804 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
8805 wcode[2] == 0 && wcode[3] == 0)) {
8806 ql_log(ql_log_fatal, vha, 0x0086,
8807 "Unable to verify integrity of firmware image.\n");
8808 ql_log(ql_log_fatal, vha, 0x0087,
8809 "Firmware data: %04x %04x %04x %04x.\n",
8810 wcode[0], wcode[1], wcode[2], wcode[3]);
8811 goto fail_fw_integrity;
8812 }
8813
8814 seg = blob->segs;
8815 while (*seg && rval == QLA_SUCCESS) {
8816 risc_addr = *seg;
8817 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
8818 risc_size = be16_to_cpu(fwcode[3]);
8819
8820 /* Validate firmware image size. */
8821 fwclen += risc_size * sizeof(uint16_t);
8822 if (blob->fw->size < fwclen) {
8823 ql_log(ql_log_fatal, vha, 0x0088,
8824 "Unable to verify integrity of firmware image "
8825 "(%zd).\n", blob->fw->size);
8826 goto fail_fw_integrity;
8827 }
8828
8829 fragment = 0;
8830 while (risc_size > 0 && rval == QLA_SUCCESS) {
8831 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
8832 if (wlen > risc_size)
8833 wlen = risc_size;
8834 ql_dbg(ql_dbg_init, vha, 0x0089,
8835 "Loading risc segment@ risc addr %x number of "
8836 "words 0x%x.\n", risc_addr, wlen);
8837
8838 for (i = 0; i < wlen; i++)
8839 wcode[i] = swab16((__force u32)fwcode[i]);
8840
8841 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
8842 wlen);
8843 if (rval) {
8844 ql_log(ql_log_fatal, vha, 0x008a,
8845 "Failed to load segment %d of firmware.\n",
8846 fragment);
8847 break;
8848 }
8849
8850 fwcode += wlen;
8851 risc_addr += wlen;
8852 risc_size -= wlen;
8853 fragment++;
8854 }
8855
8856 /* Next segment. */
8857 seg++;
8858 }
8859 return rval;
8860
8861 fail_fw_integrity:
8862 return QLA_FUNCTION_FAILED;
8863 }
8864
8865 static int
qla24xx_load_risc_blob(scsi_qla_host_t * vha,uint32_t * srisc_addr)8866 qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8867 {
8868 int rval;
8869 uint templates, segments, fragment;
8870 uint32_t *dcode;
8871 ulong dlen;
8872 uint32_t risc_addr, risc_size, risc_attr = 0;
8873 ulong i;
8874 uint j;
8875 struct fw_blob *blob;
8876 __be32 *fwcode;
8877 struct qla_hw_data *ha = vha->hw;
8878 struct req_que *req = ha->req_q_map[0];
8879 struct fwdt *fwdt = ha->fwdt;
8880
8881 ql_dbg(ql_dbg_init, vha, 0x0090,
8882 "-> FW: Loading via request-firmware.\n");
8883
8884 blob = qla2x00_request_firmware(vha);
8885 if (!blob) {
8886 ql_log(ql_log_warn, vha, 0x0092,
8887 "-> Firmware file not found.\n");
8888
8889 return QLA_FUNCTION_FAILED;
8890 }
8891
8892 fwcode = (__force __be32 *)blob->fw->data;
8893 dcode = (__force uint32_t *)fwcode;
8894 if (qla24xx_risc_firmware_invalid(dcode)) {
8895 ql_log(ql_log_fatal, vha, 0x0093,
8896 "Unable to verify integrity of firmware image (%zd).\n",
8897 blob->fw->size);
8898 ql_log(ql_log_fatal, vha, 0x0095,
8899 "Firmware data: %08x %08x %08x %08x.\n",
8900 dcode[0], dcode[1], dcode[2], dcode[3]);
8901 return QLA_FUNCTION_FAILED;
8902 }
8903
8904 dcode = (uint32_t *)req->ring;
8905 *srisc_addr = 0;
8906 segments = FA_RISC_CODE_SEGMENTS;
8907 for (j = 0; j < segments; j++) {
8908 ql_dbg(ql_dbg_init, vha, 0x0096,
8909 "-> Loading segment %u...\n", j);
8910 risc_addr = be32_to_cpu(fwcode[2]);
8911 risc_size = be32_to_cpu(fwcode[3]);
8912
8913 if (!*srisc_addr) {
8914 *srisc_addr = risc_addr;
8915 risc_attr = be32_to_cpu(fwcode[9]);
8916 }
8917
8918 dlen = ha->fw_transfer_size >> 2;
8919 for (fragment = 0; risc_size; fragment++) {
8920 if (dlen > risc_size)
8921 dlen = risc_size;
8922
8923 ql_dbg(ql_dbg_init, vha, 0x0097,
8924 "-> Loading fragment %u: %#x <- %#x (%#lx words)...\n",
8925 fragment, risc_addr,
8926 (uint32_t)(fwcode - (typeof(fwcode))blob->fw->data),
8927 dlen);
8928
8929 for (i = 0; i < dlen; i++)
8930 dcode[i] = swab32((__force u32)fwcode[i]);
8931
8932 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen);
8933 if (rval) {
8934 ql_log(ql_log_fatal, vha, 0x0098,
8935 "-> Failed load firmware fragment %u.\n",
8936 fragment);
8937 return QLA_FUNCTION_FAILED;
8938 }
8939
8940 fwcode += dlen;
8941 risc_addr += dlen;
8942 risc_size -= dlen;
8943 }
8944 }
8945
8946 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
8947 return QLA_SUCCESS;
8948
8949 templates = (risc_attr & BIT_9) ? 2 : 1;
8950 ql_dbg(ql_dbg_init, vha, 0x0170, "-> templates = %u\n", templates);
8951 for (j = 0; j < templates; j++, fwdt++) {
8952 vfree(fwdt->template);
8953 fwdt->template = NULL;
8954 fwdt->length = 0;
8955
8956 risc_size = be32_to_cpu(fwcode[2]);
8957 ql_dbg(ql_dbg_init, vha, 0x0171,
8958 "-> fwdt%u template array at %#x (%#x dwords)\n",
8959 j, (uint32_t)((void *)fwcode - (void *)blob->fw->data),
8960 risc_size);
8961 if (!risc_size || !~risc_size) {
8962 ql_dbg(ql_dbg_init, vha, 0x0172,
8963 "-> fwdt%u failed to read array\n", j);
8964 goto failed;
8965 }
8966
8967 /* skip header and ignore checksum */
8968 fwcode += 7;
8969 risc_size -= 8;
8970
8971 ql_dbg(ql_dbg_init, vha, 0x0173,
8972 "-> fwdt%u template allocate template %#x words...\n",
8973 j, risc_size);
8974 fwdt->template = vmalloc_array(risc_size, sizeof(*dcode));
8975 if (!fwdt->template) {
8976 ql_log(ql_log_warn, vha, 0x0174,
8977 "-> fwdt%u failed allocate template.\n", j);
8978 goto failed;
8979 }
8980
8981 dcode = fwdt->template;
8982 for (i = 0; i < risc_size; i++)
8983 dcode[i] = (__force u32)fwcode[i];
8984
8985 if (!qla27xx_fwdt_template_valid(dcode)) {
8986 ql_log(ql_log_warn, vha, 0x0175,
8987 "-> fwdt%u failed template validate\n", j);
8988 goto failed;
8989 }
8990
8991 dlen = qla27xx_fwdt_template_size(dcode);
8992 ql_dbg(ql_dbg_init, vha, 0x0176,
8993 "-> fwdt%u template size %#lx bytes (%#lx words)\n",
8994 j, dlen, dlen / sizeof(*dcode));
8995 if (dlen > risc_size * sizeof(*dcode)) {
8996 ql_log(ql_log_warn, vha, 0x0177,
8997 "-> fwdt%u template exceeds array (%-lu bytes)\n",
8998 j, dlen - risc_size * sizeof(*dcode));
8999 goto failed;
9000 }
9001
9002 fwdt->length = dlen;
9003 ql_dbg(ql_dbg_init, vha, 0x0178,
9004 "-> fwdt%u loaded template ok\n", j);
9005
9006 fwcode += risc_size + 1;
9007 }
9008
9009 return QLA_SUCCESS;
9010
9011 failed:
9012 vfree(fwdt->template);
9013 fwdt->template = NULL;
9014 fwdt->length = 0;
9015
9016 return QLA_SUCCESS;
9017 }
9018
9019 int
qla24xx_load_risc(scsi_qla_host_t * vha,uint32_t * srisc_addr)9020 qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
9021 {
9022 int rval;
9023
9024 if (ql2xfwloadbin == 1)
9025 return qla81xx_load_risc(vha, srisc_addr);
9026
9027 /*
9028 * FW Load priority:
9029 * 1) Firmware via request-firmware interface (.bin file).
9030 * 2) Firmware residing in flash.
9031 */
9032 rval = qla24xx_load_risc_blob(vha, srisc_addr);
9033 if (rval == QLA_SUCCESS)
9034 return rval;
9035
9036 return qla24xx_load_risc_flash(vha, srisc_addr,
9037 vha->hw->flt_region_fw);
9038 }
9039
9040 int
qla81xx_load_risc(scsi_qla_host_t * vha,uint32_t * srisc_addr)9041 qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
9042 {
9043 int rval;
9044 uint32_t f_region = 0;
9045 struct qla_hw_data *ha = vha->hw;
9046 struct active_regions active_regions = { };
9047
9048 if (ql2xfwloadbin == 2 && !IS_QLA28XX(ha))
9049 goto try_blob_fw;
9050
9051 /* FW Load priority:
9052 * 1) If 28xxx, ROM cmd to load flash firmware.
9053 * 2) Firmware residing in flash.
9054 * 3) Firmware via request-firmware interface (.bin file).
9055 * 4) Golden-Firmware residing in flash -- (limited operation).
9056 */
9057
9058 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
9059 goto try_primary_fw;
9060
9061 qla27xx_get_active_image(vha, &active_regions);
9062
9063 /* For 28XXX, always load the flash firmware using rom mbx */
9064 if (IS_QLA28XX_SECURED(ha)) {
9065 rval = qla28xx_load_flash_firmware(vha);
9066 if (rval != QLA_SUCCESS) {
9067 ql_log(ql_log_fatal, vha, 0x019e,
9068 "Failed to load flash firmware.\n");
9069 goto exit_load_risc;
9070 }
9071
9072 f_region =
9073 (active_regions.global != QLA27XX_SECONDARY_IMAGE) ?
9074 ha->flt_region_fw : ha->flt_region_fw_sec;
9075
9076 ql_log(ql_log_info, vha, 0x019f,
9077 "Load flash firmware successful (%s).\n",
9078 ((active_regions.global != QLA27XX_SECONDARY_IMAGE) ?
9079 "Primary" : "Secondary"));
9080
9081 rval = qla28xx_get_srisc_addr(vha, srisc_addr, f_region);
9082 if (rval != QLA_SUCCESS) {
9083 ql_log(ql_log_warn, vha, 0x019f,
9084 "failed to read srisc address\n");
9085 goto exit_load_risc;
9086 }
9087
9088 rval = qla28xx_load_fw_template(vha, f_region);
9089 if (rval != QLA_SUCCESS) {
9090 ql_log(ql_log_warn, vha, 0x01a0,
9091 "failed to read firmware template\n");
9092 }
9093
9094 goto exit_load_risc;
9095 }
9096
9097 if (active_regions.global != QLA27XX_SECONDARY_IMAGE)
9098 goto try_primary_fw;
9099
9100 ql_dbg(ql_dbg_init, vha, 0x008b,
9101 "Loading secondary firmware image.\n");
9102 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw_sec);
9103 if (!rval)
9104 return rval;
9105
9106 try_primary_fw:
9107 ql_dbg(ql_dbg_init, vha, 0x008b,
9108 "Loading primary firmware image.\n");
9109 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
9110 if (!rval)
9111 return rval;
9112
9113 try_blob_fw:
9114 rval = qla24xx_load_risc_blob(vha, srisc_addr);
9115 if (!rval || !ha->flt_region_gold_fw)
9116 return rval;
9117
9118 ql_log(ql_log_info, vha, 0x0099,
9119 "Attempting to fallback to golden firmware.\n");
9120 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
9121 if (rval)
9122 return rval;
9123
9124 ql_log(ql_log_info, vha, 0x009a, "Need firmware flash update.\n");
9125 ha->flags.running_gold_fw = 1;
9126
9127 exit_load_risc:
9128 return rval;
9129 }
9130
9131 void
qla2x00_try_to_stop_firmware(scsi_qla_host_t * vha)9132 qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
9133 {
9134 int ret, retries;
9135 struct qla_hw_data *ha = vha->hw;
9136
9137 if (ha->flags.pci_channel_io_perm_failure)
9138 return;
9139 if (!IS_FWI2_CAPABLE(ha))
9140 return;
9141 if (!ha->fw_major_version)
9142 return;
9143 if (!ha->flags.fw_started)
9144 return;
9145
9146 ret = qla2x00_stop_firmware(vha);
9147 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
9148 ret != QLA_INVALID_COMMAND && retries ; retries--) {
9149 ha->isp_ops->reset_chip(vha);
9150 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
9151 continue;
9152 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
9153 continue;
9154 ql_log(ql_log_info, vha, 0x8015,
9155 "Attempting retry of stop-firmware command.\n");
9156 ret = qla2x00_stop_firmware(vha);
9157 }
9158
9159 QLA_FW_STOPPED(ha);
9160 ha->flags.fw_init_done = 0;
9161 }
9162
9163 int
qla24xx_configure_vhba(scsi_qla_host_t * vha)9164 qla24xx_configure_vhba(scsi_qla_host_t *vha)
9165 {
9166 int rval = QLA_SUCCESS;
9167 int rval2;
9168 uint16_t mb[MAILBOX_REGISTER_COUNT];
9169 struct qla_hw_data *ha = vha->hw;
9170 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
9171
9172 if (!vha->vp_idx)
9173 return -EINVAL;
9174
9175 rval = qla2x00_fw_ready(base_vha);
9176
9177 if (rval == QLA_SUCCESS) {
9178 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
9179 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
9180 }
9181
9182 vha->flags.management_server_logged_in = 0;
9183
9184 /* Login to SNS first */
9185 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
9186 BIT_1);
9187 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
9188 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
9189 ql_dbg(ql_dbg_init, vha, 0x0120,
9190 "Failed SNS login: loop_id=%x, rval2=%d\n",
9191 NPH_SNS, rval2);
9192 else
9193 ql_dbg(ql_dbg_init, vha, 0x0103,
9194 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
9195 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
9196 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
9197 return (QLA_FUNCTION_FAILED);
9198 }
9199
9200 atomic_set(&vha->loop_down_timer, 0);
9201 atomic_set(&vha->loop_state, LOOP_UP);
9202 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
9203 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
9204 rval = qla2x00_loop_resync(base_vha);
9205
9206 return rval;
9207 }
9208
9209 /* 84XX Support **************************************************************/
9210
9211 static LIST_HEAD(qla_cs84xx_list);
9212 static DEFINE_MUTEX(qla_cs84xx_mutex);
9213
9214 static struct qla_chip_state_84xx *
qla84xx_get_chip(struct scsi_qla_host * vha)9215 qla84xx_get_chip(struct scsi_qla_host *vha)
9216 {
9217 struct qla_chip_state_84xx *cs84xx;
9218 struct qla_hw_data *ha = vha->hw;
9219
9220 mutex_lock(&qla_cs84xx_mutex);
9221
9222 /* Find any shared 84xx chip. */
9223 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
9224 if (cs84xx->bus == ha->pdev->bus) {
9225 kref_get(&cs84xx->kref);
9226 goto done;
9227 }
9228 }
9229
9230 cs84xx = kzalloc_obj(*cs84xx);
9231 if (!cs84xx)
9232 goto done;
9233
9234 kref_init(&cs84xx->kref);
9235 spin_lock_init(&cs84xx->access_lock);
9236 mutex_init(&cs84xx->fw_update_mutex);
9237 cs84xx->bus = ha->pdev->bus;
9238
9239 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
9240 done:
9241 mutex_unlock(&qla_cs84xx_mutex);
9242 return cs84xx;
9243 }
9244
9245 static void
__qla84xx_chip_release(struct kref * kref)9246 __qla84xx_chip_release(struct kref *kref)
9247 {
9248 struct qla_chip_state_84xx *cs84xx =
9249 container_of(kref, struct qla_chip_state_84xx, kref);
9250
9251 mutex_lock(&qla_cs84xx_mutex);
9252 list_del(&cs84xx->list);
9253 mutex_unlock(&qla_cs84xx_mutex);
9254 kfree(cs84xx);
9255 }
9256
9257 void
qla84xx_put_chip(struct scsi_qla_host * vha)9258 qla84xx_put_chip(struct scsi_qla_host *vha)
9259 {
9260 struct qla_hw_data *ha = vha->hw;
9261
9262 if (ha->cs84xx)
9263 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
9264 }
9265
9266 static int
qla84xx_init_chip(scsi_qla_host_t * vha)9267 qla84xx_init_chip(scsi_qla_host_t *vha)
9268 {
9269 int rval;
9270 uint16_t status[2];
9271 struct qla_hw_data *ha = vha->hw;
9272
9273 mutex_lock(&ha->cs84xx->fw_update_mutex);
9274
9275 rval = qla84xx_verify_chip(vha, status);
9276
9277 mutex_unlock(&ha->cs84xx->fw_update_mutex);
9278
9279 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED :
9280 QLA_SUCCESS;
9281 }
9282
9283 /* 81XX Support **************************************************************/
9284
9285 int
qla81xx_nvram_config(scsi_qla_host_t * vha)9286 qla81xx_nvram_config(scsi_qla_host_t *vha)
9287 {
9288 int rval;
9289 struct init_cb_81xx *icb;
9290 struct nvram_81xx *nv;
9291 __le32 *dptr;
9292 uint8_t *dptr1, *dptr2;
9293 uint32_t chksum;
9294 uint16_t cnt;
9295 struct qla_hw_data *ha = vha->hw;
9296 uint32_t faddr;
9297 struct active_regions active_regions = { };
9298
9299 rval = QLA_SUCCESS;
9300 icb = (struct init_cb_81xx *)ha->init_cb;
9301 nv = ha->nvram;
9302
9303 /* Determine NVRAM starting address. */
9304 ha->nvram_size = sizeof(*nv);
9305 ha->vpd_size = FA_NVRAM_VPD_SIZE;
9306 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
9307 ha->vpd_size = FA_VPD_SIZE_82XX;
9308
9309 if (IS_QLA28XX(ha) || IS_QLA27XX(ha))
9310 qla28xx_get_aux_images(vha, &active_regions);
9311
9312 /* Get VPD data into cache */
9313 ha->vpd = ha->nvram + VPD_OFFSET;
9314
9315 faddr = ha->flt_region_vpd;
9316 if (IS_QLA28XX(ha)) {
9317 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE)
9318 faddr = ha->flt_region_vpd_sec;
9319 ql_dbg(ql_dbg_init, vha, 0x0110,
9320 "Loading %s nvram image.\n",
9321 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ?
9322 "primary" : "secondary");
9323 }
9324 ha->isp_ops->read_optrom(vha, ha->vpd, faddr << 2, ha->vpd_size);
9325
9326 /* Get NVRAM data into cache and calculate checksum. */
9327 faddr = ha->flt_region_nvram;
9328 if (IS_QLA28XX(ha)) {
9329 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE)
9330 faddr = ha->flt_region_nvram_sec;
9331 }
9332 ql_dbg(ql_dbg_init, vha, 0x0110,
9333 "Loading %s nvram image.\n",
9334 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ?
9335 "primary" : "secondary");
9336 ha->isp_ops->read_optrom(vha, ha->nvram, faddr << 2, ha->nvram_size);
9337
9338 dptr = (__force __le32 *)nv;
9339 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
9340 chksum += le32_to_cpu(*dptr);
9341
9342 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
9343 "Contents of NVRAM:\n");
9344 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
9345 nv, ha->nvram_size);
9346
9347 /* Bad NVRAM data, set defaults parameters. */
9348 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
9349 le16_to_cpu(nv->nvram_version) < ICB_VERSION) {
9350 /* Reset NVRAM data. */
9351 ql_log(ql_log_info, vha, 0x0073,
9352 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n",
9353 chksum, nv->id, le16_to_cpu(nv->nvram_version));
9354 ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, sizeof(*nv));
9355 ql_log(ql_log_info, vha, 0x0074,
9356 "Falling back to functioning (yet invalid -- WWPN) "
9357 "defaults.\n");
9358
9359 /*
9360 * Set default initialization control block.
9361 */
9362 memset(nv, 0, ha->nvram_size);
9363 nv->nvram_version = cpu_to_le16(ICB_VERSION);
9364 nv->version = cpu_to_le16(ICB_VERSION);
9365 nv->frame_payload_size = cpu_to_le16(2048);
9366 nv->execution_throttle = cpu_to_le16(0xFFFF);
9367 nv->exchange_count = cpu_to_le16(0);
9368 nv->port_name[0] = 0x21;
9369 nv->port_name[1] = 0x00 + ha->port_no + 1;
9370 nv->port_name[2] = 0x00;
9371 nv->port_name[3] = 0xe0;
9372 nv->port_name[4] = 0x8b;
9373 nv->port_name[5] = 0x1c;
9374 nv->port_name[6] = 0x55;
9375 nv->port_name[7] = 0x86;
9376 nv->node_name[0] = 0x20;
9377 nv->node_name[1] = 0x00;
9378 nv->node_name[2] = 0x00;
9379 nv->node_name[3] = 0xe0;
9380 nv->node_name[4] = 0x8b;
9381 nv->node_name[5] = 0x1c;
9382 nv->node_name[6] = 0x55;
9383 nv->node_name[7] = 0x86;
9384 nv->login_retry_count = cpu_to_le16(8);
9385 nv->interrupt_delay_timer = cpu_to_le16(0);
9386 nv->login_timeout = cpu_to_le16(0);
9387 nv->firmware_options_1 =
9388 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
9389 nv->firmware_options_2 = cpu_to_le32(2 << 4);
9390 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
9391 nv->firmware_options_3 = cpu_to_le32(2 << 13);
9392 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
9393 nv->efi_parameters = cpu_to_le32(0);
9394 nv->reset_delay = 5;
9395 nv->max_luns_per_target = cpu_to_le16(128);
9396 nv->port_down_retry_count = cpu_to_le16(30);
9397 nv->link_down_timeout = cpu_to_le16(180);
9398 nv->enode_mac[0] = 0x00;
9399 nv->enode_mac[1] = 0xC0;
9400 nv->enode_mac[2] = 0xDD;
9401 nv->enode_mac[3] = 0x04;
9402 nv->enode_mac[4] = 0x05;
9403 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
9404
9405 rval = 1;
9406 }
9407
9408 if (IS_T10_PI_CAPABLE(ha))
9409 nv->frame_payload_size &= cpu_to_le16(~7);
9410
9411 qlt_81xx_config_nvram_stage1(vha, nv);
9412
9413 /* Reset Initialization control block */
9414 memset(icb, 0, ha->init_cb_size);
9415
9416 /* Copy 1st segment. */
9417 dptr1 = (uint8_t *)icb;
9418 dptr2 = (uint8_t *)&nv->version;
9419 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
9420 while (cnt--)
9421 *dptr1++ = *dptr2++;
9422
9423 icb->login_retry_count = nv->login_retry_count;
9424
9425 /* Copy 2nd segment. */
9426 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
9427 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
9428 cnt = (uint8_t *)&icb->reserved_5 -
9429 (uint8_t *)&icb->interrupt_delay_timer;
9430 while (cnt--)
9431 *dptr1++ = *dptr2++;
9432
9433 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
9434 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
9435 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
9436 icb->enode_mac[0] = 0x00;
9437 icb->enode_mac[1] = 0xC0;
9438 icb->enode_mac[2] = 0xDD;
9439 icb->enode_mac[3] = 0x04;
9440 icb->enode_mac[4] = 0x05;
9441 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
9442 }
9443
9444 /* Use extended-initialization control block. */
9445 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
9446 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
9447 /*
9448 * Setup driver NVRAM options.
9449 */
9450 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9451 "QLE8XXX");
9452
9453 qlt_81xx_config_nvram_stage2(vha, icb);
9454
9455 /* Use alternate WWN? */
9456 if (nv->host_p & cpu_to_le32(BIT_15)) {
9457 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
9458 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
9459 }
9460
9461 /* Prepare nodename */
9462 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
9463 /*
9464 * Firmware will apply the following mask if the nodename was
9465 * not provided.
9466 */
9467 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
9468 icb->node_name[0] &= 0xF0;
9469 }
9470
9471 if (IS_QLA28XX(ha) || IS_QLA27XX(ha)) {
9472 if ((nv->enhanced_features & BIT_7) == 0)
9473 ha->flags.scm_supported_a = 1;
9474 }
9475
9476 /* Set host adapter parameters. */
9477 ha->flags.disable_risc_code_load = 0;
9478 ha->flags.enable_lip_reset = 0;
9479 ha->flags.enable_lip_full_login =
9480 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0;
9481 ha->flags.enable_target_reset =
9482 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0;
9483 ha->flags.enable_led_scheme = 0;
9484 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0;
9485
9486 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
9487 (BIT_6 | BIT_5 | BIT_4)) >> 4;
9488
9489 /* save HBA serial number */
9490 ha->serial0 = icb->port_name[5];
9491 ha->serial1 = icb->port_name[6];
9492 ha->serial2 = icb->port_name[7];
9493 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
9494 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
9495
9496 icb->execution_throttle = cpu_to_le16(0xFFFF);
9497
9498 ha->retry_count = le16_to_cpu(nv->login_retry_count);
9499
9500 /* Set minimum login_timeout to 4 seconds. */
9501 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
9502 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
9503 if (le16_to_cpu(nv->login_timeout) < 4)
9504 nv->login_timeout = cpu_to_le16(4);
9505 ha->login_timeout = le16_to_cpu(nv->login_timeout);
9506
9507 /* Set minimum RATOV to 100 tenths of a second. */
9508 ha->r_a_tov = 100;
9509
9510 ha->loop_reset_delay = nv->reset_delay;
9511
9512 /* Link Down Timeout = 0:
9513 *
9514 * When Port Down timer expires we will start returning
9515 * I/O's to OS with "DID_NO_CONNECT".
9516 *
9517 * Link Down Timeout != 0:
9518 *
9519 * The driver waits for the link to come up after link down
9520 * before returning I/Os to OS with "DID_NO_CONNECT".
9521 */
9522 if (le16_to_cpu(nv->link_down_timeout) == 0) {
9523 ha->loop_down_abort_time =
9524 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
9525 } else {
9526 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
9527 ha->loop_down_abort_time =
9528 (LOOP_DOWN_TIME - ha->link_down_timeout);
9529 }
9530
9531 /* Need enough time to try and get the port back. */
9532 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
9533 if (qlport_down_retry)
9534 ha->port_down_retry_count = qlport_down_retry;
9535
9536 /* Set login_retry_count */
9537 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
9538 if (ha->port_down_retry_count ==
9539 le16_to_cpu(nv->port_down_retry_count) &&
9540 ha->port_down_retry_count > 3)
9541 ha->login_retry_count = ha->port_down_retry_count;
9542 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
9543 ha->login_retry_count = ha->port_down_retry_count;
9544 if (ql2xloginretrycount)
9545 ha->login_retry_count = ql2xloginretrycount;
9546
9547 /* if not running MSI-X we need handshaking on interrupts */
9548 if (!vha->hw->flags.msix_enabled &&
9549 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)))
9550 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
9551
9552 /* Enable ZIO. */
9553 if (!vha->flags.init_done) {
9554 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
9555 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
9556 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
9557 le16_to_cpu(icb->interrupt_delay_timer) : 2;
9558 }
9559 icb->firmware_options_2 &= cpu_to_le32(
9560 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
9561 vha->flags.process_response_queue = 0;
9562 if (ha->zio_mode != QLA_ZIO_DISABLED) {
9563 ha->zio_mode = QLA_ZIO_MODE_6;
9564
9565 ql_log(ql_log_info, vha, 0x0075,
9566 "ZIO mode %d enabled; timer delay (%d us).\n",
9567 ha->zio_mode,
9568 ha->zio_timer * 100);
9569
9570 icb->firmware_options_2 |= cpu_to_le32(
9571 (uint32_t)ha->zio_mode);
9572 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
9573 vha->flags.process_response_queue = 1;
9574 }
9575
9576 /* enable RIDA Format2 */
9577 icb->firmware_options_3 |= cpu_to_le32(BIT_0);
9578
9579 /* N2N: driver will initiate Login instead of FW */
9580 icb->firmware_options_3 |= cpu_to_le32(BIT_8);
9581
9582 /* Determine NVMe/FCP priority for target ports */
9583 ha->fc4_type_priority = qla2xxx_get_fc4_priority(vha);
9584
9585 if (rval) {
9586 ql_log(ql_log_warn, vha, 0x0076,
9587 "NVRAM configuration failed.\n");
9588 }
9589 return (rval);
9590 }
9591
9592 int
qla82xx_restart_isp(scsi_qla_host_t * vha)9593 qla82xx_restart_isp(scsi_qla_host_t *vha)
9594 {
9595 int status, rval;
9596 struct qla_hw_data *ha = vha->hw;
9597 struct scsi_qla_host *vp, *tvp;
9598 unsigned long flags;
9599
9600 status = qla2x00_init_rings(vha);
9601 if (!status) {
9602 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
9603 ha->flags.chip_reset_done = 1;
9604
9605 status = qla2x00_fw_ready(vha);
9606 if (!status) {
9607 /* Issue a marker after FW becomes ready. */
9608 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
9609 vha->flags.online = 1;
9610 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
9611 }
9612
9613 /* if no cable then assume it's good */
9614 if ((vha->device_flags & DFLG_NO_CABLE))
9615 status = 0;
9616 }
9617
9618 if (!status) {
9619 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
9620
9621 if (!atomic_read(&vha->loop_down_timer)) {
9622 /*
9623 * Issue marker command only when we are going
9624 * to start the I/O .
9625 */
9626 vha->marker_needed = 1;
9627 }
9628
9629 ha->isp_ops->enable_intrs(ha);
9630
9631 ha->isp_abort_cnt = 0;
9632 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
9633
9634 /* Update the firmware version */
9635 status = qla82xx_check_md_needed(vha);
9636
9637 if (ha->fce) {
9638 ha->flags.fce_enabled = 1;
9639 memset(ha->fce, 0,
9640 fce_calc_size(ha->fce_bufs));
9641 rval = qla2x00_enable_fce_trace(vha,
9642 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
9643 &ha->fce_bufs);
9644 if (rval) {
9645 ql_log(ql_log_warn, vha, 0x8001,
9646 "Unable to reinitialize FCE (%d).\n",
9647 rval);
9648 ha->flags.fce_enabled = 0;
9649 }
9650 }
9651
9652 if (ha->eft) {
9653 memset(ha->eft, 0, EFT_SIZE);
9654 rval = qla2x00_enable_eft_trace(vha,
9655 ha->eft_dma, EFT_NUM_BUFFERS);
9656 if (rval) {
9657 ql_log(ql_log_warn, vha, 0x8010,
9658 "Unable to reinitialize EFT (%d).\n",
9659 rval);
9660 }
9661 }
9662 }
9663
9664 if (!status) {
9665 ql_dbg(ql_dbg_taskm, vha, 0x8011,
9666 "qla82xx_restart_isp succeeded.\n");
9667
9668 spin_lock_irqsave(&ha->vport_slock, flags);
9669 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
9670 if (vp->vp_idx) {
9671 atomic_inc(&vp->vref_count);
9672 spin_unlock_irqrestore(&ha->vport_slock, flags);
9673
9674 qla2x00_vp_abort_isp(vp);
9675
9676 spin_lock_irqsave(&ha->vport_slock, flags);
9677 atomic_dec(&vp->vref_count);
9678 }
9679 }
9680 spin_unlock_irqrestore(&ha->vport_slock, flags);
9681
9682 } else {
9683 ql_log(ql_log_warn, vha, 0x8016,
9684 "qla82xx_restart_isp **** FAILED ****.\n");
9685 }
9686
9687 return status;
9688 }
9689
9690 /*
9691 * qla24xx_get_fcp_prio
9692 * Gets the fcp cmd priority value for the logged in port.
9693 * Looks for a match of the port descriptors within
9694 * each of the fcp prio config entries. If a match is found,
9695 * the tag (priority) value is returned.
9696 *
9697 * Input:
9698 * vha = scsi host structure pointer.
9699 * fcport = port structure pointer.
9700 *
9701 * Return:
9702 * non-zero (if found)
9703 * -1 (if not found)
9704 *
9705 * Context:
9706 * Kernel context
9707 */
9708 static int
qla24xx_get_fcp_prio(scsi_qla_host_t * vha,fc_port_t * fcport)9709 qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
9710 {
9711 int i, entries;
9712 uint8_t pid_match, wwn_match;
9713 int priority;
9714 uint32_t pid1, pid2;
9715 uint64_t wwn1, wwn2;
9716 struct qla_fcp_prio_entry *pri_entry;
9717 struct qla_hw_data *ha = vha->hw;
9718
9719 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
9720 return -1;
9721
9722 priority = -1;
9723 entries = ha->fcp_prio_cfg->num_entries;
9724 pri_entry = &ha->fcp_prio_cfg->entry[0];
9725
9726 for (i = 0; i < entries; i++) {
9727 pid_match = wwn_match = 0;
9728
9729 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
9730 pri_entry++;
9731 continue;
9732 }
9733
9734 /* check source pid for a match */
9735 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
9736 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
9737 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
9738 if (pid1 == INVALID_PORT_ID)
9739 pid_match++;
9740 else if (pid1 == pid2)
9741 pid_match++;
9742 }
9743
9744 /* check destination pid for a match */
9745 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
9746 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
9747 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
9748 if (pid1 == INVALID_PORT_ID)
9749 pid_match++;
9750 else if (pid1 == pid2)
9751 pid_match++;
9752 }
9753
9754 /* check source WWN for a match */
9755 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
9756 wwn1 = wwn_to_u64(vha->port_name);
9757 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
9758 if (wwn2 == (uint64_t)-1)
9759 wwn_match++;
9760 else if (wwn1 == wwn2)
9761 wwn_match++;
9762 }
9763
9764 /* check destination WWN for a match */
9765 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
9766 wwn1 = wwn_to_u64(fcport->port_name);
9767 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
9768 if (wwn2 == (uint64_t)-1)
9769 wwn_match++;
9770 else if (wwn1 == wwn2)
9771 wwn_match++;
9772 }
9773
9774 if (pid_match == 2 || wwn_match == 2) {
9775 /* Found a matching entry */
9776 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
9777 priority = pri_entry->tag;
9778 break;
9779 }
9780
9781 pri_entry++;
9782 }
9783
9784 return priority;
9785 }
9786
9787 /*
9788 * qla24xx_update_fcport_fcp_prio
9789 * Activates fcp priority for the logged in fc port
9790 *
9791 * Input:
9792 * vha = scsi host structure pointer.
9793 * fcp = port structure pointer.
9794 *
9795 * Return:
9796 * QLA_SUCCESS or QLA_FUNCTION_FAILED
9797 *
9798 * Context:
9799 * Kernel context.
9800 */
9801 int
qla24xx_update_fcport_fcp_prio(scsi_qla_host_t * vha,fc_port_t * fcport)9802 qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
9803 {
9804 int ret;
9805 int priority;
9806 uint16_t mb[5];
9807
9808 if (fcport->port_type != FCT_TARGET ||
9809 fcport->loop_id == FC_NO_LOOP_ID)
9810 return QLA_FUNCTION_FAILED;
9811
9812 priority = qla24xx_get_fcp_prio(vha, fcport);
9813 if (priority < 0)
9814 return QLA_FUNCTION_FAILED;
9815
9816 if (IS_P3P_TYPE(vha->hw)) {
9817 fcport->fcp_prio = priority & 0xf;
9818 return QLA_SUCCESS;
9819 }
9820
9821 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
9822 if (ret == QLA_SUCCESS) {
9823 if (fcport->fcp_prio != priority)
9824 ql_dbg(ql_dbg_user, vha, 0x709e,
9825 "Updated FCP_CMND priority - value=%d loop_id=%d "
9826 "port_id=%02x%02x%02x.\n", priority,
9827 fcport->loop_id, fcport->d_id.b.domain,
9828 fcport->d_id.b.area, fcport->d_id.b.al_pa);
9829 fcport->fcp_prio = priority & 0xf;
9830 } else
9831 ql_dbg(ql_dbg_user, vha, 0x704f,
9832 "Unable to update FCP_CMND priority - ret=0x%x for "
9833 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
9834 fcport->d_id.b.domain, fcport->d_id.b.area,
9835 fcport->d_id.b.al_pa);
9836 return ret;
9837 }
9838
9839 /*
9840 * qla24xx_update_all_fcp_prio
9841 * Activates fcp priority for all the logged in ports
9842 *
9843 * Input:
9844 * ha = adapter block pointer.
9845 *
9846 * Return:
9847 * QLA_SUCCESS or QLA_FUNCTION_FAILED
9848 *
9849 * Context:
9850 * Kernel context.
9851 */
9852 int
qla24xx_update_all_fcp_prio(scsi_qla_host_t * vha)9853 qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
9854 {
9855 int ret;
9856 fc_port_t *fcport;
9857
9858 ret = QLA_FUNCTION_FAILED;
9859 /* We need to set priority for all logged in ports */
9860 list_for_each_entry(fcport, &vha->vp_fcports, list)
9861 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
9862
9863 return ret;
9864 }
9865
qla2xxx_create_qpair(struct scsi_qla_host * vha,int qos,int vp_idx,bool startqp)9866 struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
9867 int vp_idx, bool startqp)
9868 {
9869 int rsp_id = 0;
9870 int req_id = 0;
9871 int i;
9872 struct qla_hw_data *ha = vha->hw;
9873 uint16_t qpair_id = 0;
9874 struct qla_qpair *qpair = NULL;
9875 struct qla_msix_entry *msix;
9876
9877 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
9878 ql_log(ql_log_warn, vha, 0x00181,
9879 "FW/Driver is not multi-queue capable.\n");
9880 return NULL;
9881 }
9882
9883 if (ql2xmqsupport || ql2xnvmeenable) {
9884 qpair = kzalloc_obj(struct qla_qpair);
9885 if (qpair == NULL) {
9886 ql_log(ql_log_warn, vha, 0x0182,
9887 "Failed to allocate memory for queue pair.\n");
9888 return NULL;
9889 }
9890
9891 qpair->hw = vha->hw;
9892 qpair->vha = vha;
9893 qpair->qp_lock_ptr = &qpair->qp_lock;
9894 spin_lock_init(&qpair->qp_lock);
9895 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
9896
9897 /* Assign available que pair id */
9898 mutex_lock(&ha->mq_lock);
9899 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
9900 if (ha->num_qpairs >= ha->max_qpairs) {
9901 mutex_unlock(&ha->mq_lock);
9902 ql_log(ql_log_warn, vha, 0x0183,
9903 "No resources to create additional q pair.\n");
9904 goto fail_qid_map;
9905 }
9906 ha->num_qpairs++;
9907 set_bit(qpair_id, ha->qpair_qid_map);
9908 ha->queue_pair_map[qpair_id] = qpair;
9909 qpair->id = qpair_id;
9910 qpair->vp_idx = vp_idx;
9911 qpair->fw_started = ha->flags.fw_started;
9912 INIT_LIST_HEAD(&qpair->hints_list);
9913 INIT_LIST_HEAD(&qpair->dsd_list);
9914 qpair->chip_reset = ha->base_qpair->chip_reset;
9915 qpair->enable_class_2 = ha->base_qpair->enable_class_2;
9916 qpair->enable_explicit_conf =
9917 ha->base_qpair->enable_explicit_conf;
9918
9919 for (i = 0; i < ha->msix_count; i++) {
9920 msix = &ha->msix_entries[i];
9921 if (msix->in_use)
9922 continue;
9923 qpair->msix = msix;
9924 ql_dbg(ql_dbg_multiq, vha, 0xc00f,
9925 "Vector %x selected for qpair\n", msix->vector);
9926 break;
9927 }
9928 if (!qpair->msix) {
9929 ql_log(ql_log_warn, vha, 0x0184,
9930 "Out of MSI-X vectors!.\n");
9931 goto fail_msix;
9932 }
9933
9934 qpair->msix->in_use = 1;
9935 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
9936 qpair->pdev = ha->pdev;
9937 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
9938 qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
9939
9940 mutex_unlock(&ha->mq_lock);
9941
9942 /* Create response queue first */
9943 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
9944 if (!rsp_id) {
9945 ql_log(ql_log_warn, vha, 0x0185,
9946 "Failed to create response queue.\n");
9947 goto fail_rsp;
9948 }
9949
9950 qpair->rsp = ha->rsp_q_map[rsp_id];
9951
9952 /* Create request queue */
9953 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
9954 startqp);
9955 if (!req_id) {
9956 ql_log(ql_log_warn, vha, 0x0186,
9957 "Failed to create request queue.\n");
9958 goto fail_req;
9959 }
9960
9961 qpair->req = ha->req_q_map[req_id];
9962 qpair->rsp->req = qpair->req;
9963 qpair->rsp->qpair = qpair;
9964
9965 if (!qpair->cpu_mapped)
9966 qla_cpu_update(qpair, raw_smp_processor_id());
9967
9968 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
9969 if (ha->fw_attributes & BIT_4)
9970 qpair->difdix_supported = 1;
9971 }
9972
9973 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
9974 if (!qpair->srb_mempool) {
9975 ql_log(ql_log_warn, vha, 0xd036,
9976 "Failed to create srb mempool for qpair %d\n",
9977 qpair->id);
9978 goto fail_mempool;
9979 }
9980
9981 if (qla_create_buf_pool(vha, qpair)) {
9982 ql_log(ql_log_warn, vha, 0xd036,
9983 "Failed to initialize buf pool for qpair %d\n",
9984 qpair->id);
9985 goto fail_bufpool;
9986 }
9987
9988 /* Mark as online */
9989 qpair->online = 1;
9990
9991 if (!vha->flags.qpairs_available)
9992 vha->flags.qpairs_available = 1;
9993
9994 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
9995 "Request/Response queue pair created, id %d\n",
9996 qpair->id);
9997 ql_dbg(ql_dbg_init, vha, 0x0187,
9998 "Request/Response queue pair created, id %d\n",
9999 qpair->id);
10000 }
10001 return qpair;
10002
10003 fail_bufpool:
10004 mempool_destroy(qpair->srb_mempool);
10005 fail_mempool:
10006 qla25xx_delete_req_que(vha, qpair->req);
10007 fail_req:
10008 qla25xx_delete_rsp_que(vha, qpair->rsp);
10009 fail_rsp:
10010 mutex_lock(&ha->mq_lock);
10011 qpair->msix->in_use = 0;
10012 list_del(&qpair->qp_list_elem);
10013 if (list_empty(&vha->qp_list))
10014 vha->flags.qpairs_available = 0;
10015 fail_msix:
10016 ha->queue_pair_map[qpair_id] = NULL;
10017 clear_bit(qpair_id, ha->qpair_qid_map);
10018 ha->num_qpairs--;
10019 mutex_unlock(&ha->mq_lock);
10020 fail_qid_map:
10021 kfree(qpair);
10022 return NULL;
10023 }
10024
qla2xxx_delete_qpair(struct scsi_qla_host * vha,struct qla_qpair * qpair)10025 int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
10026 {
10027 int ret = QLA_FUNCTION_FAILED;
10028 struct qla_hw_data *ha = qpair->hw;
10029
10030 qpair->delete_in_progress = 1;
10031
10032 qla_free_buf_pool(qpair);
10033
10034 ret = qla25xx_delete_req_que(vha, qpair->req);
10035 if (ret != QLA_SUCCESS)
10036 goto fail;
10037
10038 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
10039 if (ret != QLA_SUCCESS)
10040 goto fail;
10041
10042 if (!list_empty(&qpair->dsd_list)) {
10043 struct dsd_dma *dsd_ptr, *tdsd_ptr;
10044
10045 /* clean up allocated prev pool */
10046 list_for_each_entry_safe(dsd_ptr, tdsd_ptr,
10047 &qpair->dsd_list, list) {
10048 dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
10049 dsd_ptr->dsd_list_dma);
10050 list_del(&dsd_ptr->list);
10051 kfree(dsd_ptr);
10052 }
10053 }
10054
10055 mutex_lock(&ha->mq_lock);
10056 ha->queue_pair_map[qpair->id] = NULL;
10057 clear_bit(qpair->id, ha->qpair_qid_map);
10058 ha->num_qpairs--;
10059 list_del(&qpair->qp_list_elem);
10060 if (list_empty(&vha->qp_list)) {
10061 vha->flags.qpairs_available = 0;
10062 vha->flags.qpairs_req_created = 0;
10063 vha->flags.qpairs_rsp_created = 0;
10064 }
10065 mempool_destroy(qpair->srb_mempool);
10066 kfree(qpair);
10067 mutex_unlock(&ha->mq_lock);
10068
10069 return QLA_SUCCESS;
10070 fail:
10071 return ret;
10072 }
10073
10074 uint64_t
qla2x00_count_set_bits(uint32_t num)10075 qla2x00_count_set_bits(uint32_t num)
10076 {
10077 /* Brian Kernighan's Algorithm */
10078 u64 count = 0;
10079
10080 while (num) {
10081 num &= (num - 1);
10082 count++;
10083 }
10084 return count;
10085 }
10086
10087 uint64_t
qla2x00_get_num_tgts(scsi_qla_host_t * vha)10088 qla2x00_get_num_tgts(scsi_qla_host_t *vha)
10089 {
10090 fc_port_t *f, *tf;
10091 u64 count = 0;
10092
10093 f = NULL;
10094 tf = NULL;
10095
10096 list_for_each_entry_safe(f, tf, &vha->vp_fcports, list) {
10097 if (f->port_type != FCT_TARGET)
10098 continue;
10099 count++;
10100 }
10101 return count;
10102 }
10103
qla2xxx_reset_stats(struct Scsi_Host * host,u32 flags)10104 int qla2xxx_reset_stats(struct Scsi_Host *host, u32 flags)
10105 {
10106 scsi_qla_host_t *vha = shost_priv(host);
10107 fc_port_t *fcport = NULL;
10108 unsigned long int_flags;
10109
10110 if (flags & QLA2XX_HW_ERROR)
10111 vha->hw_err_cnt = 0;
10112 if (flags & QLA2XX_SHT_LNK_DWN)
10113 vha->short_link_down_cnt = 0;
10114 if (flags & QLA2XX_INT_ERR)
10115 vha->interface_err_cnt = 0;
10116 if (flags & QLA2XX_CMD_TIMEOUT)
10117 vha->cmd_timeout_cnt = 0;
10118 if (flags & QLA2XX_RESET_CMD_ERR)
10119 vha->reset_cmd_err_cnt = 0;
10120 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) {
10121 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags);
10122 list_for_each_entry(fcport, &vha->vp_fcports, list) {
10123 fcport->tgt_short_link_down_cnt = 0;
10124 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME;
10125 }
10126 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags);
10127 }
10128 vha->link_down_time = QLA2XX_MAX_LINK_DOWN_TIME;
10129 return 0;
10130 }
10131
qla2xxx_start_stats(struct Scsi_Host * host,u32 flags)10132 int qla2xxx_start_stats(struct Scsi_Host *host, u32 flags)
10133 {
10134 return qla2xxx_reset_stats(host, flags);
10135 }
10136
qla2xxx_stop_stats(struct Scsi_Host * host,u32 flags)10137 int qla2xxx_stop_stats(struct Scsi_Host *host, u32 flags)
10138 {
10139 return qla2xxx_reset_stats(host, flags);
10140 }
10141
qla2xxx_get_ini_stats(struct Scsi_Host * host,u32 flags,void * data,u64 size)10142 int qla2xxx_get_ini_stats(struct Scsi_Host *host, u32 flags,
10143 void *data, u64 size)
10144 {
10145 scsi_qla_host_t *vha = shost_priv(host);
10146 struct ql_vnd_host_stats_resp *resp = (struct ql_vnd_host_stats_resp *)data;
10147 struct ql_vnd_stats *rsp_data = &resp->stats;
10148 u64 ini_entry_count = 0;
10149 u64 i = 0;
10150 u64 entry_count = 0;
10151 u64 num_tgt = 0;
10152 u32 tmp_stat_type = 0;
10153 fc_port_t *fcport = NULL;
10154 unsigned long int_flags;
10155
10156 /* Copy stat type to work on it */
10157 tmp_stat_type = flags;
10158
10159 if (tmp_stat_type & BIT_17) {
10160 num_tgt = qla2x00_get_num_tgts(vha);
10161 /* unset BIT_17 */
10162 tmp_stat_type &= ~(1 << 17);
10163 }
10164 ini_entry_count = qla2x00_count_set_bits(tmp_stat_type);
10165
10166 entry_count = ini_entry_count + num_tgt;
10167
10168 rsp_data->entry_count = entry_count;
10169
10170 i = 0;
10171 if (flags & QLA2XX_HW_ERROR) {
10172 rsp_data->entry[i].stat_type = QLA2XX_HW_ERROR;
10173 rsp_data->entry[i].tgt_num = 0x0;
10174 rsp_data->entry[i].cnt = vha->hw_err_cnt;
10175 i++;
10176 }
10177
10178 if (flags & QLA2XX_SHT_LNK_DWN) {
10179 rsp_data->entry[i].stat_type = QLA2XX_SHT_LNK_DWN;
10180 rsp_data->entry[i].tgt_num = 0x0;
10181 rsp_data->entry[i].cnt = vha->short_link_down_cnt;
10182 i++;
10183 }
10184
10185 if (flags & QLA2XX_INT_ERR) {
10186 rsp_data->entry[i].stat_type = QLA2XX_INT_ERR;
10187 rsp_data->entry[i].tgt_num = 0x0;
10188 rsp_data->entry[i].cnt = vha->interface_err_cnt;
10189 i++;
10190 }
10191
10192 if (flags & QLA2XX_CMD_TIMEOUT) {
10193 rsp_data->entry[i].stat_type = QLA2XX_CMD_TIMEOUT;
10194 rsp_data->entry[i].tgt_num = 0x0;
10195 rsp_data->entry[i].cnt = vha->cmd_timeout_cnt;
10196 i++;
10197 }
10198
10199 if (flags & QLA2XX_RESET_CMD_ERR) {
10200 rsp_data->entry[i].stat_type = QLA2XX_RESET_CMD_ERR;
10201 rsp_data->entry[i].tgt_num = 0x0;
10202 rsp_data->entry[i].cnt = vha->reset_cmd_err_cnt;
10203 i++;
10204 }
10205
10206 /* i will continue from previous loop, as target
10207 * entries are after initiator
10208 */
10209 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) {
10210 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags);
10211 list_for_each_entry(fcport, &vha->vp_fcports, list) {
10212 if (fcport->port_type != FCT_TARGET)
10213 continue;
10214 if (!fcport->rport)
10215 continue;
10216 rsp_data->entry[i].stat_type = QLA2XX_TGT_SHT_LNK_DOWN;
10217 rsp_data->entry[i].tgt_num = fcport->rport->number;
10218 rsp_data->entry[i].cnt = fcport->tgt_short_link_down_cnt;
10219 i++;
10220 }
10221 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags);
10222 }
10223 resp->status = EXT_STATUS_OK;
10224
10225 return 0;
10226 }
10227
qla2xxx_get_tgt_stats(struct Scsi_Host * host,u32 flags,struct fc_rport * rport,void * data,u64 size)10228 int qla2xxx_get_tgt_stats(struct Scsi_Host *host, u32 flags,
10229 struct fc_rport *rport, void *data, u64 size)
10230 {
10231 struct ql_vnd_tgt_stats_resp *tgt_data = data;
10232 fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
10233
10234 tgt_data->status = 0;
10235 tgt_data->stats.entry_count = 1;
10236 tgt_data->stats.entry[0].stat_type = flags;
10237 tgt_data->stats.entry[0].tgt_num = rport->number;
10238 tgt_data->stats.entry[0].cnt = fcport->tgt_short_link_down_cnt;
10239
10240 return 0;
10241 }
10242
qla2xxx_disable_port(struct Scsi_Host * host)10243 int qla2xxx_disable_port(struct Scsi_Host *host)
10244 {
10245 scsi_qla_host_t *vha = shost_priv(host);
10246
10247 vha->hw->flags.port_isolated = 1;
10248
10249 if (qla2x00_isp_reg_stat(vha->hw)) {
10250 ql_log(ql_log_info, vha, 0x9006,
10251 "PCI/Register disconnect, exiting.\n");
10252 qla_pci_set_eeh_busy(vha);
10253 return FAILED;
10254 }
10255 if (qla2x00_chip_is_down(vha))
10256 return 0;
10257
10258 if (vha->flags.online) {
10259 qla2x00_abort_isp_cleanup(vha);
10260 qla2x00_wait_for_sess_deletion(vha);
10261 }
10262
10263 return 0;
10264 }
10265
qla2xxx_enable_port(struct Scsi_Host * host)10266 int qla2xxx_enable_port(struct Scsi_Host *host)
10267 {
10268 scsi_qla_host_t *vha = shost_priv(host);
10269
10270 if (qla2x00_isp_reg_stat(vha->hw)) {
10271 ql_log(ql_log_info, vha, 0x9001,
10272 "PCI/Register disconnect, exiting.\n");
10273 qla_pci_set_eeh_busy(vha);
10274 return FAILED;
10275 }
10276
10277 vha->hw->flags.port_isolated = 0;
10278 /* Set the flag to 1, so that isp_abort can proceed */
10279 vha->flags.online = 1;
10280 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
10281 qla2xxx_wake_dpc(vha);
10282
10283 return 0;
10284 }
10285