1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017 exceet electronics GmbH
4 *
5 * Authors:
6 * Frieder Schrempf <frieder.schrempf@exceet.de>
7 * Boris Brezillon <boris.brezillon@bootlin.com>
8 */
9
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/mtd/spinand.h>
13 #include <linux/units.h>
14 #include <linux/delay.h>
15
16 #define SPINAND_MFR_WINBOND 0xEF
17
18 #define WINBOND_CFG_BUF_READ BIT(3)
19
20 #define W25N04KV_STATUS_ECC_5_8_BITFLIPS (3 << 4)
21
22 #define W25N0XJW_SR4 0xD0
23 #define W25N0XJW_SR4_HS BIT(2)
24
25 #define W35N01JW_VCR_IO_MODE_REG 0x00
26 #define W35N01JW_VCR_IO_MODE_SINGLE_SDR 0xFF
27 #define W35N01JW_VCR_IO_MODE_OCTAL_SDR 0xDF
28 #define W35N01JW_VCR_IO_MODE_OCTAL_DDR_DS 0xE7
29 #define W35N01JW_VCR_IO_MODE_OCTAL_DDR 0xC7
30 #define W35N01JW_VCR_DUMMY_CLOCK_REG 0x01
31
32 /*
33 * "X2" in the core is equivalent to "dual output" in the datasheets,
34 * "X4" in the core is equivalent to "quad output" in the datasheets.
35 * Quad and octal capable chips feature an absolute maximum frequency of 166MHz.
36 */
37
38 static SPINAND_OP_VARIANTS(read_cache_octal_variants,
39 SPINAND_PAGE_READ_FROM_CACHE_8D_8D_8D_OP(0, 24, NULL, 0, 120 * HZ_PER_MHZ),
40 SPINAND_PAGE_READ_FROM_CACHE_8D_8D_8D_OP(0, 16, NULL, 0, 86 * HZ_PER_MHZ),
41 SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(0, 3, NULL, 0, 120 * HZ_PER_MHZ),
42 SPINAND_PAGE_READ_FROM_CACHE_1S_1D_8D_OP(0, 2, NULL, 0, 105 * HZ_PER_MHZ),
43 SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(0, 20, NULL, 0, 0),
44 SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(0, 16, NULL, 0, 162 * HZ_PER_MHZ),
45 SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(0, 12, NULL, 0, 124 * HZ_PER_MHZ),
46 SPINAND_PAGE_READ_FROM_CACHE_1S_8S_8S_OP(0, 8, NULL, 0, 86 * HZ_PER_MHZ),
47 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_8S_OP(0, 2, NULL, 0, 0),
48 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_8S_OP(0, 1, NULL, 0, 133 * HZ_PER_MHZ),
49 SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0),
50 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 0));
51
52 static SPINAND_OP_VARIANTS(write_cache_octal_variants,
53 SPINAND_PROG_LOAD_8D_8D_8D_OP(true, 0, NULL, 0),
54 SPINAND_PROG_LOAD_1S_8S_8S_OP(true, 0, NULL, 0),
55 SPINAND_PROG_LOAD_1S_1S_8S_OP(0, NULL, 0),
56 SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0));
57
58 static SPINAND_OP_VARIANTS(update_cache_octal_variants,
59 SPINAND_PROG_LOAD_8D_8D_8D_OP(false, 0, NULL, 0),
60 SPINAND_PROG_LOAD_1S_8S_8S_OP(false, 0, NULL, 0),
61 SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0));
62
63 static SPINAND_OP_VARIANTS(read_cache_dual_quad_dtr_variants,
64 SPINAND_PAGE_READ_FROM_CACHE_1S_4D_4D_OP(0, 8, NULL, 0, 80 * HZ_PER_MHZ),
65 SPINAND_PAGE_READ_FROM_CACHE_1S_1D_4D_OP(0, 2, NULL, 0, 80 * HZ_PER_MHZ),
66 SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(0, 4, NULL, 0, 0),
67 SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(0, 2, NULL, 0, 104 * HZ_PER_MHZ),
68 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0, 0),
69 SPINAND_PAGE_READ_FROM_CACHE_1S_2D_2D_OP(0, 4, NULL, 0, 80 * HZ_PER_MHZ),
70 SPINAND_PAGE_READ_FROM_CACHE_1S_1D_2D_OP(0, 2, NULL, 0, 80 * HZ_PER_MHZ),
71 SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(0, 2, NULL, 0, 0),
72 SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(0, 1, NULL, 0, 104 * HZ_PER_MHZ),
73 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(0, 1, NULL, 0, 0),
74 SPINAND_PAGE_READ_FROM_CACHE_1S_1D_1D_OP(0, 2, NULL, 0, 80 * HZ_PER_MHZ),
75 SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0),
76 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 54 * HZ_PER_MHZ));
77
78 static SPINAND_OP_VARIANTS(read_cache_variants,
79 SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(0, 2, NULL, 0, 0),
80 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0, 0),
81 SPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(0, 1, NULL, 0, 0),
82 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(0, 1, NULL, 0, 0),
83 SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0),
84 SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 0));
85
86 static SPINAND_OP_VARIANTS(write_cache_variants,
87 SPINAND_PROG_LOAD_1S_1S_4S_OP(true, 0, NULL, 0),
88 SPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0));
89
90 static SPINAND_OP_VARIANTS(update_cache_variants,
91 SPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0),
92 SPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0));
93
94 #define SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, buf) \
95 SPI_MEM_OP(SPI_MEM_OP_CMD(0x81, 1), \
96 SPI_MEM_OP_ADDR(3, reg, 1), \
97 SPI_MEM_OP_NO_DUMMY, \
98 SPI_MEM_OP_DATA_OUT(1, buf, 1))
99
100 #define SPINAND_WINBOND_WRITE_VCR_8D_8D_8D(reg, buf) \
101 SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x81, 8), \
102 SPI_MEM_DTR_OP_ADDR(4, reg << 8, 8), \
103 SPI_MEM_OP_NO_DUMMY, \
104 SPI_MEM_DTR_OP_DATA_OUT(2, buf, 8))
105
106 static SPINAND_OP_VARIANTS(winbond_w35_ops,
107 SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(0, NULL),
108 SPINAND_WINBOND_WRITE_VCR_8D_8D_8D(0, NULL));
109
110 static struct spi_mem_op
spinand_fill_winbond_write_vcr_op(struct spinand_device * spinand,u8 reg,void * valptr)111 spinand_fill_winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, void *valptr)
112 {
113 return (spinand->bus_iface == SSDR) ?
114 (struct spi_mem_op)SPINAND_WINBOND_WRITE_VCR_1S_1S_1S(reg, valptr) :
115 (struct spi_mem_op)SPINAND_WINBOND_WRITE_VCR_8D_8D_8D(reg, valptr);
116 }
117
118 #define SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(buf) \
119 SPI_MEM_OP(SPI_MEM_OP_CMD(0xc2, 1), \
120 SPI_MEM_OP_NO_ADDR, \
121 SPI_MEM_OP_NO_DUMMY, \
122 SPI_MEM_OP_DATA_OUT(1, buf, 1))
123
124 static SPINAND_OP_VARIANTS(winbond_w25_ops,
125 SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(NULL));
126
127 static struct spi_mem_op
spinand_fill_winbond_select_target_op(struct spinand_device * spinand,void * valptr)128 spinand_fill_winbond_select_target_op(struct spinand_device *spinand, void *valptr)
129 {
130 WARN_ON_ONCE(spinand->bus_iface != SSDR);
131
132 return (struct spi_mem_op)SPINAND_WINBOND_SELECT_TARGET_1S_0_1S(valptr);
133 }
134
w25m02gv_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)135 static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
136 struct mtd_oob_region *region)
137 {
138 if (section > 3)
139 return -ERANGE;
140
141 region->offset = (16 * section) + 8;
142 region->length = 8;
143
144 return 0;
145 }
146
w25m02gv_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)147 static int w25m02gv_ooblayout_free(struct mtd_info *mtd, int section,
148 struct mtd_oob_region *region)
149 {
150 if (section > 3)
151 return -ERANGE;
152
153 region->offset = (16 * section) + 2;
154 region->length = 6;
155
156 return 0;
157 }
158
159 static const struct mtd_ooblayout_ops w25m02gv_ooblayout = {
160 .ecc = w25m02gv_ooblayout_ecc,
161 .free = w25m02gv_ooblayout_free,
162 };
163
w25m02gv_select_target(struct spinand_device * spinand,unsigned int target)164 static int w25m02gv_select_target(struct spinand_device *spinand,
165 unsigned int target)
166 {
167 struct spi_mem_op op = SPINAND_OP(spinand, winbond_select_target,
168 spinand->scratchbuf);
169
170 *spinand->scratchbuf = target;
171 return spi_mem_exec_op(spinand->spimem, &op);
172 }
173
w25n01kv_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)174 static int w25n01kv_ooblayout_ecc(struct mtd_info *mtd, int section,
175 struct mtd_oob_region *region)
176 {
177 if (section > 3)
178 return -ERANGE;
179
180 region->offset = 64 + (8 * section);
181 region->length = 7;
182
183 return 0;
184 }
185
w25n02kv_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)186 static int w25n02kv_ooblayout_ecc(struct mtd_info *mtd, int section,
187 struct mtd_oob_region *region)
188 {
189 if (section > 3)
190 return -ERANGE;
191
192 region->offset = 64 + (16 * section);
193 region->length = 13;
194
195 return 0;
196 }
197
w25n02kv_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)198 static int w25n02kv_ooblayout_free(struct mtd_info *mtd, int section,
199 struct mtd_oob_region *region)
200 {
201 if (section > 3)
202 return -ERANGE;
203
204 region->offset = (16 * section) + 2;
205 region->length = 14;
206
207 return 0;
208 }
209
210 static const struct mtd_ooblayout_ops w25n01kv_ooblayout = {
211 .ecc = w25n01kv_ooblayout_ecc,
212 .free = w25n02kv_ooblayout_free,
213 };
214
215 static const struct mtd_ooblayout_ops w25n02kv_ooblayout = {
216 .ecc = w25n02kv_ooblayout_ecc,
217 .free = w25n02kv_ooblayout_free,
218 };
219
w25n01jw_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)220 static int w25n01jw_ooblayout_ecc(struct mtd_info *mtd, int section,
221 struct mtd_oob_region *region)
222 {
223 if (section > 3)
224 return -ERANGE;
225
226 region->offset = (16 * section) + 12;
227 region->length = 4;
228
229 return 0;
230 }
231
w25n01jw_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)232 static int w25n01jw_ooblayout_free(struct mtd_info *mtd, int section,
233 struct mtd_oob_region *region)
234 {
235 if (section > 3)
236 return -ERANGE;
237
238 region->offset = (16 * section);
239 region->length = 12;
240
241 /* Extract BBM */
242 if (!section) {
243 region->offset += 2;
244 region->length -= 2;
245 }
246
247 return 0;
248 }
249
w35n01jw_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * region)250 static int w35n01jw_ooblayout_ecc(struct mtd_info *mtd, int section,
251 struct mtd_oob_region *region)
252 {
253 if (section > 7)
254 return -ERANGE;
255
256 region->offset = (16 * section) + 12;
257 region->length = 4;
258
259 return 0;
260 }
261
w35n01jw_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * region)262 static int w35n01jw_ooblayout_free(struct mtd_info *mtd, int section,
263 struct mtd_oob_region *region)
264 {
265 if (section > 7)
266 return -ERANGE;
267
268 region->offset = 16 * section;
269 region->length = 12;
270
271 /* Extract BBM */
272 if (!section) {
273 region->offset += 2;
274 region->length -= 2;
275 }
276
277 return 0;
278 }
279
280 static const struct mtd_ooblayout_ops w25n01jw_ooblayout = {
281 .ecc = w25n01jw_ooblayout_ecc,
282 .free = w25n01jw_ooblayout_free,
283 };
284
285 static const struct mtd_ooblayout_ops w35n01jw_ooblayout = {
286 .ecc = w35n01jw_ooblayout_ecc,
287 .free = w35n01jw_ooblayout_free,
288 };
289
w25n02kv_ecc_get_status(struct spinand_device * spinand,u8 status)290 static int w25n02kv_ecc_get_status(struct spinand_device *spinand,
291 u8 status)
292 {
293 struct nand_device *nand = spinand_to_nand(spinand);
294 u8 mbf = 0;
295 struct spi_mem_op op = SPINAND_OP(spinand, get_feature,
296 0x30, spinand->scratchbuf);
297
298 switch (status & STATUS_ECC_MASK) {
299 case STATUS_ECC_NO_BITFLIPS:
300 return 0;
301
302 case STATUS_ECC_UNCOR_ERROR:
303 return -EBADMSG;
304
305 case STATUS_ECC_HAS_BITFLIPS:
306 case W25N04KV_STATUS_ECC_5_8_BITFLIPS:
307 /*
308 * Let's try to retrieve the real maximum number of bitflips
309 * in order to avoid forcing the wear-leveling layer to move
310 * data around if it's not necessary.
311 */
312 if (spi_mem_exec_op(spinand->spimem, &op))
313 return nanddev_get_ecc_conf(nand)->strength;
314
315 mbf = *(spinand->scratchbuf) >> 4;
316
317 if (WARN_ON(mbf > nanddev_get_ecc_conf(nand)->strength || !mbf))
318 return nanddev_get_ecc_conf(nand)->strength;
319
320 return mbf;
321
322 default:
323 break;
324 }
325
326 return -EINVAL;
327 }
328
w25n0xjw_hs_cfg(struct spinand_device * spinand,enum spinand_bus_interface iface)329 static int w25n0xjw_hs_cfg(struct spinand_device *spinand,
330 enum spinand_bus_interface iface)
331 {
332 const struct spi_mem_op *op;
333 bool hs;
334 u8 sr4;
335 int ret;
336
337 if (iface != SSDR)
338 return -EOPNOTSUPP;
339
340 /*
341 * SDR dual and quad I/O operations over 104MHz require the HS bit to
342 * enable a few more dummy cycles.
343 */
344 op = spinand->op_templates->read_cache;
345 if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
346 hs = false;
347 else if (op->cmd.buswidth != 1 || op->addr.buswidth == 1)
348 hs = false;
349 else if (op->max_freq && op->max_freq <= 104 * HZ_PER_MHZ)
350 hs = false;
351 else
352 hs = true;
353
354 ret = spinand_read_reg_op(spinand, W25N0XJW_SR4, &sr4);
355 if (ret)
356 return ret;
357
358 if (hs)
359 sr4 |= W25N0XJW_SR4_HS;
360 else
361 sr4 &= ~W25N0XJW_SR4_HS;
362
363 ret = spinand_write_reg_op(spinand, W25N0XJW_SR4, sr4);
364 if (ret)
365 return ret;
366
367 return 0;
368 }
369
w35n0xjw_write_vcr(struct spinand_device * spinand,u8 reg,u8 val)370 static int w35n0xjw_write_vcr(struct spinand_device *spinand, u8 reg, u8 val)
371 {
372 struct spi_mem_op op = SPINAND_OP(spinand, winbond_write_vcr,
373 reg, spinand->scratchbuf);
374 int ret;
375
376 *spinand->scratchbuf = val;
377
378 ret = spinand_write_enable_op(spinand);
379 if (ret)
380 return ret;
381
382 ret = spi_mem_exec_op(spinand->spimem, &op);
383 if (ret)
384 return ret;
385
386 /*
387 * Write VCR operation doesn't set the busy bit in SR, which means we
388 * cannot perform a status poll. Minimum time of 50ns is needed to
389 * complete the write.
390 */
391 ndelay(50);
392
393 return 0;
394 }
395
w35n0xjw_vcr_cfg(struct spinand_device * spinand,enum spinand_bus_interface iface)396 static int w35n0xjw_vcr_cfg(struct spinand_device *spinand,
397 enum spinand_bus_interface iface)
398 {
399 const struct spi_mem_op *ref_op;
400 unsigned int dummy_cycles;
401 bool dtr, single;
402 u8 io_mode;
403 int ret;
404
405 switch (iface) {
406 case SSDR:
407 ref_op = spinand->ssdr_op_templates.read_cache;
408 break;
409 case ODTR:
410 ref_op = spinand->odtr_op_templates.read_cache;
411 break;
412 default:
413 return -EOPNOTSUPP;
414 }
415
416 dummy_cycles = ((ref_op->dummy.nbytes * 8) / ref_op->dummy.buswidth) /
417 (ref_op->dummy.dtr ? 2 : 1);
418 switch (dummy_cycles) {
419 case 8:
420 case 12:
421 case 16:
422 case 20:
423 case 24:
424 case 28:
425 break;
426 default:
427 return -EINVAL;
428 }
429
430 ret = w35n0xjw_write_vcr(spinand, W35N01JW_VCR_DUMMY_CLOCK_REG, dummy_cycles);
431 if (ret)
432 return ret;
433
434 single = (ref_op->cmd.buswidth == 1 &&
435 ref_op->addr.buswidth == 1 &&
436 ref_op->data.buswidth == 1);
437 dtr = (ref_op->cmd.dtr && ref_op->addr.dtr && ref_op->data.dtr);
438 if (single && !dtr)
439 io_mode = W35N01JW_VCR_IO_MODE_SINGLE_SDR;
440 else if (!single && !dtr)
441 io_mode = W35N01JW_VCR_IO_MODE_OCTAL_SDR;
442 else if (!single && dtr)
443 io_mode = W35N01JW_VCR_IO_MODE_OCTAL_DDR;
444 else
445 return -EINVAL;
446
447 ret = w35n0xjw_write_vcr(spinand, W35N01JW_VCR_IO_MODE_REG, io_mode);
448 if (ret)
449 return ret;
450
451 return 0;
452 }
453
454 static const struct spinand_info winbond_spinand_table[] = {
455 /* 512M-bit densities */
456 SPINAND_INFO("W25N512GW", /* 1.8V */
457 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x20),
458 NAND_MEMORG(1, 2048, 64, 64, 512, 10, 1, 1, 1),
459 NAND_ECCREQ(1, 512),
460 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
461 &write_cache_variants,
462 &update_cache_variants),
463 0,
464 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
465 /* 1G-bit densities */
466 SPINAND_INFO("W25N01GV", /* 3.3V */
467 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
468 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
469 NAND_ECCREQ(1, 512),
470 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
471 &write_cache_variants,
472 &update_cache_variants),
473 0,
474 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
475 SPINAND_INFO("W25N01GW", /* 1.8V */
476 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x21),
477 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
478 NAND_ECCREQ(1, 512),
479 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
480 &write_cache_variants,
481 &update_cache_variants),
482 0,
483 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
484 SPINAND_INFO("W25N01JW", /* high-speed 1.8V */
485 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbc, 0x21),
486 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
487 NAND_ECCREQ(1, 512),
488 SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,
489 &write_cache_variants,
490 &update_cache_variants),
491 SPINAND_HAS_QE_BIT,
492 SPINAND_ECCINFO(&w25n01jw_ooblayout, NULL),
493 SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg)),
494 SPINAND_INFO("W25N01KV", /* 3.3V */
495 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
496 NAND_MEMORG(1, 2048, 96, 64, 1024, 20, 1, 1, 1),
497 NAND_ECCREQ(4, 512),
498 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
499 &write_cache_variants,
500 &update_cache_variants),
501 0,
502 SPINAND_ECCINFO(&w25n01kv_ooblayout, w25n02kv_ecc_get_status)),
503 SPINAND_INFO("W35N01JW", /* 1.8V */
504 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdc, 0x21),
505 NAND_MEMORG(1, 4096, 128, 64, 512, 10, 1, 1, 1),
506 NAND_ECCREQ(1, 512),
507 SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants,
508 &write_cache_octal_variants,
509 &update_cache_octal_variants),
510 0,
511 SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops),
512 SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL),
513 SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)),
514 SPINAND_INFO("W35N02JW", /* 1.8V */
515 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x22),
516 NAND_MEMORG(1, 4096, 128, 64, 512, 10, 1, 2, 1),
517 NAND_ECCREQ(1, 512),
518 SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants,
519 &write_cache_octal_variants,
520 &update_cache_octal_variants),
521 SPINAND_ODTR_PACKED_PAGE_READ,
522 SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops),
523 SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL),
524 SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)),
525 SPINAND_INFO("W35N04JW", /* 1.8V */
526 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x23),
527 NAND_MEMORG(1, 4096, 128, 64, 512, 10, 1, 4, 1),
528 NAND_ECCREQ(1, 512),
529 SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants,
530 &write_cache_octal_variants,
531 &update_cache_octal_variants),
532 SPINAND_ODTR_PACKED_PAGE_READ,
533 SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops),
534 SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL),
535 SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)),
536 /* 2G-bit densities */
537 SPINAND_INFO("W25M02GV", /* 2x1G-bit 3.3V */
538 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),
539 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2),
540 NAND_ECCREQ(1, 512),
541 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
542 &write_cache_variants,
543 &update_cache_variants),
544 0,
545 SPINAND_INFO_VENDOR_OPS(&winbond_w25_ops),
546 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
547 SPINAND_SELECT_TARGET(w25m02gv_select_target)),
548 SPINAND_INFO("W25N02JW", /* high-speed 1.8V */
549 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbf, 0x22),
550 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 2, 1),
551 NAND_ECCREQ(1, 512),
552 SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,
553 &write_cache_variants,
554 &update_cache_variants),
555 SPINAND_HAS_QE_BIT,
556 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
557 SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg)),
558 SPINAND_INFO("W25N02KV", /* 3.3V */
559 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
560 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
561 NAND_ECCREQ(8, 512),
562 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
563 &write_cache_variants,
564 &update_cache_variants),
565 0,
566 SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
567 SPINAND_INFO("W25N02KW", /* 1.8V */
568 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x22),
569 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
570 NAND_ECCREQ(8, 512),
571 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
572 &write_cache_variants,
573 &update_cache_variants),
574 0,
575 SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
576 /* 4G-bit densities */
577 SPINAND_INFO("W25N04KV", /* 3.3V */
578 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
579 NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 2, 1, 1),
580 NAND_ECCREQ(8, 512),
581 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
582 &write_cache_variants,
583 &update_cache_variants),
584 0,
585 SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
586 SPINAND_INFO("W25N04KW", /* 1.8V */
587 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xba, 0x23),
588 NAND_MEMORG(1, 2048, 128, 64, 4096, 40, 1, 1, 1),
589 NAND_ECCREQ(8, 512),
590 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
591 &write_cache_variants,
592 &update_cache_variants),
593 0,
594 SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
595 };
596
winbond_spinand_init(struct spinand_device * spinand)597 static int winbond_spinand_init(struct spinand_device *spinand)
598 {
599 struct nand_device *nand = spinand_to_nand(spinand);
600 unsigned int i;
601
602 /*
603 * Make sure all dies are in buffer read mode and not continuous read
604 * mode.
605 */
606 for (i = 0; i < nand->memorg.ntargets; i++) {
607 spinand_select_target(spinand, i);
608 spinand_upd_cfg(spinand, WINBOND_CFG_BUF_READ,
609 WINBOND_CFG_BUF_READ);
610 }
611
612 return 0;
613 }
614
615 static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
616 .init = winbond_spinand_init,
617 };
618
619 const struct spinand_manufacturer winbond_spinand_manufacturer = {
620 .id = SPINAND_MFR_WINBOND,
621 .name = "Winbond",
622 .chips = winbond_spinand_table,
623 .nchips = ARRAY_SIZE(winbond_spinand_table),
624 .ops = &winbond_spinand_manuf_ops,
625 };
626