1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #include <linux/devcoredump.h>
6
7 #include "main.h"
8 #include "regd.h"
9 #include "fw.h"
10 #include "ps.h"
11 #include "sec.h"
12 #include "mac.h"
13 #include "coex.h"
14 #include "phy.h"
15 #include "reg.h"
16 #include "efuse.h"
17 #include "tx.h"
18 #include "debug.h"
19 #include "bf.h"
20 #include "sar.h"
21 #include "sdio.h"
22 #include "led.h"
23
24 bool rtw_disable_lps_deep_mode;
25 EXPORT_SYMBOL(rtw_disable_lps_deep_mode);
26 bool rtw_bf_support = true;
27 unsigned int rtw_debug_mask;
28 EXPORT_SYMBOL(rtw_debug_mask);
29 /* EDCCA is enabled during normal behavior. For debugging purpose in
30 * a noisy environment, it can be disabled via edcca debugfs. Because
31 * all rtw88 devices will probably be affected if environment is noisy,
32 * rtw_edcca_enabled is just declared by driver instead of by device.
33 * So, turning it off will take effect for all rtw88 devices before
34 * there is a tough reason to maintain rtw_edcca_enabled by device.
35 */
36 bool rtw_edcca_enabled = true;
37
38 module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644);
39 module_param_named(support_bf, rtw_bf_support, bool, 0644);
40 module_param_named(debug_mask, rtw_debug_mask, uint, 0644);
41
42 MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS");
43 MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support");
44 MODULE_PARM_DESC(debug_mask, "Debugging mask");
45
46 static struct ieee80211_channel rtw_channeltable_2g[] = {
47 {.center_freq = 2412, .hw_value = 1,},
48 {.center_freq = 2417, .hw_value = 2,},
49 {.center_freq = 2422, .hw_value = 3,},
50 {.center_freq = 2427, .hw_value = 4,},
51 {.center_freq = 2432, .hw_value = 5,},
52 {.center_freq = 2437, .hw_value = 6,},
53 {.center_freq = 2442, .hw_value = 7,},
54 {.center_freq = 2447, .hw_value = 8,},
55 {.center_freq = 2452, .hw_value = 9,},
56 {.center_freq = 2457, .hw_value = 10,},
57 {.center_freq = 2462, .hw_value = 11,},
58 {.center_freq = 2467, .hw_value = 12,},
59 {.center_freq = 2472, .hw_value = 13,},
60 {.center_freq = 2484, .hw_value = 14,},
61 };
62
63 static struct ieee80211_channel rtw_channeltable_5g[] = {
64 {.center_freq = 5180, .hw_value = 36,},
65 {.center_freq = 5200, .hw_value = 40,},
66 {.center_freq = 5220, .hw_value = 44,},
67 {.center_freq = 5240, .hw_value = 48,},
68 {.center_freq = 5260, .hw_value = 52,},
69 {.center_freq = 5280, .hw_value = 56,},
70 {.center_freq = 5300, .hw_value = 60,},
71 {.center_freq = 5320, .hw_value = 64,},
72 {.center_freq = 5500, .hw_value = 100,},
73 {.center_freq = 5520, .hw_value = 104,},
74 {.center_freq = 5540, .hw_value = 108,},
75 {.center_freq = 5560, .hw_value = 112,},
76 {.center_freq = 5580, .hw_value = 116,},
77 {.center_freq = 5600, .hw_value = 120,},
78 {.center_freq = 5620, .hw_value = 124,},
79 {.center_freq = 5640, .hw_value = 128,},
80 {.center_freq = 5660, .hw_value = 132,},
81 {.center_freq = 5680, .hw_value = 136,},
82 {.center_freq = 5700, .hw_value = 140,},
83 {.center_freq = 5720, .hw_value = 144,},
84 {.center_freq = 5745, .hw_value = 149,},
85 {.center_freq = 5765, .hw_value = 153,},
86 {.center_freq = 5785, .hw_value = 157,},
87 {.center_freq = 5805, .hw_value = 161,},
88 {.center_freq = 5825, .hw_value = 165,
89 .flags = IEEE80211_CHAN_NO_HT40MINUS},
90 };
91
92 static struct ieee80211_rate rtw_ratetable[] = {
93 {.bitrate = 10, .hw_value = 0x00,},
94 {.bitrate = 20, .hw_value = 0x01,},
95 {.bitrate = 55, .hw_value = 0x02,},
96 {.bitrate = 110, .hw_value = 0x03,},
97 {.bitrate = 60, .hw_value = 0x04,},
98 {.bitrate = 90, .hw_value = 0x05,},
99 {.bitrate = 120, .hw_value = 0x06,},
100 {.bitrate = 180, .hw_value = 0x07,},
101 {.bitrate = 240, .hw_value = 0x08,},
102 {.bitrate = 360, .hw_value = 0x09,},
103 {.bitrate = 480, .hw_value = 0x0a,},
104 {.bitrate = 540, .hw_value = 0x0b,},
105 };
106
107 static const struct ieee80211_iface_limit rtw_iface_limits[] = {
108 {
109 .max = 1,
110 .types = BIT(NL80211_IFTYPE_STATION),
111 },
112 {
113 .max = 1,
114 .types = BIT(NL80211_IFTYPE_AP),
115 }
116 };
117
118 static const struct ieee80211_iface_combination rtw_iface_combs[] = {
119 {
120 .limits = rtw_iface_limits,
121 .n_limits = ARRAY_SIZE(rtw_iface_limits),
122 .max_interfaces = 2,
123 .num_different_channels = 1,
124 }
125 };
126
rtw_desc_to_bitrate(u8 desc_rate)127 u16 rtw_desc_to_bitrate(u8 desc_rate)
128 {
129 struct ieee80211_rate rate;
130
131 if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n"))
132 return 0;
133
134 rate = rtw_ratetable[desc_rate];
135
136 return rate.bitrate;
137 }
138
139 static const struct ieee80211_supported_band rtw_band_2ghz = {
140 .band = NL80211_BAND_2GHZ,
141
142 .channels = rtw_channeltable_2g,
143 .n_channels = ARRAY_SIZE(rtw_channeltable_2g),
144
145 .bitrates = rtw_ratetable,
146 .n_bitrates = ARRAY_SIZE(rtw_ratetable),
147
148 .ht_cap = {0},
149 .vht_cap = {0},
150 };
151
152 static const struct ieee80211_supported_band rtw_band_5ghz = {
153 .band = NL80211_BAND_5GHZ,
154
155 .channels = rtw_channeltable_5g,
156 .n_channels = ARRAY_SIZE(rtw_channeltable_5g),
157
158 /* 5G has no CCK rates */
159 .bitrates = rtw_ratetable + 4,
160 .n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
161
162 .ht_cap = {0},
163 .vht_cap = {0},
164 };
165
166 struct rtw_watch_dog_iter_data {
167 struct rtw_dev *rtwdev;
168 struct rtw_vif *rtwvif;
169 };
170
rtw_dynamic_csi_rate(struct rtw_dev * rtwdev,struct rtw_vif * rtwvif)171 static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif)
172 {
173 struct rtw_bf_info *bf_info = &rtwdev->bf_info;
174 u8 fix_rate_enable = 0;
175 u8 new_csi_rate_idx;
176
177 if (rtwvif->bfee.role != RTW_BFEE_SU &&
178 rtwvif->bfee.role != RTW_BFEE_MU)
179 return;
180
181 rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
182 bf_info->cur_csi_rpt_rate,
183 fix_rate_enable, &new_csi_rate_idx);
184
185 if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
186 bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
187 }
188
rtw_vif_watch_dog_iter(void * data,struct ieee80211_vif * vif)189 static void rtw_vif_watch_dog_iter(void *data, struct ieee80211_vif *vif)
190 {
191 struct rtw_watch_dog_iter_data *iter_data = data;
192 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
193
194 if (vif->type == NL80211_IFTYPE_STATION)
195 if (vif->cfg.assoc)
196 iter_data->rtwvif = rtwvif;
197
198 rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif);
199
200 rtwvif->stats.tx_unicast = 0;
201 rtwvif->stats.rx_unicast = 0;
202 rtwvif->stats.tx_cnt = 0;
203 rtwvif->stats.rx_cnt = 0;
204 }
205
rtw_sw_beacon_loss_check(struct rtw_dev * rtwdev,struct rtw_vif * rtwvif,int received_beacons)206 static void rtw_sw_beacon_loss_check(struct rtw_dev *rtwdev,
207 struct rtw_vif *rtwvif, int received_beacons)
208 {
209 int watchdog_delay = 2000000 / 1024; /* TU */
210 int beacon_int, expected_beacons;
211
212 if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_BCN_FILTER) || !rtwvif)
213 return;
214
215 beacon_int = rtwvif_to_vif(rtwvif)->bss_conf.beacon_int;
216 expected_beacons = DIV_ROUND_UP(watchdog_delay, beacon_int);
217
218 rtwdev->beacon_loss = received_beacons < expected_beacons / 2;
219 }
220
221 /* process TX/RX statistics periodically for hardware,
222 * the information helps hardware to enhance performance
223 */
rtw_watch_dog_work(struct work_struct * work)224 static void rtw_watch_dog_work(struct work_struct *work)
225 {
226 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
227 watch_dog_work.work);
228 struct rtw_traffic_stats *stats = &rtwdev->stats;
229 struct rtw_watch_dog_iter_data data = {};
230 bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
231 int received_beacons = rtwdev->dm_info.cur_pkt_count.num_bcn_pkt;
232 u32 tx_unicast_mbps, rx_unicast_mbps;
233 bool ps_active;
234
235 mutex_lock(&rtwdev->mutex);
236
237 if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
238 goto unlock;
239
240 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
241 RTW_WATCH_DOG_DELAY_TIME);
242
243 if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
244 set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
245 else
246 clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
247
248 if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
249 rtw_coex_wl_status_change_notify(rtwdev, 0);
250
251 if (stats->tx_cnt > RTW_LPS_THRESHOLD ||
252 stats->rx_cnt > RTW_LPS_THRESHOLD)
253 ps_active = true;
254 else
255 ps_active = false;
256
257 tx_unicast_mbps = stats->tx_unicast >> RTW_TP_SHIFT;
258 rx_unicast_mbps = stats->rx_unicast >> RTW_TP_SHIFT;
259
260 ewma_tp_add(&stats->tx_ewma_tp, tx_unicast_mbps);
261 ewma_tp_add(&stats->rx_ewma_tp, rx_unicast_mbps);
262 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
263 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
264
265 /* reset tx/rx statictics */
266 stats->tx_unicast = 0;
267 stats->rx_unicast = 0;
268 stats->tx_cnt = 0;
269 stats->rx_cnt = 0;
270
271 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
272 goto unlock;
273
274 /* make sure BB/RF is working for dynamic mech */
275 rtw_leave_lps(rtwdev);
276 rtw_coex_wl_status_check(rtwdev);
277 rtw_coex_query_bt_hid_list(rtwdev);
278 rtw_coex_active_query_bt_info(rtwdev);
279
280 rtw_phy_dynamic_mechanism(rtwdev);
281
282 rtw_hci_dynamic_rx_agg(rtwdev,
283 tx_unicast_mbps >= 1 || rx_unicast_mbps >= 1);
284
285 data.rtwdev = rtwdev;
286 /* rtw_iterate_vifs internally uses an atomic iterator which is needed
287 * to avoid taking local->iflist_mtx mutex
288 */
289 rtw_iterate_vifs(rtwdev, rtw_vif_watch_dog_iter, &data);
290
291 rtw_sw_beacon_loss_check(rtwdev, data.rtwvif, received_beacons);
292
293 /* fw supports only one station associated to enter lps, if there are
294 * more than two stations associated to the AP, then we can not enter
295 * lps, because fw does not handle the overlapped beacon interval
296 *
297 * rtw_recalc_lps() iterate vifs and determine if driver can enter
298 * ps by vif->type and vif->cfg.ps, all we need to do here is to
299 * get that vif and check if device is having traffic more than the
300 * threshold.
301 */
302 if (rtwdev->ps_enabled && data.rtwvif && !ps_active &&
303 !rtwdev->beacon_loss && !rtwdev->ap_active)
304 rtw_enter_lps(rtwdev, data.rtwvif->port);
305
306 rtwdev->watch_dog_cnt++;
307
308 unlock:
309 mutex_unlock(&rtwdev->mutex);
310 }
311
rtw_c2h_work(struct work_struct * work)312 static void rtw_c2h_work(struct work_struct *work)
313 {
314 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work);
315 struct sk_buff *skb, *tmp;
316
317 skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
318 skb_unlink(skb, &rtwdev->c2h_queue);
319 rtw_fw_c2h_cmd_handle(rtwdev, skb);
320 dev_kfree_skb_any(skb);
321 }
322 }
323
rtw_ips_work(struct work_struct * work)324 static void rtw_ips_work(struct work_struct *work)
325 {
326 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work);
327
328 mutex_lock(&rtwdev->mutex);
329 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)
330 rtw_enter_ips(rtwdev);
331 mutex_unlock(&rtwdev->mutex);
332 }
333
rtw_sta_rc_work(struct work_struct * work)334 static void rtw_sta_rc_work(struct work_struct *work)
335 {
336 struct rtw_sta_info *si = container_of(work, struct rtw_sta_info,
337 rc_work);
338 struct rtw_dev *rtwdev = si->rtwdev;
339
340 mutex_lock(&rtwdev->mutex);
341 rtw_update_sta_info(rtwdev, si, true);
342 mutex_unlock(&rtwdev->mutex);
343 }
344
rtw_sta_add(struct rtw_dev * rtwdev,struct ieee80211_sta * sta,struct ieee80211_vif * vif)345 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
346 struct ieee80211_vif *vif)
347 {
348 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
349 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
350 int i;
351
352 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
353 si->mac_id = rtwvif->mac_id;
354 } else {
355 si->mac_id = rtw_acquire_macid(rtwdev);
356 if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
357 return -ENOSPC;
358 }
359
360 si->rtwdev = rtwdev;
361 si->sta = sta;
362 si->vif = vif;
363 si->init_ra_lv = 1;
364 ewma_rssi_init(&si->avg_rssi);
365 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
366 rtw_txq_init(rtwdev, sta->txq[i]);
367 INIT_WORK(&si->rc_work, rtw_sta_rc_work);
368
369 rtw_update_sta_info(rtwdev, si, true);
370 rtw_fw_media_status_report(rtwdev, si->mac_id, true);
371
372 rtwdev->sta_cnt++;
373 rtwdev->beacon_loss = false;
374 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n",
375 sta->addr, si->mac_id);
376
377 return 0;
378 }
379
rtw_sta_remove(struct rtw_dev * rtwdev,struct ieee80211_sta * sta,bool fw_exist)380 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
381 bool fw_exist)
382 {
383 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
384 struct ieee80211_vif *vif = si->vif;
385 int i;
386
387 cancel_work_sync(&si->rc_work);
388
389 if (vif->type != NL80211_IFTYPE_STATION || sta->tdls)
390 rtw_release_macid(rtwdev, si->mac_id);
391 if (fw_exist)
392 rtw_fw_media_status_report(rtwdev, si->mac_id, false);
393
394 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
395 rtw_txq_cleanup(rtwdev, sta->txq[i]);
396
397 kfree(si->mask);
398
399 rtwdev->sta_cnt--;
400 rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n",
401 sta->addr, si->mac_id);
402 }
403
404 struct rtw_fwcd_hdr {
405 u32 item;
406 u32 size;
407 u32 padding1;
408 u32 padding2;
409 } __packed;
410
rtw_fwcd_prep(struct rtw_dev * rtwdev)411 static int rtw_fwcd_prep(struct rtw_dev *rtwdev)
412 {
413 const struct rtw_chip_info *chip = rtwdev->chip;
414 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
415 const struct rtw_fwcd_segs *segs = chip->fwcd_segs;
416 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr);
417 u8 i;
418
419 if (segs) {
420 prep_size += segs->num * sizeof(struct rtw_fwcd_hdr);
421
422 for (i = 0; i < segs->num; i++)
423 prep_size += segs->segs[i];
424 }
425
426 desc->data = vmalloc(prep_size);
427 if (!desc->data)
428 return -ENOMEM;
429
430 desc->size = prep_size;
431 desc->next = desc->data;
432
433 return 0;
434 }
435
rtw_fwcd_next(struct rtw_dev * rtwdev,u32 item,u32 size)436 static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size)
437 {
438 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
439 struct rtw_fwcd_hdr *hdr;
440 u8 *next;
441
442 if (!desc->data) {
443 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n");
444 return NULL;
445 }
446
447 next = desc->next + sizeof(struct rtw_fwcd_hdr);
448 if (next - desc->data + size > desc->size) {
449 rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n");
450 return NULL;
451 }
452
453 hdr = (struct rtw_fwcd_hdr *)(desc->next);
454 hdr->item = item;
455 hdr->size = size;
456 hdr->padding1 = 0x01234567;
457 hdr->padding2 = 0x89abcdef;
458 desc->next = next + size;
459
460 return next;
461 }
462
rtw_fwcd_dump(struct rtw_dev * rtwdev)463 static void rtw_fwcd_dump(struct rtw_dev *rtwdev)
464 {
465 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
466
467 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n");
468
469 /* Data will be freed after lifetime of device coredump. After calling
470 * dev_coredump, data is supposed to be handled by the device coredump
471 * framework. Note that a new dump will be discarded if a previous one
472 * hasn't been released yet.
473 */
474 dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL);
475 }
476
rtw_fwcd_free(struct rtw_dev * rtwdev,bool free_self)477 static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self)
478 {
479 struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
480
481 if (free_self) {
482 rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n");
483 vfree(desc->data);
484 }
485
486 desc->data = NULL;
487 desc->next = NULL;
488 }
489
rtw_fw_dump_crash_log(struct rtw_dev * rtwdev)490 static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev)
491 {
492 u32 size = rtwdev->chip->fw_rxff_size;
493 u32 *buf;
494 u8 seq;
495
496 buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size);
497 if (!buf)
498 return -ENOMEM;
499
500 if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {
501 rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n");
502 return -EINVAL;
503 }
504
505 if (GET_FW_DUMP_LEN(buf) == 0) {
506 rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n");
507 return -EINVAL;
508 }
509
510 seq = GET_FW_DUMP_SEQ(buf);
511 if (seq > 0) {
512 rtw_dbg(rtwdev, RTW_DBG_FW,
513 "fw crash dump's seq is wrong: %d\n", seq);
514 return -EINVAL;
515 }
516
517 return 0;
518 }
519
rtw_dump_fw(struct rtw_dev * rtwdev,const u32 ocp_src,u32 size,u32 fwcd_item)520 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
521 u32 fwcd_item)
522 {
523 u32 rxff = rtwdev->chip->fw_rxff_size;
524 u32 dump_size, done_size = 0;
525 u8 *buf;
526 int ret;
527
528 buf = rtw_fwcd_next(rtwdev, fwcd_item, size);
529 if (!buf)
530 return -ENOMEM;
531
532 while (size) {
533 dump_size = size > rxff ? rxff : size;
534
535 ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size,
536 dump_size);
537 if (ret) {
538 rtw_err(rtwdev,
539 "ddma fw 0x%x [+0x%x] to fw fifo fail\n",
540 ocp_src, done_size);
541 return ret;
542 }
543
544 ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0,
545 dump_size, (u32 *)(buf + done_size));
546 if (ret) {
547 rtw_err(rtwdev,
548 "dump fw 0x%x [+0x%x] from fw fifo fail\n",
549 ocp_src, done_size);
550 return ret;
551 }
552
553 size -= dump_size;
554 done_size += dump_size;
555 }
556
557 return 0;
558 }
559 EXPORT_SYMBOL(rtw_dump_fw);
560
rtw_dump_reg(struct rtw_dev * rtwdev,const u32 addr,const u32 size)561 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size)
562 {
563 u8 *buf;
564 u32 i;
565
566 if (addr & 0x3) {
567 WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr);
568 return -EINVAL;
569 }
570
571 buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size);
572 if (!buf)
573 return -ENOMEM;
574
575 for (i = 0; i < size; i += 4)
576 *(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i);
577
578 return 0;
579 }
580 EXPORT_SYMBOL(rtw_dump_reg);
581
rtw_vif_assoc_changed(struct rtw_vif * rtwvif,struct ieee80211_bss_conf * conf)582 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
583 struct ieee80211_bss_conf *conf)
584 {
585 struct ieee80211_vif *vif = NULL;
586
587 if (conf)
588 vif = container_of(conf, struct ieee80211_vif, bss_conf);
589
590 if (conf && vif->cfg.assoc) {
591 rtwvif->aid = vif->cfg.aid;
592 rtwvif->net_type = RTW_NET_MGD_LINKED;
593 } else {
594 rtwvif->aid = 0;
595 rtwvif->net_type = RTW_NET_NO_LINK;
596 }
597 }
598
rtw_reset_key_iter(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key,void * data)599 static void rtw_reset_key_iter(struct ieee80211_hw *hw,
600 struct ieee80211_vif *vif,
601 struct ieee80211_sta *sta,
602 struct ieee80211_key_conf *key,
603 void *data)
604 {
605 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
606 struct rtw_sec_desc *sec = &rtwdev->sec;
607
608 rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx);
609 }
610
rtw_reset_sta_iter(void * data,struct ieee80211_sta * sta)611 static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta)
612 {
613 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
614
615 if (rtwdev->sta_cnt == 0) {
616 rtw_warn(rtwdev, "sta count before reset should not be 0\n");
617 return;
618 }
619 rtw_sta_remove(rtwdev, sta, false);
620 }
621
rtw_reset_vif_iter(void * data,u8 * mac,struct ieee80211_vif * vif)622 static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
623 {
624 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
625 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
626
627 rtw_bf_disassoc(rtwdev, vif, NULL);
628 rtw_vif_assoc_changed(rtwvif, NULL);
629 rtw_txq_cleanup(rtwdev, vif->txq);
630
631 rtw_release_macid(rtwdev, rtwvif->mac_id);
632 }
633
rtw_fw_recovery(struct rtw_dev * rtwdev)634 void rtw_fw_recovery(struct rtw_dev *rtwdev)
635 {
636 if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags))
637 ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work);
638 }
639 EXPORT_SYMBOL(rtw_fw_recovery);
640
__fw_recovery_work(struct rtw_dev * rtwdev)641 static void __fw_recovery_work(struct rtw_dev *rtwdev)
642 {
643 int ret = 0;
644
645 set_bit(RTW_FLAG_RESTARTING, rtwdev->flags);
646 clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags);
647
648 ret = rtw_fwcd_prep(rtwdev);
649 if (ret)
650 goto free;
651 ret = rtw_fw_dump_crash_log(rtwdev);
652 if (ret)
653 goto free;
654 ret = rtw_chip_dump_fw_crash(rtwdev);
655 if (ret)
656 goto free;
657
658 rtw_fwcd_dump(rtwdev);
659 free:
660 rtw_fwcd_free(rtwdev, !!ret);
661 rtw_write8(rtwdev, REG_MCU_TST_CFG, 0);
662
663 WARN(1, "firmware crash, start reset and recover\n");
664
665 rcu_read_lock();
666 rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev);
667 rcu_read_unlock();
668 rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev);
669 rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev);
670 bitmap_zero(rtwdev->hw_port, RTW_PORT_NUM);
671 rtw_enter_ips(rtwdev);
672 }
673
rtw_fw_recovery_work(struct work_struct * work)674 static void rtw_fw_recovery_work(struct work_struct *work)
675 {
676 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
677 fw_recovery_work);
678
679 mutex_lock(&rtwdev->mutex);
680 __fw_recovery_work(rtwdev);
681 mutex_unlock(&rtwdev->mutex);
682
683 ieee80211_restart_hw(rtwdev->hw);
684 }
685
686 struct rtw_txq_ba_iter_data {
687 };
688
rtw_txq_ba_iter(void * data,struct ieee80211_sta * sta)689 static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta)
690 {
691 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
692 int ret;
693 u8 tid;
694
695 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
696 while (tid != IEEE80211_NUM_TIDS) {
697 clear_bit(tid, si->tid_ba);
698 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
699 if (ret == -EINVAL) {
700 struct ieee80211_txq *txq;
701 struct rtw_txq *rtwtxq;
702
703 txq = sta->txq[tid];
704 rtwtxq = (struct rtw_txq *)txq->drv_priv;
705 set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags);
706 }
707
708 tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
709 }
710 }
711
rtw_txq_ba_work(struct work_struct * work)712 static void rtw_txq_ba_work(struct work_struct *work)
713 {
714 struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work);
715 struct rtw_txq_ba_iter_data data;
716
717 rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data);
718 }
719
rtw_set_rx_freq_band(struct rtw_rx_pkt_stat * pkt_stat,u8 channel)720 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel)
721 {
722 if (IS_CH_2G_BAND(channel))
723 pkt_stat->band = NL80211_BAND_2GHZ;
724 else if (IS_CH_5G_BAND(channel))
725 pkt_stat->band = NL80211_BAND_5GHZ;
726 else
727 return;
728
729 pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band);
730 }
731 EXPORT_SYMBOL(rtw_set_rx_freq_band);
732
rtw_set_dtim_period(struct rtw_dev * rtwdev,int dtim_period)733 void rtw_set_dtim_period(struct rtw_dev *rtwdev, int dtim_period)
734 {
735 rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE);
736 rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period - 1);
737 }
738
rtw_update_channel(struct rtw_dev * rtwdev,u8 center_channel,u8 primary_channel,enum rtw_supported_band band,enum rtw_bandwidth bandwidth)739 void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
740 u8 primary_channel, enum rtw_supported_band band,
741 enum rtw_bandwidth bandwidth)
742 {
743 enum nl80211_band nl_band = rtw_hw_to_nl80211_band(band);
744 struct rtw_hal *hal = &rtwdev->hal;
745 u8 *cch_by_bw = hal->cch_by_bw;
746 u32 center_freq, primary_freq;
747 enum rtw_sar_bands sar_band;
748 u8 primary_channel_idx;
749
750 center_freq = ieee80211_channel_to_frequency(center_channel, nl_band);
751 primary_freq = ieee80211_channel_to_frequency(primary_channel, nl_band);
752
753 /* assign the center channel used while 20M bw is selected */
754 cch_by_bw[RTW_CHANNEL_WIDTH_20] = primary_channel;
755
756 /* assign the center channel used while current bw is selected */
757 cch_by_bw[bandwidth] = center_channel;
758
759 switch (bandwidth) {
760 case RTW_CHANNEL_WIDTH_20:
761 default:
762 primary_channel_idx = RTW_SC_DONT_CARE;
763 break;
764 case RTW_CHANNEL_WIDTH_40:
765 if (primary_freq > center_freq)
766 primary_channel_idx = RTW_SC_20_UPPER;
767 else
768 primary_channel_idx = RTW_SC_20_LOWER;
769 break;
770 case RTW_CHANNEL_WIDTH_80:
771 if (primary_freq > center_freq) {
772 if (primary_freq - center_freq == 10)
773 primary_channel_idx = RTW_SC_20_UPPER;
774 else
775 primary_channel_idx = RTW_SC_20_UPMOST;
776
777 /* assign the center channel used
778 * while 40M bw is selected
779 */
780 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel + 4;
781 } else {
782 if (center_freq - primary_freq == 10)
783 primary_channel_idx = RTW_SC_20_LOWER;
784 else
785 primary_channel_idx = RTW_SC_20_LOWEST;
786
787 /* assign the center channel used
788 * while 40M bw is selected
789 */
790 cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4;
791 }
792 break;
793 }
794
795 switch (center_channel) {
796 case 1 ... 14:
797 sar_band = RTW_SAR_BAND_0;
798 break;
799 case 36 ... 64:
800 sar_band = RTW_SAR_BAND_1;
801 break;
802 case 100 ... 144:
803 sar_band = RTW_SAR_BAND_3;
804 break;
805 case 149 ... 177:
806 sar_band = RTW_SAR_BAND_4;
807 break;
808 default:
809 WARN(1, "unknown ch(%u) to SAR band\n", center_channel);
810 sar_band = RTW_SAR_BAND_0;
811 break;
812 }
813
814 hal->current_primary_channel_index = primary_channel_idx;
815 hal->current_band_width = bandwidth;
816 hal->primary_channel = primary_channel;
817 hal->current_channel = center_channel;
818 hal->current_band_type = band;
819 hal->sar_band = sar_band;
820 }
821
rtw_get_channel_params(struct cfg80211_chan_def * chandef,struct rtw_channel_params * chan_params)822 void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
823 struct rtw_channel_params *chan_params)
824 {
825 struct ieee80211_channel *channel = chandef->chan;
826 enum nl80211_chan_width width = chandef->width;
827 u32 primary_freq, center_freq;
828 u8 center_chan;
829 u8 bandwidth = RTW_CHANNEL_WIDTH_20;
830
831 center_chan = channel->hw_value;
832 primary_freq = channel->center_freq;
833 center_freq = chandef->center_freq1;
834
835 switch (width) {
836 case NL80211_CHAN_WIDTH_20_NOHT:
837 case NL80211_CHAN_WIDTH_20:
838 bandwidth = RTW_CHANNEL_WIDTH_20;
839 break;
840 case NL80211_CHAN_WIDTH_40:
841 bandwidth = RTW_CHANNEL_WIDTH_40;
842 if (primary_freq > center_freq)
843 center_chan -= 2;
844 else
845 center_chan += 2;
846 break;
847 case NL80211_CHAN_WIDTH_80:
848 bandwidth = RTW_CHANNEL_WIDTH_80;
849 if (primary_freq > center_freq) {
850 if (primary_freq - center_freq == 10)
851 center_chan -= 2;
852 else
853 center_chan -= 6;
854 } else {
855 if (center_freq - primary_freq == 10)
856 center_chan += 2;
857 else
858 center_chan += 6;
859 }
860 break;
861 default:
862 center_chan = 0;
863 break;
864 }
865
866 chan_params->center_chan = center_chan;
867 chan_params->bandwidth = bandwidth;
868 chan_params->primary_chan = channel->hw_value;
869 }
870
rtw_set_channel(struct rtw_dev * rtwdev)871 void rtw_set_channel(struct rtw_dev *rtwdev)
872 {
873 const struct rtw_chip_info *chip = rtwdev->chip;
874 struct ieee80211_hw *hw = rtwdev->hw;
875 struct rtw_hal *hal = &rtwdev->hal;
876 struct rtw_channel_params ch_param;
877 u8 center_chan, primary_chan, bandwidth, band;
878
879 rtw_get_channel_params(&hw->conf.chandef, &ch_param);
880 if (WARN(ch_param.center_chan == 0, "Invalid channel\n"))
881 return;
882
883 center_chan = ch_param.center_chan;
884 primary_chan = ch_param.primary_chan;
885 bandwidth = ch_param.bandwidth;
886 band = ch_param.center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G;
887
888 rtw_update_channel(rtwdev, center_chan, primary_chan, band, bandwidth);
889
890 if (rtwdev->scan_info.op_chan)
891 rtw_store_op_chan(rtwdev, true);
892
893 chip->ops->set_channel(rtwdev, center_chan, bandwidth,
894 hal->current_primary_channel_index);
895
896 if (hal->current_band_type == RTW_BAND_5G) {
897 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
898 } else {
899 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
900 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
901 else
902 rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
903 }
904
905 rtw_phy_set_tx_power_level(rtwdev, center_chan);
906
907 /* if the channel isn't set for scanning, we will do RF calibration
908 * in ieee80211_ops::mgd_prepare_tx(). Performing the calibration
909 * during scanning on each channel takes too long.
910 */
911 if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
912 rtwdev->need_rfk = true;
913 }
914
rtw_chip_prepare_tx(struct rtw_dev * rtwdev)915 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev)
916 {
917 const struct rtw_chip_info *chip = rtwdev->chip;
918
919 if (rtwdev->need_rfk) {
920 rtwdev->need_rfk = false;
921 chip->ops->phy_calibration(rtwdev);
922 }
923 }
924
rtw_vif_write_addr(struct rtw_dev * rtwdev,u32 start,u8 * addr)925 static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr)
926 {
927 int i;
928
929 for (i = 0; i < ETH_ALEN; i++)
930 rtw_write8(rtwdev, start + i, addr[i]);
931 }
932
rtw_vif_port_config(struct rtw_dev * rtwdev,struct rtw_vif * rtwvif,u32 config)933 void rtw_vif_port_config(struct rtw_dev *rtwdev,
934 struct rtw_vif *rtwvif,
935 u32 config)
936 {
937 u32 addr, mask;
938
939 if (config & PORT_SET_MAC_ADDR) {
940 addr = rtwvif->conf->mac_addr.addr;
941 rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr);
942 }
943 if (config & PORT_SET_BSSID) {
944 addr = rtwvif->conf->bssid.addr;
945 rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid);
946 }
947 if (config & PORT_SET_NET_TYPE) {
948 addr = rtwvif->conf->net_type.addr;
949 mask = rtwvif->conf->net_type.mask;
950 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
951 }
952 if (config & PORT_SET_AID) {
953 addr = rtwvif->conf->aid.addr;
954 mask = rtwvif->conf->aid.mask;
955 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
956 }
957 if (config & PORT_SET_BCN_CTRL) {
958 addr = rtwvif->conf->bcn_ctrl.addr;
959 mask = rtwvif->conf->bcn_ctrl.mask;
960 rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
961 }
962 }
963
hw_bw_cap_to_bitamp(u8 bw_cap)964 static u8 hw_bw_cap_to_bitamp(u8 bw_cap)
965 {
966 u8 bw = 0;
967
968 switch (bw_cap) {
969 case EFUSE_HW_CAP_IGNORE:
970 case EFUSE_HW_CAP_SUPP_BW80:
971 bw |= BIT(RTW_CHANNEL_WIDTH_80);
972 fallthrough;
973 case EFUSE_HW_CAP_SUPP_BW40:
974 bw |= BIT(RTW_CHANNEL_WIDTH_40);
975 fallthrough;
976 default:
977 bw |= BIT(RTW_CHANNEL_WIDTH_20);
978 break;
979 }
980
981 return bw;
982 }
983
rtw_hw_config_rf_ant_num(struct rtw_dev * rtwdev,u8 hw_ant_num)984 static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num)
985 {
986 const struct rtw_chip_info *chip = rtwdev->chip;
987 struct rtw_hal *hal = &rtwdev->hal;
988
989 if (hw_ant_num == EFUSE_HW_CAP_IGNORE ||
990 hw_ant_num >= hal->rf_path_num)
991 return;
992
993 switch (hw_ant_num) {
994 case 1:
995 hal->rf_type = RF_1T1R;
996 hal->rf_path_num = 1;
997 if (!chip->fix_rf_phy_num)
998 hal->rf_phy_num = hal->rf_path_num;
999 hal->antenna_tx = BB_PATH_A;
1000 hal->antenna_rx = BB_PATH_A;
1001 break;
1002 default:
1003 WARN(1, "invalid hw configuration from efuse\n");
1004 break;
1005 }
1006 }
1007
get_vht_ra_mask(struct ieee80211_sta * sta)1008 static u64 get_vht_ra_mask(struct ieee80211_sta *sta)
1009 {
1010 u64 ra_mask = 0;
1011 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map);
1012 u8 vht_mcs_cap;
1013 int i, nss;
1014
1015 /* 4SS, every two bits for MCS7/8/9 */
1016 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) {
1017 vht_mcs_cap = mcs_map & 0x3;
1018 switch (vht_mcs_cap) {
1019 case 2: /* MCS9 */
1020 ra_mask |= 0x3ffULL << nss;
1021 break;
1022 case 1: /* MCS8 */
1023 ra_mask |= 0x1ffULL << nss;
1024 break;
1025 case 0: /* MCS7 */
1026 ra_mask |= 0x0ffULL << nss;
1027 break;
1028 default:
1029 break;
1030 }
1031 }
1032
1033 return ra_mask;
1034 }
1035
get_rate_id(u8 wireless_set,enum rtw_bandwidth bw_mode,u8 tx_num)1036 static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num)
1037 {
1038 u8 rate_id = 0;
1039
1040 switch (wireless_set) {
1041 case WIRELESS_CCK:
1042 rate_id = RTW_RATEID_B_20M;
1043 break;
1044 case WIRELESS_OFDM:
1045 rate_id = RTW_RATEID_G;
1046 break;
1047 case WIRELESS_CCK | WIRELESS_OFDM:
1048 rate_id = RTW_RATEID_BG;
1049 break;
1050 case WIRELESS_OFDM | WIRELESS_HT:
1051 if (tx_num == 1)
1052 rate_id = RTW_RATEID_GN_N1SS;
1053 else if (tx_num == 2)
1054 rate_id = RTW_RATEID_GN_N2SS;
1055 else if (tx_num == 3)
1056 rate_id = RTW_RATEID_ARFR5_N_3SS;
1057 break;
1058 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT:
1059 if (bw_mode == RTW_CHANNEL_WIDTH_40) {
1060 if (tx_num == 1)
1061 rate_id = RTW_RATEID_BGN_40M_1SS;
1062 else if (tx_num == 2)
1063 rate_id = RTW_RATEID_BGN_40M_2SS;
1064 else if (tx_num == 3)
1065 rate_id = RTW_RATEID_ARFR5_N_3SS;
1066 else if (tx_num == 4)
1067 rate_id = RTW_RATEID_ARFR7_N_4SS;
1068 } else {
1069 if (tx_num == 1)
1070 rate_id = RTW_RATEID_BGN_20M_1SS;
1071 else if (tx_num == 2)
1072 rate_id = RTW_RATEID_BGN_20M_2SS;
1073 else if (tx_num == 3)
1074 rate_id = RTW_RATEID_ARFR5_N_3SS;
1075 else if (tx_num == 4)
1076 rate_id = RTW_RATEID_ARFR7_N_4SS;
1077 }
1078 break;
1079 case WIRELESS_OFDM | WIRELESS_VHT:
1080 if (tx_num == 1)
1081 rate_id = RTW_RATEID_ARFR1_AC_1SS;
1082 else if (tx_num == 2)
1083 rate_id = RTW_RATEID_ARFR0_AC_2SS;
1084 else if (tx_num == 3)
1085 rate_id = RTW_RATEID_ARFR4_AC_3SS;
1086 else if (tx_num == 4)
1087 rate_id = RTW_RATEID_ARFR6_AC_4SS;
1088 break;
1089 case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT:
1090 if (bw_mode >= RTW_CHANNEL_WIDTH_80) {
1091 if (tx_num == 1)
1092 rate_id = RTW_RATEID_ARFR1_AC_1SS;
1093 else if (tx_num == 2)
1094 rate_id = RTW_RATEID_ARFR0_AC_2SS;
1095 else if (tx_num == 3)
1096 rate_id = RTW_RATEID_ARFR4_AC_3SS;
1097 else if (tx_num == 4)
1098 rate_id = RTW_RATEID_ARFR6_AC_4SS;
1099 } else {
1100 if (tx_num == 1)
1101 rate_id = RTW_RATEID_ARFR2_AC_2G_1SS;
1102 else if (tx_num == 2)
1103 rate_id = RTW_RATEID_ARFR3_AC_2G_2SS;
1104 else if (tx_num == 3)
1105 rate_id = RTW_RATEID_ARFR4_AC_3SS;
1106 else if (tx_num == 4)
1107 rate_id = RTW_RATEID_ARFR6_AC_4SS;
1108 }
1109 break;
1110 default:
1111 break;
1112 }
1113
1114 return rate_id;
1115 }
1116
1117 #define RA_MASK_CCK_RATES 0x0000f
1118 #define RA_MASK_OFDM_RATES 0x00ff0
1119 #define RA_MASK_HT_RATES_1SS (0xff000ULL << 0)
1120 #define RA_MASK_HT_RATES_2SS (0xff000ULL << 8)
1121 #define RA_MASK_HT_RATES_3SS (0xff000ULL << 16)
1122 #define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \
1123 RA_MASK_HT_RATES_2SS | \
1124 RA_MASK_HT_RATES_3SS)
1125 #define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0)
1126 #define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10)
1127 #define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20)
1128 #define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \
1129 RA_MASK_VHT_RATES_2SS | \
1130 RA_MASK_VHT_RATES_3SS)
1131 #define RA_MASK_CCK_IN_BG 0x00005
1132 #define RA_MASK_CCK_IN_HT 0x00005
1133 #define RA_MASK_CCK_IN_VHT 0x00005
1134 #define RA_MASK_OFDM_IN_VHT 0x00010
1135 #define RA_MASK_OFDM_IN_HT_2G 0x00010
1136 #define RA_MASK_OFDM_IN_HT_5G 0x00030
1137
rtw_rate_mask_rssi(struct rtw_sta_info * si,u8 wireless_set)1138 static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set)
1139 {
1140 u8 rssi_level = si->rssi_level;
1141
1142 if (wireless_set == WIRELESS_CCK)
1143 return 0xffffffffffffffffULL;
1144
1145 if (rssi_level == 0)
1146 return 0xffffffffffffffffULL;
1147 else if (rssi_level == 1)
1148 return 0xfffffffffffffff0ULL;
1149 else if (rssi_level == 2)
1150 return 0xffffffffffffefe0ULL;
1151 else if (rssi_level == 3)
1152 return 0xffffffffffffcfc0ULL;
1153 else if (rssi_level == 4)
1154 return 0xffffffffffff8f80ULL;
1155 else
1156 return 0xffffffffffff0f00ULL;
1157 }
1158
rtw_rate_mask_recover(u64 ra_mask,u64 ra_mask_bak)1159 static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak)
1160 {
1161 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
1162 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
1163
1164 if (ra_mask == 0)
1165 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
1166
1167 return ra_mask;
1168 }
1169
rtw_rate_mask_cfg(struct rtw_dev * rtwdev,struct rtw_sta_info * si,u64 ra_mask,bool is_vht_enable)1170 static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
1171 u64 ra_mask, bool is_vht_enable)
1172 {
1173 struct rtw_hal *hal = &rtwdev->hal;
1174 const struct cfg80211_bitrate_mask *mask = si->mask;
1175 u64 cfg_mask = GENMASK_ULL(63, 0);
1176 u8 band;
1177
1178 if (!si->use_cfg_mask)
1179 return ra_mask;
1180
1181 band = hal->current_band_type;
1182 if (band == RTW_BAND_2G) {
1183 band = NL80211_BAND_2GHZ;
1184 cfg_mask = mask->control[band].legacy;
1185 } else if (band == RTW_BAND_5G) {
1186 band = NL80211_BAND_5GHZ;
1187 cfg_mask = u64_encode_bits(mask->control[band].legacy,
1188 RA_MASK_OFDM_RATES);
1189 }
1190
1191 if (!is_vht_enable) {
1192 if (ra_mask & RA_MASK_HT_RATES_1SS)
1193 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
1194 RA_MASK_HT_RATES_1SS);
1195 if (ra_mask & RA_MASK_HT_RATES_2SS)
1196 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
1197 RA_MASK_HT_RATES_2SS);
1198 } else {
1199 if (ra_mask & RA_MASK_VHT_RATES_1SS)
1200 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
1201 RA_MASK_VHT_RATES_1SS);
1202 if (ra_mask & RA_MASK_VHT_RATES_2SS)
1203 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
1204 RA_MASK_VHT_RATES_2SS);
1205 }
1206
1207 ra_mask &= cfg_mask;
1208
1209 return ra_mask;
1210 }
1211
rtw_update_sta_info(struct rtw_dev * rtwdev,struct rtw_sta_info * si,bool reset_ra_mask)1212 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
1213 bool reset_ra_mask)
1214 {
1215 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1216 struct ieee80211_sta *sta = si->sta;
1217 struct rtw_efuse *efuse = &rtwdev->efuse;
1218 struct rtw_hal *hal = &rtwdev->hal;
1219 u8 wireless_set;
1220 u8 bw_mode;
1221 u8 rate_id;
1222 u8 stbc_en = 0;
1223 u8 ldpc_en = 0;
1224 u8 tx_num = 1;
1225 u64 ra_mask = 0;
1226 u64 ra_mask_bak = 0;
1227 bool is_vht_enable = false;
1228 bool is_support_sgi = false;
1229
1230 if (sta->deflink.vht_cap.vht_supported) {
1231 is_vht_enable = true;
1232 ra_mask |= get_vht_ra_mask(sta);
1233 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
1234 stbc_en = VHT_STBC_EN;
1235 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
1236 ldpc_en = VHT_LDPC_EN;
1237 } else if (sta->deflink.ht_cap.ht_supported) {
1238 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 36) |
1239 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 28) |
1240 (sta->deflink.ht_cap.mcs.rx_mask[1] << 20) |
1241 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1242 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
1243 stbc_en = HT_STBC_EN;
1244 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
1245 ldpc_en = HT_LDPC_EN;
1246 }
1247
1248 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss)
1249 ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
1250 else if (efuse->hw_cap.nss == 2)
1251 ra_mask &= RA_MASK_VHT_RATES_2SS | RA_MASK_HT_RATES_2SS |
1252 RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
1253
1254 if (hal->current_band_type == RTW_BAND_5G) {
1255 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4;
1256 ra_mask_bak = ra_mask;
1257 if (sta->deflink.vht_cap.vht_supported) {
1258 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT;
1259 wireless_set = WIRELESS_OFDM | WIRELESS_VHT;
1260 } else if (sta->deflink.ht_cap.ht_supported) {
1261 ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G;
1262 wireless_set = WIRELESS_OFDM | WIRELESS_HT;
1263 } else {
1264 wireless_set = WIRELESS_OFDM;
1265 }
1266 dm_info->rrsr_val_init = RRSR_INIT_5G;
1267 } else if (hal->current_band_type == RTW_BAND_2G) {
1268 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ];
1269 ra_mask_bak = ra_mask;
1270 if (sta->deflink.vht_cap.vht_supported) {
1271 ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT |
1272 RA_MASK_OFDM_IN_VHT;
1273 wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
1274 WIRELESS_HT | WIRELESS_VHT;
1275 } else if (sta->deflink.ht_cap.ht_supported) {
1276 ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT |
1277 RA_MASK_OFDM_IN_HT_2G;
1278 wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
1279 WIRELESS_HT;
1280 } else if (sta->deflink.supp_rates[0] <= 0xf) {
1281 wireless_set = WIRELESS_CCK;
1282 } else {
1283 ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG;
1284 wireless_set = WIRELESS_CCK | WIRELESS_OFDM;
1285 }
1286 dm_info->rrsr_val_init = RRSR_INIT_2G;
1287 } else {
1288 rtw_err(rtwdev, "Unknown band type\n");
1289 ra_mask_bak = ra_mask;
1290 wireless_set = 0;
1291 }
1292
1293 switch (sta->deflink.bandwidth) {
1294 case IEEE80211_STA_RX_BW_80:
1295 bw_mode = RTW_CHANNEL_WIDTH_80;
1296 is_support_sgi = sta->deflink.vht_cap.vht_supported &&
1297 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
1298 break;
1299 case IEEE80211_STA_RX_BW_40:
1300 bw_mode = RTW_CHANNEL_WIDTH_40;
1301 is_support_sgi = sta->deflink.ht_cap.ht_supported &&
1302 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
1303 break;
1304 default:
1305 bw_mode = RTW_CHANNEL_WIDTH_20;
1306 is_support_sgi = sta->deflink.ht_cap.ht_supported &&
1307 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
1308 break;
1309 }
1310
1311 if (sta->deflink.vht_cap.vht_supported ||
1312 sta->deflink.ht_cap.ht_supported)
1313 tx_num = efuse->hw_cap.nss;
1314
1315 rate_id = get_rate_id(wireless_set, bw_mode, tx_num);
1316
1317 ra_mask &= rtw_rate_mask_rssi(si, wireless_set);
1318 ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak);
1319 ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable);
1320
1321 si->bw_mode = bw_mode;
1322 si->stbc_en = stbc_en;
1323 si->ldpc_en = ldpc_en;
1324 si->sgi_enable = is_support_sgi;
1325 si->vht_enable = is_vht_enable;
1326 si->ra_mask = ra_mask;
1327 si->rate_id = rate_id;
1328
1329 rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask);
1330 }
1331
rtw_wait_firmware_completion(struct rtw_dev * rtwdev)1332 int rtw_wait_firmware_completion(struct rtw_dev *rtwdev)
1333 {
1334 const struct rtw_chip_info *chip = rtwdev->chip;
1335 struct rtw_fw_state *fw;
1336 int ret = 0;
1337
1338 fw = &rtwdev->fw;
1339 wait_for_completion(&fw->completion);
1340 if (!fw->firmware)
1341 ret = -EINVAL;
1342
1343 if (chip->wow_fw_name) {
1344 fw = &rtwdev->wow_fw;
1345 wait_for_completion(&fw->completion);
1346 if (!fw->firmware)
1347 ret = -EINVAL;
1348 }
1349
1350 return ret;
1351 }
1352 EXPORT_SYMBOL(rtw_wait_firmware_completion);
1353
rtw_update_lps_deep_mode(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1354 static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev,
1355 struct rtw_fw_state *fw)
1356 {
1357 const struct rtw_chip_info *chip = rtwdev->chip;
1358
1359 if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported ||
1360 !fw->feature)
1361 return LPS_DEEP_MODE_NONE;
1362
1363 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) &&
1364 rtw_fw_feature_check(fw, FW_FEATURE_PG))
1365 return LPS_DEEP_MODE_PG;
1366
1367 if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) &&
1368 rtw_fw_feature_check(fw, FW_FEATURE_LCLK))
1369 return LPS_DEEP_MODE_LCLK;
1370
1371 return LPS_DEEP_MODE_NONE;
1372 }
1373
rtw_power_on(struct rtw_dev * rtwdev)1374 int rtw_power_on(struct rtw_dev *rtwdev)
1375 {
1376 const struct rtw_chip_info *chip = rtwdev->chip;
1377 struct rtw_fw_state *fw = &rtwdev->fw;
1378 bool wifi_only;
1379 int ret;
1380
1381 ret = rtw_hci_setup(rtwdev);
1382 if (ret) {
1383 rtw_err(rtwdev, "failed to setup hci\n");
1384 goto err;
1385 }
1386
1387 /* power on MAC before firmware downloaded */
1388 ret = rtw_mac_power_on(rtwdev);
1389 if (ret) {
1390 rtw_err(rtwdev, "failed to power on mac\n");
1391 goto err;
1392 }
1393
1394 ret = rtw_wait_firmware_completion(rtwdev);
1395 if (ret) {
1396 rtw_err(rtwdev, "failed to wait firmware completion\n");
1397 goto err_off;
1398 }
1399
1400 ret = rtw_download_firmware(rtwdev, fw);
1401 if (ret) {
1402 rtw_err(rtwdev, "failed to download firmware\n");
1403 goto err_off;
1404 }
1405
1406 /* config mac after firmware downloaded */
1407 ret = rtw_mac_init(rtwdev);
1408 if (ret) {
1409 rtw_err(rtwdev, "failed to configure mac\n");
1410 goto err_off;
1411 }
1412
1413 chip->ops->phy_set_param(rtwdev);
1414
1415 ret = rtw_mac_postinit(rtwdev);
1416 if (ret) {
1417 rtw_err(rtwdev, "failed to configure mac in postinit\n");
1418 goto err_off;
1419 }
1420
1421 ret = rtw_hci_start(rtwdev);
1422 if (ret) {
1423 rtw_err(rtwdev, "failed to start hci\n");
1424 goto err_off;
1425 }
1426
1427 /* send H2C after HCI has started */
1428 rtw_fw_send_general_info(rtwdev);
1429 rtw_fw_send_phydm_info(rtwdev);
1430
1431 wifi_only = !rtwdev->efuse.btcoex;
1432 rtw_coex_power_on_setting(rtwdev);
1433 rtw_coex_init_hw_config(rtwdev, wifi_only);
1434
1435 return 0;
1436
1437 err_off:
1438 rtw_mac_power_off(rtwdev);
1439
1440 err:
1441 return ret;
1442 }
1443 EXPORT_SYMBOL(rtw_power_on);
1444
rtw_core_fw_scan_notify(struct rtw_dev * rtwdev,bool start)1445 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start)
1446 {
1447 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN))
1448 return;
1449
1450 if (start) {
1451 rtw_fw_scan_notify(rtwdev, true);
1452 } else {
1453 reinit_completion(&rtwdev->fw_scan_density);
1454 rtw_fw_scan_notify(rtwdev, false);
1455 if (!wait_for_completion_timeout(&rtwdev->fw_scan_density,
1456 SCAN_NOTIFY_TIMEOUT))
1457 rtw_warn(rtwdev, "firmware failed to report density after scan\n");
1458 }
1459 }
1460
rtw_core_scan_start(struct rtw_dev * rtwdev,struct rtw_vif * rtwvif,const u8 * mac_addr,bool hw_scan)1461 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
1462 const u8 *mac_addr, bool hw_scan)
1463 {
1464 u32 config = 0;
1465 int ret = 0;
1466
1467 rtw_leave_lps(rtwdev);
1468
1469 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) {
1470 ret = rtw_leave_ips(rtwdev);
1471 if (ret) {
1472 rtw_err(rtwdev, "failed to leave idle state\n");
1473 return;
1474 }
1475 }
1476
1477 ether_addr_copy(rtwvif->mac_addr, mac_addr);
1478 config |= PORT_SET_MAC_ADDR;
1479 rtw_vif_port_config(rtwdev, rtwvif, config);
1480
1481 rtw_coex_scan_notify(rtwdev, COEX_SCAN_START);
1482 rtw_core_fw_scan_notify(rtwdev, true);
1483
1484 set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1485 set_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1486 }
1487
rtw_core_scan_complete(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,bool hw_scan)1488 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
1489 bool hw_scan)
1490 {
1491 struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL;
1492 u32 config = 0;
1493
1494 if (!rtwvif)
1495 return;
1496
1497 clear_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1498 clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1499
1500 rtw_core_fw_scan_notify(rtwdev, false);
1501
1502 ether_addr_copy(rtwvif->mac_addr, vif->addr);
1503 config |= PORT_SET_MAC_ADDR;
1504 rtw_vif_port_config(rtwdev, rtwvif, config);
1505
1506 rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH);
1507
1508 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
1509 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
1510 }
1511
rtw_core_start(struct rtw_dev * rtwdev)1512 int rtw_core_start(struct rtw_dev *rtwdev)
1513 {
1514 int ret;
1515
1516 ret = rtwdev->chip->ops->power_on(rtwdev);
1517 if (ret)
1518 return ret;
1519
1520 rtw_sec_enable_sec_engine(rtwdev);
1521
1522 rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw);
1523 rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw);
1524
1525 /* rcr reset after powered on */
1526 rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr);
1527
1528 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
1529 RTW_WATCH_DOG_DELAY_TIME);
1530
1531 set_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1532
1533 return 0;
1534 }
1535
rtw_power_off(struct rtw_dev * rtwdev)1536 void rtw_power_off(struct rtw_dev *rtwdev)
1537 {
1538 rtw_hci_stop(rtwdev);
1539 rtw_coex_power_off_setting(rtwdev);
1540 rtw_mac_power_off(rtwdev);
1541 }
1542 EXPORT_SYMBOL(rtw_power_off);
1543
rtw_core_stop(struct rtw_dev * rtwdev)1544 void rtw_core_stop(struct rtw_dev *rtwdev)
1545 {
1546 struct rtw_coex *coex = &rtwdev->coex;
1547
1548 clear_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1549 clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
1550
1551 mutex_unlock(&rtwdev->mutex);
1552
1553 cancel_work_sync(&rtwdev->c2h_work);
1554 cancel_work_sync(&rtwdev->update_beacon_work);
1555 cancel_delayed_work_sync(&rtwdev->watch_dog_work);
1556 cancel_delayed_work_sync(&coex->bt_relink_work);
1557 cancel_delayed_work_sync(&coex->bt_reenable_work);
1558 cancel_delayed_work_sync(&coex->defreeze_work);
1559 cancel_delayed_work_sync(&coex->wl_remain_work);
1560 cancel_delayed_work_sync(&coex->bt_remain_work);
1561 cancel_delayed_work_sync(&coex->wl_connecting_work);
1562 cancel_delayed_work_sync(&coex->bt_multi_link_remain_work);
1563 cancel_delayed_work_sync(&coex->wl_ccklock_work);
1564
1565 mutex_lock(&rtwdev->mutex);
1566
1567 rtwdev->chip->ops->power_off(rtwdev);
1568 }
1569
rtw_init_ht_cap(struct rtw_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)1570 static void rtw_init_ht_cap(struct rtw_dev *rtwdev,
1571 struct ieee80211_sta_ht_cap *ht_cap)
1572 {
1573 const struct rtw_chip_info *chip = rtwdev->chip;
1574 struct rtw_efuse *efuse = &rtwdev->efuse;
1575 int i;
1576
1577 ht_cap->ht_supported = true;
1578 ht_cap->cap = 0;
1579 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
1580 IEEE80211_HT_CAP_MAX_AMSDU |
1581 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
1582
1583 if (rtw_chip_has_rx_ldpc(rtwdev))
1584 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
1585 if (rtw_chip_has_tx_stbc(rtwdev))
1586 ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC;
1587
1588 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40))
1589 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1590 IEEE80211_HT_CAP_DSSSCCK40 |
1591 IEEE80211_HT_CAP_SGI_40;
1592 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1593 ht_cap->ampdu_density = chip->ampdu_density;
1594 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1595
1596 for (i = 0; i < efuse->hw_cap.nss; i++)
1597 ht_cap->mcs.rx_mask[i] = 0xFF;
1598 ht_cap->mcs.rx_mask[4] = 0x01;
1599 ht_cap->mcs.rx_highest = cpu_to_le16(150 * efuse->hw_cap.nss);
1600 }
1601
rtw_init_vht_cap(struct rtw_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)1602 static void rtw_init_vht_cap(struct rtw_dev *rtwdev,
1603 struct ieee80211_sta_vht_cap *vht_cap)
1604 {
1605 struct rtw_efuse *efuse = &rtwdev->efuse;
1606 u16 mcs_map = 0;
1607 __le16 highest;
1608 int i;
1609
1610 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE &&
1611 efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT)
1612 return;
1613
1614 vht_cap->vht_supported = true;
1615 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
1616 IEEE80211_VHT_CAP_SHORT_GI_80 |
1617 IEEE80211_VHT_CAP_RXSTBC_1 |
1618 IEEE80211_VHT_CAP_HTC_VHT |
1619 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
1620 0;
1621 if (rtwdev->hal.rf_path_num > 1)
1622 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
1623 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
1624 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
1625 vht_cap->cap |= (rtwdev->hal.bfee_sts_cap <<
1626 IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
1627
1628 if (rtw_chip_has_rx_ldpc(rtwdev))
1629 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
1630
1631 for (i = 0; i < 8; i++) {
1632 if (i < efuse->hw_cap.nss)
1633 mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
1634 else
1635 mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
1636 }
1637
1638 highest = cpu_to_le16(390 * efuse->hw_cap.nss);
1639
1640 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
1641 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
1642 vht_cap->vht_mcs.rx_highest = highest;
1643 vht_cap->vht_mcs.tx_highest = highest;
1644 }
1645
rtw_get_max_scan_ie_len(struct rtw_dev * rtwdev)1646 static u16 rtw_get_max_scan_ie_len(struct rtw_dev *rtwdev)
1647 {
1648 u16 len;
1649
1650 len = rtwdev->chip->max_scan_ie_len;
1651
1652 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) &&
1653 rtwdev->chip->id == RTW_CHIP_TYPE_8822C)
1654 len = IEEE80211_MAX_DATA_LEN;
1655 else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM))
1656 len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE;
1657
1658 return len;
1659 }
1660
rtw_set_supported_band(struct ieee80211_hw * hw,const struct rtw_chip_info * chip)1661 static void rtw_set_supported_band(struct ieee80211_hw *hw,
1662 const struct rtw_chip_info *chip)
1663 {
1664 struct rtw_dev *rtwdev = hw->priv;
1665 struct ieee80211_supported_band *sband;
1666
1667 if (chip->band & RTW_BAND_2G) {
1668 sband = kmemdup(&rtw_band_2ghz, sizeof(*sband), GFP_KERNEL);
1669 if (!sband)
1670 goto err_out;
1671 if (chip->ht_supported)
1672 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1673 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
1674 }
1675
1676 if (chip->band & RTW_BAND_5G) {
1677 sband = kmemdup(&rtw_band_5ghz, sizeof(*sband), GFP_KERNEL);
1678 if (!sband)
1679 goto err_out;
1680 if (chip->ht_supported)
1681 rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1682 if (chip->vht_supported)
1683 rtw_init_vht_cap(rtwdev, &sband->vht_cap);
1684 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
1685 }
1686
1687 return;
1688
1689 err_out:
1690 rtw_err(rtwdev, "failed to set supported band\n");
1691 }
1692
rtw_unset_supported_band(struct ieee80211_hw * hw,const struct rtw_chip_info * chip)1693 static void rtw_unset_supported_band(struct ieee80211_hw *hw,
1694 const struct rtw_chip_info *chip)
1695 {
1696 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
1697 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
1698 }
1699
rtw_vif_smps_iter(void * data,u8 * mac,struct ieee80211_vif * vif)1700 static void rtw_vif_smps_iter(void *data, u8 *mac,
1701 struct ieee80211_vif *vif)
1702 {
1703 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
1704
1705 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
1706 return;
1707
1708 if (rtwdev->hal.txrx_1ss)
1709 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC);
1710 else
1711 ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF);
1712 }
1713
rtw_set_txrx_1ss(struct rtw_dev * rtwdev,bool txrx_1ss)1714 void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss)
1715 {
1716 const struct rtw_chip_info *chip = rtwdev->chip;
1717 struct rtw_hal *hal = &rtwdev->hal;
1718
1719 if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss)
1720 return;
1721
1722 rtwdev->hal.txrx_1ss = txrx_1ss;
1723 if (txrx_1ss)
1724 chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false);
1725 else
1726 chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx,
1727 hal->antenna_rx, false);
1728 rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev);
1729 }
1730
__update_firmware_feature(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1731 static void __update_firmware_feature(struct rtw_dev *rtwdev,
1732 struct rtw_fw_state *fw)
1733 {
1734 u32 feature;
1735 const struct rtw_fw_hdr *fw_hdr =
1736 (const struct rtw_fw_hdr *)fw->firmware->data;
1737
1738 feature = le32_to_cpu(fw_hdr->feature);
1739 fw->feature = feature & FW_FEATURE_SIG ? feature : 0;
1740
1741 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C &&
1742 RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13))
1743 fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM;
1744 }
1745
__update_firmware_info(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1746 static void __update_firmware_info(struct rtw_dev *rtwdev,
1747 struct rtw_fw_state *fw)
1748 {
1749 const struct rtw_fw_hdr *fw_hdr =
1750 (const struct rtw_fw_hdr *)fw->firmware->data;
1751
1752 fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver);
1753 fw->version = le16_to_cpu(fw_hdr->version);
1754 fw->sub_version = fw_hdr->subversion;
1755 fw->sub_index = fw_hdr->subindex;
1756
1757 __update_firmware_feature(rtwdev, fw);
1758 }
1759
__update_firmware_info_legacy(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1760 static void __update_firmware_info_legacy(struct rtw_dev *rtwdev,
1761 struct rtw_fw_state *fw)
1762 {
1763 struct rtw_fw_hdr_legacy *legacy =
1764 (struct rtw_fw_hdr_legacy *)fw->firmware->data;
1765
1766 fw->h2c_version = 0;
1767 fw->version = le16_to_cpu(legacy->version);
1768 fw->sub_version = legacy->subversion1;
1769 fw->sub_index = legacy->subversion2;
1770 }
1771
update_firmware_info(struct rtw_dev * rtwdev,struct rtw_fw_state * fw)1772 static void update_firmware_info(struct rtw_dev *rtwdev,
1773 struct rtw_fw_state *fw)
1774 {
1775 if (rtw_chip_wcpu_8051(rtwdev))
1776 __update_firmware_info_legacy(rtwdev, fw);
1777 else
1778 __update_firmware_info(rtwdev, fw);
1779 }
1780
rtw_load_firmware_cb(const struct firmware * firmware,void * context)1781 static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
1782 {
1783 struct rtw_fw_state *fw = context;
1784 struct rtw_dev *rtwdev = fw->rtwdev;
1785
1786 if (!firmware || !firmware->data) {
1787 rtw_err(rtwdev, "failed to request firmware\n");
1788 complete_all(&fw->completion);
1789 return;
1790 }
1791
1792 fw->firmware = firmware;
1793 update_firmware_info(rtwdev, fw);
1794 complete_all(&fw->completion);
1795
1796 rtw_info(rtwdev, "%sFirmware version %u.%u.%u, H2C version %u\n",
1797 fw->type == RTW_WOWLAN_FW ? "WOW " : "",
1798 fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
1799 }
1800
rtw_load_firmware(struct rtw_dev * rtwdev,enum rtw_fw_type type)1801 static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)
1802 {
1803 const char *fw_name;
1804 struct rtw_fw_state *fw;
1805 int ret;
1806
1807 switch (type) {
1808 case RTW_WOWLAN_FW:
1809 fw = &rtwdev->wow_fw;
1810 fw_name = rtwdev->chip->wow_fw_name;
1811 break;
1812
1813 case RTW_NORMAL_FW:
1814 fw = &rtwdev->fw;
1815 fw_name = rtwdev->chip->fw_name;
1816 break;
1817
1818 default:
1819 rtw_warn(rtwdev, "unsupported firmware type\n");
1820 return -ENOENT;
1821 }
1822
1823 fw->type = type;
1824 fw->rtwdev = rtwdev;
1825 init_completion(&fw->completion);
1826
1827 ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
1828 GFP_KERNEL, fw, rtw_load_firmware_cb);
1829 if (ret) {
1830 rtw_err(rtwdev, "failed to async firmware request\n");
1831 return ret;
1832 }
1833
1834 return 0;
1835 }
1836
rtw_chip_parameter_setup(struct rtw_dev * rtwdev)1837 static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
1838 {
1839 const struct rtw_chip_info *chip = rtwdev->chip;
1840 struct rtw_hal *hal = &rtwdev->hal;
1841 struct rtw_efuse *efuse = &rtwdev->efuse;
1842
1843 switch (rtw_hci_type(rtwdev)) {
1844 case RTW_HCI_TYPE_PCIE:
1845 rtwdev->hci.rpwm_addr = 0x03d9;
1846 rtwdev->hci.cpwm_addr = 0x03da;
1847 break;
1848 case RTW_HCI_TYPE_SDIO:
1849 rtwdev->hci.rpwm_addr = REG_SDIO_HRPWM1;
1850 rtwdev->hci.cpwm_addr = REG_SDIO_HCPWM1_V2;
1851 break;
1852 case RTW_HCI_TYPE_USB:
1853 rtwdev->hci.rpwm_addr = 0xfe58;
1854 rtwdev->hci.cpwm_addr = 0xfe57;
1855 break;
1856 default:
1857 rtw_err(rtwdev, "unsupported hci type\n");
1858 return -EINVAL;
1859 }
1860
1861 hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
1862 hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
1863 hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;
1864 if (hal->chip_version & BIT_RF_TYPE_ID) {
1865 hal->rf_type = RF_2T2R;
1866 hal->rf_path_num = 2;
1867 hal->antenna_tx = BB_PATH_AB;
1868 hal->antenna_rx = BB_PATH_AB;
1869 } else {
1870 hal->rf_type = RF_1T1R;
1871 hal->rf_path_num = 1;
1872 hal->antenna_tx = BB_PATH_A;
1873 hal->antenna_rx = BB_PATH_A;
1874 }
1875 hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num :
1876 hal->rf_path_num;
1877
1878 efuse->physical_size = chip->phy_efuse_size;
1879 efuse->logical_size = chip->log_efuse_size;
1880 efuse->protect_size = chip->ptct_efuse_size;
1881
1882 /* default use ack */
1883 rtwdev->hal.rcr |= BIT_VHT_DACK;
1884
1885 hal->bfee_sts_cap = 3;
1886
1887 return 0;
1888 }
1889
rtw_chip_efuse_enable(struct rtw_dev * rtwdev)1890 static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev)
1891 {
1892 struct rtw_fw_state *fw = &rtwdev->fw;
1893 int ret;
1894
1895 ret = rtw_hci_setup(rtwdev);
1896 if (ret) {
1897 rtw_err(rtwdev, "failed to setup hci\n");
1898 goto err;
1899 }
1900
1901 ret = rtw_mac_power_on(rtwdev);
1902 if (ret) {
1903 rtw_err(rtwdev, "failed to power on mac\n");
1904 goto err;
1905 }
1906
1907 rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP);
1908
1909 wait_for_completion(&fw->completion);
1910 if (!fw->firmware) {
1911 ret = -EINVAL;
1912 rtw_err(rtwdev, "failed to load firmware\n");
1913 goto err;
1914 }
1915
1916 ret = rtw_download_firmware(rtwdev, fw);
1917 if (ret) {
1918 rtw_err(rtwdev, "failed to download firmware\n");
1919 goto err_off;
1920 }
1921
1922 return 0;
1923
1924 err_off:
1925 rtw_mac_power_off(rtwdev);
1926
1927 err:
1928 return ret;
1929 }
1930
rtw_dump_hw_feature(struct rtw_dev * rtwdev)1931 static int rtw_dump_hw_feature(struct rtw_dev *rtwdev)
1932 {
1933 struct rtw_efuse *efuse = &rtwdev->efuse;
1934 u8 hw_feature[HW_FEATURE_LEN];
1935 u8 id;
1936 u8 bw;
1937 int i;
1938
1939 if (!rtwdev->chip->hw_feature_report)
1940 return 0;
1941
1942 id = rtw_read8(rtwdev, REG_C2HEVT);
1943 if (id != C2H_HW_FEATURE_REPORT) {
1944 rtw_err(rtwdev, "failed to read hw feature report\n");
1945 return -EBUSY;
1946 }
1947
1948 for (i = 0; i < HW_FEATURE_LEN; i++)
1949 hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i);
1950
1951 rtw_write8(rtwdev, REG_C2HEVT, 0);
1952
1953 bw = GET_EFUSE_HW_CAP_BW(hw_feature);
1954 efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw);
1955 efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature);
1956 efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature);
1957 efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature);
1958 efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature);
1959
1960 rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num);
1961
1962 if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE ||
1963 efuse->hw_cap.nss > rtwdev->hal.rf_path_num)
1964 efuse->hw_cap.nss = rtwdev->hal.rf_path_num;
1965
1966 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
1967 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
1968 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
1969 efuse->hw_cap.ant_num, efuse->hw_cap.nss);
1970
1971 return 0;
1972 }
1973
rtw_chip_efuse_disable(struct rtw_dev * rtwdev)1974 static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev)
1975 {
1976 rtw_hci_stop(rtwdev);
1977 rtw_mac_power_off(rtwdev);
1978 }
1979
rtw_chip_efuse_info_setup(struct rtw_dev * rtwdev)1980 static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
1981 {
1982 struct rtw_efuse *efuse = &rtwdev->efuse;
1983 int ret;
1984
1985 mutex_lock(&rtwdev->mutex);
1986
1987 /* power on mac to read efuse */
1988 ret = rtw_chip_efuse_enable(rtwdev);
1989 if (ret)
1990 goto out_unlock;
1991
1992 ret = rtw_parse_efuse_map(rtwdev);
1993 if (ret)
1994 goto out_disable;
1995
1996 ret = rtw_dump_hw_feature(rtwdev);
1997 if (ret)
1998 goto out_disable;
1999
2000 ret = rtw_check_supported_rfe(rtwdev);
2001 if (ret)
2002 goto out_disable;
2003
2004 if (efuse->crystal_cap == 0xff)
2005 efuse->crystal_cap = 0;
2006 if (efuse->pa_type_2g == 0xff)
2007 efuse->pa_type_2g = 0;
2008 if (efuse->pa_type_5g == 0xff)
2009 efuse->pa_type_5g = 0;
2010 if (efuse->lna_type_2g == 0xff)
2011 efuse->lna_type_2g = 0;
2012 if (efuse->lna_type_5g == 0xff)
2013 efuse->lna_type_5g = 0;
2014 if (efuse->channel_plan == 0xff)
2015 efuse->channel_plan = 0x7f;
2016 if (efuse->rf_board_option == 0xff)
2017 efuse->rf_board_option = 0;
2018 if (efuse->bt_setting & BIT(0))
2019 efuse->share_ant = true;
2020 if (efuse->regd == 0xff)
2021 efuse->regd = 0;
2022 if (efuse->tx_bb_swing_setting_2g == 0xff)
2023 efuse->tx_bb_swing_setting_2g = 0;
2024 if (efuse->tx_bb_swing_setting_5g == 0xff)
2025 efuse->tx_bb_swing_setting_5g = 0;
2026
2027 efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
2028 efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
2029 efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
2030 efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
2031 efuse->ext_lna_5g = efuse->lna_type_5g & BIT(3) ? 1 : 0;
2032
2033 if (!is_valid_ether_addr(efuse->addr)) {
2034 eth_random_addr(efuse->addr);
2035 dev_warn(rtwdev->dev, "efuse MAC invalid, using random\n");
2036 }
2037
2038 out_disable:
2039 rtw_chip_efuse_disable(rtwdev);
2040
2041 out_unlock:
2042 mutex_unlock(&rtwdev->mutex);
2043 return ret;
2044 }
2045
rtw_chip_board_info_setup(struct rtw_dev * rtwdev)2046 static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev)
2047 {
2048 struct rtw_hal *hal = &rtwdev->hal;
2049 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
2050
2051 if (!rfe_def)
2052 return -ENODEV;
2053
2054 rtw_phy_setup_phy_cond(rtwdev, hal->pkg_type);
2055
2056 rtw_phy_init_tx_power(rtwdev);
2057 rtw_load_table(rtwdev, rfe_def->phy_pg_tbl);
2058 rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl);
2059 rtw_phy_tx_power_by_rate_config(hal);
2060 rtw_phy_tx_power_limit_config(hal);
2061
2062 return 0;
2063 }
2064
rtw_chip_info_setup(struct rtw_dev * rtwdev)2065 int rtw_chip_info_setup(struct rtw_dev *rtwdev)
2066 {
2067 int ret;
2068
2069 ret = rtw_chip_parameter_setup(rtwdev);
2070 if (ret) {
2071 rtw_err(rtwdev, "failed to setup chip parameters\n");
2072 goto err_out;
2073 }
2074
2075 ret = rtw_chip_efuse_info_setup(rtwdev);
2076 if (ret) {
2077 rtw_err(rtwdev, "failed to setup chip efuse info\n");
2078 goto err_out;
2079 }
2080
2081 ret = rtw_chip_board_info_setup(rtwdev);
2082 if (ret) {
2083 rtw_err(rtwdev, "failed to setup chip board info\n");
2084 goto err_out;
2085 }
2086
2087 return 0;
2088
2089 err_out:
2090 return ret;
2091 }
2092 EXPORT_SYMBOL(rtw_chip_info_setup);
2093
rtw_stats_init(struct rtw_dev * rtwdev)2094 static void rtw_stats_init(struct rtw_dev *rtwdev)
2095 {
2096 struct rtw_traffic_stats *stats = &rtwdev->stats;
2097 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2098 int i;
2099
2100 ewma_tp_init(&stats->tx_ewma_tp);
2101 ewma_tp_init(&stats->rx_ewma_tp);
2102
2103 for (i = 0; i < RTW_EVM_NUM; i++)
2104 ewma_evm_init(&dm_info->ewma_evm[i]);
2105 for (i = 0; i < RTW_SNR_NUM; i++)
2106 ewma_snr_init(&dm_info->ewma_snr[i]);
2107 }
2108
rtw_core_init(struct rtw_dev * rtwdev)2109 int rtw_core_init(struct rtw_dev *rtwdev)
2110 {
2111 const struct rtw_chip_info *chip = rtwdev->chip;
2112 struct rtw_coex *coex = &rtwdev->coex;
2113 int ret;
2114
2115 INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
2116 INIT_LIST_HEAD(&rtwdev->txqs);
2117
2118 timer_setup(&rtwdev->tx_report.purge_timer,
2119 rtw_tx_report_purge_timer, 0);
2120 rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
2121 if (!rtwdev->tx_wq) {
2122 rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n");
2123 return -ENOMEM;
2124 }
2125
2126 INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
2127 INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
2128 INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
2129 INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
2130 INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work);
2131 INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work);
2132 INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work);
2133 INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work,
2134 rtw_coex_bt_multi_link_remain_work);
2135 INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work);
2136 INIT_WORK(&rtwdev->tx_work, rtw_tx_work);
2137 INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
2138 INIT_WORK(&rtwdev->ips_work, rtw_ips_work);
2139 INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work);
2140 INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work);
2141 INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work);
2142 skb_queue_head_init(&rtwdev->c2h_queue);
2143 skb_queue_head_init(&rtwdev->coex.queue);
2144 skb_queue_head_init(&rtwdev->tx_report.queue);
2145
2146 spin_lock_init(&rtwdev->txq_lock);
2147 spin_lock_init(&rtwdev->tx_report.q_lock);
2148
2149 mutex_init(&rtwdev->mutex);
2150 mutex_init(&rtwdev->hal.tx_power_mutex);
2151
2152 init_waitqueue_head(&rtwdev->coex.wait);
2153 init_completion(&rtwdev->lps_leave_check);
2154 init_completion(&rtwdev->fw_scan_density);
2155
2156 rtwdev->sec.total_cam_num = 32;
2157 rtwdev->hal.current_channel = 1;
2158 rtwdev->dm_info.fix_rate = U8_MAX;
2159
2160 rtw_stats_init(rtwdev);
2161
2162 /* default rx filter setting */
2163 rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV |
2164 BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS |
2165 BIT_AB | BIT_AM | BIT_APM;
2166
2167 ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW);
2168 if (ret) {
2169 rtw_warn(rtwdev, "no firmware loaded\n");
2170 goto out;
2171 }
2172
2173 if (chip->wow_fw_name) {
2174 ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW);
2175 if (ret) {
2176 rtw_warn(rtwdev, "no wow firmware loaded\n");
2177 wait_for_completion(&rtwdev->fw.completion);
2178 if (rtwdev->fw.firmware)
2179 release_firmware(rtwdev->fw.firmware);
2180 goto out;
2181 }
2182 }
2183
2184 return 0;
2185
2186 out:
2187 destroy_workqueue(rtwdev->tx_wq);
2188 return ret;
2189 }
2190 EXPORT_SYMBOL(rtw_core_init);
2191
rtw_core_deinit(struct rtw_dev * rtwdev)2192 void rtw_core_deinit(struct rtw_dev *rtwdev)
2193 {
2194 struct rtw_fw_state *fw = &rtwdev->fw;
2195 struct rtw_fw_state *wow_fw = &rtwdev->wow_fw;
2196 struct rtw_rsvd_page *rsvd_pkt, *tmp;
2197 unsigned long flags;
2198
2199 rtw_wait_firmware_completion(rtwdev);
2200
2201 if (fw->firmware)
2202 release_firmware(fw->firmware);
2203
2204 if (wow_fw->firmware)
2205 release_firmware(wow_fw->firmware);
2206
2207 destroy_workqueue(rtwdev->tx_wq);
2208 timer_delete_sync(&rtwdev->tx_report.purge_timer);
2209 spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags);
2210 skb_queue_purge(&rtwdev->tx_report.queue);
2211 spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags);
2212 skb_queue_purge(&rtwdev->coex.queue);
2213 skb_queue_purge(&rtwdev->c2h_queue);
2214
2215 list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list,
2216 build_list) {
2217 list_del(&rsvd_pkt->build_list);
2218 kfree(rsvd_pkt);
2219 }
2220
2221 mutex_destroy(&rtwdev->mutex);
2222 mutex_destroy(&rtwdev->hal.tx_power_mutex);
2223 }
2224 EXPORT_SYMBOL(rtw_core_deinit);
2225
rtw_register_hw(struct rtw_dev * rtwdev,struct ieee80211_hw * hw)2226 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
2227 {
2228 struct rtw_hal *hal = &rtwdev->hal;
2229 int max_tx_headroom = 0;
2230 int ret;
2231
2232 max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
2233
2234 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO)
2235 max_tx_headroom += RTW_SDIO_DATA_PTR_ALIGN;
2236
2237 hw->extra_tx_headroom = max_tx_headroom;
2238 hw->queues = IEEE80211_NUM_ACS;
2239 hw->txq_data_size = sizeof(struct rtw_txq);
2240 hw->sta_data_size = sizeof(struct rtw_sta_info);
2241 hw->vif_data_size = sizeof(struct rtw_vif);
2242
2243 ieee80211_hw_set(hw, SIGNAL_DBM);
2244 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
2245 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
2246 ieee80211_hw_set(hw, MFP_CAPABLE);
2247 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
2248 ieee80211_hw_set(hw, SUPPORTS_PS);
2249 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
2250 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
2251 if (rtwdev->chip->amsdu_in_ampdu)
2252 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
2253 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
2254 ieee80211_hw_set(hw, TX_AMSDU);
2255 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
2256
2257 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
2258 BIT(NL80211_IFTYPE_AP) |
2259 BIT(NL80211_IFTYPE_ADHOC);
2260 hw->wiphy->available_antennas_tx = hal->antenna_tx;
2261 hw->wiphy->available_antennas_rx = hal->antenna_rx;
2262
2263 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
2264 WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
2265
2266 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
2267 hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS;
2268 hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev);
2269
2270 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C) {
2271 hw->wiphy->iface_combinations = rtw_iface_combs;
2272 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw_iface_combs);
2273 }
2274
2275 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
2276 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
2277 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
2278
2279 #ifdef CONFIG_PM
2280 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
2281 hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids;
2282 #endif
2283 rtw_set_supported_band(hw, rtwdev->chip);
2284 SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr);
2285
2286 hw->wiphy->sar_capa = &rtw_sar_capa;
2287
2288 ret = rtw_regd_init(rtwdev);
2289 if (ret) {
2290 rtw_err(rtwdev, "failed to init regd\n");
2291 return ret;
2292 }
2293
2294 rtw_led_init(rtwdev);
2295
2296 ret = ieee80211_register_hw(hw);
2297 if (ret) {
2298 rtw_err(rtwdev, "failed to register hw\n");
2299 goto led_deinit;
2300 }
2301
2302 ret = rtw_regd_hint(rtwdev);
2303 if (ret) {
2304 rtw_err(rtwdev, "failed to hint regd\n");
2305 goto led_deinit;
2306 }
2307
2308 rtw_debugfs_init(rtwdev);
2309
2310 rtwdev->bf_info.bfer_mu_cnt = 0;
2311 rtwdev->bf_info.bfer_su_cnt = 0;
2312
2313 return 0;
2314
2315 led_deinit:
2316 rtw_led_deinit(rtwdev);
2317 return ret;
2318 }
2319 EXPORT_SYMBOL(rtw_register_hw);
2320
rtw_unregister_hw(struct rtw_dev * rtwdev,struct ieee80211_hw * hw)2321 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
2322 {
2323 const struct rtw_chip_info *chip = rtwdev->chip;
2324
2325 ieee80211_unregister_hw(hw);
2326 rtw_unset_supported_band(hw, chip);
2327 rtw_debugfs_deinit(rtwdev);
2328 rtw_led_deinit(rtwdev);
2329 }
2330 EXPORT_SYMBOL(rtw_unregister_hw);
2331
2332 static
rtw_swap_reg_nbytes(struct rtw_dev * rtwdev,const struct rtw_hw_reg * reg1,const struct rtw_hw_reg * reg2,u8 nbytes)2333 void rtw_swap_reg_nbytes(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1,
2334 const struct rtw_hw_reg *reg2, u8 nbytes)
2335 {
2336 u8 i;
2337
2338 for (i = 0; i < nbytes; i++) {
2339 u8 v1 = rtw_read8(rtwdev, reg1->addr + i);
2340 u8 v2 = rtw_read8(rtwdev, reg2->addr + i);
2341
2342 rtw_write8(rtwdev, reg1->addr + i, v2);
2343 rtw_write8(rtwdev, reg2->addr + i, v1);
2344 }
2345 }
2346
2347 static
rtw_swap_reg_mask(struct rtw_dev * rtwdev,const struct rtw_hw_reg * reg1,const struct rtw_hw_reg * reg2)2348 void rtw_swap_reg_mask(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1,
2349 const struct rtw_hw_reg *reg2)
2350 {
2351 u32 v1, v2;
2352
2353 v1 = rtw_read32_mask(rtwdev, reg1->addr, reg1->mask);
2354 v2 = rtw_read32_mask(rtwdev, reg2->addr, reg2->mask);
2355 rtw_write32_mask(rtwdev, reg2->addr, reg2->mask, v1);
2356 rtw_write32_mask(rtwdev, reg1->addr, reg1->mask, v2);
2357 }
2358
2359 struct rtw_iter_port_switch_data {
2360 struct rtw_dev *rtwdev;
2361 struct rtw_vif *rtwvif_ap;
2362 };
2363
rtw_port_switch_iter(void * data,struct ieee80211_vif * vif)2364 static void rtw_port_switch_iter(void *data, struct ieee80211_vif *vif)
2365 {
2366 struct rtw_iter_port_switch_data *iter_data = data;
2367 struct rtw_dev *rtwdev = iter_data->rtwdev;
2368 struct rtw_vif *rtwvif_target = (struct rtw_vif *)vif->drv_priv;
2369 struct rtw_vif *rtwvif_ap = iter_data->rtwvif_ap;
2370 const struct rtw_hw_reg *reg1, *reg2;
2371
2372 if (rtwvif_target->port != RTW_PORT_0)
2373 return;
2374
2375 rtw_dbg(rtwdev, RTW_DBG_STATE, "AP port switch from %d -> %d\n",
2376 rtwvif_ap->port, rtwvif_target->port);
2377
2378 /* Leave LPS so the value swapped are not in PS mode */
2379 rtw_leave_lps(rtwdev);
2380
2381 reg1 = &rtwvif_ap->conf->net_type;
2382 reg2 = &rtwvif_target->conf->net_type;
2383 rtw_swap_reg_mask(rtwdev, reg1, reg2);
2384
2385 reg1 = &rtwvif_ap->conf->mac_addr;
2386 reg2 = &rtwvif_target->conf->mac_addr;
2387 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN);
2388
2389 reg1 = &rtwvif_ap->conf->bssid;
2390 reg2 = &rtwvif_target->conf->bssid;
2391 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN);
2392
2393 reg1 = &rtwvif_ap->conf->bcn_ctrl;
2394 reg2 = &rtwvif_target->conf->bcn_ctrl;
2395 rtw_swap_reg_nbytes(rtwdev, reg1, reg2, 1);
2396
2397 swap(rtwvif_target->port, rtwvif_ap->port);
2398 swap(rtwvif_target->conf, rtwvif_ap->conf);
2399
2400 rtw_fw_default_port(rtwdev, rtwvif_target);
2401 }
2402
rtw_core_port_switch(struct rtw_dev * rtwdev,struct ieee80211_vif * vif)2403 void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif)
2404 {
2405 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
2406 struct rtw_iter_port_switch_data iter_data;
2407
2408 if (vif->type != NL80211_IFTYPE_AP || rtwvif->port == RTW_PORT_0)
2409 return;
2410
2411 iter_data.rtwdev = rtwdev;
2412 iter_data.rtwvif_ap = rtwvif;
2413 rtw_iterate_vifs(rtwdev, rtw_port_switch_iter, &iter_data);
2414 }
2415
rtw_check_sta_active_iter(void * data,struct ieee80211_vif * vif)2416 static void rtw_check_sta_active_iter(void *data, struct ieee80211_vif *vif)
2417 {
2418 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
2419 bool *active = data;
2420
2421 if (*active)
2422 return;
2423
2424 if (vif->type != NL80211_IFTYPE_STATION)
2425 return;
2426
2427 if (vif->cfg.assoc || !is_zero_ether_addr(rtwvif->bssid))
2428 *active = true;
2429 }
2430
rtw_core_check_sta_active(struct rtw_dev * rtwdev)2431 bool rtw_core_check_sta_active(struct rtw_dev *rtwdev)
2432 {
2433 bool sta_active = false;
2434
2435 rtw_iterate_vifs(rtwdev, rtw_check_sta_active_iter, &sta_active);
2436
2437 return rtwdev->ap_active || sta_active;
2438 }
2439
rtw_core_enable_beacon(struct rtw_dev * rtwdev,bool enable)2440 void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable)
2441 {
2442 if (!rtwdev->ap_active)
2443 return;
2444
2445 if (enable) {
2446 rtw_write32_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2447 rtw_write32_clr(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
2448 } else {
2449 rtw_write32_clr(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2450 rtw_write32_set(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
2451 }
2452 }
2453
rtw_set_ampdu_factor(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf)2454 void rtw_set_ampdu_factor(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
2455 struct ieee80211_bss_conf *bss_conf)
2456 {
2457 const struct rtw_chip_ops *ops = rtwdev->chip->ops;
2458 struct ieee80211_sta *sta;
2459 u8 factor = 0xff;
2460
2461 if (!ops->set_ampdu_factor)
2462 return;
2463
2464 rcu_read_lock();
2465
2466 sta = ieee80211_find_sta(vif, bss_conf->bssid);
2467 if (!sta) {
2468 rcu_read_unlock();
2469 rtw_warn(rtwdev, "%s: failed to find station %pM\n",
2470 __func__, bss_conf->bssid);
2471 return;
2472 }
2473
2474 if (sta->deflink.vht_cap.vht_supported)
2475 factor = u32_get_bits(sta->deflink.vht_cap.cap,
2476 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK);
2477 else if (sta->deflink.ht_cap.ht_supported)
2478 factor = sta->deflink.ht_cap.ampdu_factor;
2479
2480 rcu_read_unlock();
2481
2482 if (factor != 0xff)
2483 ops->set_ampdu_factor(rtwdev, factor);
2484 }
2485
2486 MODULE_AUTHOR("Realtek Corporation");
2487 MODULE_DESCRIPTION("Realtek 802.11ac wireless core module");
2488 MODULE_LICENSE("Dual BSD/GPL");
2489