1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 * This file implements dp specific link capability retrieval sequence. It is
28 * responsible for retrieving, parsing, overriding, deciding capability obtained
29 * from dp link. Link capability consists of encoders, DPRXs, cables, retimers,
30 * usb and all other possible backend capabilities. Other components should
31 * include this header file in order to access link capability. Accessing link
32 * capability by dereferencing dc_link outside dp_link_capability is not a
33 * recommended method as it makes the component dependent on the underlying data
34 * structure used to represent link capability instead of function interfaces.
35 */
36
37 #include "link_dp_capability.h"
38 #include "link_ddc.h"
39 #include "link_dpcd.h"
40 #include "link_dp_dpia.h"
41 #include "link_dp_phy.h"
42 #include "link_edp_panel_control.h"
43 #include "link_dp_irq_handler.h"
44 #include "link/accessories/link_dp_trace.h"
45 #include "link/link_detection.h"
46 #include "link/link_validation.h"
47 #include "link_dp_training.h"
48 #include "atomfirmware.h"
49 #include "resource.h"
50 #include "link_enc_cfg.h"
51 #include "dc_dmub_srv.h"
52 #include "gpio_service_interface.h"
53
54 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
55
56 #define DC_LOGGER \
57 link->ctx->logger
58
59 #ifndef MAX
60 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
61 #endif
62 #ifndef MIN
63 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
64 #endif
65
66 struct dp_lt_fallback_entry {
67 enum dc_lane_count lane_count;
68 enum dc_link_rate link_rate;
69 };
70
71 static const struct dp_lt_fallback_entry dp_lt_fallbacks[] = {
72 /* This link training fallback array is ordered by
73 * link bandwidth from highest to lowest.
74 * DP specs makes it a normative policy to always
75 * choose the next highest link bandwidth during
76 * link training fallback.
77 */
78 {LANE_COUNT_FOUR, LINK_RATE_UHBR20},
79 {LANE_COUNT_FOUR, LINK_RATE_UHBR13_5},
80 {LANE_COUNT_TWO, LINK_RATE_UHBR20},
81 {LANE_COUNT_FOUR, LINK_RATE_UHBR10},
82 {LANE_COUNT_TWO, LINK_RATE_UHBR13_5},
83 {LANE_COUNT_FOUR, LINK_RATE_HIGH3},
84 {LANE_COUNT_ONE, LINK_RATE_UHBR20},
85 {LANE_COUNT_TWO, LINK_RATE_UHBR10},
86 {LANE_COUNT_FOUR, LINK_RATE_HIGH2},
87 {LANE_COUNT_ONE, LINK_RATE_UHBR13_5},
88 {LANE_COUNT_TWO, LINK_RATE_HIGH3},
89 {LANE_COUNT_ONE, LINK_RATE_UHBR10},
90 {LANE_COUNT_TWO, LINK_RATE_HIGH2},
91 {LANE_COUNT_FOUR, LINK_RATE_HIGH},
92 {LANE_COUNT_ONE, LINK_RATE_HIGH3},
93 {LANE_COUNT_FOUR, LINK_RATE_LOW},
94 {LANE_COUNT_ONE, LINK_RATE_HIGH2},
95 {LANE_COUNT_TWO, LINK_RATE_HIGH},
96 {LANE_COUNT_TWO, LINK_RATE_LOW},
97 {LANE_COUNT_ONE, LINK_RATE_HIGH},
98 {LANE_COUNT_ONE, LINK_RATE_LOW},
99 };
100
101 static const struct dc_link_settings fail_safe_link_settings = {
102 .lane_count = LANE_COUNT_ONE,
103 .link_rate = LINK_RATE_LOW,
104 .link_spread = LINK_SPREAD_DISABLED,
105 };
106
is_dp_active_dongle(const struct dc_link * link)107 bool is_dp_active_dongle(const struct dc_link *link)
108 {
109 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
110 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
111 }
112
is_dp_branch_device(const struct dc_link * link)113 bool is_dp_branch_device(const struct dc_link *link)
114 {
115 return link->dpcd_caps.is_branch_dev;
116 }
117
translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)118 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
119 {
120 switch (bpc) {
121 case DOWN_STREAM_MAX_8BPC:
122 return 8;
123 case DOWN_STREAM_MAX_10BPC:
124 return 10;
125 case DOWN_STREAM_MAX_12BPC:
126 return 12;
127 case DOWN_STREAM_MAX_16BPC:
128 return 16;
129 default:
130 break;
131 }
132
133 return -1;
134 }
135
dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)136 uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)
137 {
138 switch (lttpr_repeater_count) {
139 case 0x80: // 1 lttpr repeater
140 return 1;
141 case 0x40: // 2 lttpr repeaters
142 return 2;
143 case 0x20: // 3 lttpr repeaters
144 return 3;
145 case 0x10: // 4 lttpr repeaters
146 return 4;
147 case 0x08: // 5 lttpr repeaters
148 return 5;
149 case 0x04: // 6 lttpr repeaters
150 return 6;
151 case 0x02: // 7 lttpr repeaters
152 return 7;
153 case 0x01: // 8 lttpr repeaters
154 return 8;
155 default:
156 break;
157 }
158 return 0; // invalid value
159 }
160
dp_get_closest_lttpr_offset(uint8_t lttpr_count)161 uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count)
162 {
163 /* Calculate offset for LTTPR closest to DPTX which is highest in the chain
164 * Offset is 0 for single LTTPR cases as base LTTPR DPCD addresses target LTTPR 1
165 */
166 return DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE * (lttpr_count - 1);
167 }
168
link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)169 uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)
170 {
171 switch (bw) {
172 case 0b001:
173 return 9000000;
174 case 0b010:
175 return 18000000;
176 case 0b011:
177 return 24000000;
178 case 0b100:
179 return 32000000;
180 case 0b101:
181 return 40000000;
182 case 0b110:
183 return 48000000;
184 }
185
186 return 0;
187 }
188
linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)189 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
190 {
191 enum dc_link_rate link_rate;
192 // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
193 switch (link_rate_in_khz) {
194 case 1620000:
195 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane
196 break;
197 case 2160000:
198 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane
199 break;
200 case 2430000:
201 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane
202 break;
203 case 2700000:
204 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane
205 break;
206 case 3240000:
207 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane
208 break;
209 case 4320000:
210 link_rate = LINK_RATE_RATE_6; // Rate_6 - 4.32 Gbps/Lane
211 break;
212 case 5400000:
213 link_rate = LINK_RATE_HIGH2; // Rate_7 (HBR2)- 5.40 Gbps/Lane
214 break;
215 case 6750000:
216 link_rate = LINK_RATE_RATE_8; // Rate_8 - 6.75 Gbps/Lane
217 break;
218 case 8100000:
219 link_rate = LINK_RATE_HIGH3; // Rate_9 (HBR3)- 8.10 Gbps/Lane
220 break;
221 case 10000000:
222 link_rate = LINK_RATE_UHBR10; // UHBR10 - 10.0 Gbps/Lane
223 break;
224 case 13500000:
225 link_rate = LINK_RATE_UHBR13_5; // UHBR13.5 - 13.5 Gbps/Lane
226 break;
227 case 20000000:
228 link_rate = LINK_RATE_UHBR20; // UHBR20 - 20.0 Gbps/Lane
229 break;
230
231 default:
232 link_rate = LINK_RATE_UNKNOWN;
233 break;
234 }
235 return link_rate;
236 }
237
intersect_cable_id(union dp_cable_id * a,union dp_cable_id * b)238 static union dp_cable_id intersect_cable_id(
239 union dp_cable_id *a, union dp_cable_id *b)
240 {
241 union dp_cable_id out;
242
243 out.bits.UHBR10_20_CAPABILITY = MIN(a->bits.UHBR10_20_CAPABILITY,
244 b->bits.UHBR10_20_CAPABILITY);
245 out.bits.UHBR13_5_CAPABILITY = MIN(a->bits.UHBR13_5_CAPABILITY,
246 b->bits.UHBR13_5_CAPABILITY);
247 out.bits.CABLE_TYPE = MAX(a->bits.CABLE_TYPE, b->bits.CABLE_TYPE);
248
249 return out;
250 }
251
252 /*
253 * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw.
254 */
intersect_frl_link_bw_support(const uint32_t max_supported_frl_bw_in_kbps,const union hdmi_encoded_link_bw hdmi_encoded_link_bw)255 static uint32_t intersect_frl_link_bw_support(
256 const uint32_t max_supported_frl_bw_in_kbps,
257 const union hdmi_encoded_link_bw hdmi_encoded_link_bw)
258 {
259 uint32_t supported_bw_in_kbps = max_supported_frl_bw_in_kbps;
260
261 /* Skip checking FRL_MODE bit, as certain PCON will clear
262 * it despite supporting the link BW indicated in the other bits.
263 */
264 if (hdmi_encoded_link_bw.bits.BW_48Gbps)
265 supported_bw_in_kbps = 48000000;
266 else if (hdmi_encoded_link_bw.bits.BW_40Gbps)
267 supported_bw_in_kbps = 40000000;
268 else if (hdmi_encoded_link_bw.bits.BW_32Gbps)
269 supported_bw_in_kbps = 32000000;
270 else if (hdmi_encoded_link_bw.bits.BW_24Gbps)
271 supported_bw_in_kbps = 24000000;
272 else if (hdmi_encoded_link_bw.bits.BW_18Gbps)
273 supported_bw_in_kbps = 18000000;
274 else if (hdmi_encoded_link_bw.bits.BW_9Gbps)
275 supported_bw_in_kbps = 9000000;
276 else if (hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED)
277 supported_bw_in_kbps = 0; /* This case should only get hit in regulated autonomous mode. */
278
279 return supported_bw_in_kbps;
280 }
281
get_clock_source_id(struct dc_link * link)282 static enum clock_source_id get_clock_source_id(struct dc_link *link)
283 {
284 enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
285 struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
286
287 if (dp_cs != NULL) {
288 dp_cs_id = dp_cs->id;
289 } else {
290 /*
291 * dp clock source is not initialized for some reason.
292 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
293 */
294 ASSERT(dp_cs);
295 }
296
297 return dp_cs_id;
298 }
299
dp_wa_power_up_0010FA(struct dc_link * link,uint8_t * dpcd_data,int length)300 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
301 int length)
302 {
303 int retry = 0;
304
305 if (!link->dpcd_caps.dpcd_rev.raw) {
306 do {
307 dpcd_write_rx_power_ctrl(link, true);
308 core_link_read_dpcd(link, DP_DPCD_REV,
309 dpcd_data, length);
310 link->dpcd_caps.dpcd_rev.raw = dpcd_data[
311 DP_DPCD_REV -
312 DP_DPCD_REV];
313 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
314 }
315
316 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
317 switch (link->dpcd_caps.branch_dev_id) {
318 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
319 * all internal circuits including AUX communication preventing
320 * reading DPCD table and EDID (spec violation).
321 * Encoder will skip DP RX power down on disable_output to
322 * keep receiver powered all the time.*/
323 case DP_BRANCH_DEVICE_ID_0010FA:
324 case DP_BRANCH_DEVICE_ID_0080E1:
325 case DP_BRANCH_DEVICE_ID_00E04C:
326 link->wa_flags.dp_keep_receiver_powered = true;
327 break;
328
329 /* TODO: May need work around for other dongles. */
330 default:
331 link->wa_flags.dp_keep_receiver_powered = false;
332 break;
333 }
334 } else
335 link->wa_flags.dp_keep_receiver_powered = false;
336 }
337
dp_is_fec_supported(const struct dc_link * link)338 bool dp_is_fec_supported(const struct dc_link *link)
339 {
340 /* TODO - use asic cap instead of link_enc->features
341 * we no longer know which link enc to use for this link before commit
342 */
343 struct resource_context *res_ctx = &link->dc->current_state->res_ctx;
344 struct resource_pool *res_pool = link->dc->res_pool;
345 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link);
346
347 if (!link->dc->config.unify_link_enc_assignment)
348 link_enc = link_enc_cfg_get_link_enc(link);
349 ASSERT(link_enc);
350
351 return (dc_is_dp_signal(link->connector_signal) && link_enc &&
352 link_enc->features.fec_supported &&
353 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE);
354 }
355
dp_should_enable_fec(const struct dc_link * link)356 bool dp_should_enable_fec(const struct dc_link *link)
357 {
358 bool force_disable = false;
359
360 if (link->fec_state == dc_link_fec_enabled)
361 force_disable = false;
362 else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
363 link->local_sink &&
364 link->local_sink->edid_caps.panel_patch.disable_fec)
365 force_disable = true;
366 else if (link->connector_signal == SIGNAL_TYPE_EDP
367 && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
368 dsc_support.DSC_SUPPORT == false
369 || link->panel_config.dsc.disable_dsc_edp
370 || !link->dc->caps.edp_dsc_support))
371 force_disable = true;
372
373 return !force_disable && dp_is_fec_supported(link);
374 }
375
dp_is_128b_132b_signal(struct pipe_ctx * pipe_ctx)376 bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)
377 {
378 /* If this assert is hit then we have a link encoder dynamic management issue */
379 ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
380 return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
381 pipe_ctx->link_res.hpo_dp_link_enc &&
382 dc_is_dp_signal(pipe_ctx->stream->signal));
383 }
384
dp_is_lttpr_present(struct dc_link * link)385 bool dp_is_lttpr_present(struct dc_link *link)
386 {
387 /* Some sink devices report invalid LTTPR revision, so don't validate against that cap */
388 uint32_t lttpr_count = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
389 bool is_lttpr_present = (lttpr_count > 0 &&
390 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
391 link->dpcd_caps.lttpr_caps.max_lane_count <= 4);
392
393 if (lttpr_count > 0 && !is_lttpr_present)
394 DC_LOG_ERROR("LTTPR count is nonzero but invalid lane count reported. Assuming no LTTPR present.\n");
395
396 return is_lttpr_present;
397 }
398
399 /* in DP compliance test, DPR-120 may have
400 * a random value in its MAX_LINK_BW dpcd field.
401 * We map it to the maximum supported link rate that
402 * is smaller than MAX_LINK_BW in this case.
403 */
get_link_rate_from_max_link_bw(uint8_t max_link_bw)404 static enum dc_link_rate get_link_rate_from_max_link_bw(
405 uint8_t max_link_bw)
406 {
407 enum dc_link_rate link_rate;
408
409 if (max_link_bw >= LINK_RATE_HIGH3) {
410 link_rate = LINK_RATE_HIGH3;
411 } else if (max_link_bw < LINK_RATE_HIGH3
412 && max_link_bw >= LINK_RATE_HIGH2) {
413 link_rate = LINK_RATE_HIGH2;
414 } else if (max_link_bw < LINK_RATE_HIGH2
415 && max_link_bw >= LINK_RATE_HIGH) {
416 link_rate = LINK_RATE_HIGH;
417 } else if (max_link_bw < LINK_RATE_HIGH
418 && max_link_bw >= LINK_RATE_LOW) {
419 link_rate = LINK_RATE_LOW;
420 } else {
421 link_rate = LINK_RATE_UNKNOWN;
422 }
423
424 return link_rate;
425 }
426
get_lttpr_max_link_rate(struct dc_link * link)427 static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link)
428 {
429
430 enum dc_link_rate lttpr_max_link_rate = LINK_RATE_UNKNOWN;
431
432 switch (link->dpcd_caps.lttpr_caps.max_link_rate) {
433 case LINK_RATE_LOW:
434 case LINK_RATE_HIGH:
435 case LINK_RATE_HIGH2:
436 case LINK_RATE_HIGH3:
437 lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
438 break;
439 }
440
441 if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20)
442 lttpr_max_link_rate = LINK_RATE_UHBR20;
443 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
444 lttpr_max_link_rate = LINK_RATE_UHBR13_5;
445 else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR10)
446 lttpr_max_link_rate = LINK_RATE_UHBR10;
447
448 return lttpr_max_link_rate;
449 }
450
get_cable_max_link_rate(struct dc_link * link)451 static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link)
452 {
453 enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN;
454
455 if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR20) {
456 cable_max_link_rate = LINK_RATE_UHBR20;
457 } else if (link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY) {
458 cable_max_link_rate = LINK_RATE_UHBR13_5;
459 } else if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR10) {
460 // allow DP40 cables to do UHBR13.5 for passive or unknown cable type
461 if (link->dpcd_caps.cable_id.bits.CABLE_TYPE < 2) {
462 cable_max_link_rate = LINK_RATE_UHBR13_5;
463 } else {
464 cable_max_link_rate = LINK_RATE_UHBR10;
465 }
466 }
467
468 return cable_max_link_rate;
469 }
470
reached_minimum_lane_count(enum dc_lane_count lane_count)471 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
472 {
473 return lane_count <= LANE_COUNT_ONE;
474 }
475
reached_minimum_link_rate(enum dc_link_rate link_rate)476 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
477 {
478 return link_rate <= LINK_RATE_LOW;
479 }
480
reduce_lane_count(enum dc_lane_count lane_count)481 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
482 {
483 switch (lane_count) {
484 case LANE_COUNT_FOUR:
485 return LANE_COUNT_TWO;
486 case LANE_COUNT_TWO:
487 return LANE_COUNT_ONE;
488 case LANE_COUNT_ONE:
489 return LANE_COUNT_UNKNOWN;
490 default:
491 return LANE_COUNT_UNKNOWN;
492 }
493 }
494
reduce_link_rate(const struct dc_link * link,enum dc_link_rate link_rate)495 static enum dc_link_rate reduce_link_rate(const struct dc_link *link, enum dc_link_rate link_rate)
496 {
497 // NEEDSWORK: provide some details about why this function never returns some of the
498 // obscure link rates such as 4.32 Gbps or 3.24 Gbps and if such behavior is intended.
499 //
500
501 switch (link_rate) {
502 case LINK_RATE_UHBR20:
503 return LINK_RATE_UHBR13_5;
504 case LINK_RATE_UHBR13_5:
505 return LINK_RATE_UHBR10;
506 case LINK_RATE_UHBR10:
507 return LINK_RATE_HIGH3;
508 case LINK_RATE_HIGH3:
509 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->debug.support_eDP1_5)
510 return LINK_RATE_RATE_8;
511 return LINK_RATE_HIGH2;
512 case LINK_RATE_RATE_8:
513 return LINK_RATE_HIGH2;
514 case LINK_RATE_HIGH2:
515 return LINK_RATE_HIGH;
516 case LINK_RATE_RATE_6:
517 case LINK_RATE_RBR2:
518 return LINK_RATE_HIGH;
519 case LINK_RATE_HIGH:
520 return LINK_RATE_LOW;
521 case LINK_RATE_RATE_3:
522 case LINK_RATE_RATE_2:
523 return LINK_RATE_LOW;
524 case LINK_RATE_LOW:
525 default:
526 return LINK_RATE_UNKNOWN;
527 }
528 }
529
increase_lane_count(enum dc_lane_count lane_count)530 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
531 {
532 switch (lane_count) {
533 case LANE_COUNT_ONE:
534 return LANE_COUNT_TWO;
535 case LANE_COUNT_TWO:
536 return LANE_COUNT_FOUR;
537 default:
538 return LANE_COUNT_UNKNOWN;
539 }
540 }
541
increase_link_rate(struct dc_link * link,enum dc_link_rate link_rate)542 static enum dc_link_rate increase_link_rate(struct dc_link *link,
543 enum dc_link_rate link_rate)
544 {
545 switch (link_rate) {
546 case LINK_RATE_LOW:
547 return LINK_RATE_HIGH;
548 case LINK_RATE_HIGH:
549 return LINK_RATE_HIGH2;
550 case LINK_RATE_HIGH2:
551 return LINK_RATE_HIGH3;
552 case LINK_RATE_HIGH3:
553 return LINK_RATE_UHBR10;
554 case LINK_RATE_UHBR10:
555 /* upto DP2.x specs UHBR13.5 is the only link rate that could be
556 * not supported by DPRX when higher link rate is supported.
557 * so we treat it as a special case for code simplicity. When we
558 * have new specs with more link rates like this, we should
559 * consider a more generic solution to handle discrete link
560 * rate capabilities.
561 */
562 return link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 ?
563 LINK_RATE_UHBR13_5 : LINK_RATE_UHBR20;
564 case LINK_RATE_UHBR13_5:
565 return LINK_RATE_UHBR20;
566 default:
567 return LINK_RATE_UNKNOWN;
568 }
569 }
570
increase_edp_link_rate(struct dc_link * link,struct dc_link_settings * current_link_setting)571 static void increase_edp_link_rate(struct dc_link *link,
572 struct dc_link_settings *current_link_setting)
573 {
574 if (current_link_setting->use_link_rate_set) {
575 if (current_link_setting->link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
576 current_link_setting->link_rate_set++;
577 current_link_setting->link_rate =
578 link->dpcd_caps.edp_supported_link_rates[current_link_setting->link_rate_set];
579 } else {
580 current_link_setting->use_link_rate_set = false;
581 current_link_setting->link_rate = LINK_RATE_UHBR10;
582 }
583 } else {
584 current_link_setting->link_rate = increase_link_rate(link, current_link_setting->link_rate);
585 }
586 }
587
decide_fallback_link_setting_max_bw_policy(struct dc_link * link,const struct dc_link_settings * max,struct dc_link_settings * cur,enum link_training_result training_result)588 static bool decide_fallback_link_setting_max_bw_policy(
589 struct dc_link *link,
590 const struct dc_link_settings *max,
591 struct dc_link_settings *cur,
592 enum link_training_result training_result)
593 {
594 uint32_t cur_idx = 0, next_idx;
595 bool found = false;
596
597 if (training_result == LINK_TRAINING_ABORT)
598 return false;
599
600 while (cur_idx < ARRAY_SIZE(dp_lt_fallbacks))
601 /* find current index */
602 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count &&
603 dp_lt_fallbacks[cur_idx].link_rate == cur->link_rate)
604 break;
605 else
606 cur_idx++;
607
608 next_idx = cur_idx + 1;
609
610 while (next_idx < ARRAY_SIZE(dp_lt_fallbacks))
611 /* find next index */
612 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count ||
613 dp_lt_fallbacks[next_idx].link_rate > max->link_rate)
614 next_idx++;
615 else if (dp_lt_fallbacks[next_idx].link_rate == LINK_RATE_UHBR13_5 &&
616 link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 == 0)
617 /* upto DP2.x specs UHBR13.5 is the only link rate that
618 * could be not supported by DPRX when higher link rate
619 * is supported. so we treat it as a special case for
620 * code simplicity. When we have new specs with more
621 * link rates like this, we should consider a more
622 * generic solution to handle discrete link rate
623 * capabilities.
624 */
625 next_idx++;
626 else
627 break;
628
629 if (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) {
630 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count;
631 cur->link_rate = dp_lt_fallbacks[next_idx].link_rate;
632 found = true;
633 }
634
635 return found;
636 }
637
638 /*
639 * function: set link rate and lane count fallback based
640 * on current link setting and last link training result
641 * return value:
642 * true - link setting could be set
643 * false - has reached minimum setting
644 * and no further fallback could be done
645 */
decide_fallback_link_setting(struct dc_link * link,struct dc_link_settings * max,struct dc_link_settings * cur,enum link_training_result training_result)646 bool decide_fallback_link_setting(
647 struct dc_link *link,
648 struct dc_link_settings *max,
649 struct dc_link_settings *cur,
650 enum link_training_result training_result)
651 {
652 if (link_dp_get_encoding_format(max) == DP_128b_132b_ENCODING ||
653 link->dc->debug.force_dp2_lt_fallback_method)
654 return decide_fallback_link_setting_max_bw_policy(link, max,
655 cur, training_result);
656
657 switch (training_result) {
658 case LINK_TRAINING_CR_FAIL_LANE0:
659 case LINK_TRAINING_CR_FAIL_LANE1:
660 case LINK_TRAINING_CR_FAIL_LANE23:
661 case LINK_TRAINING_LQA_FAIL:
662 {
663 if (!reached_minimum_link_rate(cur->link_rate)) {
664 cur->link_rate = reduce_link_rate(link, cur->link_rate);
665 } else if (!reached_minimum_lane_count(cur->lane_count)) {
666 cur->link_rate = max->link_rate;
667 if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
668 return false;
669 else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
670 cur->lane_count = LANE_COUNT_ONE;
671 else if (training_result == LINK_TRAINING_CR_FAIL_LANE23)
672 cur->lane_count = LANE_COUNT_TWO;
673 else
674 cur->lane_count = reduce_lane_count(cur->lane_count);
675 } else {
676 return false;
677 }
678 break;
679 }
680 case LINK_TRAINING_EQ_FAIL_EQ:
681 case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
682 {
683 if (!reached_minimum_lane_count(cur->lane_count)) {
684 cur->lane_count = reduce_lane_count(cur->lane_count);
685 } else if (!reached_minimum_link_rate(cur->link_rate)) {
686 cur->link_rate = reduce_link_rate(link, cur->link_rate);
687 /* Reduce max link rate to avoid potential infinite loop.
688 * Needed so that any subsequent CR_FAIL fallback can't
689 * re-set the link rate higher than the link rate from
690 * the latest EQ_FAIL fallback.
691 */
692 max->link_rate = cur->link_rate;
693 cur->lane_count = max->lane_count;
694 } else {
695 return false;
696 }
697 break;
698 }
699 case LINK_TRAINING_EQ_FAIL_CR:
700 {
701 if (!reached_minimum_link_rate(cur->link_rate)) {
702 cur->link_rate = reduce_link_rate(link, cur->link_rate);
703 /* Reduce max link rate to avoid potential infinite loop.
704 * Needed so that any subsequent CR_FAIL fallback can't
705 * re-set the link rate higher than the link rate from
706 * the latest EQ_FAIL fallback.
707 */
708 max->link_rate = cur->link_rate;
709 cur->lane_count = max->lane_count;
710 } else {
711 return false;
712 }
713 break;
714 }
715 default:
716 return false;
717 }
718 return true;
719 }
decide_dp_link_settings(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw)720 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
721 {
722 struct dc_link_settings initial_link_setting = {
723 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
724 struct dc_link_settings current_link_setting =
725 initial_link_setting;
726 uint32_t link_bw;
727
728 if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap))
729 return false;
730
731 /* search for the minimum link setting that:
732 * 1. is supported according to the link training result
733 * 2. could support the b/w requested by the timing
734 */
735 while (current_link_setting.link_rate <=
736 link->verified_link_cap.link_rate) {
737 link_bw = dp_link_bandwidth_kbps(
738 link,
739 ¤t_link_setting);
740 if (req_bw <= link_bw) {
741 *link_setting = current_link_setting;
742 return true;
743 }
744
745 if (current_link_setting.lane_count <
746 link->verified_link_cap.lane_count) {
747 current_link_setting.lane_count =
748 increase_lane_count(
749 current_link_setting.lane_count);
750 } else {
751 current_link_setting.link_rate =
752 increase_link_rate(link,
753 current_link_setting.link_rate);
754 current_link_setting.lane_count =
755 initial_link_setting.lane_count;
756 }
757 }
758
759 return false;
760 }
761
edp_decide_link_settings(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw)762 bool edp_decide_link_settings(struct dc_link *link,
763 struct dc_link_settings *link_setting, uint32_t req_bw)
764 {
765 struct dc_link_settings initial_link_setting;
766 struct dc_link_settings current_link_setting;
767 uint32_t link_bw;
768
769 /*
770 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
771 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
772 */
773 if (!edp_is_ilr_optimization_enabled(link)) {
774 *link_setting = link->verified_link_cap;
775 return true;
776 }
777
778 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
779 initial_link_setting.lane_count = LANE_COUNT_ONE;
780 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
781 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
782 initial_link_setting.use_link_rate_set = true;
783 initial_link_setting.link_rate_set = 0;
784 current_link_setting = initial_link_setting;
785
786 /* search for the minimum link setting that:
787 * 1. is supported according to the link training result
788 * 2. could support the b/w requested by the timing
789 */
790 while (current_link_setting.link_rate <=
791 link->verified_link_cap.link_rate) {
792 link_bw = dp_link_bandwidth_kbps(
793 link,
794 ¤t_link_setting);
795 if (req_bw <= link_bw) {
796 *link_setting = current_link_setting;
797 return true;
798 }
799
800 if (current_link_setting.lane_count <
801 link->verified_link_cap.lane_count) {
802 current_link_setting.lane_count =
803 increase_lane_count(
804 current_link_setting.lane_count);
805 } else {
806 increase_edp_link_rate(link, ¤t_link_setting);
807 }
808 }
809 return false;
810 }
811
decide_edp_link_settings_with_dsc(struct dc_link * link,struct dc_link_settings * link_setting,uint32_t req_bw,enum dc_link_rate max_link_rate)812 bool decide_edp_link_settings_with_dsc(struct dc_link *link,
813 struct dc_link_settings *link_setting,
814 uint32_t req_bw,
815 enum dc_link_rate max_link_rate)
816 {
817 struct dc_link_settings initial_link_setting;
818 struct dc_link_settings current_link_setting;
819 uint32_t link_bw;
820
821 unsigned int policy = 0;
822
823 policy = link->panel_config.dsc.force_dsc_edp_policy;
824 if (max_link_rate == LINK_RATE_UNKNOWN)
825 max_link_rate = link->verified_link_cap.link_rate;
826 /*
827 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
828 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
829 */
830 if (!edp_is_ilr_optimization_enabled(link)) {
831 /* for DSC enabled case, we search for minimum lane count */
832 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
833 initial_link_setting.lane_count = LANE_COUNT_ONE;
834 initial_link_setting.link_rate = LINK_RATE_LOW;
835 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
836 initial_link_setting.use_link_rate_set = false;
837 initial_link_setting.link_rate_set = 0;
838 current_link_setting = initial_link_setting;
839 if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap))
840 return false;
841
842 /* search for the minimum link setting that:
843 * 1. is supported according to the link training result
844 * 2. could support the b/w requested by the timing
845 */
846 while (current_link_setting.link_rate <=
847 max_link_rate) {
848 link_bw = dp_link_bandwidth_kbps(
849 link,
850 ¤t_link_setting);
851 if (req_bw <= link_bw) {
852 *link_setting = current_link_setting;
853 return true;
854 }
855 if (policy) {
856 /* minimize lane */
857 if (current_link_setting.link_rate < max_link_rate) {
858 increase_edp_link_rate(link, ¤t_link_setting);
859 } else {
860 if (current_link_setting.lane_count <
861 link->verified_link_cap.lane_count) {
862 current_link_setting.lane_count =
863 increase_lane_count(
864 current_link_setting.lane_count);
865 current_link_setting.link_rate = initial_link_setting.link_rate;
866 } else
867 break;
868 }
869 } else {
870 /* minimize link rate */
871 if (current_link_setting.lane_count <
872 link->verified_link_cap.lane_count) {
873 current_link_setting.lane_count =
874 increase_lane_count(
875 current_link_setting.lane_count);
876 } else {
877 increase_edp_link_rate(link, ¤t_link_setting);
878 current_link_setting.lane_count =
879 initial_link_setting.lane_count;
880 }
881 }
882 }
883 return false;
884 }
885
886 /* if optimize edp link is supported */
887 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
888 initial_link_setting.lane_count = LANE_COUNT_ONE;
889 initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
890 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
891 initial_link_setting.use_link_rate_set = true;
892 initial_link_setting.link_rate_set = 0;
893 current_link_setting = initial_link_setting;
894
895 /* search for the minimum link setting that:
896 * 1. is supported according to the link training result
897 * 2. could support the b/w requested by the timing
898 */
899 while (current_link_setting.link_rate <=
900 max_link_rate) {
901 link_bw = dp_link_bandwidth_kbps(
902 link,
903 ¤t_link_setting);
904 if (req_bw <= link_bw) {
905 *link_setting = current_link_setting;
906 return true;
907 }
908 if (policy) {
909 /* minimize lane */
910 if (current_link_setting.link_rate < max_link_rate) {
911 increase_edp_link_rate(link, ¤t_link_setting);
912 } else {
913 if (current_link_setting.lane_count < link->verified_link_cap.lane_count) {
914 current_link_setting.lane_count =
915 increase_lane_count(
916 current_link_setting.lane_count);
917 current_link_setting.link_rate_set = initial_link_setting.link_rate_set;
918 current_link_setting.use_link_rate_set = initial_link_setting.use_link_rate_set;
919 current_link_setting.link_rate =
920 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
921 } else
922 break;
923 }
924 } else {
925 /* minimize link rate */
926 if (current_link_setting.lane_count <
927 link->verified_link_cap.lane_count) {
928 current_link_setting.lane_count =
929 increase_lane_count(
930 current_link_setting.lane_count);
931 } else {
932 increase_edp_link_rate(link, ¤t_link_setting);
933 if (current_link_setting.link_rate == LINK_RATE_UNKNOWN)
934 break;
935 }
936 }
937 }
938 return false;
939 }
940
decide_mst_link_settings(const struct dc_link * link,struct dc_link_settings * link_setting)941 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
942 {
943 *link_setting = link->verified_link_cap;
944 return true;
945 }
946
link_decide_link_settings(struct dc_stream_state * stream,struct dc_link_settings * link_setting)947 bool link_decide_link_settings(struct dc_stream_state *stream,
948 struct dc_link_settings *link_setting)
949 {
950 struct dc_link *link = stream->link;
951 uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, dc_link_get_highest_encoding_format(link));
952
953 memset(link_setting, 0, sizeof(*link_setting));
954
955 if (dc_is_dp_signal(stream->signal) &&
956 link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
957 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) {
958 /* if preferred is specified through AMDDP, use it, if it's enough
959 * to drive the mode
960 */
961 *link_setting = link->preferred_link_setting;
962 } else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
963 /* MST doesn't perform link training for now
964 * TODO: add MST specific link training routine
965 */
966 decide_mst_link_settings(link, link_setting);
967 } else if (stream->signal == SIGNAL_TYPE_VIRTUAL) {
968 link_setting->lane_count = LANE_COUNT_FOUR;
969 link_setting->link_rate = LINK_RATE_HIGH3;
970 } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
971 /* enable edp link optimization for DSC eDP case */
972 if (stream->timing.flags.DSC) {
973 enum dc_link_rate max_link_rate = LINK_RATE_UNKNOWN;
974
975 if (link->panel_config.dsc.force_dsc_edp_policy) {
976 /* calculate link max link rate cap*/
977 struct dc_link_settings tmp_link_setting;
978 struct dc_crtc_timing tmp_timing = stream->timing;
979 uint32_t orig_req_bw;
980
981 tmp_link_setting.link_rate = LINK_RATE_UNKNOWN;
982 tmp_timing.flags.DSC = 0;
983 orig_req_bw = dc_bandwidth_in_kbps_from_timing(&tmp_timing,
984 dc_link_get_highest_encoding_format(link));
985 edp_decide_link_settings(link, &tmp_link_setting, orig_req_bw);
986 max_link_rate = tmp_link_setting.link_rate;
987 }
988 decide_edp_link_settings_with_dsc(link, link_setting, req_bw, max_link_rate);
989 } else {
990 edp_decide_link_settings(link, link_setting, req_bw);
991 }
992 } else {
993 decide_dp_link_settings(link, link_setting, req_bw);
994 }
995
996 return link_setting->lane_count != LANE_COUNT_UNKNOWN &&
997 link_setting->link_rate != LINK_RATE_UNKNOWN;
998 }
999
link_dp_get_encoding_format(const struct dc_link_settings * link_settings)1000 enum dp_link_encoding link_dp_get_encoding_format(const struct dc_link_settings *link_settings)
1001 {
1002 if ((link_settings->link_rate >= LINK_RATE_LOW) &&
1003 (link_settings->link_rate <= LINK_RATE_HIGH3))
1004 return DP_8b_10b_ENCODING;
1005 else if ((link_settings->link_rate >= LINK_RATE_UHBR10) &&
1006 (link_settings->link_rate <= LINK_RATE_UHBR20))
1007 return DP_128b_132b_ENCODING;
1008 return DP_UNKNOWN_ENCODING;
1009 }
1010
mst_decide_link_encoding_format(const struct dc_link * link)1011 enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link)
1012 {
1013 struct dc_link_settings link_settings = {0};
1014
1015 if (!dc_is_dp_signal(link->connector_signal))
1016 return DP_UNKNOWN_ENCODING;
1017
1018 if (link->preferred_link_setting.lane_count !=
1019 LANE_COUNT_UNKNOWN &&
1020 link->preferred_link_setting.link_rate !=
1021 LINK_RATE_UNKNOWN) {
1022 link_settings = link->preferred_link_setting;
1023 } else {
1024 decide_mst_link_settings(link, &link_settings);
1025 }
1026
1027 return link_dp_get_encoding_format(&link_settings);
1028 }
1029
read_dp_device_vendor_id(struct dc_link * link)1030 static void read_dp_device_vendor_id(struct dc_link *link)
1031 {
1032 struct dp_device_vendor_id dp_id = {0};
1033
1034 /* read IEEE branch device id */
1035 core_link_read_dpcd(
1036 link,
1037 DP_BRANCH_OUI,
1038 (uint8_t *)&dp_id,
1039 sizeof(dp_id));
1040
1041 link->dpcd_caps.branch_dev_id =
1042 (dp_id.ieee_oui[0] << 16) +
1043 (dp_id.ieee_oui[1] << 8) +
1044 dp_id.ieee_oui[2];
1045
1046 memmove(
1047 link->dpcd_caps.branch_dev_name,
1048 dp_id.ieee_device_id,
1049 sizeof(dp_id.ieee_device_id));
1050 }
1051
wake_up_aux_channel(struct dc_link * link)1052 static enum dc_status wake_up_aux_channel(struct dc_link *link)
1053 {
1054 enum dc_status status = DC_ERROR_UNEXPECTED;
1055 uint32_t aux_channel_retry_cnt = 0;
1056 uint8_t dpcd_power_state = '\0';
1057
1058 while (status != DC_OK && aux_channel_retry_cnt < 10) {
1059 status = core_link_read_dpcd(link, DP_SET_POWER,
1060 &dpcd_power_state, sizeof(dpcd_power_state));
1061
1062 /* Delay 1 ms if AUX CH is in power down state. Based on spec
1063 * section 2.3.1.2, if AUX CH may be powered down due to
1064 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
1065 * signal and may need up to 1 ms before being able to reply.
1066 */
1067 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) {
1068 fsleep(1000);
1069 aux_channel_retry_cnt++;
1070 }
1071 }
1072
1073 if (status != DC_OK) {
1074 dpcd_power_state = DP_SET_POWER_D0;
1075 status = core_link_write_dpcd(
1076 link,
1077 DP_SET_POWER,
1078 &dpcd_power_state,
1079 sizeof(dpcd_power_state));
1080
1081 dpcd_power_state = DP_SET_POWER_D3;
1082 status = core_link_write_dpcd(
1083 link,
1084 DP_SET_POWER,
1085 &dpcd_power_state,
1086 sizeof(dpcd_power_state));
1087 DC_LOG_DC("%s: Failed to power up sink\n", __func__);
1088 return DC_ERROR_UNEXPECTED;
1089 }
1090
1091 return DC_OK;
1092 }
1093
read_and_intersect_post_frl_lt_status(struct dc_link * link)1094 static void read_and_intersect_post_frl_lt_status(
1095 struct dc_link *link)
1096 {
1097 union autonomous_mode_and_frl_link_status autonomous_mode_caps = {0};
1098 union hdmi_tx_link_status hdmi_tx_link_status = {0};
1099 union hdmi_encoded_link_bw hdmi_encoded_link_bw = {0};
1100
1101 /* Check if dongle supports regulated autonomous mode. */
1102 core_link_read_dpcd(link, DP_REGULATED_AUTONOMOUS_MODE_SUPPORTED_AND_HDMI_LINK_TRAINING_STATUS,
1103 &autonomous_mode_caps.raw, sizeof(autonomous_mode_caps));
1104
1105 link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support =
1106 autonomous_mode_caps.bits.REGULATED_AUTONOMOUS_MODE_SUPPORTED;
1107
1108 if (link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support) {
1109 DC_LOG_DC("%s: PCON supports regulated autonomous mode.\n", __func__);
1110
1111 core_link_read_dpcd(link, DP_PCON_HDMI_TX_LINK_STATUS,
1112 &hdmi_tx_link_status.raw, sizeof(hdmi_tx_link_status));
1113 }
1114
1115 // Intersect reported max link bw support with the supported link rate post FRL link training
1116 if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS,
1117 &hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) {
1118
1119 if (link->dpcd_caps.dongle_caps.dp_hdmi_regulated_autonomous_mode_support &&
1120 (!hdmi_tx_link_status.bits.HDMI_TX_READY_STATUS ||
1121 !hdmi_encoded_link_bw.bits.FRL_LINK_TRAINING_FINISHED)) {
1122 DC_LOG_WARNING("%s: PCON TX link training has not finished.\n", __func__);
1123
1124 /* Link training not finished, ignore values from this DPCD reg. */
1125 return;
1126 }
1127
1128 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support(
1129 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps,
1130 hdmi_encoded_link_bw);
1131 DC_LOG_DC("%s: pcon frl link bw = %u\n", __func__,
1132 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps);
1133 }
1134 }
1135
get_active_converter_info(uint8_t data,struct dc_link * link)1136 static void get_active_converter_info(
1137 uint8_t data, struct dc_link *link)
1138 {
1139 union dp_downstream_port_present ds_port = { .byte = data };
1140 memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
1141
1142 /* decode converter info*/
1143 if (!ds_port.fields.PORT_PRESENT) {
1144 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1145 set_dongle_type(link->ddc,
1146 link->dpcd_caps.dongle_type);
1147 link->dpcd_caps.is_branch_dev = false;
1148 return;
1149 }
1150
1151 /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
1152 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
1153
1154 switch (ds_port.fields.PORT_TYPE) {
1155 case DOWNSTREAM_VGA:
1156 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
1157 break;
1158 case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
1159 /* At this point we don't know is it DVI or HDMI or DP++,
1160 * assume DVI.*/
1161 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
1162 break;
1163 default:
1164 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1165 break;
1166 }
1167
1168 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
1169 uint8_t det_caps[16] = {0}; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
1170 union dwnstream_port_caps_byte0 *port_caps =
1171 (union dwnstream_port_caps_byte0 *)det_caps;
1172 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
1173 det_caps, sizeof(det_caps)) == DC_OK) {
1174
1175 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
1176 /*Handle DP case as DONGLE_NONE*/
1177 case DOWN_STREAM_DETAILED_DP:
1178 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1179 break;
1180 case DOWN_STREAM_DETAILED_VGA:
1181 link->dpcd_caps.dongle_type =
1182 DISPLAY_DONGLE_DP_VGA_CONVERTER;
1183 break;
1184 case DOWN_STREAM_DETAILED_DVI:
1185 link->dpcd_caps.dongle_type =
1186 DISPLAY_DONGLE_DP_DVI_CONVERTER;
1187 break;
1188 case DOWN_STREAM_DETAILED_HDMI:
1189 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
1190 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
1191 link->dpcd_caps.dongle_type =
1192 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
1193
1194 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
1195 if (ds_port.fields.DETAILED_CAPS) {
1196
1197 union dwnstream_port_caps_byte3_hdmi
1198 hdmi_caps = {.raw = det_caps[3] };
1199 union dwnstream_port_caps_byte2
1200 hdmi_color_caps = {.raw = det_caps[2] };
1201 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
1202 det_caps[1] * 2500;
1203
1204 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
1205 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
1206 /*YCBCR capability only for HDMI case*/
1207 if (port_caps->bits.DWN_STRM_PORTX_TYPE
1208 == DOWN_STREAM_DETAILED_HDMI) {
1209 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
1210 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
1211 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
1212 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
1213 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
1214 hdmi_caps.bits.YCrCr422_CONVERSION;
1215 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
1216 hdmi_caps.bits.YCrCr420_CONVERSION;
1217 }
1218
1219 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
1220 translate_dpcd_max_bpc(
1221 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
1222
1223 if (link->dc->caps.dp_hdmi21_pcon_support) {
1224
1225 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps =
1226 link_bw_kbps_from_raw_frl_link_rate_data(
1227 hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT);
1228
1229 read_and_intersect_post_frl_lt_status(link);
1230
1231 if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0)
1232 link->dpcd_caps.dongle_caps.extendedCapValid = true;
1233 }
1234
1235 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
1236 link->dpcd_caps.dongle_caps.extendedCapValid = true;
1237 }
1238
1239 break;
1240 }
1241 }
1242 }
1243
1244 set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
1245
1246 {
1247 struct dp_sink_hw_fw_revision dp_hw_fw_revision = {0};
1248
1249 core_link_read_dpcd(
1250 link,
1251 DP_BRANCH_REVISION_START,
1252 (uint8_t *)&dp_hw_fw_revision,
1253 sizeof(dp_hw_fw_revision));
1254
1255 link->dpcd_caps.branch_hw_revision =
1256 dp_hw_fw_revision.ieee_hw_rev;
1257
1258 memmove(
1259 link->dpcd_caps.branch_fw_revision,
1260 dp_hw_fw_revision.ieee_fw_rev,
1261 sizeof(dp_hw_fw_revision.ieee_fw_rev));
1262 }
1263
1264 core_link_read_dpcd(
1265 link,
1266 DP_BRANCH_VENDOR_SPECIFIC_START,
1267 (uint8_t *)link->dpcd_caps.branch_vendor_specific_data,
1268 sizeof(link->dpcd_caps.branch_vendor_specific_data));
1269
1270 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
1271 link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1272 union dp_dfp_cap_ext dfp_cap_ext;
1273 memset(&dfp_cap_ext, '\0', sizeof (dfp_cap_ext));
1274 core_link_read_dpcd(
1275 link,
1276 DP_DFP_CAPABILITY_EXTENSION_SUPPORT,
1277 dfp_cap_ext.raw,
1278 sizeof(dfp_cap_ext.raw));
1279 link->dpcd_caps.dongle_caps.dfp_cap_ext.supported = dfp_cap_ext.fields.supported;
1280 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps =
1281 dfp_cap_ext.fields.max_pixel_rate_in_mps[0] +
1282 (dfp_cap_ext.fields.max_pixel_rate_in_mps[1] << 8);
1283 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width =
1284 dfp_cap_ext.fields.max_video_h_active_width[0] +
1285 (dfp_cap_ext.fields.max_video_h_active_width[1] << 8);
1286 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height =
1287 dfp_cap_ext.fields.max_video_v_active_height[0] +
1288 (dfp_cap_ext.fields.max_video_v_active_height[1] << 8);
1289 link->dpcd_caps.dongle_caps.dfp_cap_ext.encoding_format_caps =
1290 dfp_cap_ext.fields.encoding_format_caps;
1291 link->dpcd_caps.dongle_caps.dfp_cap_ext.rgb_color_depth_caps =
1292 dfp_cap_ext.fields.rgb_color_depth_caps;
1293 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr444_color_depth_caps =
1294 dfp_cap_ext.fields.ycbcr444_color_depth_caps;
1295 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr422_color_depth_caps =
1296 dfp_cap_ext.fields.ycbcr422_color_depth_caps;
1297 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr420_color_depth_caps =
1298 dfp_cap_ext.fields.ycbcr420_color_depth_caps;
1299 DC_LOG_DP2("DFP capability extension is read at link %d", link->link_index);
1300 DC_LOG_DP2("\tdfp_cap_ext.supported = %s", link->dpcd_caps.dongle_caps.dfp_cap_ext.supported ? "true" : "false");
1301 DC_LOG_DP2("\tdfp_cap_ext.max_pixel_rate_in_mps = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps);
1302 DC_LOG_DP2("\tdfp_cap_ext.max_video_h_active_width = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width);
1303 DC_LOG_DP2("\tdfp_cap_ext.max_video_v_active_height = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height);
1304 }
1305 }
1306
apply_usbc_combo_phy_reset_wa(struct dc_link * link,struct dc_link_settings * link_settings)1307 static void apply_usbc_combo_phy_reset_wa(struct dc_link *link,
1308 struct dc_link_settings *link_settings)
1309 {
1310 /* Temporary Renoir-specific workaround PHY will sometimes be in bad
1311 * state on hotplugging display from certain USB-C dongle, so add extra
1312 * cycle of enabling and disabling the PHY before first link training.
1313 */
1314 struct link_resource link_res = {0};
1315 enum clock_source_id dp_cs_id = get_clock_source_id(link);
1316
1317 dp_enable_link_phy(link, &link_res, link->connector_signal,
1318 dp_cs_id, link_settings);
1319 dp_disable_link_phy(link, &link_res, link->connector_signal);
1320 }
1321
dp_overwrite_extended_receiver_cap(struct dc_link * link)1322 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
1323 {
1324 uint8_t dpcd_data[16] = {0};
1325 uint32_t read_dpcd_retry_cnt = 3;
1326 enum dc_status status = DC_ERROR_UNEXPECTED;
1327 union dp_downstream_port_present ds_port = { 0 };
1328 union down_stream_port_count down_strm_port_count;
1329 union edp_configuration_cap edp_config_cap;
1330
1331 int i;
1332
1333 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1334 status = core_link_read_dpcd(
1335 link,
1336 DP_DPCD_REV,
1337 dpcd_data,
1338 sizeof(dpcd_data));
1339 if (status == DC_OK)
1340 break;
1341 }
1342
1343 link->dpcd_caps.dpcd_rev.raw =
1344 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1345
1346 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1347 return false;
1348
1349 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1350 DP_DPCD_REV];
1351
1352 get_active_converter_info(ds_port.byte, link);
1353
1354 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1355 DP_DPCD_REV];
1356
1357 link->dpcd_caps.allow_invalid_MSA_timing_param =
1358 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1359
1360 link->dpcd_caps.max_ln_count.raw = dpcd_data[
1361 DP_MAX_LANE_COUNT - DP_DPCD_REV];
1362
1363 link->dpcd_caps.max_down_spread.raw = dpcd_data[
1364 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1365
1366 link->reported_link_cap.lane_count =
1367 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1368 link->reported_link_cap.link_rate = dpcd_data[
1369 DP_MAX_LINK_RATE - DP_DPCD_REV];
1370 link->reported_link_cap.link_spread =
1371 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1372 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1373
1374 edp_config_cap.raw = dpcd_data[
1375 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1376 link->dpcd_caps.panel_mode_edp =
1377 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1378 link->dpcd_caps.dpcd_display_control_capable =
1379 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1380
1381 return true;
1382 }
1383
dpcd_set_source_specific_data(struct dc_link * link)1384 void dpcd_set_source_specific_data(struct dc_link *link)
1385 {
1386 if (!link->dc->vendor_signature.is_valid) {
1387 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
1388 struct dpcd_amd_signature amd_signature = {0};
1389 struct dpcd_amd_device_id amd_device_id = {0};
1390
1391 if (link->is_dds) {
1392 uint8_t dpcd_dp_edp_backlight_mode = 0;
1393
1394 /*
1395 * Write 0 to bits 0:1 for dp_edp_backlight_mode_set register
1396 * if platform is DDS
1397 */
1398 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
1399 &dpcd_dp_edp_backlight_mode, sizeof(uint8_t));
1400 dpcd_dp_edp_backlight_mode &= ~0x3;
1401
1402 core_link_write_dpcd(link, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
1403 &dpcd_dp_edp_backlight_mode, sizeof(uint8_t));
1404 }
1405
1406 amd_device_id.device_id_byte1 =
1407 (uint8_t)(link->ctx->asic_id.chip_id);
1408 amd_device_id.device_id_byte2 =
1409 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
1410 amd_device_id.dce_version =
1411 (uint8_t)(link->ctx->dce_version);
1412 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
1413 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
1414
1415 core_link_read_dpcd(link, DP_SOURCE_OUI,
1416 (uint8_t *)(&amd_signature),
1417 sizeof(amd_signature));
1418
1419 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
1420 (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
1421 (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
1422
1423 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
1424 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
1425 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
1426
1427 core_link_write_dpcd(link, DP_SOURCE_OUI,
1428 (uint8_t *)(&amd_signature),
1429 sizeof(amd_signature));
1430 }
1431
1432 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
1433 (uint8_t *)(&amd_device_id),
1434 sizeof(amd_device_id));
1435
1436 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
1437 link->dc->caps.min_horizontal_blanking_period != 0) {
1438
1439 uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
1440
1441 result_write_min_hblank = core_link_write_dpcd(link,
1442 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
1443 sizeof(hblank_size));
1444 }
1445 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
1446 WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
1447 "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
1448 result_write_min_hblank,
1449 link->link_index,
1450 link->ctx->dce_version,
1451 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
1452 link->dc->caps.min_horizontal_blanking_period,
1453 link->dpcd_caps.branch_dev_id,
1454 link->dpcd_caps.branch_dev_name[0],
1455 link->dpcd_caps.branch_dev_name[1],
1456 link->dpcd_caps.branch_dev_name[2],
1457 link->dpcd_caps.branch_dev_name[3],
1458 link->dpcd_caps.branch_dev_name[4],
1459 link->dpcd_caps.branch_dev_name[5]);
1460 } else {
1461 core_link_write_dpcd(link, DP_SOURCE_OUI,
1462 link->dc->vendor_signature.data.raw,
1463 sizeof(link->dc->vendor_signature.data.raw));
1464 }
1465 }
1466
dpcd_write_cable_id_to_dprx(struct dc_link * link)1467 void dpcd_write_cable_id_to_dprx(struct dc_link *link)
1468 {
1469 if (!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED ||
1470 link->dpcd_caps.cable_id.raw == 0 ||
1471 link->dprx_states.cable_id_written)
1472 return;
1473
1474 core_link_write_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX,
1475 &link->dpcd_caps.cable_id.raw,
1476 sizeof(link->dpcd_caps.cable_id.raw));
1477
1478 link->dprx_states.cable_id_written = 1;
1479 }
1480
get_usbc_cable_id(struct dc_link * link,union dp_cable_id * cable_id)1481 static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id)
1482 {
1483 union dmub_rb_cmd cmd;
1484
1485 if (!link->ctx->dmub_srv ||
1486 link->ep_type != DISPLAY_ENDPOINT_PHY ||
1487 link->link_enc->features.flags.bits.DP_IS_USB_C == 0)
1488 return false;
1489
1490 memset(&cmd, 0, sizeof(cmd));
1491 cmd.cable_id.header.type = DMUB_CMD_GET_USBC_CABLE_ID;
1492 cmd.cable_id.header.payload_bytes = sizeof(cmd.cable_id.data);
1493 cmd.cable_id.data.input.phy_inst = resource_transmitter_to_phy_idx(
1494 link->dc, link->link_enc->transmitter);
1495 if (dc_wake_and_execute_dmub_cmd(link->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
1496 cmd.cable_id.header.ret_status == 1) {
1497 cable_id->raw = cmd.cable_id.data.output_raw;
1498 DC_LOG_DC("usbc_cable_id = %d.\n", cable_id->raw);
1499 }
1500 return cmd.cable_id.header.ret_status == 1;
1501 }
1502
retrieve_cable_id(struct dc_link * link)1503 static void retrieve_cable_id(struct dc_link *link)
1504 {
1505 union dp_cable_id usbc_cable_id = {0};
1506
1507 link->dpcd_caps.cable_id.raw = 0;
1508 core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX,
1509 &link->dpcd_caps.cable_id.raw, sizeof(uint8_t));
1510
1511 if (get_usbc_cable_id(link, &usbc_cable_id))
1512 link->dpcd_caps.cable_id = intersect_cable_id(
1513 &link->dpcd_caps.cable_id, &usbc_cable_id);
1514 }
1515
read_is_mst_supported(struct dc_link * link)1516 bool read_is_mst_supported(struct dc_link *link)
1517 {
1518 bool mst = false;
1519 enum dc_status st = DC_OK;
1520 union dpcd_rev rev;
1521 union mstm_cap cap;
1522
1523 if (link->preferred_training_settings.mst_enable &&
1524 *link->preferred_training_settings.mst_enable == false) {
1525 return false;
1526 }
1527
1528 rev.raw = 0;
1529 cap.raw = 0;
1530
1531 st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
1532 sizeof(rev));
1533
1534 if (st == DC_OK && rev.raw >= DPCD_REV_12) {
1535
1536 st = core_link_read_dpcd(link, DP_MSTM_CAP,
1537 &cap.raw, sizeof(cap));
1538 if (st == DC_OK && cap.bits.MST_CAP == 1)
1539 mst = true;
1540 }
1541 return mst;
1542
1543 }
1544
1545 /* Read additional sink caps defined in source specific DPCD area
1546 * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
1547 * TODO: Add FS caps and read from DP_SOURCE_SINK_FS_CAP as well
1548 */
dpcd_read_sink_ext_caps(struct dc_link * link)1549 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
1550 {
1551 uint8_t dpcd_data = 0;
1552 uint8_t edp_general_cap2 = 0;
1553
1554 if (!link)
1555 return false;
1556
1557 if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
1558 return false;
1559
1560 link->dpcd_sink_ext_caps.raw = dpcd_data;
1561 if (link->is_dds && !link->dpcd_sink_ext_caps.bits.oled) {
1562 link->dpcd_sink_ext_caps.raw = 0;
1563 return false;
1564 }
1565
1566 if (core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, &edp_general_cap2, 1) != DC_OK)
1567 return false;
1568
1569 link->dpcd_caps.panel_luminance_control = (edp_general_cap2 & DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) != 0;
1570
1571 return true;
1572 }
1573
dp_retrieve_lttpr_cap(struct dc_link * link)1574 enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
1575 {
1576 uint8_t lttpr_dpcd_data[10] = {0};
1577 enum dc_status status;
1578 bool is_lttpr_present;
1579 uint32_t lttpr_count;
1580 uint32_t closest_lttpr_offset;
1581
1582 /* Logic to determine LTTPR support*/
1583 bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
1584
1585 if (!vbios_lttpr_interop || !link->dc->caps.extended_aux_timeout_support)
1586 return DC_NOT_SUPPORTED;
1587
1588 /* By reading LTTPR capability, RX assumes that we will enable
1589 * LTTPR extended aux timeout if LTTPR is present.
1590 */
1591 status = core_link_read_dpcd(
1592 link,
1593 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
1594 lttpr_dpcd_data,
1595 sizeof(lttpr_dpcd_data));
1596
1597 link->dpcd_caps.lttpr_caps.revision.raw =
1598 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
1599 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1600
1601 link->dpcd_caps.lttpr_caps.max_link_rate =
1602 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
1603 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1604
1605 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
1606 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
1607 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1608
1609 link->dpcd_caps.lttpr_caps.max_lane_count =
1610 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
1611 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1612
1613 link->dpcd_caps.lttpr_caps.mode =
1614 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
1615 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1616
1617 link->dpcd_caps.lttpr_caps.max_ext_timeout =
1618 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
1619 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1620 link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw =
1621 lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
1622 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1623
1624 link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
1625 lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
1626 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1627
1628 link->dpcd_caps.lttpr_caps.alpm.raw =
1629 lttpr_dpcd_data[DP_LTTPR_ALPM_CAPABILITIES -
1630 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1631
1632 lttpr_count = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1633
1634 /* If this chip cap is set, at least one retimer must exist in the chain
1635 * Override count to 1 if we receive a known bad count (0 or an invalid value) */
1636 if (((link->chip_caps & AMD_EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK) == AMD_EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
1637 lttpr_count == 0) {
1638 /* If you see this message consistently, either the host platform has FIXED_VS flag
1639 * incorrectly configured or the sink device is returning an invalid count.
1640 */
1641 DC_LOG_ERROR("lttpr_caps phy_repeater_cnt is 0x%x, forcing it to 0x80.",
1642 link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1643 link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80;
1644 lttpr_count = 1;
1645 DC_LOG_DC("lttpr_caps forced phy_repeater_cnt = %d\n", link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1646 }
1647
1648 is_lttpr_present = dp_is_lttpr_present(link);
1649
1650 DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present);
1651
1652 if (is_lttpr_present) {
1653 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
1654
1655 // Identify closest LTTPR to determine if workarounds required for known embedded LTTPR
1656 closest_lttpr_offset = dp_get_closest_lttpr_offset(lttpr_count);
1657
1658 core_link_read_dpcd(link, (DP_LTTPR_IEEE_OUI + closest_lttpr_offset),
1659 link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui));
1660 core_link_read_dpcd(link, (DP_LTTPR_DEVICE_ID + closest_lttpr_offset),
1661 link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id));
1662
1663 if (lttpr_count > 1) {
1664 CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui),
1665 "Closest LTTPR To Host's IEEE OUI: ");
1666 CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id),
1667 "Closest LTTPR To Host's LTTPR Device ID: ");
1668 } else {
1669 CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui),
1670 "LTTPR IEEE OUI: ");
1671 CONN_DATA_DETECT(link, link->dpcd_caps.lttpr_caps.lttpr_device_id, sizeof(link->dpcd_caps.lttpr_caps.lttpr_device_id),
1672 "LTTPR Device ID: ");
1673 }
1674 }
1675
1676 return status;
1677 }
1678
retrieve_link_cap(struct dc_link * link)1679 static bool retrieve_link_cap(struct dc_link *link)
1680 {
1681 /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
1682 * which means size 16 will be good for both of those DPCD register block reads
1683 */
1684 uint8_t dpcd_data[16];
1685 /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
1686 */
1687 uint8_t dpcd_dprx_data = '\0';
1688
1689 struct dp_device_vendor_id sink_id;
1690 union down_stream_port_count down_strm_port_count;
1691 union edp_configuration_cap edp_config_cap;
1692 union dp_downstream_port_present ds_port = { 0 };
1693 enum dc_status status = DC_ERROR_UNEXPECTED;
1694 uint32_t read_dpcd_retry_cnt = 3;
1695 int i;
1696 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
1697 const uint32_t post_oui_delay = 30; // 30ms
1698 bool is_fec_supported = false;
1699 bool is_dsc_basic_supported = false;
1700 bool is_dsc_passthrough_supported = false;
1701
1702 memset(dpcd_data, '\0', sizeof(dpcd_data));
1703 memset(&down_strm_port_count,
1704 '\0', sizeof(union down_stream_port_count));
1705 memset(&edp_config_cap, '\0',
1706 sizeof(union edp_configuration_cap));
1707
1708 /* if extended timeout is supported in hardware,
1709 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
1710 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
1711 */
1712 try_to_configure_aux_timeout(link->ddc,
1713 LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
1714
1715 status = dp_retrieve_lttpr_cap(link);
1716
1717 if (status != DC_OK) {
1718 status = wake_up_aux_channel(link);
1719 if (status == DC_OK)
1720 dp_retrieve_lttpr_cap(link);
1721 else
1722 return false;
1723 }
1724
1725 if (dp_is_lttpr_present(link)) {
1726 configure_lttpr_mode_transparent(link);
1727
1728 // Echo TOTAL_LTTPR_CNT back downstream
1729 core_link_write_dpcd(
1730 link,
1731 DP_TOTAL_LTTPR_CNT,
1732 &link->dpcd_caps.lttpr_caps.phy_repeater_cnt,
1733 sizeof(link->dpcd_caps.lttpr_caps.phy_repeater_cnt));
1734 }
1735
1736 dpcd_set_source_specific_data(link);
1737 /* Sink may need to configure internals based on vendor, so allow some
1738 * time before proceeding with possibly vendor specific transactions
1739 */
1740 msleep(post_oui_delay);
1741
1742 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1743 status = core_link_read_dpcd(
1744 link,
1745 DP_DPCD_REV,
1746 dpcd_data,
1747 sizeof(dpcd_data));
1748 if (status == DC_OK)
1749 break;
1750 }
1751
1752
1753 if (status != DC_OK) {
1754 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
1755 return false;
1756 }
1757
1758 if (!dp_is_lttpr_present(link))
1759 try_to_configure_aux_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
1760
1761
1762 {
1763 union training_aux_rd_interval aux_rd_interval;
1764
1765 aux_rd_interval.raw =
1766 dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
1767
1768 link->dpcd_caps.ext_receiver_cap_field_present =
1769 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
1770
1771 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
1772 uint8_t ext_cap_data[16];
1773
1774 memset(ext_cap_data, '\0', sizeof(ext_cap_data));
1775 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1776 status = core_link_read_dpcd(
1777 link,
1778 DP_DP13_DPCD_REV,
1779 ext_cap_data,
1780 sizeof(ext_cap_data));
1781 if (status == DC_OK) {
1782 memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
1783 break;
1784 }
1785 }
1786 if (status != DC_OK)
1787 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
1788 }
1789 }
1790
1791 link->dpcd_caps.dpcd_rev.raw =
1792 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1793
1794 if (link->dpcd_caps.ext_receiver_cap_field_present) {
1795 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1796 status = core_link_read_dpcd(
1797 link,
1798 DP_DPRX_FEATURE_ENUMERATION_LIST,
1799 &dpcd_dprx_data,
1800 sizeof(dpcd_dprx_data));
1801 if (status == DC_OK)
1802 break;
1803 }
1804
1805 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
1806
1807 if (status != DC_OK)
1808 dm_error("%s: Read DPRX feature list failed.\n", __func__);
1809
1810 /* AdaptiveSyncCapability */
1811 dpcd_dprx_data = 0;
1812 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1813 status = core_link_read_dpcd(
1814 link, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
1815 &dpcd_dprx_data, sizeof(dpcd_dprx_data));
1816 if (status == DC_OK)
1817 break;
1818 }
1819
1820 link->dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.raw = dpcd_dprx_data;
1821
1822 if (status != DC_OK)
1823 dm_error("%s: Read DPRX feature list_1 failed. Addr:%#x\n",
1824 __func__, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1);
1825 }
1826 else {
1827 link->dpcd_caps.dprx_feature.raw = 0;
1828 }
1829
1830 /* Error condition checking...
1831 * It is impossible for Sink to report Max Lane Count = 0.
1832 * It is possible for Sink to report Max Link Rate = 0, if it is
1833 * an eDP device that is reporting specialized link rates in the
1834 * SUPPORTED_LINK_RATE table.
1835 */
1836 if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1837 return false;
1838
1839 ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1840 DP_DPCD_REV];
1841
1842 read_dp_device_vendor_id(link);
1843
1844 /* TODO - decouple raw mst capability from policy decision */
1845 link->dpcd_caps.is_mst_capable = read_is_mst_supported(link);
1846 DC_LOG_DC("%s: MST_Support: %s\n", __func__, str_yes_no(link->dpcd_caps.is_mst_capable));
1847
1848 get_active_converter_info(ds_port.byte, link);
1849
1850 dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
1851
1852 down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1853 DP_DPCD_REV];
1854
1855 link->dpcd_caps.allow_invalid_MSA_timing_param =
1856 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1857
1858 link->dpcd_caps.max_ln_count.raw = dpcd_data[
1859 DP_MAX_LANE_COUNT - DP_DPCD_REV];
1860
1861 link->dpcd_caps.max_down_spread.raw = dpcd_data[
1862 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1863
1864 link->reported_link_cap.lane_count =
1865 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1866 link->reported_link_cap.link_rate = get_link_rate_from_max_link_bw(
1867 dpcd_data[DP_MAX_LINK_RATE - DP_DPCD_REV]);
1868 link->reported_link_cap.link_spread =
1869 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1870 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1871
1872 edp_config_cap.raw = dpcd_data[
1873 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1874 link->dpcd_caps.panel_mode_edp =
1875 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1876 link->dpcd_caps.dpcd_display_control_capable =
1877 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1878 link->dpcd_caps.channel_coding_cap.raw =
1879 dpcd_data[DP_MAIN_LINK_CHANNEL_CODING - DP_DPCD_REV];
1880 link->test_pattern_enabled = false;
1881 link->compliance_test_state.raw = 0;
1882
1883 link->dpcd_caps.receive_port0_cap.raw[0] =
1884 dpcd_data[DP_RECEIVE_PORT_0_CAP_0 - DP_DPCD_REV];
1885 link->dpcd_caps.receive_port0_cap.raw[1] =
1886 dpcd_data[DP_RECEIVE_PORT_0_BUFFER_SIZE - DP_DPCD_REV];
1887
1888 /* read sink count */
1889 core_link_read_dpcd(link,
1890 DP_SINK_COUNT,
1891 &link->dpcd_caps.sink_count.raw,
1892 sizeof(link->dpcd_caps.sink_count.raw));
1893
1894 /* read sink ieee oui */
1895 core_link_read_dpcd(link,
1896 DP_SINK_OUI,
1897 (uint8_t *)(&sink_id),
1898 sizeof(sink_id));
1899
1900 link->dpcd_caps.sink_dev_id =
1901 (sink_id.ieee_oui[0] << 16) +
1902 (sink_id.ieee_oui[1] << 8) +
1903 (sink_id.ieee_oui[2]);
1904
1905 memmove(
1906 link->dpcd_caps.sink_dev_id_str,
1907 sink_id.ieee_device_id,
1908 sizeof(sink_id.ieee_device_id));
1909
1910 core_link_read_dpcd(
1911 link,
1912 DP_SINK_HW_REVISION_START,
1913 (uint8_t *)&dp_hw_fw_revision,
1914 sizeof(dp_hw_fw_revision));
1915
1916 link->dpcd_caps.sink_hw_revision =
1917 dp_hw_fw_revision.ieee_hw_rev;
1918
1919 memmove(
1920 link->dpcd_caps.sink_fw_revision,
1921 dp_hw_fw_revision.ieee_fw_rev,
1922 sizeof(dp_hw_fw_revision.ieee_fw_rev));
1923
1924 /* Quirk for Retina panels: wrong DP_MAX_LINK_RATE */
1925 {
1926 uint8_t str_mbp_2018[] = { 101, 68, 21, 103, 98, 97 };
1927 uint8_t fwrev_mbp_2018[] = { 7, 4 };
1928 uint8_t fwrev_mbp_2018_vega[] = { 8, 4 };
1929
1930 /* We also check for the firmware revision as 16,1 models have an
1931 * identical device id and are incorrectly quirked otherwise.
1932 */
1933 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
1934 !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2018,
1935 sizeof(str_mbp_2018)) &&
1936 (!memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018,
1937 sizeof(fwrev_mbp_2018)) ||
1938 !memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018_vega,
1939 sizeof(fwrev_mbp_2018_vega)))) {
1940 link->reported_link_cap.link_rate = LINK_RATE_RBR2;
1941 }
1942 }
1943
1944 memset(&link->dpcd_caps.dsc_caps, '\0',
1945 sizeof(link->dpcd_caps.dsc_caps));
1946 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
1947 /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
1948 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
1949 status = core_link_read_dpcd(
1950 link,
1951 DP_FEC_CAPABILITY,
1952 &link->dpcd_caps.fec_cap.raw,
1953 sizeof(link->dpcd_caps.fec_cap.raw));
1954 if (status != DC_OK)
1955 DC_LOG_ERROR("%s:%d: core_link_read_dpcd (DP_FEC_CAPABILITY) failed\n", __func__, __LINE__);
1956
1957 status = core_link_read_dpcd(
1958 link,
1959 DP_DSC_SUPPORT,
1960 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
1961 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
1962 if (status == DC_OK) {
1963 is_fec_supported = link->dpcd_caps.fec_cap.bits.FEC_CAPABLE;
1964 is_dsc_basic_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT;
1965 is_dsc_passthrough_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT;
1966 DC_LOG_DC("%s: FEC_Sink_Support: %s\n", __func__,
1967 str_yes_no(is_fec_supported));
1968 DC_LOG_DC("%s: DSC_Basic_Sink_Support: %s\n", __func__,
1969 str_yes_no(is_dsc_basic_supported));
1970 DC_LOG_DC("%s: DSC_Passthrough_Sink_Support: %s\n", __func__,
1971 str_yes_no(is_dsc_passthrough_supported));
1972 }
1973 if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1974 status = core_link_read_dpcd(
1975 link,
1976 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
1977 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
1978 sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
1979 if (status != DC_OK)
1980 DC_LOG_ERROR("%s:%d: core_link_read_dpcd (DP_DSC_BRANCH_OVERALL_THROUGHPUT_0) failed\n", __func__, __LINE__);
1981
1982 DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index);
1983 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x",
1984 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_0);
1985 DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_1 = 0x%02x",
1986 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_1);
1987 DC_LOG_DSC("\tBRANCH_MAX_LINE_WIDTH 0x%02x",
1988 link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_MAX_LINE_WIDTH);
1989 }
1990
1991 /* Apply work around to disable FEC and DSC for USB4 tunneling in TBT3 compatibility mode
1992 * only if required.
1993 */
1994 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
1995 link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around &&
1996 link->dpcd_caps.is_branch_dev &&
1997 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
1998 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&
1999 (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE ||
2000 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)) {
2001 /* A TBT3 device is expected to report no support for FEC or DSC to a USB4 DPIA.
2002 * Clear FEC and DSC capabilities as a work around if that is not the case.
2003 */
2004 link->wa_flags.dpia_forced_tbt3_mode = true;
2005 memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps));
2006 memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
2007 DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index);
2008 } else
2009 link->wa_flags.dpia_forced_tbt3_mode = false;
2010 }
2011
2012 if (!dpcd_read_sink_ext_caps(link))
2013 link->dpcd_sink_ext_caps.raw = 0;
2014
2015 if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
2016 DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index);
2017
2018 /* Read 128b/132b suppoerted link rates */
2019 core_link_read_dpcd(link,
2020 DP_128B132B_SUPPORTED_LINK_RATES,
2021 &link->dpcd_caps.dp_128b_132b_supported_link_rates.raw,
2022 sizeof(link->dpcd_caps.dp_128b_132b_supported_link_rates.raw));
2023 if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR20)
2024 link->reported_link_cap.link_rate = LINK_RATE_UHBR20;
2025 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)
2026 link->reported_link_cap.link_rate = LINK_RATE_UHBR13_5;
2027 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR10)
2028 link->reported_link_cap.link_rate = LINK_RATE_UHBR10;
2029 else
2030 dm_error("%s: Invalid RX 128b_132b_supported_link_rates\n", __func__);
2031 DC_LOG_DP2("128b/132b supported link rates is read at link %d", link->link_index);
2032 DC_LOG_DP2("\tmax 128b/132b link rate support is %d.%d GHz",
2033 link->reported_link_cap.link_rate / 100,
2034 link->reported_link_cap.link_rate % 100);
2035
2036 core_link_read_dpcd(link,
2037 DP_SINK_VIDEO_FALLBACK_FORMATS,
2038 &link->dpcd_caps.fallback_formats.raw,
2039 sizeof(link->dpcd_caps.fallback_formats.raw));
2040 DC_LOG_DP2("sink video fallback format is read at link %d", link->link_index);
2041 if (link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support)
2042 DC_LOG_DP2("\t1920x1080@60Hz 24bpp fallback format supported");
2043 if (link->dpcd_caps.fallback_formats.bits.dp_1280x720_60Hz_24bpp_support)
2044 DC_LOG_DP2("\t1280x720@60Hz 24bpp fallback format supported");
2045 if (link->dpcd_caps.fallback_formats.bits.dp_1024x768_60Hz_24bpp_support)
2046 DC_LOG_DP2("\t1024x768@60Hz 24bpp fallback format supported");
2047 if (link->dpcd_caps.fallback_formats.raw == 0) {
2048 DC_LOG_DP2("\tno supported fallback formats, assume 1920x1080@60Hz 24bpp is supported");
2049 link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support = 1;
2050 }
2051
2052 core_link_read_dpcd(link,
2053 DP_FEC_CAPABILITY_1,
2054 &link->dpcd_caps.fec_cap1.raw,
2055 sizeof(link->dpcd_caps.fec_cap1.raw));
2056 DC_LOG_DP2("FEC CAPABILITY 1 is read at link %d", link->link_index);
2057 if (link->dpcd_caps.fec_cap1.bits.AGGREGATED_ERROR_COUNTERS_CAPABLE)
2058 DC_LOG_DP2("\tFEC aggregated error counters are supported");
2059 }
2060
2061 core_link_read_dpcd(link,
2062 DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP,
2063 link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw,
2064 sizeof(link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw));
2065
2066 /* Read DP tunneling information. */
2067 status = dpcd_get_tunneling_device_data(link);
2068 if (status != DC_OK)
2069 DC_LOG_DP2("%s: Read DP tunneling device data failed.\n", __func__);
2070
2071 retrieve_cable_id(link);
2072 dpcd_write_cable_id_to_dprx(link);
2073
2074 /* Connectivity log: detection */
2075 CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
2076
2077 return true;
2078 }
2079
detect_dp_sink_caps(struct dc_link * link)2080 bool detect_dp_sink_caps(struct dc_link *link)
2081 {
2082 return retrieve_link_cap(link);
2083 }
2084
detect_edp_sink_caps(struct dc_link * link)2085 void detect_edp_sink_caps(struct dc_link *link)
2086 {
2087 uint8_t supported_link_rates[16];
2088 uint32_t entry;
2089 uint32_t link_rate_in_khz;
2090 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
2091 uint8_t backlight_adj_cap = 0;
2092 uint8_t general_edp_cap = 0;
2093
2094 retrieve_link_cap(link);
2095 link->dpcd_caps.edp_supported_link_rates_count = 0;
2096 memset(supported_link_rates, 0, sizeof(supported_link_rates));
2097
2098 /*
2099 * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
2100 * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
2101 */
2102 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13) {
2103 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
2104 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
2105 supported_link_rates, sizeof(supported_link_rates));
2106
2107 for (entry = 0; entry < 16; entry += 2) {
2108 // DPCD register reports per-lane link rate = 16-bit link rate capability
2109 // value X 200 kHz. Need multiplier to find link rate in kHz.
2110 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
2111 supported_link_rates[entry]) * 200;
2112
2113 DC_LOG_DC("%s: eDP v1.4 supported sink rates: [%d] %d kHz\n", __func__,
2114 entry / 2, link_rate_in_khz);
2115
2116 if (link_rate_in_khz != 0) {
2117 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
2118 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
2119 link->dpcd_caps.edp_supported_link_rates_count++;
2120 }
2121 }
2122 }
2123
2124 core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
2125 &backlight_adj_cap, sizeof(backlight_adj_cap));
2126
2127 link->dpcd_caps.dynamic_backlight_capable_edp =
2128 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
2129
2130 core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1,
2131 &general_edp_cap, sizeof(general_edp_cap));
2132
2133 link->dpcd_caps.set_power_state_capable_edp =
2134 (general_edp_cap & DP_EDP_SET_POWER_CAP) ? true:false;
2135
2136 set_default_brightness_aux(link);
2137
2138 core_link_read_dpcd(link, DP_EDP_DPCD_REV,
2139 &link->dpcd_caps.edp_rev,
2140 sizeof(link->dpcd_caps.edp_rev));
2141 /*
2142 * PSR is only valid for eDP v1.3 or higher.
2143 */
2144 if (link->dpcd_caps.edp_rev >= DP_EDP_13) {
2145 core_link_read_dpcd(link, DP_PSR_SUPPORT,
2146 &link->dpcd_caps.psr_info.psr_version,
2147 sizeof(link->dpcd_caps.psr_info.psr_version));
2148 if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
2149 core_link_read_dpcd(link, DP_FORCE_PSRSU_CAPABILITY,
2150 &link->dpcd_caps.psr_info.force_psrsu_cap,
2151 sizeof(link->dpcd_caps.psr_info.force_psrsu_cap));
2152 core_link_read_dpcd(link, DP_PSR_CAPS,
2153 &link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
2154 sizeof(link->dpcd_caps.psr_info.psr_dpcd_caps.raw));
2155 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) {
2156 core_link_read_dpcd(link, DP_PSR2_SU_Y_GRANULARITY,
2157 &link->dpcd_caps.psr_info.psr2_su_y_granularity_cap,
2158 sizeof(link->dpcd_caps.psr_info.psr2_su_y_granularity_cap));
2159 }
2160 }
2161
2162 /*
2163 * ALPM is only valid for eDP v1.4 or higher.
2164 */
2165 if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14)
2166 core_link_read_dpcd(link, DP_RECEIVER_ALPM_CAP,
2167 &link->dpcd_caps.alpm_caps.raw,
2168 sizeof(link->dpcd_caps.alpm_caps.raw));
2169
2170 /*
2171 * Read REPLAY info
2172 */
2173 core_link_read_dpcd(link, DP_SINK_PR_PIXEL_DEVIATION_PER_LINE,
2174 &link->dpcd_caps.pr_info.pixel_deviation_per_line,
2175 sizeof(link->dpcd_caps.pr_info.pixel_deviation_per_line));
2176 core_link_read_dpcd(link, DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE,
2177 &link->dpcd_caps.pr_info.max_deviation_line,
2178 sizeof(link->dpcd_caps.pr_info.max_deviation_line));
2179
2180 /*
2181 * OLED Emission Rate info
2182 */
2183 if (link->dpcd_sink_ext_caps.bits.emission_output)
2184 core_link_read_dpcd(link, DP_SINK_EMISSION_RATE,
2185 (uint8_t *)&link->dpcd_caps.edp_oled_emission_rate,
2186 sizeof(link->dpcd_caps.edp_oled_emission_rate));
2187
2188 /*
2189 * Read Multi-SST (Single Stream Transport) capability
2190 * for eDP version 1.4 or higher.
2191 */
2192 if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14)
2193 core_link_read_dpcd(
2194 link,
2195 DP_EDP_MSO_LINK_CAPABILITIES,
2196 (uint8_t *)&link->dpcd_caps.mso_cap_sst_links_supported,
2197 sizeof(link->dpcd_caps.mso_cap_sst_links_supported));
2198 }
2199
dp_get_max_link_enc_cap(const struct dc_link * link,struct dc_link_settings * max_link_enc_cap)2200 bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2201 {
2202 struct resource_context *res_ctx = &link->dc->current_state->res_ctx;
2203 struct resource_pool *res_pool = link->dc->res_pool;
2204 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link);
2205
2206 if (!max_link_enc_cap) {
2207 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2208 return false;
2209 }
2210
2211 if (!link->dc->config.unify_link_enc_assignment)
2212 link_enc = link_enc_cfg_get_link_enc(link);
2213 ASSERT(link_enc);
2214
2215 if (link_enc && link_enc->funcs->get_max_link_cap) {
2216 link_enc->funcs->get_max_link_cap(link_enc, max_link_enc_cap);
2217 return true;
2218 }
2219
2220 DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2221 max_link_enc_cap->lane_count = 1;
2222 max_link_enc_cap->link_rate = 6;
2223 return false;
2224 }
2225
dp_get_verified_link_cap(const struct dc_link * link)2226 const struct dc_link_settings *dp_get_verified_link_cap(
2227 const struct dc_link *link)
2228 {
2229 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
2230 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
2231 return &link->preferred_link_setting;
2232 return &link->verified_link_cap;
2233 }
2234
dp_get_max_link_cap(struct dc_link * link)2235 struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)
2236 {
2237 struct dc_link_settings max_link_cap = {0};
2238 enum dc_link_rate lttpr_max_link_rate;
2239 enum dc_link_rate cable_max_link_rate;
2240 struct resource_context *res_ctx = &link->dc->current_state->res_ctx;
2241 struct resource_pool *res_pool = link->dc->res_pool;
2242 struct link_encoder *link_enc = get_temp_dio_link_enc(res_ctx, res_pool, link);
2243 bool is_uhbr13_5_supported = true;
2244
2245 if (!link->dc->config.unify_link_enc_assignment)
2246 link_enc = link_enc_cfg_get_link_enc(link);
2247 ASSERT(link_enc);
2248
2249 /* get max link encoder capability */
2250 if (link_enc)
2251 link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap);
2252
2253 /* Lower link settings based on sink's link cap */
2254 if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2255 max_link_cap.lane_count =
2256 link->reported_link_cap.lane_count;
2257 if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2258 max_link_cap.link_rate =
2259 link->reported_link_cap.link_rate;
2260 if (link->reported_link_cap.link_spread <
2261 max_link_cap.link_spread)
2262 max_link_cap.link_spread =
2263 link->reported_link_cap.link_spread;
2264
2265 if (!link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)
2266 is_uhbr13_5_supported = false;
2267
2268 /* Lower link settings based on cable attributes
2269 * Cable ID is a DP2 feature to identify max certified link rate that
2270 * a cable can carry. The cable identification method requires both
2271 * cable and display hardware support. Since the specs comes late, it is
2272 * anticipated that the first round of DP2 cables and displays may not
2273 * be fully compatible to reliably return cable ID data. Therefore the
2274 * decision of our cable id policy is that if the cable can return non
2275 * zero cable id data, we will take cable's link rate capability into
2276 * account. However if we get zero data, the cable link rate capability
2277 * is considered inconclusive. In this case, we will not take cable's
2278 * capability into account to avoid of over limiting hardware capability
2279 * from users. The max overall link rate capability is still determined
2280 * after actual dp pre-training. Cable id is considered as an auxiliary
2281 * method of determining max link bandwidth capability.
2282 */
2283 cable_max_link_rate = get_cable_max_link_rate(link);
2284
2285 if (!link->dc->debug.ignore_cable_id &&
2286 cable_max_link_rate != LINK_RATE_UNKNOWN) {
2287 if (cable_max_link_rate < max_link_cap.link_rate)
2288 max_link_cap.link_rate = cable_max_link_rate;
2289
2290 if (!link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY &&
2291 link->dpcd_caps.cable_id.bits.CABLE_TYPE >= 2)
2292 is_uhbr13_5_supported = false;
2293 }
2294
2295 /* account for lttpr repeaters cap
2296 * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2297 */
2298 if (dp_is_lttpr_present(link)) {
2299
2300 /* Some LTTPR devices do not report valid DPCD revisions, if so, do not take it's link cap into consideration. */
2301 if (link->dpcd_caps.lttpr_caps.revision.raw >= DPCD_REV_14) {
2302 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2303 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2304 lttpr_max_link_rate = get_lttpr_max_link_rate(link);
2305
2306 if (lttpr_max_link_rate < max_link_cap.link_rate)
2307 max_link_cap.link_rate = lttpr_max_link_rate;
2308
2309 if (!link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
2310 is_uhbr13_5_supported = false;
2311 }
2312
2313 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR, max_lane count %d max_link rate %d \n",
2314 __func__,
2315 max_link_cap.lane_count,
2316 max_link_cap.link_rate);
2317 }
2318
2319 if (max_link_cap.link_rate == LINK_RATE_UHBR13_5 &&
2320 !is_uhbr13_5_supported)
2321 max_link_cap.link_rate = LINK_RATE_UHBR10;
2322
2323 if (link_dp_get_encoding_format(&max_link_cap) == DP_128b_132b_ENCODING &&
2324 link->dc->debug.disable_uhbr)
2325 max_link_cap.link_rate = LINK_RATE_HIGH3;
2326
2327 return max_link_cap;
2328 }
2329
dp_verify_link_cap(struct dc_link * link,struct dc_link_settings * known_limit_link_setting,int * fail_count)2330 static bool dp_verify_link_cap(
2331 struct dc_link *link,
2332 struct dc_link_settings *known_limit_link_setting,
2333 int *fail_count)
2334 {
2335 struct dc_link_settings cur_link_settings = {0};
2336 struct dc_link_settings max_link_settings = *known_limit_link_setting;
2337 bool success = false;
2338 bool skip_video_pattern;
2339 enum clock_source_id dp_cs_id = get_clock_source_id(link);
2340 enum link_training_result status = LINK_TRAINING_SUCCESS;
2341 union hpd_irq_data irq_data;
2342 struct link_resource link_res;
2343
2344 memset(&irq_data, 0, sizeof(irq_data));
2345 cur_link_settings = max_link_settings;
2346
2347 /* Grant extended timeout request */
2348 if (dp_is_lttpr_present(link) && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
2349 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2350
2351 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2352 }
2353
2354 do {
2355 if (!get_temp_dp_link_res(link, &link_res, &cur_link_settings))
2356 continue;
2357
2358 skip_video_pattern = cur_link_settings.link_rate != LINK_RATE_LOW;
2359 dp_enable_link_phy(
2360 link,
2361 &link_res,
2362 link->connector_signal,
2363 dp_cs_id,
2364 &cur_link_settings);
2365
2366 status = dp_perform_link_training(
2367 link,
2368 &link_res,
2369 &cur_link_settings,
2370 skip_video_pattern);
2371
2372 if (status == LINK_TRAINING_SUCCESS) {
2373 success = true;
2374 fsleep(1000);
2375 if (dp_read_hpd_rx_irq_data(link, &irq_data) == DC_OK &&
2376 dp_parse_link_loss_status(
2377 link,
2378 &irq_data))
2379 (*fail_count)++;
2380 } else if (status == LINK_TRAINING_LINK_LOSS) {
2381 success = true;
2382 (*fail_count)++;
2383 } else {
2384 (*fail_count)++;
2385 }
2386 dp_trace_lt_total_count_increment(link, true);
2387 dp_trace_lt_result_update(link, status, true);
2388 dp_disable_link_phy(link, &link_res, link->connector_signal);
2389 } while (!success && decide_fallback_link_setting(link,
2390 &max_link_settings, &cur_link_settings, status));
2391
2392 link->verified_link_cap = success ?
2393 cur_link_settings : fail_safe_link_settings;
2394 return success;
2395 }
2396
dp_verify_link_cap_with_retries(struct dc_link * link,struct dc_link_settings * known_limit_link_setting,int attempts)2397 bool dp_verify_link_cap_with_retries(
2398 struct dc_link *link,
2399 struct dc_link_settings *known_limit_link_setting,
2400 int attempts)
2401 {
2402 int i = 0;
2403 bool success = false;
2404 int fail_count = 0;
2405 struct dc_link_settings last_verified_link_cap = fail_safe_link_settings;
2406
2407 dp_trace_detect_lt_init(link);
2408
2409 if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C &&
2410 link->dc->debug.usbc_combo_phy_reset_wa)
2411 apply_usbc_combo_phy_reset_wa(link, known_limit_link_setting);
2412
2413 dp_trace_set_lt_start_timestamp(link, false);
2414 for (i = 0; i < attempts; i++) {
2415 enum dc_connection_type type = dc_connection_none;
2416
2417 memset(&link->verified_link_cap, 0,
2418 sizeof(struct dc_link_settings));
2419 if (link->link_enc && (!link_detect_connection_type(link, &type) || type == dc_connection_none)) {
2420 link->verified_link_cap = fail_safe_link_settings;
2421 break;
2422 } else if (dp_verify_link_cap(link, known_limit_link_setting, &fail_count)) {
2423 last_verified_link_cap = link->verified_link_cap;
2424 if (fail_count == 0) {
2425 success = true;
2426 break;
2427 }
2428 } else {
2429 link->verified_link_cap = last_verified_link_cap;
2430 }
2431
2432 /* For Dp tunneling link, a pending HPD means that we have a race condition between processing
2433 * current link and processing the pending HPD. Since the training is failed, we should just brak
2434 * the loop so that we have chance to process the pending HPD.
2435 */
2436 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->is_hpd_pending)
2437 break;
2438
2439 fsleep(10 * 1000);
2440 }
2441
2442 dp_trace_lt_fail_count_update(link, fail_count, true);
2443 dp_trace_set_lt_end_timestamp(link, true);
2444
2445 return success;
2446 }
2447
2448 /*
2449 * Check if there is a native DP or passive DP-HDMI dongle connected
2450 */
dp_is_sink_present(struct dc_link * link)2451 bool dp_is_sink_present(struct dc_link *link)
2452 {
2453 enum gpio_result gpio_result;
2454 uint32_t clock_pin = 0;
2455 uint8_t retry = 0;
2456 struct ddc *ddc;
2457
2458 enum connector_id connector_id =
2459 dal_graphics_object_id_get_connector_id(link->link_id);
2460
2461 bool present =
2462 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
2463 (connector_id == CONNECTOR_ID_EDP) ||
2464 (connector_id == CONNECTOR_ID_USBC));
2465
2466 ddc = get_ddc_pin(link->ddc);
2467
2468 if (!ddc) {
2469 BREAK_TO_DEBUGGER();
2470 return present;
2471 }
2472
2473 /* Open GPIO and set it to I2C mode */
2474 /* Note: this GpioMode_Input will be converted
2475 * to GpioConfigType_I2cAuxDualMode in GPIO component,
2476 * which indicates we need additional delay
2477 */
2478
2479 if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
2480 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
2481 dal_ddc_close(ddc);
2482
2483 return present;
2484 }
2485
2486 /*
2487 * Read GPIO: DP sink is present if both clock and data pins are zero
2488 *
2489 * [W/A] plug-unplug DP cable, sometimes customer board has
2490 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
2491 * then monitor can't br light up. Add retry 3 times
2492 * But in real passive dongle, it need additional 3ms to detect
2493 */
2494 do {
2495 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
2496 ASSERT(gpio_result == GPIO_RESULT_OK);
2497 if (clock_pin)
2498 fsleep(1000);
2499 else
2500 break;
2501 } while (retry++ < 3);
2502
2503 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
2504
2505 dal_ddc_close(ddc);
2506
2507 return present;
2508 }
2509