1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <linux/pci.h>
28
29 #include <drm/drm_device.h>
30 #include <drm/drm_edid.h>
31 #include <drm/radeon_drm.h>
32
33 #include "radeon.h"
34
35 #include "atom.h"
36 #include "atom-bits.h"
37 #include "radeon_asic.h"
38 #include "radeon_atombios.h"
39 #include "radeon_legacy_encoders.h"
40
41 union atom_supported_devices {
42 struct _ATOM_SUPPORTED_DEVICES_INFO info;
43 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
44 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
45 };
46
radeon_lookup_i2c_gpio_quirks(struct radeon_device * rdev,ATOM_GPIO_I2C_ASSIGMENT * gpio,u8 index)47 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
48 ATOM_GPIO_I2C_ASSIGMENT *gpio,
49 u8 index)
50 {
51 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
52 if ((rdev->family == CHIP_R420) ||
53 (rdev->family == CHIP_R423) ||
54 (rdev->family == CHIP_RV410)) {
55 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
58 gpio->ucClkMaskShift = 0x19;
59 gpio->ucDataMaskShift = 0x18;
60 }
61 }
62
63 /* some evergreen boards have bad data for this entry */
64 if (ASIC_IS_DCE4(rdev)) {
65 if ((index == 7) &&
66 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
67 (gpio->sucI2cId.ucAccess == 0)) {
68 gpio->sucI2cId.ucAccess = 0x97;
69 gpio->ucDataMaskShift = 8;
70 gpio->ucDataEnShift = 8;
71 gpio->ucDataY_Shift = 8;
72 gpio->ucDataA_Shift = 8;
73 }
74 }
75
76 /* some DCE3 boards have bad data for this entry */
77 if (ASIC_IS_DCE3(rdev)) {
78 if ((index == 4) &&
79 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
80 (gpio->sucI2cId.ucAccess == 0x94))
81 gpio->sucI2cId.ucAccess = 0x14;
82 }
83 }
84
radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT * gpio)85 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
86 {
87 struct radeon_i2c_bus_rec i2c;
88
89 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
90
91 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
92 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
93 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
94 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
95 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
96 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
97 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
98 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
99 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
100 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
101 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
102 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
103 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
104 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
105 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
106 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
107
108 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
109 i2c.hw_capable = true;
110 else
111 i2c.hw_capable = false;
112
113 if (gpio->sucI2cId.ucAccess == 0xa0)
114 i2c.mm_i2c = true;
115 else
116 i2c.mm_i2c = false;
117
118 i2c.i2c_id = gpio->sucI2cId.ucAccess;
119
120 if (i2c.mask_clk_reg)
121 i2c.valid = true;
122 else
123 i2c.valid = false;
124
125 return i2c;
126 }
127
radeon_lookup_i2c_gpio(struct radeon_device * rdev,uint8_t id)128 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
129 uint8_t id)
130 {
131 struct atom_context *ctx = rdev->mode_info.atom_context;
132 ATOM_GPIO_I2C_ASSIGMENT *gpio;
133 struct radeon_i2c_bus_rec i2c;
134 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
135 struct _ATOM_GPIO_I2C_INFO *i2c_info;
136 uint16_t data_offset, size;
137 int i, num_indices;
138
139 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
140 i2c.valid = false;
141
142 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
143 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
144
145 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
146 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
147
148 gpio = &i2c_info->asGPIO_Info[0];
149 for (i = 0; i < num_indices; i++) {
150
151 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
152
153 if (gpio->sucI2cId.ucAccess == id) {
154 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
155 break;
156 }
157 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
158 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
159 }
160 }
161
162 return i2c;
163 }
164
radeon_atombios_i2c_init(struct radeon_device * rdev)165 void radeon_atombios_i2c_init(struct radeon_device *rdev)
166 {
167 struct atom_context *ctx = rdev->mode_info.atom_context;
168 ATOM_GPIO_I2C_ASSIGMENT *gpio;
169 struct radeon_i2c_bus_rec i2c;
170 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
171 struct _ATOM_GPIO_I2C_INFO *i2c_info;
172 uint16_t data_offset, size;
173 int i, num_indices;
174 char stmp[32];
175
176 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
177 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
178
179 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
180 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
181
182 gpio = &i2c_info->asGPIO_Info[0];
183 for (i = 0; i < num_indices; i++) {
184 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
185
186 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
187
188 if (i2c.valid) {
189 sprintf(stmp, "0x%x", i2c.i2c_id);
190 rdev->i2c_bus[i] = radeon_i2c_create(rdev_to_drm(rdev), &i2c, stmp);
191 }
192 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
193 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
194 }
195 }
196 }
197
radeon_atombios_lookup_gpio(struct radeon_device * rdev,u8 id)198 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
199 u8 id)
200 {
201 struct atom_context *ctx = rdev->mode_info.atom_context;
202 struct radeon_gpio_rec gpio;
203 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
204 struct _ATOM_GPIO_PIN_LUT *gpio_info;
205 ATOM_GPIO_PIN_ASSIGNMENT *pin;
206 u16 data_offset, size;
207 int i, num_indices;
208
209 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
210 gpio.valid = false;
211
212 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
213 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
214
215 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
216 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
217
218 pin = gpio_info->asGPIO_Pin;
219 for (i = 0; i < num_indices; i++) {
220 if (id == pin->ucGPIO_ID) {
221 gpio.id = pin->ucGPIO_ID;
222 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
223 gpio.shift = pin->ucGpioPinBitShift;
224 gpio.mask = (1 << pin->ucGpioPinBitShift);
225 gpio.valid = true;
226 break;
227 }
228 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
229 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
230 }
231 }
232
233 return gpio;
234 }
235
radeon_atom_get_hpd_info_from_gpio(struct radeon_device * rdev,struct radeon_gpio_rec * gpio)236 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
237 struct radeon_gpio_rec *gpio)
238 {
239 struct radeon_hpd hpd;
240 u32 reg;
241
242 memset(&hpd, 0, sizeof(struct radeon_hpd));
243
244 if (ASIC_IS_DCE6(rdev))
245 reg = SI_DC_GPIO_HPD_A;
246 else if (ASIC_IS_DCE4(rdev))
247 reg = EVERGREEN_DC_GPIO_HPD_A;
248 else
249 reg = AVIVO_DC_GPIO_HPD_A;
250
251 hpd.gpio = *gpio;
252 if (gpio->reg == reg) {
253 switch(gpio->mask) {
254 case (1 << 0):
255 hpd.hpd = RADEON_HPD_1;
256 break;
257 case (1 << 8):
258 hpd.hpd = RADEON_HPD_2;
259 break;
260 case (1 << 16):
261 hpd.hpd = RADEON_HPD_3;
262 break;
263 case (1 << 24):
264 hpd.hpd = RADEON_HPD_4;
265 break;
266 case (1 << 26):
267 hpd.hpd = RADEON_HPD_5;
268 break;
269 case (1 << 28):
270 hpd.hpd = RADEON_HPD_6;
271 break;
272 default:
273 hpd.hpd = RADEON_HPD_NONE;
274 break;
275 }
276 } else
277 hpd.hpd = RADEON_HPD_NONE;
278 return hpd;
279 }
280
radeon_atom_apply_quirks(struct drm_device * dev,uint32_t supported_device,int * connector_type,struct radeon_i2c_bus_rec * i2c_bus,uint16_t * line_mux,struct radeon_hpd * hpd)281 static bool radeon_atom_apply_quirks(struct drm_device *dev,
282 uint32_t supported_device,
283 int *connector_type,
284 struct radeon_i2c_bus_rec *i2c_bus,
285 uint16_t *line_mux,
286 struct radeon_hpd *hpd)
287 {
288 struct pci_dev *pdev = to_pci_dev(dev->dev);
289
290 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
291 if ((pdev->device == 0x791e) &&
292 (pdev->subsystem_vendor == 0x1043) &&
293 (pdev->subsystem_device == 0x826d)) {
294 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
295 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
296 *connector_type = DRM_MODE_CONNECTOR_DVID;
297 }
298
299 /* Asrock RS600 board lists the DVI port as HDMI */
300 if ((pdev->device == 0x7941) &&
301 (pdev->subsystem_vendor == 0x1849) &&
302 (pdev->subsystem_device == 0x7941)) {
303 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
304 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
305 *connector_type = DRM_MODE_CONNECTOR_DVID;
306 }
307
308 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
309 if ((pdev->device == 0x796e) &&
310 (pdev->subsystem_vendor == 0x1462) &&
311 (pdev->subsystem_device == 0x7302)) {
312 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
313 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
314 return false;
315 }
316
317 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
318 if ((pdev->device == 0x7941) &&
319 (pdev->subsystem_vendor == 0x147b) &&
320 (pdev->subsystem_device == 0x2412)) {
321 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
322 return false;
323 }
324
325 /* Falcon NW laptop lists vga ddc line for LVDS */
326 if ((pdev->device == 0x5653) &&
327 (pdev->subsystem_vendor == 0x1462) &&
328 (pdev->subsystem_device == 0x0291)) {
329 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
330 i2c_bus->valid = false;
331 *line_mux = 53;
332 }
333 }
334
335 /* HIS X1300 is DVI+VGA, not DVI+DVI */
336 if ((pdev->device == 0x7146) &&
337 (pdev->subsystem_vendor == 0x17af) &&
338 (pdev->subsystem_device == 0x2058)) {
339 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
340 return false;
341 }
342
343 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
344 if ((pdev->device == 0x7142) &&
345 (pdev->subsystem_vendor == 0x1458) &&
346 (pdev->subsystem_device == 0x2134)) {
347 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
348 return false;
349 }
350
351
352 /* Funky macbooks */
353 if ((pdev->device == 0x71C5) &&
354 (pdev->subsystem_vendor == 0x106b) &&
355 (pdev->subsystem_device == 0x0080)) {
356 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
357 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
358 return false;
359 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
360 *line_mux = 0x90;
361 }
362
363 /* mac rv630, rv730, others */
364 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
365 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
366 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
367 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
368 }
369
370 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
371 if ((pdev->device == 0x9598) &&
372 (pdev->subsystem_vendor == 0x1043) &&
373 (pdev->subsystem_device == 0x01da)) {
374 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
375 *connector_type = DRM_MODE_CONNECTOR_DVII;
376 }
377 }
378
379 /* ASUS HD 3600 board lists the DVI port as HDMI */
380 if ((pdev->device == 0x9598) &&
381 (pdev->subsystem_vendor == 0x1043) &&
382 (pdev->subsystem_device == 0x01e4)) {
383 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
384 *connector_type = DRM_MODE_CONNECTOR_DVII;
385 }
386 }
387
388 /* ASUS HD 3450 board lists the DVI port as HDMI */
389 if ((pdev->device == 0x95C5) &&
390 (pdev->subsystem_vendor == 0x1043) &&
391 (pdev->subsystem_device == 0x01e2)) {
392 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
393 *connector_type = DRM_MODE_CONNECTOR_DVII;
394 }
395 }
396
397 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
398 * HDMI + VGA reporting as HDMI
399 */
400 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
401 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
402 *connector_type = DRM_MODE_CONNECTOR_VGA;
403 *line_mux = 0;
404 }
405 }
406
407 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
408 * on the laptop and a DVI port on the docking station and
409 * both share the same encoder, hpd pin, and ddc line.
410 * So while the bios table is technically correct,
411 * we drop the DVI port here since xrandr has no concept of
412 * encoders and will try and drive both connectors
413 * with different crtcs which isn't possible on the hardware
414 * side and leaves no crtcs for LVDS or VGA.
415 */
416 if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) &&
417 (pdev->subsystem_vendor == 0x1025) &&
418 (pdev->subsystem_device == 0x013c)) {
419 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
420 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
421 /* actually it's a DVI-D port not DVI-I */
422 *connector_type = DRM_MODE_CONNECTOR_DVID;
423 return false;
424 }
425 }
426
427 /* XFX Pine Group device rv730 reports no VGA DDC lines
428 * even though they are wired up to record 0x93
429 */
430 if ((pdev->device == 0x9498) &&
431 (pdev->subsystem_vendor == 0x1682) &&
432 (pdev->subsystem_device == 0x2452) &&
433 (i2c_bus->valid == false) &&
434 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
435 struct radeon_device *rdev = dev->dev_private;
436 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
437 }
438
439 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
440 if (((pdev->device == 0x9802) ||
441 (pdev->device == 0x9805) ||
442 (pdev->device == 0x9806)) &&
443 (pdev->subsystem_vendor == 0x1734) &&
444 (pdev->subsystem_device == 0x11bd)) {
445 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
446 *connector_type = DRM_MODE_CONNECTOR_DVII;
447 *line_mux = 0x3103;
448 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
449 *connector_type = DRM_MODE_CONNECTOR_DVII;
450 }
451 }
452
453 return true;
454 }
455
456 static const int supported_devices_connector_convert[] = {
457 DRM_MODE_CONNECTOR_Unknown,
458 DRM_MODE_CONNECTOR_VGA,
459 DRM_MODE_CONNECTOR_DVII,
460 DRM_MODE_CONNECTOR_DVID,
461 DRM_MODE_CONNECTOR_DVIA,
462 DRM_MODE_CONNECTOR_SVIDEO,
463 DRM_MODE_CONNECTOR_Composite,
464 DRM_MODE_CONNECTOR_LVDS,
465 DRM_MODE_CONNECTOR_Unknown,
466 DRM_MODE_CONNECTOR_Unknown,
467 DRM_MODE_CONNECTOR_HDMIA,
468 DRM_MODE_CONNECTOR_HDMIB,
469 DRM_MODE_CONNECTOR_Unknown,
470 DRM_MODE_CONNECTOR_Unknown,
471 DRM_MODE_CONNECTOR_9PinDIN,
472 DRM_MODE_CONNECTOR_DisplayPort
473 };
474
475 static const uint16_t supported_devices_connector_object_id_convert[] = {
476 CONNECTOR_OBJECT_ID_NONE,
477 CONNECTOR_OBJECT_ID_VGA,
478 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
479 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
480 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
481 CONNECTOR_OBJECT_ID_COMPOSITE,
482 CONNECTOR_OBJECT_ID_SVIDEO,
483 CONNECTOR_OBJECT_ID_LVDS,
484 CONNECTOR_OBJECT_ID_9PIN_DIN,
485 CONNECTOR_OBJECT_ID_9PIN_DIN,
486 CONNECTOR_OBJECT_ID_DISPLAYPORT,
487 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
488 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
489 CONNECTOR_OBJECT_ID_SVIDEO
490 };
491
492 static const int object_connector_convert[] = {
493 DRM_MODE_CONNECTOR_Unknown,
494 DRM_MODE_CONNECTOR_DVII,
495 DRM_MODE_CONNECTOR_DVII,
496 DRM_MODE_CONNECTOR_DVID,
497 DRM_MODE_CONNECTOR_DVID,
498 DRM_MODE_CONNECTOR_VGA,
499 DRM_MODE_CONNECTOR_Composite,
500 DRM_MODE_CONNECTOR_SVIDEO,
501 DRM_MODE_CONNECTOR_Unknown,
502 DRM_MODE_CONNECTOR_Unknown,
503 DRM_MODE_CONNECTOR_9PinDIN,
504 DRM_MODE_CONNECTOR_Unknown,
505 DRM_MODE_CONNECTOR_HDMIA,
506 DRM_MODE_CONNECTOR_HDMIB,
507 DRM_MODE_CONNECTOR_LVDS,
508 DRM_MODE_CONNECTOR_9PinDIN,
509 DRM_MODE_CONNECTOR_Unknown,
510 DRM_MODE_CONNECTOR_Unknown,
511 DRM_MODE_CONNECTOR_Unknown,
512 DRM_MODE_CONNECTOR_DisplayPort,
513 DRM_MODE_CONNECTOR_eDP,
514 DRM_MODE_CONNECTOR_Unknown
515 };
516
radeon_get_atom_connector_info_from_object_table(struct drm_device * dev)517 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
518 {
519 struct radeon_device *rdev = dev->dev_private;
520 struct radeon_mode_info *mode_info = &rdev->mode_info;
521 struct atom_context *ctx = mode_info->atom_context;
522 int index = GetIndexIntoMasterTable(DATA, Object_Header);
523 u16 size, data_offset;
524 u8 frev, crev;
525 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
526 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
527 ATOM_OBJECT_TABLE *router_obj;
528 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
529 ATOM_OBJECT_HEADER *obj_header;
530 int i, j, k, path_size, device_support;
531 int connector_type;
532 u16 igp_lane_info, conn_id, connector_object_id;
533 struct radeon_i2c_bus_rec ddc_bus;
534 struct radeon_router router;
535 struct radeon_gpio_rec gpio;
536 struct radeon_hpd hpd;
537
538 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
539 return false;
540
541 if (crev < 2)
542 return false;
543
544 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
545 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
546 (ctx->bios + data_offset +
547 le16_to_cpu(obj_header->usDisplayPathTableOffset));
548 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
549 (ctx->bios + data_offset +
550 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
551 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
552 (ctx->bios + data_offset +
553 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
554 router_obj = (ATOM_OBJECT_TABLE *)
555 (ctx->bios + data_offset +
556 le16_to_cpu(obj_header->usRouterObjectTableOffset));
557 device_support = le16_to_cpu(obj_header->usDeviceSupport);
558
559 path_size = 0;
560 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
561 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
562 ATOM_DISPLAY_OBJECT_PATH *path;
563 addr += path_size;
564 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
565 path_size += le16_to_cpu(path->usSize);
566
567 if (device_support & le16_to_cpu(path->usDeviceTag)) {
568 uint8_t con_obj_id, con_obj_num;
569
570 con_obj_id =
571 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
572 >> OBJECT_ID_SHIFT;
573 con_obj_num =
574 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
575 >> ENUM_ID_SHIFT;
576
577 /* TODO CV support */
578 if (le16_to_cpu(path->usDeviceTag) ==
579 ATOM_DEVICE_CV_SUPPORT)
580 continue;
581
582 /* IGP chips */
583 if ((rdev->flags & RADEON_IS_IGP) &&
584 (con_obj_id ==
585 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
586 uint16_t igp_offset = 0;
587 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
588
589 index =
590 GetIndexIntoMasterTable(DATA,
591 IntegratedSystemInfo);
592
593 if (atom_parse_data_header(ctx, index, &size, &frev,
594 &crev, &igp_offset)) {
595
596 if (crev >= 2) {
597 igp_obj =
598 (ATOM_INTEGRATED_SYSTEM_INFO_V2
599 *) (ctx->bios + igp_offset);
600
601 if (igp_obj) {
602 uint32_t slot_config, ct;
603
604 if (con_obj_num == 1)
605 slot_config =
606 igp_obj->
607 ulDDISlot1Config;
608 else
609 slot_config =
610 igp_obj->
611 ulDDISlot2Config;
612
613 ct = (slot_config >> 16) & 0xff;
614 connector_type =
615 object_connector_convert
616 [ct];
617 connector_object_id = ct;
618 igp_lane_info =
619 slot_config & 0xffff;
620 } else
621 continue;
622 } else
623 continue;
624 } else {
625 igp_lane_info = 0;
626 connector_type =
627 object_connector_convert[con_obj_id];
628 connector_object_id = con_obj_id;
629 }
630 } else {
631 igp_lane_info = 0;
632 connector_type =
633 object_connector_convert[con_obj_id];
634 connector_object_id = con_obj_id;
635 }
636
637 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
638 continue;
639
640 router.ddc_valid = false;
641 router.cd_valid = false;
642 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
643 uint8_t grph_obj_type =
644 (le16_to_cpu(path->usGraphicObjIds[j]) &
645 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
646
647 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
648 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
649 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
650 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
651 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
652 (ctx->bios + data_offset +
653 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
654 ATOM_ENCODER_CAP_RECORD *cap_record;
655 u16 caps = 0;
656
657 while (record->ucRecordSize > 0 &&
658 record->ucRecordType > 0 &&
659 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
660 switch (record->ucRecordType) {
661 case ATOM_ENCODER_CAP_RECORD_TYPE:
662 cap_record =(ATOM_ENCODER_CAP_RECORD *)
663 record;
664 caps = le16_to_cpu(cap_record->usEncoderCap);
665 break;
666 }
667 record = (ATOM_COMMON_RECORD_HEADER *)
668 ((char *)record + record->ucRecordSize);
669 }
670 radeon_add_atom_encoder(dev,
671 encoder_obj,
672 le16_to_cpu
673 (path->
674 usDeviceTag),
675 caps);
676 }
677 }
678 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
679 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
680 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
681 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
682 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
683 (ctx->bios + data_offset +
684 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
685 ATOM_I2C_RECORD *i2c_record;
686 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
687 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
688 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
689 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
690 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
691 (ctx->bios + data_offset +
692 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
693 u8 *num_dst_objs = (u8 *)
694 ((u8 *)router_src_dst_table + 1 +
695 (router_src_dst_table->ucNumberOfSrc * 2));
696 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
697 int enum_id;
698
699 router.router_id = router_obj_id;
700 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
701 if (le16_to_cpu(path->usConnObjectId) ==
702 le16_to_cpu(dst_objs[enum_id]))
703 break;
704 }
705
706 while (record->ucRecordSize > 0 &&
707 record->ucRecordType > 0 &&
708 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
709 switch (record->ucRecordType) {
710 case ATOM_I2C_RECORD_TYPE:
711 i2c_record =
712 (ATOM_I2C_RECORD *)
713 record;
714 i2c_config =
715 (ATOM_I2C_ID_CONFIG_ACCESS *)
716 &i2c_record->sucI2cId;
717 router.i2c_info =
718 radeon_lookup_i2c_gpio(rdev,
719 i2c_config->
720 ucAccess);
721 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
722 break;
723 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
724 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
725 record;
726 router.ddc_valid = true;
727 router.ddc_mux_type = ddc_path->ucMuxType;
728 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
729 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
730 break;
731 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
732 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
733 record;
734 router.cd_valid = true;
735 router.cd_mux_type = cd_path->ucMuxType;
736 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
737 router.cd_mux_state = cd_path->ucMuxState[enum_id];
738 break;
739 }
740 record = (ATOM_COMMON_RECORD_HEADER *)
741 ((char *)record + record->ucRecordSize);
742 }
743 }
744 }
745 }
746 }
747
748 /* look up gpio for ddc, hpd */
749 ddc_bus.valid = false;
750 hpd.hpd = RADEON_HPD_NONE;
751 if ((le16_to_cpu(path->usDeviceTag) &
752 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
753 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
754 if (le16_to_cpu(path->usConnObjectId) ==
755 le16_to_cpu(con_obj->asObjects[j].
756 usObjectID)) {
757 ATOM_COMMON_RECORD_HEADER
758 *record =
759 (ATOM_COMMON_RECORD_HEADER
760 *)
761 (ctx->bios + data_offset +
762 le16_to_cpu(con_obj->
763 asObjects[j].
764 usRecordOffset));
765 ATOM_I2C_RECORD *i2c_record;
766 ATOM_HPD_INT_RECORD *hpd_record;
767 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
768
769 while (record->ucRecordSize > 0 &&
770 record->ucRecordType > 0 &&
771 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
772 switch (record->ucRecordType) {
773 case ATOM_I2C_RECORD_TYPE:
774 i2c_record =
775 (ATOM_I2C_RECORD *)
776 record;
777 i2c_config =
778 (ATOM_I2C_ID_CONFIG_ACCESS *)
779 &i2c_record->sucI2cId;
780 ddc_bus = radeon_lookup_i2c_gpio(rdev,
781 i2c_config->
782 ucAccess);
783 break;
784 case ATOM_HPD_INT_RECORD_TYPE:
785 hpd_record =
786 (ATOM_HPD_INT_RECORD *)
787 record;
788 gpio = radeon_atombios_lookup_gpio(rdev,
789 hpd_record->ucHPDIntGPIOID);
790 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
791 hpd.plugged_state = hpd_record->ucPlugged_PinState;
792 break;
793 }
794 record =
795 (ATOM_COMMON_RECORD_HEADER
796 *) ((char *)record
797 +
798 record->
799 ucRecordSize);
800 }
801 break;
802 }
803 }
804 }
805
806 /* needed for aux chan transactions */
807 ddc_bus.hpd = hpd.hpd;
808
809 conn_id = le16_to_cpu(path->usConnObjectId);
810
811 if (!radeon_atom_apply_quirks
812 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
813 &ddc_bus, &conn_id, &hpd))
814 continue;
815
816 radeon_add_atom_connector(dev,
817 conn_id,
818 le16_to_cpu(path->
819 usDeviceTag),
820 connector_type, &ddc_bus,
821 igp_lane_info,
822 connector_object_id,
823 &hpd,
824 &router);
825
826 }
827 }
828
829 radeon_link_encoder_connector(dev);
830 return true;
831 }
832
atombios_get_connector_object_id(struct drm_device * dev,int connector_type,uint16_t devices)833 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
834 int connector_type,
835 uint16_t devices)
836 {
837 struct radeon_device *rdev = dev->dev_private;
838
839 if (rdev->flags & RADEON_IS_IGP) {
840 return supported_devices_connector_object_id_convert
841 [connector_type];
842 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
843 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
844 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
845 struct radeon_mode_info *mode_info = &rdev->mode_info;
846 struct atom_context *ctx = mode_info->atom_context;
847 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
848 uint16_t size, data_offset;
849 uint8_t frev, crev;
850 ATOM_XTMDS_INFO *xtmds;
851
852 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
853 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
854
855 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
856 if (connector_type == DRM_MODE_CONNECTOR_DVII)
857 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
858 else
859 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
860 } else {
861 if (connector_type == DRM_MODE_CONNECTOR_DVII)
862 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
863 else
864 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
865 }
866 } else
867 return supported_devices_connector_object_id_convert
868 [connector_type];
869 } else {
870 return supported_devices_connector_object_id_convert
871 [connector_type];
872 }
873 }
874
875 struct bios_connector {
876 bool valid;
877 uint16_t line_mux;
878 uint16_t devices;
879 int connector_type;
880 struct radeon_i2c_bus_rec ddc_bus;
881 struct radeon_hpd hpd;
882 };
883
radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device * dev)884 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
885 drm_device
886 *dev)
887 {
888 struct radeon_device *rdev = dev->dev_private;
889 struct radeon_mode_info *mode_info = &rdev->mode_info;
890 struct atom_context *ctx = mode_info->atom_context;
891 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
892 uint16_t size, data_offset;
893 uint8_t frev, crev;
894 uint16_t device_support;
895 uint8_t dac;
896 union atom_supported_devices *supported_devices;
897 int i, j, max_device;
898 struct bios_connector *bios_connectors;
899 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
900 struct radeon_router router;
901
902 router.ddc_valid = false;
903 router.cd_valid = false;
904
905 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
906 if (!bios_connectors)
907 return false;
908
909 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
910 &data_offset)) {
911 kfree(bios_connectors);
912 return false;
913 }
914
915 supported_devices =
916 (union atom_supported_devices *)(ctx->bios + data_offset);
917
918 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
919
920 if (frev > 1)
921 max_device = ATOM_MAX_SUPPORTED_DEVICE;
922 else
923 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
924
925 for (i = 0; i < max_device; i++) {
926 ATOM_CONNECTOR_INFO_I2C ci;
927
928 if (frev > 1)
929 ci = supported_devices->info_2d1.asConnInfo[i];
930 else
931 ci = supported_devices->info.asConnInfo[i];
932
933 bios_connectors[i].valid = false;
934
935 if (!(device_support & (1 << i))) {
936 continue;
937 }
938
939 if (i == ATOM_DEVICE_CV_INDEX) {
940 DRM_DEBUG_KMS("Skipping Component Video\n");
941 continue;
942 }
943
944 bios_connectors[i].connector_type =
945 supported_devices_connector_convert[ci.sucConnectorInfo.
946 sbfAccess.
947 bfConnectorType];
948
949 if (bios_connectors[i].connector_type ==
950 DRM_MODE_CONNECTOR_Unknown)
951 continue;
952
953 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
954
955 bios_connectors[i].line_mux =
956 ci.sucI2cId.ucAccess;
957
958 /* give tv unique connector ids */
959 if (i == ATOM_DEVICE_TV1_INDEX) {
960 bios_connectors[i].ddc_bus.valid = false;
961 bios_connectors[i].line_mux = 50;
962 } else if (i == ATOM_DEVICE_TV2_INDEX) {
963 bios_connectors[i].ddc_bus.valid = false;
964 bios_connectors[i].line_mux = 51;
965 } else if (i == ATOM_DEVICE_CV_INDEX) {
966 bios_connectors[i].ddc_bus.valid = false;
967 bios_connectors[i].line_mux = 52;
968 } else
969 bios_connectors[i].ddc_bus =
970 radeon_lookup_i2c_gpio(rdev,
971 bios_connectors[i].line_mux);
972
973 if ((crev > 1) && (frev > 1)) {
974 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
975 switch (isb) {
976 case 0x4:
977 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
978 break;
979 case 0xa:
980 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
981 break;
982 default:
983 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
984 break;
985 }
986 } else {
987 if (i == ATOM_DEVICE_DFP1_INDEX)
988 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
989 else if (i == ATOM_DEVICE_DFP2_INDEX)
990 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
991 else
992 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
993 }
994
995 /* Always set the connector type to VGA for CRT1/CRT2. if they are
996 * shared with a DVI port, we'll pick up the DVI connector when we
997 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
998 */
999 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1000 bios_connectors[i].connector_type =
1001 DRM_MODE_CONNECTOR_VGA;
1002
1003 if (!radeon_atom_apply_quirks
1004 (dev, (1 << i), &bios_connectors[i].connector_type,
1005 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1006 &bios_connectors[i].hpd))
1007 continue;
1008
1009 bios_connectors[i].valid = true;
1010 bios_connectors[i].devices = (1 << i);
1011
1012 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1013 radeon_add_atom_encoder(dev,
1014 radeon_get_encoder_enum(dev,
1015 (1 << i),
1016 dac),
1017 (1 << i),
1018 0);
1019 else
1020 radeon_add_legacy_encoder(dev,
1021 radeon_get_encoder_enum(dev,
1022 (1 << i),
1023 dac),
1024 (1 << i));
1025 }
1026
1027 /* combine shared connectors */
1028 for (i = 0; i < max_device; i++) {
1029 if (bios_connectors[i].valid) {
1030 for (j = 0; j < max_device; j++) {
1031 if (bios_connectors[j].valid && (i != j)) {
1032 if (bios_connectors[i].line_mux ==
1033 bios_connectors[j].line_mux) {
1034 /* make sure not to combine LVDS */
1035 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1036 bios_connectors[i].line_mux = 53;
1037 bios_connectors[i].ddc_bus.valid = false;
1038 continue;
1039 }
1040 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1041 bios_connectors[j].line_mux = 53;
1042 bios_connectors[j].ddc_bus.valid = false;
1043 continue;
1044 }
1045 /* combine analog and digital for DVI-I */
1046 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1047 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1048 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1049 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1050 bios_connectors[i].devices |=
1051 bios_connectors[j].devices;
1052 bios_connectors[i].connector_type =
1053 DRM_MODE_CONNECTOR_DVII;
1054 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1055 bios_connectors[i].hpd =
1056 bios_connectors[j].hpd;
1057 bios_connectors[j].valid = false;
1058 }
1059 }
1060 }
1061 }
1062 }
1063 }
1064
1065 /* add the connectors */
1066 for (i = 0; i < max_device; i++) {
1067 if (bios_connectors[i].valid) {
1068 uint16_t connector_object_id =
1069 atombios_get_connector_object_id(dev,
1070 bios_connectors[i].connector_type,
1071 bios_connectors[i].devices);
1072 radeon_add_atom_connector(dev,
1073 bios_connectors[i].line_mux,
1074 bios_connectors[i].devices,
1075 bios_connectors[i].
1076 connector_type,
1077 &bios_connectors[i].ddc_bus,
1078 0,
1079 connector_object_id,
1080 &bios_connectors[i].hpd,
1081 &router);
1082 }
1083 }
1084
1085 radeon_link_encoder_connector(dev);
1086
1087 kfree(bios_connectors);
1088 return true;
1089 }
1090
1091 union firmware_info {
1092 ATOM_FIRMWARE_INFO info;
1093 ATOM_FIRMWARE_INFO_V1_2 info_12;
1094 ATOM_FIRMWARE_INFO_V1_3 info_13;
1095 ATOM_FIRMWARE_INFO_V1_4 info_14;
1096 ATOM_FIRMWARE_INFO_V2_1 info_21;
1097 ATOM_FIRMWARE_INFO_V2_2 info_22;
1098 };
1099
1100 union igp_info {
1101 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1102 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1103 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1104 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1105 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1106 };
1107
radeon_atombios_get_dentist_vco_freq(struct radeon_device * rdev)1108 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1109 {
1110 struct radeon_mode_info *mode_info = &rdev->mode_info;
1111 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1112 union igp_info *igp_info;
1113 u8 frev, crev;
1114 u16 data_offset;
1115
1116 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1117 &frev, &crev, &data_offset)) {
1118 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1119 data_offset);
1120 rdev->clock.vco_freq =
1121 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1122 }
1123 }
1124
radeon_atom_get_clock_info(struct drm_device * dev)1125 bool radeon_atom_get_clock_info(struct drm_device *dev)
1126 {
1127 struct radeon_device *rdev = dev->dev_private;
1128 struct radeon_mode_info *mode_info = &rdev->mode_info;
1129 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1130 union firmware_info *firmware_info;
1131 uint8_t frev, crev;
1132 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1133 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1134 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1135 struct radeon_pll *spll = &rdev->clock.spll;
1136 struct radeon_pll *mpll = &rdev->clock.mpll;
1137 uint16_t data_offset;
1138
1139 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1140 &frev, &crev, &data_offset)) {
1141 firmware_info =
1142 (union firmware_info *)(mode_info->atom_context->bios +
1143 data_offset);
1144 /* pixel clocks */
1145 p1pll->reference_freq =
1146 le16_to_cpu(firmware_info->info.usReferenceClock);
1147 p1pll->reference_div = 0;
1148
1149 if ((frev < 2) && (crev < 2))
1150 p1pll->pll_out_min =
1151 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1152 else
1153 p1pll->pll_out_min =
1154 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1155 p1pll->pll_out_max =
1156 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1157
1158 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1159 p1pll->lcd_pll_out_min =
1160 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1161 if (p1pll->lcd_pll_out_min == 0)
1162 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1163 p1pll->lcd_pll_out_max =
1164 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1165 if (p1pll->lcd_pll_out_max == 0)
1166 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1167 } else {
1168 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1169 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1170 }
1171
1172 if (p1pll->pll_out_min == 0) {
1173 if (ASIC_IS_AVIVO(rdev))
1174 p1pll->pll_out_min = 64800;
1175 else
1176 p1pll->pll_out_min = 20000;
1177 }
1178
1179 p1pll->pll_in_min =
1180 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1181 p1pll->pll_in_max =
1182 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1183
1184 *p2pll = *p1pll;
1185
1186 /* system clock */
1187 if (ASIC_IS_DCE4(rdev))
1188 spll->reference_freq =
1189 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1190 else
1191 spll->reference_freq =
1192 le16_to_cpu(firmware_info->info.usReferenceClock);
1193 spll->reference_div = 0;
1194
1195 spll->pll_out_min =
1196 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1197 spll->pll_out_max =
1198 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1199
1200 /* ??? */
1201 if (spll->pll_out_min == 0) {
1202 if (ASIC_IS_AVIVO(rdev))
1203 spll->pll_out_min = 64800;
1204 else
1205 spll->pll_out_min = 20000;
1206 }
1207
1208 spll->pll_in_min =
1209 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1210 spll->pll_in_max =
1211 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1212
1213 /* memory clock */
1214 if (ASIC_IS_DCE4(rdev))
1215 mpll->reference_freq =
1216 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1217 else
1218 mpll->reference_freq =
1219 le16_to_cpu(firmware_info->info.usReferenceClock);
1220 mpll->reference_div = 0;
1221
1222 mpll->pll_out_min =
1223 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1224 mpll->pll_out_max =
1225 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1226
1227 /* ??? */
1228 if (mpll->pll_out_min == 0) {
1229 if (ASIC_IS_AVIVO(rdev))
1230 mpll->pll_out_min = 64800;
1231 else
1232 mpll->pll_out_min = 20000;
1233 }
1234
1235 mpll->pll_in_min =
1236 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1237 mpll->pll_in_max =
1238 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1239
1240 rdev->clock.default_sclk =
1241 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1242 rdev->clock.default_mclk =
1243 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1244
1245 if (ASIC_IS_DCE4(rdev)) {
1246 rdev->clock.default_dispclk =
1247 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1248 if (rdev->clock.default_dispclk == 0) {
1249 if (ASIC_IS_DCE6(rdev))
1250 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1251 else if (ASIC_IS_DCE5(rdev))
1252 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1253 else
1254 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1255 }
1256 /* set a reasonable default for DP */
1257 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1258 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1259 rdev->clock.default_dispclk / 100);
1260 rdev->clock.default_dispclk = 60000;
1261 }
1262 rdev->clock.dp_extclk =
1263 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1264 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1265 }
1266 *dcpll = *p1pll;
1267
1268 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1269 if (rdev->clock.max_pixel_clock == 0)
1270 rdev->clock.max_pixel_clock = 40000;
1271
1272 /* not technically a clock, but... */
1273 rdev->mode_info.firmware_flags =
1274 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1275
1276 if (ASIC_IS_DCE8(rdev))
1277 rdev->clock.vco_freq =
1278 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1279 else if (ASIC_IS_DCE5(rdev))
1280 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1281 else if (ASIC_IS_DCE41(rdev))
1282 radeon_atombios_get_dentist_vco_freq(rdev);
1283 else
1284 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1285
1286 if (rdev->clock.vco_freq == 0)
1287 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1288
1289 return true;
1290 }
1291
1292 return false;
1293 }
1294
radeon_atombios_sideport_present(struct radeon_device * rdev)1295 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1296 {
1297 struct radeon_mode_info *mode_info = &rdev->mode_info;
1298 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1299 union igp_info *igp_info;
1300 u8 frev, crev;
1301 u16 data_offset;
1302
1303 /* sideport is AMD only */
1304 if (rdev->family == CHIP_RS600)
1305 return false;
1306
1307 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1308 &frev, &crev, &data_offset)) {
1309 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1310 data_offset);
1311 switch (crev) {
1312 case 1:
1313 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1314 return true;
1315 break;
1316 case 2:
1317 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1318 return true;
1319 break;
1320 default:
1321 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1322 break;
1323 }
1324 }
1325 return false;
1326 }
1327
radeon_atombios_get_tmds_info(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1328 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1329 struct radeon_encoder_int_tmds *tmds)
1330 {
1331 struct drm_device *dev = encoder->base.dev;
1332 struct radeon_device *rdev = dev->dev_private;
1333 struct radeon_mode_info *mode_info = &rdev->mode_info;
1334 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1335 uint16_t data_offset;
1336 struct _ATOM_TMDS_INFO *tmds_info;
1337 uint8_t frev, crev;
1338 uint16_t maxfreq;
1339 int i;
1340
1341 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1342 &frev, &crev, &data_offset)) {
1343 tmds_info =
1344 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1345 data_offset);
1346
1347 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1348 for (i = 0; i < 4; i++) {
1349 tmds->tmds_pll[i].freq =
1350 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1351 tmds->tmds_pll[i].value =
1352 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1353 tmds->tmds_pll[i].value |=
1354 (tmds_info->asMiscInfo[i].
1355 ucPLL_VCO_Gain & 0x3f) << 6;
1356 tmds->tmds_pll[i].value |=
1357 (tmds_info->asMiscInfo[i].
1358 ucPLL_DutyCycle & 0xf) << 12;
1359 tmds->tmds_pll[i].value |=
1360 (tmds_info->asMiscInfo[i].
1361 ucPLL_VoltageSwing & 0xf) << 16;
1362
1363 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1364 tmds->tmds_pll[i].freq,
1365 tmds->tmds_pll[i].value);
1366
1367 if (maxfreq == tmds->tmds_pll[i].freq) {
1368 tmds->tmds_pll[i].freq = 0xffffffff;
1369 break;
1370 }
1371 }
1372 return true;
1373 }
1374 return false;
1375 }
1376
radeon_atombios_get_ppll_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1377 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1378 struct radeon_atom_ss *ss,
1379 int id)
1380 {
1381 struct radeon_mode_info *mode_info = &rdev->mode_info;
1382 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1383 uint16_t data_offset, size;
1384 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1385 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1386 uint8_t frev, crev;
1387 int i, num_indices;
1388
1389 memset(ss, 0, sizeof(struct radeon_atom_ss));
1390 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1391 &frev, &crev, &data_offset)) {
1392 ss_info =
1393 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1394
1395 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1396 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1397 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *)
1398 ((u8 *)&ss_info->asSS_Info[0]);
1399 for (i = 0; i < num_indices; i++) {
1400 if (ss_assign->ucSS_Id == id) {
1401 ss->percentage =
1402 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1403 ss->type = ss_assign->ucSpreadSpectrumType;
1404 ss->step = ss_assign->ucSS_Step;
1405 ss->delay = ss_assign->ucSS_Delay;
1406 ss->range = ss_assign->ucSS_Range;
1407 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1408 return true;
1409 }
1410 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *)
1411 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1412 }
1413 }
1414 return false;
1415 }
1416
radeon_atombios_get_igp_ss_overrides(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id)1417 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1418 struct radeon_atom_ss *ss,
1419 int id)
1420 {
1421 struct radeon_mode_info *mode_info = &rdev->mode_info;
1422 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1423 u16 data_offset, size;
1424 union igp_info *igp_info;
1425 u8 frev, crev;
1426 u16 percentage = 0, rate = 0;
1427
1428 /* get any igp specific overrides */
1429 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1430 &frev, &crev, &data_offset)) {
1431 igp_info = (union igp_info *)
1432 (mode_info->atom_context->bios + data_offset);
1433 switch (crev) {
1434 case 6:
1435 switch (id) {
1436 case ASIC_INTERNAL_SS_ON_TMDS:
1437 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1438 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1439 break;
1440 case ASIC_INTERNAL_SS_ON_HDMI:
1441 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1442 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1443 break;
1444 case ASIC_INTERNAL_SS_ON_LVDS:
1445 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1446 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1447 break;
1448 }
1449 break;
1450 case 7:
1451 switch (id) {
1452 case ASIC_INTERNAL_SS_ON_TMDS:
1453 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1454 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1455 break;
1456 case ASIC_INTERNAL_SS_ON_HDMI:
1457 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1458 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1459 break;
1460 case ASIC_INTERNAL_SS_ON_LVDS:
1461 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1462 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1463 break;
1464 }
1465 break;
1466 case 8:
1467 switch (id) {
1468 case ASIC_INTERNAL_SS_ON_TMDS:
1469 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1470 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1471 break;
1472 case ASIC_INTERNAL_SS_ON_HDMI:
1473 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1474 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1475 break;
1476 case ASIC_INTERNAL_SS_ON_LVDS:
1477 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1478 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1479 break;
1480 }
1481 break;
1482 default:
1483 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1484 break;
1485 }
1486 if (percentage)
1487 ss->percentage = percentage;
1488 if (rate)
1489 ss->rate = rate;
1490 }
1491 }
1492
1493 union asic_ss_info {
1494 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1495 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1496 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1497 };
1498
1499 union asic_ss_assignment {
1500 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1501 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1502 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1503 };
1504
radeon_atombios_get_asic_ss_info(struct radeon_device * rdev,struct radeon_atom_ss * ss,int id,u32 clock)1505 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1506 struct radeon_atom_ss *ss,
1507 int id, u32 clock)
1508 {
1509 struct radeon_mode_info *mode_info = &rdev->mode_info;
1510 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1511 uint16_t data_offset, size;
1512 union asic_ss_info *ss_info;
1513 union asic_ss_assignment *ss_assign;
1514 uint8_t frev, crev;
1515 int i, num_indices;
1516
1517 if (id == ASIC_INTERNAL_MEMORY_SS) {
1518 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1519 return false;
1520 }
1521 if (id == ASIC_INTERNAL_ENGINE_SS) {
1522 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1523 return false;
1524 }
1525
1526 memset(ss, 0, sizeof(struct radeon_atom_ss));
1527 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1528 &frev, &crev, &data_offset)) {
1529
1530 ss_info =
1531 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1532
1533 switch (frev) {
1534 case 1:
1535 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1536 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1537
1538 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1539 for (i = 0; i < num_indices; i++) {
1540 if ((ss_assign->v1.ucClockIndication == id) &&
1541 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1542 ss->percentage =
1543 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1544 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1545 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1546 ss->percentage_divider = 100;
1547 return true;
1548 }
1549 ss_assign = (union asic_ss_assignment *)
1550 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1551 }
1552 break;
1553 case 2:
1554 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1555 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1556 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1557 for (i = 0; i < num_indices; i++) {
1558 if ((ss_assign->v2.ucClockIndication == id) &&
1559 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1560 ss->percentage =
1561 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1562 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1563 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1564 ss->percentage_divider = 100;
1565 if ((crev == 2) &&
1566 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1567 (id == ASIC_INTERNAL_MEMORY_SS)))
1568 ss->rate /= 100;
1569 return true;
1570 }
1571 ss_assign = (union asic_ss_assignment *)
1572 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1573 }
1574 break;
1575 case 3:
1576 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1577 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1578 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1579 for (i = 0; i < num_indices; i++) {
1580 if ((ss_assign->v3.ucClockIndication == id) &&
1581 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1582 ss->percentage =
1583 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1584 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1585 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1586 if (ss_assign->v3.ucSpreadSpectrumMode &
1587 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1588 ss->percentage_divider = 1000;
1589 else
1590 ss->percentage_divider = 100;
1591 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1592 (id == ASIC_INTERNAL_MEMORY_SS))
1593 ss->rate /= 100;
1594 if (rdev->flags & RADEON_IS_IGP)
1595 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1596 return true;
1597 }
1598 ss_assign = (union asic_ss_assignment *)
1599 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1600 }
1601 break;
1602 default:
1603 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1604 break;
1605 }
1606
1607 }
1608 return false;
1609 }
1610
1611 union lvds_info {
1612 struct _ATOM_LVDS_INFO info;
1613 struct _ATOM_LVDS_INFO_V12 info_12;
1614 };
1615
radeon_atombios_get_lvds_info(struct radeon_encoder * encoder)1616 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1617 radeon_encoder
1618 *encoder)
1619 {
1620 struct drm_device *dev = encoder->base.dev;
1621 struct radeon_device *rdev = dev->dev_private;
1622 struct radeon_mode_info *mode_info = &rdev->mode_info;
1623 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1624 uint16_t data_offset, misc;
1625 union lvds_info *lvds_info;
1626 uint8_t frev, crev;
1627 struct radeon_encoder_atom_dig *lvds = NULL;
1628 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1629
1630 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1631 &frev, &crev, &data_offset)) {
1632 lvds_info =
1633 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1634 lvds =
1635 kzalloc_obj(struct radeon_encoder_atom_dig);
1636
1637 if (!lvds)
1638 return NULL;
1639
1640 lvds->native_mode.clock =
1641 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1642 lvds->native_mode.hdisplay =
1643 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1644 lvds->native_mode.vdisplay =
1645 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1646 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1647 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1648 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1649 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1650 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1651 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1652 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1653 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1654 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1655 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1656 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1657 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1658 lvds->panel_pwr_delay =
1659 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1660 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1661
1662 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1663 if (misc & ATOM_VSYNC_POLARITY)
1664 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1665 if (misc & ATOM_HSYNC_POLARITY)
1666 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1667 if (misc & ATOM_COMPOSITESYNC)
1668 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1669 if (misc & ATOM_INTERLACE)
1670 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1671 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1672 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1673
1674 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1675 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1676
1677 /* set crtc values */
1678 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1679
1680 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1681
1682 encoder->native_mode = lvds->native_mode;
1683
1684 if (encoder_enum == 2)
1685 lvds->linkb = true;
1686 else
1687 lvds->linkb = false;
1688
1689 /* parse the lcd record table */
1690 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1691 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1692 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1693 bool bad_record = false;
1694 u8 *record;
1695
1696 if ((frev == 1) && (crev < 2))
1697 /* absolute */
1698 record = (u8 *)(mode_info->atom_context->bios +
1699 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1700 else
1701 /* relative */
1702 record = (u8 *)(mode_info->atom_context->bios +
1703 data_offset +
1704 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1705 while (*record != ATOM_RECORD_END_TYPE) {
1706 switch (*record) {
1707 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1708 record += sizeof(ATOM_PATCH_RECORD_MODE);
1709 break;
1710 case LCD_RTS_RECORD_TYPE:
1711 record += sizeof(ATOM_LCD_RTS_RECORD);
1712 break;
1713 case LCD_CAP_RECORD_TYPE:
1714 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1715 break;
1716 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1717 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1718 if (fake_edid_record->ucFakeEDIDLength) {
1719 const struct drm_edid *edid;
1720 int edid_size;
1721
1722 if (fake_edid_record->ucFakeEDIDLength == 128)
1723 edid_size = fake_edid_record->ucFakeEDIDLength;
1724 else
1725 edid_size = fake_edid_record->ucFakeEDIDLength * 128;
1726 edid = drm_edid_alloc(fake_edid_record->ucFakeEDIDString, edid_size);
1727 if (drm_edid_valid(edid))
1728 rdev->mode_info.bios_hardcoded_edid = edid;
1729 else
1730 drm_edid_free(edid);
1731 record += struct_size(fake_edid_record,
1732 ucFakeEDIDString,
1733 edid_size);
1734 } else {
1735 /* empty fake edid record must be 3 bytes long */
1736 record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
1737 }
1738 break;
1739 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1740 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1741 lvds->native_mode.width_mm = panel_res_record->usHSize;
1742 lvds->native_mode.height_mm = panel_res_record->usVSize;
1743 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1744 break;
1745 default:
1746 DRM_ERROR("Bad LCD record %d\n", *record);
1747 bad_record = true;
1748 break;
1749 }
1750 if (bad_record)
1751 break;
1752 }
1753 }
1754 }
1755 return lvds;
1756 }
1757
1758 struct radeon_encoder_primary_dac *
radeon_atombios_get_primary_dac_info(struct radeon_encoder * encoder)1759 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1760 {
1761 struct drm_device *dev = encoder->base.dev;
1762 struct radeon_device *rdev = dev->dev_private;
1763 struct radeon_mode_info *mode_info = &rdev->mode_info;
1764 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1765 uint16_t data_offset;
1766 struct _COMPASSIONATE_DATA *dac_info;
1767 uint8_t frev, crev;
1768 uint8_t bg, dac;
1769 struct radeon_encoder_primary_dac *p_dac = NULL;
1770
1771 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1772 &frev, &crev, &data_offset)) {
1773 dac_info = (struct _COMPASSIONATE_DATA *)
1774 (mode_info->atom_context->bios + data_offset);
1775
1776 p_dac = kzalloc_obj(struct radeon_encoder_primary_dac);
1777
1778 if (!p_dac)
1779 return NULL;
1780
1781 bg = dac_info->ucDAC1_BG_Adjustment;
1782 dac = dac_info->ucDAC1_DAC_Adjustment;
1783 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1784
1785 }
1786 return p_dac;
1787 }
1788
radeon_atom_get_tv_timings(struct radeon_device * rdev,int index,struct drm_display_mode * mode)1789 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1790 struct drm_display_mode *mode)
1791 {
1792 struct radeon_mode_info *mode_info = &rdev->mode_info;
1793 ATOM_ANALOG_TV_INFO *tv_info;
1794 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1795 ATOM_DTD_FORMAT *dtd_timings;
1796 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1797 u8 frev, crev;
1798 u16 data_offset, misc;
1799
1800 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1801 &frev, &crev, &data_offset))
1802 return false;
1803
1804 switch (crev) {
1805 case 1:
1806 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1807 if (index >= MAX_SUPPORTED_TV_TIMING)
1808 return false;
1809
1810 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1811 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1812 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1813 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1814 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1815
1816 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1817 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1818 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1819 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1820 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1821
1822 mode->flags = 0;
1823 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1824 if (misc & ATOM_VSYNC_POLARITY)
1825 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1826 if (misc & ATOM_HSYNC_POLARITY)
1827 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1828 if (misc & ATOM_COMPOSITESYNC)
1829 mode->flags |= DRM_MODE_FLAG_CSYNC;
1830 if (misc & ATOM_INTERLACE)
1831 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1832 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1833 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1834
1835 mode->crtc_clock = mode->clock =
1836 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1837
1838 if (index == 1) {
1839 /* PAL timings appear to have wrong values for totals */
1840 mode->crtc_htotal -= 1;
1841 mode->crtc_vtotal -= 1;
1842 }
1843 break;
1844 case 2:
1845 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1846 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1847 return false;
1848
1849 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1850 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1851 le16_to_cpu(dtd_timings->usHBlanking_Time);
1852 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1853 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1854 le16_to_cpu(dtd_timings->usHSyncOffset);
1855 mode->crtc_hsync_end = mode->crtc_hsync_start +
1856 le16_to_cpu(dtd_timings->usHSyncWidth);
1857
1858 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1859 le16_to_cpu(dtd_timings->usVBlanking_Time);
1860 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1861 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1862 le16_to_cpu(dtd_timings->usVSyncOffset);
1863 mode->crtc_vsync_end = mode->crtc_vsync_start +
1864 le16_to_cpu(dtd_timings->usVSyncWidth);
1865
1866 mode->flags = 0;
1867 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1868 if (misc & ATOM_VSYNC_POLARITY)
1869 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1870 if (misc & ATOM_HSYNC_POLARITY)
1871 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1872 if (misc & ATOM_COMPOSITESYNC)
1873 mode->flags |= DRM_MODE_FLAG_CSYNC;
1874 if (misc & ATOM_INTERLACE)
1875 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1876 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1877 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1878
1879 mode->crtc_clock = mode->clock =
1880 le16_to_cpu(dtd_timings->usPixClk) * 10;
1881 break;
1882 }
1883 return true;
1884 }
1885
1886 enum radeon_tv_std
radeon_atombios_get_tv_info(struct radeon_device * rdev)1887 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1888 {
1889 struct radeon_mode_info *mode_info = &rdev->mode_info;
1890 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1891 uint16_t data_offset;
1892 uint8_t frev, crev;
1893 struct _ATOM_ANALOG_TV_INFO *tv_info;
1894 enum radeon_tv_std tv_std = TV_STD_NTSC;
1895
1896 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1897 &frev, &crev, &data_offset)) {
1898
1899 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1900 (mode_info->atom_context->bios + data_offset);
1901
1902 switch (tv_info->ucTV_BootUpDefaultStandard) {
1903 case ATOM_TV_NTSC:
1904 tv_std = TV_STD_NTSC;
1905 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1906 break;
1907 case ATOM_TV_NTSCJ:
1908 tv_std = TV_STD_NTSC_J;
1909 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1910 break;
1911 case ATOM_TV_PAL:
1912 tv_std = TV_STD_PAL;
1913 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1914 break;
1915 case ATOM_TV_PALM:
1916 tv_std = TV_STD_PAL_M;
1917 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1918 break;
1919 case ATOM_TV_PALN:
1920 tv_std = TV_STD_PAL_N;
1921 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1922 break;
1923 case ATOM_TV_PALCN:
1924 tv_std = TV_STD_PAL_CN;
1925 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1926 break;
1927 case ATOM_TV_PAL60:
1928 tv_std = TV_STD_PAL_60;
1929 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1930 break;
1931 case ATOM_TV_SECAM:
1932 tv_std = TV_STD_SECAM;
1933 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1934 break;
1935 default:
1936 tv_std = TV_STD_NTSC;
1937 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1938 break;
1939 }
1940 }
1941 return tv_std;
1942 }
1943
1944 struct radeon_encoder_tv_dac *
radeon_atombios_get_tv_dac_info(struct radeon_encoder * encoder)1945 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1946 {
1947 struct drm_device *dev = encoder->base.dev;
1948 struct radeon_device *rdev = dev->dev_private;
1949 struct radeon_mode_info *mode_info = &rdev->mode_info;
1950 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1951 uint16_t data_offset;
1952 struct _COMPASSIONATE_DATA *dac_info;
1953 uint8_t frev, crev;
1954 uint8_t bg, dac;
1955 struct radeon_encoder_tv_dac *tv_dac = NULL;
1956
1957 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1958 &frev, &crev, &data_offset)) {
1959
1960 dac_info = (struct _COMPASSIONATE_DATA *)
1961 (mode_info->atom_context->bios + data_offset);
1962
1963 tv_dac = kzalloc_obj(struct radeon_encoder_tv_dac);
1964
1965 if (!tv_dac)
1966 return NULL;
1967
1968 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1969 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1970 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1971
1972 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1973 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1974 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1975
1976 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1977 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1978 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1979
1980 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1981 }
1982 return tv_dac;
1983 }
1984
1985 static const char *thermal_controller_names[] = {
1986 "NONE",
1987 "lm63",
1988 "adm1032",
1989 "adm1030",
1990 "max6649",
1991 "lm63", /* lm64 */
1992 "f75375",
1993 "asc7xxx",
1994 };
1995
1996 static const char *pp_lib_thermal_controller_names[] = {
1997 "NONE",
1998 "lm63",
1999 "adm1032",
2000 "adm1030",
2001 "max6649",
2002 "lm63", /* lm64 */
2003 "f75375",
2004 "RV6xx",
2005 "RV770",
2006 "adt7473",
2007 "NONE",
2008 "External GPIO",
2009 "Evergreen",
2010 "emc2103",
2011 "Sumo",
2012 "Northern Islands",
2013 "Southern Islands",
2014 "lm96163",
2015 "Sea Islands",
2016 };
2017
2018 union power_info {
2019 struct _ATOM_POWERPLAY_INFO info;
2020 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2021 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2022 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2023 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2024 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2025 };
2026
2027 union pplib_clock_info {
2028 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2029 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2030 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2031 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2032 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2033 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2034 };
2035
2036 union pplib_power_state {
2037 struct _ATOM_PPLIB_STATE v1;
2038 struct _ATOM_PPLIB_STATE_V2 v2;
2039 };
2040
radeon_atombios_parse_misc_flags_1_3(struct radeon_device * rdev,int state_index,u32 misc,u32 misc2)2041 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2042 int state_index,
2043 u32 misc, u32 misc2)
2044 {
2045 rdev->pm.power_state[state_index].misc = misc;
2046 rdev->pm.power_state[state_index].misc2 = misc2;
2047 /* order matters! */
2048 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2049 rdev->pm.power_state[state_index].type =
2050 POWER_STATE_TYPE_POWERSAVE;
2051 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2052 rdev->pm.power_state[state_index].type =
2053 POWER_STATE_TYPE_BATTERY;
2054 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2055 rdev->pm.power_state[state_index].type =
2056 POWER_STATE_TYPE_BATTERY;
2057 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2058 rdev->pm.power_state[state_index].type =
2059 POWER_STATE_TYPE_BALANCED;
2060 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2061 rdev->pm.power_state[state_index].type =
2062 POWER_STATE_TYPE_PERFORMANCE;
2063 rdev->pm.power_state[state_index].flags &=
2064 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2065 }
2066 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2067 rdev->pm.power_state[state_index].type =
2068 POWER_STATE_TYPE_BALANCED;
2069 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2070 rdev->pm.power_state[state_index].type =
2071 POWER_STATE_TYPE_DEFAULT;
2072 rdev->pm.default_power_state_index = state_index;
2073 rdev->pm.power_state[state_index].default_clock_mode =
2074 &rdev->pm.power_state[state_index].clock_info[0];
2075 } else if (state_index == 0) {
2076 rdev->pm.power_state[state_index].clock_info[0].flags |=
2077 RADEON_PM_MODE_NO_DISPLAY;
2078 }
2079 }
2080
radeon_atombios_parse_power_table_1_3(struct radeon_device * rdev)2081 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2082 {
2083 struct radeon_mode_info *mode_info = &rdev->mode_info;
2084 u32 misc, misc2 = 0;
2085 int num_modes = 0, i;
2086 int state_index = 0;
2087 struct radeon_i2c_bus_rec i2c_bus;
2088 union power_info *power_info;
2089 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2090 u16 data_offset;
2091 u8 frev, crev;
2092
2093 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2094 &frev, &crev, &data_offset))
2095 return state_index;
2096 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2097
2098 /* add the i2c bus for thermal/fan chip */
2099 if ((power_info->info.ucOverdriveThermalController > 0) &&
2100 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2101 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2102 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2103 power_info->info.ucOverdriveControllerAddress >> 1);
2104 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2105 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2106 if (rdev->pm.i2c_bus) {
2107 struct i2c_board_info info = { };
2108 const char *name = thermal_controller_names[power_info->info.
2109 ucOverdriveThermalController];
2110 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2111 strscpy(info.type, name, sizeof(info.type));
2112 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2113 }
2114 }
2115 num_modes = power_info->info.ucNumOfPowerModeEntries;
2116 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2117 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2118 if (num_modes == 0)
2119 return state_index;
2120 rdev->pm.power_state = kzalloc_objs(struct radeon_power_state,
2121 num_modes);
2122 if (!rdev->pm.power_state)
2123 return state_index;
2124 /* last mode is usually default, array is low to high */
2125 for (i = 0; i < num_modes; i++) {
2126 /* avoid memory leaks from invalid modes or unknown frev. */
2127 if (!rdev->pm.power_state[state_index].clock_info) {
2128 rdev->pm.power_state[state_index].clock_info =
2129 kzalloc_obj(struct radeon_pm_clock_info);
2130 }
2131 if (!rdev->pm.power_state[state_index].clock_info)
2132 goto out;
2133 rdev->pm.power_state[state_index].num_clock_modes = 1;
2134 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2135 switch (frev) {
2136 case 1:
2137 rdev->pm.power_state[state_index].clock_info[0].mclk =
2138 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2139 rdev->pm.power_state[state_index].clock_info[0].sclk =
2140 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2141 /* skip invalid modes */
2142 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2143 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2144 continue;
2145 rdev->pm.power_state[state_index].pcie_lanes =
2146 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2147 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2148 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2149 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2150 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2151 VOLTAGE_GPIO;
2152 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2153 radeon_atombios_lookup_gpio(rdev,
2154 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2155 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2156 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2157 true;
2158 else
2159 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2160 false;
2161 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2162 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2163 VOLTAGE_VDDC;
2164 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2165 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2166 }
2167 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2168 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2169 state_index++;
2170 break;
2171 case 2:
2172 rdev->pm.power_state[state_index].clock_info[0].mclk =
2173 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2174 rdev->pm.power_state[state_index].clock_info[0].sclk =
2175 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2176 /* skip invalid modes */
2177 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2178 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2179 continue;
2180 rdev->pm.power_state[state_index].pcie_lanes =
2181 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2182 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2183 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2184 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2185 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2186 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2187 VOLTAGE_GPIO;
2188 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2189 radeon_atombios_lookup_gpio(rdev,
2190 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2191 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2192 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2193 true;
2194 else
2195 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2196 false;
2197 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2198 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2199 VOLTAGE_VDDC;
2200 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2201 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2202 }
2203 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2204 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2205 state_index++;
2206 break;
2207 case 3:
2208 rdev->pm.power_state[state_index].clock_info[0].mclk =
2209 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2210 rdev->pm.power_state[state_index].clock_info[0].sclk =
2211 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2212 /* skip invalid modes */
2213 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2214 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2215 continue;
2216 rdev->pm.power_state[state_index].pcie_lanes =
2217 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2218 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2219 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2220 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2221 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2222 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2223 VOLTAGE_GPIO;
2224 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2225 radeon_atombios_lookup_gpio(rdev,
2226 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2227 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2228 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2229 true;
2230 else
2231 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2232 false;
2233 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2234 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2235 VOLTAGE_VDDC;
2236 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2237 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2238 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2239 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2240 true;
2241 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2242 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2243 }
2244 }
2245 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2246 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2247 state_index++;
2248 break;
2249 }
2250 }
2251 out:
2252 /* free any unused clock_info allocation. */
2253 if (state_index && state_index < num_modes) {
2254 kfree(rdev->pm.power_state[state_index].clock_info);
2255 rdev->pm.power_state[state_index].clock_info = NULL;
2256 }
2257
2258 /* last mode is usually default */
2259 if (state_index && rdev->pm.default_power_state_index == -1) {
2260 rdev->pm.power_state[state_index - 1].type =
2261 POWER_STATE_TYPE_DEFAULT;
2262 rdev->pm.default_power_state_index = state_index - 1;
2263 rdev->pm.power_state[state_index - 1].default_clock_mode =
2264 &rdev->pm.power_state[state_index - 1].clock_info[0];
2265 rdev->pm.power_state[state_index - 1].flags &=
2266 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2267 rdev->pm.power_state[state_index - 1].misc = 0;
2268 rdev->pm.power_state[state_index - 1].misc2 = 0;
2269 }
2270 return state_index;
2271 }
2272
radeon_atombios_add_pplib_thermal_controller(struct radeon_device * rdev,ATOM_PPLIB_THERMALCONTROLLER * controller)2273 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2274 ATOM_PPLIB_THERMALCONTROLLER *controller)
2275 {
2276 struct radeon_i2c_bus_rec i2c_bus;
2277
2278 /* add the i2c bus for thermal/fan chip */
2279 if (controller->ucType > 0) {
2280 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2281 rdev->pm.no_fan = true;
2282 rdev->pm.fan_pulses_per_revolution =
2283 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2284 if (rdev->pm.fan_pulses_per_revolution) {
2285 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2286 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2287 }
2288 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2289 DRM_INFO("Internal thermal controller %s fan control\n",
2290 (controller->ucFanParameters &
2291 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2292 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2293 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2294 DRM_INFO("Internal thermal controller %s fan control\n",
2295 (controller->ucFanParameters &
2296 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2297 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2298 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2299 DRM_INFO("Internal thermal controller %s fan control\n",
2300 (controller->ucFanParameters &
2301 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2302 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2303 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2304 DRM_INFO("Internal thermal controller %s fan control\n",
2305 (controller->ucFanParameters &
2306 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2307 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2308 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2309 DRM_INFO("Internal thermal controller %s fan control\n",
2310 (controller->ucFanParameters &
2311 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2312 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2313 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2314 DRM_INFO("Internal thermal controller %s fan control\n",
2315 (controller->ucFanParameters &
2316 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2317 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2318 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2319 DRM_INFO("Internal thermal controller %s fan control\n",
2320 (controller->ucFanParameters &
2321 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2322 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2323 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2324 DRM_INFO("Internal thermal controller %s fan control\n",
2325 (controller->ucFanParameters &
2326 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2327 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2328 } else if (controller->ucType ==
2329 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2330 DRM_INFO("External GPIO thermal controller %s fan control\n",
2331 (controller->ucFanParameters &
2332 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2333 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2334 } else if (controller->ucType ==
2335 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2336 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2337 (controller->ucFanParameters &
2338 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2339 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2340 } else if (controller->ucType ==
2341 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2342 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2343 (controller->ucFanParameters &
2344 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2345 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2346 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2347 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2348 pp_lib_thermal_controller_names[controller->ucType],
2349 controller->ucI2cAddress >> 1,
2350 (controller->ucFanParameters &
2351 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2352 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2353 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2354 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2355 if (rdev->pm.i2c_bus) {
2356 struct i2c_board_info info = { };
2357 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2358 info.addr = controller->ucI2cAddress >> 1;
2359 strscpy(info.type, name, sizeof(info.type));
2360 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2361 }
2362 } else {
2363 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2364 controller->ucType,
2365 controller->ucI2cAddress >> 1,
2366 (controller->ucFanParameters &
2367 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2368 }
2369 }
2370 }
2371
radeon_atombios_get_default_voltages(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 * mvdd)2372 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2373 u16 *vddc, u16 *vddci, u16 *mvdd)
2374 {
2375 struct radeon_mode_info *mode_info = &rdev->mode_info;
2376 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2377 u8 frev, crev;
2378 u16 data_offset;
2379 union firmware_info *firmware_info;
2380
2381 *vddc = 0;
2382 *vddci = 0;
2383 *mvdd = 0;
2384
2385 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2386 &frev, &crev, &data_offset)) {
2387 firmware_info =
2388 (union firmware_info *)(mode_info->atom_context->bios +
2389 data_offset);
2390 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2391 if ((frev == 2) && (crev >= 2)) {
2392 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2393 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2394 }
2395 }
2396 }
2397
radeon_atombios_parse_pplib_non_clock_info(struct radeon_device * rdev,int state_index,int mode_index,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info)2398 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2399 int state_index, int mode_index,
2400 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2401 {
2402 int j;
2403 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2404 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2405 u16 vddc, vddci, mvdd;
2406
2407 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2408
2409 rdev->pm.power_state[state_index].misc = misc;
2410 rdev->pm.power_state[state_index].misc2 = misc2;
2411 rdev->pm.power_state[state_index].pcie_lanes =
2412 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2413 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2414 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2415 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2416 rdev->pm.power_state[state_index].type =
2417 POWER_STATE_TYPE_BATTERY;
2418 break;
2419 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2420 rdev->pm.power_state[state_index].type =
2421 POWER_STATE_TYPE_BALANCED;
2422 break;
2423 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2424 rdev->pm.power_state[state_index].type =
2425 POWER_STATE_TYPE_PERFORMANCE;
2426 break;
2427 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2428 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2429 rdev->pm.power_state[state_index].type =
2430 POWER_STATE_TYPE_PERFORMANCE;
2431 break;
2432 }
2433 rdev->pm.power_state[state_index].flags = 0;
2434 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2435 rdev->pm.power_state[state_index].flags |=
2436 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2437 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2438 rdev->pm.power_state[state_index].type =
2439 POWER_STATE_TYPE_DEFAULT;
2440 rdev->pm.default_power_state_index = state_index;
2441 rdev->pm.power_state[state_index].default_clock_mode =
2442 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2443 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2444 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2445 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2446 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2447 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2448 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2449 } else {
2450 u16 max_vddci = 0;
2451
2452 if (ASIC_IS_DCE4(rdev))
2453 radeon_atom_get_max_voltage(rdev,
2454 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2455 &max_vddci);
2456 /* patch the table values with the default sclk/mclk from firmware info */
2457 for (j = 0; j < mode_index; j++) {
2458 rdev->pm.power_state[state_index].clock_info[j].mclk =
2459 rdev->clock.default_mclk;
2460 rdev->pm.power_state[state_index].clock_info[j].sclk =
2461 rdev->clock.default_sclk;
2462 if (vddc)
2463 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2464 vddc;
2465 if (max_vddci)
2466 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2467 max_vddci;
2468 }
2469 }
2470 }
2471 }
2472
radeon_atombios_parse_pplib_clock_info(struct radeon_device * rdev,int state_index,int mode_index,union pplib_clock_info * clock_info)2473 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2474 int state_index, int mode_index,
2475 union pplib_clock_info *clock_info)
2476 {
2477 u32 sclk, mclk;
2478 u16 vddc;
2479
2480 if (rdev->flags & RADEON_IS_IGP) {
2481 if (rdev->family >= CHIP_PALM) {
2482 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2483 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2484 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2485 } else {
2486 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2487 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2488 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2489 }
2490 } else if (rdev->family >= CHIP_BONAIRE) {
2491 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2492 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2493 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2494 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2495 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2496 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2497 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2498 VOLTAGE_NONE;
2499 } else if (rdev->family >= CHIP_TAHITI) {
2500 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2501 sclk |= clock_info->si.ucEngineClockHigh << 16;
2502 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2503 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2504 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2505 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2506 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2507 VOLTAGE_SW;
2508 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2509 le16_to_cpu(clock_info->si.usVDDC);
2510 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2511 le16_to_cpu(clock_info->si.usVDDCI);
2512 } else if (rdev->family >= CHIP_CEDAR) {
2513 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2514 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2515 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2516 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2517 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2518 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2519 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2520 VOLTAGE_SW;
2521 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2522 le16_to_cpu(clock_info->evergreen.usVDDC);
2523 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2524 le16_to_cpu(clock_info->evergreen.usVDDCI);
2525 } else {
2526 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2527 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2528 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2529 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2530 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2531 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2532 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2533 VOLTAGE_SW;
2534 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2535 le16_to_cpu(clock_info->r600.usVDDC);
2536 }
2537
2538 /* patch up vddc if necessary */
2539 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2540 case ATOM_VIRTUAL_VOLTAGE_ID0:
2541 case ATOM_VIRTUAL_VOLTAGE_ID1:
2542 case ATOM_VIRTUAL_VOLTAGE_ID2:
2543 case ATOM_VIRTUAL_VOLTAGE_ID3:
2544 case ATOM_VIRTUAL_VOLTAGE_ID4:
2545 case ATOM_VIRTUAL_VOLTAGE_ID5:
2546 case ATOM_VIRTUAL_VOLTAGE_ID6:
2547 case ATOM_VIRTUAL_VOLTAGE_ID7:
2548 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2549 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2550 &vddc) == 0)
2551 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2552 break;
2553 default:
2554 break;
2555 }
2556
2557 if (rdev->flags & RADEON_IS_IGP) {
2558 /* skip invalid modes */
2559 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2560 return false;
2561 } else {
2562 /* skip invalid modes */
2563 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2564 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2565 return false;
2566 }
2567 return true;
2568 }
2569
radeon_atombios_parse_power_table_4_5(struct radeon_device * rdev)2570 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2571 {
2572 struct radeon_mode_info *mode_info = &rdev->mode_info;
2573 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2574 union pplib_power_state *power_state;
2575 int i, j;
2576 int state_index = 0, mode_index = 0;
2577 union pplib_clock_info *clock_info;
2578 bool valid;
2579 union power_info *power_info;
2580 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2581 u16 data_offset;
2582 u8 frev, crev;
2583
2584 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2585 &frev, &crev, &data_offset))
2586 return state_index;
2587 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2588
2589 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2590 if (power_info->pplib.ucNumStates == 0)
2591 return state_index;
2592 rdev->pm.power_state = kzalloc_objs(struct radeon_power_state,
2593 power_info->pplib.ucNumStates);
2594 if (!rdev->pm.power_state)
2595 return state_index;
2596 /* first mode is usually default, followed by low to high */
2597 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2598 mode_index = 0;
2599 power_state = (union pplib_power_state *)
2600 (mode_info->atom_context->bios + data_offset +
2601 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2602 i * power_info->pplib.ucStateEntrySize);
2603 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2604 (mode_info->atom_context->bios + data_offset +
2605 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2606 (power_state->v1.ucNonClockStateIndex *
2607 power_info->pplib.ucNonClockSize));
2608 rdev->pm.power_state[i].clock_info =
2609 kzalloc_objs(struct radeon_pm_clock_info,
2610 (power_info->pplib.ucStateEntrySize - 1) ? (power_info->pplib.ucStateEntrySize - 1) : 1);
2611 if (!rdev->pm.power_state[i].clock_info)
2612 return state_index;
2613 if (power_info->pplib.ucStateEntrySize - 1) {
2614 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2615 clock_info = (union pplib_clock_info *)
2616 (mode_info->atom_context->bios + data_offset +
2617 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2618 (power_state->v1.ucClockStateIndices[j] *
2619 power_info->pplib.ucClockInfoSize));
2620 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2621 state_index, mode_index,
2622 clock_info);
2623 if (valid)
2624 mode_index++;
2625 }
2626 } else {
2627 rdev->pm.power_state[state_index].clock_info[0].mclk =
2628 rdev->clock.default_mclk;
2629 rdev->pm.power_state[state_index].clock_info[0].sclk =
2630 rdev->clock.default_sclk;
2631 mode_index++;
2632 }
2633 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2634 if (mode_index) {
2635 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2636 non_clock_info);
2637 state_index++;
2638 }
2639 }
2640 /* if multiple clock modes, mark the lowest as no display */
2641 for (i = 0; i < state_index; i++) {
2642 if (rdev->pm.power_state[i].num_clock_modes > 1)
2643 rdev->pm.power_state[i].clock_info[0].flags |=
2644 RADEON_PM_MODE_NO_DISPLAY;
2645 }
2646 /* first mode is usually default */
2647 if (rdev->pm.default_power_state_index == -1) {
2648 rdev->pm.power_state[0].type =
2649 POWER_STATE_TYPE_DEFAULT;
2650 rdev->pm.default_power_state_index = 0;
2651 rdev->pm.power_state[0].default_clock_mode =
2652 &rdev->pm.power_state[0].clock_info[0];
2653 }
2654 return state_index;
2655 }
2656
radeon_atombios_parse_power_table_6(struct radeon_device * rdev)2657 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2658 {
2659 struct radeon_mode_info *mode_info = &rdev->mode_info;
2660 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2661 union pplib_power_state *power_state;
2662 int i, j, non_clock_array_index, clock_array_index;
2663 int state_index = 0, mode_index = 0;
2664 union pplib_clock_info *clock_info;
2665 struct _StateArray *state_array;
2666 struct _ClockInfoArray *clock_info_array;
2667 struct _NonClockInfoArray *non_clock_info_array;
2668 bool valid;
2669 union power_info *power_info;
2670 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2671 u16 data_offset;
2672 u8 frev, crev;
2673 u8 *power_state_offset;
2674
2675 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2676 &frev, &crev, &data_offset))
2677 return state_index;
2678 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2679
2680 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2681 state_array = (struct _StateArray *)
2682 (mode_info->atom_context->bios + data_offset +
2683 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2684 clock_info_array = (struct _ClockInfoArray *)
2685 (mode_info->atom_context->bios + data_offset +
2686 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2687 non_clock_info_array = (struct _NonClockInfoArray *)
2688 (mode_info->atom_context->bios + data_offset +
2689 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2690 if (state_array->ucNumEntries == 0)
2691 return state_index;
2692 rdev->pm.power_state = kzalloc_objs(struct radeon_power_state,
2693 state_array->ucNumEntries);
2694 if (!rdev->pm.power_state)
2695 return state_index;
2696 power_state_offset = (u8 *)state_array->states;
2697 for (i = 0; i < state_array->ucNumEntries; i++) {
2698 mode_index = 0;
2699 power_state = (union pplib_power_state *)power_state_offset;
2700 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2701 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2702 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2703 rdev->pm.power_state[i].clock_info =
2704 kzalloc_objs(struct radeon_pm_clock_info,
2705 power_state->v2.ucNumDPMLevels ? power_state->v2.ucNumDPMLevels : 1);
2706 if (!rdev->pm.power_state[i].clock_info)
2707 return state_index;
2708 if (power_state->v2.ucNumDPMLevels) {
2709 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2710 clock_array_index = power_state->v2.clockInfoIndex[j];
2711 clock_info = (union pplib_clock_info *)
2712 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2713 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2714 state_index, mode_index,
2715 clock_info);
2716 if (valid)
2717 mode_index++;
2718 }
2719 } else {
2720 rdev->pm.power_state[state_index].clock_info[0].mclk =
2721 rdev->clock.default_mclk;
2722 rdev->pm.power_state[state_index].clock_info[0].sclk =
2723 rdev->clock.default_sclk;
2724 mode_index++;
2725 }
2726 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2727 if (mode_index) {
2728 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2729 non_clock_info);
2730 state_index++;
2731 }
2732 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2733 }
2734 /* if multiple clock modes, mark the lowest as no display */
2735 for (i = 0; i < state_index; i++) {
2736 if (rdev->pm.power_state[i].num_clock_modes > 1)
2737 rdev->pm.power_state[i].clock_info[0].flags |=
2738 RADEON_PM_MODE_NO_DISPLAY;
2739 }
2740 /* first mode is usually default */
2741 if (rdev->pm.default_power_state_index == -1) {
2742 rdev->pm.power_state[0].type =
2743 POWER_STATE_TYPE_DEFAULT;
2744 rdev->pm.default_power_state_index = 0;
2745 rdev->pm.power_state[0].default_clock_mode =
2746 &rdev->pm.power_state[0].clock_info[0];
2747 }
2748 return state_index;
2749 }
2750
radeon_atombios_get_power_modes(struct radeon_device * rdev)2751 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2752 {
2753 struct radeon_mode_info *mode_info = &rdev->mode_info;
2754 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2755 u16 data_offset;
2756 u8 frev, crev;
2757 int state_index = 0;
2758
2759 rdev->pm.default_power_state_index = -1;
2760
2761 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2762 &frev, &crev, &data_offset)) {
2763 switch (frev) {
2764 case 1:
2765 case 2:
2766 case 3:
2767 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2768 break;
2769 case 4:
2770 case 5:
2771 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2772 break;
2773 case 6:
2774 state_index = radeon_atombios_parse_power_table_6(rdev);
2775 break;
2776 default:
2777 break;
2778 }
2779 }
2780
2781 if (state_index == 0) {
2782 rdev->pm.power_state = kzalloc_obj(struct radeon_power_state);
2783 if (rdev->pm.power_state) {
2784 rdev->pm.power_state[0].clock_info =
2785 kzalloc_objs(struct radeon_pm_clock_info, 1);
2786 if (rdev->pm.power_state[0].clock_info) {
2787 /* add the default mode */
2788 rdev->pm.power_state[state_index].type =
2789 POWER_STATE_TYPE_DEFAULT;
2790 rdev->pm.power_state[state_index].num_clock_modes = 1;
2791 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2792 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2793 rdev->pm.power_state[state_index].default_clock_mode =
2794 &rdev->pm.power_state[state_index].clock_info[0];
2795 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2796 rdev->pm.power_state[state_index].pcie_lanes = 16;
2797 rdev->pm.default_power_state_index = state_index;
2798 rdev->pm.power_state[state_index].flags = 0;
2799 state_index++;
2800 }
2801 }
2802 }
2803
2804 rdev->pm.num_power_states = state_index;
2805
2806 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2807 rdev->pm.current_clock_mode_index = 0;
2808 if (rdev->pm.default_power_state_index >= 0)
2809 rdev->pm.current_vddc =
2810 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2811 else
2812 rdev->pm.current_vddc = 0;
2813 }
2814
2815 union get_clock_dividers {
2816 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2817 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2818 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2819 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2820 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2821 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2822 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2823 };
2824
radeon_atom_get_clock_dividers(struct radeon_device * rdev,u8 clock_type,u32 clock,bool strobe_mode,struct atom_clock_dividers * dividers)2825 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2826 u8 clock_type,
2827 u32 clock,
2828 bool strobe_mode,
2829 struct atom_clock_dividers *dividers)
2830 {
2831 union get_clock_dividers args;
2832 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2833 u8 frev, crev;
2834
2835 memset(&args, 0, sizeof(args));
2836 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2837
2838 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2839 return -EINVAL;
2840
2841 switch (crev) {
2842 case 1:
2843 /* r4xx, r5xx */
2844 args.v1.ucAction = clock_type;
2845 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2846
2847 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2848
2849 dividers->post_div = args.v1.ucPostDiv;
2850 dividers->fb_div = args.v1.ucFbDiv;
2851 dividers->enable_post_div = true;
2852 break;
2853 case 2:
2854 case 3:
2855 case 5:
2856 /* r6xx, r7xx, evergreen, ni, si */
2857 if (rdev->family <= CHIP_RV770) {
2858 args.v2.ucAction = clock_type;
2859 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2860
2861 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2862
2863 dividers->post_div = args.v2.ucPostDiv;
2864 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2865 dividers->ref_div = args.v2.ucAction;
2866 if (rdev->family == CHIP_RV770) {
2867 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2868 true : false;
2869 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2870 } else
2871 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2872 } else {
2873 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2874 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2875
2876 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2877
2878 dividers->post_div = args.v3.ucPostDiv;
2879 dividers->enable_post_div = (args.v3.ucCntlFlag &
2880 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2881 dividers->enable_dithen = (args.v3.ucCntlFlag &
2882 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2883 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2884 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2885 dividers->ref_div = args.v3.ucRefDiv;
2886 dividers->vco_mode = (args.v3.ucCntlFlag &
2887 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2888 } else {
2889 /* for SI we use ComputeMemoryClockParam for memory plls */
2890 if (rdev->family >= CHIP_TAHITI)
2891 return -EINVAL;
2892 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2893 if (strobe_mode)
2894 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2895
2896 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2897
2898 dividers->post_div = args.v5.ucPostDiv;
2899 dividers->enable_post_div = (args.v5.ucCntlFlag &
2900 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2901 dividers->enable_dithen = (args.v5.ucCntlFlag &
2902 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2903 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2904 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2905 dividers->ref_div = args.v5.ucRefDiv;
2906 dividers->vco_mode = (args.v5.ucCntlFlag &
2907 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2908 }
2909 }
2910 break;
2911 case 4:
2912 /* fusion */
2913 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2914
2915 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2916
2917 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2918 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2919 break;
2920 case 6:
2921 /* CI */
2922 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2923 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2924 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2925
2926 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2927
2928 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2929 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2930 dividers->ref_div = args.v6_out.ucPllRefDiv;
2931 dividers->post_div = args.v6_out.ucPllPostDiv;
2932 dividers->flags = args.v6_out.ucPllCntlFlag;
2933 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2934 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2935 break;
2936 default:
2937 return -EINVAL;
2938 }
2939 return 0;
2940 }
2941
radeon_atom_get_memory_pll_dividers(struct radeon_device * rdev,u32 clock,bool strobe_mode,struct atom_mpll_param * mpll_param)2942 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2943 u32 clock,
2944 bool strobe_mode,
2945 struct atom_mpll_param *mpll_param)
2946 {
2947 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2948 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2949 u8 frev, crev;
2950
2951 memset(&args, 0, sizeof(args));
2952 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2953
2954 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2955 return -EINVAL;
2956
2957 switch (frev) {
2958 case 2:
2959 switch (crev) {
2960 case 1:
2961 /* SI */
2962 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2963 args.ucInputFlag = 0;
2964 if (strobe_mode)
2965 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2966
2967 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
2968
2969 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2970 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2971 mpll_param->post_div = args.ucPostDiv;
2972 mpll_param->dll_speed = args.ucDllSpeed;
2973 mpll_param->bwcntl = args.ucBWCntl;
2974 mpll_param->vco_mode =
2975 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2976 mpll_param->yclk_sel =
2977 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2978 mpll_param->qdr =
2979 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2980 mpll_param->half_rate =
2981 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
2982 break;
2983 default:
2984 return -EINVAL;
2985 }
2986 break;
2987 default:
2988 return -EINVAL;
2989 }
2990 return 0;
2991 }
2992
radeon_atom_set_clock_gating(struct radeon_device * rdev,int enable)2993 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2994 {
2995 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2996 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2997
2998 args.ucEnable = enable;
2999
3000 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3001 }
3002
radeon_atom_get_engine_clock(struct radeon_device * rdev)3003 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3004 {
3005 GET_ENGINE_CLOCK_PS_ALLOCATION args;
3006 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3007
3008 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3009 return le32_to_cpu(args.ulReturnEngineClock);
3010 }
3011
radeon_atom_get_memory_clock(struct radeon_device * rdev)3012 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3013 {
3014 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3015 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3016
3017 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3018 return le32_to_cpu(args.ulReturnMemoryClock);
3019 }
3020
radeon_atom_set_engine_clock(struct radeon_device * rdev,uint32_t eng_clock)3021 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3022 uint32_t eng_clock)
3023 {
3024 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3025 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3026
3027 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3028
3029 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3030 }
3031
radeon_atom_set_memory_clock(struct radeon_device * rdev,uint32_t mem_clock)3032 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3033 uint32_t mem_clock)
3034 {
3035 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3036 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3037
3038 if (rdev->flags & RADEON_IS_IGP)
3039 return;
3040
3041 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3042
3043 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3044 }
3045
radeon_atom_set_engine_dram_timings(struct radeon_device * rdev,u32 eng_clock,u32 mem_clock)3046 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3047 u32 eng_clock, u32 mem_clock)
3048 {
3049 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3050 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3051 u32 tmp;
3052
3053 memset(&args, 0, sizeof(args));
3054
3055 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3056 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3057
3058 args.ulTargetEngineClock = cpu_to_le32(tmp);
3059 if (mem_clock)
3060 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3061
3062 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3063 }
3064
radeon_atom_update_memory_dll(struct radeon_device * rdev,u32 mem_clock)3065 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3066 u32 mem_clock)
3067 {
3068 u32 args;
3069 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3070
3071 args = cpu_to_le32(mem_clock); /* 10 khz */
3072
3073 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3074 }
3075
radeon_atom_set_ac_timing(struct radeon_device * rdev,u32 mem_clock)3076 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3077 u32 mem_clock)
3078 {
3079 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3080 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3081 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3082
3083 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3084
3085 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3086 }
3087
3088 union set_voltage {
3089 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3090 struct _SET_VOLTAGE_PARAMETERS v1;
3091 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3092 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3093 };
3094
radeon_atom_set_voltage(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type)3095 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3096 {
3097 union set_voltage args;
3098 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3099 u8 frev, crev, volt_index = voltage_level;
3100
3101 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3102 return;
3103
3104 /* 0xff01 is a flag rather then an actual voltage */
3105 if (voltage_level == 0xff01)
3106 return;
3107
3108 switch (crev) {
3109 case 1:
3110 args.v1.ucVoltageType = voltage_type;
3111 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3112 args.v1.ucVoltageIndex = volt_index;
3113 break;
3114 case 2:
3115 args.v2.ucVoltageType = voltage_type;
3116 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3117 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3118 break;
3119 case 3:
3120 args.v3.ucVoltageType = voltage_type;
3121 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3122 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3123 break;
3124 default:
3125 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3126 return;
3127 }
3128
3129 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3130 }
3131
radeon_atom_get_max_vddc(struct radeon_device * rdev,u8 voltage_type,u16 voltage_id,u16 * voltage)3132 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3133 u16 voltage_id, u16 *voltage)
3134 {
3135 union set_voltage args;
3136 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3137 u8 frev, crev;
3138
3139 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3140 return -EINVAL;
3141
3142 switch (crev) {
3143 case 1:
3144 return -EINVAL;
3145 case 2:
3146 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3147 args.v2.ucVoltageMode = 0;
3148 args.v2.usVoltageLevel = 0;
3149
3150 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3151
3152 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3153 break;
3154 case 3:
3155 args.v3.ucVoltageType = voltage_type;
3156 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3157 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3158
3159 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3160
3161 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3162 break;
3163 default:
3164 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3165 return -EINVAL;
3166 }
3167
3168 return 0;
3169 }
3170
radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device * rdev,u16 * voltage,u16 leakage_idx)3171 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3172 u16 *voltage,
3173 u16 leakage_idx)
3174 {
3175 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3176 }
3177
radeon_atom_get_leakage_id_from_vbios(struct radeon_device * rdev,u16 * leakage_id)3178 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3179 u16 *leakage_id)
3180 {
3181 union set_voltage args;
3182 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3183 u8 frev, crev;
3184
3185 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3186 return -EINVAL;
3187
3188 switch (crev) {
3189 case 3:
3190 case 4:
3191 args.v3.ucVoltageType = 0;
3192 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3193 args.v3.usVoltageLevel = 0;
3194
3195 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3196
3197 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3198 break;
3199 default:
3200 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3201 return -EINVAL;
3202 }
3203
3204 return 0;
3205 }
3206
radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device * rdev,u16 * vddc,u16 * vddci,u16 virtual_voltage_id,u16 vbios_voltage_id)3207 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3208 u16 *vddc, u16 *vddci,
3209 u16 virtual_voltage_id,
3210 u16 vbios_voltage_id)
3211 {
3212 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3213 u8 frev, crev;
3214 u16 data_offset, size;
3215 int i, j;
3216 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3217 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3218
3219 *vddc = 0;
3220 *vddci = 0;
3221
3222 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3223 &frev, &crev, &data_offset))
3224 return -EINVAL;
3225
3226 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3227 (rdev->mode_info.atom_context->bios + data_offset);
3228
3229 switch (frev) {
3230 case 1:
3231 return -EINVAL;
3232 case 2:
3233 switch (crev) {
3234 case 1:
3235 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3236 return -EINVAL;
3237 leakage_bin = (u16 *)
3238 (rdev->mode_info.atom_context->bios + data_offset +
3239 le16_to_cpu(profile->usLeakageBinArrayOffset));
3240 vddc_id_buf = (u16 *)
3241 (rdev->mode_info.atom_context->bios + data_offset +
3242 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3243 vddc_buf = (u16 *)
3244 (rdev->mode_info.atom_context->bios + data_offset +
3245 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3246 vddci_id_buf = (u16 *)
3247 (rdev->mode_info.atom_context->bios + data_offset +
3248 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3249 vddci_buf = (u16 *)
3250 (rdev->mode_info.atom_context->bios + data_offset +
3251 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3252
3253 if (profile->ucElbVDDC_Num > 0) {
3254 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3255 if (vddc_id_buf[i] == virtual_voltage_id) {
3256 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3257 if (vbios_voltage_id <= leakage_bin[j]) {
3258 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3259 break;
3260 }
3261 }
3262 break;
3263 }
3264 }
3265 }
3266 if (profile->ucElbVDDCI_Num > 0) {
3267 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3268 if (vddci_id_buf[i] == virtual_voltage_id) {
3269 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3270 if (vbios_voltage_id <= leakage_bin[j]) {
3271 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3272 break;
3273 }
3274 }
3275 break;
3276 }
3277 }
3278 }
3279 break;
3280 default:
3281 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3282 return -EINVAL;
3283 }
3284 break;
3285 default:
3286 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3287 return -EINVAL;
3288 }
3289
3290 return 0;
3291 }
3292
3293 union get_voltage_info {
3294 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3295 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3296 };
3297
radeon_atom_get_voltage_evv(struct radeon_device * rdev,u16 virtual_voltage_id,u16 * voltage)3298 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3299 u16 virtual_voltage_id,
3300 u16 *voltage)
3301 {
3302 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3303 u32 entry_id;
3304 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3305 union get_voltage_info args;
3306
3307 for (entry_id = 0; entry_id < count; entry_id++) {
3308 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3309 virtual_voltage_id)
3310 break;
3311 }
3312
3313 if (entry_id >= count)
3314 return -EINVAL;
3315
3316 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3317 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3318 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3319 args.in.ulSCLKFreq =
3320 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3321
3322 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3323
3324 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3325
3326 return 0;
3327 }
3328
radeon_atom_get_voltage_gpio_settings(struct radeon_device * rdev,u16 voltage_level,u8 voltage_type,u32 * gpio_value,u32 * gpio_mask)3329 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3330 u16 voltage_level, u8 voltage_type,
3331 u32 *gpio_value, u32 *gpio_mask)
3332 {
3333 union set_voltage args;
3334 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3335 u8 frev, crev;
3336
3337 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3338 return -EINVAL;
3339
3340 switch (crev) {
3341 case 1:
3342 return -EINVAL;
3343 case 2:
3344 args.v2.ucVoltageType = voltage_type;
3345 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3346 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3347
3348 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3349
3350 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3351
3352 args.v2.ucVoltageType = voltage_type;
3353 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3354 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3355
3356 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
3357
3358 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3359 break;
3360 default:
3361 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3362 return -EINVAL;
3363 }
3364
3365 return 0;
3366 }
3367
3368 union voltage_object_info {
3369 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3370 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3371 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3372 };
3373
3374 union voltage_object {
3375 struct _ATOM_VOLTAGE_OBJECT v1;
3376 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3377 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3378 };
3379
atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO * v1,u8 voltage_type)3380 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3381 u8 voltage_type)
3382 {
3383 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3384 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3385 u8 *start = (u8 *)v1;
3386
3387 while (offset < size) {
3388 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3389 if (vo->ucVoltageType == voltage_type)
3390 return vo;
3391 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3392 vo->asFormula.ucNumOfVoltageEntries;
3393 }
3394 return NULL;
3395 }
3396
atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 * v2,u8 voltage_type)3397 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3398 u8 voltage_type)
3399 {
3400 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3401 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3402 u8 *start = (u8 *)v2;
3403
3404 while (offset < size) {
3405 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3406 if (vo->ucVoltageType == voltage_type)
3407 return vo;
3408 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3409 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3410 }
3411 return NULL;
3412 }
3413
atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 * v3,u8 voltage_type,u8 voltage_mode)3414 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3415 u8 voltage_type, u8 voltage_mode)
3416 {
3417 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3418 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3419 u8 *start = (u8 *)v3;
3420
3421 while (offset < size) {
3422 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3423 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3424 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3425 return vo;
3426 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3427 }
3428 return NULL;
3429 }
3430
3431 bool
radeon_atom_is_voltage_gpio(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode)3432 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3433 u8 voltage_type, u8 voltage_mode)
3434 {
3435 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3436 u8 frev, crev;
3437 u16 data_offset, size;
3438 union voltage_object_info *voltage_info;
3439 union voltage_object *voltage_object = NULL;
3440
3441 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3442 &frev, &crev, &data_offset)) {
3443 voltage_info = (union voltage_object_info *)
3444 (rdev->mode_info.atom_context->bios + data_offset);
3445
3446 switch (frev) {
3447 case 1:
3448 case 2:
3449 switch (crev) {
3450 case 1:
3451 voltage_object = (union voltage_object *)
3452 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3453 if (voltage_object &&
3454 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3455 return true;
3456 break;
3457 case 2:
3458 voltage_object = (union voltage_object *)
3459 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3460 if (voltage_object &&
3461 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3462 return true;
3463 break;
3464 default:
3465 DRM_ERROR("unknown voltage object table\n");
3466 return false;
3467 }
3468 break;
3469 case 3:
3470 switch (crev) {
3471 case 1:
3472 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3473 voltage_type, voltage_mode))
3474 return true;
3475 break;
3476 default:
3477 DRM_ERROR("unknown voltage object table\n");
3478 return false;
3479 }
3480 break;
3481 default:
3482 DRM_ERROR("unknown voltage object table\n");
3483 return false;
3484 }
3485
3486 }
3487 return false;
3488 }
3489
radeon_atom_get_svi2_info(struct radeon_device * rdev,u8 voltage_type,u8 * svd_gpio_id,u8 * svc_gpio_id)3490 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3491 u8 voltage_type,
3492 u8 *svd_gpio_id, u8 *svc_gpio_id)
3493 {
3494 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3495 u8 frev, crev;
3496 u16 data_offset, size;
3497 union voltage_object_info *voltage_info;
3498 union voltage_object *voltage_object = NULL;
3499
3500 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3501 &frev, &crev, &data_offset)) {
3502 voltage_info = (union voltage_object_info *)
3503 (rdev->mode_info.atom_context->bios + data_offset);
3504
3505 switch (frev) {
3506 case 3:
3507 switch (crev) {
3508 case 1:
3509 voltage_object = (union voltage_object *)
3510 atom_lookup_voltage_object_v3(&voltage_info->v3,
3511 voltage_type,
3512 VOLTAGE_OBJ_SVID2);
3513 if (voltage_object) {
3514 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3515 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3516 } else {
3517 return -EINVAL;
3518 }
3519 break;
3520 default:
3521 DRM_ERROR("unknown voltage object table\n");
3522 return -EINVAL;
3523 }
3524 break;
3525 default:
3526 DRM_ERROR("unknown voltage object table\n");
3527 return -EINVAL;
3528 }
3529
3530 }
3531 return 0;
3532 }
3533
radeon_atom_get_max_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * max_voltage)3534 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3535 u8 voltage_type, u16 *max_voltage)
3536 {
3537 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3538 u8 frev, crev;
3539 u16 data_offset, size;
3540 union voltage_object_info *voltage_info;
3541 union voltage_object *voltage_object = NULL;
3542
3543 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3544 &frev, &crev, &data_offset)) {
3545 voltage_info = (union voltage_object_info *)
3546 (rdev->mode_info.atom_context->bios + data_offset);
3547
3548 switch (crev) {
3549 case 1:
3550 voltage_object = (union voltage_object *)
3551 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3552 if (voltage_object) {
3553 ATOM_VOLTAGE_FORMULA *formula =
3554 &voltage_object->v1.asFormula;
3555 if (formula->ucFlag & 1)
3556 *max_voltage =
3557 le16_to_cpu(formula->usVoltageBaseLevel) +
3558 formula->ucNumOfVoltageEntries / 2 *
3559 le16_to_cpu(formula->usVoltageStep);
3560 else
3561 *max_voltage =
3562 le16_to_cpu(formula->usVoltageBaseLevel) +
3563 (formula->ucNumOfVoltageEntries - 1) *
3564 le16_to_cpu(formula->usVoltageStep);
3565 return 0;
3566 }
3567 break;
3568 case 2:
3569 voltage_object = (union voltage_object *)
3570 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3571 if (voltage_object) {
3572 ATOM_VOLTAGE_FORMULA_V2 *formula =
3573 &voltage_object->v2.asFormula;
3574 if (formula->ucNumOfVoltageEntries) {
3575 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3576 ((u8 *)&formula->asVIDAdjustEntries[0] +
3577 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3578 *max_voltage =
3579 le16_to_cpu(lut->usVoltageValue);
3580 return 0;
3581 }
3582 }
3583 break;
3584 default:
3585 DRM_ERROR("unknown voltage object table\n");
3586 return -EINVAL;
3587 }
3588
3589 }
3590 return -EINVAL;
3591 }
3592
radeon_atom_get_min_voltage(struct radeon_device * rdev,u8 voltage_type,u16 * min_voltage)3593 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3594 u8 voltage_type, u16 *min_voltage)
3595 {
3596 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3597 u8 frev, crev;
3598 u16 data_offset, size;
3599 union voltage_object_info *voltage_info;
3600 union voltage_object *voltage_object = NULL;
3601
3602 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3603 &frev, &crev, &data_offset)) {
3604 voltage_info = (union voltage_object_info *)
3605 (rdev->mode_info.atom_context->bios + data_offset);
3606
3607 switch (crev) {
3608 case 1:
3609 voltage_object = (union voltage_object *)
3610 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3611 if (voltage_object) {
3612 ATOM_VOLTAGE_FORMULA *formula =
3613 &voltage_object->v1.asFormula;
3614 *min_voltage =
3615 le16_to_cpu(formula->usVoltageBaseLevel);
3616 return 0;
3617 }
3618 break;
3619 case 2:
3620 voltage_object = (union voltage_object *)
3621 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3622 if (voltage_object) {
3623 ATOM_VOLTAGE_FORMULA_V2 *formula =
3624 &voltage_object->v2.asFormula;
3625 if (formula->ucNumOfVoltageEntries) {
3626 *min_voltage =
3627 le16_to_cpu(formula->asVIDAdjustEntries[
3628 0
3629 ].usVoltageValue);
3630 return 0;
3631 }
3632 }
3633 break;
3634 default:
3635 DRM_ERROR("unknown voltage object table\n");
3636 return -EINVAL;
3637 }
3638
3639 }
3640 return -EINVAL;
3641 }
3642
radeon_atom_get_voltage_step(struct radeon_device * rdev,u8 voltage_type,u16 * voltage_step)3643 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3644 u8 voltage_type, u16 *voltage_step)
3645 {
3646 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3647 u8 frev, crev;
3648 u16 data_offset, size;
3649 union voltage_object_info *voltage_info;
3650 union voltage_object *voltage_object = NULL;
3651
3652 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3653 &frev, &crev, &data_offset)) {
3654 voltage_info = (union voltage_object_info *)
3655 (rdev->mode_info.atom_context->bios + data_offset);
3656
3657 switch (crev) {
3658 case 1:
3659 voltage_object = (union voltage_object *)
3660 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3661 if (voltage_object) {
3662 ATOM_VOLTAGE_FORMULA *formula =
3663 &voltage_object->v1.asFormula;
3664 if (formula->ucFlag & 1)
3665 *voltage_step =
3666 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3667 else
3668 *voltage_step =
3669 le16_to_cpu(formula->usVoltageStep);
3670 return 0;
3671 }
3672 break;
3673 case 2:
3674 return -EINVAL;
3675 default:
3676 DRM_ERROR("unknown voltage object table\n");
3677 return -EINVAL;
3678 }
3679
3680 }
3681 return -EINVAL;
3682 }
3683
radeon_atom_round_to_true_voltage(struct radeon_device * rdev,u8 voltage_type,u16 nominal_voltage,u16 * true_voltage)3684 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3685 u8 voltage_type,
3686 u16 nominal_voltage,
3687 u16 *true_voltage)
3688 {
3689 u16 min_voltage, max_voltage, voltage_step;
3690
3691 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3692 return -EINVAL;
3693 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3694 return -EINVAL;
3695 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3696 return -EINVAL;
3697
3698 if (nominal_voltage <= min_voltage)
3699 *true_voltage = min_voltage;
3700 else if (nominal_voltage >= max_voltage)
3701 *true_voltage = max_voltage;
3702 else
3703 *true_voltage = min_voltage +
3704 ((nominal_voltage - min_voltage) / voltage_step) *
3705 voltage_step;
3706
3707 return 0;
3708 }
3709
radeon_atom_get_voltage_table(struct radeon_device * rdev,u8 voltage_type,u8 voltage_mode,struct atom_voltage_table * voltage_table)3710 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3711 u8 voltage_type, u8 voltage_mode,
3712 struct atom_voltage_table *voltage_table)
3713 {
3714 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3715 u8 frev, crev;
3716 u16 data_offset, size;
3717 int i, ret;
3718 union voltage_object_info *voltage_info;
3719 union voltage_object *voltage_object = NULL;
3720
3721 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3722 &frev, &crev, &data_offset)) {
3723 voltage_info = (union voltage_object_info *)
3724 (rdev->mode_info.atom_context->bios + data_offset);
3725
3726 switch (frev) {
3727 case 1:
3728 case 2:
3729 switch (crev) {
3730 case 1:
3731 DRM_ERROR("old table version %d, %d\n", frev, crev);
3732 return -EINVAL;
3733 case 2:
3734 voltage_object = (union voltage_object *)
3735 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3736 if (voltage_object) {
3737 ATOM_VOLTAGE_FORMULA_V2 *formula =
3738 &voltage_object->v2.asFormula;
3739 VOLTAGE_LUT_ENTRY *lut;
3740 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3741 return -EINVAL;
3742 lut = &formula->asVIDAdjustEntries[0];
3743 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3744 voltage_table->entries[i].value =
3745 le16_to_cpu(lut->usVoltageValue);
3746 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3747 voltage_table->entries[i].value,
3748 voltage_type,
3749 &voltage_table->entries[i].smio_low,
3750 &voltage_table->mask_low);
3751 if (ret)
3752 return ret;
3753 lut = (VOLTAGE_LUT_ENTRY *)
3754 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3755 }
3756 voltage_table->count = formula->ucNumOfVoltageEntries;
3757 return 0;
3758 }
3759 break;
3760 default:
3761 DRM_ERROR("unknown voltage object table\n");
3762 return -EINVAL;
3763 }
3764 break;
3765 case 3:
3766 switch (crev) {
3767 case 1:
3768 voltage_object = (union voltage_object *)
3769 atom_lookup_voltage_object_v3(&voltage_info->v3,
3770 voltage_type, voltage_mode);
3771 if (voltage_object) {
3772 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3773 &voltage_object->v3.asGpioVoltageObj;
3774 VOLTAGE_LUT_ENTRY_V2 *lut;
3775 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3776 return -EINVAL;
3777 lut = &gpio->asVolGpioLut[0];
3778 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3779 voltage_table->entries[i].value =
3780 le16_to_cpu(lut->usVoltageValue);
3781 voltage_table->entries[i].smio_low =
3782 le32_to_cpu(lut->ulVoltageId);
3783 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3784 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3785 }
3786 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3787 voltage_table->count = gpio->ucGpioEntryNum;
3788 voltage_table->phase_delay = gpio->ucPhaseDelay;
3789 return 0;
3790 }
3791 break;
3792 default:
3793 DRM_ERROR("unknown voltage object table\n");
3794 return -EINVAL;
3795 }
3796 break;
3797 default:
3798 DRM_ERROR("unknown voltage object table\n");
3799 return -EINVAL;
3800 }
3801 }
3802 return -EINVAL;
3803 }
3804
3805 union vram_info {
3806 struct _ATOM_VRAM_INFO_V3 v1_3;
3807 struct _ATOM_VRAM_INFO_V4 v1_4;
3808 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3809 };
3810
radeon_atom_get_memory_info(struct radeon_device * rdev,u8 module_index,struct atom_memory_info * mem_info)3811 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3812 u8 module_index, struct atom_memory_info *mem_info)
3813 {
3814 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3815 u8 frev, crev, i;
3816 u16 data_offset, size;
3817 union vram_info *vram_info;
3818
3819 memset(mem_info, 0, sizeof(struct atom_memory_info));
3820
3821 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3822 &frev, &crev, &data_offset)) {
3823 vram_info = (union vram_info *)
3824 (rdev->mode_info.atom_context->bios + data_offset);
3825 switch (frev) {
3826 case 1:
3827 switch (crev) {
3828 case 3:
3829 /* r6xx */
3830 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3831 ATOM_VRAM_MODULE_V3 *vram_module =
3832 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3833
3834 for (i = 0; i < module_index; i++) {
3835 if (le16_to_cpu(vram_module->usSize) == 0)
3836 return -EINVAL;
3837 vram_module = (ATOM_VRAM_MODULE_V3 *)
3838 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3839 }
3840 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3841 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3842 } else
3843 return -EINVAL;
3844 break;
3845 case 4:
3846 /* r7xx, evergreen */
3847 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3848 ATOM_VRAM_MODULE_V4 *vram_module =
3849 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3850
3851 for (i = 0; i < module_index; i++) {
3852 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3853 return -EINVAL;
3854 vram_module = (ATOM_VRAM_MODULE_V4 *)
3855 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3856 }
3857 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3858 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3859 } else
3860 return -EINVAL;
3861 break;
3862 default:
3863 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3864 return -EINVAL;
3865 }
3866 break;
3867 case 2:
3868 switch (crev) {
3869 case 1:
3870 /* ni */
3871 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3872 ATOM_VRAM_MODULE_V7 *vram_module =
3873 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3874
3875 for (i = 0; i < module_index; i++) {
3876 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3877 return -EINVAL;
3878 vram_module = (ATOM_VRAM_MODULE_V7 *)
3879 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3880 }
3881 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3882 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3883 } else
3884 return -EINVAL;
3885 break;
3886 default:
3887 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3888 return -EINVAL;
3889 }
3890 break;
3891 default:
3892 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3893 return -EINVAL;
3894 }
3895 return 0;
3896 }
3897 return -EINVAL;
3898 }
3899
radeon_atom_get_mclk_range_table(struct radeon_device * rdev,bool gddr5,u8 module_index,struct atom_memory_clock_range_table * mclk_range_table)3900 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3901 bool gddr5, u8 module_index,
3902 struct atom_memory_clock_range_table *mclk_range_table)
3903 {
3904 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3905 u8 frev, crev, i;
3906 u16 data_offset, size;
3907 union vram_info *vram_info;
3908 u32 mem_timing_size = gddr5 ?
3909 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3910
3911 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3912
3913 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3914 &frev, &crev, &data_offset)) {
3915 vram_info = (union vram_info *)
3916 (rdev->mode_info.atom_context->bios + data_offset);
3917 switch (frev) {
3918 case 1:
3919 switch (crev) {
3920 case 3:
3921 DRM_ERROR("old table version %d, %d\n", frev, crev);
3922 return -EINVAL;
3923 case 4:
3924 /* r7xx, evergreen */
3925 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3926 ATOM_VRAM_MODULE_V4 *vram_module =
3927 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3928 ATOM_MEMORY_TIMING_FORMAT *format;
3929
3930 for (i = 0; i < module_index; i++) {
3931 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3932 return -EINVAL;
3933 vram_module = (ATOM_VRAM_MODULE_V4 *)
3934 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3935 }
3936 mclk_range_table->num_entries = (u8)
3937 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3938 mem_timing_size);
3939 format = &vram_module->asMemTiming[0];
3940 for (i = 0; i < mclk_range_table->num_entries; i++) {
3941 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3942 format = (ATOM_MEMORY_TIMING_FORMAT *)
3943 ((u8 *)format + mem_timing_size);
3944 }
3945 } else
3946 return -EINVAL;
3947 break;
3948 default:
3949 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3950 return -EINVAL;
3951 }
3952 break;
3953 case 2:
3954 DRM_ERROR("new table version %d, %d\n", frev, crev);
3955 return -EINVAL;
3956 default:
3957 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3958 return -EINVAL;
3959 }
3960 return 0;
3961 }
3962 return -EINVAL;
3963 }
3964
3965 #define MEM_ID_MASK 0xff000000
3966 #define MEM_ID_SHIFT 24
3967 #define CLOCK_RANGE_MASK 0x00ffffff
3968 #define CLOCK_RANGE_SHIFT 0
3969 #define LOW_NIBBLE_MASK 0xf
3970 #define DATA_EQU_PREV 0
3971 #define DATA_FROM_TABLE 4
3972
radeon_atom_init_mc_reg_table(struct radeon_device * rdev,u8 module_index,struct atom_mc_reg_table * reg_table)3973 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3974 u8 module_index,
3975 struct atom_mc_reg_table *reg_table)
3976 {
3977 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3978 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3979 u32 i = 0, j;
3980 u16 data_offset, size;
3981 union vram_info *vram_info;
3982
3983 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3984
3985 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3986 &frev, &crev, &data_offset)) {
3987 vram_info = (union vram_info *)
3988 (rdev->mode_info.atom_context->bios + data_offset);
3989 switch (frev) {
3990 case 1:
3991 DRM_ERROR("old table version %d, %d\n", frev, crev);
3992 return -EINVAL;
3993 case 2:
3994 switch (crev) {
3995 case 1:
3996 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3997 ATOM_INIT_REG_BLOCK *reg_block =
3998 (ATOM_INIT_REG_BLOCK *)
3999 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4000 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4001 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4002 ((u8 *)reg_block + (2 * sizeof(u16)) +
4003 le16_to_cpu(reg_block->usRegIndexTblSize));
4004 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4005 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4006 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4007 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4008 return -EINVAL;
4009 while (i < num_entries) {
4010 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4011 break;
4012 reg_table->mc_reg_address[i].s1 =
4013 (u16)(le16_to_cpu(format->usRegIndex));
4014 reg_table->mc_reg_address[i].pre_reg_data =
4015 (u8)(format->ucPreRegDataLength);
4016 i++;
4017 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4018 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4019 }
4020 reg_table->last = i;
4021 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4022 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4023 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4024 >> MEM_ID_SHIFT);
4025 if (module_index == t_mem_id) {
4026 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4027 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4028 >> CLOCK_RANGE_SHIFT);
4029 for (i = 0, j = 1; i < reg_table->last; i++) {
4030 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4031 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4032 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4033 j++;
4034 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4035 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4036 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4037 }
4038 }
4039 num_ranges++;
4040 }
4041 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4042 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4043 }
4044 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4045 return -EINVAL;
4046 reg_table->num_entries = num_ranges;
4047 } else
4048 return -EINVAL;
4049 break;
4050 default:
4051 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4052 return -EINVAL;
4053 }
4054 break;
4055 default:
4056 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4057 return -EINVAL;
4058 }
4059 return 0;
4060 }
4061 return -EINVAL;
4062 }
4063
radeon_atom_initialize_bios_scratch_regs(struct drm_device * dev)4064 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4065 {
4066 struct radeon_device *rdev = dev->dev_private;
4067 uint32_t bios_2_scratch, bios_6_scratch;
4068
4069 if (rdev->family >= CHIP_R600) {
4070 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4071 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4072 } else {
4073 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4074 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4075 }
4076
4077 /* let the bios control the backlight */
4078 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4079
4080 /* tell the bios not to handle mode switching */
4081 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4082
4083 /* clear the vbios dpms state */
4084 if (ASIC_IS_DCE4(rdev))
4085 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4086
4087 if (rdev->family >= CHIP_R600) {
4088 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4089 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4090 } else {
4091 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4092 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4093 }
4094
4095 }
4096
radeon_save_bios_scratch_regs(struct radeon_device * rdev)4097 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4098 {
4099 uint32_t scratch_reg;
4100 int i;
4101
4102 if (rdev->family >= CHIP_R600)
4103 scratch_reg = R600_BIOS_0_SCRATCH;
4104 else
4105 scratch_reg = RADEON_BIOS_0_SCRATCH;
4106
4107 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4108 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4109 }
4110
radeon_restore_bios_scratch_regs(struct radeon_device * rdev)4111 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4112 {
4113 uint32_t scratch_reg;
4114 int i;
4115
4116 if (rdev->family >= CHIP_R600)
4117 scratch_reg = R600_BIOS_0_SCRATCH;
4118 else
4119 scratch_reg = RADEON_BIOS_0_SCRATCH;
4120
4121 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4122 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4123 }
4124
radeon_atom_output_lock(struct drm_encoder * encoder,bool lock)4125 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4126 {
4127 struct drm_device *dev = encoder->dev;
4128 struct radeon_device *rdev = dev->dev_private;
4129 uint32_t bios_6_scratch;
4130
4131 if (rdev->family >= CHIP_R600)
4132 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4133 else
4134 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4135
4136 if (lock) {
4137 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4138 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4139 } else {
4140 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4141 bios_6_scratch |= ATOM_S6_ACC_MODE;
4142 }
4143
4144 if (rdev->family >= CHIP_R600)
4145 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4146 else
4147 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4148 }
4149
4150 /* at some point we may want to break this out into individual functions */
4151 void
radeon_atombios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)4152 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4153 struct drm_encoder *encoder,
4154 bool connected)
4155 {
4156 struct drm_device *dev = connector->dev;
4157 struct radeon_device *rdev = dev->dev_private;
4158 struct radeon_connector *radeon_connector =
4159 to_radeon_connector(connector);
4160 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4161 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4162
4163 if (rdev->family >= CHIP_R600) {
4164 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4165 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4166 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4167 } else {
4168 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4169 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4170 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4171 }
4172
4173 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4174 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4175 if (connected) {
4176 DRM_DEBUG_KMS("TV1 connected\n");
4177 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4178 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4179 } else {
4180 DRM_DEBUG_KMS("TV1 disconnected\n");
4181 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4182 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4183 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4184 }
4185 }
4186 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4187 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4188 if (connected) {
4189 DRM_DEBUG_KMS("CV connected\n");
4190 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4191 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4192 } else {
4193 DRM_DEBUG_KMS("CV disconnected\n");
4194 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4195 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4196 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4197 }
4198 }
4199 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4200 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4201 if (connected) {
4202 DRM_DEBUG_KMS("LCD1 connected\n");
4203 bios_0_scratch |= ATOM_S0_LCD1;
4204 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4205 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4206 } else {
4207 DRM_DEBUG_KMS("LCD1 disconnected\n");
4208 bios_0_scratch &= ~ATOM_S0_LCD1;
4209 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4210 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4211 }
4212 }
4213 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4214 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4215 if (connected) {
4216 DRM_DEBUG_KMS("CRT1 connected\n");
4217 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4218 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4219 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4220 } else {
4221 DRM_DEBUG_KMS("CRT1 disconnected\n");
4222 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4223 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4224 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4225 }
4226 }
4227 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4228 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4229 if (connected) {
4230 DRM_DEBUG_KMS("CRT2 connected\n");
4231 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4232 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4233 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4234 } else {
4235 DRM_DEBUG_KMS("CRT2 disconnected\n");
4236 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4237 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4238 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4239 }
4240 }
4241 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4242 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4243 if (connected) {
4244 DRM_DEBUG_KMS("DFP1 connected\n");
4245 bios_0_scratch |= ATOM_S0_DFP1;
4246 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4247 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4248 } else {
4249 DRM_DEBUG_KMS("DFP1 disconnected\n");
4250 bios_0_scratch &= ~ATOM_S0_DFP1;
4251 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4252 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4253 }
4254 }
4255 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4256 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4257 if (connected) {
4258 DRM_DEBUG_KMS("DFP2 connected\n");
4259 bios_0_scratch |= ATOM_S0_DFP2;
4260 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4261 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4262 } else {
4263 DRM_DEBUG_KMS("DFP2 disconnected\n");
4264 bios_0_scratch &= ~ATOM_S0_DFP2;
4265 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4266 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4267 }
4268 }
4269 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4270 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4271 if (connected) {
4272 DRM_DEBUG_KMS("DFP3 connected\n");
4273 bios_0_scratch |= ATOM_S0_DFP3;
4274 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4275 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4276 } else {
4277 DRM_DEBUG_KMS("DFP3 disconnected\n");
4278 bios_0_scratch &= ~ATOM_S0_DFP3;
4279 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4280 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4281 }
4282 }
4283 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4284 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4285 if (connected) {
4286 DRM_DEBUG_KMS("DFP4 connected\n");
4287 bios_0_scratch |= ATOM_S0_DFP4;
4288 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4289 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4290 } else {
4291 DRM_DEBUG_KMS("DFP4 disconnected\n");
4292 bios_0_scratch &= ~ATOM_S0_DFP4;
4293 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4294 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4295 }
4296 }
4297 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4298 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4299 if (connected) {
4300 DRM_DEBUG_KMS("DFP5 connected\n");
4301 bios_0_scratch |= ATOM_S0_DFP5;
4302 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4303 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4304 } else {
4305 DRM_DEBUG_KMS("DFP5 disconnected\n");
4306 bios_0_scratch &= ~ATOM_S0_DFP5;
4307 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4308 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4309 }
4310 }
4311 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4312 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4313 if (connected) {
4314 DRM_DEBUG_KMS("DFP6 connected\n");
4315 bios_0_scratch |= ATOM_S0_DFP6;
4316 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4317 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4318 } else {
4319 DRM_DEBUG_KMS("DFP6 disconnected\n");
4320 bios_0_scratch &= ~ATOM_S0_DFP6;
4321 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4322 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4323 }
4324 }
4325
4326 if (rdev->family >= CHIP_R600) {
4327 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4328 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4329 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4330 } else {
4331 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4332 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4333 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4334 }
4335 }
4336
4337 void
radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)4338 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4339 {
4340 struct drm_device *dev = encoder->dev;
4341 struct radeon_device *rdev = dev->dev_private;
4342 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4343 uint32_t bios_3_scratch;
4344
4345 if (ASIC_IS_DCE4(rdev))
4346 return;
4347
4348 if (rdev->family >= CHIP_R600)
4349 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4350 else
4351 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4352
4353 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4354 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4355 bios_3_scratch |= (crtc << 18);
4356 }
4357 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4358 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4359 bios_3_scratch |= (crtc << 24);
4360 }
4361 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4362 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4363 bios_3_scratch |= (crtc << 16);
4364 }
4365 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4366 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4367 bios_3_scratch |= (crtc << 20);
4368 }
4369 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4370 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4371 bios_3_scratch |= (crtc << 17);
4372 }
4373 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4374 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4375 bios_3_scratch |= (crtc << 19);
4376 }
4377 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4378 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4379 bios_3_scratch |= (crtc << 23);
4380 }
4381 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4382 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4383 bios_3_scratch |= (crtc << 25);
4384 }
4385
4386 if (rdev->family >= CHIP_R600)
4387 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4388 else
4389 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4390 }
4391
4392 void
radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)4393 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4394 {
4395 struct drm_device *dev = encoder->dev;
4396 struct radeon_device *rdev = dev->dev_private;
4397 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4398 uint32_t bios_2_scratch;
4399
4400 if (ASIC_IS_DCE4(rdev))
4401 return;
4402
4403 if (rdev->family >= CHIP_R600)
4404 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4405 else
4406 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4407
4408 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4409 if (on)
4410 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4411 else
4412 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4413 }
4414 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4415 if (on)
4416 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4417 else
4418 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4419 }
4420 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4421 if (on)
4422 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4423 else
4424 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4425 }
4426 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4427 if (on)
4428 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4429 else
4430 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4431 }
4432 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4433 if (on)
4434 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4435 else
4436 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4437 }
4438 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4439 if (on)
4440 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4441 else
4442 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4443 }
4444 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4445 if (on)
4446 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4447 else
4448 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4449 }
4450 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4451 if (on)
4452 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4453 else
4454 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4455 }
4456 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4457 if (on)
4458 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4459 else
4460 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4461 }
4462 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4463 if (on)
4464 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4465 else
4466 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4467 }
4468
4469 if (rdev->family >= CHIP_R600)
4470 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4471 else
4472 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4473 }
4474