1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2020-2026 Intel Corporation
4 */
5
6 #ifndef __IVPU_DRV_H__
7 #define __IVPU_DRV_H__
8
9 #include <drm/drm_device.h>
10 #include <drm/drm_drv.h>
11 #include <drm/drm_managed.h>
12 #include <drm/drm_mm.h>
13 #include <drm/drm_print.h>
14
15 #include <linux/hashtable.h>
16 #include <linux/pci.h>
17 #include <linux/xarray.h>
18 #include <uapi/drm/ivpu_accel.h>
19
20 #include "ivpu_mmu_context.h"
21 #include "ivpu_ipc.h"
22
23 #define DRIVER_NAME "intel_vpu"
24 #define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
25
26 #define PCI_DEVICE_ID_MTL 0x7d1d
27 #define PCI_DEVICE_ID_ARL 0xad1d
28 #define PCI_DEVICE_ID_LNL 0x643e
29 #define PCI_DEVICE_ID_PTL_P 0xb03e
30 #define PCI_DEVICE_ID_WCL 0xfd3e
31 #define PCI_DEVICE_ID_NVL 0xd71d
32
33 #define IVPU_HW_IP_37XX 37
34 #define IVPU_HW_IP_40XX 40
35 #define IVPU_HW_IP_50XX 50
36 #define IVPU_HW_IP_60XX 60
37
38 #define IVPU_HW_IP_REV_LNL_B0 4
39 #define IVPU_HW_IP_REV_NVL_A0 0
40
41 #define IVPU_HW_BTRS_MTL 1
42 #define IVPU_HW_BTRS_LNL 2
43
44 #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
45 /* SSID 1 is used by the VPU to represent reserved context */
46 #define IVPU_RESERVED_CONTEXT_MMU_SSID 1
47 #define IVPU_USER_CONTEXT_MIN_SSID 2
48 #define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 128)
49
50 #define IVPU_MIN_DB 1
51 #define IVPU_MAX_DB 255
52
53 #define IVPU_JOB_ID_JOB_MASK GENMASK(7, 0)
54 #define IVPU_JOB_ID_CONTEXT_MASK GENMASK(31, 8)
55
56 #define IVPU_CMDQ_MIN_ID 1
57 #define IVPU_CMDQ_MAX_ID 255
58
59 #define IVPU_PLATFORM_SILICON 0
60 #define IVPU_PLATFORM_SIMICS 2
61 #define IVPU_PLATFORM_FPGA 3
62 #define IVPU_PLATFORM_HSLE 4
63 #define IVPU_PLATFORM_INVALID 8
64
65 #define IVPU_SCHED_MODE_AUTO -1
66
67 #define IVPU_DBG_REG BIT(0)
68 #define IVPU_DBG_IRQ BIT(1)
69 #define IVPU_DBG_MMU BIT(2)
70 #define IVPU_DBG_FILE BIT(3)
71 #define IVPU_DBG_MISC BIT(4)
72 #define IVPU_DBG_FW_BOOT BIT(5)
73 #define IVPU_DBG_PM BIT(6)
74 #define IVPU_DBG_IPC BIT(7)
75 #define IVPU_DBG_BO BIT(8)
76 #define IVPU_DBG_JOB BIT(9)
77 #define IVPU_DBG_JSM BIT(10)
78 #define IVPU_DBG_KREF BIT(11)
79 #define IVPU_DBG_RPM BIT(12)
80 #define IVPU_DBG_MMU_MAP BIT(13)
81 #define IVPU_DBG_IOCTL BIT(14)
82
83 #define ivpu_err(vdev, fmt, ...) \
84 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
85
86 #define ivpu_err_ratelimited(vdev, fmt, ...) \
87 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
88
89 #define ivpu_warn(vdev, fmt, ...) \
90 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
91
92 #define ivpu_warn_ratelimited(vdev, fmt, ...) \
93 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
94
95 #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
96
97 #define ivpu_dbg(vdev, type, fmt, args...) do { \
98 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \
99 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \
100 } while (0)
101
102 #define IVPU_WA(wa_name) (vdev->wa.wa_name)
103
104 #define IVPU_PRINT_WA(wa_name) do { \
105 if (IVPU_WA(wa_name)) \
106 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
107 } while (0)
108
109 struct ivpu_wa_table {
110 bool punit_disabled;
111 bool clear_runtime_mem;
112 bool interrupt_clear_with_0;
113 bool disable_clock_relinquish;
114 bool disable_d0i3_msg;
115 bool wp0_during_power_up;
116 bool disable_d0i2;
117 };
118
119 struct ivpu_hw_info;
120 struct ivpu_mmu_info;
121 struct ivpu_fw_info;
122 struct ivpu_ipc_info;
123 struct ivpu_pm_info;
124
125 struct ivpu_user_limits {
126 struct hlist_node hash_node;
127 struct ivpu_device *vdev;
128 struct kref ref;
129 u32 max_ctx_count;
130 u32 max_db_count;
131 u32 uid;
132 atomic_t db_count;
133 };
134
135 struct ivpu_device {
136 struct drm_device drm;
137 void __iomem *regb;
138 void __iomem *regv;
139 u32 platform;
140 u32 irq;
141
142 struct ivpu_wa_table wa;
143 struct ivpu_hw_info *hw;
144 struct ivpu_mmu_info *mmu;
145 struct ivpu_fw_info *fw;
146 struct ivpu_ipc_info *ipc;
147 struct ivpu_pm_info *pm;
148
149 struct ivpu_mmu_context gctx;
150 struct ivpu_mmu_context rctx;
151 struct mutex context_list_lock; /* Protects user context addition/removal */
152 struct xarray context_xa;
153 struct xa_limit context_xa_limit;
154 DECLARE_HASHTABLE(user_limits, 8);
155 struct mutex user_limits_lock; /* Protects user_limits */
156
157 struct xarray db_xa;
158 struct xa_limit db_limit;
159 u32 db_next;
160
161 struct work_struct irq_ipc_work;
162 struct work_struct irq_dct_work;
163 struct work_struct context_abort_work;
164
165 struct mutex bo_list_lock; /* Protects bo_list */
166 struct list_head bo_list;
167
168 struct mutex submitted_jobs_lock; /* Protects submitted_jobs */
169 struct xarray submitted_jobs_xa;
170 struct ivpu_ipc_consumer job_done_consumer;
171 atomic_t job_timeout_counter;
172 atomic_t faults_detected;
173
174 atomic64_t unique_id_counter;
175
176 ktime_t busy_start_ts;
177 ktime_t busy_time;
178
179 struct {
180 int boot;
181 int jsm;
182 int tdr;
183 int inference;
184 int autosuspend;
185 int d0i3_entry_msg;
186 int state_dump_msg;
187 } timeout;
188 };
189
190 /*
191 * file_priv has its own refcount (ref) that allows user space to close the fd
192 * without blocking even if VPU is still processing some jobs.
193 */
194 struct ivpu_file_priv {
195 struct kref ref;
196 struct ivpu_device *vdev;
197 struct mutex lock; /* Protects cmdq */
198 struct xarray cmdq_xa;
199 struct ivpu_mmu_context ctx;
200 struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */
201 struct list_head ms_instance_list;
202 struct ivpu_bo *ms_info_bo;
203 struct xa_limit job_limit;
204 struct ivpu_user_limits *user_limits;
205 u32 job_id_next;
206 struct xa_limit cmdq_limit;
207 u32 cmdq_id_next;
208 bool has_mmu_faults;
209 bool bound;
210 bool aborted;
211 };
212
213 extern int ivpu_dbg_mask;
214 extern u8 ivpu_pll_min_ratio;
215 extern u8 ivpu_pll_max_ratio;
216 extern int ivpu_sched_mode;
217 extern bool ivpu_disable_mmu_cont_pages;
218 extern bool ivpu_force_snoop;
219
220 #define IVPU_TEST_MODE_FW_TEST BIT(0)
221 #define IVPU_TEST_MODE_NULL_HW BIT(1)
222 #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2)
223 #define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)
224 #define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)
225 #define IVPU_TEST_MODE_MIP_DISABLE BIT(6)
226 #define IVPU_TEST_MODE_DISABLE_TIMEOUTS BIT(8)
227 #define IVPU_TEST_MODE_TURBO_ENABLE BIT(9)
228 #define IVPU_TEST_MODE_TURBO_DISABLE BIT(10)
229 #define IVPU_TEST_MODE_CLK_RELINQ_DISABLE BIT(11)
230 #define IVPU_TEST_MODE_CLK_RELINQ_ENABLE BIT(12)
231 #define IVPU_TEST_MODE_D0I2_DISABLE BIT(13)
232 extern int ivpu_test_mode;
233
234 struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
235 void ivpu_file_priv_put(struct ivpu_file_priv **link);
236
237 int ivpu_boot(struct ivpu_device *vdev);
238 int ivpu_shutdown(struct ivpu_device *vdev);
239 void ivpu_prepare_for_reset(struct ivpu_device *vdev);
240 bool ivpu_is_capable(struct ivpu_device *vdev, u32 capability);
241
ivpu_revision(struct ivpu_device * vdev)242 static inline u8 ivpu_revision(struct ivpu_device *vdev)
243 {
244 return to_pci_dev(vdev->drm.dev)->revision;
245 }
246
ivpu_device_id(struct ivpu_device * vdev)247 static inline u16 ivpu_device_id(struct ivpu_device *vdev)
248 {
249 return to_pci_dev(vdev->drm.dev)->device;
250 }
251
ivpu_hw_ip_gen(struct ivpu_device * vdev)252 static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)
253 {
254 switch (ivpu_device_id(vdev)) {
255 case PCI_DEVICE_ID_MTL:
256 case PCI_DEVICE_ID_ARL:
257 return IVPU_HW_IP_37XX;
258 case PCI_DEVICE_ID_LNL:
259 return IVPU_HW_IP_40XX;
260 case PCI_DEVICE_ID_PTL_P:
261 case PCI_DEVICE_ID_WCL:
262 return IVPU_HW_IP_50XX;
263 case PCI_DEVICE_ID_NVL:
264 return IVPU_HW_IP_60XX;
265 default:
266 dump_stack();
267 ivpu_err(vdev, "Unknown NPU IP generation\n");
268 return 0;
269 }
270 }
271
ivpu_hw_btrs_gen(struct ivpu_device * vdev)272 static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)
273 {
274 switch (ivpu_device_id(vdev)) {
275 case PCI_DEVICE_ID_MTL:
276 case PCI_DEVICE_ID_ARL:
277 return IVPU_HW_BTRS_MTL;
278 case PCI_DEVICE_ID_LNL:
279 case PCI_DEVICE_ID_PTL_P:
280 case PCI_DEVICE_ID_WCL:
281 case PCI_DEVICE_ID_NVL:
282 return IVPU_HW_BTRS_LNL;
283 default:
284 dump_stack();
285 ivpu_err(vdev, "Unknown buttress generation\n");
286 return 0;
287 }
288 }
289
to_ivpu_device(struct drm_device * dev)290 static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
291 {
292 return container_of(dev, struct ivpu_device, drm);
293 }
294
ivpu_get_context_count(struct ivpu_device * vdev)295 static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
296 {
297 struct xa_limit ctx_limit = vdev->context_xa_limit;
298
299 return (ctx_limit.max - ctx_limit.min + 1);
300 }
301
ivpu_get_doorbell_count(struct ivpu_device * vdev)302 static inline u32 ivpu_get_doorbell_count(struct ivpu_device *vdev)
303 {
304 struct xa_limit db_limit = vdev->db_limit;
305
306 return (db_limit.max - db_limit.min + 1);
307 }
308
ivpu_get_platform(struct ivpu_device * vdev)309 static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
310 {
311 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
312 return vdev->platform;
313 }
314
ivpu_is_silicon(struct ivpu_device * vdev)315 static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
316 {
317 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
318 }
319
ivpu_is_simics(struct ivpu_device * vdev)320 static inline bool ivpu_is_simics(struct ivpu_device *vdev)
321 {
322 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
323 }
324
ivpu_is_fpga(struct ivpu_device * vdev)325 static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
326 {
327 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA ||
328 ivpu_get_platform(vdev) == IVPU_PLATFORM_HSLE;
329 }
330
ivpu_is_force_snoop_enabled(struct ivpu_device * vdev)331 static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev)
332 {
333 return ivpu_force_snoop;
334 }
335
336 #endif /* __IVPU_DRV_H__ */
337