1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 4 Broadcom B43legacy wireless driver 5 6 DMA ringbuffer and descriptor allocation/management 7 8 Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch> 9 10 Some code in this file is derived from the b44.c driver 11 Copyright (C) 2002 David S. Miller 12 Copyright (C) Pekka Pietikainen 13 14 15 */ 16 17 #include "b43legacy.h" 18 #include "dma.h" 19 #include "main.h" 20 #include "debugfs.h" 21 #include "xmit.h" 22 23 #include <linux/dma-mapping.h> 24 #include <linux/pci.h> 25 #include <linux/delay.h> 26 #include <linux/skbuff.h> 27 #include <linux/slab.h> 28 #include <net/dst.h> 29 30 /* 32bit DMA ops. */ 31 static 32 struct b43legacy_dmadesc32 *op32_idx2desc(struct b43legacy_dmaring *ring, 33 int slot, 34 struct b43legacy_dmadesc_meta **meta) 35 { 36 struct b43legacy_dmadesc32 *desc; 37 38 *meta = &(ring->meta[slot]); 39 desc = ring->descbase; 40 desc = &(desc[slot]); 41 42 return desc; 43 } 44 45 static void op32_fill_descriptor(struct b43legacy_dmaring *ring, 46 struct b43legacy_dmadesc32 *desc, 47 dma_addr_t dmaaddr, u16 bufsize, 48 int start, int end, int irq) 49 { 50 struct b43legacy_dmadesc32 *descbase = ring->descbase; 51 int slot; 52 u32 ctl; 53 u32 addr; 54 u32 addrext; 55 56 slot = (int)(desc - descbase); 57 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); 58 59 addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK); 60 addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK) 61 >> SSB_DMA_TRANSLATION_SHIFT; 62 addr |= ring->dev->dma.translation; 63 ctl = (bufsize - ring->frameoffset) 64 & B43legacy_DMA32_DCTL_BYTECNT; 65 if (slot == ring->nr_slots - 1) 66 ctl |= B43legacy_DMA32_DCTL_DTABLEEND; 67 if (start) 68 ctl |= B43legacy_DMA32_DCTL_FRAMESTART; 69 if (end) 70 ctl |= B43legacy_DMA32_DCTL_FRAMEEND; 71 if (irq) 72 ctl |= B43legacy_DMA32_DCTL_IRQ; 73 ctl |= (addrext << B43legacy_DMA32_DCTL_ADDREXT_SHIFT) 74 & B43legacy_DMA32_DCTL_ADDREXT_MASK; 75 76 desc->control = cpu_to_le32(ctl); 77 desc->address = cpu_to_le32(addr); 78 } 79 80 static void op32_poke_tx(struct b43legacy_dmaring *ring, int slot) 81 { 82 b43legacy_dma_write(ring, B43legacy_DMA32_TXINDEX, 83 (u32)(slot * sizeof(struct b43legacy_dmadesc32))); 84 } 85 86 static void op32_tx_suspend(struct b43legacy_dmaring *ring) 87 { 88 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL, 89 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL) 90 | B43legacy_DMA32_TXSUSPEND); 91 } 92 93 static void op32_tx_resume(struct b43legacy_dmaring *ring) 94 { 95 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL, 96 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL) 97 & ~B43legacy_DMA32_TXSUSPEND); 98 } 99 100 static int op32_get_current_rxslot(struct b43legacy_dmaring *ring) 101 { 102 u32 val; 103 104 val = b43legacy_dma_read(ring, B43legacy_DMA32_RXSTATUS); 105 val &= B43legacy_DMA32_RXDPTR; 106 107 return (val / sizeof(struct b43legacy_dmadesc32)); 108 } 109 110 static void op32_set_current_rxslot(struct b43legacy_dmaring *ring, 111 int slot) 112 { 113 b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX, 114 (u32)(slot * sizeof(struct b43legacy_dmadesc32))); 115 } 116 117 static inline int free_slots(struct b43legacy_dmaring *ring) 118 { 119 return (ring->nr_slots - ring->used_slots); 120 } 121 122 static inline int next_slot(struct b43legacy_dmaring *ring, int slot) 123 { 124 B43legacy_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1)); 125 if (slot == ring->nr_slots - 1) 126 return 0; 127 return slot + 1; 128 } 129 130 #ifdef CONFIG_B43LEGACY_DEBUG 131 static void update_max_used_slots(struct b43legacy_dmaring *ring, 132 int current_used_slots) 133 { 134 if (current_used_slots <= ring->max_used_slots) 135 return; 136 ring->max_used_slots = current_used_slots; 137 if (b43legacy_debug(ring->dev, B43legacy_DBG_DMAVERBOSE)) 138 b43legacydbg(ring->dev->wl, 139 "max_used_slots increased to %d on %s ring %d\n", 140 ring->max_used_slots, 141 ring->tx ? "TX" : "RX", 142 ring->index); 143 } 144 #else 145 static inline 146 void update_max_used_slots(struct b43legacy_dmaring *ring, 147 int current_used_slots) 148 { } 149 #endif /* DEBUG */ 150 151 /* Request a slot for usage. */ 152 static inline 153 int request_slot(struct b43legacy_dmaring *ring) 154 { 155 int slot; 156 157 B43legacy_WARN_ON(!ring->tx); 158 B43legacy_WARN_ON(ring->stopped); 159 B43legacy_WARN_ON(free_slots(ring) == 0); 160 161 slot = next_slot(ring, ring->current_slot); 162 ring->current_slot = slot; 163 ring->used_slots++; 164 165 update_max_used_slots(ring, ring->used_slots); 166 167 return slot; 168 } 169 170 /* Mac80211-queue to b43legacy-ring mapping */ 171 static struct b43legacy_dmaring *priority_to_txring( 172 struct b43legacy_wldev *dev, 173 int queue_priority) 174 { 175 struct b43legacy_dmaring *ring; 176 177 /*FIXME: For now we always run on TX-ring-1 */ 178 return dev->dma.tx_ring1; 179 180 /* 0 = highest priority */ 181 switch (queue_priority) { 182 default: 183 B43legacy_WARN_ON(1); 184 fallthrough; 185 case 0: 186 ring = dev->dma.tx_ring3; 187 break; 188 case 1: 189 ring = dev->dma.tx_ring2; 190 break; 191 case 2: 192 ring = dev->dma.tx_ring1; 193 break; 194 case 3: 195 ring = dev->dma.tx_ring0; 196 break; 197 case 4: 198 ring = dev->dma.tx_ring4; 199 break; 200 case 5: 201 ring = dev->dma.tx_ring5; 202 break; 203 } 204 205 return ring; 206 } 207 208 static u16 b43legacy_dmacontroller_base(enum b43legacy_dmatype type, 209 int controller_idx) 210 { 211 static const u16 map32[] = { 212 B43legacy_MMIO_DMA32_BASE0, 213 B43legacy_MMIO_DMA32_BASE1, 214 B43legacy_MMIO_DMA32_BASE2, 215 B43legacy_MMIO_DMA32_BASE3, 216 B43legacy_MMIO_DMA32_BASE4, 217 B43legacy_MMIO_DMA32_BASE5, 218 }; 219 220 B43legacy_WARN_ON(!(controller_idx >= 0 && 221 controller_idx < ARRAY_SIZE(map32))); 222 return map32[controller_idx]; 223 } 224 225 static inline 226 dma_addr_t map_descbuffer(struct b43legacy_dmaring *ring, 227 unsigned char *buf, 228 size_t len, 229 int tx) 230 { 231 dma_addr_t dmaaddr; 232 233 if (tx) 234 dmaaddr = dma_map_single(ring->dev->dev->dma_dev, 235 buf, len, 236 DMA_TO_DEVICE); 237 else 238 dmaaddr = dma_map_single(ring->dev->dev->dma_dev, 239 buf, len, 240 DMA_FROM_DEVICE); 241 242 return dmaaddr; 243 } 244 245 static inline 246 void unmap_descbuffer(struct b43legacy_dmaring *ring, 247 dma_addr_t addr, 248 size_t len, 249 int tx) 250 { 251 if (tx) 252 dma_unmap_single(ring->dev->dev->dma_dev, 253 addr, len, 254 DMA_TO_DEVICE); 255 else 256 dma_unmap_single(ring->dev->dev->dma_dev, 257 addr, len, 258 DMA_FROM_DEVICE); 259 } 260 261 static inline 262 void sync_descbuffer_for_cpu(struct b43legacy_dmaring *ring, 263 dma_addr_t addr, 264 size_t len) 265 { 266 B43legacy_WARN_ON(ring->tx); 267 268 dma_sync_single_for_cpu(ring->dev->dev->dma_dev, 269 addr, len, DMA_FROM_DEVICE); 270 } 271 272 static inline 273 void sync_descbuffer_for_device(struct b43legacy_dmaring *ring, 274 dma_addr_t addr, 275 size_t len) 276 { 277 B43legacy_WARN_ON(ring->tx); 278 279 dma_sync_single_for_device(ring->dev->dev->dma_dev, 280 addr, len, DMA_FROM_DEVICE); 281 } 282 283 static inline 284 void free_descriptor_buffer(struct b43legacy_dmaring *ring, 285 struct b43legacy_dmadesc_meta *meta, 286 int irq_context) 287 { 288 if (meta->skb) { 289 if (irq_context) 290 dev_kfree_skb_irq(meta->skb); 291 else 292 dev_kfree_skb(meta->skb); 293 meta->skb = NULL; 294 } 295 } 296 297 static int alloc_ringmemory(struct b43legacy_dmaring *ring) 298 { 299 /* GFP flags must match the flags in free_ringmemory()! */ 300 ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev, 301 B43legacy_DMA_RINGMEMSIZE, 302 &(ring->dmabase), GFP_KERNEL); 303 if (!ring->descbase) 304 return -ENOMEM; 305 306 return 0; 307 } 308 309 static void free_ringmemory(struct b43legacy_dmaring *ring) 310 { 311 dma_free_coherent(ring->dev->dev->dma_dev, B43legacy_DMA_RINGMEMSIZE, 312 ring->descbase, ring->dmabase); 313 } 314 315 /* Reset the RX DMA channel */ 316 static int b43legacy_dmacontroller_rx_reset(struct b43legacy_wldev *dev, 317 u16 mmio_base, 318 enum b43legacy_dmatype type) 319 { 320 int i; 321 u32 value; 322 u16 offset; 323 324 might_sleep(); 325 326 offset = B43legacy_DMA32_RXCTL; 327 b43legacy_write32(dev, mmio_base + offset, 0); 328 for (i = 0; i < 10; i++) { 329 offset = B43legacy_DMA32_RXSTATUS; 330 value = b43legacy_read32(dev, mmio_base + offset); 331 value &= B43legacy_DMA32_RXSTATE; 332 if (value == B43legacy_DMA32_RXSTAT_DISABLED) { 333 i = -1; 334 break; 335 } 336 msleep(1); 337 } 338 if (i != -1) { 339 b43legacyerr(dev->wl, "DMA RX reset timed out\n"); 340 return -ENODEV; 341 } 342 343 return 0; 344 } 345 346 /* Reset the RX DMA channel */ 347 static int b43legacy_dmacontroller_tx_reset(struct b43legacy_wldev *dev, 348 u16 mmio_base, 349 enum b43legacy_dmatype type) 350 { 351 int i; 352 u32 value; 353 u16 offset; 354 355 might_sleep(); 356 357 for (i = 0; i < 10; i++) { 358 offset = B43legacy_DMA32_TXSTATUS; 359 value = b43legacy_read32(dev, mmio_base + offset); 360 value &= B43legacy_DMA32_TXSTATE; 361 if (value == B43legacy_DMA32_TXSTAT_DISABLED || 362 value == B43legacy_DMA32_TXSTAT_IDLEWAIT || 363 value == B43legacy_DMA32_TXSTAT_STOPPED) 364 break; 365 msleep(1); 366 } 367 offset = B43legacy_DMA32_TXCTL; 368 b43legacy_write32(dev, mmio_base + offset, 0); 369 for (i = 0; i < 10; i++) { 370 offset = B43legacy_DMA32_TXSTATUS; 371 value = b43legacy_read32(dev, mmio_base + offset); 372 value &= B43legacy_DMA32_TXSTATE; 373 if (value == B43legacy_DMA32_TXSTAT_DISABLED) { 374 i = -1; 375 break; 376 } 377 msleep(1); 378 } 379 if (i != -1) { 380 b43legacyerr(dev->wl, "DMA TX reset timed out\n"); 381 return -ENODEV; 382 } 383 /* ensure the reset is completed. */ 384 msleep(1); 385 386 return 0; 387 } 388 389 /* Check if a DMA mapping address is invalid. */ 390 static bool b43legacy_dma_mapping_error(struct b43legacy_dmaring *ring, 391 dma_addr_t addr, 392 size_t buffersize, 393 bool dma_to_device) 394 { 395 if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr))) 396 return true; 397 398 switch (ring->type) { 399 case B43legacy_DMA_30BIT: 400 if ((u64)addr + buffersize > (1ULL << 30)) 401 goto address_error; 402 break; 403 case B43legacy_DMA_32BIT: 404 if ((u64)addr + buffersize > (1ULL << 32)) 405 goto address_error; 406 break; 407 } 408 409 /* The address is OK. */ 410 return false; 411 412 address_error: 413 /* We can't support this address. Unmap it again. */ 414 unmap_descbuffer(ring, addr, buffersize, dma_to_device); 415 416 return true; 417 } 418 419 static int setup_rx_descbuffer(struct b43legacy_dmaring *ring, 420 struct b43legacy_dmadesc32 *desc, 421 struct b43legacy_dmadesc_meta *meta, 422 gfp_t gfp_flags) 423 { 424 struct b43legacy_rxhdr_fw3 *rxhdr; 425 struct b43legacy_hwtxstatus *txstat; 426 dma_addr_t dmaaddr; 427 struct sk_buff *skb; 428 429 B43legacy_WARN_ON(ring->tx); 430 431 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); 432 if (unlikely(!skb)) 433 return -ENOMEM; 434 dmaaddr = map_descbuffer(ring, skb->data, 435 ring->rx_buffersize, 0); 436 if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) { 437 /* ugh. try to realloc in zone_dma */ 438 gfp_flags |= GFP_DMA; 439 440 dev_kfree_skb_any(skb); 441 442 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); 443 if (unlikely(!skb)) 444 return -ENOMEM; 445 dmaaddr = map_descbuffer(ring, skb->data, 446 ring->rx_buffersize, 0); 447 } 448 449 if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) { 450 dev_kfree_skb_any(skb); 451 return -EIO; 452 } 453 454 meta->skb = skb; 455 meta->dmaaddr = dmaaddr; 456 op32_fill_descriptor(ring, desc, dmaaddr, ring->rx_buffersize, 0, 0, 0); 457 458 rxhdr = (struct b43legacy_rxhdr_fw3 *)(skb->data); 459 rxhdr->frame_len = 0; 460 txstat = (struct b43legacy_hwtxstatus *)(skb->data); 461 txstat->cookie = 0; 462 463 return 0; 464 } 465 466 /* Allocate the initial descbuffers. 467 * This is used for an RX ring only. 468 */ 469 static int alloc_initial_descbuffers(struct b43legacy_dmaring *ring) 470 { 471 int i; 472 int err = -ENOMEM; 473 struct b43legacy_dmadesc32 *desc; 474 struct b43legacy_dmadesc_meta *meta; 475 476 for (i = 0; i < ring->nr_slots; i++) { 477 desc = op32_idx2desc(ring, i, &meta); 478 479 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL); 480 if (err) { 481 b43legacyerr(ring->dev->wl, 482 "Failed to allocate initial descbuffers\n"); 483 goto err_unwind; 484 } 485 } 486 mb(); /* all descbuffer setup before next line */ 487 ring->used_slots = ring->nr_slots; 488 err = 0; 489 out: 490 return err; 491 492 err_unwind: 493 for (i--; i >= 0; i--) { 494 desc = op32_idx2desc(ring, i, &meta); 495 496 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0); 497 dev_kfree_skb(meta->skb); 498 } 499 goto out; 500 } 501 502 /* Do initial setup of the DMA controller. 503 * Reset the controller, write the ring busaddress 504 * and switch the "enable" bit on. 505 */ 506 static int dmacontroller_setup(struct b43legacy_dmaring *ring) 507 { 508 int err = 0; 509 u32 value; 510 u32 addrext; 511 u32 trans = ring->dev->dma.translation; 512 u32 ringbase = (u32)(ring->dmabase); 513 514 if (ring->tx) { 515 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK) 516 >> SSB_DMA_TRANSLATION_SHIFT; 517 value = B43legacy_DMA32_TXENABLE; 518 value |= (addrext << B43legacy_DMA32_TXADDREXT_SHIFT) 519 & B43legacy_DMA32_TXADDREXT_MASK; 520 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL, value); 521 b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, 522 (ringbase & ~SSB_DMA_TRANSLATION_MASK) 523 | trans); 524 } else { 525 err = alloc_initial_descbuffers(ring); 526 if (err) 527 goto out; 528 529 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK) 530 >> SSB_DMA_TRANSLATION_SHIFT; 531 value = (ring->frameoffset << 532 B43legacy_DMA32_RXFROFF_SHIFT); 533 value |= B43legacy_DMA32_RXENABLE; 534 value |= (addrext << B43legacy_DMA32_RXADDREXT_SHIFT) 535 & B43legacy_DMA32_RXADDREXT_MASK; 536 b43legacy_dma_write(ring, B43legacy_DMA32_RXCTL, value); 537 b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, 538 (ringbase & ~SSB_DMA_TRANSLATION_MASK) 539 | trans); 540 b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX, 200); 541 } 542 543 out: 544 return err; 545 } 546 547 /* Shutdown the DMA controller. */ 548 static void dmacontroller_cleanup(struct b43legacy_dmaring *ring) 549 { 550 if (ring->tx) { 551 b43legacy_dmacontroller_tx_reset(ring->dev, ring->mmio_base, 552 ring->type); 553 b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, 0); 554 } else { 555 b43legacy_dmacontroller_rx_reset(ring->dev, ring->mmio_base, 556 ring->type); 557 b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, 0); 558 } 559 } 560 561 static void free_all_descbuffers(struct b43legacy_dmaring *ring) 562 { 563 struct b43legacy_dmadesc_meta *meta; 564 int i; 565 566 if (!ring->used_slots) 567 return; 568 for (i = 0; i < ring->nr_slots; i++) { 569 op32_idx2desc(ring, i, &meta); 570 571 if (!meta->skb) { 572 B43legacy_WARN_ON(!ring->tx); 573 continue; 574 } 575 if (ring->tx) 576 unmap_descbuffer(ring, meta->dmaaddr, 577 meta->skb->len, 1); 578 else 579 unmap_descbuffer(ring, meta->dmaaddr, 580 ring->rx_buffersize, 0); 581 free_descriptor_buffer(ring, meta, 0); 582 } 583 } 584 585 static enum b43legacy_dmatype b43legacy_engine_type(struct b43legacy_wldev *dev) 586 { 587 u32 tmp; 588 u16 mmio_base; 589 590 mmio_base = b43legacy_dmacontroller_base(0, 0); 591 b43legacy_write32(dev, 592 mmio_base + B43legacy_DMA32_TXCTL, 593 B43legacy_DMA32_TXADDREXT_MASK); 594 tmp = b43legacy_read32(dev, mmio_base + 595 B43legacy_DMA32_TXCTL); 596 if (tmp & B43legacy_DMA32_TXADDREXT_MASK) 597 return B43legacy_DMA_32BIT; 598 return B43legacy_DMA_30BIT; 599 } 600 601 /* Main initialization function. */ 602 static 603 struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev, 604 int controller_index, 605 int for_tx, 606 enum b43legacy_dmatype type) 607 { 608 struct b43legacy_dmaring *ring; 609 int err; 610 int nr_slots; 611 dma_addr_t dma_test; 612 613 if (for_tx) 614 nr_slots = B43legacy_TXRING_SLOTS; 615 else 616 nr_slots = B43legacy_RXRING_SLOTS; 617 618 ring = kzalloc_flex(*ring, meta, nr_slots); 619 if (!ring) 620 goto out; 621 622 ring->nr_slots = nr_slots; 623 ring->type = type; 624 ring->dev = dev; 625 626 if (for_tx) { 627 ring->txhdr_cache = kcalloc(nr_slots, 628 sizeof(struct b43legacy_txhdr_fw3), 629 GFP_KERNEL); 630 if (!ring->txhdr_cache) 631 goto err_kfree_ring; 632 633 /* test for ability to dma to txhdr_cache */ 634 dma_test = dma_map_single(dev->dev->dma_dev, ring->txhdr_cache, 635 sizeof(struct b43legacy_txhdr_fw3), 636 DMA_TO_DEVICE); 637 638 if (b43legacy_dma_mapping_error(ring, dma_test, 639 sizeof(struct b43legacy_txhdr_fw3), 1)) { 640 /* ugh realloc */ 641 kfree(ring->txhdr_cache); 642 ring->txhdr_cache = kcalloc(nr_slots, 643 sizeof(struct b43legacy_txhdr_fw3), 644 GFP_KERNEL | GFP_DMA); 645 if (!ring->txhdr_cache) 646 goto err_kfree_txhdr_cache; 647 648 dma_test = dma_map_single(dev->dev->dma_dev, 649 ring->txhdr_cache, 650 sizeof(struct b43legacy_txhdr_fw3), 651 DMA_TO_DEVICE); 652 653 if (b43legacy_dma_mapping_error(ring, dma_test, 654 sizeof(struct b43legacy_txhdr_fw3), 1)) 655 goto err_kfree_txhdr_cache; 656 } 657 658 dma_unmap_single(dev->dev->dma_dev, dma_test, 659 sizeof(struct b43legacy_txhdr_fw3), 660 DMA_TO_DEVICE); 661 } 662 663 ring->mmio_base = b43legacy_dmacontroller_base(type, controller_index); 664 ring->index = controller_index; 665 if (for_tx) { 666 ring->tx = true; 667 ring->current_slot = -1; 668 } else { 669 if (ring->index == 0) { 670 ring->rx_buffersize = B43legacy_DMA0_RX_BUFFERSIZE; 671 ring->frameoffset = B43legacy_DMA0_RX_FRAMEOFFSET; 672 } else if (ring->index == 3) { 673 ring->rx_buffersize = B43legacy_DMA3_RX_BUFFERSIZE; 674 ring->frameoffset = B43legacy_DMA3_RX_FRAMEOFFSET; 675 } else 676 B43legacy_WARN_ON(1); 677 } 678 #ifdef CONFIG_B43LEGACY_DEBUG 679 ring->last_injected_overflow = jiffies; 680 #endif 681 682 err = alloc_ringmemory(ring); 683 if (err) 684 goto err_kfree_txhdr_cache; 685 err = dmacontroller_setup(ring); 686 if (err) 687 goto err_free_ringmemory; 688 689 out: 690 return ring; 691 692 err_free_ringmemory: 693 free_ringmemory(ring); 694 err_kfree_txhdr_cache: 695 kfree(ring->txhdr_cache); 696 err_kfree_ring: 697 kfree(ring); 698 ring = NULL; 699 goto out; 700 } 701 702 /* Main cleanup function. */ 703 static void b43legacy_destroy_dmaring(struct b43legacy_dmaring *ring) 704 { 705 if (!ring) 706 return; 707 708 b43legacydbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots:" 709 " %d/%d\n", (unsigned int)(ring->type), ring->mmio_base, 710 (ring->tx) ? "TX" : "RX", ring->max_used_slots, 711 ring->nr_slots); 712 /* Device IRQs are disabled prior entering this function, 713 * so no need to take care of concurrency with rx handler stuff. 714 */ 715 dmacontroller_cleanup(ring); 716 free_all_descbuffers(ring); 717 free_ringmemory(ring); 718 719 kfree(ring->txhdr_cache); 720 kfree(ring); 721 } 722 723 void b43legacy_dma_free(struct b43legacy_wldev *dev) 724 { 725 struct b43legacy_dma *dma; 726 727 if (b43legacy_using_pio(dev)) 728 return; 729 dma = &dev->dma; 730 731 b43legacy_destroy_dmaring(dma->rx_ring3); 732 dma->rx_ring3 = NULL; 733 b43legacy_destroy_dmaring(dma->rx_ring0); 734 dma->rx_ring0 = NULL; 735 736 b43legacy_destroy_dmaring(dma->tx_ring5); 737 dma->tx_ring5 = NULL; 738 b43legacy_destroy_dmaring(dma->tx_ring4); 739 dma->tx_ring4 = NULL; 740 b43legacy_destroy_dmaring(dma->tx_ring3); 741 dma->tx_ring3 = NULL; 742 b43legacy_destroy_dmaring(dma->tx_ring2); 743 dma->tx_ring2 = NULL; 744 b43legacy_destroy_dmaring(dma->tx_ring1); 745 dma->tx_ring1 = NULL; 746 b43legacy_destroy_dmaring(dma->tx_ring0); 747 dma->tx_ring0 = NULL; 748 } 749 750 int b43legacy_dma_init(struct b43legacy_wldev *dev) 751 { 752 struct b43legacy_dma *dma = &dev->dma; 753 struct b43legacy_dmaring *ring; 754 enum b43legacy_dmatype type = b43legacy_engine_type(dev); 755 int err; 756 757 err = dma_set_mask_and_coherent(dev->dev->dma_dev, DMA_BIT_MASK(type)); 758 if (err) { 759 #ifdef CONFIG_B43LEGACY_PIO 760 b43legacywarn(dev->wl, "DMA for this device not supported. " 761 "Falling back to PIO\n"); 762 dev->__using_pio = true; 763 return -EAGAIN; 764 #else 765 b43legacyerr(dev->wl, "DMA for this device not supported and " 766 "no PIO support compiled in\n"); 767 return -EOPNOTSUPP; 768 #endif 769 } 770 dma->translation = ssb_dma_translation(dev->dev); 771 772 err = -ENOMEM; 773 /* setup TX DMA channels. */ 774 ring = b43legacy_setup_dmaring(dev, 0, 1, type); 775 if (!ring) 776 goto out; 777 dma->tx_ring0 = ring; 778 779 ring = b43legacy_setup_dmaring(dev, 1, 1, type); 780 if (!ring) 781 goto err_destroy_tx0; 782 dma->tx_ring1 = ring; 783 784 ring = b43legacy_setup_dmaring(dev, 2, 1, type); 785 if (!ring) 786 goto err_destroy_tx1; 787 dma->tx_ring2 = ring; 788 789 ring = b43legacy_setup_dmaring(dev, 3, 1, type); 790 if (!ring) 791 goto err_destroy_tx2; 792 dma->tx_ring3 = ring; 793 794 ring = b43legacy_setup_dmaring(dev, 4, 1, type); 795 if (!ring) 796 goto err_destroy_tx3; 797 dma->tx_ring4 = ring; 798 799 ring = b43legacy_setup_dmaring(dev, 5, 1, type); 800 if (!ring) 801 goto err_destroy_tx4; 802 dma->tx_ring5 = ring; 803 804 /* setup RX DMA channels. */ 805 ring = b43legacy_setup_dmaring(dev, 0, 0, type); 806 if (!ring) 807 goto err_destroy_tx5; 808 dma->rx_ring0 = ring; 809 810 if (dev->dev->id.revision < 5) { 811 ring = b43legacy_setup_dmaring(dev, 3, 0, type); 812 if (!ring) 813 goto err_destroy_rx0; 814 dma->rx_ring3 = ring; 815 } 816 817 b43legacydbg(dev->wl, "%u-bit DMA initialized\n", (unsigned int)type); 818 err = 0; 819 out: 820 return err; 821 822 err_destroy_rx0: 823 b43legacy_destroy_dmaring(dma->rx_ring0); 824 dma->rx_ring0 = NULL; 825 err_destroy_tx5: 826 b43legacy_destroy_dmaring(dma->tx_ring5); 827 dma->tx_ring5 = NULL; 828 err_destroy_tx4: 829 b43legacy_destroy_dmaring(dma->tx_ring4); 830 dma->tx_ring4 = NULL; 831 err_destroy_tx3: 832 b43legacy_destroy_dmaring(dma->tx_ring3); 833 dma->tx_ring3 = NULL; 834 err_destroy_tx2: 835 b43legacy_destroy_dmaring(dma->tx_ring2); 836 dma->tx_ring2 = NULL; 837 err_destroy_tx1: 838 b43legacy_destroy_dmaring(dma->tx_ring1); 839 dma->tx_ring1 = NULL; 840 err_destroy_tx0: 841 b43legacy_destroy_dmaring(dma->tx_ring0); 842 dma->tx_ring0 = NULL; 843 goto out; 844 } 845 846 /* Generate a cookie for the TX header. */ 847 static u16 generate_cookie(struct b43legacy_dmaring *ring, 848 int slot) 849 { 850 u16 cookie = 0x1000; 851 852 /* Use the upper 4 bits of the cookie as 853 * DMA controller ID and store the slot number 854 * in the lower 12 bits. 855 * Note that the cookie must never be 0, as this 856 * is a special value used in RX path. 857 */ 858 switch (ring->index) { 859 case 0: 860 cookie = 0xA000; 861 break; 862 case 1: 863 cookie = 0xB000; 864 break; 865 case 2: 866 cookie = 0xC000; 867 break; 868 case 3: 869 cookie = 0xD000; 870 break; 871 case 4: 872 cookie = 0xE000; 873 break; 874 case 5: 875 cookie = 0xF000; 876 break; 877 } 878 B43legacy_WARN_ON(!(((u16)slot & 0xF000) == 0x0000)); 879 cookie |= (u16)slot; 880 881 return cookie; 882 } 883 884 /* Inspect a cookie and find out to which controller/slot it belongs. */ 885 static 886 struct b43legacy_dmaring *parse_cookie(struct b43legacy_wldev *dev, 887 u16 cookie, int *slot) 888 { 889 struct b43legacy_dma *dma = &dev->dma; 890 struct b43legacy_dmaring *ring = NULL; 891 892 switch (cookie & 0xF000) { 893 case 0xA000: 894 ring = dma->tx_ring0; 895 break; 896 case 0xB000: 897 ring = dma->tx_ring1; 898 break; 899 case 0xC000: 900 ring = dma->tx_ring2; 901 break; 902 case 0xD000: 903 ring = dma->tx_ring3; 904 break; 905 case 0xE000: 906 ring = dma->tx_ring4; 907 break; 908 case 0xF000: 909 ring = dma->tx_ring5; 910 break; 911 default: 912 B43legacy_WARN_ON(1); 913 } 914 *slot = (cookie & 0x0FFF); 915 B43legacy_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots)); 916 917 return ring; 918 } 919 920 static int dma_tx_fragment(struct b43legacy_dmaring *ring, 921 struct sk_buff **in_skb) 922 { 923 struct sk_buff *skb = *in_skb; 924 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 925 u8 *header; 926 int slot, old_top_slot, old_used_slots; 927 int err; 928 struct b43legacy_dmadesc32 *desc; 929 struct b43legacy_dmadesc_meta *meta; 930 struct b43legacy_dmadesc_meta *meta_hdr; 931 struct sk_buff *bounce_skb; 932 933 #define SLOTS_PER_PACKET 2 934 B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags != 0); 935 936 old_top_slot = ring->current_slot; 937 old_used_slots = ring->used_slots; 938 939 /* Get a slot for the header. */ 940 slot = request_slot(ring); 941 desc = op32_idx2desc(ring, slot, &meta_hdr); 942 memset(meta_hdr, 0, sizeof(*meta_hdr)); 943 944 header = &(ring->txhdr_cache[slot * sizeof( 945 struct b43legacy_txhdr_fw3)]); 946 err = b43legacy_generate_txhdr(ring->dev, header, 947 skb->data, skb->len, info, 948 generate_cookie(ring, slot)); 949 if (unlikely(err)) { 950 ring->current_slot = old_top_slot; 951 ring->used_slots = old_used_slots; 952 return err; 953 } 954 955 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header, 956 sizeof(struct b43legacy_txhdr_fw3), 1); 957 if (b43legacy_dma_mapping_error(ring, meta_hdr->dmaaddr, 958 sizeof(struct b43legacy_txhdr_fw3), 1)) { 959 ring->current_slot = old_top_slot; 960 ring->used_slots = old_used_slots; 961 return -EIO; 962 } 963 op32_fill_descriptor(ring, desc, meta_hdr->dmaaddr, 964 sizeof(struct b43legacy_txhdr_fw3), 1, 0, 0); 965 966 /* Get a slot for the payload. */ 967 slot = request_slot(ring); 968 desc = op32_idx2desc(ring, slot, &meta); 969 memset(meta, 0, sizeof(*meta)); 970 971 meta->skb = skb; 972 meta->is_last_fragment = true; 973 974 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1); 975 /* create a bounce buffer in zone_dma on mapping failure. */ 976 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) { 977 bounce_skb = alloc_skb(skb->len, GFP_KERNEL | GFP_DMA); 978 if (!bounce_skb) { 979 ring->current_slot = old_top_slot; 980 ring->used_slots = old_used_slots; 981 err = -ENOMEM; 982 goto out_unmap_hdr; 983 } 984 985 skb_put_data(bounce_skb, skb->data, skb->len); 986 memcpy(bounce_skb->cb, skb->cb, sizeof(skb->cb)); 987 bounce_skb->dev = skb->dev; 988 skb_set_queue_mapping(bounce_skb, skb_get_queue_mapping(skb)); 989 info = IEEE80211_SKB_CB(bounce_skb); 990 991 dev_kfree_skb_any(skb); 992 skb = bounce_skb; 993 *in_skb = bounce_skb; 994 meta->skb = skb; 995 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1); 996 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) { 997 ring->current_slot = old_top_slot; 998 ring->used_slots = old_used_slots; 999 err = -EIO; 1000 goto out_free_bounce; 1001 } 1002 } 1003 1004 op32_fill_descriptor(ring, desc, meta->dmaaddr, 1005 skb->len, 0, 1, 1); 1006 1007 wmb(); /* previous stuff MUST be done */ 1008 /* Now transfer the whole frame. */ 1009 op32_poke_tx(ring, next_slot(ring, slot)); 1010 return 0; 1011 1012 out_free_bounce: 1013 dev_kfree_skb_any(skb); 1014 out_unmap_hdr: 1015 unmap_descbuffer(ring, meta_hdr->dmaaddr, 1016 sizeof(struct b43legacy_txhdr_fw3), 1); 1017 return err; 1018 } 1019 1020 static inline 1021 int should_inject_overflow(struct b43legacy_dmaring *ring) 1022 { 1023 #ifdef CONFIG_B43LEGACY_DEBUG 1024 if (unlikely(b43legacy_debug(ring->dev, 1025 B43legacy_DBG_DMAOVERFLOW))) { 1026 /* Check if we should inject another ringbuffer overflow 1027 * to test handling of this situation in the stack. */ 1028 unsigned long next_overflow; 1029 1030 next_overflow = ring->last_injected_overflow + HZ; 1031 if (time_after(jiffies, next_overflow)) { 1032 ring->last_injected_overflow = jiffies; 1033 b43legacydbg(ring->dev->wl, 1034 "Injecting TX ring overflow on " 1035 "DMA controller %d\n", ring->index); 1036 return 1; 1037 } 1038 } 1039 #endif /* CONFIG_B43LEGACY_DEBUG */ 1040 return 0; 1041 } 1042 1043 int b43legacy_dma_tx(struct b43legacy_wldev *dev, 1044 struct sk_buff *skb) 1045 { 1046 struct b43legacy_dmaring *ring; 1047 int err = 0; 1048 1049 ring = priority_to_txring(dev, skb_get_queue_mapping(skb)); 1050 B43legacy_WARN_ON(!ring->tx); 1051 1052 if (unlikely(ring->stopped)) { 1053 /* We get here only because of a bug in mac80211. 1054 * Because of a race, one packet may be queued after 1055 * the queue is stopped, thus we got called when we shouldn't. 1056 * For now, just refuse the transmit. */ 1057 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE)) 1058 b43legacyerr(dev->wl, "Packet after queue stopped\n"); 1059 return -ENOSPC; 1060 } 1061 1062 if (WARN_ON(free_slots(ring) < SLOTS_PER_PACKET)) { 1063 /* If we get here, we have a real error with the queue 1064 * full, but queues not stopped. */ 1065 b43legacyerr(dev->wl, "DMA queue overflow\n"); 1066 return -ENOSPC; 1067 } 1068 1069 /* dma_tx_fragment might reallocate the skb, so invalidate pointers pointing 1070 * into the skb data or cb now. */ 1071 err = dma_tx_fragment(ring, &skb); 1072 if (unlikely(err == -ENOKEY)) { 1073 /* Drop this packet, as we don't have the encryption key 1074 * anymore and must not transmit it unencrypted. */ 1075 dev_kfree_skb_any(skb); 1076 return 0; 1077 } 1078 if (unlikely(err)) { 1079 b43legacyerr(dev->wl, "DMA tx mapping failure\n"); 1080 return err; 1081 } 1082 if ((free_slots(ring) < SLOTS_PER_PACKET) || 1083 should_inject_overflow(ring)) { 1084 /* This TX ring is full. */ 1085 unsigned int skb_mapping = skb_get_queue_mapping(skb); 1086 ieee80211_stop_queue(dev->wl->hw, skb_mapping); 1087 dev->wl->tx_queue_stopped[skb_mapping] = 1; 1088 ring->stopped = true; 1089 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE)) 1090 b43legacydbg(dev->wl, "Stopped TX ring %d\n", 1091 ring->index); 1092 } 1093 return err; 1094 } 1095 1096 void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev, 1097 const struct b43legacy_txstatus *status) 1098 { 1099 struct b43legacy_dmaring *ring; 1100 struct b43legacy_dmadesc_meta *meta; 1101 int retry_limit; 1102 int slot; 1103 int firstused; 1104 1105 ring = parse_cookie(dev, status->cookie, &slot); 1106 if (unlikely(!ring)) 1107 return; 1108 B43legacy_WARN_ON(!ring->tx); 1109 1110 /* Sanity check: TX packets are processed in-order on one ring. 1111 * Check if the slot deduced from the cookie really is the first 1112 * used slot. */ 1113 firstused = ring->current_slot - ring->used_slots + 1; 1114 if (firstused < 0) 1115 firstused = ring->nr_slots + firstused; 1116 if (unlikely(slot != firstused)) { 1117 /* This possibly is a firmware bug and will result in 1118 * malfunction, memory leaks and/or stall of DMA functionality. 1119 */ 1120 b43legacydbg(dev->wl, "Out of order TX status report on DMA " 1121 "ring %d. Expected %d, but got %d\n", 1122 ring->index, firstused, slot); 1123 return; 1124 } 1125 1126 while (1) { 1127 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); 1128 op32_idx2desc(ring, slot, &meta); 1129 1130 if (meta->skb) 1131 unmap_descbuffer(ring, meta->dmaaddr, 1132 meta->skb->len, 1); 1133 else 1134 unmap_descbuffer(ring, meta->dmaaddr, 1135 sizeof(struct b43legacy_txhdr_fw3), 1136 1); 1137 1138 if (meta->is_last_fragment) { 1139 struct ieee80211_tx_info *info; 1140 BUG_ON(!meta->skb); 1141 info = IEEE80211_SKB_CB(meta->skb); 1142 1143 /* preserve the confiured retry limit before clearing the status 1144 * The xmit function has overwritten the rc's value with the actual 1145 * retry limit done by the hardware */ 1146 retry_limit = info->status.rates[0].count; 1147 ieee80211_tx_info_clear_status(info); 1148 1149 if (status->acked) 1150 info->flags |= IEEE80211_TX_STAT_ACK; 1151 1152 if (status->rts_count > dev->wl->hw->conf.short_frame_max_tx_count) { 1153 /* 1154 * If the short retries (RTS, not data frame) have exceeded 1155 * the limit, the hw will not have tried the selected rate, 1156 * but will have used the fallback rate instead. 1157 * Don't let the rate control count attempts for the selected 1158 * rate in this case, otherwise the statistics will be off. 1159 */ 1160 info->status.rates[0].count = 0; 1161 info->status.rates[1].count = status->frame_count; 1162 } else { 1163 if (status->frame_count > retry_limit) { 1164 info->status.rates[0].count = retry_limit; 1165 info->status.rates[1].count = status->frame_count - 1166 retry_limit; 1167 1168 } else { 1169 info->status.rates[0].count = status->frame_count; 1170 info->status.rates[1].idx = -1; 1171 } 1172 } 1173 1174 /* Call back to inform the ieee80211 subsystem about the 1175 * status of the transmission. 1176 * Some fields of txstat are already filled in dma_tx(). 1177 */ 1178 ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb); 1179 /* skb is freed by ieee80211_tx_status_irqsafe() */ 1180 meta->skb = NULL; 1181 } else { 1182 /* No need to call free_descriptor_buffer here, as 1183 * this is only the txhdr, which is not allocated. 1184 */ 1185 B43legacy_WARN_ON(meta->skb != NULL); 1186 } 1187 1188 /* Everything unmapped and free'd. So it's not used anymore. */ 1189 ring->used_slots--; 1190 1191 if (meta->is_last_fragment) 1192 break; 1193 slot = next_slot(ring, slot); 1194 } 1195 dev->stats.last_tx = jiffies; 1196 if (ring->stopped) { 1197 B43legacy_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET); 1198 ring->stopped = false; 1199 } 1200 1201 if (dev->wl->tx_queue_stopped[ring->queue_prio]) { 1202 dev->wl->tx_queue_stopped[ring->queue_prio] = 0; 1203 } else { 1204 /* If the driver queue is running wake the corresponding 1205 * mac80211 queue. */ 1206 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio); 1207 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE)) 1208 b43legacydbg(dev->wl, "Woke up TX ring %d\n", 1209 ring->index); 1210 } 1211 /* Add work to the queue. */ 1212 ieee80211_queue_work(dev->wl->hw, &dev->wl->tx_work); 1213 } 1214 1215 static void dma_rx(struct b43legacy_dmaring *ring, 1216 int *slot) 1217 { 1218 struct b43legacy_dmadesc32 *desc; 1219 struct b43legacy_dmadesc_meta *meta; 1220 struct b43legacy_rxhdr_fw3 *rxhdr; 1221 struct sk_buff *skb; 1222 u16 len; 1223 int err; 1224 dma_addr_t dmaaddr; 1225 1226 desc = op32_idx2desc(ring, *slot, &meta); 1227 1228 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize); 1229 skb = meta->skb; 1230 1231 if (ring->index == 3) { 1232 /* We received an xmit status. */ 1233 struct b43legacy_hwtxstatus *hw = 1234 (struct b43legacy_hwtxstatus *)skb->data; 1235 int i = 0; 1236 1237 while (hw->cookie == 0) { 1238 if (i > 100) 1239 break; 1240 i++; 1241 udelay(2); 1242 barrier(); 1243 } 1244 b43legacy_handle_hwtxstatus(ring->dev, hw); 1245 /* recycle the descriptor buffer. */ 1246 sync_descbuffer_for_device(ring, meta->dmaaddr, 1247 ring->rx_buffersize); 1248 1249 return; 1250 } 1251 rxhdr = (struct b43legacy_rxhdr_fw3 *)skb->data; 1252 len = le16_to_cpu(rxhdr->frame_len); 1253 if (len == 0) { 1254 int i = 0; 1255 1256 do { 1257 udelay(2); 1258 barrier(); 1259 len = le16_to_cpu(rxhdr->frame_len); 1260 } while (len == 0 && i++ < 5); 1261 if (unlikely(len == 0)) { 1262 /* recycle the descriptor buffer. */ 1263 sync_descbuffer_for_device(ring, meta->dmaaddr, 1264 ring->rx_buffersize); 1265 goto drop; 1266 } 1267 } 1268 if (unlikely(len > ring->rx_buffersize)) { 1269 /* The data did not fit into one descriptor buffer 1270 * and is split over multiple buffers. 1271 * This should never happen, as we try to allocate buffers 1272 * big enough. So simply ignore this packet. 1273 */ 1274 int cnt = 0; 1275 s32 tmp = len; 1276 1277 while (1) { 1278 desc = op32_idx2desc(ring, *slot, &meta); 1279 /* recycle the descriptor buffer. */ 1280 sync_descbuffer_for_device(ring, meta->dmaaddr, 1281 ring->rx_buffersize); 1282 *slot = next_slot(ring, *slot); 1283 cnt++; 1284 tmp -= ring->rx_buffersize; 1285 if (tmp <= 0) 1286 break; 1287 } 1288 b43legacyerr(ring->dev->wl, "DMA RX buffer too small " 1289 "(len: %u, buffer: %u, nr-dropped: %d)\n", 1290 len, ring->rx_buffersize, cnt); 1291 goto drop; 1292 } 1293 1294 dmaaddr = meta->dmaaddr; 1295 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC); 1296 if (unlikely(err)) { 1297 b43legacydbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer()" 1298 " failed\n"); 1299 sync_descbuffer_for_device(ring, dmaaddr, 1300 ring->rx_buffersize); 1301 goto drop; 1302 } 1303 1304 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0); 1305 skb_put(skb, len + ring->frameoffset); 1306 skb_pull(skb, ring->frameoffset); 1307 1308 b43legacy_rx(ring->dev, skb, rxhdr); 1309 drop: 1310 return; 1311 } 1312 1313 void b43legacy_dma_rx(struct b43legacy_dmaring *ring) 1314 { 1315 int slot; 1316 int current_slot; 1317 int used_slots = 0; 1318 1319 B43legacy_WARN_ON(ring->tx); 1320 current_slot = op32_get_current_rxslot(ring); 1321 B43legacy_WARN_ON(!(current_slot >= 0 && current_slot < 1322 ring->nr_slots)); 1323 1324 slot = ring->current_slot; 1325 for (; slot != current_slot; slot = next_slot(ring, slot)) { 1326 dma_rx(ring, &slot); 1327 update_max_used_slots(ring, ++used_slots); 1328 } 1329 op32_set_current_rxslot(ring, slot); 1330 ring->current_slot = slot; 1331 } 1332 1333 static void b43legacy_dma_tx_suspend_ring(struct b43legacy_dmaring *ring) 1334 { 1335 B43legacy_WARN_ON(!ring->tx); 1336 op32_tx_suspend(ring); 1337 } 1338 1339 static void b43legacy_dma_tx_resume_ring(struct b43legacy_dmaring *ring) 1340 { 1341 B43legacy_WARN_ON(!ring->tx); 1342 op32_tx_resume(ring); 1343 } 1344 1345 void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev) 1346 { 1347 b43legacy_power_saving_ctl_bits(dev, -1, 1); 1348 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring0); 1349 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring1); 1350 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring2); 1351 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring3); 1352 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring4); 1353 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring5); 1354 } 1355 1356 void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev) 1357 { 1358 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring5); 1359 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring4); 1360 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring3); 1361 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring2); 1362 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring1); 1363 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring0); 1364 b43legacy_power_saving_ctl_bits(dev, -1, -1); 1365 } 1366