1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #include <linux/etherdevice.h>
7 #include <linux/of.h>
8 #include <linux/hwmon.h>
9 #include <linux/hwmon-sysfs.h>
10 #include <linux/thermal.h>
11 #include "mt7996.h"
12 #include "mac.h"
13 #include "mcu.h"
14 #include "coredump.h"
15 #include "eeprom.h"
16
17 static const struct ieee80211_iface_limit if_limits_global = {
18 .max = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS,
19 .types = BIT(NL80211_IFTYPE_STATION)
20 | BIT(NL80211_IFTYPE_ADHOC)
21 | BIT(NL80211_IFTYPE_AP)
22 #ifdef CONFIG_MAC80211_MESH
23 | BIT(NL80211_IFTYPE_MESH_POINT)
24 #endif
25 };
26
27 static const struct ieee80211_iface_combination if_comb_global = {
28 .limits = &if_limits_global,
29 .n_limits = 1,
30 .max_interfaces = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS,
31 .num_different_channels = MT7996_MAX_RADIOS,
32 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
33 BIT(NL80211_CHAN_WIDTH_20) |
34 BIT(NL80211_CHAN_WIDTH_40) |
35 BIT(NL80211_CHAN_WIDTH_80) |
36 BIT(NL80211_CHAN_WIDTH_160),
37 };
38
39 static const struct ieee80211_iface_combination if_comb_global_7992 = {
40 .limits = &if_limits_global,
41 .n_limits = 1,
42 .max_interfaces = 32,
43 .num_different_channels = MT7996_MAX_RADIOS - 1,
44 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
45 BIT(NL80211_CHAN_WIDTH_20) |
46 BIT(NL80211_CHAN_WIDTH_40) |
47 BIT(NL80211_CHAN_WIDTH_80) |
48 BIT(NL80211_CHAN_WIDTH_160),
49 };
50
51 static const struct ieee80211_iface_limit if_limits[] = {
52 {
53 .max = 16,
54 .types = BIT(NL80211_IFTYPE_AP)
55 #ifdef CONFIG_MAC80211_MESH
56 | BIT(NL80211_IFTYPE_MESH_POINT)
57 #endif
58 }, {
59 .max = MT7996_MAX_INTERFACES,
60 .types = BIT(NL80211_IFTYPE_STATION)
61 }
62 };
63
64 static const struct ieee80211_iface_combination if_comb = {
65 .limits = if_limits,
66 .n_limits = ARRAY_SIZE(if_limits),
67 .max_interfaces = MT7996_MAX_INTERFACES,
68 .num_different_channels = 1,
69 .beacon_int_infra_match = true,
70 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
71 BIT(NL80211_CHAN_WIDTH_20) |
72 BIT(NL80211_CHAN_WIDTH_40) |
73 BIT(NL80211_CHAN_WIDTH_80) |
74 BIT(NL80211_CHAN_WIDTH_160),
75 .beacon_int_min_gcd = 100,
76 };
77
78 static const u8 if_types_ext_capa_ap[] = {
79 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING,
80 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT,
81 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF,
82 };
83
84 static const struct wiphy_iftype_ext_capab iftypes_ext_capa[] = {
85 {
86 .iftype = NL80211_IFTYPE_AP,
87 .extended_capabilities = if_types_ext_capa_ap,
88 .extended_capabilities_mask = if_types_ext_capa_ap,
89 .extended_capabilities_len = sizeof(if_types_ext_capa_ap),
90 .eml_capabilities = IEEE80211_EML_CAP_EMLSR_SUPP,
91 .mld_capa_and_ops =
92 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS,
93 MT7996_MAX_RADIOS - 1),
94 }, {
95 .iftype = NL80211_IFTYPE_STATION,
96 .extended_capabilities = if_types_ext_capa_ap,
97 .extended_capabilities_mask = if_types_ext_capa_ap,
98 .extended_capabilities_len = sizeof(if_types_ext_capa_ap),
99 .mld_capa_and_ops =
100 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_FREQ_SEP_TYPE_IND, 1) |
101 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS,
102 MT7996_MAX_RADIOS - 1),
103 },
104 };
105
mt7996_thermal_temp_show(struct device * dev,struct device_attribute * attr,char * buf)106 static ssize_t mt7996_thermal_temp_show(struct device *dev,
107 struct device_attribute *attr,
108 char *buf)
109 {
110 struct mt7996_phy *phy = dev_get_drvdata(dev);
111 int i = to_sensor_dev_attr(attr)->index;
112 int temperature;
113
114 switch (i) {
115 case 0:
116 temperature = mt7996_mcu_get_temperature(phy);
117 if (temperature < 0)
118 return temperature;
119 /* display in millidegree celcius */
120 return sprintf(buf, "%u\n", temperature * 1000);
121 case 1:
122 case 2:
123 return sprintf(buf, "%u\n",
124 phy->throttle_temp[i - 1] * 1000);
125 case 3:
126 return sprintf(buf, "%hhu\n", phy->throttle_state);
127 default:
128 return -EINVAL;
129 }
130 }
131
mt7996_thermal_temp_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)132 static ssize_t mt7996_thermal_temp_store(struct device *dev,
133 struct device_attribute *attr,
134 const char *buf, size_t count)
135 {
136 struct mt7996_phy *phy = dev_get_drvdata(dev);
137 int ret, i = to_sensor_dev_attr(attr)->index;
138 long val;
139
140 ret = kstrtol(buf, 10, &val);
141 if (ret < 0)
142 return ret;
143
144 mutex_lock(&phy->dev->mt76.mutex);
145 val = DIV_ROUND_CLOSEST(clamp_val(val, 40 * 1000, 130 * 1000), 1000);
146
147 /* add a safety margin ~10 */
148 if ((i - 1 == MT7996_CRIT_TEMP_IDX &&
149 val > phy->throttle_temp[MT7996_MAX_TEMP_IDX] - 10) ||
150 (i - 1 == MT7996_MAX_TEMP_IDX &&
151 val - 10 < phy->throttle_temp[MT7996_CRIT_TEMP_IDX])) {
152 dev_err(phy->dev->mt76.dev,
153 "temp1_max shall be 10 degrees higher than temp1_crit.");
154 mutex_unlock(&phy->dev->mt76.mutex);
155 return -EINVAL;
156 }
157
158 phy->throttle_temp[i - 1] = val;
159 mutex_unlock(&phy->dev->mt76.mutex);
160
161 ret = mt7996_mcu_set_thermal_protect(phy, true);
162 if (ret)
163 return ret;
164
165 return count;
166 }
167
168 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7996_thermal_temp, 0);
169 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7996_thermal_temp, 1);
170 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7996_thermal_temp, 2);
171 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7996_thermal_temp, 3);
172
173 static struct attribute *mt7996_hwmon_attrs[] = {
174 &sensor_dev_attr_temp1_input.dev_attr.attr,
175 &sensor_dev_attr_temp1_crit.dev_attr.attr,
176 &sensor_dev_attr_temp1_max.dev_attr.attr,
177 &sensor_dev_attr_throttle1.dev_attr.attr,
178 NULL,
179 };
180 ATTRIBUTE_GROUPS(mt7996_hwmon);
181
182 static int
mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)183 mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev,
184 unsigned long *state)
185 {
186 *state = MT7996_CDEV_THROTTLE_MAX;
187
188 return 0;
189 }
190
191 static int
mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)192 mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev,
193 unsigned long *state)
194 {
195 struct mt7996_phy *phy = cdev->devdata;
196
197 *state = phy->cdev_state;
198
199 return 0;
200 }
201
202 static int
mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long state)203 mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev,
204 unsigned long state)
205 {
206 struct mt7996_phy *phy = cdev->devdata;
207 u8 throttling = MT7996_THERMAL_THROTTLE_MAX - state;
208 int ret;
209
210 if (state > MT7996_CDEV_THROTTLE_MAX) {
211 dev_err(phy->dev->mt76.dev,
212 "please specify a valid throttling state\n");
213 return -EINVAL;
214 }
215
216 if (state == phy->cdev_state)
217 return 0;
218
219 /* cooling_device convention: 0 = no cooling, more = more cooling
220 * mcu convention: 1 = max cooling, more = less cooling
221 */
222 ret = mt7996_mcu_set_thermal_throttling(phy, throttling);
223 if (ret)
224 return ret;
225
226 phy->cdev_state = state;
227
228 return 0;
229 }
230
231 static const struct thermal_cooling_device_ops mt7996_thermal_ops = {
232 .get_max_state = mt7996_thermal_get_max_throttle_state,
233 .get_cur_state = mt7996_thermal_get_cur_throttle_state,
234 .set_cur_state = mt7996_thermal_set_cur_throttle_state,
235 };
236
mt7996_unregister_thermal(struct mt7996_phy * phy)237 static void mt7996_unregister_thermal(struct mt7996_phy *phy)
238 {
239 struct wiphy *wiphy = phy->mt76->hw->wiphy;
240 char name[sizeof("cooling_deviceXXX")];
241
242 if (!phy->cdev)
243 return;
244
245 snprintf(name, sizeof(name), "cooling_device%d", phy->mt76->band_idx);
246 sysfs_remove_link(&wiphy->dev.kobj, name);
247 thermal_cooling_device_unregister(phy->cdev);
248 }
249
mt7996_thermal_init(struct mt7996_phy * phy)250 static int mt7996_thermal_init(struct mt7996_phy *phy)
251 {
252 struct wiphy *wiphy = phy->mt76->hw->wiphy;
253 char cname[sizeof("cooling_deviceXXX")];
254 struct thermal_cooling_device *cdev;
255 struct device *hwmon;
256 const char *name;
257
258 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7996_%s.%d",
259 wiphy_name(wiphy), phy->mt76->band_idx);
260 if (!name)
261 return -ENOMEM;
262
263 snprintf(cname, sizeof(cname), "cooling_device%d", phy->mt76->band_idx);
264
265 cdev = thermal_cooling_device_register(name, phy, &mt7996_thermal_ops);
266 if (!IS_ERR(cdev)) {
267 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj,
268 cname) < 0)
269 thermal_cooling_device_unregister(cdev);
270 else
271 phy->cdev = cdev;
272 }
273
274 /* initialize critical/maximum high temperature */
275 phy->throttle_temp[MT7996_CRIT_TEMP_IDX] = MT7996_CRIT_TEMP;
276 phy->throttle_temp[MT7996_MAX_TEMP_IDX] = MT7996_MAX_TEMP;
277
278 if (!IS_REACHABLE(CONFIG_HWMON))
279 return 0;
280
281 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy,
282 mt7996_hwmon_groups);
283
284 if (IS_ERR(hwmon))
285 return PTR_ERR(hwmon);
286
287 return 0;
288 }
289
mt7996_led_set_config(struct led_classdev * led_cdev,u8 delay_on,u8 delay_off)290 static void mt7996_led_set_config(struct led_classdev *led_cdev,
291 u8 delay_on, u8 delay_off)
292 {
293 struct mt7996_dev *dev;
294 struct mt76_phy *mphy;
295 u32 val;
296
297 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev);
298 dev = container_of(mphy->dev, struct mt7996_dev, mt76);
299
300 /* select TX blink mode, 2: only data frames */
301 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2);
302
303 /* enable LED */
304 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1);
305
306 /* set LED Tx blink on/off time */
307 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) |
308 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off);
309 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val);
310
311 /* turn LED off */
312 if (delay_off == 0xff && delay_on == 0x0) {
313 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK;
314 } else {
315 /* control LED */
316 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK;
317 if (mphy->band_idx == MT_BAND1)
318 val |= MT_LED_CTRL_BLINK_BAND_SEL;
319 }
320
321 if (mphy->leds.al)
322 val |= MT_LED_CTRL_POLARITY;
323
324 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val);
325 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK);
326 }
327
mt7996_led_set_blink(struct led_classdev * led_cdev,unsigned long * delay_on,unsigned long * delay_off)328 static int mt7996_led_set_blink(struct led_classdev *led_cdev,
329 unsigned long *delay_on,
330 unsigned long *delay_off)
331 {
332 u16 delta_on = 0, delta_off = 0;
333
334 #define HW_TICK 10
335 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK)
336
337 if (*delay_on)
338 delta_on = TO_HW_TICK(*delay_on);
339 if (*delay_off)
340 delta_off = TO_HW_TICK(*delay_off);
341
342 mt7996_led_set_config(led_cdev, delta_on, delta_off);
343
344 return 0;
345 }
346
mt7996_led_set_brightness(struct led_classdev * led_cdev,enum led_brightness brightness)347 static void mt7996_led_set_brightness(struct led_classdev *led_cdev,
348 enum led_brightness brightness)
349 {
350 if (!brightness)
351 mt7996_led_set_config(led_cdev, 0, 0xff);
352 else
353 mt7996_led_set_config(led_cdev, 0xff, 0);
354 }
355
__mt7996_init_txpower(struct mt7996_phy * phy,struct ieee80211_supported_band * sband)356 static void __mt7996_init_txpower(struct mt7996_phy *phy,
357 struct ieee80211_supported_band *sband)
358 {
359 struct mt7996_dev *dev = phy->dev;
360 int i, n_chains = hweight16(phy->mt76->chainmask);
361 int path_delta = mt76_tx_power_path_delta(n_chains);
362 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band);
363 struct mt76_power_limits limits;
364
365 for (i = 0; i < sband->n_channels; i++) {
366 struct ieee80211_channel *chan = &sband->channels[i];
367 int target_power = mt7996_eeprom_get_target_power(dev, chan);
368
369 target_power += pwr_delta;
370 target_power = mt76_get_rate_power_limits(phy->mt76, chan,
371 &limits,
372 target_power);
373 target_power += path_delta;
374 target_power = DIV_ROUND_UP(target_power, 2);
375 chan->max_power = min_t(int, chan->max_reg_power,
376 target_power);
377 chan->orig_mpwr = target_power;
378 }
379 }
380
mt7996_init_txpower(struct mt7996_phy * phy)381 void mt7996_init_txpower(struct mt7996_phy *phy)
382 {
383 if (!phy)
384 return;
385
386 if (phy->mt76->cap.has_2ghz)
387 __mt7996_init_txpower(phy, &phy->mt76->sband_2g.sband);
388 if (phy->mt76->cap.has_5ghz)
389 __mt7996_init_txpower(phy, &phy->mt76->sband_5g.sband);
390 if (phy->mt76->cap.has_6ghz)
391 __mt7996_init_txpower(phy, &phy->mt76->sband_6g.sband);
392 }
393
394 static void
mt7996_regd_notifier(struct wiphy * wiphy,struct regulatory_request * request)395 mt7996_regd_notifier(struct wiphy *wiphy,
396 struct regulatory_request *request)
397 {
398 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
399 struct mt7996_dev *dev = mt7996_hw_dev(hw);
400 struct mt7996_phy *phy;
401
402 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2));
403 dev->mt76.region = request->dfs_region;
404
405 mt7996_for_each_phy(dev, phy) {
406 if (dev->mt76.region == NL80211_DFS_UNSET)
407 mt7996_mcu_rdd_background_enable(phy, NULL);
408
409 mt7996_init_txpower(phy);
410 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN;
411 mt7996_dfs_init_radar_detector(phy);
412 }
413 }
414
415 static void
mt7996_init_wiphy_band(struct ieee80211_hw * hw,struct mt7996_phy * phy)416 mt7996_init_wiphy_band(struct ieee80211_hw *hw, struct mt7996_phy *phy)
417 {
418 struct mt7996_dev *dev = phy->dev;
419 struct wiphy *wiphy = hw->wiphy;
420 int n_radios = hw->wiphy->n_radio;
421 struct wiphy_radio_freq_range *freq = &dev->radio_freqs[n_radios];
422 struct wiphy_radio *radio = &dev->radios[n_radios];
423
424 phy->slottime = 9;
425 phy->beacon_rate = -1;
426 phy->rxfilter = MT_WF_RFCR_DROP_OTHER_UC;
427
428 if (phy->mt76->cap.has_2ghz) {
429 phy->mt76->sband_2g.sband.ht_cap.cap |=
430 IEEE80211_HT_CAP_LDPC_CODING |
431 IEEE80211_HT_CAP_MAX_AMSDU;
432 phy->mt76->sband_2g.sband.ht_cap.ampdu_density =
433 IEEE80211_HT_MPDU_DENSITY_2;
434 freq->start_freq = 2400000;
435 freq->end_freq = 2500000;
436 } else if (phy->mt76->cap.has_5ghz) {
437 phy->mt76->sband_5g.sband.ht_cap.cap |=
438 IEEE80211_HT_CAP_LDPC_CODING |
439 IEEE80211_HT_CAP_MAX_AMSDU;
440
441 phy->mt76->sband_5g.sband.vht_cap.cap |=
442 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
443 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
444 IEEE80211_VHT_CAP_SHORT_GI_160 |
445 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
446 phy->mt76->sband_5g.sband.ht_cap.ampdu_density =
447 IEEE80211_HT_MPDU_DENSITY_1;
448
449 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
450 freq->start_freq = 5000000;
451 freq->end_freq = 5900000;
452 } else if (phy->mt76->cap.has_6ghz) {
453 freq->start_freq = 5900000;
454 freq->end_freq = 7200000;
455 } else {
456 return;
457 }
458
459 dev->radio_phy[n_radios] = phy;
460 radio->freq_range = freq;
461 radio->n_freq_range = 1;
462 radio->iface_combinations = &if_comb;
463 radio->n_iface_combinations = 1;
464 memcpy(dev->radio_addrs[n_radios].addr, phy->mt76->macaddr, ETH_ALEN);
465 hw->wiphy->n_addresses++;
466 hw->wiphy->n_radio++;
467
468 wiphy->available_antennas_rx |= phy->mt76->chainmask;
469 wiphy->available_antennas_tx |= phy->mt76->chainmask;
470
471 mt76_set_stream_caps(phy->mt76, true);
472 mt7996_set_stream_vht_txbf_caps(phy);
473 mt7996_set_stream_he_eht_caps(phy);
474 mt7996_init_txpower(phy);
475 }
476
477 static void
mt7996_init_wiphy(struct ieee80211_hw * hw,struct mtk_wed_device * wed)478 mt7996_init_wiphy(struct ieee80211_hw *hw, struct mtk_wed_device *wed)
479 {
480 struct mt7996_dev *dev = mt7996_hw_dev(hw);
481 struct mt76_dev *mdev = &dev->mt76;
482 struct wiphy *wiphy = hw->wiphy;
483 u16 max_subframes = dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT :
484 IEEE80211_MAX_AMPDU_BUF_HE;
485
486 hw->queues = 4;
487 hw->max_rx_aggregation_subframes = max_subframes;
488 hw->max_tx_aggregation_subframes = max_subframes;
489 if (is_mt7990(mdev) && dev->has_eht)
490 hw->max_tx_aggregation_subframes = 512;
491
492 hw->netdev_features = NETIF_F_RXCSUM;
493 if (mtk_wed_device_active(wed) || mt76_npu_device_active(mdev))
494 hw->netdev_features |= NETIF_F_HW_TC;
495
496 hw->radiotap_timestamp.units_pos =
497 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
498
499 hw->sta_data_size = sizeof(struct mt7996_sta);
500 hw->vif_data_size = sizeof(struct mt7996_vif);
501 hw->chanctx_data_size = sizeof(struct mt76_chanctx);
502
503 wiphy->iface_combinations = is_mt7996(&dev->mt76) ? &if_comb_global :
504 &if_comb_global_7992;
505 wiphy->n_iface_combinations = 1;
506
507 wiphy->radio = dev->radios;
508 wiphy->addresses = dev->radio_addrs;
509
510 wiphy->reg_notifier = mt7996_regd_notifier;
511 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH |
512 WIPHY_FLAG_SUPPORTS_MLO;
513 wiphy->mbssid_max_interfaces = 16;
514 wiphy->iftype_ext_capab = iftypes_ext_capa;
515 wiphy->num_iftype_ext_capab = ARRAY_SIZE(iftypes_ext_capa);
516
517 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR);
518 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
519 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY);
520 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT);
521 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT);
522 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE);
523 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP);
524 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY);
525 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT);
526 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
527 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER);
528 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
529
530 if (mt7996_eeprom_has_background_radar(dev) &&
531 (!mdev->dev->of_node ||
532 !of_property_read_bool(mdev->dev->of_node,
533 "mediatek,disable-radar-background")))
534 wiphy_ext_feature_set(wiphy,
535 NL80211_EXT_FEATURE_RADAR_BACKGROUND);
536
537 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
538 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD);
539 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD);
540 ieee80211_hw_set(hw, NO_VIRTUAL_MONITOR);
541 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
542 ieee80211_hw_set(hw, CHANCTX_STA_CSA);
543
544 hw->max_tx_fragments = 4;
545 wiphy->txq_memory_limit = 32 << 20; /* 32 MiB */
546
547 /* init led callbacks */
548 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
549 dev->mphy.leds.cdev.brightness_set = mt7996_led_set_brightness;
550 dev->mphy.leds.cdev.blink_set = mt7996_led_set_blink;
551 }
552
553 wiphy->max_scan_ssids = 4;
554 wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
555
556 mt7996_init_wiphy_band(hw, &dev->phy);
557 }
558
559 static void
mt7996_mac_init_band(struct mt7996_dev * dev,u8 band)560 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band)
561 {
562 u32 mask, set;
563
564 if (!mt7996_band_valid(dev, band))
565 return;
566
567 /* clear estimated value of EIFS for Rx duration & OBSS time */
568 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR);
569
570 /* clear backoff time for Rx duration */
571 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band),
572 MT_WF_RMAC_MIB_NONQOSD_BACKOFF);
573 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band),
574 MT_WF_RMAC_MIB_QOS01_BACKOFF);
575 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band),
576 MT_WF_RMAC_MIB_QOS23_BACKOFF);
577
578 /* clear backoff time for Tx duration */
579 mt76_clear(dev, MT_WTBLOFF_ACR(band),
580 MT_WTBLOFF_ADM_BACKOFFTIME);
581
582 /* clear backoff time and set software compensation for OBSS time */
583 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET;
584 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) |
585 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4);
586 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set);
587
588 /* filter out non-resp frames and get instanstaeous signal reporting */
589 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM;
590 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) |
591 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3);
592 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set);
593
594 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than
595 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set.
596 */
597 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H);
598
599 if (!is_mt7996(&dev->mt76))
600 mt7996_mcu_set_bssid_mapping_addr(&dev->mt76, band);
601 }
602
mt7996_mac_init_basic_rates(struct mt7996_dev * dev)603 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev)
604 {
605 int i;
606
607 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) {
608 u16 rate = mt76_rates[i].hw_value;
609 /* odd index for driver, even index for firmware */
610 u16 idx = MT7996_BASIC_RATES_TBL + 2 * i;
611
612 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) |
613 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0));
614 mt7996_mcu_set_fixed_rate_table(&dev->phy, idx, rate, false);
615 }
616 }
617
mt7996_mac_init(struct mt7996_dev * dev)618 void mt7996_mac_init(struct mt7996_dev *dev)
619 {
620 #define HIF_TXD_V2_1 0x21
621 int i, rx_path_type;
622
623 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT);
624
625 for (i = 0; i < mt7996_wtbl_size(dev); i++)
626 mt7996_mac_wtbl_update(dev, i,
627 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
628
629 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
630 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2;
631 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4);
632 }
633
634 /* rro module init */
635 if (dev->hif2) {
636 if (mt76_npu_device_active(&dev->mt76))
637 rx_path_type = is_mt7996(&dev->mt76) ? 6 : 8;
638 else
639 rx_path_type = is_mt7996(&dev->mt76) ? 2 : 7;
640 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE,
641 rx_path_type);
642 } else {
643 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 0);
644 }
645
646 if (mt7996_has_hwrro(dev)) {
647 u16 timeout;
648
649 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128;
650 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout);
651 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE,
652 is_mt7996(&dev->mt76) ? 1 : 2);
653 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH,
654 !is_mt7996(&dev->mt76));
655 } else {
656 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3);
657 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1);
658 }
659
660 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
661 MCU_WA_PARAM_HW_PATH_HIF_VER,
662 HIF_TXD_V2_1, 0);
663
664 for (i = MT_BAND0; i <= MT_BAND2; i++)
665 mt7996_mac_init_band(dev, i);
666
667 mt7996_mac_init_basic_rates(dev);
668 }
669
mt7996_txbf_init(struct mt7996_dev * dev)670 int mt7996_txbf_init(struct mt7996_dev *dev)
671 {
672 int ret;
673
674 if (mt7996_band_valid(dev, MT_BAND1) ||
675 mt7996_band_valid(dev, MT_BAND2)) {
676 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL);
677 if (ret)
678 return ret;
679 }
680
681 /* trigger sounding packets */
682 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON);
683 if (ret)
684 return ret;
685
686 /* enable eBF */
687 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE);
688 }
689
mt7996_register_phy(struct mt7996_dev * dev,enum mt76_band_id band)690 static int mt7996_register_phy(struct mt7996_dev *dev, enum mt76_band_id band)
691 {
692 struct mt7996_phy *phy;
693 struct mt76_phy *mphy;
694 u32 mac_ofs, hif1_ofs = 0;
695 int ret;
696 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
697
698 if (!mt7996_band_valid(dev, band))
699 return 0;
700
701 if (dev->hif2 &&
702 ((is_mt7992(&dev->mt76) && band == MT_BAND1) ||
703 (is_mt7996(&dev->mt76) && band == MT_BAND2 &&
704 !mt76_npu_device_active(&dev->mt76)))) {
705 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
706 wed = &dev->mt76.mmio.wed_hif2;
707 }
708
709 mphy = mt76_alloc_radio_phy(&dev->mt76, sizeof(*phy), band);
710 if (!mphy)
711 return -ENOMEM;
712
713 phy = mphy->priv;
714 phy->dev = dev;
715 phy->mt76 = mphy;
716 mphy->dev->phys[band] = mphy;
717
718 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work);
719
720 ret = mt7996_eeprom_parse_hw_cap(dev, phy);
721 if (ret)
722 goto error;
723
724 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2;
725 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN);
726 /* Make the extra PHY MAC address local without overlapping with
727 * the usual MAC address allocation scheme on multiple virtual interfaces
728 */
729 if (!is_valid_ether_addr(mphy->macaddr)) {
730 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
731 ETH_ALEN);
732 mphy->macaddr[0] |= 2;
733 mphy->macaddr[0] ^= BIT(7);
734 if (band == MT_BAND2)
735 mphy->macaddr[0] ^= BIT(6);
736 }
737 ret = mt76_eeprom_override(mphy);
738 if (ret)
739 goto error;
740
741 /* init wiphy according to mphy and phy */
742 mt7996_init_wiphy_band(mphy->hw, phy);
743
744 if (is_mt7996(&dev->mt76) &&
745 ((band == MT_BAND1 && !dev->hif2) ||
746 (band == MT_BAND2 && mt76_npu_device_active(&dev->mt76)))) {
747 int i;
748
749 for (i = 0; i <= MT_TXQ_PSD; i++)
750 mphy->q_tx[i] = dev->mt76.phys[band - 1]->q_tx[0];
751 } else {
752 int size = is_mt7996(&dev->mt76) &&
753 mt76_npu_device_active(&dev->mt76)
754 ? MT7996_NPU_TX_RING_SIZE / 2 : MT7996_TX_RING_SIZE;
755
756 ret = mt7996_init_tx_queues(mphy->priv, MT_TXQ_ID(band), size,
757 MT_TXQ_RING_BASE(band) + hif1_ofs,
758 wed);
759 if (ret)
760 goto error;
761 }
762
763 ret = mt76_register_phy(mphy, true, mt76_rates,
764 ARRAY_SIZE(mt76_rates));
765 if (ret)
766 goto error;
767
768 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) {
769 mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TX_RX_DONE_EXT);
770 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2,
771 MT_INT_TX_RX_DONE_EXT);
772 }
773
774 return 0;
775
776 error:
777 mphy->dev->phys[band] = NULL;
778 return ret;
779 }
780
781 static void
mt7996_unregister_phy(struct mt7996_phy * phy)782 mt7996_unregister_phy(struct mt7996_phy *phy)
783 {
784 if (phy)
785 mt7996_unregister_thermal(phy);
786 }
787
mt7996_init_work(struct work_struct * work)788 static void mt7996_init_work(struct work_struct *work)
789 {
790 struct mt7996_dev *dev = container_of(work, struct mt7996_dev,
791 init_work);
792
793 mt7996_mcu_set_eeprom(dev);
794 mt7996_mac_init(dev);
795 mt7996_txbf_init(dev);
796
797 if (!is_mt7990(&dev->mt76))
798 mt7996_mcu_set_dup_wtbl(dev);
799 }
800
mt7996_wfsys_reset(struct mt7996_dev * dev)801 void mt7996_wfsys_reset(struct mt7996_dev *dev)
802 {
803 if (!is_mt7990(&dev->mt76)) {
804 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
805 msleep(20);
806
807 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
808 msleep(20);
809
810 return;
811 }
812
813 if (!dev->recovery.hw_full_reset)
814 return;
815
816 mt76_set(dev, MT_WF_SUBSYS_RST,
817 MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT |
818 MT_WF_SUBSYS_RST_BYPASS_WFDMA_SLP_PROT |
819 MT_WF_SUBSYS_RST_BYPASS_WFDMA2_SLP_PROT);
820 mt76_rmw(dev, MT_WF_SUBSYS_RST,
821 MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE,
822 u32_encode_bits(0x20, MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE));
823 mt76_clear(dev, MT_WF_L05_RST, MT_WF_L05_RST_WF_RST_MASK);
824 mt76_set(dev, MT_WF_SUBSYS_RST, MT_WF_SUBSYS_RST_WHOLE_PATH_RST);
825 msleep(20);
826
827 if (mt76_poll(dev, MT_WF_L05_RST, MT_WF_L05_RST_WF_RST_MASK, 0x1a, 1000))
828 return;
829
830 dev_err(dev->mt76.dev, "wfsys reset fail\n");
831 }
832
mt7996_rro_hw_init_v3(struct mt7996_dev * dev)833 static void mt7996_rro_hw_init_v3(struct mt7996_dev *dev)
834 {
835 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
836 u32 session_id;
837
838 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1)
839 return;
840
841 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
842 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) {
843 wed->wlan.ind_cmd.win_size =
844 ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6;
845 if (is_mt7996(&dev->mt76))
846 wed->wlan.ind_cmd.particular_sid =
847 MT7996_RRO_MAX_SESSION;
848 else
849 wed->wlan.ind_cmd.particular_sid = 1;
850 wed->wlan.ind_cmd.particular_se_phys =
851 dev->wed_rro.session.phy_addr;
852 wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN;
853 wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL;
854 }
855 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */
856
857 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) {
858 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00);
859 mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1,
860 MT_RRO_IND_CMD_SIGNATURE_BASE1_EN);
861 } else {
862 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0);
863 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 0);
864 }
865
866 /* particular session configure */
867 /* use max session idx + 1 as particular session id */
868 mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr);
869
870 session_id = is_mt7996(&dev->mt76) ? MT7996_RRO_MAX_SESSION : 1;
871 mt76_wr(dev, MT_RRO_PARTICULAR_CFG1,
872 MT_RRO_PARTICULAR_CONFG_EN |
873 FIELD_PREP(MT_RRO_PARTICULAR_SID, session_id));
874 }
875
mt7996_rro_hw_init(struct mt7996_dev * dev)876 void mt7996_rro_hw_init(struct mt7996_dev *dev)
877 {
878 u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0;
879 int i;
880
881 if (!mt7996_has_hwrro(dev))
882 return;
883
884 INIT_LIST_HEAD(&dev->wed_rro.page_cache);
885 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.page_map); i++)
886 INIT_LIST_HEAD(&dev->wed_rro.page_map[i]);
887
888 if (!is_mt7996(&dev->mt76)) {
889 reg = MT_RRO_MSDU_PG_SEG_ADDR0;
890
891 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) {
892 mt76_clear(dev, MT_RRO_3_0_EMU_CONF,
893 MT_RRO_3_0_EMU_CONF_EN_MASK);
894 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG,
895 MT_RRO_3_1_GLOBAL_CONFIG_RXDMAD_SEL);
896 if (!mtk_wed_device_active(&dev->mt76.mmio.wed) &&
897 !mt76_npu_device_active(&dev->mt76)) {
898 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG,
899 MT_RRO_3_1_GLOBAL_CONFIG_RX_DIDX_WR_EN |
900 MT_RRO_3_1_GLOBAL_CONFIG_RX_CIDX_RD_EN);
901 mt76_wr(dev, MT_RRO_RX_RING_AP_CIDX_ADDR,
902 dev->wed_rro.emi_rings_cpu.phy_addr >> 4);
903 mt76_wr(dev, MT_RRO_RX_RING_AP_DIDX_ADDR,
904 dev->wed_rro.emi_rings_dma.phy_addr >> 4);
905 }
906 } else {
907 /* set emul 3.0 function */
908 mt76_set(dev, MT_RRO_3_0_EMU_CONF, MT_RRO_3_0_EMU_CONF_EN_MASK);
909
910 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE0,
911 dev->wed_rro.addr_elem[0].phy_addr);
912 }
913
914 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG,
915 MT_RRO_3_1_GLOBAL_CONFIG_INTERLEAVE_EN);
916
917 /* setup Msdu page address */
918 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) {
919 mt76_wr(dev, reg,
920 dev->wed_rro.msdu_pg[i].phy_addr >> 4);
921 reg += 4;
922 }
923 } else {
924 /* TODO: remove line after WM has set */
925 mt76_clear(dev, WF_RRO_AXI_MST_CFG,
926 WF_RRO_AXI_MST_CFG_DIDX_OK);
927
928 /* setup BA bitmap cache address */
929 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0,
930 dev->wed_rro.ba_bitmap[0].phy_addr);
931 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0);
932 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0,
933 dev->wed_rro.ba_bitmap[1].phy_addr);
934 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0);
935
936 /* Setup Address element address */
937 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
938 mt76_wr(dev, reg,
939 dev->wed_rro.addr_elem[i].phy_addr >> 4);
940 reg += 4;
941 }
942
943 /* Setup Address element address - separate address segment
944 * mode.
945 */
946 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1,
947 MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE);
948 }
949
950 mt7996_rro_hw_init_v3(dev);
951
952 /* interrupt enable */
953 mt76_wr(dev, MT_RRO_HOST_INT_ENA,
954 MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA);
955 }
956
mt7996_wed_rro_init(struct mt7996_dev * dev)957 static int mt7996_wed_rro_init(struct mt7996_dev *dev)
958 {
959 u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff);
960 struct mt7996_wed_rro_addr *addr;
961 void *ptr;
962 int i;
963
964 if (!mt7996_has_hwrro(dev))
965 return 0;
966
967 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3) {
968 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) {
969 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
970 MT7996_RRO_BA_BITMAP_CR_SIZE,
971 &dev->wed_rro.ba_bitmap[i].phy_addr,
972 GFP_KERNEL);
973 if (!ptr)
974 return -ENOMEM;
975
976 dev->wed_rro.ba_bitmap[i].ptr = ptr;
977 }
978 }
979
980 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
981 int j;
982
983 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
984 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr),
985 &dev->wed_rro.addr_elem[i].phy_addr,
986 GFP_KERNEL);
987 if (!ptr)
988 return -ENOMEM;
989
990 dev->wed_rro.addr_elem[i].ptr = ptr;
991 memset(dev->wed_rro.addr_elem[i].ptr, 0,
992 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr));
993
994 addr = dev->wed_rro.addr_elem[i].ptr;
995 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) {
996 addr->data = cpu_to_le32(val);
997 addr++;
998 }
999
1000 if (is_mt7996(&dev->mt76) &&
1001 mt76_npu_device_active(&dev->mt76))
1002 mt76_npu_send_txrx_addr(&dev->mt76, 0, i,
1003 dev->wed_rro.addr_elem[i].phy_addr,
1004 0, 0);
1005
1006 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
1007 if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
1008 mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) {
1009 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
1010
1011 wed->wlan.ind_cmd.addr_elem_phys[i] =
1012 dev->wed_rro.addr_elem[i].phy_addr;
1013 }
1014 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */
1015 }
1016
1017 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) {
1018 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
1019 MT7996_RRO_MSDU_PG_SIZE_PER_CR,
1020 &dev->wed_rro.msdu_pg[i].phy_addr,
1021 GFP_KERNEL);
1022 if (!ptr)
1023 return -ENOMEM;
1024
1025 dev->wed_rro.msdu_pg[i].ptr = ptr;
1026
1027 memset(dev->wed_rro.msdu_pg[i].ptr, 0,
1028 MT7996_RRO_MSDU_PG_SIZE_PER_CR);
1029 }
1030
1031 if (!mtk_wed_device_active(&dev->mt76.mmio.wed) &&
1032 dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) {
1033 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
1034 sizeof(*dev->wed_rro.emi_rings_cpu.ptr),
1035 &dev->wed_rro.emi_rings_cpu.phy_addr,
1036 GFP_KERNEL);
1037 if (!ptr)
1038 return -ENOMEM;
1039
1040 dev->wed_rro.emi_rings_cpu.ptr = ptr;
1041
1042 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
1043 sizeof(*dev->wed_rro.emi_rings_dma.ptr),
1044 &dev->wed_rro.emi_rings_dma.phy_addr,
1045 GFP_KERNEL);
1046 if (!ptr)
1047 return -ENOMEM;
1048
1049 dev->wed_rro.emi_rings_dma.ptr = ptr;
1050 }
1051
1052 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
1053 MT7996_RRO_WINDOW_MAX_LEN * sizeof(*addr),
1054 &dev->wed_rro.session.phy_addr,
1055 GFP_KERNEL);
1056 if (!ptr)
1057 return -ENOMEM;
1058
1059 dev->wed_rro.session.ptr = ptr;
1060 addr = dev->wed_rro.session.ptr;
1061 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) {
1062 addr->data = cpu_to_le32(val);
1063 addr++;
1064 }
1065
1066 if (is_mt7996(&dev->mt76) && mt76_npu_device_active(&dev->mt76))
1067 mt76_npu_send_txrx_addr(&dev->mt76, 1, 0,
1068 dev->wed_rro.session.phy_addr, 0, 0);
1069
1070 mt7996_rro_hw_init(dev);
1071
1072 return mt7996_dma_rro_init(dev);
1073 }
1074
mt7996_wed_rro_free(struct mt7996_dev * dev)1075 static void mt7996_wed_rro_free(struct mt7996_dev *dev)
1076 {
1077 int i;
1078
1079 if (!mt7996_has_hwrro(dev))
1080 return;
1081
1082 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) {
1083 if (!dev->wed_rro.ba_bitmap[i].ptr)
1084 continue;
1085
1086 dmam_free_coherent(dev->mt76.dma_dev,
1087 MT7996_RRO_BA_BITMAP_CR_SIZE,
1088 dev->wed_rro.ba_bitmap[i].ptr,
1089 dev->wed_rro.ba_bitmap[i].phy_addr);
1090 }
1091
1092 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
1093 if (!dev->wed_rro.addr_elem[i].ptr)
1094 continue;
1095
1096 dmam_free_coherent(dev->mt76.dma_dev,
1097 MT7996_RRO_WINDOW_MAX_SIZE *
1098 sizeof(struct mt7996_wed_rro_addr),
1099 dev->wed_rro.addr_elem[i].ptr,
1100 dev->wed_rro.addr_elem[i].phy_addr);
1101 }
1102
1103 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) {
1104 if (!dev->wed_rro.msdu_pg[i].ptr)
1105 continue;
1106
1107 dmam_free_coherent(dev->mt76.dma_dev,
1108 MT7996_RRO_MSDU_PG_SIZE_PER_CR,
1109 dev->wed_rro.msdu_pg[i].ptr,
1110 dev->wed_rro.msdu_pg[i].phy_addr);
1111 }
1112
1113 if (dev->wed_rro.emi_rings_cpu.ptr)
1114 dmam_free_coherent(dev->mt76.dma_dev,
1115 sizeof(*dev->wed_rro.emi_rings_cpu.ptr),
1116 dev->wed_rro.emi_rings_cpu.ptr,
1117 dev->wed_rro.emi_rings_cpu.phy_addr);
1118
1119 if (dev->wed_rro.emi_rings_dma.ptr)
1120 dmam_free_coherent(dev->mt76.dma_dev,
1121 sizeof(*dev->wed_rro.emi_rings_dma.ptr),
1122 dev->wed_rro.emi_rings_dma.ptr,
1123 dev->wed_rro.emi_rings_dma.phy_addr);
1124
1125 if (!dev->wed_rro.session.ptr)
1126 return;
1127
1128 dmam_free_coherent(dev->mt76.dma_dev,
1129 MT7996_RRO_WINDOW_MAX_LEN *
1130 sizeof(struct mt7996_wed_rro_addr),
1131 dev->wed_rro.session.ptr,
1132 dev->wed_rro.session.phy_addr);
1133 }
1134
mt7996_wed_rro_work(struct work_struct * work)1135 static void mt7996_wed_rro_work(struct work_struct *work)
1136 {
1137 u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff);
1138 struct mt7996_dev *dev;
1139 LIST_HEAD(list);
1140
1141 dev = (struct mt7996_dev *)container_of(work, struct mt7996_dev,
1142 wed_rro.work);
1143
1144 spin_lock_bh(&dev->wed_rro.lock);
1145 list_splice_init(&dev->wed_rro.poll_list, &list);
1146 spin_unlock_bh(&dev->wed_rro.lock);
1147
1148 while (!list_empty(&list)) {
1149 struct mt7996_wed_rro_session_id *e;
1150 int i;
1151
1152 e = list_first_entry(&list, struct mt7996_wed_rro_session_id,
1153 list);
1154 list_del_init(&e->list);
1155
1156 if (mt76_npu_device_active(&dev->mt76)) {
1157 if (is_mt7996(&dev->mt76))
1158 mt76_npu_send_txrx_addr(&dev->mt76, 3, e->id,
1159 0, 0, 0);
1160 goto reset_session;
1161 }
1162
1163 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) {
1164 void *ptr = dev->wed_rro.session.ptr;
1165 struct mt7996_wed_rro_addr *elem;
1166 u32 idx, elem_id = i;
1167
1168 if (e->id == MT7996_RRO_MAX_SESSION)
1169 goto reset;
1170
1171 idx = e->id / MT7996_RRO_BA_BITMAP_SESSION_SIZE;
1172 if (idx >= ARRAY_SIZE(dev->wed_rro.addr_elem))
1173 goto out;
1174
1175 ptr = dev->wed_rro.addr_elem[idx].ptr;
1176 elem_id +=
1177 (e->id % MT7996_RRO_BA_BITMAP_SESSION_SIZE) *
1178 MT7996_RRO_WINDOW_MAX_LEN;
1179 reset:
1180 elem = ptr + elem_id * sizeof(*elem);
1181 elem->data |= cpu_to_le32(val);
1182 }
1183 reset_session:
1184 mt7996_mcu_wed_rro_reset_sessions(dev, e->id);
1185 out:
1186 kfree(e);
1187 }
1188 }
1189
mt7996_variant_type_init(struct mt7996_dev * dev)1190 static int mt7996_variant_type_init(struct mt7996_dev *dev)
1191 {
1192 u32 val = mt76_rr(dev, MT_PAD_GPIO);
1193 u8 var_type;
1194
1195 switch (mt76_chip(&dev->mt76)) {
1196 case MT7996_DEVICE_ID:
1197 if (val & MT_PAD_GPIO_2ADIE_TBTC)
1198 var_type = MT7996_VAR_TYPE_233;
1199 else
1200 var_type = MT7996_VAR_TYPE_444;
1201 break;
1202 case MT7992_DEVICE_ID:
1203 if (val & MT_PAD_GPIO_ADIE_SINGLE)
1204 var_type = MT7992_VAR_TYPE_23;
1205 else if (u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992))
1206 var_type = MT7992_VAR_TYPE_44;
1207 else
1208 var_type = MT7992_VAR_TYPE_24;
1209 break;
1210 case MT7990_DEVICE_ID:
1211 var_type = MT7990_VAR_TYPE_23;
1212 break;
1213 default:
1214 return -EINVAL;
1215 }
1216
1217 dev->var.type = var_type;
1218 return 0;
1219 }
1220
mt7996_variant_fem_init(struct mt7996_dev * dev)1221 static int mt7996_variant_fem_init(struct mt7996_dev *dev)
1222 {
1223 #define MT7976C_EFUSE_OFFSET 0x470
1224 u8 buf[MT7996_EEPROM_BLOCK_SIZE], idx, adie_idx, adie_comb;
1225 u32 regval, val = mt76_rr(dev, MT_PAD_GPIO);
1226 u16 adie_id, adie_ver;
1227 bool is_7976c;
1228 int ret;
1229
1230 if (is_mt7992(&dev->mt76)) {
1231 adie_idx = (val & MT_PAD_GPIO_ADIE_SINGLE) ? 0 : 1;
1232 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992);
1233 } else {
1234 adie_idx = 0;
1235 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB);
1236 }
1237
1238 ret = mt7996_mcu_rf_regval(dev, MT_ADIE_CHIP_ID(adie_idx), ®val, false);
1239 if (ret)
1240 return ret;
1241
1242 ret = mt7996_mcu_get_eeprom(dev, MT7976C_EFUSE_OFFSET, buf, sizeof(buf),
1243 EEPROM_MODE_EFUSE);
1244 if (ret && ret != -EINVAL)
1245 return ret;
1246
1247 adie_ver = u32_get_bits(regval, MT_ADIE_VERSION_MASK);
1248 idx = MT7976C_EFUSE_OFFSET % MT7996_EEPROM_BLOCK_SIZE;
1249 is_7976c = adie_ver == 0x8a10 || adie_ver == 0x8b00 ||
1250 adie_ver == 0x8c10 || buf[idx] == 0xc;
1251
1252 adie_id = u32_get_bits(regval, MT_ADIE_CHIP_ID_MASK);
1253 if (adie_id == 0x7975 || adie_id == 0x7979 ||
1254 (adie_id == 0x7976 && is_7976c))
1255 dev->var.fem = MT7996_FEM_INT;
1256 else if (adie_id == 0x7977 && adie_comb == 1)
1257 dev->var.fem = MT7996_FEM_MIX;
1258 else
1259 dev->var.fem = MT7996_FEM_EXT;
1260
1261 return 0;
1262 }
1263
mt7996_init_hardware(struct mt7996_dev * dev)1264 static int mt7996_init_hardware(struct mt7996_dev *dev)
1265 {
1266 int ret, idx;
1267
1268 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
1269 if (is_mt7992(&dev->mt76)) {
1270 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0);
1271 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0);
1272 }
1273
1274 INIT_WORK(&dev->init_work, mt7996_init_work);
1275 INIT_WORK(&dev->wed_rro.work, mt7996_wed_rro_work);
1276 INIT_LIST_HEAD(&dev->wed_rro.poll_list);
1277 spin_lock_init(&dev->wed_rro.lock);
1278
1279 ret = mt7996_variant_type_init(dev);
1280 if (ret)
1281 return ret;
1282
1283 ret = mt7996_dma_init(dev);
1284 if (ret)
1285 return ret;
1286
1287 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
1288
1289 ret = mt7996_mcu_init(dev);
1290 if (ret)
1291 return ret;
1292
1293 ret = mt7996_wed_rro_init(dev);
1294 if (ret)
1295 return ret;
1296
1297 ret = mt7996_variant_fem_init(dev);
1298 if (ret)
1299 return ret;
1300
1301 ret = mt7996_eeprom_init(dev);
1302 if (ret < 0)
1303 return ret;
1304
1305 /* Beacon and mgmt frames should occupy wcid 0 */
1306 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA);
1307 if (idx)
1308 return -ENOSPC;
1309
1310 dev->mt76.global_wcid.idx = idx;
1311 dev->mt76.global_wcid.hw_key_idx = -1;
1312 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET;
1313 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid);
1314
1315 return 0;
1316 }
1317
mt7996_set_stream_vht_txbf_caps(struct mt7996_phy * phy)1318 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy)
1319 {
1320 int sts;
1321 u32 *cap;
1322
1323 if (!phy->mt76->cap.has_5ghz)
1324 return;
1325
1326 sts = hweight16(phy->mt76->chainmask);
1327 cap = &phy->mt76->sband_5g.sband.vht_cap.cap;
1328
1329 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
1330 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
1331
1332 if (is_mt7992(phy->mt76->dev))
1333 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 4);
1334 else
1335 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 3);
1336
1337 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK |
1338 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
1339 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
1340
1341 if (sts < 2)
1342 return;
1343
1344 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
1345 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE |
1346 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1);
1347 }
1348
1349 static void
mt7996_set_stream_he_txbf_caps(struct mt7996_phy * phy,struct ieee80211_sta_he_cap * he_cap,int vif,enum nl80211_band band)1350 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy,
1351 struct ieee80211_sta_he_cap *he_cap, int vif,
1352 enum nl80211_band band)
1353 {
1354 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem;
1355 int sts = hweight16(phy->mt76->chainmask);
1356 bool non_2g = band != NL80211_BAND_2GHZ;
1357 u8 c;
1358
1359 #ifdef CONFIG_MAC80211_MESH
1360 if (vif == NL80211_IFTYPE_MESH_POINT)
1361 return;
1362 #endif
1363
1364 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
1365 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
1366
1367 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK |
1368 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK;
1369 elem->phy_cap_info[5] &= ~c;
1370
1371 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
1372 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
1373 elem->phy_cap_info[6] &= ~c;
1374
1375 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
1376
1377 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
1378 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO;
1379 elem->phy_cap_info[2] |= c;
1380
1381 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE;
1382
1383 if (is_mt7992(phy->mt76->dev))
1384 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5 |
1385 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5 * non_2g);
1386 else
1387 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 |
1388 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4 * non_2g);
1389
1390 elem->phy_cap_info[4] |= c;
1391
1392 /* do not support NG16 due to spec D4.0 changes subcarrier idx */
1393 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
1394 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU;
1395
1396 if (vif == NL80211_IFTYPE_STATION)
1397 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO;
1398
1399 elem->phy_cap_info[6] |= c;
1400
1401 if (sts < 2)
1402 return;
1403
1404 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */
1405 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3;
1406
1407 if (!(vif == NL80211_IFTYPE_AP || vif == NL80211_IFTYPE_STATION))
1408 return;
1409
1410 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
1411
1412 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
1413 sts - 1) |
1414 (FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK,
1415 sts - 1) * non_2g);
1416
1417 elem->phy_cap_info[5] |= c;
1418
1419 if (vif != NL80211_IFTYPE_AP)
1420 return;
1421
1422 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
1423
1424 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
1425 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
1426 elem->phy_cap_info[6] |= c;
1427
1428 c = 0;
1429 if (non_2g)
1430 c |= IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ |
1431 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
1432 elem->phy_cap_info[7] |= c;
1433 }
1434
1435 static void
mt7996_init_he_caps(struct mt7996_phy * phy,enum nl80211_band band,struct ieee80211_sband_iftype_data * data,enum nl80211_iftype iftype)1436 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band,
1437 struct ieee80211_sband_iftype_data *data,
1438 enum nl80211_iftype iftype)
1439 {
1440 struct ieee80211_sta_he_cap *he_cap = &data->he_cap;
1441 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem;
1442 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp;
1443 int i, nss = hweight8(phy->mt76->antenna_mask);
1444 u16 mcs_map = 0;
1445
1446 for (i = 0; i < 8; i++) {
1447 if (i < nss)
1448 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
1449 else
1450 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
1451 }
1452
1453 he_cap->has_he = true;
1454
1455 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
1456 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
1457 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
1458 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
1459
1460 if (band == NL80211_BAND_2GHZ)
1461 he_cap_elem->phy_cap_info[0] =
1462 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
1463 else
1464 he_cap_elem->phy_cap_info[0] =
1465 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
1466 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
1467
1468 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD;
1469 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
1470 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
1471
1472 he_cap_elem->phy_cap_info[7] =
1473 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI;
1474
1475 switch (iftype) {
1476 case NL80211_IFTYPE_AP:
1477 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES;
1478 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR;
1479 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR;
1480 he_cap_elem->mac_cap_info[5] |=
1481 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX;
1482 he_cap_elem->phy_cap_info[3] |=
1483 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1484 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1485 he_cap_elem->phy_cap_info[6] |=
1486 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1487 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1488 he_cap_elem->phy_cap_info[9] |=
1489 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1490 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
1491 break;
1492 case NL80211_IFTYPE_STATION:
1493 he_cap_elem->mac_cap_info[1] |=
1494 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
1495
1496 if (band == NL80211_BAND_2GHZ)
1497 he_cap_elem->phy_cap_info[0] |=
1498 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G;
1499 else
1500 he_cap_elem->phy_cap_info[0] |=
1501 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G;
1502
1503 he_cap_elem->phy_cap_info[1] |=
1504 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
1505 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
1506 he_cap_elem->phy_cap_info[3] |=
1507 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1508 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1509 he_cap_elem->phy_cap_info[6] |=
1510 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB |
1511 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1512 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1513 he_cap_elem->phy_cap_info[7] |=
1514 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP;
1515 he_cap_elem->phy_cap_info[8] |=
1516 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
1517 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
1518 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
1519 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484;
1520 he_cap_elem->phy_cap_info[9] |=
1521 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
1522 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
1523 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1524 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
1525 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
1526 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB;
1527 break;
1528 default:
1529 break;
1530 }
1531
1532 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map);
1533 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map);
1534 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map);
1535 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map);
1536
1537 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype, band);
1538
1539 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres));
1540 if (he_cap_elem->phy_cap_info[6] &
1541 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) {
1542 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band);
1543 } else {
1544 he_cap_elem->phy_cap_info[9] |=
1545 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
1546 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
1547 }
1548
1549 if (band == NL80211_BAND_6GHZ) {
1550 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS |
1551 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
1552
1553 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5,
1554 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
1555 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
1556 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
1557 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
1558 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
1559
1560 data->he_6ghz_capa.capa = cpu_to_le16(cap);
1561 }
1562 }
1563
1564 static void
mt7996_init_eht_caps(struct mt7996_phy * phy,enum nl80211_band band,struct ieee80211_sband_iftype_data * data,enum nl80211_iftype iftype)1565 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band,
1566 struct ieee80211_sband_iftype_data *data,
1567 enum nl80211_iftype iftype)
1568 {
1569 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap;
1570 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem;
1571 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp;
1572 int nss = hweight8(phy->mt76->antenna_mask);
1573 int sts = hweight16(phy->mt76->chainmask);
1574 u8 val;
1575
1576 if (!phy->dev->has_eht)
1577 return;
1578
1579 eht_cap->has_eht = true;
1580
1581 eht_cap_elem->mac_cap_info[0] =
1582 IEEE80211_EHT_MAC_CAP0_OM_CONTROL |
1583 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454,
1584 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
1585
1586 eht_cap_elem->mac_cap_info[1] |=
1587 IEEE80211_EHT_MAC_CAP1_MAX_AMPDU_LEN_MASK;
1588
1589 eht_cap_elem->phy_cap_info[0] =
1590 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
1591 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER |
1592 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
1593
1594 /* Set the maximum capability regardless of the antenna configuration. */
1595 val = is_mt7992(phy->mt76->dev) ? 4 : 3;
1596 eht_cap_elem->phy_cap_info[0] |=
1597 u8_encode_bits(u8_get_bits(val, BIT(0)),
1598 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK);
1599
1600 eht_cap_elem->phy_cap_info[1] =
1601 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)),
1602 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK);
1603
1604 eht_cap_elem->phy_cap_info[2] =
1605 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK);
1606
1607 if (band != NL80211_BAND_2GHZ) {
1608 eht_cap_elem->phy_cap_info[1] |=
1609 u8_encode_bits(val,
1610 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
1611
1612 eht_cap_elem->phy_cap_info[2] |=
1613 u8_encode_bits(sts - 1,
1614 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK);
1615 }
1616
1617 if (band == NL80211_BAND_6GHZ) {
1618 eht_cap_elem->phy_cap_info[0] |=
1619 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
1620
1621 eht_cap_elem->phy_cap_info[1] |=
1622 u8_encode_bits(val,
1623 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
1624
1625 eht_cap_elem->phy_cap_info[2] |=
1626 u8_encode_bits(sts - 1,
1627 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK);
1628 }
1629
1630 eht_cap_elem->phy_cap_info[3] =
1631 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
1632 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
1633 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
1634 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK;
1635
1636 eht_cap_elem->phy_cap_info[4] =
1637 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI |
1638 u8_encode_bits(min_t(int, sts - 1, 2),
1639 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
1640
1641 eht_cap_elem->phy_cap_info[5] =
1642 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US,
1643 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) |
1644 u8_encode_bits(u8_get_bits(1, GENMASK(1, 0)),
1645 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK);
1646
1647 eht_cap_elem->phy_cap_info[6] = IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK;
1648 if (band != NL80211_BAND_6GHZ) {
1649 eht_cap_elem->phy_cap_info[6] &=
1650 ~IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_320MHZ;
1651
1652 if (band != NL80211_BAND_5GHZ)
1653 eht_cap_elem->phy_cap_info[6] &=
1654 ~(IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_160MHZ |
1655 IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_80MHZ);
1656 }
1657
1658 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) |
1659 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX);
1660 #define SET_EHT_MAX_NSS(_bw, _val) do { \
1661 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \
1662 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \
1663 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \
1664 } while (0)
1665
1666 SET_EHT_MAX_NSS(80, val);
1667 SET_EHT_MAX_NSS(160, val);
1668 if (band == NL80211_BAND_6GHZ)
1669 SET_EHT_MAX_NSS(320, val);
1670 #undef SET_EHT_MAX_NSS
1671
1672 if (iftype != NL80211_IFTYPE_AP)
1673 return;
1674
1675 eht_cap_elem->phy_cap_info[3] |=
1676 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
1677 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
1678
1679 eht_cap_elem->phy_cap_info[7] =
1680 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ |
1681 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ;
1682
1683 if (band == NL80211_BAND_2GHZ)
1684 return;
1685
1686 eht_cap_elem->phy_cap_info[7] |=
1687 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ |
1688 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ;
1689
1690 if (band != NL80211_BAND_6GHZ)
1691 return;
1692
1693 eht_cap_elem->phy_cap_info[7] |=
1694 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ |
1695 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ;
1696 }
1697
1698 static void
__mt7996_set_stream_he_eht_caps(struct mt7996_phy * phy,struct ieee80211_supported_band * sband,enum nl80211_band band)1699 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy,
1700 struct ieee80211_supported_band *sband,
1701 enum nl80211_band band)
1702 {
1703 struct ieee80211_sband_iftype_data *data = phy->iftype[band];
1704 int i, n = 0;
1705
1706 for (i = 0; i < NUM_NL80211_IFTYPES; i++) {
1707 switch (i) {
1708 case NL80211_IFTYPE_STATION:
1709 case NL80211_IFTYPE_AP:
1710 #ifdef CONFIG_MAC80211_MESH
1711 case NL80211_IFTYPE_MESH_POINT:
1712 #endif
1713 break;
1714 default:
1715 continue;
1716 }
1717
1718 data[n].types_mask = BIT(i);
1719 mt7996_init_he_caps(phy, band, &data[n], i);
1720 mt7996_init_eht_caps(phy, band, &data[n], i);
1721
1722 n++;
1723 }
1724
1725 _ieee80211_set_sband_iftype_data(sband, data, n);
1726 }
1727
mt7996_set_stream_he_eht_caps(struct mt7996_phy * phy)1728 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy)
1729 {
1730 if (phy->mt76->cap.has_2ghz)
1731 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband,
1732 NL80211_BAND_2GHZ);
1733
1734 if (phy->mt76->cap.has_5ghz)
1735 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband,
1736 NL80211_BAND_5GHZ);
1737
1738 if (phy->mt76->cap.has_6ghz)
1739 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband,
1740 NL80211_BAND_6GHZ);
1741 }
1742
mt7996_register_device(struct mt7996_dev * dev)1743 int mt7996_register_device(struct mt7996_dev *dev)
1744 {
1745 struct ieee80211_hw *hw = mt76_hw(dev);
1746 struct mt7996_phy *phy;
1747 int ret;
1748
1749 dev->phy.dev = dev;
1750 dev->phy.mt76 = &dev->mt76.phy;
1751 dev->mt76.phy.priv = &dev->phy;
1752 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work);
1753 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work);
1754 INIT_LIST_HEAD(&dev->sta_rc_list);
1755 INIT_LIST_HEAD(&dev->twt_list);
1756
1757 init_waitqueue_head(&dev->reset_wait);
1758 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work);
1759 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work);
1760 mutex_init(&dev->dump_mutex);
1761
1762 ret = mt7996_init_hardware(dev);
1763 if (ret)
1764 return ret;
1765
1766 mt7996_init_wiphy(hw, &dev->mt76.mmio.wed);
1767
1768 ret = mt7996_register_phy(dev, MT_BAND1);
1769 if (ret)
1770 return ret;
1771
1772 ret = mt7996_register_phy(dev, MT_BAND2);
1773 if (ret)
1774 return ret;
1775
1776 ret = mt7996_npu_hw_init(dev);
1777 if (ret)
1778 return ret;
1779
1780 mt7996_dma_rro_start(dev);
1781
1782 ret = mt76_register_device(&dev->mt76, true, mt76_rates,
1783 ARRAY_SIZE(mt76_rates));
1784 if (ret)
1785 return ret;
1786
1787 mt7996_for_each_phy(dev, phy)
1788 mt7996_thermal_init(phy);
1789
1790 ieee80211_queue_work(mt76_hw(dev), &dev->init_work);
1791
1792 dev->recovery.hw_init_done = true;
1793
1794 ret = mt7996_init_debugfs(dev);
1795 if (ret)
1796 goto error;
1797
1798 ret = mt7996_coredump_register(dev);
1799 if (ret)
1800 goto error;
1801
1802 return 0;
1803
1804 error:
1805 cancel_work_sync(&dev->init_work);
1806
1807 return ret;
1808 }
1809
mt7996_unregister_device(struct mt7996_dev * dev)1810 void mt7996_unregister_device(struct mt7996_dev *dev)
1811 {
1812 cancel_work_sync(&dev->dump_work);
1813 cancel_work_sync(&dev->wed_rro.work);
1814 cancel_work_sync(&dev->reset_work);
1815 cancel_work_sync(&dev->rc_work);
1816 mt7996_unregister_phy(mt7996_phy3(dev));
1817 mt7996_unregister_phy(mt7996_phy2(dev));
1818 mt7996_unregister_thermal(&dev->phy);
1819 mt7996_coredump_unregister(dev);
1820 mt76_unregister_device(&dev->mt76);
1821 mt7996_wed_rro_free(dev);
1822 mt7996_mcu_exit(dev);
1823 mt7996_tx_token_put(dev);
1824 mt7996_dma_cleanup(dev);
1825 if (mt7996_has_hwrro(dev) &&
1826 !mtk_wed_device_active(&dev->mt76.mmio.wed))
1827 mt7996_rro_msdu_page_map_free(dev);
1828 tasklet_disable(&dev->mt76.irq_tasklet);
1829
1830 mt76_free_device(&dev->mt76);
1831 }
1832