1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/of.h> 8 #include <linux/hwmon.h> 9 #include <linux/hwmon-sysfs.h> 10 #include <linux/thermal.h> 11 #include "mt7996.h" 12 #include "mac.h" 13 #include "mcu.h" 14 #include "coredump.h" 15 #include "eeprom.h" 16 17 static const struct ieee80211_iface_limit if_limits_global = { 18 .max = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS, 19 .types = BIT(NL80211_IFTYPE_STATION) 20 | BIT(NL80211_IFTYPE_ADHOC) 21 | BIT(NL80211_IFTYPE_AP) 22 #ifdef CONFIG_MAC80211_MESH 23 | BIT(NL80211_IFTYPE_MESH_POINT) 24 #endif 25 }; 26 27 static const struct ieee80211_iface_combination if_comb_global = { 28 .limits = &if_limits_global, 29 .n_limits = 1, 30 .max_interfaces = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS, 31 .num_different_channels = MT7996_MAX_RADIOS, 32 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 33 BIT(NL80211_CHAN_WIDTH_20) | 34 BIT(NL80211_CHAN_WIDTH_40) | 35 BIT(NL80211_CHAN_WIDTH_80) | 36 BIT(NL80211_CHAN_WIDTH_160), 37 }; 38 39 static const struct ieee80211_iface_combination if_comb_global_7992 = { 40 .limits = &if_limits_global, 41 .n_limits = 1, 42 .max_interfaces = 32, 43 .num_different_channels = MT7996_MAX_RADIOS - 1, 44 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 45 BIT(NL80211_CHAN_WIDTH_20) | 46 BIT(NL80211_CHAN_WIDTH_40) | 47 BIT(NL80211_CHAN_WIDTH_80) | 48 BIT(NL80211_CHAN_WIDTH_160), 49 }; 50 51 static const struct ieee80211_iface_limit if_limits[] = { 52 { 53 .max = 16, 54 .types = BIT(NL80211_IFTYPE_AP) 55 #ifdef CONFIG_MAC80211_MESH 56 | BIT(NL80211_IFTYPE_MESH_POINT) 57 #endif 58 }, { 59 .max = MT7996_MAX_INTERFACES, 60 .types = BIT(NL80211_IFTYPE_STATION) 61 } 62 }; 63 64 static const struct ieee80211_iface_combination if_comb = { 65 .limits = if_limits, 66 .n_limits = ARRAY_SIZE(if_limits), 67 .max_interfaces = MT7996_MAX_INTERFACES, 68 .num_different_channels = 1, 69 .beacon_int_infra_match = true, 70 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 71 BIT(NL80211_CHAN_WIDTH_20) | 72 BIT(NL80211_CHAN_WIDTH_40) | 73 BIT(NL80211_CHAN_WIDTH_80) | 74 BIT(NL80211_CHAN_WIDTH_160), 75 .beacon_int_min_gcd = 100, 76 }; 77 78 static const u8 if_types_ext_capa_ap[] = { 79 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, 80 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 81 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 82 }; 83 84 static const struct wiphy_iftype_ext_capab iftypes_ext_capa[] = { 85 { 86 .iftype = NL80211_IFTYPE_AP, 87 .extended_capabilities = if_types_ext_capa_ap, 88 .extended_capabilities_mask = if_types_ext_capa_ap, 89 .extended_capabilities_len = sizeof(if_types_ext_capa_ap), 90 .eml_capabilities = IEEE80211_EML_CAP_EMLSR_SUPP, 91 .mld_capa_and_ops = 92 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS, 93 MT7996_MAX_RADIOS - 1), 94 }, { 95 .iftype = NL80211_IFTYPE_STATION, 96 .extended_capabilities = if_types_ext_capa_ap, 97 .extended_capabilities_mask = if_types_ext_capa_ap, 98 .extended_capabilities_len = sizeof(if_types_ext_capa_ap), 99 .mld_capa_and_ops = 100 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_FREQ_SEP_TYPE_IND, 1) | 101 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS, 102 MT7996_MAX_RADIOS - 1), 103 }, 104 }; 105 106 static ssize_t mt7996_thermal_temp_show(struct device *dev, 107 struct device_attribute *attr, 108 char *buf) 109 { 110 struct mt7996_phy *phy = dev_get_drvdata(dev); 111 int i = to_sensor_dev_attr(attr)->index; 112 int temperature; 113 114 switch (i) { 115 case 0: 116 temperature = mt7996_mcu_get_temperature(phy); 117 if (temperature < 0) 118 return temperature; 119 /* display in millidegree celcius */ 120 return sprintf(buf, "%u\n", temperature * 1000); 121 case 1: 122 case 2: 123 return sprintf(buf, "%u\n", 124 phy->throttle_temp[i - 1] * 1000); 125 case 3: 126 return sprintf(buf, "%hhu\n", phy->throttle_state); 127 default: 128 return -EINVAL; 129 } 130 } 131 132 static ssize_t mt7996_thermal_temp_store(struct device *dev, 133 struct device_attribute *attr, 134 const char *buf, size_t count) 135 { 136 struct mt7996_phy *phy = dev_get_drvdata(dev); 137 int ret, i = to_sensor_dev_attr(attr)->index; 138 long val; 139 140 ret = kstrtol(buf, 10, &val); 141 if (ret < 0) 142 return ret; 143 144 mutex_lock(&phy->dev->mt76.mutex); 145 val = DIV_ROUND_CLOSEST(clamp_val(val, 40 * 1000, 130 * 1000), 1000); 146 147 /* add a safety margin ~10 */ 148 if ((i - 1 == MT7996_CRIT_TEMP_IDX && 149 val > phy->throttle_temp[MT7996_MAX_TEMP_IDX] - 10) || 150 (i - 1 == MT7996_MAX_TEMP_IDX && 151 val - 10 < phy->throttle_temp[MT7996_CRIT_TEMP_IDX])) { 152 dev_err(phy->dev->mt76.dev, 153 "temp1_max shall be 10 degrees higher than temp1_crit."); 154 mutex_unlock(&phy->dev->mt76.mutex); 155 return -EINVAL; 156 } 157 158 phy->throttle_temp[i - 1] = val; 159 mutex_unlock(&phy->dev->mt76.mutex); 160 161 ret = mt7996_mcu_set_thermal_protect(phy, true); 162 if (ret) 163 return ret; 164 165 return count; 166 } 167 168 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7996_thermal_temp, 0); 169 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7996_thermal_temp, 1); 170 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7996_thermal_temp, 2); 171 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7996_thermal_temp, 3); 172 173 static struct attribute *mt7996_hwmon_attrs[] = { 174 &sensor_dev_attr_temp1_input.dev_attr.attr, 175 &sensor_dev_attr_temp1_crit.dev_attr.attr, 176 &sensor_dev_attr_temp1_max.dev_attr.attr, 177 &sensor_dev_attr_throttle1.dev_attr.attr, 178 NULL, 179 }; 180 ATTRIBUTE_GROUPS(mt7996_hwmon); 181 182 static int 183 mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 184 unsigned long *state) 185 { 186 *state = MT7996_CDEV_THROTTLE_MAX; 187 188 return 0; 189 } 190 191 static int 192 mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 193 unsigned long *state) 194 { 195 struct mt7996_phy *phy = cdev->devdata; 196 197 *state = phy->cdev_state; 198 199 return 0; 200 } 201 202 static int 203 mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 204 unsigned long state) 205 { 206 struct mt7996_phy *phy = cdev->devdata; 207 u8 throttling = MT7996_THERMAL_THROTTLE_MAX - state; 208 int ret; 209 210 if (state > MT7996_CDEV_THROTTLE_MAX) { 211 dev_err(phy->dev->mt76.dev, 212 "please specify a valid throttling state\n"); 213 return -EINVAL; 214 } 215 216 if (state == phy->cdev_state) 217 return 0; 218 219 /* cooling_device convention: 0 = no cooling, more = more cooling 220 * mcu convention: 1 = max cooling, more = less cooling 221 */ 222 ret = mt7996_mcu_set_thermal_throttling(phy, throttling); 223 if (ret) 224 return ret; 225 226 phy->cdev_state = state; 227 228 return 0; 229 } 230 231 static const struct thermal_cooling_device_ops mt7996_thermal_ops = { 232 .get_max_state = mt7996_thermal_get_max_throttle_state, 233 .get_cur_state = mt7996_thermal_get_cur_throttle_state, 234 .set_cur_state = mt7996_thermal_set_cur_throttle_state, 235 }; 236 237 static void mt7996_unregister_thermal(struct mt7996_phy *phy) 238 { 239 struct wiphy *wiphy = phy->mt76->hw->wiphy; 240 char name[sizeof("cooling_deviceXXX")]; 241 242 if (!phy->cdev) 243 return; 244 245 snprintf(name, sizeof(name), "cooling_device%d", phy->mt76->band_idx); 246 sysfs_remove_link(&wiphy->dev.kobj, name); 247 thermal_cooling_device_unregister(phy->cdev); 248 } 249 250 static int mt7996_thermal_init(struct mt7996_phy *phy) 251 { 252 struct wiphy *wiphy = phy->mt76->hw->wiphy; 253 char cname[sizeof("cooling_deviceXXX")]; 254 struct thermal_cooling_device *cdev; 255 struct device *hwmon; 256 const char *name; 257 258 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7996_%s.%d", 259 wiphy_name(wiphy), phy->mt76->band_idx); 260 if (!name) 261 return -ENOMEM; 262 263 snprintf(cname, sizeof(cname), "cooling_device%d", phy->mt76->band_idx); 264 265 cdev = thermal_cooling_device_register(name, phy, &mt7996_thermal_ops); 266 if (!IS_ERR(cdev)) { 267 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 268 cname) < 0) 269 thermal_cooling_device_unregister(cdev); 270 else 271 phy->cdev = cdev; 272 } 273 274 /* initialize critical/maximum high temperature */ 275 phy->throttle_temp[MT7996_CRIT_TEMP_IDX] = MT7996_CRIT_TEMP; 276 phy->throttle_temp[MT7996_MAX_TEMP_IDX] = MT7996_MAX_TEMP; 277 278 if (!IS_REACHABLE(CONFIG_HWMON)) 279 return 0; 280 281 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 282 mt7996_hwmon_groups); 283 284 if (IS_ERR(hwmon)) 285 return PTR_ERR(hwmon); 286 287 return 0; 288 } 289 290 static void mt7996_led_set_config(struct led_classdev *led_cdev, 291 u8 delay_on, u8 delay_off) 292 { 293 struct mt7996_dev *dev; 294 struct mt76_phy *mphy; 295 u32 val; 296 297 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 298 dev = container_of(mphy->dev, struct mt7996_dev, mt76); 299 300 /* select TX blink mode, 2: only data frames */ 301 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2); 302 303 /* enable LED */ 304 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 305 306 /* set LED Tx blink on/off time */ 307 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) | 308 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off); 309 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val); 310 311 /* turn LED off */ 312 if (delay_off == 0xff && delay_on == 0x0) { 313 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK; 314 } else { 315 /* control LED */ 316 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK; 317 if (mphy->band_idx == MT_BAND1) 318 val |= MT_LED_CTRL_BLINK_BAND_SEL; 319 } 320 321 if (mphy->leds.al) 322 val |= MT_LED_CTRL_POLARITY; 323 324 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 325 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 326 } 327 328 static int mt7996_led_set_blink(struct led_classdev *led_cdev, 329 unsigned long *delay_on, 330 unsigned long *delay_off) 331 { 332 u16 delta_on = 0, delta_off = 0; 333 334 #define HW_TICK 10 335 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 336 337 if (*delay_on) 338 delta_on = TO_HW_TICK(*delay_on); 339 if (*delay_off) 340 delta_off = TO_HW_TICK(*delay_off); 341 342 mt7996_led_set_config(led_cdev, delta_on, delta_off); 343 344 return 0; 345 } 346 347 static void mt7996_led_set_brightness(struct led_classdev *led_cdev, 348 enum led_brightness brightness) 349 { 350 if (!brightness) 351 mt7996_led_set_config(led_cdev, 0, 0xff); 352 else 353 mt7996_led_set_config(led_cdev, 0xff, 0); 354 } 355 356 static void __mt7996_init_txpower(struct mt7996_phy *phy, 357 struct ieee80211_supported_band *sband) 358 { 359 struct mt7996_dev *dev = phy->dev; 360 int i, n_chains = hweight16(phy->mt76->chainmask); 361 int path_delta = mt76_tx_power_path_delta(n_chains); 362 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band); 363 struct mt76_power_limits limits; 364 365 for (i = 0; i < sband->n_channels; i++) { 366 struct ieee80211_channel *chan = &sband->channels[i]; 367 int target_power = mt7996_eeprom_get_target_power(dev, chan); 368 369 target_power += pwr_delta; 370 target_power = mt76_get_rate_power_limits(phy->mt76, chan, 371 &limits, 372 target_power); 373 target_power += path_delta; 374 target_power = DIV_ROUND_UP(target_power, 2); 375 chan->max_power = min_t(int, chan->max_reg_power, 376 target_power); 377 chan->orig_mpwr = target_power; 378 } 379 } 380 381 void mt7996_init_txpower(struct mt7996_phy *phy) 382 { 383 if (!phy) 384 return; 385 386 if (phy->mt76->cap.has_2ghz) 387 __mt7996_init_txpower(phy, &phy->mt76->sband_2g.sband); 388 if (phy->mt76->cap.has_5ghz) 389 __mt7996_init_txpower(phy, &phy->mt76->sband_5g.sband); 390 if (phy->mt76->cap.has_6ghz) 391 __mt7996_init_txpower(phy, &phy->mt76->sband_6g.sband); 392 } 393 394 static void 395 mt7996_regd_notifier(struct wiphy *wiphy, 396 struct regulatory_request *request) 397 { 398 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 399 struct mt7996_dev *dev = mt7996_hw_dev(hw); 400 struct mt7996_phy *phy; 401 402 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 403 dev->mt76.region = request->dfs_region; 404 405 mt7996_for_each_phy(dev, phy) { 406 if (dev->mt76.region == NL80211_DFS_UNSET) 407 mt7996_mcu_rdd_background_enable(phy, NULL); 408 409 mt7996_init_txpower(phy); 410 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 411 mt7996_dfs_init_radar_detector(phy); 412 } 413 } 414 415 static void 416 mt7996_init_wiphy_band(struct ieee80211_hw *hw, struct mt7996_phy *phy) 417 { 418 struct mt7996_dev *dev = phy->dev; 419 struct wiphy *wiphy = hw->wiphy; 420 int n_radios = hw->wiphy->n_radio; 421 struct wiphy_radio_freq_range *freq = &dev->radio_freqs[n_radios]; 422 struct wiphy_radio *radio = &dev->radios[n_radios]; 423 424 phy->slottime = 9; 425 phy->beacon_rate = -1; 426 phy->rxfilter = MT_WF_RFCR_DROP_OTHER_UC; 427 428 if (phy->mt76->cap.has_2ghz) { 429 phy->mt76->sband_2g.sband.ht_cap.cap |= 430 IEEE80211_HT_CAP_LDPC_CODING | 431 IEEE80211_HT_CAP_MAX_AMSDU; 432 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 433 IEEE80211_HT_MPDU_DENSITY_2; 434 freq->start_freq = 2400000; 435 freq->end_freq = 2500000; 436 } else if (phy->mt76->cap.has_5ghz) { 437 phy->mt76->sband_5g.sband.ht_cap.cap |= 438 IEEE80211_HT_CAP_LDPC_CODING | 439 IEEE80211_HT_CAP_MAX_AMSDU; 440 441 phy->mt76->sband_5g.sband.vht_cap.cap |= 442 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 443 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 444 IEEE80211_VHT_CAP_SHORT_GI_160 | 445 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 446 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 447 IEEE80211_HT_MPDU_DENSITY_1; 448 449 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 450 freq->start_freq = 5000000; 451 freq->end_freq = 5900000; 452 } else if (phy->mt76->cap.has_6ghz) { 453 freq->start_freq = 5900000; 454 freq->end_freq = 7200000; 455 } else { 456 return; 457 } 458 459 dev->radio_phy[n_radios] = phy; 460 radio->freq_range = freq; 461 radio->n_freq_range = 1; 462 radio->iface_combinations = &if_comb; 463 radio->n_iface_combinations = 1; 464 memcpy(dev->radio_addrs[n_radios].addr, phy->mt76->macaddr, ETH_ALEN); 465 hw->wiphy->n_addresses++; 466 hw->wiphy->n_radio++; 467 468 wiphy->available_antennas_rx |= phy->mt76->chainmask; 469 wiphy->available_antennas_tx |= phy->mt76->chainmask; 470 471 mt76_set_stream_caps(phy->mt76, true); 472 mt7996_set_stream_vht_txbf_caps(phy); 473 mt7996_set_stream_he_eht_caps(phy); 474 mt7996_init_txpower(phy); 475 } 476 477 static void 478 mt7996_init_wiphy(struct ieee80211_hw *hw, struct mtk_wed_device *wed) 479 { 480 struct mt7996_dev *dev = mt7996_hw_dev(hw); 481 struct mt76_dev *mdev = &dev->mt76; 482 struct wiphy *wiphy = hw->wiphy; 483 u16 max_subframes = dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT : 484 IEEE80211_MAX_AMPDU_BUF_HE; 485 486 hw->queues = 4; 487 hw->max_rx_aggregation_subframes = max_subframes; 488 hw->max_tx_aggregation_subframes = max_subframes; 489 if (is_mt7990(mdev) && dev->has_eht) 490 hw->max_tx_aggregation_subframes = 512; 491 492 hw->netdev_features = NETIF_F_RXCSUM; 493 if (mtk_wed_device_active(wed) || mt76_npu_device_active(mdev)) 494 hw->netdev_features |= NETIF_F_HW_TC; 495 496 hw->radiotap_timestamp.units_pos = 497 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 498 499 hw->sta_data_size = sizeof(struct mt7996_sta); 500 hw->vif_data_size = sizeof(struct mt7996_vif); 501 hw->chanctx_data_size = sizeof(struct mt76_chanctx); 502 503 wiphy->iface_combinations = is_mt7996(&dev->mt76) ? &if_comb_global : 504 &if_comb_global_7992; 505 wiphy->n_iface_combinations = 1; 506 507 wiphy->radio = dev->radios; 508 wiphy->addresses = dev->radio_addrs; 509 510 wiphy->reg_notifier = mt7996_regd_notifier; 511 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH | 512 WIPHY_FLAG_SUPPORTS_MLO; 513 wiphy->mbssid_max_interfaces = 16; 514 wiphy->iftype_ext_capab = iftypes_ext_capa; 515 wiphy->num_iftype_ext_capab = ARRAY_SIZE(iftypes_ext_capa); 516 517 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 518 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 519 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 520 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 521 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 522 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 523 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 524 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 525 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 526 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 527 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER); 528 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 529 530 if (mt7996_eeprom_has_background_radar(dev) && 531 (!mdev->dev->of_node || 532 !of_property_read_bool(mdev->dev->of_node, 533 "mediatek,disable-radar-background"))) 534 wiphy_ext_feature_set(wiphy, 535 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 536 537 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 538 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 539 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 540 ieee80211_hw_set(hw, NO_VIRTUAL_MONITOR); 541 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 542 ieee80211_hw_set(hw, CHANCTX_STA_CSA); 543 ieee80211_hw_set(hw, CONNECTION_MONITOR); 544 545 hw->max_tx_fragments = 4; 546 wiphy->txq_memory_limit = 32 << 20; /* 32 MiB */ 547 548 /* init led callbacks */ 549 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 550 dev->mphy.leds.cdev.brightness_set = mt7996_led_set_brightness; 551 dev->mphy.leds.cdev.blink_set = mt7996_led_set_blink; 552 } 553 554 wiphy->max_scan_ssids = 4; 555 wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 556 557 mt7996_init_wiphy_band(hw, &dev->phy); 558 } 559 560 static void 561 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band) 562 { 563 u32 mask, set; 564 565 if (!mt7996_band_valid(dev, band)) 566 return; 567 568 /* clear estimated value of EIFS for Rx duration & OBSS time */ 569 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 570 571 /* clear backoff time for Rx duration */ 572 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 573 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 574 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 575 MT_WF_RMAC_MIB_QOS01_BACKOFF); 576 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 577 MT_WF_RMAC_MIB_QOS23_BACKOFF); 578 579 /* clear backoff time for Tx duration */ 580 mt76_clear(dev, MT_WTBLOFF_ACR(band), 581 MT_WTBLOFF_ADM_BACKOFFTIME); 582 583 /* clear backoff time and set software compensation for OBSS time */ 584 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 585 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 586 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 587 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 588 589 /* filter out non-resp frames and get instanstaeous signal reporting */ 590 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM; 591 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) | 592 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3); 593 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set); 594 595 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 596 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 597 */ 598 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 599 600 if (!is_mt7996(&dev->mt76)) 601 mt7996_mcu_set_bssid_mapping_addr(&dev->mt76, band); 602 } 603 604 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev) 605 { 606 int i; 607 608 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) { 609 u16 rate = mt76_rates[i].hw_value; 610 /* odd index for driver, even index for firmware */ 611 u16 idx = MT7996_BASIC_RATES_TBL + 2 * i; 612 613 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) | 614 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0)); 615 mt7996_mcu_set_fixed_rate_table(&dev->phy, idx, rate, false); 616 } 617 } 618 619 void mt7996_mac_init(struct mt7996_dev *dev) 620 { 621 #define HIF_TXD_V2_1 0x21 622 int i, rx_path_type; 623 624 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 625 626 for (i = 0; i < mt7996_wtbl_size(dev); i++) 627 mt7996_mac_wtbl_update(dev, i, 628 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 629 630 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 631 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; 632 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); 633 } 634 635 /* rro module init */ 636 if (dev->hif2) { 637 if (mt76_npu_device_active(&dev->mt76)) 638 rx_path_type = is_mt7996(&dev->mt76) ? 6 : 8; 639 else 640 rx_path_type = is_mt7996(&dev->mt76) ? 2 : 7; 641 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 642 rx_path_type); 643 } else { 644 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 0); 645 } 646 647 if (mt7996_has_hwrro(dev)) { 648 u16 timeout; 649 650 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128; 651 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout); 652 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 653 is_mt7996(&dev->mt76) ? 1 : 2); 654 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 655 !is_mt7996(&dev->mt76)); 656 } else { 657 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); 658 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); 659 } 660 661 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), 662 MCU_WA_PARAM_HW_PATH_HIF_VER, 663 HIF_TXD_V2_1, 0); 664 665 for (i = MT_BAND0; i <= MT_BAND2; i++) 666 mt7996_mac_init_band(dev, i); 667 668 mt7996_mac_init_basic_rates(dev); 669 } 670 671 int mt7996_txbf_init(struct mt7996_dev *dev) 672 { 673 int ret; 674 675 if (mt7996_band_valid(dev, MT_BAND1) || 676 mt7996_band_valid(dev, MT_BAND2)) { 677 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL); 678 if (ret) 679 return ret; 680 } 681 682 /* trigger sounding packets */ 683 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON); 684 if (ret) 685 return ret; 686 687 /* enable eBF */ 688 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 689 } 690 691 static int mt7996_register_phy(struct mt7996_dev *dev, enum mt76_band_id band) 692 { 693 struct mt7996_phy *phy; 694 struct mt76_phy *mphy; 695 u32 mac_ofs, hif1_ofs = 0; 696 int ret; 697 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 698 699 if (!mt7996_band_valid(dev, band)) 700 return 0; 701 702 if (dev->hif2 && 703 ((is_mt7992(&dev->mt76) && band == MT_BAND1) || 704 (is_mt7996(&dev->mt76) && band == MT_BAND2 && 705 !mt76_npu_device_active(&dev->mt76)))) { 706 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 707 wed = &dev->mt76.mmio.wed_hif2; 708 } 709 710 mphy = mt76_alloc_radio_phy(&dev->mt76, sizeof(*phy), band); 711 if (!mphy) 712 return -ENOMEM; 713 714 phy = mphy->priv; 715 phy->dev = dev; 716 phy->mt76 = mphy; 717 mphy->dev->phys[band] = mphy; 718 719 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work); 720 721 ret = mt7996_eeprom_parse_hw_cap(dev, phy); 722 if (ret) 723 goto error; 724 725 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2; 726 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN); 727 /* Make the extra PHY MAC address local without overlapping with 728 * the usual MAC address allocation scheme on multiple virtual interfaces 729 */ 730 if (!is_valid_ether_addr(mphy->macaddr)) { 731 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 732 ETH_ALEN); 733 mphy->macaddr[0] |= 2; 734 mphy->macaddr[0] ^= BIT(7); 735 if (band == MT_BAND2) 736 mphy->macaddr[0] ^= BIT(6); 737 } 738 ret = mt76_eeprom_override(mphy); 739 if (ret) 740 goto error; 741 742 /* init wiphy according to mphy and phy */ 743 mt7996_init_wiphy_band(mphy->hw, phy); 744 745 if (is_mt7996(&dev->mt76) && 746 ((band == MT_BAND1 && !dev->hif2) || 747 (band == MT_BAND2 && mt76_npu_device_active(&dev->mt76)))) { 748 int i; 749 750 for (i = 0; i <= MT_TXQ_PSD; i++) 751 mphy->q_tx[i] = dev->mt76.phys[band - 1]->q_tx[0]; 752 } else { 753 int size = is_mt7996(&dev->mt76) && 754 mt76_npu_device_active(&dev->mt76) 755 ? MT7996_NPU_TX_RING_SIZE / 2 : MT7996_TX_RING_SIZE; 756 757 ret = mt7996_init_tx_queues(mphy->priv, MT_TXQ_ID(band), size, 758 MT_TXQ_RING_BASE(band) + hif1_ofs, 759 wed); 760 if (ret) 761 goto error; 762 } 763 764 ret = mt76_register_phy(mphy, true, mt76_rates, 765 ARRAY_SIZE(mt76_rates)); 766 if (ret) 767 goto error; 768 769 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) { 770 mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TX_RX_DONE_EXT); 771 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, 772 MT_INT_TX_RX_DONE_EXT); 773 } 774 775 return 0; 776 777 error: 778 mphy->dev->phys[band] = NULL; 779 return ret; 780 } 781 782 static void 783 mt7996_unregister_phy(struct mt7996_phy *phy) 784 { 785 if (phy) 786 mt7996_unregister_thermal(phy); 787 } 788 789 static void mt7996_init_work(struct work_struct *work) 790 { 791 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, 792 init_work); 793 794 mt7996_mcu_set_eeprom(dev); 795 mt7996_mac_init(dev); 796 mt7996_txbf_init(dev); 797 798 if (!is_mt7990(&dev->mt76)) 799 mt7996_mcu_set_dup_wtbl(dev); 800 } 801 802 void mt7996_wfsys_reset(struct mt7996_dev *dev) 803 { 804 if (!is_mt7990(&dev->mt76)) { 805 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 806 msleep(20); 807 808 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 809 msleep(20); 810 811 return; 812 } 813 814 if (!dev->recovery.hw_full_reset) 815 return; 816 817 mt76_set(dev, MT_WF_SUBSYS_RST, 818 MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT | 819 MT_WF_SUBSYS_RST_BYPASS_WFDMA_SLP_PROT | 820 MT_WF_SUBSYS_RST_BYPASS_WFDMA2_SLP_PROT); 821 mt76_rmw(dev, MT_WF_SUBSYS_RST, 822 MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE, 823 u32_encode_bits(0x20, MT_WF_SUBSYS_RST_WHOLE_PATH_RST_REVERT_CYCLE)); 824 mt76_clear(dev, MT_WF_L05_RST, MT_WF_L05_RST_WF_RST_MASK); 825 mt76_set(dev, MT_WF_SUBSYS_RST, MT_WF_SUBSYS_RST_WHOLE_PATH_RST); 826 msleep(20); 827 828 if (mt76_poll(dev, MT_WF_L05_RST, MT_WF_L05_RST_WF_RST_MASK, 0x1a, 1000)) 829 return; 830 831 dev_err(dev->mt76.dev, "wfsys reset fail\n"); 832 } 833 834 static void mt7996_rro_hw_init_v3(struct mt7996_dev *dev) 835 { 836 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 837 u32 session_id; 838 839 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) 840 return; 841 842 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 843 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 844 wed->wlan.ind_cmd.win_size = 845 ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6; 846 if (is_mt7996(&dev->mt76)) 847 wed->wlan.ind_cmd.particular_sid = 848 MT7996_RRO_MAX_SESSION; 849 else 850 wed->wlan.ind_cmd.particular_sid = 1; 851 wed->wlan.ind_cmd.particular_se_phys = 852 dev->wed_rro.session.phy_addr; 853 wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN; 854 wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL; 855 } 856 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 857 858 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) { 859 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00); 860 mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 861 MT_RRO_IND_CMD_SIGNATURE_BASE1_EN); 862 } else { 863 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0); 864 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 0); 865 } 866 867 /* particular session configure */ 868 /* use max session idx + 1 as particular session id */ 869 mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr); 870 871 session_id = is_mt7996(&dev->mt76) ? MT7996_RRO_MAX_SESSION : 1; 872 mt76_wr(dev, MT_RRO_PARTICULAR_CFG1, 873 MT_RRO_PARTICULAR_CONFG_EN | 874 FIELD_PREP(MT_RRO_PARTICULAR_SID, session_id)); 875 } 876 877 void mt7996_rro_hw_init(struct mt7996_dev *dev) 878 { 879 u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0; 880 int i; 881 882 if (!mt7996_has_hwrro(dev)) 883 return; 884 885 INIT_LIST_HEAD(&dev->wed_rro.page_cache); 886 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.page_map); i++) 887 INIT_LIST_HEAD(&dev->wed_rro.page_map[i]); 888 889 if (!is_mt7996(&dev->mt76)) { 890 reg = MT_RRO_MSDU_PG_SEG_ADDR0; 891 892 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 893 mt76_clear(dev, MT_RRO_3_0_EMU_CONF, 894 MT_RRO_3_0_EMU_CONF_EN_MASK); 895 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 896 MT_RRO_3_1_GLOBAL_CONFIG_RXDMAD_SEL); 897 if (!mtk_wed_device_active(&dev->mt76.mmio.wed) && 898 !mt76_npu_device_active(&dev->mt76)) { 899 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 900 MT_RRO_3_1_GLOBAL_CONFIG_RX_DIDX_WR_EN | 901 MT_RRO_3_1_GLOBAL_CONFIG_RX_CIDX_RD_EN); 902 mt76_wr(dev, MT_RRO_RX_RING_AP_CIDX_ADDR, 903 dev->wed_rro.emi_rings_cpu.phy_addr >> 4); 904 mt76_wr(dev, MT_RRO_RX_RING_AP_DIDX_ADDR, 905 dev->wed_rro.emi_rings_dma.phy_addr >> 4); 906 } 907 } else { 908 /* set emul 3.0 function */ 909 mt76_set(dev, MT_RRO_3_0_EMU_CONF, MT_RRO_3_0_EMU_CONF_EN_MASK); 910 911 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE0, 912 dev->wed_rro.addr_elem[0].phy_addr); 913 } 914 915 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG, 916 MT_RRO_3_1_GLOBAL_CONFIG_INTERLEAVE_EN); 917 918 /* setup Msdu page address */ 919 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 920 mt76_wr(dev, reg, 921 dev->wed_rro.msdu_pg[i].phy_addr >> 4); 922 reg += 4; 923 } 924 } else { 925 /* TODO: remove line after WM has set */ 926 mt76_clear(dev, WF_RRO_AXI_MST_CFG, 927 WF_RRO_AXI_MST_CFG_DIDX_OK); 928 929 /* setup BA bitmap cache address */ 930 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0, 931 dev->wed_rro.ba_bitmap[0].phy_addr); 932 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0); 933 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0, 934 dev->wed_rro.ba_bitmap[1].phy_addr); 935 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0); 936 937 /* Setup Address element address */ 938 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 939 mt76_wr(dev, reg, 940 dev->wed_rro.addr_elem[i].phy_addr >> 4); 941 reg += 4; 942 } 943 944 /* Setup Address element address - separate address segment 945 * mode. 946 */ 947 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1, 948 MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE); 949 } 950 951 mt7996_rro_hw_init_v3(dev); 952 953 /* interrupt enable */ 954 mt76_wr(dev, MT_RRO_HOST_INT_ENA, 955 MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA); 956 } 957 958 static int mt7996_wed_rro_init(struct mt7996_dev *dev) 959 { 960 u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff); 961 struct mt7996_wed_rro_addr *addr; 962 void *ptr; 963 int i; 964 965 if (!mt7996_has_hwrro(dev)) 966 return 0; 967 968 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3) { 969 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 970 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 971 MT7996_RRO_BA_BITMAP_CR_SIZE, 972 &dev->wed_rro.ba_bitmap[i].phy_addr, 973 GFP_KERNEL); 974 if (!ptr) 975 return -ENOMEM; 976 977 dev->wed_rro.ba_bitmap[i].ptr = ptr; 978 } 979 } 980 981 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 982 int j; 983 984 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 985 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr), 986 &dev->wed_rro.addr_elem[i].phy_addr, 987 GFP_KERNEL); 988 if (!ptr) 989 return -ENOMEM; 990 991 dev->wed_rro.addr_elem[i].ptr = ptr; 992 memset(dev->wed_rro.addr_elem[i].ptr, 0, 993 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr)); 994 995 addr = dev->wed_rro.addr_elem[i].ptr; 996 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) { 997 addr->data = cpu_to_le32(val); 998 addr++; 999 } 1000 1001 if (is_mt7996(&dev->mt76) && 1002 mt76_npu_device_active(&dev->mt76)) 1003 mt76_npu_send_txrx_addr(&dev->mt76, 0, i, 1004 dev->wed_rro.addr_elem[i].phy_addr, 1005 0, 0); 1006 1007 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 1008 if (mtk_wed_device_active(&dev->mt76.mmio.wed) && 1009 mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) { 1010 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 1011 1012 wed->wlan.ind_cmd.addr_elem_phys[i] = 1013 dev->wed_rro.addr_elem[i].phy_addr; 1014 } 1015 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 1016 } 1017 1018 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 1019 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 1020 MT7996_RRO_MSDU_PG_SIZE_PER_CR, 1021 &dev->wed_rro.msdu_pg[i].phy_addr, 1022 GFP_KERNEL); 1023 if (!ptr) 1024 return -ENOMEM; 1025 1026 dev->wed_rro.msdu_pg[i].ptr = ptr; 1027 1028 memset(dev->wed_rro.msdu_pg[i].ptr, 0, 1029 MT7996_RRO_MSDU_PG_SIZE_PER_CR); 1030 } 1031 1032 if (!mtk_wed_device_active(&dev->mt76.mmio.wed) && 1033 dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) { 1034 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 1035 sizeof(*dev->wed_rro.emi_rings_cpu.ptr), 1036 &dev->wed_rro.emi_rings_cpu.phy_addr, 1037 GFP_KERNEL); 1038 if (!ptr) 1039 return -ENOMEM; 1040 1041 dev->wed_rro.emi_rings_cpu.ptr = ptr; 1042 1043 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 1044 sizeof(*dev->wed_rro.emi_rings_dma.ptr), 1045 &dev->wed_rro.emi_rings_dma.phy_addr, 1046 GFP_KERNEL); 1047 if (!ptr) 1048 return -ENOMEM; 1049 1050 dev->wed_rro.emi_rings_dma.ptr = ptr; 1051 } 1052 1053 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 1054 MT7996_RRO_WINDOW_MAX_LEN * sizeof(*addr), 1055 &dev->wed_rro.session.phy_addr, 1056 GFP_KERNEL); 1057 if (!ptr) 1058 return -ENOMEM; 1059 1060 dev->wed_rro.session.ptr = ptr; 1061 addr = dev->wed_rro.session.ptr; 1062 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 1063 addr->data = cpu_to_le32(val); 1064 addr++; 1065 } 1066 1067 if (is_mt7996(&dev->mt76) && mt76_npu_device_active(&dev->mt76)) 1068 mt76_npu_send_txrx_addr(&dev->mt76, 1, 0, 1069 dev->wed_rro.session.phy_addr, 0, 0); 1070 1071 mt7996_rro_hw_init(dev); 1072 1073 return mt7996_dma_rro_init(dev); 1074 } 1075 1076 static void mt7996_wed_rro_free(struct mt7996_dev *dev) 1077 { 1078 int i; 1079 1080 if (!mt7996_has_hwrro(dev)) 1081 return; 1082 1083 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 1084 if (!dev->wed_rro.ba_bitmap[i].ptr) 1085 continue; 1086 1087 dmam_free_coherent(dev->mt76.dma_dev, 1088 MT7996_RRO_BA_BITMAP_CR_SIZE, 1089 dev->wed_rro.ba_bitmap[i].ptr, 1090 dev->wed_rro.ba_bitmap[i].phy_addr); 1091 } 1092 1093 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 1094 if (!dev->wed_rro.addr_elem[i].ptr) 1095 continue; 1096 1097 dmam_free_coherent(dev->mt76.dma_dev, 1098 MT7996_RRO_WINDOW_MAX_SIZE * 1099 sizeof(struct mt7996_wed_rro_addr), 1100 dev->wed_rro.addr_elem[i].ptr, 1101 dev->wed_rro.addr_elem[i].phy_addr); 1102 } 1103 1104 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) { 1105 if (!dev->wed_rro.msdu_pg[i].ptr) 1106 continue; 1107 1108 dmam_free_coherent(dev->mt76.dma_dev, 1109 MT7996_RRO_MSDU_PG_SIZE_PER_CR, 1110 dev->wed_rro.msdu_pg[i].ptr, 1111 dev->wed_rro.msdu_pg[i].phy_addr); 1112 } 1113 1114 if (dev->wed_rro.emi_rings_cpu.ptr) 1115 dmam_free_coherent(dev->mt76.dma_dev, 1116 sizeof(*dev->wed_rro.emi_rings_cpu.ptr), 1117 dev->wed_rro.emi_rings_cpu.ptr, 1118 dev->wed_rro.emi_rings_cpu.phy_addr); 1119 1120 if (dev->wed_rro.emi_rings_dma.ptr) 1121 dmam_free_coherent(dev->mt76.dma_dev, 1122 sizeof(*dev->wed_rro.emi_rings_dma.ptr), 1123 dev->wed_rro.emi_rings_dma.ptr, 1124 dev->wed_rro.emi_rings_dma.phy_addr); 1125 1126 if (!dev->wed_rro.session.ptr) 1127 return; 1128 1129 dmam_free_coherent(dev->mt76.dma_dev, 1130 MT7996_RRO_WINDOW_MAX_LEN * 1131 sizeof(struct mt7996_wed_rro_addr), 1132 dev->wed_rro.session.ptr, 1133 dev->wed_rro.session.phy_addr); 1134 } 1135 1136 static void mt7996_wed_rro_work(struct work_struct *work) 1137 { 1138 u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff); 1139 struct mt7996_dev *dev; 1140 LIST_HEAD(list); 1141 1142 dev = (struct mt7996_dev *)container_of(work, struct mt7996_dev, 1143 wed_rro.work); 1144 1145 spin_lock_bh(&dev->wed_rro.lock); 1146 list_splice_init(&dev->wed_rro.poll_list, &list); 1147 spin_unlock_bh(&dev->wed_rro.lock); 1148 1149 while (!list_empty(&list)) { 1150 struct mt7996_wed_rro_session_id *e; 1151 int i; 1152 1153 e = list_first_entry(&list, struct mt7996_wed_rro_session_id, 1154 list); 1155 list_del_init(&e->list); 1156 1157 if (mt76_npu_device_active(&dev->mt76)) { 1158 if (is_mt7996(&dev->mt76)) 1159 mt76_npu_send_txrx_addr(&dev->mt76, 3, e->id, 1160 0, 0, 0); 1161 goto reset_session; 1162 } 1163 1164 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 1165 void *ptr = dev->wed_rro.session.ptr; 1166 struct mt7996_wed_rro_addr *elem; 1167 u32 idx, elem_id = i; 1168 1169 if (e->id == MT7996_RRO_MAX_SESSION) 1170 goto reset; 1171 1172 idx = e->id / MT7996_RRO_BA_BITMAP_SESSION_SIZE; 1173 if (idx >= ARRAY_SIZE(dev->wed_rro.addr_elem)) 1174 goto out; 1175 1176 ptr = dev->wed_rro.addr_elem[idx].ptr; 1177 elem_id += 1178 (e->id % MT7996_RRO_BA_BITMAP_SESSION_SIZE) * 1179 MT7996_RRO_WINDOW_MAX_LEN; 1180 reset: 1181 elem = ptr + elem_id * sizeof(*elem); 1182 elem->data |= cpu_to_le32(val); 1183 } 1184 reset_session: 1185 mt7996_mcu_wed_rro_reset_sessions(dev, e->id); 1186 out: 1187 kfree(e); 1188 } 1189 } 1190 1191 static int mt7996_variant_type_init(struct mt7996_dev *dev) 1192 { 1193 u32 val = mt76_rr(dev, MT_PAD_GPIO); 1194 u8 var_type; 1195 1196 switch (mt76_chip(&dev->mt76)) { 1197 case MT7996_DEVICE_ID: 1198 if (val & MT_PAD_GPIO_2ADIE_TBTC) 1199 var_type = MT7996_VAR_TYPE_233; 1200 else 1201 var_type = MT7996_VAR_TYPE_444; 1202 break; 1203 case MT7992_DEVICE_ID: 1204 if (val & MT_PAD_GPIO_ADIE_SINGLE) 1205 var_type = MT7992_VAR_TYPE_23; 1206 else if (u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992)) 1207 var_type = MT7992_VAR_TYPE_44; 1208 else 1209 var_type = MT7992_VAR_TYPE_24; 1210 break; 1211 case MT7990_DEVICE_ID: 1212 var_type = MT7990_VAR_TYPE_23; 1213 break; 1214 default: 1215 return -EINVAL; 1216 } 1217 1218 dev->var.type = var_type; 1219 return 0; 1220 } 1221 1222 static int mt7996_variant_fem_init(struct mt7996_dev *dev) 1223 { 1224 #define MT7976C_EFUSE_OFFSET 0x470 1225 u8 buf[MT7996_EEPROM_BLOCK_SIZE], idx, adie_idx, adie_comb; 1226 u32 regval, val = mt76_rr(dev, MT_PAD_GPIO); 1227 u16 adie_id, adie_ver; 1228 bool is_7976c; 1229 int ret; 1230 1231 if (is_mt7992(&dev->mt76)) { 1232 adie_idx = (val & MT_PAD_GPIO_ADIE_SINGLE) ? 0 : 1; 1233 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992); 1234 } else { 1235 adie_idx = 0; 1236 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB); 1237 } 1238 1239 ret = mt7996_mcu_rf_regval(dev, MT_ADIE_CHIP_ID(adie_idx), ®val, false); 1240 if (ret) 1241 return ret; 1242 1243 ret = mt7996_mcu_get_eeprom(dev, MT7976C_EFUSE_OFFSET, buf, sizeof(buf), 1244 EEPROM_MODE_EFUSE); 1245 if (ret && ret != -EINVAL) 1246 return ret; 1247 1248 adie_ver = u32_get_bits(regval, MT_ADIE_VERSION_MASK); 1249 idx = MT7976C_EFUSE_OFFSET % MT7996_EEPROM_BLOCK_SIZE; 1250 is_7976c = adie_ver == 0x8a10 || adie_ver == 0x8b00 || 1251 adie_ver == 0x8c10 || (!ret && buf[idx] == 0xc); 1252 1253 adie_id = u32_get_bits(regval, MT_ADIE_CHIP_ID_MASK); 1254 if (adie_id == 0x7975 || adie_id == 0x7979 || 1255 (adie_id == 0x7976 && is_7976c)) 1256 dev->var.fem = MT7996_FEM_INT; 1257 else if (adie_id == 0x7977 && adie_comb == 1) 1258 dev->var.fem = MT7996_FEM_MIX; 1259 else 1260 dev->var.fem = MT7996_FEM_EXT; 1261 1262 return 0; 1263 } 1264 1265 static int mt7996_init_hardware(struct mt7996_dev *dev) 1266 { 1267 int ret, idx; 1268 1269 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1270 if (is_mt7992(&dev->mt76)) { 1271 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 1272 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 1273 } 1274 1275 INIT_WORK(&dev->init_work, mt7996_init_work); 1276 INIT_WORK(&dev->wed_rro.work, mt7996_wed_rro_work); 1277 INIT_LIST_HEAD(&dev->wed_rro.poll_list); 1278 spin_lock_init(&dev->wed_rro.lock); 1279 1280 ret = mt7996_variant_type_init(dev); 1281 if (ret) 1282 return ret; 1283 1284 ret = mt7996_dma_init(dev); 1285 if (ret) 1286 return ret; 1287 1288 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 1289 1290 ret = mt7996_mcu_init(dev); 1291 if (ret) 1292 return ret; 1293 1294 ret = mt7996_wed_rro_init(dev); 1295 if (ret) 1296 return ret; 1297 1298 ret = mt7996_variant_fem_init(dev); 1299 if (ret) 1300 return ret; 1301 1302 ret = mt7996_eeprom_init(dev); 1303 if (ret < 0) 1304 return ret; 1305 1306 /* Beacon and mgmt frames should occupy wcid 0 */ 1307 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA); 1308 if (idx) 1309 return -ENOSPC; 1310 1311 dev->mt76.global_wcid.idx = idx; 1312 dev->mt76.global_wcid.hw_key_idx = -1; 1313 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 1314 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 1315 1316 return 0; 1317 } 1318 1319 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy) 1320 { 1321 int sts; 1322 u32 *cap; 1323 1324 if (!phy->mt76->cap.has_5ghz) 1325 return; 1326 1327 sts = hweight16(phy->mt76->chainmask); 1328 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 1329 1330 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 1331 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 1332 1333 if (is_mt7992(phy->mt76->dev)) 1334 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 4); 1335 else 1336 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 3); 1337 1338 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 1339 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1340 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 1341 1342 if (sts < 2) 1343 return; 1344 1345 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1346 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 1347 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1); 1348 } 1349 1350 static void 1351 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy, 1352 struct ieee80211_sta_he_cap *he_cap, int vif, 1353 enum nl80211_band band) 1354 { 1355 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 1356 int sts = hweight16(phy->mt76->chainmask); 1357 bool non_2g = band != NL80211_BAND_2GHZ; 1358 u8 c; 1359 1360 #ifdef CONFIG_MAC80211_MESH 1361 if (vif == NL80211_IFTYPE_MESH_POINT) 1362 return; 1363 #endif 1364 1365 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1366 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1367 1368 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK | 1369 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 1370 elem->phy_cap_info[5] &= ~c; 1371 1372 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1373 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1374 elem->phy_cap_info[6] &= ~c; 1375 1376 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 1377 1378 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 1379 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO; 1380 elem->phy_cap_info[2] |= c; 1381 1382 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE; 1383 1384 if (is_mt7992(phy->mt76->dev)) 1385 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5 | 1386 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5 * non_2g); 1387 else 1388 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 | 1389 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4 * non_2g); 1390 1391 elem->phy_cap_info[4] |= c; 1392 1393 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 1394 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 1395 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 1396 1397 if (vif == NL80211_IFTYPE_STATION) 1398 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 1399 1400 elem->phy_cap_info[6] |= c; 1401 1402 if (sts < 2) 1403 return; 1404 1405 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 1406 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 1407 1408 if (!(vif == NL80211_IFTYPE_AP || vif == NL80211_IFTYPE_STATION)) 1409 return; 1410 1411 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1412 1413 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 1414 sts - 1) | 1415 (FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 1416 sts - 1) * non_2g); 1417 1418 elem->phy_cap_info[5] |= c; 1419 1420 if (vif != NL80211_IFTYPE_AP) 1421 return; 1422 1423 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1424 1425 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1426 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1427 elem->phy_cap_info[6] |= c; 1428 1429 c = 0; 1430 if (non_2g) 1431 c |= IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 1432 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 1433 elem->phy_cap_info[7] |= c; 1434 } 1435 1436 static void 1437 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band, 1438 struct ieee80211_sband_iftype_data *data, 1439 enum nl80211_iftype iftype) 1440 { 1441 struct ieee80211_sta_he_cap *he_cap = &data->he_cap; 1442 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem; 1443 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp; 1444 int i, nss = hweight8(phy->mt76->antenna_mask); 1445 u16 mcs_map = 0; 1446 1447 for (i = 0; i < 8; i++) { 1448 if (i < nss) 1449 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1450 else 1451 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1452 } 1453 1454 he_cap->has_he = true; 1455 1456 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 1457 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1458 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1459 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1460 1461 if (band == NL80211_BAND_2GHZ) 1462 he_cap_elem->phy_cap_info[0] = 1463 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1464 else 1465 he_cap_elem->phy_cap_info[0] = 1466 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1467 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1468 1469 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1470 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1471 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1472 1473 he_cap_elem->phy_cap_info[7] = 1474 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1475 1476 switch (iftype) { 1477 case NL80211_IFTYPE_AP: 1478 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES; 1479 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR; 1480 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR; 1481 he_cap_elem->mac_cap_info[5] |= 1482 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1483 he_cap_elem->phy_cap_info[3] |= 1484 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1485 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1486 he_cap_elem->phy_cap_info[6] |= 1487 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1488 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1489 he_cap_elem->phy_cap_info[9] |= 1490 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1491 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1492 break; 1493 case NL80211_IFTYPE_STATION: 1494 he_cap_elem->mac_cap_info[1] |= 1495 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1496 1497 if (band == NL80211_BAND_2GHZ) 1498 he_cap_elem->phy_cap_info[0] |= 1499 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1500 else 1501 he_cap_elem->phy_cap_info[0] |= 1502 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1503 1504 he_cap_elem->phy_cap_info[1] |= 1505 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1506 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1507 he_cap_elem->phy_cap_info[3] |= 1508 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1509 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1510 he_cap_elem->phy_cap_info[6] |= 1511 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1512 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1513 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1514 he_cap_elem->phy_cap_info[7] |= 1515 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP; 1516 he_cap_elem->phy_cap_info[8] |= 1517 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1518 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1519 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 1520 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1521 he_cap_elem->phy_cap_info[9] |= 1522 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1523 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1524 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1525 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1526 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1527 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1528 break; 1529 default: 1530 break; 1531 } 1532 1533 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1534 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1535 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map); 1536 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map); 1537 1538 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype, band); 1539 1540 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1541 if (he_cap_elem->phy_cap_info[6] & 1542 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1543 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band); 1544 } else { 1545 he_cap_elem->phy_cap_info[9] |= 1546 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1547 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1548 } 1549 1550 if (band == NL80211_BAND_6GHZ) { 1551 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1552 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1553 1554 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5, 1555 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1556 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1557 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1558 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1559 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1560 1561 data->he_6ghz_capa.capa = cpu_to_le16(cap); 1562 } 1563 } 1564 1565 static void 1566 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band, 1567 struct ieee80211_sband_iftype_data *data, 1568 enum nl80211_iftype iftype) 1569 { 1570 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap; 1571 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem; 1572 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp; 1573 int nss = hweight8(phy->mt76->antenna_mask); 1574 int sts = hweight16(phy->mt76->chainmask); 1575 u8 val; 1576 1577 if (!phy->dev->has_eht) 1578 return; 1579 1580 eht_cap->has_eht = true; 1581 1582 eht_cap_elem->mac_cap_info[0] = 1583 IEEE80211_EHT_MAC_CAP0_OM_CONTROL | 1584 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454, 1585 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 1586 1587 eht_cap_elem->mac_cap_info[1] |= 1588 IEEE80211_EHT_MAC_CAP1_MAX_AMPDU_LEN_MASK; 1589 1590 eht_cap_elem->phy_cap_info[0] = 1591 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 1592 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER | 1593 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 1594 1595 /* Set the maximum capability regardless of the antenna configuration. */ 1596 val = is_mt7992(phy->mt76->dev) ? 4 : 3; 1597 eht_cap_elem->phy_cap_info[0] |= 1598 u8_encode_bits(u8_get_bits(val, BIT(0)), 1599 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 1600 1601 eht_cap_elem->phy_cap_info[1] = 1602 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)), 1603 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK); 1604 1605 eht_cap_elem->phy_cap_info[2] = 1606 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK); 1607 1608 if (band != NL80211_BAND_2GHZ) { 1609 eht_cap_elem->phy_cap_info[1] |= 1610 u8_encode_bits(val, 1611 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 1612 1613 eht_cap_elem->phy_cap_info[2] |= 1614 u8_encode_bits(sts - 1, 1615 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK); 1616 } 1617 1618 if (band == NL80211_BAND_6GHZ) { 1619 eht_cap_elem->phy_cap_info[0] |= 1620 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 1621 1622 eht_cap_elem->phy_cap_info[1] |= 1623 u8_encode_bits(val, 1624 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 1625 1626 eht_cap_elem->phy_cap_info[2] |= 1627 u8_encode_bits(sts - 1, 1628 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK); 1629 } 1630 1631 eht_cap_elem->phy_cap_info[3] = 1632 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 1633 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 1634 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 1635 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK; 1636 1637 eht_cap_elem->phy_cap_info[4] = 1638 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI | 1639 u8_encode_bits(min_t(int, sts - 1, 2), 1640 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 1641 1642 eht_cap_elem->phy_cap_info[5] = 1643 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US, 1644 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) | 1645 u8_encode_bits(u8_get_bits(1, GENMASK(1, 0)), 1646 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK); 1647 1648 eht_cap_elem->phy_cap_info[6] = IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK; 1649 if (band != NL80211_BAND_6GHZ) { 1650 eht_cap_elem->phy_cap_info[6] &= 1651 ~IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_320MHZ; 1652 1653 if (band != NL80211_BAND_5GHZ) 1654 eht_cap_elem->phy_cap_info[6] &= 1655 ~(IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_160MHZ | 1656 IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_80MHZ); 1657 } 1658 1659 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) | 1660 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX); 1661 #define SET_EHT_MAX_NSS(_bw, _val) do { \ 1662 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \ 1663 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \ 1664 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \ 1665 } while (0) 1666 1667 SET_EHT_MAX_NSS(80, val); 1668 SET_EHT_MAX_NSS(160, val); 1669 if (band == NL80211_BAND_6GHZ) 1670 SET_EHT_MAX_NSS(320, val); 1671 #undef SET_EHT_MAX_NSS 1672 1673 if (iftype != NL80211_IFTYPE_AP) 1674 return; 1675 1676 eht_cap_elem->phy_cap_info[3] |= 1677 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 1678 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 1679 1680 eht_cap_elem->phy_cap_info[7] = 1681 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ | 1682 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ; 1683 1684 if (band == NL80211_BAND_2GHZ) 1685 return; 1686 1687 eht_cap_elem->phy_cap_info[7] |= 1688 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ | 1689 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ; 1690 1691 if (band != NL80211_BAND_6GHZ) 1692 return; 1693 1694 eht_cap_elem->phy_cap_info[7] |= 1695 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ | 1696 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ; 1697 } 1698 1699 static void 1700 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy, 1701 struct ieee80211_supported_band *sband, 1702 enum nl80211_band band) 1703 { 1704 struct ieee80211_sband_iftype_data *data = phy->iftype[band]; 1705 int i, n = 0; 1706 1707 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 1708 switch (i) { 1709 case NL80211_IFTYPE_STATION: 1710 case NL80211_IFTYPE_AP: 1711 #ifdef CONFIG_MAC80211_MESH 1712 case NL80211_IFTYPE_MESH_POINT: 1713 #endif 1714 break; 1715 default: 1716 continue; 1717 } 1718 1719 data[n].types_mask = BIT(i); 1720 mt7996_init_he_caps(phy, band, &data[n], i); 1721 mt7996_init_eht_caps(phy, band, &data[n], i); 1722 1723 n++; 1724 } 1725 1726 _ieee80211_set_sband_iftype_data(sband, data, n); 1727 } 1728 1729 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy) 1730 { 1731 if (phy->mt76->cap.has_2ghz) 1732 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband, 1733 NL80211_BAND_2GHZ); 1734 1735 if (phy->mt76->cap.has_5ghz) 1736 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband, 1737 NL80211_BAND_5GHZ); 1738 1739 if (phy->mt76->cap.has_6ghz) 1740 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband, 1741 NL80211_BAND_6GHZ); 1742 } 1743 1744 int mt7996_register_device(struct mt7996_dev *dev) 1745 { 1746 struct ieee80211_hw *hw = mt76_hw(dev); 1747 struct mt7996_phy *phy; 1748 int ret; 1749 1750 dev->phy.dev = dev; 1751 dev->phy.mt76 = &dev->mt76.phy; 1752 dev->mt76.phy.priv = &dev->phy; 1753 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work); 1754 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work); 1755 INIT_LIST_HEAD(&dev->sta_rc_list); 1756 INIT_LIST_HEAD(&dev->twt_list); 1757 1758 init_waitqueue_head(&dev->reset_wait); 1759 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work); 1760 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work); 1761 mutex_init(&dev->dump_mutex); 1762 1763 ret = mt7996_init_hardware(dev); 1764 if (ret) 1765 return ret; 1766 1767 mt7996_init_wiphy(hw, &dev->mt76.mmio.wed); 1768 1769 ret = mt7996_register_phy(dev, MT_BAND1); 1770 if (ret) 1771 return ret; 1772 1773 ret = mt7996_register_phy(dev, MT_BAND2); 1774 if (ret) 1775 return ret; 1776 1777 ret = mt7996_npu_hw_init(dev); 1778 if (ret) 1779 return ret; 1780 1781 mt7996_dma_rro_start(dev); 1782 1783 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1784 ARRAY_SIZE(mt76_rates)); 1785 if (ret) 1786 return ret; 1787 1788 mt7996_for_each_phy(dev, phy) 1789 mt7996_thermal_init(phy); 1790 1791 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1792 1793 dev->recovery.hw_init_done = true; 1794 1795 ret = mt7996_init_debugfs(dev); 1796 if (ret) 1797 goto error; 1798 1799 ret = mt7996_coredump_register(dev); 1800 if (ret) 1801 goto error; 1802 1803 return 0; 1804 1805 error: 1806 cancel_work_sync(&dev->init_work); 1807 1808 return ret; 1809 } 1810 1811 void mt7996_unregister_device(struct mt7996_dev *dev) 1812 { 1813 cancel_work_sync(&dev->dump_work); 1814 cancel_work_sync(&dev->wed_rro.work); 1815 cancel_work_sync(&dev->reset_work); 1816 cancel_work_sync(&dev->rc_work); 1817 mt7996_unregister_phy(mt7996_phy3(dev)); 1818 mt7996_unregister_phy(mt7996_phy2(dev)); 1819 mt7996_unregister_thermal(&dev->phy); 1820 mt7996_coredump_unregister(dev); 1821 mt76_unregister_device(&dev->mt76); 1822 mt7996_wed_rro_free(dev); 1823 mt7996_mcu_exit(dev); 1824 mt7996_tx_token_put(dev); 1825 mt7996_dma_cleanup(dev); 1826 if (mt7996_has_hwrro(dev) && 1827 !mtk_wed_device_active(&dev->mt76.mmio.wed)) 1828 mt7996_rro_msdu_page_map_free(dev); 1829 tasklet_disable(&dev->mt76.irq_tasklet); 1830 1831 mt76_free_device(&dev->mt76); 1832 } 1833