1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Base Board: https://www.ti.com/lit/zip/SPRR463 6 */ 7 8/dts-v1/; 9 10#include "k3-am68-sk-som.dtsi" 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy-cadence.h> 13#include <dt-bindings/phy/phy.h> 14 15#include "k3-serdes.h" 16 17/ { 18 compatible = "ti,am68-sk", "ti,j721s2"; 19 model = "Texas Instruments AM68 SK"; 20 21 chosen { 22 stdout-path = "serial2:115200n8"; 23 }; 24 25 aliases { 26 serial0 = &wkup_uart0; 27 serial1 = &mcu_uart0; 28 serial2 = &main_uart8; 29 mmc1 = &main_sdhci1; 30 can0 = &mcu_mcan0; 31 can1 = &mcu_mcan1; 32 can2 = &main_mcan6; 33 can3 = &main_mcan7; 34 ethernet0 = &cpsw_port1; 35 }; 36 37 vusb_main: regulator-vusb-main5v0 { 38 /* USB MAIN INPUT 5V DC */ 39 compatible = "regulator-fixed"; 40 regulator-name = "vusb-main5v0"; 41 regulator-min-microvolt = <5000000>; 42 regulator-max-microvolt = <5000000>; 43 regulator-always-on; 44 regulator-boot-on; 45 }; 46 47 vsys_5v0: regulator-vsys5v0 { 48 /* Output of LM61460 */ 49 compatible = "regulator-fixed"; 50 regulator-name = "vsys_5v0"; 51 regulator-min-microvolt = <5000000>; 52 regulator-max-microvolt = <5000000>; 53 vin-supply = <&vusb_main>; 54 regulator-always-on; 55 regulator-boot-on; 56 }; 57 58 vsys_3v3: regulator-vsys3v3 { 59 /* Output of LM5141 */ 60 compatible = "regulator-fixed"; 61 regulator-name = "vsys_3v3"; 62 regulator-min-microvolt = <3300000>; 63 regulator-max-microvolt = <3300000>; 64 vin-supply = <&vusb_main>; 65 regulator-always-on; 66 regulator-boot-on; 67 }; 68 69 vdd_mmc1: regulator-sd { 70 /* Output of TPS22918 */ 71 compatible = "regulator-fixed"; 72 regulator-name = "vdd_mmc1"; 73 regulator-min-microvolt = <3300000>; 74 regulator-max-microvolt = <3300000>; 75 regulator-boot-on; 76 enable-active-high; 77 vin-supply = <&vsys_3v3>; 78 gpio = <&exp1 8 GPIO_ACTIVE_HIGH>; 79 }; 80 81 vdd_sd_dv: regulator-tlv71033 { 82 /* Output of TLV71033 */ 83 compatible = "regulator-gpio"; 84 regulator-name = "tlv71033"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&vdd_sd_dv_pins_default>; 87 regulator-min-microvolt = <1800000>; 88 regulator-max-microvolt = <3300000>; 89 regulator-boot-on; 90 vin-supply = <&vsys_5v0>; 91 gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; 92 states = <1800000 0x0>, 93 <3300000 0x1>; 94 }; 95 96 vsys_io_1v8: regulator-vsys-io-1v8 { 97 compatible = "regulator-fixed"; 98 regulator-name = "vsys_io_1v8"; 99 regulator-min-microvolt = <1800000>; 100 regulator-max-microvolt = <1800000>; 101 regulator-always-on; 102 regulator-boot-on; 103 }; 104 105 vsys_io_1v2: regulator-vsys-io-1v2 { 106 compatible = "regulator-fixed"; 107 regulator-name = "vsys_io_1v2"; 108 regulator-min-microvolt = <1200000>; 109 regulator-max-microvolt = <1200000>; 110 regulator-always-on; 111 regulator-boot-on; 112 }; 113 114 transceiver1: can-phy0 { 115 compatible = "ti,tcan1042"; 116 #phy-cells = <0>; 117 max-bitrate = <5000000>; 118 }; 119 120 transceiver2: can-phy1 { 121 compatible = "ti,tcan1042"; 122 #phy-cells = <0>; 123 max-bitrate = <5000000>; 124 }; 125 126 transceiver3: can-phy2 { 127 compatible = "ti,tcan1042"; 128 #phy-cells = <0>; 129 max-bitrate = <5000000>; 130 }; 131 132 transceiver4: can-phy3 { 133 compatible = "ti,tcan1042"; 134 #phy-cells = <0>; 135 max-bitrate = <5000000>; 136 }; 137 138 edp0_refclk: clock-edp0-refclk { 139 compatible = "fixed-clock"; 140 clock-frequency = <19200000>; 141 #clock-cells = <0>; 142 }; 143 144 dp0_pwr_3v3: regulator-dp0-pwr { 145 compatible = "regulator-fixed"; 146 regulator-name = "dp0-pwr"; 147 regulator-min-microvolt = <3300000>; 148 regulator-max-microvolt = <3300000>; 149 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; /*P0 - DP0_3V3 _EN */ 150 enable-active-high; 151 }; 152 153 dp0: dp0-connector { 154 compatible = "dp-connector"; 155 label = "DP0"; 156 type = "full-size"; 157 dp-pwr-supply = <&dp0_pwr_3v3>; 158 159 port { 160 dp0_connector_in: endpoint { 161 remote-endpoint = <&dp0_out>; 162 }; 163 }; 164 }; 165 166 connector-hdmi { 167 compatible = "hdmi-connector"; 168 label = "hdmi"; 169 type = "a"; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&hdmi_hpd_pins_default>; 172 ddc-i2c-bus = <&mcu_i2c1>; 173 /* HDMI_HPD */ 174 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; 175 176 port { 177 hdmi_connector_in: endpoint { 178 remote-endpoint = <&tfp410_out>; 179 }; 180 }; 181 }; 182 183 bridge-dvi { 184 compatible = "ti,tfp410"; 185 /* HDMI_PDn */ 186 powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>; 187 ti,deskew = <0>; 188 189 ports { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 193 port@0 { 194 reg = <0>; 195 196 tfp410_in: endpoint { 197 remote-endpoint = <&dpi_out0>; 198 pclk-sample = <1>; 199 }; 200 }; 201 202 port@1 { 203 reg = <1>; 204 205 tfp410_out: endpoint { 206 remote-endpoint = <&hdmi_connector_in>; 207 }; 208 }; 209 }; 210 }; 211 212 csi_mux: mux-controller { 213 compatible = "gpio-mux"; 214 #mux-state-cells = <1>; 215 mux-gpios = <&exp3 1 GPIO_ACTIVE_HIGH>; 216 idle-state = <0>; 217 }; 218}; 219 220&main_pmx0 { 221 main_uart8_pins_default: main-uart8-default-pins { 222 pinctrl-single,pins = < 223 J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ 224 J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ 225 >; 226 bootph-all; 227 }; 228 229 main_i2c0_pins_default: main-i2c0-default-pins { 230 pinctrl-single,pins = < 231 J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */ 232 J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ 233 >; 234 }; 235 236 main_i2c1_pins_default: main-i2c1-default-pins { 237 pinctrl-single,pins = < 238 J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */ 239 J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */ 240 >; 241 }; 242 243 main_mmc1_pins_default: main-mmc1-default-pins { 244 pinctrl-single,pins = < 245 J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ 246 J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ 247 J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ 248 J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ 249 J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 250 J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ 251 J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ 252 J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ 253 >; 254 bootph-all; 255 }; 256 257 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 258 pinctrl-single,pins = < 259 J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */ 260 >; 261 }; 262 263 main_usbss0_pins_default: main-usbss0-default-pins { 264 pinctrl-single,pins = < 265 J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ 266 >; 267 }; 268 269 main_mcan6_pins_default: main-mcan6-default-pins { 270 pinctrl-single,pins = < 271 J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */ 272 J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */ 273 >; 274 }; 275 276 main_mcan7_pins_default: main-mcan7-default-pins { 277 pinctrl-single,pins = < 278 J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */ 279 J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ 280 >; 281 }; 282 283 main_i2c4_pins_default: main-i2c4-default-pins { 284 pinctrl-single,pins = < 285 J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ 286 J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ 287 >; 288 }; 289 290 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { 291 pinctrl-single,pins = < 292 J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */ 293 J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */ 294 J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */ 295 J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */ 296 J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ 297 J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */ 298 J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */ 299 J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */ 300 J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */ 301 J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */ 302 J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */ 303 J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */ 304 J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */ 305 J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ 306 >; 307 }; 308 309 dss_vout0_pins_default: dss-vout0-default-pins { 310 pinctrl-single,pins = < 311 J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */ 312 J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */ 313 J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */ 314 J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */ 315 J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */ 316 J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */ 317 J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */ 318 J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */ 319 J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */ 320 J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */ 321 J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */ 322 J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */ 323 J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */ 324 J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */ 325 J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */ 326 J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */ 327 J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */ 328 J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */ 329 J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */ 330 J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */ 331 J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */ 332 J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */ 333 J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */ 334 J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */ 335 J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */ 336 J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */ 337 J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */ 338 J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */ 339 >; 340 }; 341 342 hdmi_hpd_pins_default: hdmi-hpd-default-pins { 343 pinctrl-single,pins = < 344 J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */ 345 >; 346 }; 347}; 348 349&wkup_pmx2 { 350 wkup_uart0_pins_default: wkup-uart0-default-pins { 351 pinctrl-single,pins = < 352 J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ 353 J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ 354 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ 355 J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ 356 >; 357 bootph-all; 358 }; 359 360 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 361 pinctrl-single,pins = < 362 J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ 363 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ 364 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ 365 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ 366 J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ 367 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ 368 J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ 369 J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ 370 J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ 371 J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ 372 J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ 373 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ 374 >; 375 bootph-all; 376 }; 377 378 mcu_mdio_pins_default: mcu-mdio-default-pins { 379 pinctrl-single,pins = < 380 J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ 381 J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ 382 >; 383 bootph-all; 384 }; 385 386 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 387 pinctrl-single,pins = < 388 J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ 389 J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ 390 >; 391 }; 392 393 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 394 pinctrl-single,pins = < 395 J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ 396 J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ 397 >; 398 }; 399 400 mcu_i2c0_pins_default: mcu-i2c0-default-pins { 401 pinctrl-single,pins = < 402 J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */ 403 J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */ 404 >; 405 }; 406 407 mcu_i2c1_pins_default: mcu-i2c1-default-pins { 408 pinctrl-single,pins = < 409 J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ 410 J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ 411 >; 412 }; 413 414 mcu_uart0_pins_default: mcu-uart0-default-pins { 415 pinctrl-single,pins = < 416 J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ 417 J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ 418 >; 419 bootph-all; 420 }; 421 422 mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { 423 pinctrl-single,pins = < 424 J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ 425 J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ 426 J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */ 427 J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */ 428 J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/ 429 J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */ 430 J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */ 431 J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */ 432 J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */ 433 >; 434 }; 435}; 436 437&wkup_pmx3 { 438 mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 { 439 pinctrl-single,pins = < 440 J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */ 441 >; 442 }; 443}; 444 445&cpsw_mac_syscon { 446 bootph-all; 447}; 448 449&phy_gmii_sel { 450 bootph-all; 451}; 452 453&main_gpio0 { 454 status = "okay"; 455 pinctrl-names = "default"; 456 pinctrl-0 = <&rpi_header_gpio0_pins_default>; 457}; 458 459&wkup_gpio0 { 460 status = "okay"; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>; 463}; 464 465&wkup_uart0 { 466 status = "reserved"; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&wkup_uart0_pins_default>; 469 bootph-all; 470}; 471 472&wkup_i2c0 { 473 bootph-all; 474 clock-frequency = <400000>; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&wkup_i2c0_pins_default>; 477 status = "okay"; 478 479 lp8733: pmic@60 { 480 compatible = "ti,lp8733"; 481 reg = <0x60>; 482 buck0-in-supply = <&vsys_3v3>; 483 buck1-in-supply = <&vsys_3v3>; 484 ldo0-in-supply = <&vsys_3v3>; 485 ldo1-in-supply = <&vsys_3v3>; 486 487 lp8733_regulators: regulators { 488 lp8733_buck0_reg: buck0 { 489 /* FB_B0 -> LP8733-BUCK1 - VDD_MCU_0V85 */ 490 regulator-name = "lp8733-buck0"; 491 regulator-min-microvolt = <850000>; 492 regulator-max-microvolt = <850000>; 493 regulator-always-on; 494 regulator-boot-on; 495 }; 496 497 lp8733_buck1_reg: buck1 { 498 /* FB_B1 -> LP8733-BUCK2 - VDD_DDR_1V1 */ 499 regulator-name = "lp8733-buck1"; 500 regulator-min-microvolt = <1100000>; 501 regulator-max-microvolt = <1100000>; 502 regulator-always-on; 503 regulator-boot-on; 504 }; 505 506 lp8733_ldo0_reg: ldo0 { 507 /* LDO0 -> LP8733-LDO1 - VDA_DLL_0V8 */ 508 regulator-name = "lp8733-ldo0"; 509 regulator-min-microvolt = <800000>; 510 regulator-max-microvolt = <800000>; 511 regulator-boot-on; 512 regulator-always-on; 513 }; 514 515 lp8733_ldo1_reg: ldo1 { 516 /* LDO1 -> LP8733-LDO2 - VDA_LN_1V8 */ 517 regulator-name = "lp8733-ldo1"; 518 regulator-min-microvolt = <1800000>; 519 regulator-max-microvolt = <1800000>; 520 regulator-always-on; 521 regulator-boot-on; 522 }; 523 }; 524 }; 525 526 tps62873a: regulator@40 { 527 compatible = "ti,tps62873"; 528 reg = <0x40>; 529 bootph-pre-ram; 530 regulator-name = "VDD_CPU_AVS"; 531 regulator-min-microvolt = <600000>; 532 regulator-max-microvolt = <900000>; 533 regulator-boot-on; 534 regulator-always-on; 535 }; 536 537 tps62873b: regulator@43 { 538 compatible = "ti,tps62873"; 539 reg = <0x43>; 540 regulator-name = "VDD_CORE_0V8"; 541 regulator-min-microvolt = <800000>; 542 regulator-max-microvolt = <800000>; 543 regulator-boot-on; 544 regulator-always-on; 545 }; 546}; 547 548&mcu_uart0 { 549 status = "okay"; 550 pinctrl-names = "default"; 551 pinctrl-0 = <&mcu_uart0_pins_default>; 552 bootph-all; 553}; 554 555&main_uart8 { 556 status = "okay"; 557 pinctrl-names = "default"; 558 pinctrl-0 = <&main_uart8_pins_default>; 559 /* Shared with TFA on this platform */ 560 power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; 561 bootph-all; 562}; 563 564&main_i2c0 { 565 pinctrl-names = "default"; 566 pinctrl-0 = <&main_i2c0_pins_default>; 567 clock-frequency = <400000>; 568 569 exp1: gpio@21 { 570 compatible = "ti,tca6416"; 571 reg = <0x21>; 572 gpio-controller; 573 #gpio-cells = <2>; 574 gpio-line-names = " ", " ", " ", " ", " ", 575 "BOARDID_EEPROM_WP", "CAN_STB", " ", 576 "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz", 577 "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " "; 578 }; 579}; 580 581&main_i2c1 { 582 pinctrl-names = "default"; 583 pinctrl-0 = <&main_i2c1_pins_default>; 584 status = "okay"; 585 586 exp3: gpio@20 { 587 compatible = "ti,tca6408"; 588 reg = <0x20>; 589 gpio-controller; 590 #gpio-cells = <2>; 591 gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", 592 "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1", 593 "CSI1_B_GPIO1"; 594 }; 595 596 i2c-mux@70 { 597 compatible = "nxp,pca9543"; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 reg = <0x70>; 601 602 cam0_i2c: i2c@0 { 603 #address-cells = <1>; 604 #size-cells = <0>; 605 reg = <0>; 606 }; 607 608 cam1_i2c: i2c@1 { 609 #address-cells = <1>; 610 #size-cells = <0>; 611 reg = <1>; 612 }; 613 614 }; 615}; 616 617&main_i2c4 { 618 status = "okay"; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&main_i2c4_pins_default>; 621 clock-frequency = <400000>; 622}; 623 624&mcu_i2c0 { 625 status = "okay"; 626 pinctrl-names = "default"; 627 pinctrl-0 = <&mcu_i2c0_pins_default>; 628 clock-frequency = <400000>; 629}; 630 631&mcu_i2c1 { 632 status = "okay"; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&mcu_i2c1_pins_default>; 635 /* i2c1 is used for DVI DDC, so we need to use 100kHz */ 636 clock-frequency = <100000>; 637 638 exp2: gpio@20 { 639 compatible = "ti,tca6408"; 640 reg = <0x20>; 641 gpio-controller; 642 #gpio-cells = <2>; 643 gpio-line-names = "HDMI_PDn","HDMI_LS_OE", 644 "DP0_3V3_EN","eDP_ENABLE"; 645 }; 646 647 bridge_dsi_edp: bridge-dsi-edp@2c { 648 compatible = "ti,sn65dsi86"; 649 reg = <0x2c>; 650 clock-names = "refclk"; 651 clocks = <&edp0_refclk>; 652 enable-gpios = <&exp2 3 GPIO_ACTIVE_HIGH>; 653 vpll-supply = <&vsys_io_1v8>; 654 vccio-supply = <&vsys_io_1v8>; 655 vcca-supply = <&vsys_io_1v2>; 656 vcc-supply = <&vsys_io_1v2>; 657 658 dsi_edp_bridge_ports: ports { 659 #address-cells = <1>; 660 #size-cells = <0>; 661 662 port@0 { 663 reg = <0>; 664 665 dp0_in: endpoint { 666 remote-endpoint = <&dsi0_out>; 667 }; 668 }; 669 670 port@1 { 671 reg = <1>; 672 673 dp0_out: endpoint { 674 remote-endpoint = <&dp0_connector_in>; 675 }; 676 }; 677 }; 678 }; 679}; 680 681&main_sdhci1 { 682 /* SD card */ 683 status = "okay"; 684 pinctrl-0 = <&main_mmc1_pins_default>; 685 pinctrl-names = "default"; 686 disable-wp; 687 vmmc-supply = <&vdd_mmc1>; 688 vqmmc-supply = <&vdd_sd_dv>; 689 bootph-all; 690}; 691 692&mcu_cpsw { 693 pinctrl-names = "default"; 694 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 695 status = "okay"; 696}; 697 698&davinci_mdio { 699 phy0: ethernet-phy@0 { 700 reg = <0>; 701 bootph-all; 702 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 703 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 704 ti,min-output-impedance; 705 }; 706}; 707 708&cpsw_port1 { 709 phy-mode = "rgmii-id"; 710 phy-handle = <&phy0>; 711 bootph-all; 712}; 713 714&mcu_mcan0 { 715 status = "okay"; 716 pinctrl-names = "default"; 717 pinctrl-0 = <&mcu_mcan0_pins_default>; 718 phys = <&transceiver1>; 719}; 720 721&mcu_mcan1 { 722 status = "okay"; 723 pinctrl-names = "default"; 724 pinctrl-0 = <&mcu_mcan1_pins_default>; 725 phys = <&transceiver2>; 726}; 727 728&main_mcan6 { 729 status = "okay"; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&main_mcan6_pins_default>; 732 phys = <&transceiver3>; 733}; 734 735&main_mcan7 { 736 status = "okay"; 737 pinctrl-names = "default"; 738 pinctrl-0 = <&main_mcan7_pins_default>; 739 phys = <&transceiver4>; 740}; 741 742&dss { 743 status = "okay"; 744 pinctrl-names = "default"; 745 pinctrl-0 = <&dss_vout0_pins_default>; 746 /* 747 * These clock assignments are chosen to enable the following outputs: 748 * 749 * VP0 - DisplayPort SST 750 * VP1 - DPI0 751 * VP2 - DSI 752 * VP3 - DPI1 753 */ 754 assigned-clocks = <&k3_clks 158 2>, 755 <&k3_clks 158 5>, 756 <&k3_clks 158 14>, 757 <&k3_clks 158 18>; 758 assigned-clock-parents = <&k3_clks 158 3>, 759 <&k3_clks 158 7>, 760 <&k3_clks 158 16>, 761 <&k3_clks 158 22>; 762}; 763 764&dss_ports { 765 #address-cells = <1>; 766 #size-cells = <0>; 767 768 /* HDMI */ 769 port@1 { 770 reg = <1>; 771 772 dpi_out0: endpoint { 773 remote-endpoint = <&tfp410_in>; 774 }; 775 }; 776 777 /* DSI */ 778 port@2 { 779 reg = <2>; 780 781 dpi0_out: endpoint { 782 remote-endpoint = <&dsi0_in>; 783 }; 784 }; 785}; 786 787&serdes_ln_ctrl { 788 idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_PCIE1_LANE1>, 789 <J721S2_SERDES0_LANE2_USB_SWAP>, <J721S2_SERDES0_LANE3_USB>; 790}; 791 792&serdes_refclk { 793 clock-frequency = <100000000>; 794}; 795 796&serdes0 { 797 status = "okay"; 798 799 serdes0_pcie_link: phy@0 { 800 reg = <0>; 801 cdns,num-lanes = <2>; 802 #phy-cells = <0>; 803 cdns,phy-type = <PHY_TYPE_PCIE>; 804 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; 805 }; 806 807 serdes0_usb_link: phy@2 { 808 status = "okay"; 809 reg = <2>; 810 cdns,num-lanes = <1>; 811 #phy-cells = <0>; 812 cdns,phy-type = <PHY_TYPE_USB3>; 813 resets = <&serdes_wiz0 3>; 814 }; 815}; 816 817&pcie1_rc { 818 status = "okay"; 819 reset-gpios = <&exp1 10 GPIO_ACTIVE_HIGH>; 820 phys = <&serdes0_pcie_link>; 821 phy-names = "pcie-phy"; 822 num-lanes = <2>; 823}; 824 825&usb_serdes_mux { 826 idle-states = <0>; /* USB0 to SERDES lane 2 */ 827}; 828 829&usbss0 { 830 status = "okay"; 831 pinctrl-0 = <&main_usbss0_pins_default>; 832 pinctrl-names = "default"; 833 ti,vbus-divider; 834}; 835 836&usb0 { 837 dr_mode = "host"; 838 maximum-speed = "super-speed"; 839 phys = <&serdes0_usb_link>; 840 phy-names = "cdns3,usb3-phy"; 841}; 842 843&dphy_tx0 { 844 status = "okay"; 845}; 846 847&dsi0 { 848 status = "okay"; 849}; 850 851&dsi0_ports { 852 853 port@0 { 854 reg = <0>; 855 856 dsi0_out: endpoint { 857 remote-endpoint = <&dp0_in>; 858 }; 859 }; 860 861 port@1 { 862 reg = <1>; 863 864 dsi0_in: endpoint { 865 remote-endpoint = <&dpi0_out>; 866 }; 867 }; 868}; 869