1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RZ/G3E TSU Temperature Sensor Unit
4 *
5 * Copyright (C) 2025 Renesas Electronics Corporation
6 */
7 #include <linux/arm-smccc.h>
8 #include <linux/clk.h>
9 #include <linux/cleanup.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/kernel.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23 #include <linux/thermal.h>
24 #include <linux/units.h>
25
26 #include "../thermal_hwmon.h"
27
28 /* TSU Register offsets and bits */
29 #define TSU_SSUSR 0x00
30 #define TSU_SSUSR_EN_TS BIT(0)
31 #define TSU_SSUSR_ADC_PD_TS BIT(1)
32 #define TSU_SSUSR_SOC_TS_EN BIT(2)
33
34 #define TSU_STRGR 0x04
35 #define TSU_STRGR_ADST BIT(0)
36
37 #define TSU_SOSR1 0x08
38 #define TSU_SOSR1_ADCT_8 0x03
39 #define TSU_SOSR1_ADCS BIT(4)
40 #define TSU_SOSR1_OUTSEL BIT(9)
41
42 #define TSU_SCRR 0x10
43 #define TSU_SCRR_OUT12BIT_TS GENMASK(11, 0)
44
45 #define TSU_SSR 0x14
46 #define TSU_SSR_CONV BIT(0)
47
48 #define TSU_CMSR 0x18
49 #define TSU_CMSR_CMPEN BIT(0)
50
51 #define TSU_LLSR 0x1C
52 #define TSU_ULSR 0x20
53
54 #define TSU_SISR 0x30
55 #define TSU_SISR_ADF BIT(0)
56 #define TSU_SISR_CMPF BIT(1)
57
58 #define TSU_SIER 0x34
59 #define TSU_SIER_CMPIE BIT(1)
60
61 #define TSU_SICR 0x38
62 #define TSU_SICR_ADCLR BIT(0)
63 #define TSU_SICR_CMPCLR BIT(1)
64
65 /* Temperature calculation constants from datasheet */
66 #define TSU_CODE_MAX 0xFFF
67
68 /* Timing specifications from datasheet */
69 #define TSU_POWERUP_TIME_US 120 /* 120T at 1MHz sensor clock per datasheet */
70 #define TSU_CONV_TIME_US 50 /* Per sample conversion time */
71 #define TSU_POLL_DELAY_US 10 /* Polling interval */
72 #define TSU_MIN_CLOCK_RATE 24000000 /* TSU_PCLK minimum 24MHz */
73
74 #define RZ_SIP_SVC_GET_SYSTSU 0x82000022
75 #define OTP_TSU_REG_ADR_TEMPHI 0x01DC
76 #define OTP_TSU_REG_ADR_TEMPLO 0x01DD
77
78 struct rzg3e_thermal_priv;
79
80 struct rzg3e_thermal_info {
81 int (*get_trim)(struct rzg3e_thermal_priv *priv);
82 int temp_d_mc;
83 int temp_e_mc;
84 };
85
86 /**
87 * struct rzg3e_thermal_priv - RZ/G3E TSU private data
88 * @base: TSU register base
89 * @dev: device pointer
90 * @syscon: regmap for calibration values
91 * @zone: thermal zone device
92 * @rstc: reset control
93 * @info: chip type specific information
94 * @trmval0: calibration value 0 (b)
95 * @trmval1: calibration value 1 (c)
96 * @lock: protects hardware access during conversions
97 */
98 struct rzg3e_thermal_priv {
99 void __iomem *base;
100 struct device *dev;
101 struct thermal_zone_device *zone;
102 struct reset_control *rstc;
103 const struct rzg3e_thermal_info *info;
104 u16 trmval0;
105 u16 trmval1;
106 struct mutex lock;
107 };
108
rzg3e_thermal_power_on(struct rzg3e_thermal_priv * priv)109 static int rzg3e_thermal_power_on(struct rzg3e_thermal_priv *priv)
110 {
111 u32 val;
112 int ret;
113
114 /* Clear any pending interrupts */
115 writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR);
116
117 /* Disable all interrupts during setup */
118 writel(0, priv->base + TSU_SIER);
119
120 /*
121 * Power-on sequence per datasheet 7.11.9.1:
122 * SOC_TS_EN must be set at same time or before EN_TS and ADC_PD_TS
123 */
124 val = TSU_SSUSR_SOC_TS_EN | TSU_SSUSR_EN_TS;
125 writel(val, priv->base + TSU_SSUSR);
126
127 /* Wait for sensor stabilization per datasheet 7.11.7.1 */
128 usleep_range(TSU_POWERUP_TIME_US, TSU_POWERUP_TIME_US + 10);
129
130 /* Configure for average mode with 8 samples */
131 val = TSU_SOSR1_OUTSEL | TSU_SOSR1_ADCT_8;
132 writel(val, priv->base + TSU_SOSR1);
133
134 /* Ensure we're in single scan mode (default) */
135 val = readl(priv->base + TSU_SOSR1);
136 if (val & TSU_SOSR1_ADCS) {
137 dev_err(priv->dev, "Invalid scan mode setting\n");
138 return -EINVAL;
139 }
140
141 /* Wait for any ongoing conversion to complete */
142 ret = readl_poll_timeout(priv->base + TSU_SSR, val,
143 !(val & TSU_SSR_CONV),
144 TSU_POLL_DELAY_US,
145 USEC_PER_MSEC);
146 if (ret) {
147 dev_err(priv->dev, "Timeout waiting for conversion\n");
148 return ret;
149 }
150
151 return 0;
152 }
153
rzg3e_thermal_power_off(struct rzg3e_thermal_priv * priv)154 static void rzg3e_thermal_power_off(struct rzg3e_thermal_priv *priv)
155 {
156 /* Disable all interrupts */
157 writel(0, priv->base + TSU_SIER);
158
159 /* Clear pending interrupts */
160 writel(TSU_SICR_ADCLR | TSU_SICR_CMPCLR, priv->base + TSU_SICR);
161
162 /* Power down sequence per datasheet */
163 writel(TSU_SSUSR_ADC_PD_TS, priv->base + TSU_SSUSR);
164 }
165
166 /*
167 * Convert 12-bit sensor code to temperature in millicelsius
168 * Formula from datasheet 7.11.7.8:
169 * T(°C) = ((e - d) / (c - b)) * (a - b) + d
170 * where: a = sensor code, b = trmval0, c = trmval1, d = -41, e = 126
171 */
rzg3e_thermal_code_to_temp(struct rzg3e_thermal_priv * priv,u16 code)172 static int rzg3e_thermal_code_to_temp(struct rzg3e_thermal_priv *priv, u16 code)
173 {
174 const struct rzg3e_thermal_info *info = priv->info;
175 s64 numerator, denominator;
176 int temp_mc;
177
178 numerator = (info->temp_e_mc - info->temp_d_mc) *
179 (s64)(code - priv->trmval0);
180 denominator = priv->trmval1 - priv->trmval0;
181
182 temp_mc = div64_s64(numerator, denominator) + info->temp_d_mc;
183
184 return clamp(temp_mc, info->temp_d_mc, info->temp_e_mc);
185 }
186
187 /*
188 * Convert temperature in millicelsius to 12-bit sensor code
189 * Formula from datasheet 7.11.7.9 (inverse of above)
190 */
rzg3e_thermal_temp_to_code(struct rzg3e_thermal_priv * priv,int temp_mc)191 static u16 rzg3e_thermal_temp_to_code(struct rzg3e_thermal_priv *priv, int temp_mc)
192 {
193 const struct rzg3e_thermal_info *info = priv->info;
194 s64 numerator, denominator;
195 s64 code;
196
197 numerator = (temp_mc - info->temp_d_mc) * (priv->trmval1 - priv->trmval0);
198 denominator = info->temp_e_mc - info->temp_d_mc;
199
200 code = div64_s64(numerator, denominator) + priv->trmval0;
201
202 return clamp_val(code, 0, TSU_CODE_MAX);
203 }
204
rzg3e_thermal_get_temp(struct thermal_zone_device * tz,int * temp)205 static int rzg3e_thermal_get_temp(struct thermal_zone_device *tz, int *temp)
206 {
207 struct rzg3e_thermal_priv *priv = thermal_zone_device_priv(tz);
208 u32 status, code;
209 int ret, timeout;
210
211 ret = pm_runtime_resume_and_get(priv->dev);
212 if (ret < 0)
213 return ret;
214
215 guard(mutex)(&priv->lock);
216
217 /* Clear any previous conversion status */
218 writel(TSU_SICR_ADCLR, priv->base + TSU_SICR);
219
220 /* Start single conversion */
221 writel(TSU_STRGR_ADST, priv->base + TSU_STRGR);
222
223 /* Wait for conversion completion - 8 samples at ~50us each */
224 timeout = TSU_CONV_TIME_US * 8 * 2; /* Double for margin */
225 ret = readl_poll_timeout(priv->base + TSU_SISR, status,
226 status & TSU_SISR_ADF,
227 TSU_POLL_DELAY_US, timeout);
228 if (ret) {
229 dev_err(priv->dev, "Conversion timeout (status=0x%08x)\n", status);
230 goto out;
231 }
232
233 /* Read the averaged result and clear the complete flag */
234 code = readl(priv->base + TSU_SCRR) & TSU_SCRR_OUT12BIT_TS;
235 writel(TSU_SICR_ADCLR, priv->base + TSU_SICR);
236
237 /* Convert to temperature */
238 *temp = rzg3e_thermal_code_to_temp(priv, code);
239
240 dev_dbg(priv->dev, "temp=%d mC (%d.%03d°C), code=0x%03x\n",
241 *temp, *temp / 1000, abs(*temp) % 1000, code);
242
243 out:
244 pm_runtime_mark_last_busy(priv->dev);
245 pm_runtime_put_autosuspend(priv->dev);
246 return ret;
247 }
248
rzg3e_thermal_set_trips(struct thermal_zone_device * tz,int low,int high)249 static int rzg3e_thermal_set_trips(struct thermal_zone_device *tz,
250 int low, int high)
251 {
252 struct rzg3e_thermal_priv *priv = thermal_zone_device_priv(tz);
253 u16 low_code, high_code;
254 u32 val;
255 int ret;
256
257 /* Hardware requires low < high */
258 if (low >= high)
259 return -EINVAL;
260
261 ret = pm_runtime_resume_and_get(priv->dev);
262 if (ret < 0)
263 return ret;
264
265 guard(mutex)(&priv->lock);
266
267 /* Convert temperatures to codes */
268 low_code = rzg3e_thermal_temp_to_code(priv, low);
269 high_code = rzg3e_thermal_temp_to_code(priv, high);
270
271 dev_dbg(priv->dev, "set_trips: low=%d high=%d (codes: 0x%03x/0x%03x)\n",
272 low, high, low_code, high_code);
273
274 /* Disable comparison during reconfiguration */
275 writel(0, priv->base + TSU_SIER);
276 writel(0, priv->base + TSU_CMSR);
277
278 /* Clear any pending comparison interrupts */
279 writel(TSU_SICR_CMPCLR, priv->base + TSU_SICR);
280
281 /* Set trip points */
282 writel(low_code, priv->base + TSU_LLSR);
283 writel(high_code, priv->base + TSU_ULSR);
284
285 /*
286 * Ensure OUTSEL is set for comparison per datasheet 7.11.7.4
287 * Comparison uses averaged data
288 */
289 val = readl(priv->base + TSU_SOSR1);
290 val |= TSU_SOSR1_OUTSEL;
291 writel(val, priv->base + TSU_SOSR1);
292
293 /* Enable comparison with "out of range" mode (CMPCOND=0) */
294 writel(TSU_CMSR_CMPEN, priv->base + TSU_CMSR);
295
296 /* Unmask compare IRQ and start a conversion to evaluate window */
297 writel(TSU_SIER_CMPIE, priv->base + TSU_SIER);
298 writel(TSU_STRGR_ADST, priv->base + TSU_STRGR);
299
300 pm_runtime_mark_last_busy(priv->dev);
301 pm_runtime_put_autosuspend(priv->dev);
302
303 return 0;
304 }
305
rzg3e_thermal_irq_thread(int irq,void * data)306 static irqreturn_t rzg3e_thermal_irq_thread(int irq, void *data)
307 {
308 struct rzg3e_thermal_priv *priv = data;
309
310 dev_dbg(priv->dev, "Temperature threshold crossed\n");
311
312 /* Notify thermal framework to re-evaluate trip points */
313 thermal_zone_device_update(priv->zone, THERMAL_TRIP_VIOLATED);
314
315 return IRQ_HANDLED;
316 }
317
rzg3e_thermal_irq(int irq,void * data)318 static irqreturn_t rzg3e_thermal_irq(int irq, void *data)
319 {
320 struct rzg3e_thermal_priv *priv = data;
321 u32 status;
322
323 status = readl(priv->base + TSU_SISR);
324
325 /* Check if comparison interrupt occurred */
326 if (status & TSU_SISR_CMPF) {
327 /* Clear irq flag and disable interrupt until reconfigured */
328 writel(TSU_SICR_CMPCLR, priv->base + TSU_SICR);
329 writel(0, priv->base + TSU_SIER);
330
331 return IRQ_WAKE_THREAD;
332 }
333
334 return IRQ_NONE;
335 }
336
337 static const struct thermal_zone_device_ops rzg3e_tz_ops = {
338 .get_temp = rzg3e_thermal_get_temp,
339 .set_trips = rzg3e_thermal_set_trips,
340 };
341
rzg3e_thermal_get_syscon_trim(struct rzg3e_thermal_priv * priv)342 static int rzg3e_thermal_get_syscon_trim(struct rzg3e_thermal_priv *priv)
343 {
344 struct device_node *np = priv->dev->of_node;
345 struct regmap *syscon;
346 u32 offset;
347 int ret;
348 u32 val;
349
350 syscon = syscon_regmap_lookup_by_phandle_args(np, "renesas,tsu-trim", 1, &offset);
351 if (IS_ERR(syscon))
352 return dev_err_probe(priv->dev, PTR_ERR(syscon),
353 "Failed to parse renesas,tsu-trim\n");
354
355 /* Read calibration values from syscon */
356 ret = regmap_read(syscon, offset, &val);
357 if (ret)
358 return ret;
359 priv->trmval0 = val & TSU_CODE_MAX;
360
361 ret = regmap_read(syscon, offset + 4, &val);
362 if (ret)
363 return ret;
364 priv->trmval1 = val & TSU_CODE_MAX;
365
366 return 0;
367 }
368
rzg3e_thermal_get_smc_trim(struct rzg3e_thermal_priv * priv)369 static int rzg3e_thermal_get_smc_trim(struct rzg3e_thermal_priv *priv)
370 {
371 struct arm_smccc_res local_res;
372
373 arm_smccc_smc(RZ_SIP_SVC_GET_SYSTSU, OTP_TSU_REG_ADR_TEMPLO,
374 0, 0, 0, 0, 0, 0, &local_res);
375 priv->trmval0 = local_res.a0 & TSU_CODE_MAX;
376
377 arm_smccc_smc(RZ_SIP_SVC_GET_SYSTSU, OTP_TSU_REG_ADR_TEMPHI,
378 0, 0, 0, 0, 0, 0, &local_res);
379 priv->trmval1 = local_res.a0 & TSU_CODE_MAX;
380
381 return 0;
382 }
383
rzg3e_thermal_probe(struct platform_device * pdev)384 static int rzg3e_thermal_probe(struct platform_device *pdev)
385 {
386 struct device *dev = &pdev->dev;
387 struct rzg3e_thermal_priv *priv;
388 struct clk *clk;
389 int irq, ret;
390
391 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
392 if (!priv)
393 return -ENOMEM;
394
395 priv->dev = dev;
396 ret = devm_mutex_init(dev, &priv->lock);
397 if (ret)
398 return ret;
399 platform_set_drvdata(pdev, priv);
400
401 priv->info = device_get_match_data(dev);
402
403 priv->base = devm_platform_ioremap_resource(pdev, 0);
404 if (IS_ERR(priv->base))
405 return PTR_ERR(priv->base);
406
407 ret = priv->info->get_trim(priv);
408 if (ret)
409 return ret;
410
411 if (!priv->trmval0 || !priv->trmval1 ||
412 priv->trmval0 == priv->trmval1 ||
413 priv->trmval0 == TSU_CODE_MAX || priv->trmval1 == TSU_CODE_MAX)
414 return dev_err_probe(priv->dev, -EINVAL,
415 "Invalid calibration: b=0x%03x, c=0x%03x\n",
416 priv->trmval0, priv->trmval1);
417
418 dev_dbg(priv->dev, "Calibration: b=0x%03x (%u), c=0x%03x (%u)\n",
419 priv->trmval0, priv->trmval0, priv->trmval1, priv->trmval1);
420
421 /* Get clock to verify frequency - clock is managed by power domain */
422 clk = devm_clk_get(dev, NULL);
423 if (IS_ERR(clk))
424 return dev_err_probe(dev, PTR_ERR(clk),
425 "Failed to get clock\n");
426
427 if (clk_get_rate(clk) < TSU_MIN_CLOCK_RATE)
428 return dev_err_probe(dev, -EINVAL,
429 "Clock rate %lu Hz too low (min %u Hz)\n",
430 clk_get_rate(clk), TSU_MIN_CLOCK_RATE);
431
432 priv->rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
433 if (IS_ERR(priv->rstc))
434 return dev_err_probe(dev, PTR_ERR(priv->rstc),
435 "Failed to get/deassert reset control\n");
436
437 /* Get comparison interrupt */
438 irq = platform_get_irq_byname(pdev, "adcmpi");
439 if (irq < 0)
440 return irq;
441
442 /* Enable runtime PM */
443 pm_runtime_set_autosuspend_delay(dev, 1000);
444 pm_runtime_use_autosuspend(dev);
445 devm_pm_runtime_enable(dev);
446
447 /* Initial hardware setup */
448 ret = pm_runtime_resume_and_get(dev);
449 if (ret < 0)
450 return dev_err_probe(dev, ret, "Runtime resume failed\n");
451
452 /* Register thermal zone - this will trigger DT parsing */
453 priv->zone = devm_thermal_of_zone_register(dev, 0, priv, &rzg3e_tz_ops);
454 if (IS_ERR(priv->zone)) {
455 ret = PTR_ERR(priv->zone);
456 dev_err(dev, "Failed to register thermal zone: %d\n", ret);
457 goto err_pm_put;
458 }
459
460 /* Request threaded IRQ for comparison interrupt */
461 ret = devm_request_threaded_irq(dev, irq, rzg3e_thermal_irq,
462 rzg3e_thermal_irq_thread,
463 IRQF_ONESHOT, "rzg3e_thermal", priv);
464 if (ret)
465 goto err_pm_put;
466
467 /* Add hwmon sysfs interface */
468 ret = devm_thermal_add_hwmon_sysfs(dev, priv->zone);
469 if (ret)
470 dev_warn(dev, "Failed to add hwmon sysfs attributes\n");
471
472 pm_runtime_mark_last_busy(dev);
473 pm_runtime_put_autosuspend(dev);
474
475 dev_info(dev, "RZ/G3E thermal sensor registered\n");
476
477 return 0;
478
479 err_pm_put:
480 pm_runtime_put_sync(dev);
481 return ret;
482 }
483
rzg3e_thermal_runtime_suspend(struct device * dev)484 static int rzg3e_thermal_runtime_suspend(struct device *dev)
485 {
486 struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
487
488 rzg3e_thermal_power_off(priv);
489 return 0;
490 }
491
rzg3e_thermal_runtime_resume(struct device * dev)492 static int rzg3e_thermal_runtime_resume(struct device *dev)
493 {
494 struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
495
496 return rzg3e_thermal_power_on(priv);
497 }
498
rzg3e_thermal_suspend(struct device * dev)499 static int rzg3e_thermal_suspend(struct device *dev)
500 {
501 struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
502
503 /* If device is active, power it off */
504 if (pm_runtime_active(dev))
505 rzg3e_thermal_power_off(priv);
506
507 /* Assert reset to ensure clean state after resume */
508 reset_control_assert(priv->rstc);
509
510 return 0;
511 }
512
rzg3e_thermal_resume(struct device * dev)513 static int rzg3e_thermal_resume(struct device *dev)
514 {
515 struct rzg3e_thermal_priv *priv = dev_get_drvdata(dev);
516 int ret;
517
518 /* Deassert reset */
519 ret = reset_control_deassert(priv->rstc);
520 if (ret) {
521 dev_err(dev, "Failed to deassert reset: %d\n", ret);
522 return ret;
523 }
524
525 /* If device was active before suspend, power it back on */
526 if (pm_runtime_active(dev))
527 return rzg3e_thermal_power_on(priv);
528
529 return 0;
530 }
531
532 static const struct dev_pm_ops rzg3e_thermal_pm_ops = {
533 RUNTIME_PM_OPS(rzg3e_thermal_runtime_suspend,
534 rzg3e_thermal_runtime_resume, NULL)
535 SYSTEM_SLEEP_PM_OPS(rzg3e_thermal_suspend, rzg3e_thermal_resume)
536 };
537
538 static const struct rzg3e_thermal_info rzg3e_thermal_info = {
539 .get_trim = rzg3e_thermal_get_syscon_trim,
540 .temp_d_mc = -41000,
541 .temp_e_mc = 126000,
542 };
543
544 static const struct rzg3e_thermal_info rzt2h_thermal_info = {
545 .get_trim = rzg3e_thermal_get_smc_trim,
546 .temp_d_mc = -40000,
547 .temp_e_mc = 125000,
548 };
549
550 static const struct of_device_id rzg3e_thermal_dt_ids[] = {
551 { .compatible = "renesas,r9a09g047-tsu", .data = &rzg3e_thermal_info },
552 { .compatible = "renesas,r9a09g077-tsu", .data = &rzt2h_thermal_info },
553 { /* sentinel */ }
554 };
555 MODULE_DEVICE_TABLE(of, rzg3e_thermal_dt_ids);
556
557 static struct platform_driver rzg3e_thermal_driver = {
558 .driver = {
559 .name = "rzg3e_thermal",
560 .of_match_table = rzg3e_thermal_dt_ids,
561 .pm = pm_ptr(&rzg3e_thermal_pm_ops),
562 },
563 .probe = rzg3e_thermal_probe,
564 };
565 module_platform_driver(rzg3e_thermal_driver);
566
567 MODULE_DESCRIPTION("Renesas RZ/G3E TSU Thermal Sensor Driver");
568 MODULE_AUTHOR("John Madieu <john.madieu.xa@bp.renesas.com>");
569 MODULE_LICENSE("GPL");
570