1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Red Hat
4 *
5 * based in parts on udlfb.c:
6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it>
7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
9 */
10
11 #include <linux/bitfield.h>
12
13 #include <drm/drm_atomic.h>
14 #include <drm/drm_atomic_helper.h>
15 #include <drm/drm_crtc_helper.h>
16 #include <drm/drm_damage_helper.h>
17 #include <drm/drm_drv.h>
18 #include <drm/drm_edid.h>
19 #include <drm/drm_fourcc.h>
20 #include <drm/drm_gem_atomic_helper.h>
21 #include <drm/drm_gem_framebuffer_helper.h>
22 #include <drm/drm_gem_shmem_helper.h>
23 #include <drm/drm_modeset_helper_vtables.h>
24 #include <drm/drm_print.h>
25 #include <drm/drm_probe_helper.h>
26 #include <drm/drm_vblank.h>
27
28 #include "udl_drv.h"
29 #include "udl_edid.h"
30 #include "udl_proto.h"
31
32 /*
33 * All DisplayLink bulk operations start with 0xaf (UDL_MSG_BULK), followed by
34 * a specific command code. All operations are written to a command buffer, which
35 * the driver sends to the device.
36 */
udl_set_register(char * buf,u8 reg,u8 val)37 static char *udl_set_register(char *buf, u8 reg, u8 val)
38 {
39 *buf++ = UDL_MSG_BULK;
40 *buf++ = UDL_CMD_WRITEREG;
41 *buf++ = reg;
42 *buf++ = val;
43
44 return buf;
45 }
46
udl_vidreg_lock(char * buf)47 static char *udl_vidreg_lock(char *buf)
48 {
49 return udl_set_register(buf, UDL_REG_VIDREG, UDL_VIDREG_LOCK);
50 }
51
udl_vidreg_unlock(char * buf)52 static char *udl_vidreg_unlock(char *buf)
53 {
54 return udl_set_register(buf, UDL_REG_VIDREG, UDL_VIDREG_UNLOCK);
55 }
56
udl_set_blank_mode(char * buf,u8 mode)57 static char *udl_set_blank_mode(char *buf, u8 mode)
58 {
59 return udl_set_register(buf, UDL_REG_BLANKMODE, mode);
60 }
61
udl_set_color_depth(char * buf,u8 selection)62 static char *udl_set_color_depth(char *buf, u8 selection)
63 {
64 return udl_set_register(buf, UDL_REG_COLORDEPTH, selection);
65 }
66
udl_set_base16bpp(char * buf,u32 base)67 static char *udl_set_base16bpp(char *buf, u32 base)
68 {
69 /* the base pointer is 24 bits wide, 0x20 is hi byte. */
70 u8 reg20 = FIELD_GET(UDL_BASE_ADDR2_MASK, base);
71 u8 reg21 = FIELD_GET(UDL_BASE_ADDR1_MASK, base);
72 u8 reg22 = FIELD_GET(UDL_BASE_ADDR0_MASK, base);
73
74 buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR2, reg20);
75 buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR1, reg21);
76 buf = udl_set_register(buf, UDL_REG_BASE16BPP_ADDR0, reg22);
77
78 return buf;
79 }
80
81 /*
82 * DisplayLink HW has separate 16bpp and 8bpp framebuffers.
83 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
84 */
udl_set_base8bpp(char * buf,u32 base)85 static char *udl_set_base8bpp(char *buf, u32 base)
86 {
87 /* the base pointer is 24 bits wide, 0x26 is hi byte. */
88 u8 reg26 = FIELD_GET(UDL_BASE_ADDR2_MASK, base);
89 u8 reg27 = FIELD_GET(UDL_BASE_ADDR1_MASK, base);
90 u8 reg28 = FIELD_GET(UDL_BASE_ADDR0_MASK, base);
91
92 buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR2, reg26);
93 buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR1, reg27);
94 buf = udl_set_register(buf, UDL_REG_BASE8BPP_ADDR0, reg28);
95
96 return buf;
97 }
98
udl_set_register_16(char * wrptr,u8 reg,u16 value)99 static char *udl_set_register_16(char *wrptr, u8 reg, u16 value)
100 {
101 wrptr = udl_set_register(wrptr, reg, value >> 8);
102 return udl_set_register(wrptr, reg+1, value);
103 }
104
105 /*
106 * This is kind of weird because the controller takes some
107 * register values in a different byte order than other registers.
108 */
udl_set_register_16be(char * wrptr,u8 reg,u16 value)109 static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value)
110 {
111 wrptr = udl_set_register(wrptr, reg, value);
112 return udl_set_register(wrptr, reg+1, value >> 8);
113 }
114
115 /*
116 * LFSR is linear feedback shift register. The reason we have this is
117 * because the display controller needs to minimize the clock depth of
118 * various counters used in the display path. So this code reverses the
119 * provided value into the lfsr16 value by counting backwards to get
120 * the value that needs to be set in the hardware comparator to get the
121 * same actual count. This makes sense once you read above a couple of
122 * times and think about it from a hardware perspective.
123 */
udl_lfsr16(u16 actual_count)124 static u16 udl_lfsr16(u16 actual_count)
125 {
126 u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */
127
128 while (actual_count--) {
129 lv = ((lv << 1) |
130 (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1))
131 & 0xFFFF;
132 }
133
134 return (u16) lv;
135 }
136
137 /*
138 * This does LFSR conversion on the value that is to be written.
139 * See LFSR explanation above for more detail.
140 */
udl_set_register_lfsr16(char * wrptr,u8 reg,u16 value)141 static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value)
142 {
143 return udl_set_register_16(wrptr, reg, udl_lfsr16(value));
144 }
145
146 /*
147 * Takes a DRM display mode and converts it into the DisplayLink
148 * equivalent register commands.
149 */
udl_set_display_mode(char * buf,struct drm_display_mode * mode)150 static char *udl_set_display_mode(char *buf, struct drm_display_mode *mode)
151 {
152 u16 reg01 = mode->crtc_htotal - mode->crtc_hsync_start;
153 u16 reg03 = reg01 + mode->crtc_hdisplay;
154 u16 reg05 = mode->crtc_vtotal - mode->crtc_vsync_start;
155 u16 reg07 = reg05 + mode->crtc_vdisplay;
156 u16 reg09 = mode->crtc_htotal - 1;
157 u16 reg0b = 1; /* libdlo hardcodes hsync start to 1 */
158 u16 reg0d = mode->crtc_hsync_end - mode->crtc_hsync_start + 1;
159 u16 reg0f = mode->hdisplay;
160 u16 reg11 = mode->crtc_vtotal;
161 u16 reg13 = 0; /* libdlo hardcodes vsync start to 0 */
162 u16 reg15 = mode->crtc_vsync_end - mode->crtc_vsync_start;
163 u16 reg17 = mode->crtc_vdisplay;
164 u16 reg1b = mode->clock / 5;
165
166 buf = udl_set_register_lfsr16(buf, UDL_REG_XDISPLAYSTART, reg01);
167 buf = udl_set_register_lfsr16(buf, UDL_REG_XDISPLAYEND, reg03);
168 buf = udl_set_register_lfsr16(buf, UDL_REG_YDISPLAYSTART, reg05);
169 buf = udl_set_register_lfsr16(buf, UDL_REG_YDISPLAYEND, reg07);
170 buf = udl_set_register_lfsr16(buf, UDL_REG_XENDCOUNT, reg09);
171 buf = udl_set_register_lfsr16(buf, UDL_REG_HSYNCSTART, reg0b);
172 buf = udl_set_register_lfsr16(buf, UDL_REG_HSYNCEND, reg0d);
173 buf = udl_set_register_16(buf, UDL_REG_HPIXELS, reg0f);
174 buf = udl_set_register_lfsr16(buf, UDL_REG_YENDCOUNT, reg11);
175 buf = udl_set_register_lfsr16(buf, UDL_REG_VSYNCSTART, reg13);
176 buf = udl_set_register_lfsr16(buf, UDL_REG_VSYNCEND, reg15);
177 buf = udl_set_register_16(buf, UDL_REG_VPIXELS, reg17);
178 buf = udl_set_register_16be(buf, UDL_REG_PIXELCLOCK5KHZ, reg1b);
179
180 return buf;
181 }
182
udl_dummy_render(char * wrptr)183 static char *udl_dummy_render(char *wrptr)
184 {
185 *wrptr++ = UDL_MSG_BULK;
186 *wrptr++ = UDL_CMD_WRITECOPY16;
187 *wrptr++ = 0x00; /* from addr */
188 *wrptr++ = 0x00;
189 *wrptr++ = 0x00;
190 *wrptr++ = 0x01; /* one pixel */
191 *wrptr++ = 0x00; /* to address */
192 *wrptr++ = 0x00;
193 *wrptr++ = 0x00;
194 return wrptr;
195 }
196
udl_log_cpp(unsigned int cpp)197 static long udl_log_cpp(unsigned int cpp)
198 {
199 if (WARN_ON(!is_power_of_2(cpp)))
200 return -EINVAL;
201 return __ffs(cpp);
202 }
203
udl_handle_damage(struct drm_framebuffer * fb,const struct iosys_map * map,const struct drm_rect * clip)204 static int udl_handle_damage(struct drm_framebuffer *fb,
205 const struct iosys_map *map,
206 const struct drm_rect *clip)
207 {
208 struct drm_device *dev = fb->dev;
209 struct udl_device *udl = to_udl(dev);
210 void *vaddr = map->vaddr; /* TODO: Use mapping abstraction properly */
211 int i, ret;
212 char *cmd;
213 struct urb *urb;
214 int log_bpp;
215
216 ret = udl_log_cpp(fb->format->cpp[0]);
217 if (ret < 0)
218 return ret;
219 log_bpp = ret;
220
221 urb = udl_get_urb(udl);
222 if (!urb)
223 return -ENOMEM;
224 cmd = urb->transfer_buffer;
225
226 for (i = clip->y1; i < clip->y2; i++) {
227 const int line_offset = fb->pitches[0] * i;
228 const int byte_offset = line_offset + (clip->x1 << log_bpp);
229 const int dev_byte_offset = (fb->width * i + clip->x1) << log_bpp;
230 const int byte_width = drm_rect_width(clip) << log_bpp;
231 ret = udl_render_hline(udl, log_bpp, &urb, (char *)vaddr,
232 &cmd, byte_offset, dev_byte_offset,
233 byte_width);
234 if (ret)
235 return ret;
236 }
237
238 if (cmd > (char *)urb->transfer_buffer) {
239 /* Send partial buffer remaining before exiting */
240 int len;
241 if (cmd < (char *)urb->transfer_buffer + urb->transfer_buffer_length)
242 *cmd++ = UDL_MSG_BULK;
243 len = cmd - (char *)urb->transfer_buffer;
244 ret = udl_submit_urb(udl, urb, len);
245 } else {
246 udl_urb_completion(urb);
247 }
248
249 return 0;
250 }
251
252 /*
253 * Primary plane
254 */
255
256 static const uint32_t udl_primary_plane_formats[] = {
257 DRM_FORMAT_RGB565,
258 DRM_FORMAT_XRGB8888,
259 };
260
261 static const uint64_t udl_primary_plane_fmtmods[] = {
262 DRM_FORMAT_MOD_LINEAR,
263 DRM_FORMAT_MOD_INVALID
264 };
265
udl_primary_plane_helper_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)266 static int udl_primary_plane_helper_atomic_check(struct drm_plane *plane,
267 struct drm_atomic_state *state)
268 {
269 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane);
270 struct drm_crtc *new_crtc = new_plane_state->crtc;
271 struct drm_crtc_state *new_crtc_state = NULL;
272
273 if (new_crtc)
274 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
275
276 return drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
277 DRM_PLANE_NO_SCALING,
278 DRM_PLANE_NO_SCALING,
279 false, false);
280 }
281
udl_primary_plane_helper_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)282 static void udl_primary_plane_helper_atomic_update(struct drm_plane *plane,
283 struct drm_atomic_state *state)
284 {
285 struct drm_device *dev = plane->dev;
286 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
287 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
288 struct drm_framebuffer *fb = plane_state->fb;
289 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
290 struct drm_atomic_helper_damage_iter iter;
291 struct drm_rect damage;
292 int ret, idx;
293
294 if (!fb)
295 return; /* no framebuffer; plane is disabled */
296
297 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
298 if (ret)
299 return;
300
301 if (!drm_dev_enter(dev, &idx))
302 goto out_drm_gem_fb_end_cpu_access;
303
304 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
305 drm_atomic_for_each_plane_damage(&iter, &damage) {
306 udl_handle_damage(fb, &shadow_plane_state->data[0], &damage);
307 }
308
309 drm_dev_exit(idx);
310
311 out_drm_gem_fb_end_cpu_access:
312 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
313 }
314
315 static const struct drm_plane_helper_funcs udl_primary_plane_helper_funcs = {
316 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
317 .atomic_check = udl_primary_plane_helper_atomic_check,
318 .atomic_update = udl_primary_plane_helper_atomic_update,
319 };
320
321 static const struct drm_plane_funcs udl_primary_plane_funcs = {
322 .update_plane = drm_atomic_helper_update_plane,
323 .disable_plane = drm_atomic_helper_disable_plane,
324 .destroy = drm_plane_cleanup,
325 DRM_GEM_SHADOW_PLANE_FUNCS,
326 };
327
328 /*
329 * CRTC
330 */
331
udl_crtc_helper_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)332 static void udl_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state)
333 {
334 struct drm_device *dev = crtc->dev;
335 struct udl_device *udl = to_udl(dev);
336 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
337 struct drm_display_mode *mode = &crtc_state->mode;
338 struct urb *urb;
339 char *buf;
340 int idx;
341
342 if (!drm_dev_enter(dev, &idx))
343 return;
344
345 urb = udl_get_urb(udl);
346 if (!urb) {
347 drm_err_ratelimited(dev, "get urb failed when enabling crtc\n");
348 goto out;
349 }
350
351 buf = (char *)urb->transfer_buffer;
352 buf = udl_vidreg_lock(buf);
353 buf = udl_set_color_depth(buf, UDL_COLORDEPTH_16BPP);
354 /* set base for 16bpp segment to 0 */
355 buf = udl_set_base16bpp(buf, 0);
356 /* set base for 8bpp segment to end of fb */
357 buf = udl_set_base8bpp(buf, 2 * mode->vdisplay * mode->hdisplay);
358 buf = udl_set_display_mode(buf, mode);
359 buf = udl_set_blank_mode(buf, UDL_BLANKMODE_ON);
360 buf = udl_vidreg_unlock(buf);
361 buf = udl_dummy_render(buf);
362
363 udl_submit_urb(udl, urb, buf - (char *)urb->transfer_buffer);
364
365 out:
366 drm_dev_exit(idx);
367 }
368
udl_crtc_helper_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)369 static void udl_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state)
370 {
371 struct drm_device *dev = crtc->dev;
372 struct udl_device *udl = to_udl(dev);
373 struct urb *urb;
374 char *buf;
375 int idx;
376
377 if (!drm_dev_enter(dev, &idx))
378 return;
379
380 urb = udl_get_urb(udl);
381 if (!urb)
382 goto out;
383
384 buf = (char *)urb->transfer_buffer;
385 buf = udl_vidreg_lock(buf);
386 buf = udl_set_blank_mode(buf, UDL_BLANKMODE_POWERDOWN);
387 buf = udl_vidreg_unlock(buf);
388 buf = udl_dummy_render(buf);
389
390 udl_submit_urb(udl, urb, buf - (char *)urb->transfer_buffer);
391
392 out:
393 drm_dev_exit(idx);
394 }
395
396 static const struct drm_crtc_helper_funcs udl_crtc_helper_funcs = {
397 .atomic_check = drm_crtc_helper_atomic_check,
398 .atomic_enable = udl_crtc_helper_atomic_enable,
399 .atomic_disable = udl_crtc_helper_atomic_disable,
400 };
401
402 static const struct drm_crtc_funcs udl_crtc_funcs = {
403 .reset = drm_atomic_helper_crtc_reset,
404 .destroy = drm_crtc_cleanup,
405 .set_config = drm_atomic_helper_set_config,
406 .page_flip = drm_atomic_helper_page_flip,
407 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
408 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
409 };
410
411 /*
412 * Encoder
413 */
414
415 static const struct drm_encoder_funcs udl_encoder_funcs = {
416 .destroy = drm_encoder_cleanup,
417 };
418
419 /*
420 * Connector
421 */
422
udl_connector_helper_get_modes(struct drm_connector * connector)423 static int udl_connector_helper_get_modes(struct drm_connector *connector)
424 {
425 const struct drm_edid *drm_edid;
426 int count;
427
428 drm_edid = udl_edid_read(connector);
429 drm_edid_connector_update(connector, drm_edid);
430 count = drm_edid_connector_add_modes(connector);
431 drm_edid_free(drm_edid);
432
433 return count;
434 }
435
udl_connector_helper_detect_ctx(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)436 static int udl_connector_helper_detect_ctx(struct drm_connector *connector,
437 struct drm_modeset_acquire_ctx *ctx,
438 bool force)
439 {
440 struct udl_device *udl = to_udl(connector->dev);
441
442 if (udl_probe_edid(udl))
443 return connector_status_connected;
444
445 return connector_status_disconnected;
446 }
447
448 static const struct drm_connector_helper_funcs udl_connector_helper_funcs = {
449 .get_modes = udl_connector_helper_get_modes,
450 .detect_ctx = udl_connector_helper_detect_ctx,
451 };
452
453 static const struct drm_connector_funcs udl_connector_funcs = {
454 .reset = drm_atomic_helper_connector_reset,
455 .fill_modes = drm_helper_probe_single_connector_modes,
456 .destroy = drm_connector_cleanup,
457 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
458 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
459 };
460
461 /*
462 * Modesetting
463 */
464
udl_mode_config_mode_valid(struct drm_device * dev,const struct drm_display_mode * mode)465 static enum drm_mode_status udl_mode_config_mode_valid(struct drm_device *dev,
466 const struct drm_display_mode *mode)
467 {
468 struct udl_device *udl = to_udl(dev);
469
470 if (udl->sku_pixel_limit) {
471 if (mode->vdisplay * mode->hdisplay > udl->sku_pixel_limit)
472 return MODE_MEM;
473 }
474
475 return MODE_OK;
476 }
477
478 static const struct drm_mode_config_funcs udl_mode_config_funcs = {
479 .fb_create = drm_gem_fb_create_with_dirty,
480 .mode_valid = udl_mode_config_mode_valid,
481 .atomic_check = drm_atomic_helper_check,
482 .atomic_commit = drm_atomic_helper_commit,
483 };
484
udl_modeset_init(struct udl_device * udl)485 int udl_modeset_init(struct udl_device *udl)
486 {
487 struct drm_device *dev = &udl->drm;
488 struct drm_plane *primary_plane;
489 struct drm_crtc *crtc;
490 struct drm_encoder *encoder;
491 struct drm_connector *connector;
492 int ret;
493
494 ret = drmm_mode_config_init(dev);
495 if (ret)
496 return ret;
497
498 dev->mode_config.min_width = 640;
499 dev->mode_config.min_height = 480;
500 dev->mode_config.max_width = 2048;
501 dev->mode_config.max_height = 2048;
502 dev->mode_config.preferred_depth = 16;
503 dev->mode_config.funcs = &udl_mode_config_funcs;
504
505 primary_plane = &udl->primary_plane;
506 ret = drm_universal_plane_init(dev, primary_plane, 0,
507 &udl_primary_plane_funcs,
508 udl_primary_plane_formats,
509 ARRAY_SIZE(udl_primary_plane_formats),
510 udl_primary_plane_fmtmods,
511 DRM_PLANE_TYPE_PRIMARY, NULL);
512 if (ret)
513 return ret;
514 drm_plane_helper_add(primary_plane, &udl_primary_plane_helper_funcs);
515 drm_plane_enable_fb_damage_clips(primary_plane);
516
517 crtc = &udl->crtc;
518 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL,
519 &udl_crtc_funcs, NULL);
520 if (ret)
521 return ret;
522 drm_crtc_helper_add(crtc, &udl_crtc_helper_funcs);
523
524 encoder = &udl->encoder;
525 ret = drm_encoder_init(dev, encoder, &udl_encoder_funcs, DRM_MODE_ENCODER_DAC, NULL);
526 if (ret)
527 return ret;
528 encoder->possible_crtcs = drm_crtc_mask(crtc);
529
530 connector = &udl->connector;
531 ret = drm_connector_init(dev, connector, &udl_connector_funcs, DRM_MODE_CONNECTOR_VGA);
532 if (ret)
533 return ret;
534 drm_connector_helper_add(connector, &udl_connector_helper_funcs);
535
536 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
537 DRM_CONNECTOR_POLL_DISCONNECT;
538
539 ret = drm_connector_attach_encoder(connector, encoder);
540 if (ret)
541 return ret;
542
543 drm_mode_config_reset(dev);
544 drmm_kms_helper_poll_init(dev);
545
546 return 0;
547 }
548