1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #include <asm/msr-index.h> 7 8 #include "test_util.h" 9 #include "kvm_util.h" 10 #include "processor.h" 11 #include "vmx.h" 12 13 #define KVM_EPT_PAGE_TABLE_MIN_PADDR 0x1c0000 14 15 #define EPTP_MT_SHIFT 0 /* EPTP memtype bits 2:0 */ 16 #define EPTP_PWL_SHIFT 3 /* EPTP page walk length bits 5:3 */ 17 #define EPTP_AD_ENABLED_SHIFT 6 /* EPTP AD enabled bit 6 */ 18 19 #define EPTP_WB (X86_MEMTYPE_WB << EPTP_MT_SHIFT) 20 #define EPTP_PWL_4 (3ULL << EPTP_PWL_SHIFT) /* PWL is (levels - 1) */ 21 #define EPTP_AD_ENABLED (1ULL << EPTP_AD_ENABLED_SHIFT) 22 23 bool enable_evmcs; 24 25 struct hv_enlightened_vmcs *current_evmcs; 26 struct hv_vp_assist_page *current_vp_assist; 27 28 int vcpu_enable_evmcs(struct kvm_vcpu *vcpu) 29 { 30 u16 evmcs_ver; 31 32 vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 33 (unsigned long)&evmcs_ver); 34 35 /* KVM should return supported EVMCS version range */ 36 TEST_ASSERT(((evmcs_ver >> 8) >= (evmcs_ver & 0xff)) && 37 (evmcs_ver & 0xff) > 0, 38 "Incorrect EVMCS version range: %x:%x", 39 evmcs_ver & 0xff, evmcs_ver >> 8); 40 41 return evmcs_ver; 42 } 43 44 void vm_enable_ept(struct kvm_vm *vm) 45 { 46 struct pte_masks pte_masks; 47 48 TEST_ASSERT(kvm_cpu_has_ept(), "KVM doesn't support nested EPT"); 49 50 /* 51 * EPTs do not have 'present' or 'user' bits, instead bit 0 is the 52 * 'readable' bit. 53 */ 54 pte_masks = (struct pte_masks) { 55 .present = 0, 56 .user = 0, 57 .readable = BIT_ULL(0), 58 .writable = BIT_ULL(1), 59 .executable = BIT_ULL(2), 60 .huge = BIT_ULL(7), 61 .accessed = BIT_ULL(8), 62 .dirty = BIT_ULL(9), 63 .nx = 0, 64 }; 65 66 /* TODO: Add support for 5-level EPT. */ 67 tdp_mmu_init(vm, 4, &pte_masks); 68 } 69 70 /* Allocate memory regions for nested VMX tests. 71 * 72 * Input Args: 73 * vm - The VM to allocate guest-virtual addresses in. 74 * 75 * Output Args: 76 * p_vmx_gva - The guest virtual address for the struct vmx_pages. 77 * 78 * Return: 79 * Pointer to structure with the addresses of the VMX areas. 80 */ 81 struct vmx_pages * 82 vcpu_alloc_vmx(struct kvm_vm *vm, gva_t *p_vmx_gva) 83 { 84 gva_t vmx_gva = vm_alloc_page(vm); 85 struct vmx_pages *vmx = addr_gva2hva(vm, vmx_gva); 86 87 /* Setup of a region of guest memory for the vmxon region. */ 88 vmx->vmxon = (void *)vm_alloc_page(vm); 89 vmx->vmxon_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmxon); 90 vmx->vmxon_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmxon); 91 92 /* Setup of a region of guest memory for a vmcs. */ 93 vmx->vmcs = (void *)vm_alloc_page(vm); 94 vmx->vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmcs); 95 vmx->vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmcs); 96 97 /* Setup of a region of guest memory for the MSR bitmap. */ 98 vmx->msr = (void *)vm_alloc_page(vm); 99 vmx->msr_hva = addr_gva2hva(vm, (uintptr_t)vmx->msr); 100 vmx->msr_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->msr); 101 memset(vmx->msr_hva, 0, getpagesize()); 102 103 /* Setup of a region of guest memory for the shadow VMCS. */ 104 vmx->shadow_vmcs = (void *)vm_alloc_page(vm); 105 vmx->shadow_vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->shadow_vmcs); 106 vmx->shadow_vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->shadow_vmcs); 107 108 /* Setup of a region of guest memory for the VMREAD and VMWRITE bitmaps. */ 109 vmx->vmread = (void *)vm_alloc_page(vm); 110 vmx->vmread_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmread); 111 vmx->vmread_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmread); 112 memset(vmx->vmread_hva, 0, getpagesize()); 113 114 vmx->vmwrite = (void *)vm_alloc_page(vm); 115 vmx->vmwrite_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmwrite); 116 vmx->vmwrite_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmwrite); 117 memset(vmx->vmwrite_hva, 0, getpagesize()); 118 119 vmx->stack = (void *)vm_alloc_stack(vm, 1); 120 121 if (vm->stage2_mmu.pgd_created) 122 vmx->eptp_gpa = vm->stage2_mmu.pgd; 123 124 *p_vmx_gva = vmx_gva; 125 return vmx; 126 } 127 128 void prepare_for_vmx_operation(struct vmx_pages *vmx) 129 { 130 u64 feature_control; 131 u64 required; 132 unsigned long cr0; 133 unsigned long cr4; 134 135 /* 136 * Ensure bits in CR0 and CR4 are valid in VMX operation: 137 * - Bit X is 1 in _FIXED0: bit X is fixed to 1 in CRx. 138 * - Bit X is 0 in _FIXED1: bit X is fixed to 0 in CRx. 139 */ 140 __asm__ __volatile__("mov %%cr0, %0" : "=r"(cr0) : : "memory"); 141 cr0 &= rdmsr(MSR_IA32_VMX_CR0_FIXED1); 142 cr0 |= rdmsr(MSR_IA32_VMX_CR0_FIXED0); 143 __asm__ __volatile__("mov %0, %%cr0" : : "r"(cr0) : "memory"); 144 145 __asm__ __volatile__("mov %%cr4, %0" : "=r"(cr4) : : "memory"); 146 cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1); 147 cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0); 148 /* Enable VMX operation */ 149 cr4 |= X86_CR4_VMXE; 150 __asm__ __volatile__("mov %0, %%cr4" : : "r"(cr4) : "memory"); 151 152 /* 153 * Configure IA32_FEATURE_CONTROL MSR to allow VMXON: 154 * Bit 0: Lock bit. If clear, VMXON causes a #GP. 155 * Bit 2: Enables VMXON outside of SMX operation. If clear, VMXON 156 * outside of SMX causes a #GP. 157 */ 158 required = FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 159 required |= FEAT_CTL_LOCKED; 160 feature_control = rdmsr(MSR_IA32_FEAT_CTL); 161 if ((feature_control & required) != required) 162 wrmsr(MSR_IA32_FEAT_CTL, feature_control | required); 163 164 /* Enter VMX root operation. */ 165 *(u32 *)(vmx->vmxon) = vmcs_revision(); 166 vmxon(vmx->vmxon_gpa); 167 } 168 169 void load_vmcs(struct vmx_pages *vmx) 170 { 171 /* Load a VMCS. */ 172 *(u32 *)(vmx->vmcs) = vmcs_revision(); 173 vmclear(vmx->vmcs_gpa); 174 175 vmptrld(vmx->vmcs_gpa); 176 177 /* Setup shadow VMCS, do not load it yet. */ 178 *(u32 *)(vmx->shadow_vmcs) = vmcs_revision() | 0x80000000ul; 179 vmclear(vmx->shadow_vmcs_gpa); 180 } 181 182 #define __BUILD_VMX_VM_ENTRY_HELPER(insn, prefix, vmwrite_insn, vmwrite_operand, \ 183 __host_rsp, __host_rip) \ 184 static int __##prefix##_##insn(void) \ 185 { \ 186 int ret; \ 187 \ 188 __asm__ __volatile__("push $0;" \ 189 __stringify(vmwrite_insn) " %%rsp, %[host_rsp];" \ 190 "lea 1f(%%rip), %%rax;" \ 191 __stringify(vmwrite_insn) " %%rax, %[host_rip];" \ 192 VMX_SWITCH_GPRS_ASM \ 193 __stringify(insn)";" \ 194 "incq (%%rsp);" \ 195 "1: ;" \ 196 VMX_SWITCH_GPRS_ASM \ 197 "pop %%rax;" \ 198 : [ret]"=&a"(ret) \ 199 : [host_rsp]__stringify(vmwrite_operand)(__host_rsp), \ 200 [host_rip]__stringify(vmwrite_operand)(__host_rip), \ 201 GUEST_REGS_OFFSETS \ 202 : "memory", "cc"); \ 203 return ret; \ 204 } 205 206 #define BUILD_VMX_VM_ENTRY_HELPER(insn) \ 207 __BUILD_VMX_VM_ENTRY_HELPER(insn, _, vmwrite, r, (u64)HOST_RSP, (u64)HOST_RIP) \ 208 __BUILD_VMX_VM_ENTRY_HELPER(insn, __evmcs, mov, m, \ 209 current_evmcs->host_rsp, current_evmcs->host_rip) 210 211 BUILD_VMX_VM_ENTRY_HELPER(vmlaunch) 212 BUILD_VMX_VM_ENTRY_HELPER(vmresume) 213 214 int __vmlaunch(void) 215 { 216 if (enable_evmcs) { 217 current_evmcs->hv_clean_fields = 0; 218 return ____evmcs_vmlaunch(); 219 } 220 221 return ____vmlaunch(); 222 } 223 224 int __vmresume(void) 225 { 226 if (enable_evmcs) { 227 /* HOST_RIP */ 228 current_evmcs->hv_clean_fields &= ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1; 229 /* HOST_RSP */ 230 current_evmcs->hv_clean_fields &= ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER; 231 return ____evmcs_vmresume(); 232 } 233 234 return ____vmresume(); 235 } 236 237 static bool ept_vpid_cap_supported(u64 mask) 238 { 239 return rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & mask; 240 } 241 242 bool ept_1g_pages_supported(void) 243 { 244 return ept_vpid_cap_supported(VMX_EPT_VPID_CAP_1G_PAGES); 245 } 246 247 /* 248 * Initialize the control fields to the most basic settings possible. 249 */ 250 static inline void init_vmcs_control_fields(struct vmx_pages *vmx) 251 { 252 u32 sec_exec_ctl = 0; 253 254 __vmwrite(VIRTUAL_PROCESSOR_ID, 0); 255 __vmwrite(POSTED_INTR_NV, 0); 256 257 vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS)); 258 259 if (vmx->eptp_gpa) { 260 u64 eptp = vmx->eptp_gpa | EPTP_WB | EPTP_PWL_4; 261 262 TEST_ASSERT((vmx->eptp_gpa & ~PHYSICAL_PAGE_MASK) == 0, 263 "Illegal bits set in vmx->eptp_gpa"); 264 265 if (ept_vpid_cap_supported(VMX_EPT_VPID_CAP_AD_BITS)) 266 eptp |= EPTP_AD_ENABLED; 267 268 vmwrite(EPT_POINTER, eptp); 269 sec_exec_ctl |= SECONDARY_EXEC_ENABLE_EPT; 270 } 271 272 if (!__vmwrite(SECONDARY_VM_EXEC_CONTROL, sec_exec_ctl)) 273 vmwrite(CPU_BASED_VM_EXEC_CONTROL, 274 rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); 275 else { 276 vmwrite(CPU_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS)); 277 GUEST_ASSERT(!sec_exec_ctl); 278 } 279 280 vmwrite(EXCEPTION_BITMAP, 0); 281 vmwrite(PAGE_FAULT_ERROR_CODE_MASK, 0); 282 vmwrite(PAGE_FAULT_ERROR_CODE_MATCH, 0); 283 vmwrite(CR3_TARGET_COUNT, 0); 284 vmwrite(VM_EXIT_CONTROLS, rdmsr(MSR_IA32_VMX_EXIT_CTLS) | 285 VM_EXIT_HOST_ADDR_SPACE_SIZE); /* 64-bit host */ 286 vmwrite(VM_EXIT_MSR_STORE_COUNT, 0); 287 vmwrite(VM_EXIT_MSR_LOAD_COUNT, 0); 288 vmwrite(VM_ENTRY_CONTROLS, rdmsr(MSR_IA32_VMX_ENTRY_CTLS) | 289 VM_ENTRY_IA32E_MODE); /* 64-bit guest */ 290 vmwrite(VM_ENTRY_MSR_LOAD_COUNT, 0); 291 vmwrite(VM_ENTRY_INTR_INFO_FIELD, 0); 292 __vmwrite(TPR_THRESHOLD, 0); 293 294 vmwrite(CR0_GUEST_HOST_MASK, 0); 295 vmwrite(CR4_GUEST_HOST_MASK, 0); 296 vmwrite(CR0_READ_SHADOW, get_cr0()); 297 vmwrite(CR4_READ_SHADOW, get_cr4()); 298 299 __vmwrite(MSR_BITMAP, vmx->msr_gpa); 300 __vmwrite(VMREAD_BITMAP, vmx->vmread_gpa); 301 __vmwrite(VMWRITE_BITMAP, vmx->vmwrite_gpa); 302 } 303 304 /* 305 * Initialize the host state fields based on the current host state, with 306 * the exception of HOST_RSP and HOST_RIP, which should be set by vmlaunch 307 * or vmresume. 308 */ 309 static inline void init_vmcs_host_state(void) 310 { 311 u32 exit_controls = vmread(VM_EXIT_CONTROLS); 312 313 vmwrite(HOST_ES_SELECTOR, get_es()); 314 vmwrite(HOST_CS_SELECTOR, get_cs()); 315 vmwrite(HOST_SS_SELECTOR, get_ss()); 316 vmwrite(HOST_DS_SELECTOR, get_ds()); 317 vmwrite(HOST_FS_SELECTOR, get_fs()); 318 vmwrite(HOST_GS_SELECTOR, get_gs()); 319 vmwrite(HOST_TR_SELECTOR, get_tr()); 320 321 if (exit_controls & VM_EXIT_LOAD_IA32_PAT) 322 vmwrite(HOST_IA32_PAT, rdmsr(MSR_IA32_CR_PAT)); 323 if (exit_controls & VM_EXIT_LOAD_IA32_EFER) 324 vmwrite(HOST_IA32_EFER, rdmsr(MSR_EFER)); 325 if (exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 326 vmwrite(HOST_IA32_PERF_GLOBAL_CTRL, 327 rdmsr(MSR_CORE_PERF_GLOBAL_CTRL)); 328 329 vmwrite(HOST_IA32_SYSENTER_CS, rdmsr(MSR_IA32_SYSENTER_CS)); 330 331 vmwrite(HOST_CR0, get_cr0()); 332 vmwrite(HOST_CR3, get_cr3()); 333 vmwrite(HOST_CR4, get_cr4()); 334 vmwrite(HOST_FS_BASE, rdmsr(MSR_FS_BASE)); 335 vmwrite(HOST_GS_BASE, rdmsr(MSR_GS_BASE)); 336 vmwrite(HOST_TR_BASE, 337 get_desc64_base((struct desc64 *)(get_gdt().address + get_tr()))); 338 vmwrite(HOST_GDTR_BASE, get_gdt().address); 339 vmwrite(HOST_IDTR_BASE, get_idt().address); 340 vmwrite(HOST_IA32_SYSENTER_ESP, rdmsr(MSR_IA32_SYSENTER_ESP)); 341 vmwrite(HOST_IA32_SYSENTER_EIP, rdmsr(MSR_IA32_SYSENTER_EIP)); 342 } 343 344 /* 345 * Initialize the guest state fields essentially as a clone of 346 * the host state fields. Some host state fields have fixed 347 * values, and we set the corresponding guest state fields accordingly. 348 */ 349 static inline void init_vmcs_guest_state(void *rip, void *rsp) 350 { 351 vmwrite(GUEST_ES_SELECTOR, vmread(HOST_ES_SELECTOR)); 352 vmwrite(GUEST_CS_SELECTOR, vmread(HOST_CS_SELECTOR)); 353 vmwrite(GUEST_SS_SELECTOR, vmread(HOST_SS_SELECTOR)); 354 vmwrite(GUEST_DS_SELECTOR, vmread(HOST_DS_SELECTOR)); 355 vmwrite(GUEST_FS_SELECTOR, vmread(HOST_FS_SELECTOR)); 356 vmwrite(GUEST_GS_SELECTOR, vmread(HOST_GS_SELECTOR)); 357 vmwrite(GUEST_LDTR_SELECTOR, 0); 358 vmwrite(GUEST_TR_SELECTOR, vmread(HOST_TR_SELECTOR)); 359 __vmwrite(GUEST_INTR_STATUS, 0); 360 __vmwrite(GUEST_PML_INDEX, 0); 361 362 vmwrite(VMCS_LINK_POINTER, -1ll); 363 vmwrite(GUEST_IA32_DEBUGCTL, 0); 364 __vmwrite(GUEST_IA32_PAT, vmread(HOST_IA32_PAT)); 365 __vmwrite(GUEST_IA32_EFER, vmread(HOST_IA32_EFER)); 366 __vmwrite(GUEST_IA32_PERF_GLOBAL_CTRL, 367 vmread(HOST_IA32_PERF_GLOBAL_CTRL)); 368 369 vmwrite(GUEST_ES_LIMIT, -1); 370 vmwrite(GUEST_CS_LIMIT, -1); 371 vmwrite(GUEST_SS_LIMIT, -1); 372 vmwrite(GUEST_DS_LIMIT, -1); 373 vmwrite(GUEST_FS_LIMIT, -1); 374 vmwrite(GUEST_GS_LIMIT, -1); 375 vmwrite(GUEST_LDTR_LIMIT, -1); 376 vmwrite(GUEST_TR_LIMIT, 0x67); 377 vmwrite(GUEST_GDTR_LIMIT, 0xffff); 378 vmwrite(GUEST_IDTR_LIMIT, 0xffff); 379 vmwrite(GUEST_ES_AR_BYTES, 380 vmread(GUEST_ES_SELECTOR) == 0 ? 0x10000 : 0xc093); 381 vmwrite(GUEST_CS_AR_BYTES, 0xa09b); 382 vmwrite(GUEST_SS_AR_BYTES, 0xc093); 383 vmwrite(GUEST_DS_AR_BYTES, 384 vmread(GUEST_DS_SELECTOR) == 0 ? 0x10000 : 0xc093); 385 vmwrite(GUEST_FS_AR_BYTES, 386 vmread(GUEST_FS_SELECTOR) == 0 ? 0x10000 : 0xc093); 387 vmwrite(GUEST_GS_AR_BYTES, 388 vmread(GUEST_GS_SELECTOR) == 0 ? 0x10000 : 0xc093); 389 vmwrite(GUEST_LDTR_AR_BYTES, 0x10000); 390 vmwrite(GUEST_TR_AR_BYTES, 0x8b); 391 vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0); 392 vmwrite(GUEST_ACTIVITY_STATE, 0); 393 vmwrite(GUEST_SYSENTER_CS, vmread(HOST_IA32_SYSENTER_CS)); 394 __vmwrite(VMX_PREEMPTION_TIMER_VALUE, 0); 395 396 vmwrite(GUEST_CR0, vmread(HOST_CR0)); 397 vmwrite(GUEST_CR3, vmread(HOST_CR3)); 398 vmwrite(GUEST_CR4, vmread(HOST_CR4)); 399 vmwrite(GUEST_ES_BASE, 0); 400 vmwrite(GUEST_CS_BASE, 0); 401 vmwrite(GUEST_SS_BASE, 0); 402 vmwrite(GUEST_DS_BASE, 0); 403 vmwrite(GUEST_FS_BASE, vmread(HOST_FS_BASE)); 404 vmwrite(GUEST_GS_BASE, vmread(HOST_GS_BASE)); 405 vmwrite(GUEST_LDTR_BASE, 0); 406 vmwrite(GUEST_TR_BASE, vmread(HOST_TR_BASE)); 407 vmwrite(GUEST_GDTR_BASE, vmread(HOST_GDTR_BASE)); 408 vmwrite(GUEST_IDTR_BASE, vmread(HOST_IDTR_BASE)); 409 vmwrite(GUEST_DR7, 0x400); 410 vmwrite(GUEST_RSP, (u64)rsp); 411 vmwrite(GUEST_RIP, (u64)rip); 412 vmwrite(GUEST_RFLAGS, X86_EFLAGS_FIXED); 413 vmwrite(GUEST_PENDING_DBG_EXCEPTIONS, 0); 414 vmwrite(GUEST_SYSENTER_ESP, vmread(HOST_IA32_SYSENTER_ESP)); 415 vmwrite(GUEST_SYSENTER_EIP, vmread(HOST_IA32_SYSENTER_EIP)); 416 } 417 418 void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip) 419 { 420 init_vmcs_control_fields(vmx); 421 init_vmcs_host_state(); 422 init_vmcs_guest_state(guest_rip, vmx->stack); 423 } 424 425 bool kvm_cpu_has_secondary_exec_control(u32 ctrl) 426 { 427 u64 ctrl_msr; 428 429 if (!kvm_cpu_has(X86_FEATURE_VMX)) 430 return false; 431 432 ctrl_msr = kvm_get_feature_msr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) >> 32; 433 if (!(ctrl_msr & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) 434 return false; 435 436 ctrl_msr = kvm_get_feature_msr(MSR_IA32_VMX_PROCBASED_CTLS2) >> 32; 437 return ctrl_msr & ctrl; 438 } 439 440 void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm) 441 { 442 vmx->apic_access = (void *)vm_alloc_page(vm); 443 vmx->apic_access_hva = addr_gva2hva(vm, (uintptr_t)vmx->apic_access); 444 vmx->apic_access_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->apic_access); 445 } 446