1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #include <hyp/switch.h>
8
9 #include <linux/arm-smccc.h>
10 #include <linux/kvm_host.h>
11 #include <linux/types.h>
12 #include <linux/jump_label.h>
13 #include <linux/percpu.h>
14 #include <uapi/linux/psci.h>
15
16 #include <kvm/arm_psci.h>
17
18 #include <asm/barrier.h>
19 #include <asm/cpufeature.h>
20 #include <asm/kprobes.h>
21 #include <asm/kvm_asm.h>
22 #include <asm/kvm_emulate.h>
23 #include <asm/kvm_hyp.h>
24 #include <asm/kvm_mmu.h>
25 #include <asm/fpsimd.h>
26 #include <asm/debug-monitors.h>
27 #include <asm/processor.h>
28 #include <asm/thread_info.h>
29 #include <asm/vectors.h>
30
31 /* VHE specific context */
32 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
33 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
34 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
35
36 /*
37 * HCR_EL2 bits that the NV guest can freely change (no RES0/RES1
38 * semantics, irrespective of the configuration), but that cannot be
39 * applied to the actual HW as things would otherwise break badly.
40 *
41 * - TGE: we want the guest to use EL1, which is incompatible with
42 * this bit being set
43 *
44 * - API/APK: they are already accounted for by vcpu_load(), and can
45 * only take effect across a load/put cycle (such as ERET)
46 */
47 #define NV_HCR_GUEST_EXCLUDE (HCR_TGE | HCR_API | HCR_APK)
48
__compute_hcr(struct kvm_vcpu * vcpu)49 static u64 __compute_hcr(struct kvm_vcpu *vcpu)
50 {
51 u64 guest_hcr, hcr = vcpu->arch.hcr_el2;
52
53 if (!vcpu_has_nv(vcpu))
54 return hcr;
55
56 /*
57 * We rely on the invariant that a vcpu entered from HYP
58 * context must also exit in the same context, as only an ERET
59 * instruction can kick us out of it, and we obviously trap
60 * that sucker. PSTATE.M will get fixed-up on exit.
61 */
62 if (is_hyp_ctxt(vcpu)) {
63 host_data_set_flag(VCPU_IN_HYP_CONTEXT);
64
65 hcr |= HCR_NV | HCR_NV2 | HCR_AT | HCR_TTLB;
66
67 if (!vcpu_el2_e2h_is_set(vcpu))
68 hcr |= HCR_NV1;
69
70 /*
71 * Nothing in HCR_EL2 should impact running in hypervisor
72 * context, apart from bits we have defined as RESx (E2H,
73 * HCD and co), or that cannot be set directly (the EXCLUDE
74 * bits). Given that we OR the guest's view with the host's,
75 * we can use the 0 value as the starting point, and only
76 * use the config-driven RES1 bits.
77 */
78 guest_hcr = kvm_vcpu_apply_reg_masks(vcpu, HCR_EL2, 0);
79
80 write_sysreg_s(vcpu->arch.ctxt.vncr_array, SYS_VNCR_EL2);
81 } else {
82 host_data_clear_flag(VCPU_IN_HYP_CONTEXT);
83
84 guest_hcr = __vcpu_sys_reg(vcpu, HCR_EL2);
85 if (guest_hcr & HCR_NV) {
86 u64 va = __fix_to_virt(vncr_fixmap(smp_processor_id()));
87
88 /* Inherit the low bits from the actual register */
89 va |= __vcpu_sys_reg(vcpu, VNCR_EL2) & GENMASK(PAGE_SHIFT - 1, 0);
90 write_sysreg_s(va, SYS_VNCR_EL2);
91
92 /* Force NV2 in case the guest is forgetful... */
93 guest_hcr |= HCR_NV2;
94 }
95 }
96
97 BUG_ON(host_data_test_flag(VCPU_IN_HYP_CONTEXT) &&
98 host_data_test_flag(L1_VNCR_MAPPED));
99
100 return hcr | (guest_hcr & ~NV_HCR_GUEST_EXCLUDE);
101 }
102
__activate_traps(struct kvm_vcpu * vcpu)103 static void __activate_traps(struct kvm_vcpu *vcpu)
104 {
105 u64 val;
106
107 ___activate_traps(vcpu, __compute_hcr(vcpu));
108
109 if (has_cntpoff()) {
110 struct timer_map map;
111
112 get_timer_map(vcpu, &map);
113
114 /*
115 * We're entrering the guest. Reload the correct
116 * values from memory now that TGE is clear.
117 */
118 if (map.direct_ptimer == vcpu_ptimer(vcpu))
119 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
120 if (map.direct_ptimer == vcpu_hptimer(vcpu))
121 val = __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2);
122
123 if (map.direct_ptimer) {
124 write_sysreg_el0(val, SYS_CNTP_CVAL);
125 isb();
126 }
127 }
128
129 __activate_cptr_traps(vcpu);
130
131 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1);
132 }
133 NOKPROBE_SYMBOL(__activate_traps);
134
__deactivate_traps(struct kvm_vcpu * vcpu)135 static void __deactivate_traps(struct kvm_vcpu *vcpu)
136 {
137 const char *host_vectors = vectors;
138
139 ___deactivate_traps(vcpu);
140
141 write_sysreg_hcr(HCR_HOST_VHE_FLAGS);
142
143 if (has_cntpoff()) {
144 struct timer_map map;
145 u64 val, offset;
146
147 get_timer_map(vcpu, &map);
148
149 /*
150 * We're exiting the guest. Save the latest CVAL value
151 * to memory and apply the offset now that TGE is set.
152 */
153 val = read_sysreg_el0(SYS_CNTP_CVAL);
154 if (map.direct_ptimer == vcpu_ptimer(vcpu))
155 __vcpu_assign_sys_reg(vcpu, CNTP_CVAL_EL0, val);
156 if (map.direct_ptimer == vcpu_hptimer(vcpu))
157 __vcpu_assign_sys_reg(vcpu, CNTHP_CVAL_EL2, val);
158
159 offset = read_sysreg_s(SYS_CNTPOFF_EL2);
160
161 if (map.direct_ptimer && offset) {
162 write_sysreg_el0(val + offset, SYS_CNTP_CVAL);
163 isb();
164 }
165 }
166
167 /*
168 * ARM errata 1165522 and 1530923 require the actual execution of the
169 * above before we can switch to the EL2/EL0 translation regime used by
170 * the host.
171 */
172 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
173
174 __deactivate_cptr_traps(vcpu);
175
176 if (!arm64_kernel_unmapped_at_el0())
177 host_vectors = __this_cpu_read(this_cpu_vector);
178 write_sysreg(host_vectors, vbar_el1);
179 }
180 NOKPROBE_SYMBOL(__deactivate_traps);
181
182 /*
183 * Disable IRQs in __vcpu_{load,put}_{activate,deactivate}_traps() to
184 * prevent a race condition between context switching of PMUSERENR_EL0
185 * in __{activate,deactivate}_traps_common() and IPIs that attempts to
186 * update PMUSERENR_EL0. See also kvm_set_pmuserenr().
187 */
__vcpu_load_activate_traps(struct kvm_vcpu * vcpu)188 static void __vcpu_load_activate_traps(struct kvm_vcpu *vcpu)
189 {
190 unsigned long flags;
191
192 local_irq_save(flags);
193 __activate_traps_common(vcpu);
194 local_irq_restore(flags);
195 }
196
__vcpu_put_deactivate_traps(struct kvm_vcpu * vcpu)197 static void __vcpu_put_deactivate_traps(struct kvm_vcpu *vcpu)
198 {
199 unsigned long flags;
200
201 local_irq_save(flags);
202 __deactivate_traps_common(vcpu);
203 local_irq_restore(flags);
204 }
205
kvm_vcpu_load_vhe(struct kvm_vcpu * vcpu)206 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu)
207 {
208 host_data_ptr(host_ctxt)->__hyp_running_vcpu = vcpu;
209
210 __vcpu_load_switch_sysregs(vcpu);
211 __vcpu_load_activate_traps(vcpu);
212 __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch);
213 }
214
kvm_vcpu_put_vhe(struct kvm_vcpu * vcpu)215 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu)
216 {
217 __vcpu_put_deactivate_traps(vcpu);
218 __vcpu_put_switch_sysregs(vcpu);
219
220 host_data_ptr(host_ctxt)->__hyp_running_vcpu = NULL;
221 }
222
compute_emulated_cntx_ctl_el0(struct kvm_vcpu * vcpu,enum vcpu_sysreg reg)223 static u64 compute_emulated_cntx_ctl_el0(struct kvm_vcpu *vcpu,
224 enum vcpu_sysreg reg)
225 {
226 unsigned long ctl;
227 u64 cval, cnt;
228 bool stat;
229
230 switch (reg) {
231 case CNTP_CTL_EL0:
232 cval = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
233 ctl = __vcpu_sys_reg(vcpu, CNTP_CTL_EL0);
234 cnt = compute_counter_value(vcpu_ptimer(vcpu));
235 break;
236 case CNTV_CTL_EL0:
237 cval = __vcpu_sys_reg(vcpu, CNTV_CVAL_EL0);
238 ctl = __vcpu_sys_reg(vcpu, CNTV_CTL_EL0);
239 cnt = compute_counter_value(vcpu_vtimer(vcpu));
240 break;
241 default:
242 BUG();
243 }
244
245 stat = cval <= cnt;
246 __assign_bit(__ffs(ARCH_TIMER_CTRL_IT_STAT), &ctl, stat);
247
248 return ctl;
249 }
250
kvm_hyp_handle_timer(struct kvm_vcpu * vcpu,u64 * exit_code)251 static bool kvm_hyp_handle_timer(struct kvm_vcpu *vcpu, u64 *exit_code)
252 {
253 u64 esr, val;
254
255 /*
256 * Having FEAT_ECV allows for a better quality of timer emulation.
257 * However, this comes at a huge cost in terms of traps. Try and
258 * satisfy the reads from guest's hypervisor context without
259 * returning to the kernel if we can.
260 */
261 if (!is_hyp_ctxt(vcpu))
262 return false;
263
264 esr = kvm_vcpu_get_esr(vcpu);
265 if ((esr & ESR_ELx_SYS64_ISS_DIR_MASK) != ESR_ELx_SYS64_ISS_DIR_READ)
266 return false;
267
268 switch (esr_sys64_to_sysreg(esr)) {
269 case SYS_CNTP_CTL_EL02:
270 val = compute_emulated_cntx_ctl_el0(vcpu, CNTP_CTL_EL0);
271 break;
272 case SYS_CNTP_CTL_EL0:
273 if (vcpu_el2_e2h_is_set(vcpu))
274 val = read_sysreg_el0(SYS_CNTP_CTL);
275 else
276 val = compute_emulated_cntx_ctl_el0(vcpu, CNTP_CTL_EL0);
277 break;
278 case SYS_CNTP_CVAL_EL02:
279 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
280 break;
281 case SYS_CNTP_CVAL_EL0:
282 if (vcpu_el2_e2h_is_set(vcpu)) {
283 val = read_sysreg_el0(SYS_CNTP_CVAL);
284
285 if (!has_cntpoff())
286 val -= timer_get_offset(vcpu_hptimer(vcpu));
287 } else {
288 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
289 }
290 break;
291 case SYS_CNTPCT_EL0:
292 case SYS_CNTPCTSS_EL0:
293 val = compute_counter_value(vcpu_hptimer(vcpu));
294 break;
295 case SYS_CNTV_CTL_EL02:
296 val = compute_emulated_cntx_ctl_el0(vcpu, CNTV_CTL_EL0);
297 break;
298 case SYS_CNTV_CTL_EL0:
299 if (vcpu_el2_e2h_is_set(vcpu))
300 val = read_sysreg_el0(SYS_CNTV_CTL);
301 else
302 val = compute_emulated_cntx_ctl_el0(vcpu, CNTV_CTL_EL0);
303 break;
304 case SYS_CNTV_CVAL_EL02:
305 val = __vcpu_sys_reg(vcpu, CNTV_CVAL_EL0);
306 break;
307 case SYS_CNTV_CVAL_EL0:
308 if (vcpu_el2_e2h_is_set(vcpu))
309 val = read_sysreg_el0(SYS_CNTV_CVAL);
310 else
311 val = __vcpu_sys_reg(vcpu, CNTV_CVAL_EL0);
312 break;
313 case SYS_CNTVCT_EL0:
314 case SYS_CNTVCTSS_EL0:
315 val = compute_counter_value(vcpu_hvtimer(vcpu));
316 break;
317 default:
318 return false;
319 }
320
321 vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val);
322 __kvm_skip_instr(vcpu);
323
324 return true;
325 }
326
kvm_hyp_handle_eret(struct kvm_vcpu * vcpu,u64 * exit_code)327 static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu, u64 *exit_code)
328 {
329 u64 esr = kvm_vcpu_get_esr(vcpu);
330 u64 spsr, elr, mode;
331
332 /*
333 * Going through the whole put/load motions is a waste of time
334 * if this is a VHE guest hypervisor returning to its own
335 * userspace, or the hypervisor performing a local exception
336 * return. No need to save/restore registers, no need to
337 * switch S2 MMU. Just do the canonical ERET.
338 *
339 * Unless the trap has to be forwarded further down the line,
340 * of course...
341 */
342 if ((__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_NV) ||
343 (__vcpu_sys_reg(vcpu, HFGITR_EL2) & HFGITR_EL2_ERET))
344 return false;
345
346 spsr = read_sysreg_el1(SYS_SPSR);
347 mode = spsr & (PSR_MODE_MASK | PSR_MODE32_BIT);
348
349 switch (mode) {
350 case PSR_MODE_EL0t:
351 if (!(vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)))
352 return false;
353 break;
354 case PSR_MODE_EL2t:
355 mode = PSR_MODE_EL1t;
356 break;
357 case PSR_MODE_EL2h:
358 mode = PSR_MODE_EL1h;
359 break;
360 default:
361 return false;
362 }
363
364 /* If ERETAx fails, take the slow path */
365 if (esr_iss_is_eretax(esr)) {
366 if (!(vcpu_has_ptrauth(vcpu) && kvm_auth_eretax(vcpu, &elr)))
367 return false;
368 } else {
369 elr = read_sysreg_el1(SYS_ELR);
370 }
371
372 spsr = (spsr & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode;
373
374 write_sysreg_el2(spsr, SYS_SPSR);
375 write_sysreg_el2(elr, SYS_ELR);
376
377 return true;
378 }
379
kvm_hyp_handle_tlbi_el2(struct kvm_vcpu * vcpu,u64 * exit_code)380 static bool kvm_hyp_handle_tlbi_el2(struct kvm_vcpu *vcpu, u64 *exit_code)
381 {
382 int ret = -EINVAL;
383 u32 instr;
384 u64 val;
385
386 /*
387 * Ideally, we would never trap on EL2 S1 TLB invalidations using
388 * the EL1 instructions when the guest's HCR_EL2.{E2H,TGE}=={1,1}.
389 * But "thanks" to FEAT_NV2, we don't trap writes to HCR_EL2,
390 * meaning that we can't track changes to the virtual TGE bit. So we
391 * have to leave HCR_EL2.TTLB set on the host. Oopsie...
392 *
393 * Try and handle these invalidation as quickly as possible, without
394 * fully exiting. Note that we don't need to consider any forwarding
395 * here, as having E2H+TGE set is the very definition of being
396 * InHost.
397 *
398 * For the lesser hypervisors out there that have failed to get on
399 * with the VHE program, we can also handle the nVHE style of EL2
400 * invalidation.
401 */
402 if (!(is_hyp_ctxt(vcpu)))
403 return false;
404
405 instr = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
406 val = vcpu_get_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu));
407
408 if ((kvm_supported_tlbi_s1e1_op(vcpu, instr) &&
409 vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)) ||
410 kvm_supported_tlbi_s1e2_op (vcpu, instr))
411 ret = __kvm_tlbi_s1e2(NULL, val, instr);
412
413 if (ret)
414 return false;
415
416 /*
417 * If we have to check for any VNCR mapping being invalidated,
418 * go back to the slow path for further processing.
419 */
420 if (vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu) &&
421 atomic_read(&vcpu->kvm->arch.vncr_map_count))
422 return false;
423
424 __kvm_skip_instr(vcpu);
425
426 return true;
427 }
428
kvm_hyp_handle_cpacr_el1(struct kvm_vcpu * vcpu,u64 * exit_code)429 static bool kvm_hyp_handle_cpacr_el1(struct kvm_vcpu *vcpu, u64 *exit_code)
430 {
431 u64 esr = kvm_vcpu_get_esr(vcpu);
432 int rt;
433
434 if (!is_hyp_ctxt(vcpu) || esr_sys64_to_sysreg(esr) != SYS_CPACR_EL1)
435 return false;
436
437 rt = kvm_vcpu_sys_get_rt(vcpu);
438
439 if ((esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ) {
440 vcpu_set_reg(vcpu, rt, __vcpu_sys_reg(vcpu, CPTR_EL2));
441 } else {
442 vcpu_write_sys_reg(vcpu, vcpu_get_reg(vcpu, rt), CPTR_EL2);
443 __activate_cptr_traps(vcpu);
444 }
445
446 __kvm_skip_instr(vcpu);
447
448 return true;
449 }
450
kvm_hyp_handle_zcr_el2(struct kvm_vcpu * vcpu,u64 * exit_code)451 static bool kvm_hyp_handle_zcr_el2(struct kvm_vcpu *vcpu, u64 *exit_code)
452 {
453 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
454
455 if (!vcpu_has_nv(vcpu))
456 return false;
457
458 if (sysreg != SYS_ZCR_EL2)
459 return false;
460
461 if (guest_owns_fp_regs())
462 return false;
463
464 /*
465 * ZCR_EL2 traps are handled in the slow path, with the expectation
466 * that the guest's FP context has already been loaded onto the CPU.
467 *
468 * Load the guest's FP context and unconditionally forward to the
469 * slow path for handling (i.e. return false).
470 */
471 kvm_hyp_handle_fpsimd(vcpu, exit_code);
472 return false;
473 }
474
kvm_hyp_handle_sysreg_vhe(struct kvm_vcpu * vcpu,u64 * exit_code)475 static bool kvm_hyp_handle_sysreg_vhe(struct kvm_vcpu *vcpu, u64 *exit_code)
476 {
477 if (kvm_hyp_handle_tlbi_el2(vcpu, exit_code))
478 return true;
479
480 if (kvm_hyp_handle_timer(vcpu, exit_code))
481 return true;
482
483 if (kvm_hyp_handle_cpacr_el1(vcpu, exit_code))
484 return true;
485
486 if (kvm_hyp_handle_zcr_el2(vcpu, exit_code))
487 return true;
488
489 return kvm_hyp_handle_sysreg(vcpu, exit_code);
490 }
491
kvm_hyp_handle_impdef(struct kvm_vcpu * vcpu,u64 * exit_code)492 static bool kvm_hyp_handle_impdef(struct kvm_vcpu *vcpu, u64 *exit_code)
493 {
494 u64 iss;
495
496 if (!cpus_have_final_cap(ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS))
497 return false;
498
499 /*
500 * Compute a synthetic ESR for a sysreg trap. Conveniently, AFSR1_EL2
501 * is populated with a correct ISS for a sysreg trap. These fruity
502 * parts are 64bit only, so unconditionally set IL.
503 */
504 iss = ESR_ELx_ISS(read_sysreg_s(SYS_AFSR1_EL2));
505 vcpu->arch.fault.esr_el2 = FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_SYS64) |
506 FIELD_PREP(ESR_ELx_ISS_MASK, iss) |
507 ESR_ELx_IL;
508 return false;
509 }
510
511 static const exit_handler_fn hyp_exit_handlers[] = {
512 [0 ... ESR_ELx_EC_MAX] = NULL,
513 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32,
514 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg_vhe,
515 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd,
516 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
517 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
518 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
519 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low,
520 [ESR_ELx_EC_ERET] = kvm_hyp_handle_eret,
521 [ESR_ELx_EC_MOPS] = kvm_hyp_handle_mops,
522
523 /* Apple shenanigans */
524 [0x3F] = kvm_hyp_handle_impdef,
525 };
526
fixup_guest_exit(struct kvm_vcpu * vcpu,u64 * exit_code)527 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
528 {
529 synchronize_vcpu_pstate(vcpu, exit_code);
530
531 /*
532 * If we were in HYP context on entry, adjust the PSTATE view
533 * so that the usual helpers work correctly. This enforces our
534 * invariant that the guest's HYP context status is preserved
535 * across a run.
536 */
537 if (vcpu_has_nv(vcpu) &&
538 unlikely(host_data_test_flag(VCPU_IN_HYP_CONTEXT))) {
539 u64 mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT);
540
541 switch (mode) {
542 case PSR_MODE_EL1t:
543 mode = PSR_MODE_EL2t;
544 break;
545 case PSR_MODE_EL1h:
546 mode = PSR_MODE_EL2h;
547 break;
548 }
549
550 *vcpu_cpsr(vcpu) &= ~(PSR_MODE_MASK | PSR_MODE32_BIT);
551 *vcpu_cpsr(vcpu) |= mode;
552 }
553
554 /* Apply extreme paranoia! */
555 BUG_ON(vcpu_has_nv(vcpu) &&
556 !!host_data_test_flag(VCPU_IN_HYP_CONTEXT) != is_hyp_ctxt(vcpu));
557
558 return __fixup_guest_exit(vcpu, exit_code, hyp_exit_handlers);
559 }
560
561 /* Switch to the guest for VHE systems running in EL2 */
__kvm_vcpu_run_vhe(struct kvm_vcpu * vcpu)562 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
563 {
564 struct kvm_cpu_context *host_ctxt;
565 struct kvm_cpu_context *guest_ctxt;
566 u64 exit_code;
567
568 host_ctxt = host_data_ptr(host_ctxt);
569 guest_ctxt = &vcpu->arch.ctxt;
570
571 fpsimd_lazy_switch_to_guest(vcpu);
572
573 sysreg_save_host_state_vhe(host_ctxt);
574
575 /*
576 * Note that ARM erratum 1165522 requires us to configure both stage 1
577 * and stage 2 translation for the guest context before we clear
578 * HCR_EL2.TGE. The stage 1 and stage 2 guest context has already been
579 * loaded on the CPU in kvm_vcpu_load_vhe().
580 */
581 __activate_traps(vcpu);
582
583 __kvm_adjust_pc(vcpu);
584
585 sysreg_restore_guest_state_vhe(guest_ctxt);
586 __debug_switch_to_guest(vcpu);
587
588 do {
589 /* Jump in the fire! */
590 exit_code = __guest_enter(vcpu);
591
592 /* And we're baaack! */
593 } while (fixup_guest_exit(vcpu, &exit_code));
594
595 sysreg_save_guest_state_vhe(guest_ctxt);
596
597 __deactivate_traps(vcpu);
598
599 sysreg_restore_host_state_vhe(host_ctxt);
600
601 __debug_switch_to_host(vcpu);
602
603 /*
604 * Ensure that all system register writes above have taken effect
605 * before returning to the host. In VHE mode, CPTR traps for
606 * FPSIMD/SVE/SME also apply to EL2, so FPSIMD/SVE/SME state must be
607 * manipulated after the ISB.
608 */
609 isb();
610
611 fpsimd_lazy_switch_to_host(vcpu);
612
613 if (guest_owns_fp_regs())
614 __fpsimd_save_fpexc32(vcpu);
615
616 return exit_code;
617 }
618 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe);
619
__kvm_vcpu_run(struct kvm_vcpu * vcpu)620 int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
621 {
622 int ret;
623
624 local_daif_mask();
625
626 /*
627 * Having IRQs masked via PMR when entering the guest means the GIC
628 * will not signal the CPU of interrupts of lower priority, and the
629 * only way to get out will be via guest exceptions.
630 * Naturally, we want to avoid this.
631 *
632 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a
633 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU.
634 */
635 pmr_sync();
636
637 ret = __kvm_vcpu_run_vhe(vcpu);
638
639 /*
640 * local_daif_restore() takes care to properly restore PSTATE.DAIF
641 * and the GIC PMR if the host is using IRQ priorities.
642 */
643 local_daif_restore(DAIF_PROCCTX_NOIRQ);
644
645 return ret;
646 }
647
__hyp_call_panic(u64 spsr,u64 elr,u64 par)648 static void __noreturn __hyp_call_panic(u64 spsr, u64 elr, u64 par)
649 {
650 struct kvm_cpu_context *host_ctxt;
651 struct kvm_vcpu *vcpu;
652
653 host_ctxt = host_data_ptr(host_ctxt);
654 vcpu = host_ctxt->__hyp_running_vcpu;
655
656 __deactivate_traps(vcpu);
657 sysreg_restore_host_state_vhe(host_ctxt);
658
659 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n",
660 spsr, elr,
661 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR),
662 read_sysreg(hpfar_el2), par, vcpu);
663 }
664 NOKPROBE_SYMBOL(__hyp_call_panic);
665
hyp_panic(void)666 void __noreturn hyp_panic(void)
667 {
668 u64 spsr = read_sysreg_el2(SYS_SPSR);
669 u64 elr = read_sysreg_el2(SYS_ELR);
670 u64 par = read_sysreg_par();
671
672 __hyp_call_panic(spsr, elr, par);
673 }
674
kvm_unexpected_el2_exception(void)675 asmlinkage void kvm_unexpected_el2_exception(void)
676 {
677 __kvm_unexpected_el2_exception();
678 }
679