1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2024 Yixun Lan <dlan@gentoo.org> */
3
4 #include <linux/bits.h>
5 #include <linux/clk.h>
6 #include <linux/cleanup.h>
7 #include <linux/io.h>
8 #include <linux/of.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11 #include <linux/seq_file.h>
12 #include <linux/spinlock.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16
17 #include <linux/pinctrl/pinconf-generic.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinctrl.h>
20 #include <linux/pinctrl/pinmux.h>
21
22 #include "../core.h"
23 #include "../pinctrl-utils.h"
24 #include "../pinconf.h"
25 #include "../pinmux.h"
26 #include "pinctrl-k1.h"
27
28 /*
29 * | pull | drive | schmitter | slew | edge | strong | mux |
30 * SoC | up/down | strength | trigger | rate | detect | pull | mode |
31 *-----+---------+----------+-----------+-------+--------+--------+--------+
32 * K1 | 3 bits | 3 bits | 2 bits | 1 bit | 3 bits | 1 bit | 3 bits |
33 *-----+---------+----------+-----------+-------+--------+--------+--------+
34 * K3 | 3 bits | 4 bits | 1 bits | 1 bit | 3 bits | 1 bit | 3 bits |
35 */
36
37 #define PAD_MUX GENMASK(2, 0)
38 #define PAD_STRONG_PULL BIT(3)
39 #define PAD_EDGE_RISE BIT(4)
40 #define PAD_EDGE_FALL BIT(5)
41 #define PAD_EDGE_CLEAR BIT(6)
42 #define PAD_SLEW_RATE GENMASK(12, 11)
43 #define PAD_SLEW_RATE_EN BIT(7)
44 #define PAD_SCHMITT_K1 GENMASK(9, 8)
45 #define PAD_DRIVE_K1 GENMASK(12, 10)
46 #define PAD_SCHMITT_K3 BIT(8)
47 #define PAD_DRIVE_K3 GENMASK(12, 9)
48 #define PAD_PULLDOWN BIT(13)
49 #define PAD_PULLUP BIT(14)
50 #define PAD_PULL_EN BIT(15)
51
52 #define IO_PWR_DOMAIN_OFFSET 0x800
53
54 #define IO_PWR_DOMAIN_GPIO2_Kx 0x0c
55 #define IO_PWR_DOMAIN_MMC_Kx 0x1c
56
57 #define IO_PWR_DOMAIN_GPIO3_K1 0x10
58 #define IO_PWR_DOMAIN_QSPI_K1 0x20
59
60 #define IO_PWR_DOMAIN_GPIO1_K3 0x04
61 #define IO_PWR_DOMAIN_GPIO5_K3 0x10
62 #define IO_PWR_DOMAIN_GPIO4_K3 0x20
63 #define IO_PWR_DOMAIN_QSPI_K3 0x2c
64
65 #define IO_PWR_DOMAIN_V18EN BIT(2)
66
67 #define APBC_ASFAR 0x50
68 #define APBC_ASSAR 0x54
69
70 #define APBC_ASFAR_AKEY 0xbaba
71 #define APBC_ASSAR_AKEY 0xeb10
72
73 struct spacemit_pin_drv_strength {
74 u8 val;
75 u32 mA;
76 };
77
78 struct spacemit_pinctrl_dconf {
79 u64 schmitt_mask;
80 u64 drive_mask;
81
82 struct spacemit_pin_drv_strength *ds_1v8_tbl;
83 size_t ds_1v8_tbl_num;
84 struct spacemit_pin_drv_strength *ds_3v3_tbl;
85 size_t ds_3v3_tbl_num;
86 };
87
88 struct spacemit_pin {
89 u16 pin;
90 u16 flags;
91 u8 gpiofunc;
92 };
93
94 struct spacemit_pinctrl {
95 struct device *dev;
96 struct pinctrl_dev *pctl_dev;
97 const struct spacemit_pinctrl_data *data;
98 struct pinctrl_desc pdesc;
99
100 struct mutex mutex;
101 raw_spinlock_t lock;
102
103 void __iomem *regs;
104
105 struct regmap *regmap_apbc;
106 };
107
108 struct spacemit_pinctrl_data {
109 const struct pinctrl_pin_desc *pins;
110 const struct spacemit_pin *data;
111 u16 npins;
112 unsigned int (*pin_to_offset)(unsigned int pin);
113 unsigned int (*pin_to_io_pd_offset)(unsigned int pin);
114 const struct spacemit_pinctrl_dconf *dconf;
115 };
116
117 /* map pin id to pinctrl register offset, refer MFPR definition */
spacemit_k1_pin_to_offset(unsigned int pin)118 static unsigned int spacemit_k1_pin_to_offset(unsigned int pin)
119 {
120 unsigned int offset = 0;
121
122 switch (pin) {
123 case 0 ... 85:
124 offset = pin + 1;
125 break;
126 case 86 ... 92:
127 offset = pin + 37;
128 break;
129 case 93 ... 97:
130 offset = pin + 24;
131 break;
132 case 98:
133 offset = 93;
134 break;
135 case 99:
136 offset = 92;
137 break;
138 case 100:
139 offset = 91;
140 break;
141 case 101:
142 offset = 90;
143 break;
144 case 102:
145 offset = 95;
146 break;
147 case 103:
148 offset = 94;
149 break;
150 case 104 ... 110:
151 offset = pin + 6;
152 break;
153 case 111 ... 127:
154 offset = pin + 20;
155 break;
156 default:
157 break;
158 }
159
160 return offset << 2;
161 }
162
spacemit_k3_pin_to_offset(unsigned int pin)163 static unsigned int spacemit_k3_pin_to_offset(unsigned int pin)
164 {
165 unsigned int offset = pin > 130 ? (pin + 2) : pin;
166
167 return offset << 2;
168 }
169
spacemit_k1_pin_to_io_pd_offset(unsigned int pin)170 static unsigned int spacemit_k1_pin_to_io_pd_offset(unsigned int pin)
171 {
172 unsigned int offset = 0;
173
174 switch (pin) {
175 case 47 ... 52:
176 offset = IO_PWR_DOMAIN_GPIO3_K1;
177 break;
178 case 75 ... 80:
179 offset = IO_PWR_DOMAIN_GPIO2_Kx;
180 break;
181 case 98 ... 103:
182 offset = IO_PWR_DOMAIN_QSPI_K1;
183 break;
184 case 104 ... 109:
185 offset = IO_PWR_DOMAIN_MMC_Kx;
186 break;
187 }
188
189 return offset;
190 }
191
spacemit_k3_pin_to_io_pd_offset(unsigned int pin)192 static unsigned int spacemit_k3_pin_to_io_pd_offset(unsigned int pin)
193 {
194 unsigned int offset = 0;
195
196 switch (pin) {
197 case 0 ... 20:
198 offset = IO_PWR_DOMAIN_GPIO1_K3;
199 break;
200 case 21 ... 41:
201 offset = IO_PWR_DOMAIN_GPIO2_Kx;
202 break;
203 case 76 ... 98:
204 offset = IO_PWR_DOMAIN_GPIO4_K3;
205 break;
206 case 99 ... 127:
207 offset = IO_PWR_DOMAIN_GPIO5_K3;
208 break;
209 case 132 ... 137:
210 offset = IO_PWR_DOMAIN_MMC_Kx;
211 break;
212 case 138 ... 144:
213 offset = IO_PWR_DOMAIN_QSPI_K3;
214 break;
215 }
216
217 return offset;
218 }
219
spacemit_pin_to_reg(struct spacemit_pinctrl * pctrl,unsigned int pin)220 static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl,
221 unsigned int pin)
222 {
223 return pctrl->regs + pctrl->data->pin_to_offset(pin);
224 }
225
spacemit_get_pin(struct spacemit_pinctrl * pctrl,unsigned long pin)226 static const struct spacemit_pin *spacemit_get_pin(struct spacemit_pinctrl *pctrl,
227 unsigned long pin)
228 {
229 const struct spacemit_pin *pdata = pctrl->data->data;
230 int i;
231
232 for (i = 0; i < pctrl->data->npins; i++) {
233 if (pin == pdata[i].pin)
234 return &pdata[i];
235 }
236
237 return NULL;
238 }
239
spacemit_to_pin_io_type(const struct spacemit_pin * pin)240 static inline enum spacemit_pin_io_type spacemit_to_pin_io_type(
241 const struct spacemit_pin *pin)
242 {
243 return K1_PIN_GET_IO_TYPE(pin->flags);
244 }
245
246 /* External: IO voltage via external source, can be 1.8V or 3.3V */
247 static const char * const io_type_desc[] = {
248 "None",
249 "Fixed/1V8",
250 "Fixed/3V3",
251 "External",
252 };
253
spacemit_pctrl_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * seq,unsigned int pin)254 static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev,
255 struct seq_file *seq, unsigned int pin)
256 {
257 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
258 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
259 enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin);
260 void __iomem *reg;
261 u32 value;
262
263 seq_printf(seq, "offset: 0x%04x ", pctrl->data->pin_to_offset(pin));
264 seq_printf(seq, "type: %s ", io_type_desc[type]);
265
266 reg = spacemit_pin_to_reg(pctrl, pin);
267 value = readl(reg);
268 seq_printf(seq, "mux: %ld reg: 0x%04x", (value & PAD_MUX), value);
269 }
270
271 static const struct spacemit_pinctrl_dconf k1_drive_conf = {
272 .drive_mask = PAD_DRIVE_K1,
273 .schmitt_mask = PAD_SCHMITT_K1,
274 .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) {
275 { 0, 11 },
276 { 2, 21 },
277 { 4, 32 },
278 { 6, 42 },
279 },
280 .ds_1v8_tbl_num = 4,
281 .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) {
282 { 0, 7 },
283 { 2, 10 },
284 { 4, 13 },
285 { 6, 16 },
286 { 1, 19 },
287 { 3, 23 },
288 { 5, 26 },
289 { 7, 29 },
290 },
291 .ds_3v3_tbl_num = 8,
292 };
293
294 static const struct spacemit_pinctrl_dconf k3_drive_conf = {
295 .drive_mask = PAD_DRIVE_K3,
296 .schmitt_mask = PAD_SCHMITT_K3,
297 .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) {
298 { 0, 2 },
299 { 1, 4 },
300 { 2, 6 },
301 { 3, 7 },
302 { 4, 9 },
303 { 5, 11 },
304 { 6, 13 },
305 { 7, 14 },
306 { 8, 21 },
307 { 9, 23 },
308 { 10, 25 },
309 { 11, 26 },
310 { 12, 28 },
311 { 13, 30 },
312 { 14, 31 },
313 { 15, 33 },
314 },
315 .ds_1v8_tbl_num = 16,
316 .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) {
317 { 0, 3 },
318 { 1, 5 },
319 { 2, 7 },
320 { 3, 9 },
321 { 4, 11 },
322 { 5, 13 },
323 { 6, 15 },
324 { 7, 17 },
325 { 8, 25 },
326 { 9, 27 },
327 { 10, 29 },
328 { 11, 31 },
329 { 12, 33 },
330 { 13, 35 },
331 { 14, 37 },
332 { 15, 38 },
333 },
334 .ds_3v3_tbl_num = 16,
335 };
336
spacemit_get_ds_value(struct spacemit_pin_drv_strength * tbl,u32 num,u32 mA)337 static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl,
338 u32 num, u32 mA)
339 {
340 int i;
341
342 for (i = 0; i < num; i++)
343 if (mA <= tbl[i].mA)
344 return tbl[i].val;
345
346 return tbl[num - 1].val;
347 }
348
spacemit_get_ds_mA(struct spacemit_pin_drv_strength * tbl,u32 num,u32 val)349 static inline u32 spacemit_get_ds_mA(struct spacemit_pin_drv_strength *tbl,
350 u32 num, u32 val)
351 {
352 int i;
353
354 for (i = 0; i < num; i++)
355 if (val == tbl[i].val)
356 return tbl[i].mA;
357
358 return 0;
359 }
360
spacemit_get_driver_strength(enum spacemit_pin_io_type type,const struct spacemit_pinctrl_dconf * dconf,u32 mA)361 static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type,
362 const struct spacemit_pinctrl_dconf *dconf,
363 u32 mA)
364 {
365 switch (type) {
366 case IO_TYPE_1V8:
367 return spacemit_get_ds_value(dconf->ds_1v8_tbl,
368 dconf->ds_1v8_tbl_num,
369 mA);
370 case IO_TYPE_3V3:
371 return spacemit_get_ds_value(dconf->ds_3v3_tbl,
372 dconf->ds_3v3_tbl_num,
373 mA);
374 default:
375 return 0;
376 }
377 }
378
spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type,const struct spacemit_pinctrl_dconf * dconf,u32 value)379 static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type,
380 const struct spacemit_pinctrl_dconf *dconf,
381 u32 value)
382 {
383 switch (type) {
384 case IO_TYPE_1V8:
385 return spacemit_get_ds_mA(dconf->ds_1v8_tbl,
386 dconf->ds_1v8_tbl_num,
387 value);
388 case IO_TYPE_3V3:
389 return spacemit_get_ds_mA(dconf->ds_3v3_tbl,
390 dconf->ds_3v3_tbl_num,
391 value);
392 default:
393 return 0;
394 }
395 }
396
spacemit_set_io_pwr_domain(struct spacemit_pinctrl * pctrl,const struct spacemit_pin * spin,const enum spacemit_pin_io_type type)397 static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl,
398 const struct spacemit_pin *spin,
399 const enum spacemit_pin_io_type type)
400 {
401 u32 offset, val = 0;
402
403 if (!pctrl->regmap_apbc)
404 return;
405
406 offset = pctrl->data->pin_to_io_pd_offset(spin->pin);
407
408 /* Other bits are reserved so don't need to save them */
409 if (type == IO_TYPE_1V8)
410 val = IO_PWR_DOMAIN_V18EN;
411
412 /*
413 * IO power domain registers are protected and cannot be accessed
414 * directly. Before performing any read or write to the IO power
415 * domain registers, an explicit unlock sequence must be issued
416 * via the AIB Secure Access Register (ASAR).
417 *
418 * The unlock sequence allows exactly one subsequent access to the
419 * IO power domain registers. After that access completes, the ASAR
420 * keys are automatically cleared, and the registers become locked
421 * again.
422 *
423 * This mechanism ensures that IO power domain configuration is
424 * performed intentionally, as incorrect voltage settings may
425 * result in functional failures or hardware damage.
426 */
427 regmap_write(pctrl->regmap_apbc, APBC_ASFAR, APBC_ASFAR_AKEY);
428 regmap_write(pctrl->regmap_apbc, APBC_ASSAR, APBC_ASSAR_AKEY);
429
430 writel_relaxed(val, pctrl->regs + IO_PWR_DOMAIN_OFFSET + offset);
431 }
432
433 static const struct pinctrl_ops spacemit_pctrl_ops = {
434 .get_groups_count = pinctrl_generic_get_group_count,
435 .get_group_name = pinctrl_generic_get_group_name,
436 .get_group_pins = pinctrl_generic_get_group_pins,
437 .pin_dbg_show = spacemit_pctrl_dbg_show,
438 .dt_node_to_map = pinctrl_generic_pinmux_dt_node_to_map,
439 .dt_free_map = pinctrl_utils_free_map,
440 };
441
spacemit_pmx_set_mux(struct pinctrl_dev * pctldev,unsigned int fsel,unsigned int gsel)442 static int spacemit_pmx_set_mux(struct pinctrl_dev *pctldev,
443 unsigned int fsel, unsigned int gsel)
444 {
445 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
446 const struct group_desc *group;
447 unsigned int i, mux;
448 unsigned int *configs;
449 void __iomem *reg;
450
451 group = pinctrl_generic_get_group(pctldev, gsel);
452 if (!group)
453 return -EINVAL;
454
455 configs = group->data;
456
457 for (i = 0; i < group->grp.npins; i++) {
458 const struct spacemit_pin *spin;
459 u32 value = configs[i];
460
461 spin = spacemit_get_pin(pctrl, group->grp.pins[i]);
462 if (!spin) {
463 dev_err(pctrl->dev, "Invalid pin %u\n", group->grp.pins[i]);
464 return -EINVAL;
465 }
466
467 reg = spacemit_pin_to_reg(pctrl, spin->pin);
468 mux = value;
469
470 guard(raw_spinlock_irqsave)(&pctrl->lock);
471 value = readl_relaxed(reg) & ~PAD_MUX;
472 writel_relaxed(mux | value, reg);
473 }
474
475 return 0;
476 }
477
spacemit_request_gpio(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin)478 static int spacemit_request_gpio(struct pinctrl_dev *pctldev,
479 struct pinctrl_gpio_range *range,
480 unsigned int pin)
481 {
482 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
483 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
484 void __iomem *reg;
485
486 reg = spacemit_pin_to_reg(pctrl, pin);
487 guard(raw_spinlock_irqsave)(&pctrl->lock);
488 writel_relaxed(spin->gpiofunc, reg);
489
490 return 0;
491 }
492
493 static const struct pinmux_ops spacemit_pmx_ops = {
494 .get_functions_count = pinmux_generic_get_function_count,
495 .get_function_name = pinmux_generic_get_function_name,
496 .get_function_groups = pinmux_generic_get_function_groups,
497 .set_mux = spacemit_pmx_set_mux,
498 .gpio_request_enable = spacemit_request_gpio,
499 .strict = true,
500 };
501
spacemit_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)502 static int spacemit_pinconf_get(struct pinctrl_dev *pctldev,
503 unsigned int pin, unsigned long *config)
504 {
505 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
506 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
507 int param = pinconf_to_config_param(*config);
508 u32 value, arg = 0;
509
510 if (!spin)
511 return -EINVAL;
512
513 value = readl(spacemit_pin_to_reg(pctrl, spin->pin));
514
515 switch (param) {
516 case PIN_CONFIG_SLEW_RATE:
517 if (FIELD_GET(PAD_SLEW_RATE_EN, value))
518 arg = FIELD_GET(PAD_SLEW_RATE, value) + 2;
519 else
520 arg = 0;
521 break;
522 default:
523 return -ENOTSUPP;
524 }
525
526 *config = pinconf_to_config_packed(param, arg);
527
528 return 0;
529 }
530
531 #define ENABLE_DRV_STRENGTH BIT(1)
532 #define ENABLE_SLEW_RATE BIT(2)
spacemit_pinconf_generate_config(struct spacemit_pinctrl * pctrl,const struct spacemit_pin * spin,const struct spacemit_pinctrl_dconf * dconf,unsigned long * configs,unsigned int num_configs,u32 * value)533 static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl,
534 const struct spacemit_pin *spin,
535 const struct spacemit_pinctrl_dconf *dconf,
536 unsigned long *configs,
537 unsigned int num_configs,
538 u32 *value)
539 {
540 enum spacemit_pin_io_type type;
541 int i, param;
542 u32 v = 0, voltage = 0, arg, val;
543 u32 flag = 0, drv_strength, slew_rate;
544
545 if (!spin)
546 return -EINVAL;
547
548 for (i = 0; i < num_configs; i++) {
549 param = pinconf_to_config_param(configs[i]);
550 arg = pinconf_to_config_argument(configs[i]);
551
552 switch (param) {
553 case PIN_CONFIG_BIAS_DISABLE:
554 v &= ~(PAD_PULL_EN | PAD_PULLDOWN | PAD_PULLUP);
555 v &= ~PAD_STRONG_PULL;
556 break;
557 case PIN_CONFIG_BIAS_PULL_DOWN:
558 v &= ~(PAD_PULLUP | PAD_STRONG_PULL);
559 v |= (PAD_PULL_EN | PAD_PULLDOWN);
560 break;
561 case PIN_CONFIG_BIAS_PULL_UP:
562 v &= ~PAD_PULLDOWN;
563 v |= (PAD_PULL_EN | PAD_PULLUP);
564
565 if (arg == 1)
566 v |= PAD_STRONG_PULL;
567 break;
568 case PIN_CONFIG_DRIVE_STRENGTH:
569 flag |= ENABLE_DRV_STRENGTH;
570 drv_strength = arg;
571 break;
572 case PIN_CONFIG_INPUT_SCHMITT:
573 v &= ~dconf->schmitt_mask;
574 v |= (arg << __ffs(dconf->schmitt_mask)) & dconf->schmitt_mask;
575 break;
576 case PIN_CONFIG_POWER_SOURCE:
577 voltage = arg;
578 break;
579 case PIN_CONFIG_SLEW_RATE:
580 if (arg) {
581 flag |= ENABLE_SLEW_RATE;
582 v |= PAD_SLEW_RATE_EN;
583 slew_rate = arg;
584 } else {
585 v &= ~PAD_SLEW_RATE_EN;
586 }
587 break;
588 default:
589 return -ENOTSUPP;
590 }
591 }
592
593 if (flag & ENABLE_DRV_STRENGTH) {
594 type = spacemit_to_pin_io_type(spin);
595
596 /* fix external io type */
597 if (type == IO_TYPE_EXTERNAL) {
598 switch (voltage) {
599 case 1800:
600 type = IO_TYPE_1V8;
601 break;
602 case 3300:
603 type = IO_TYPE_3V3;
604 break;
605 default:
606 return -EINVAL;
607 }
608 spacemit_set_io_pwr_domain(pctrl, spin, type);
609 }
610
611 val = spacemit_get_driver_strength(type, dconf, drv_strength);
612
613 v &= ~dconf->drive_mask;
614 v |= (val << __ffs(dconf->drive_mask)) & dconf->drive_mask;
615 }
616
617 if (flag & ENABLE_SLEW_RATE) {
618 /* check, driver strength & slew rate */
619 if (flag & ENABLE_DRV_STRENGTH) {
620 val = FIELD_GET(PAD_SLEW_RATE, v) + 2;
621 if (slew_rate > 1 && slew_rate != val) {
622 pr_err("slew rate conflict with drive strength\n");
623 return -EINVAL;
624 }
625 } else {
626 slew_rate = slew_rate > 1 ? (slew_rate - 2) : 0;
627 FIELD_MODIFY(PAD_SLEW_RATE, &v, slew_rate);
628 }
629 }
630
631 *value = v;
632
633 return 0;
634 }
635
spacemit_pin_set_config(struct spacemit_pinctrl * pctrl,unsigned int pin,u32 value)636 static int spacemit_pin_set_config(struct spacemit_pinctrl *pctrl,
637 unsigned int pin, u32 value)
638 {
639 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
640 void __iomem *reg;
641 unsigned int mux;
642
643 if (!spin)
644 return -EINVAL;
645
646 reg = spacemit_pin_to_reg(pctrl, spin->pin);
647
648 guard(raw_spinlock_irqsave)(&pctrl->lock);
649 mux = readl_relaxed(reg) & PAD_MUX;
650 writel_relaxed(mux | value, reg);
651
652 return 0;
653 }
654
spacemit_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)655 static int spacemit_pinconf_set(struct pinctrl_dev *pctldev,
656 unsigned int pin, unsigned long *configs,
657 unsigned int num_configs)
658 {
659 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
660 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
661 u32 value;
662 int ret;
663
664 ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf,
665 configs, num_configs, &value);
666 if (ret)
667 return ret;
668
669 return spacemit_pin_set_config(pctrl, pin, value);
670 }
671
spacemit_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int gsel,unsigned long * configs,unsigned int num_configs)672 static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev,
673 unsigned int gsel,
674 unsigned long *configs,
675 unsigned int num_configs)
676 {
677 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
678 const struct spacemit_pin *spin;
679 const struct group_desc *group;
680 u32 value;
681 int i, ret;
682
683 group = pinctrl_generic_get_group(pctldev, gsel);
684 if (!group)
685 return -EINVAL;
686
687 spin = spacemit_get_pin(pctrl, group->grp.pins[0]);
688 ret = spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf,
689 configs, num_configs, &value);
690 if (ret)
691 return ret;
692
693 for (i = 0; i < group->grp.npins; i++) {
694 if (!spacemit_get_pin(pctrl, group->grp.pins[i]))
695 return -EINVAL;
696 }
697
698 for (i = 0; i < group->grp.npins; i++)
699 spacemit_pin_set_config(pctrl, group->grp.pins[i], value);
700
701 return 0;
702 }
703
spacemit_pinconf_dbg_pull(struct seq_file * seq,unsigned int value)704 static void spacemit_pinconf_dbg_pull(struct seq_file *seq, unsigned int value)
705 {
706 u32 normal, strong;
707
708 if (!FIELD_GET(PAD_PULL_EN, value)) {
709 seq_puts(seq, ", bias pull disabled");
710 return;
711 }
712
713 if (FIELD_GET(PAD_PULLDOWN, value))
714 seq_puts(seq, ", bias pull down");
715
716 normal = FIELD_GET(PAD_PULLUP, value);
717 strong = FIELD_GET(PAD_STRONG_PULL, value);
718
719 if (normal && strong)
720 seq_puts(seq, ", bias strong pull up");
721 else if (normal)
722 seq_puts(seq, ", bias normal pull up");
723 }
724
spacemit_pinconf_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * seq,unsigned int pin)725 static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev,
726 struct seq_file *seq, unsigned int pin)
727 {
728 struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
729 const struct spacemit_pinctrl_dconf *dconf = pctrl->data->dconf;
730 const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
731 enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin);
732 void __iomem *reg = spacemit_pin_to_reg(pctrl, pin);
733 u32 value, tmp, mA;
734
735 value = readl(reg);
736 spacemit_pinconf_dbg_pull(seq, value);
737
738 seq_printf(seq, ", io type (%s)", io_type_desc[type]);
739
740 tmp = (value & dconf->drive_mask) >> __ffs(dconf->drive_mask);
741 if (type == IO_TYPE_1V8 || type == IO_TYPE_3V3) {
742 mA = spacemit_get_drive_strength_mA(type, dconf, tmp);
743 seq_printf(seq, ", drive strength (%d mA)", mA);
744 }
745
746 /* drive strength depend on power source, so show all values */
747 if (type == IO_TYPE_EXTERNAL)
748 seq_printf(seq, ", drive strength (%d or %d mA)",
749 spacemit_get_drive_strength_mA(IO_TYPE_1V8, dconf, tmp),
750 spacemit_get_drive_strength_mA(IO_TYPE_3V3, dconf, tmp));
751
752 seq_printf(seq, ", register (0x%04x)", value);
753 }
754
755 static const struct pinconf_ops spacemit_pinconf_ops = {
756 .pin_config_get = spacemit_pinconf_get,
757 .pin_config_set = spacemit_pinconf_set,
758 .pin_config_group_set = spacemit_pinconf_group_set,
759 .pin_config_dbg_show = spacemit_pinconf_dbg_show,
760 .is_generic = true,
761 };
762
spacemit_pinctrl_probe(struct platform_device * pdev)763 static int spacemit_pinctrl_probe(struct platform_device *pdev)
764 {
765 struct device_node *np = pdev->dev.of_node;
766 struct device *dev = &pdev->dev;
767 struct spacemit_pinctrl *pctrl;
768 struct clk *func_clk, *bus_clk;
769 const struct spacemit_pinctrl_data *pctrl_data;
770 int ret;
771
772 pctrl_data = device_get_match_data(dev);
773 if (!pctrl_data)
774 return -ENODEV;
775
776 if (pctrl_data->npins == 0)
777 return dev_err_probe(dev, -EINVAL, "invalid pin data\n");
778
779 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
780 if (!pctrl)
781 return -ENOMEM;
782
783 pctrl->regs = devm_platform_ioremap_resource(pdev, 0);
784 if (IS_ERR(pctrl->regs))
785 return PTR_ERR(pctrl->regs);
786
787 pctrl->regmap_apbc = syscon_regmap_lookup_by_phandle(np, "spacemit,apbc");
788 if (IS_ERR(pctrl->regmap_apbc)) {
789 dev_warn(dev, "no syscon found, disable power voltage switch functionality\n");
790 pctrl->regmap_apbc = NULL;
791 }
792
793 func_clk = devm_clk_get_enabled(dev, "func");
794 if (IS_ERR(func_clk))
795 return dev_err_probe(dev, PTR_ERR(func_clk), "failed to get func clock\n");
796
797 bus_clk = devm_clk_get_enabled(dev, "bus");
798 if (IS_ERR(bus_clk))
799 return dev_err_probe(dev, PTR_ERR(bus_clk), "failed to get bus clock\n");
800
801 pctrl->pdesc.name = dev_name(dev);
802 pctrl->pdesc.pins = pctrl_data->pins;
803 pctrl->pdesc.npins = pctrl_data->npins;
804 pctrl->pdesc.pctlops = &spacemit_pctrl_ops;
805 pctrl->pdesc.pmxops = &spacemit_pmx_ops;
806 pctrl->pdesc.confops = &spacemit_pinconf_ops;
807 pctrl->pdesc.owner = THIS_MODULE;
808
809 pctrl->data = pctrl_data;
810 pctrl->dev = dev;
811 raw_spin_lock_init(&pctrl->lock);
812
813 ret = devm_mutex_init(dev, &pctrl->mutex);
814 if (ret)
815 return ret;
816
817 platform_set_drvdata(pdev, pctrl);
818
819 ret = devm_pinctrl_register_and_init(dev, &pctrl->pdesc,
820 pctrl, &pctrl->pctl_dev);
821 if (ret)
822 return dev_err_probe(dev, ret,
823 "fail to register pinctrl driver\n");
824
825 return pinctrl_enable(pctrl->pctl_dev);
826 }
827
828 static const struct pinctrl_pin_desc k1_pin_desc[] = {
829 PINCTRL_PIN(0, "GPIO_00"),
830 PINCTRL_PIN(1, "GPIO_01"),
831 PINCTRL_PIN(2, "GPIO_02"),
832 PINCTRL_PIN(3, "GPIO_03"),
833 PINCTRL_PIN(4, "GPIO_04"),
834 PINCTRL_PIN(5, "GPIO_05"),
835 PINCTRL_PIN(6, "GPIO_06"),
836 PINCTRL_PIN(7, "GPIO_07"),
837 PINCTRL_PIN(8, "GPIO_08"),
838 PINCTRL_PIN(9, "GPIO_09"),
839 PINCTRL_PIN(10, "GPIO_10"),
840 PINCTRL_PIN(11, "GPIO_11"),
841 PINCTRL_PIN(12, "GPIO_12"),
842 PINCTRL_PIN(13, "GPIO_13"),
843 PINCTRL_PIN(14, "GPIO_14"),
844 PINCTRL_PIN(15, "GPIO_15"),
845 PINCTRL_PIN(16, "GPIO_16"),
846 PINCTRL_PIN(17, "GPIO_17"),
847 PINCTRL_PIN(18, "GPIO_18"),
848 PINCTRL_PIN(19, "GPIO_19"),
849 PINCTRL_PIN(20, "GPIO_20"),
850 PINCTRL_PIN(21, "GPIO_21"),
851 PINCTRL_PIN(22, "GPIO_22"),
852 PINCTRL_PIN(23, "GPIO_23"),
853 PINCTRL_PIN(24, "GPIO_24"),
854 PINCTRL_PIN(25, "GPIO_25"),
855 PINCTRL_PIN(26, "GPIO_26"),
856 PINCTRL_PIN(27, "GPIO_27"),
857 PINCTRL_PIN(28, "GPIO_28"),
858 PINCTRL_PIN(29, "GPIO_29"),
859 PINCTRL_PIN(30, "GPIO_30"),
860 PINCTRL_PIN(31, "GPIO_31"),
861 PINCTRL_PIN(32, "GPIO_32"),
862 PINCTRL_PIN(33, "GPIO_33"),
863 PINCTRL_PIN(34, "GPIO_34"),
864 PINCTRL_PIN(35, "GPIO_35"),
865 PINCTRL_PIN(36, "GPIO_36"),
866 PINCTRL_PIN(37, "GPIO_37"),
867 PINCTRL_PIN(38, "GPIO_38"),
868 PINCTRL_PIN(39, "GPIO_39"),
869 PINCTRL_PIN(40, "GPIO_40"),
870 PINCTRL_PIN(41, "GPIO_41"),
871 PINCTRL_PIN(42, "GPIO_42"),
872 PINCTRL_PIN(43, "GPIO_43"),
873 PINCTRL_PIN(44, "GPIO_44"),
874 PINCTRL_PIN(45, "GPIO_45"),
875 PINCTRL_PIN(46, "GPIO_46"),
876 PINCTRL_PIN(47, "GPIO_47"),
877 PINCTRL_PIN(48, "GPIO_48"),
878 PINCTRL_PIN(49, "GPIO_49"),
879 PINCTRL_PIN(50, "GPIO_50"),
880 PINCTRL_PIN(51, "GPIO_51"),
881 PINCTRL_PIN(52, "GPIO_52"),
882 PINCTRL_PIN(53, "GPIO_53"),
883 PINCTRL_PIN(54, "GPIO_54"),
884 PINCTRL_PIN(55, "GPIO_55"),
885 PINCTRL_PIN(56, "GPIO_56"),
886 PINCTRL_PIN(57, "GPIO_57"),
887 PINCTRL_PIN(58, "GPIO_58"),
888 PINCTRL_PIN(59, "GPIO_59"),
889 PINCTRL_PIN(60, "GPIO_60"),
890 PINCTRL_PIN(61, "GPIO_61"),
891 PINCTRL_PIN(62, "GPIO_62"),
892 PINCTRL_PIN(63, "GPIO_63"),
893 PINCTRL_PIN(64, "GPIO_64"),
894 PINCTRL_PIN(65, "GPIO_65"),
895 PINCTRL_PIN(66, "GPIO_66"),
896 PINCTRL_PIN(67, "GPIO_67"),
897 PINCTRL_PIN(68, "GPIO_68"),
898 PINCTRL_PIN(69, "GPIO_69"),
899 PINCTRL_PIN(70, "GPIO_70/PRI_TDI"),
900 PINCTRL_PIN(71, "GPIO_71/PRI_TMS"),
901 PINCTRL_PIN(72, "GPIO_72/PRI_TCK"),
902 PINCTRL_PIN(73, "GPIO_73/PRI_TDO"),
903 PINCTRL_PIN(74, "GPIO_74"),
904 PINCTRL_PIN(75, "GPIO_75"),
905 PINCTRL_PIN(76, "GPIO_76"),
906 PINCTRL_PIN(77, "GPIO_77"),
907 PINCTRL_PIN(78, "GPIO_78"),
908 PINCTRL_PIN(79, "GPIO_79"),
909 PINCTRL_PIN(80, "GPIO_80"),
910 PINCTRL_PIN(81, "GPIO_81"),
911 PINCTRL_PIN(82, "GPIO_82"),
912 PINCTRL_PIN(83, "GPIO_83"),
913 PINCTRL_PIN(84, "GPIO_84"),
914 PINCTRL_PIN(85, "GPIO_85"),
915 PINCTRL_PIN(86, "GPIO_86"),
916 PINCTRL_PIN(87, "GPIO_87"),
917 PINCTRL_PIN(88, "GPIO_88"),
918 PINCTRL_PIN(89, "GPIO_89"),
919 PINCTRL_PIN(90, "GPIO_90"),
920 PINCTRL_PIN(91, "GPIO_91"),
921 PINCTRL_PIN(92, "GPIO_92"),
922 PINCTRL_PIN(93, "GPIO_93/PWR_SCL"),
923 PINCTRL_PIN(94, "GPIO_94/PWR_SDA"),
924 PINCTRL_PIN(95, "GPIO_95/VCX0_EN"),
925 PINCTRL_PIN(96, "GPIO_96/DVL0"),
926 PINCTRL_PIN(97, "GPIO_97/DVL1"),
927 PINCTRL_PIN(98, "GPIO_98/QSPI_DAT3"),
928 PINCTRL_PIN(99, "GPIO_99/QSPI_DAT2"),
929 PINCTRL_PIN(100, "GPIO_100/QSPI_DAT1"),
930 PINCTRL_PIN(101, "GPIO_101/QSPI_DAT0"),
931 PINCTRL_PIN(102, "GPIO_102/QSPI_CLK"),
932 PINCTRL_PIN(103, "GPIO_103/QSPI_CS1"),
933 PINCTRL_PIN(104, "GPIO_104/MMC1_DAT3"),
934 PINCTRL_PIN(105, "GPIO_105/MMC1_DAT2"),
935 PINCTRL_PIN(106, "GPIO_106/MMC1_DAT1"),
936 PINCTRL_PIN(107, "GPIO_107/MMC1_DAT0"),
937 PINCTRL_PIN(108, "GPIO_108/MMC1_CMD"),
938 PINCTRL_PIN(109, "GPIO_109/MMC1_CLK"),
939 PINCTRL_PIN(110, "GPIO_110"),
940 PINCTRL_PIN(111, "GPIO_111"),
941 PINCTRL_PIN(112, "GPIO_112"),
942 PINCTRL_PIN(113, "GPIO_113"),
943 PINCTRL_PIN(114, "GPIO_114"),
944 PINCTRL_PIN(115, "GPIO_115"),
945 PINCTRL_PIN(116, "GPIO_116"),
946 PINCTRL_PIN(117, "GPIO_117"),
947 PINCTRL_PIN(118, "GPIO_118"),
948 PINCTRL_PIN(119, "GPIO_119"),
949 PINCTRL_PIN(120, "GPIO_120"),
950 PINCTRL_PIN(121, "GPIO_121"),
951 PINCTRL_PIN(122, "GPIO_122"),
952 PINCTRL_PIN(123, "GPIO_123"),
953 PINCTRL_PIN(124, "GPIO_124"),
954 PINCTRL_PIN(125, "GPIO_125"),
955 PINCTRL_PIN(126, "GPIO_126"),
956 PINCTRL_PIN(127, "GPIO_127"),
957 };
958
959 static const struct spacemit_pin k1_pin_data[ARRAY_SIZE(k1_pin_desc)] = {
960 K1_FUNC_PIN(0, 0, IO_TYPE_1V8),
961 K1_FUNC_PIN(1, 0, IO_TYPE_1V8),
962 K1_FUNC_PIN(2, 0, IO_TYPE_1V8),
963 K1_FUNC_PIN(3, 0, IO_TYPE_1V8),
964 K1_FUNC_PIN(4, 0, IO_TYPE_1V8),
965 K1_FUNC_PIN(5, 0, IO_TYPE_1V8),
966 K1_FUNC_PIN(6, 0, IO_TYPE_1V8),
967 K1_FUNC_PIN(7, 0, IO_TYPE_1V8),
968 K1_FUNC_PIN(8, 0, IO_TYPE_1V8),
969 K1_FUNC_PIN(9, 0, IO_TYPE_1V8),
970 K1_FUNC_PIN(10, 0, IO_TYPE_1V8),
971 K1_FUNC_PIN(11, 0, IO_TYPE_1V8),
972 K1_FUNC_PIN(12, 0, IO_TYPE_1V8),
973 K1_FUNC_PIN(13, 0, IO_TYPE_1V8),
974 K1_FUNC_PIN(14, 0, IO_TYPE_1V8),
975 K1_FUNC_PIN(15, 0, IO_TYPE_1V8),
976 K1_FUNC_PIN(16, 0, IO_TYPE_1V8),
977 K1_FUNC_PIN(17, 0, IO_TYPE_1V8),
978 K1_FUNC_PIN(18, 0, IO_TYPE_1V8),
979 K1_FUNC_PIN(19, 0, IO_TYPE_1V8),
980 K1_FUNC_PIN(20, 0, IO_TYPE_1V8),
981 K1_FUNC_PIN(21, 0, IO_TYPE_1V8),
982 K1_FUNC_PIN(22, 0, IO_TYPE_1V8),
983 K1_FUNC_PIN(23, 0, IO_TYPE_1V8),
984 K1_FUNC_PIN(24, 0, IO_TYPE_1V8),
985 K1_FUNC_PIN(25, 0, IO_TYPE_1V8),
986 K1_FUNC_PIN(26, 0, IO_TYPE_1V8),
987 K1_FUNC_PIN(27, 0, IO_TYPE_1V8),
988 K1_FUNC_PIN(28, 0, IO_TYPE_1V8),
989 K1_FUNC_PIN(29, 0, IO_TYPE_1V8),
990 K1_FUNC_PIN(30, 0, IO_TYPE_1V8),
991 K1_FUNC_PIN(31, 0, IO_TYPE_1V8),
992 K1_FUNC_PIN(32, 0, IO_TYPE_1V8),
993 K1_FUNC_PIN(33, 0, IO_TYPE_1V8),
994 K1_FUNC_PIN(34, 0, IO_TYPE_1V8),
995 K1_FUNC_PIN(35, 0, IO_TYPE_1V8),
996 K1_FUNC_PIN(36, 0, IO_TYPE_1V8),
997 K1_FUNC_PIN(37, 0, IO_TYPE_1V8),
998 K1_FUNC_PIN(38, 0, IO_TYPE_1V8),
999 K1_FUNC_PIN(39, 0, IO_TYPE_1V8),
1000 K1_FUNC_PIN(40, 0, IO_TYPE_1V8),
1001 K1_FUNC_PIN(41, 0, IO_TYPE_1V8),
1002 K1_FUNC_PIN(42, 0, IO_TYPE_1V8),
1003 K1_FUNC_PIN(43, 0, IO_TYPE_1V8),
1004 K1_FUNC_PIN(44, 0, IO_TYPE_1V8),
1005 K1_FUNC_PIN(45, 0, IO_TYPE_1V8),
1006 K1_FUNC_PIN(46, 0, IO_TYPE_1V8),
1007 K1_FUNC_PIN(47, 0, IO_TYPE_EXTERNAL),
1008 K1_FUNC_PIN(48, 0, IO_TYPE_EXTERNAL),
1009 K1_FUNC_PIN(49, 0, IO_TYPE_EXTERNAL),
1010 K1_FUNC_PIN(50, 0, IO_TYPE_EXTERNAL),
1011 K1_FUNC_PIN(51, 0, IO_TYPE_EXTERNAL),
1012 K1_FUNC_PIN(52, 0, IO_TYPE_EXTERNAL),
1013 K1_FUNC_PIN(53, 0, IO_TYPE_1V8),
1014 K1_FUNC_PIN(54, 0, IO_TYPE_1V8),
1015 K1_FUNC_PIN(55, 0, IO_TYPE_1V8),
1016 K1_FUNC_PIN(56, 0, IO_TYPE_1V8),
1017 K1_FUNC_PIN(57, 0, IO_TYPE_1V8),
1018 K1_FUNC_PIN(58, 0, IO_TYPE_1V8),
1019 K1_FUNC_PIN(59, 0, IO_TYPE_1V8),
1020 K1_FUNC_PIN(60, 0, IO_TYPE_1V8),
1021 K1_FUNC_PIN(61, 0, IO_TYPE_1V8),
1022 K1_FUNC_PIN(62, 0, IO_TYPE_1V8),
1023 K1_FUNC_PIN(63, 0, IO_TYPE_1V8),
1024 K1_FUNC_PIN(64, 0, IO_TYPE_1V8),
1025 K1_FUNC_PIN(65, 0, IO_TYPE_1V8),
1026 K1_FUNC_PIN(66, 0, IO_TYPE_1V8),
1027 K1_FUNC_PIN(67, 0, IO_TYPE_1V8),
1028 K1_FUNC_PIN(68, 0, IO_TYPE_1V8),
1029 K1_FUNC_PIN(69, 0, IO_TYPE_1V8),
1030 K1_FUNC_PIN(70, 1, IO_TYPE_1V8),
1031 K1_FUNC_PIN(71, 1, IO_TYPE_1V8),
1032 K1_FUNC_PIN(72, 1, IO_TYPE_1V8),
1033 K1_FUNC_PIN(73, 1, IO_TYPE_1V8),
1034 K1_FUNC_PIN(74, 0, IO_TYPE_1V8),
1035 K1_FUNC_PIN(75, 0, IO_TYPE_EXTERNAL),
1036 K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL),
1037 K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL),
1038 K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL),
1039 K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL),
1040 K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL),
1041 K1_FUNC_PIN(81, 0, IO_TYPE_1V8),
1042 K1_FUNC_PIN(82, 0, IO_TYPE_1V8),
1043 K1_FUNC_PIN(83, 0, IO_TYPE_1V8),
1044 K1_FUNC_PIN(84, 0, IO_TYPE_1V8),
1045 K1_FUNC_PIN(85, 0, IO_TYPE_1V8),
1046 K1_FUNC_PIN(86, 0, IO_TYPE_1V8),
1047 K1_FUNC_PIN(87, 0, IO_TYPE_1V8),
1048 K1_FUNC_PIN(88, 0, IO_TYPE_1V8),
1049 K1_FUNC_PIN(89, 0, IO_TYPE_1V8),
1050 K1_FUNC_PIN(90, 0, IO_TYPE_1V8),
1051 K1_FUNC_PIN(91, 0, IO_TYPE_1V8),
1052 K1_FUNC_PIN(92, 0, IO_TYPE_1V8),
1053 K1_FUNC_PIN(93, 1, IO_TYPE_1V8),
1054 K1_FUNC_PIN(94, 1, IO_TYPE_1V8),
1055 K1_FUNC_PIN(95, 1, IO_TYPE_1V8),
1056 K1_FUNC_PIN(96, 1, IO_TYPE_1V8),
1057 K1_FUNC_PIN(97, 1, IO_TYPE_1V8),
1058 K1_FUNC_PIN(98, 1, IO_TYPE_EXTERNAL),
1059 K1_FUNC_PIN(99, 1, IO_TYPE_EXTERNAL),
1060 K1_FUNC_PIN(100, 1, IO_TYPE_EXTERNAL),
1061 K1_FUNC_PIN(101, 1, IO_TYPE_EXTERNAL),
1062 K1_FUNC_PIN(102, 1, IO_TYPE_EXTERNAL),
1063 K1_FUNC_PIN(103, 1, IO_TYPE_EXTERNAL),
1064 K1_FUNC_PIN(104, 4, IO_TYPE_EXTERNAL),
1065 K1_FUNC_PIN(105, 4, IO_TYPE_EXTERNAL),
1066 K1_FUNC_PIN(106, 4, IO_TYPE_EXTERNAL),
1067 K1_FUNC_PIN(107, 4, IO_TYPE_EXTERNAL),
1068 K1_FUNC_PIN(108, 4, IO_TYPE_EXTERNAL),
1069 K1_FUNC_PIN(109, 4, IO_TYPE_EXTERNAL),
1070 K1_FUNC_PIN(110, 0, IO_TYPE_1V8),
1071 K1_FUNC_PIN(111, 0, IO_TYPE_1V8),
1072 K1_FUNC_PIN(112, 0, IO_TYPE_1V8),
1073 K1_FUNC_PIN(113, 0, IO_TYPE_1V8),
1074 K1_FUNC_PIN(114, 0, IO_TYPE_1V8),
1075 K1_FUNC_PIN(115, 0, IO_TYPE_1V8),
1076 K1_FUNC_PIN(116, 0, IO_TYPE_1V8),
1077 K1_FUNC_PIN(117, 0, IO_TYPE_1V8),
1078 K1_FUNC_PIN(118, 0, IO_TYPE_1V8),
1079 K1_FUNC_PIN(119, 0, IO_TYPE_1V8),
1080 K1_FUNC_PIN(120, 0, IO_TYPE_1V8),
1081 K1_FUNC_PIN(121, 0, IO_TYPE_1V8),
1082 K1_FUNC_PIN(122, 0, IO_TYPE_1V8),
1083 K1_FUNC_PIN(123, 0, IO_TYPE_1V8),
1084 K1_FUNC_PIN(124, 0, IO_TYPE_1V8),
1085 K1_FUNC_PIN(125, 0, IO_TYPE_1V8),
1086 K1_FUNC_PIN(126, 0, IO_TYPE_1V8),
1087 K1_FUNC_PIN(127, 0, IO_TYPE_1V8),
1088 };
1089
1090 static const struct spacemit_pinctrl_data k1_pinctrl_data = {
1091 .pins = k1_pin_desc,
1092 .data = k1_pin_data,
1093 .npins = ARRAY_SIZE(k1_pin_desc),
1094 .pin_to_offset = spacemit_k1_pin_to_offset,
1095 .pin_to_io_pd_offset = spacemit_k1_pin_to_io_pd_offset,
1096 .dconf = &k1_drive_conf,
1097 };
1098
1099 static const struct pinctrl_pin_desc k3_pin_desc[] = {
1100 PINCTRL_PIN(0, "GPIO_00"),
1101 PINCTRL_PIN(1, "GPIO_01"),
1102 PINCTRL_PIN(2, "GPIO_02"),
1103 PINCTRL_PIN(3, "GPIO_03"),
1104 PINCTRL_PIN(4, "GPIO_04"),
1105 PINCTRL_PIN(5, "GPIO_05"),
1106 PINCTRL_PIN(6, "GPIO_06"),
1107 PINCTRL_PIN(7, "GPIO_07"),
1108 PINCTRL_PIN(8, "GPIO_08"),
1109 PINCTRL_PIN(9, "GPIO_09"),
1110 PINCTRL_PIN(10, "GPIO_10"),
1111 PINCTRL_PIN(11, "GPIO_11"),
1112 PINCTRL_PIN(12, "GPIO_12"),
1113 PINCTRL_PIN(13, "GPIO_13"),
1114 PINCTRL_PIN(14, "GPIO_14"),
1115 PINCTRL_PIN(15, "GPIO_15"),
1116 PINCTRL_PIN(16, "GPIO_16"),
1117 PINCTRL_PIN(17, "GPIO_17"),
1118 PINCTRL_PIN(18, "GPIO_18"),
1119 PINCTRL_PIN(19, "GPIO_19"),
1120 PINCTRL_PIN(20, "GPIO_20"),
1121 PINCTRL_PIN(21, "GPIO_21"),
1122 PINCTRL_PIN(22, "GPIO_22"),
1123 PINCTRL_PIN(23, "GPIO_23"),
1124 PINCTRL_PIN(24, "GPIO_24"),
1125 PINCTRL_PIN(25, "GPIO_25"),
1126 PINCTRL_PIN(26, "GPIO_26"),
1127 PINCTRL_PIN(27, "GPIO_27"),
1128 PINCTRL_PIN(28, "GPIO_28"),
1129 PINCTRL_PIN(29, "GPIO_29"),
1130 PINCTRL_PIN(30, "GPIO_30"),
1131 PINCTRL_PIN(31, "GPIO_31"),
1132 PINCTRL_PIN(32, "GPIO_32"),
1133 PINCTRL_PIN(33, "GPIO_33"),
1134 PINCTRL_PIN(34, "GPIO_34"),
1135 PINCTRL_PIN(35, "GPIO_35"),
1136 PINCTRL_PIN(36, "GPIO_36"),
1137 PINCTRL_PIN(37, "GPIO_37"),
1138 PINCTRL_PIN(38, "GPIO_38"),
1139 PINCTRL_PIN(39, "GPIO_39"),
1140 PINCTRL_PIN(40, "GPIO_40"),
1141 PINCTRL_PIN(41, "GPIO_41"),
1142 PINCTRL_PIN(42, "GPIO_42"),
1143 PINCTRL_PIN(43, "GPIO_43"),
1144 PINCTRL_PIN(44, "GPIO_44"),
1145 PINCTRL_PIN(45, "GPIO_45"),
1146 PINCTRL_PIN(46, "GPIO_46"),
1147 PINCTRL_PIN(47, "GPIO_47"),
1148 PINCTRL_PIN(48, "GPIO_48"),
1149 PINCTRL_PIN(49, "GPIO_49"),
1150 PINCTRL_PIN(50, "GPIO_50"),
1151 PINCTRL_PIN(51, "GPIO_51"),
1152 PINCTRL_PIN(52, "GPIO_52"),
1153 PINCTRL_PIN(53, "GPIO_53"),
1154 PINCTRL_PIN(54, "GPIO_54"),
1155 PINCTRL_PIN(55, "GPIO_55"),
1156 PINCTRL_PIN(56, "GPIO_56"),
1157 PINCTRL_PIN(57, "GPIO_57"),
1158 PINCTRL_PIN(58, "GPIO_58"),
1159 PINCTRL_PIN(59, "GPIO_59"),
1160 PINCTRL_PIN(60, "GPIO_60"),
1161 PINCTRL_PIN(61, "GPIO_61"),
1162 PINCTRL_PIN(62, "GPIO_62"),
1163 PINCTRL_PIN(63, "GPIO_63"),
1164 PINCTRL_PIN(64, "GPIO_64"),
1165 PINCTRL_PIN(65, "GPIO_65"),
1166 PINCTRL_PIN(66, "GPIO_66"),
1167 PINCTRL_PIN(67, "GPIO_67"),
1168 PINCTRL_PIN(68, "GPIO_68"),
1169 PINCTRL_PIN(69, "GPIO_69"),
1170 PINCTRL_PIN(70, "GPIO_70"),
1171 PINCTRL_PIN(71, "GPIO_71"),
1172 PINCTRL_PIN(72, "GPIO_72"),
1173 PINCTRL_PIN(73, "GPIO_73"),
1174 PINCTRL_PIN(74, "GPIO_74"),
1175 PINCTRL_PIN(75, "GPIO_75"),
1176 PINCTRL_PIN(76, "GPIO_76"),
1177 PINCTRL_PIN(77, "GPIO_77"),
1178 PINCTRL_PIN(78, "GPIO_78"),
1179 PINCTRL_PIN(79, "GPIO_79"),
1180 PINCTRL_PIN(80, "GPIO_80"),
1181 PINCTRL_PIN(81, "GPIO_81"),
1182 PINCTRL_PIN(82, "GPIO_82"),
1183 PINCTRL_PIN(83, "GPIO_83"),
1184 PINCTRL_PIN(84, "GPIO_84"),
1185 PINCTRL_PIN(85, "GPIO_85"),
1186 PINCTRL_PIN(86, "GPIO_86"),
1187 PINCTRL_PIN(87, "GPIO_87"),
1188 PINCTRL_PIN(88, "GPIO_88"),
1189 PINCTRL_PIN(89, "GPIO_89"),
1190 PINCTRL_PIN(90, "GPIO_90"),
1191 PINCTRL_PIN(91, "GPIO_91"),
1192 PINCTRL_PIN(92, "GPIO_92"),
1193 PINCTRL_PIN(93, "GPIO_93"),
1194 PINCTRL_PIN(94, "GPIO_94"),
1195 PINCTRL_PIN(95, "GPIO_95"),
1196 PINCTRL_PIN(96, "GPIO_96"),
1197 PINCTRL_PIN(97, "GPIO_97"),
1198 PINCTRL_PIN(98, "GPIO_98"),
1199 PINCTRL_PIN(99, "GPIO_99"),
1200 PINCTRL_PIN(100, "GPIO_100"),
1201 PINCTRL_PIN(101, "GPIO_101"),
1202 PINCTRL_PIN(102, "GPIO_102"),
1203 PINCTRL_PIN(103, "GPIO_103"),
1204 PINCTRL_PIN(104, "GPIO_104"),
1205 PINCTRL_PIN(105, "GPIO_105"),
1206 PINCTRL_PIN(106, "GPIO_106"),
1207 PINCTRL_PIN(107, "GPIO_107"),
1208 PINCTRL_PIN(108, "GPIO_108"),
1209 PINCTRL_PIN(109, "GPIO_109"),
1210 PINCTRL_PIN(110, "GPIO_110"),
1211 PINCTRL_PIN(111, "GPIO_111"),
1212 PINCTRL_PIN(112, "GPIO_112"),
1213 PINCTRL_PIN(113, "GPIO_113"),
1214 PINCTRL_PIN(114, "GPIO_114"),
1215 PINCTRL_PIN(115, "GPIO_115"),
1216 PINCTRL_PIN(116, "GPIO_116"),
1217 PINCTRL_PIN(117, "GPIO_117"),
1218 PINCTRL_PIN(118, "GPIO_118"),
1219 PINCTRL_PIN(119, "GPIO_119"),
1220 PINCTRL_PIN(120, "GPIO_120"),
1221 PINCTRL_PIN(121, "GPIO_121"),
1222 PINCTRL_PIN(122, "GPIO_122"),
1223 PINCTRL_PIN(123, "GPIO_123"),
1224 PINCTRL_PIN(124, "GPIO_124"),
1225 PINCTRL_PIN(125, "GPIO_125"),
1226 PINCTRL_PIN(126, "GPIO_126"),
1227 PINCTRL_PIN(127, "GPIO_127"),
1228 PINCTRL_PIN(128, "PWR_SCL"),
1229 PINCTRL_PIN(129, "PWR_SDA"),
1230 PINCTRL_PIN(130, "VCXO_EN"),
1231 PINCTRL_PIN(131, "PMIC_INT_N"),
1232 PINCTRL_PIN(132, "MMC1_DAT3"),
1233 PINCTRL_PIN(133, "MMC1_DAT2"),
1234 PINCTRL_PIN(134, "MMC1_DAT1"),
1235 PINCTRL_PIN(135, "MMC1_DAT0"),
1236 PINCTRL_PIN(136, "MMC1_CMD"),
1237 PINCTRL_PIN(137, "MMC1_CLK"),
1238 PINCTRL_PIN(138, "QSPI_DAT0"),
1239 PINCTRL_PIN(139, "QSPI_DAT1"),
1240 PINCTRL_PIN(140, "QSPI_DAT2"),
1241 PINCTRL_PIN(141, "QSPI_DAT3"),
1242 PINCTRL_PIN(142, "QSPI_CS0"),
1243 PINCTRL_PIN(143, "QSPI_CS1"),
1244 PINCTRL_PIN(144, "QSPI_CLK"),
1245 PINCTRL_PIN(145, "PRI_TDI"),
1246 PINCTRL_PIN(146, "PRI_TMS"),
1247 PINCTRL_PIN(147, "PRI_TCK"),
1248 PINCTRL_PIN(148, "PRI_TDO"),
1249 PINCTRL_PIN(149, "PWR_SSP_SCLK"),
1250 PINCTRL_PIN(150, "PWR_SSP_FRM"),
1251 PINCTRL_PIN(151, "PWR_SSP_TXD"),
1252 PINCTRL_PIN(152, "PWR_SSP_RXD"),
1253 };
1254
1255 static const struct spacemit_pin k3_pin_data[ARRAY_SIZE(k3_pin_desc)] = {
1256 /* GPIO1 bank */
1257 K1_FUNC_PIN(0, 0, IO_TYPE_EXTERNAL),
1258 K1_FUNC_PIN(1, 0, IO_TYPE_EXTERNAL),
1259 K1_FUNC_PIN(2, 0, IO_TYPE_EXTERNAL),
1260 K1_FUNC_PIN(3, 0, IO_TYPE_EXTERNAL),
1261 K1_FUNC_PIN(4, 0, IO_TYPE_EXTERNAL),
1262 K1_FUNC_PIN(5, 0, IO_TYPE_EXTERNAL),
1263 K1_FUNC_PIN(6, 0, IO_TYPE_EXTERNAL),
1264 K1_FUNC_PIN(7, 0, IO_TYPE_EXTERNAL),
1265 K1_FUNC_PIN(8, 0, IO_TYPE_EXTERNAL),
1266 K1_FUNC_PIN(9, 0, IO_TYPE_EXTERNAL),
1267 K1_FUNC_PIN(10, 0, IO_TYPE_EXTERNAL),
1268 K1_FUNC_PIN(11, 0, IO_TYPE_EXTERNAL),
1269 K1_FUNC_PIN(12, 0, IO_TYPE_EXTERNAL),
1270 K1_FUNC_PIN(13, 0, IO_TYPE_EXTERNAL),
1271 K1_FUNC_PIN(14, 0, IO_TYPE_EXTERNAL),
1272 K1_FUNC_PIN(15, 0, IO_TYPE_EXTERNAL),
1273 K1_FUNC_PIN(16, 0, IO_TYPE_EXTERNAL),
1274 K1_FUNC_PIN(17, 0, IO_TYPE_EXTERNAL),
1275 K1_FUNC_PIN(18, 0, IO_TYPE_EXTERNAL),
1276 K1_FUNC_PIN(19, 0, IO_TYPE_EXTERNAL),
1277 K1_FUNC_PIN(20, 0, IO_TYPE_EXTERNAL),
1278
1279 /* GPIO2 bank */
1280 K1_FUNC_PIN(21, 0, IO_TYPE_EXTERNAL),
1281 K1_FUNC_PIN(22, 0, IO_TYPE_EXTERNAL),
1282 K1_FUNC_PIN(23, 0, IO_TYPE_EXTERNAL),
1283 K1_FUNC_PIN(24, 0, IO_TYPE_EXTERNAL),
1284 K1_FUNC_PIN(25, 0, IO_TYPE_EXTERNAL),
1285 K1_FUNC_PIN(26, 0, IO_TYPE_EXTERNAL),
1286 K1_FUNC_PIN(27, 0, IO_TYPE_EXTERNAL),
1287 K1_FUNC_PIN(28, 0, IO_TYPE_EXTERNAL),
1288 K1_FUNC_PIN(29, 0, IO_TYPE_EXTERNAL),
1289 K1_FUNC_PIN(30, 0, IO_TYPE_EXTERNAL),
1290 K1_FUNC_PIN(31, 0, IO_TYPE_EXTERNAL),
1291 K1_FUNC_PIN(32, 0, IO_TYPE_EXTERNAL),
1292 K1_FUNC_PIN(33, 0, IO_TYPE_EXTERNAL),
1293 K1_FUNC_PIN(34, 0, IO_TYPE_EXTERNAL),
1294 K1_FUNC_PIN(35, 0, IO_TYPE_EXTERNAL),
1295 K1_FUNC_PIN(36, 0, IO_TYPE_EXTERNAL),
1296 K1_FUNC_PIN(37, 0, IO_TYPE_EXTERNAL),
1297 K1_FUNC_PIN(38, 0, IO_TYPE_EXTERNAL),
1298 K1_FUNC_PIN(39, 0, IO_TYPE_EXTERNAL),
1299 K1_FUNC_PIN(40, 0, IO_TYPE_EXTERNAL),
1300 K1_FUNC_PIN(41, 0, IO_TYPE_EXTERNAL),
1301
1302 /* GPIO3 bank */
1303 K1_FUNC_PIN(42, 0, IO_TYPE_1V8),
1304 K1_FUNC_PIN(43, 0, IO_TYPE_1V8),
1305 K1_FUNC_PIN(44, 0, IO_TYPE_1V8),
1306 K1_FUNC_PIN(45, 0, IO_TYPE_1V8),
1307 K1_FUNC_PIN(46, 0, IO_TYPE_1V8),
1308 K1_FUNC_PIN(47, 0, IO_TYPE_1V8),
1309 K1_FUNC_PIN(48, 0, IO_TYPE_1V8),
1310 K1_FUNC_PIN(49, 0, IO_TYPE_1V8),
1311 K1_FUNC_PIN(50, 0, IO_TYPE_1V8),
1312 K1_FUNC_PIN(51, 0, IO_TYPE_1V8),
1313 K1_FUNC_PIN(52, 0, IO_TYPE_1V8),
1314 K1_FUNC_PIN(53, 0, IO_TYPE_1V8),
1315 K1_FUNC_PIN(54, 0, IO_TYPE_1V8),
1316 K1_FUNC_PIN(55, 0, IO_TYPE_1V8),
1317 K1_FUNC_PIN(56, 0, IO_TYPE_1V8),
1318 K1_FUNC_PIN(57, 0, IO_TYPE_1V8),
1319 K1_FUNC_PIN(58, 0, IO_TYPE_1V8),
1320 K1_FUNC_PIN(59, 0, IO_TYPE_1V8),
1321 K1_FUNC_PIN(60, 0, IO_TYPE_1V8),
1322 K1_FUNC_PIN(61, 0, IO_TYPE_1V8),
1323 K1_FUNC_PIN(62, 0, IO_TYPE_1V8),
1324 K1_FUNC_PIN(63, 0, IO_TYPE_1V8),
1325 K1_FUNC_PIN(64, 0, IO_TYPE_1V8),
1326 K1_FUNC_PIN(65, 0, IO_TYPE_1V8),
1327 K1_FUNC_PIN(66, 0, IO_TYPE_1V8),
1328 K1_FUNC_PIN(67, 0, IO_TYPE_1V8),
1329 K1_FUNC_PIN(68, 0, IO_TYPE_1V8),
1330 K1_FUNC_PIN(69, 0, IO_TYPE_1V8),
1331 K1_FUNC_PIN(70, 0, IO_TYPE_1V8),
1332 K1_FUNC_PIN(71, 0, IO_TYPE_1V8),
1333 K1_FUNC_PIN(72, 0, IO_TYPE_1V8),
1334 K1_FUNC_PIN(73, 0, IO_TYPE_1V8),
1335 K1_FUNC_PIN(74, 0, IO_TYPE_1V8),
1336 K1_FUNC_PIN(75, 0, IO_TYPE_1V8),
1337
1338 /* GPIO4 bank */
1339 K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL),
1340 K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL),
1341 K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL),
1342 K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL),
1343 K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL),
1344 K1_FUNC_PIN(81, 0, IO_TYPE_EXTERNAL),
1345 K1_FUNC_PIN(82, 0, IO_TYPE_EXTERNAL),
1346 K1_FUNC_PIN(83, 0, IO_TYPE_EXTERNAL),
1347 K1_FUNC_PIN(84, 0, IO_TYPE_EXTERNAL),
1348 K1_FUNC_PIN(85, 0, IO_TYPE_EXTERNAL),
1349 K1_FUNC_PIN(86, 0, IO_TYPE_EXTERNAL),
1350 K1_FUNC_PIN(87, 0, IO_TYPE_EXTERNAL),
1351 K1_FUNC_PIN(88, 0, IO_TYPE_EXTERNAL),
1352 K1_FUNC_PIN(89, 0, IO_TYPE_EXTERNAL),
1353 K1_FUNC_PIN(90, 0, IO_TYPE_EXTERNAL),
1354 K1_FUNC_PIN(91, 0, IO_TYPE_EXTERNAL),
1355 K1_FUNC_PIN(92, 0, IO_TYPE_EXTERNAL),
1356 K1_FUNC_PIN(93, 0, IO_TYPE_EXTERNAL),
1357 K1_FUNC_PIN(94, 0, IO_TYPE_EXTERNAL),
1358 K1_FUNC_PIN(95, 0, IO_TYPE_EXTERNAL),
1359 K1_FUNC_PIN(96, 0, IO_TYPE_EXTERNAL),
1360 K1_FUNC_PIN(97, 0, IO_TYPE_EXTERNAL),
1361 K1_FUNC_PIN(98, 0, IO_TYPE_EXTERNAL),
1362
1363 /* GPIO5 bank */
1364 K1_FUNC_PIN(99, 0, IO_TYPE_EXTERNAL),
1365 K1_FUNC_PIN(100, 0, IO_TYPE_EXTERNAL),
1366 K1_FUNC_PIN(101, 0, IO_TYPE_EXTERNAL),
1367 K1_FUNC_PIN(102, 0, IO_TYPE_EXTERNAL),
1368 K1_FUNC_PIN(103, 0, IO_TYPE_EXTERNAL),
1369 K1_FUNC_PIN(104, 0, IO_TYPE_EXTERNAL),
1370 K1_FUNC_PIN(105, 0, IO_TYPE_EXTERNAL),
1371 K1_FUNC_PIN(106, 0, IO_TYPE_EXTERNAL),
1372 K1_FUNC_PIN(107, 0, IO_TYPE_EXTERNAL),
1373 K1_FUNC_PIN(108, 0, IO_TYPE_EXTERNAL),
1374 K1_FUNC_PIN(109, 0, IO_TYPE_EXTERNAL),
1375 K1_FUNC_PIN(110, 0, IO_TYPE_EXTERNAL),
1376 K1_FUNC_PIN(111, 0, IO_TYPE_EXTERNAL),
1377 K1_FUNC_PIN(112, 0, IO_TYPE_EXTERNAL),
1378 K1_FUNC_PIN(113, 0, IO_TYPE_EXTERNAL),
1379 K1_FUNC_PIN(114, 0, IO_TYPE_EXTERNAL),
1380 K1_FUNC_PIN(115, 0, IO_TYPE_EXTERNAL),
1381 K1_FUNC_PIN(116, 0, IO_TYPE_EXTERNAL),
1382 K1_FUNC_PIN(117, 0, IO_TYPE_EXTERNAL),
1383 K1_FUNC_PIN(118, 0, IO_TYPE_EXTERNAL),
1384 K1_FUNC_PIN(119, 0, IO_TYPE_EXTERNAL),
1385 K1_FUNC_PIN(120, 0, IO_TYPE_EXTERNAL),
1386 K1_FUNC_PIN(121, 0, IO_TYPE_EXTERNAL),
1387 K1_FUNC_PIN(122, 0, IO_TYPE_EXTERNAL),
1388 K1_FUNC_PIN(123, 0, IO_TYPE_EXTERNAL),
1389 K1_FUNC_PIN(124, 0, IO_TYPE_EXTERNAL),
1390 K1_FUNC_PIN(125, 0, IO_TYPE_EXTERNAL),
1391 K1_FUNC_PIN(126, 0, IO_TYPE_EXTERNAL),
1392 K1_FUNC_PIN(127, 0, IO_TYPE_EXTERNAL),
1393
1394 /* PMIC */
1395 K1_FUNC_PIN(128, 0, IO_TYPE_1V8),
1396 K1_FUNC_PIN(129, 0, IO_TYPE_1V8),
1397 K1_FUNC_PIN(130, 0, IO_TYPE_1V8),
1398 K1_FUNC_PIN(131, 0, IO_TYPE_1V8),
1399
1400 /* SD/MMC1 */
1401 K1_FUNC_PIN(132, 1, IO_TYPE_EXTERNAL),
1402 K1_FUNC_PIN(133, 1, IO_TYPE_EXTERNAL),
1403 K1_FUNC_PIN(134, 1, IO_TYPE_EXTERNAL),
1404 K1_FUNC_PIN(135, 1, IO_TYPE_EXTERNAL),
1405 K1_FUNC_PIN(136, 1, IO_TYPE_EXTERNAL),
1406 K1_FUNC_PIN(137, 1, IO_TYPE_EXTERNAL),
1407
1408 /* QSPI */
1409 K1_FUNC_PIN(138, 1, IO_TYPE_EXTERNAL),
1410 K1_FUNC_PIN(139, 1, IO_TYPE_EXTERNAL),
1411 K1_FUNC_PIN(140, 1, IO_TYPE_EXTERNAL),
1412 K1_FUNC_PIN(141, 1, IO_TYPE_EXTERNAL),
1413 K1_FUNC_PIN(142, 1, IO_TYPE_EXTERNAL),
1414 K1_FUNC_PIN(143, 1, IO_TYPE_EXTERNAL),
1415 K1_FUNC_PIN(144, 1, IO_TYPE_EXTERNAL),
1416
1417 /* PMIC */
1418 K1_FUNC_PIN(145, 1, IO_TYPE_1V8),
1419 K1_FUNC_PIN(146, 1, IO_TYPE_1V8),
1420 K1_FUNC_PIN(147, 1, IO_TYPE_1V8),
1421 K1_FUNC_PIN(148, 1, IO_TYPE_1V8),
1422 K1_FUNC_PIN(149, 1, IO_TYPE_1V8),
1423 K1_FUNC_PIN(150, 1, IO_TYPE_1V8),
1424 K1_FUNC_PIN(151, 1, IO_TYPE_1V8),
1425 K1_FUNC_PIN(152, 1, IO_TYPE_1V8),
1426 };
1427
1428 static const struct spacemit_pinctrl_data k3_pinctrl_data = {
1429 .pins = k3_pin_desc,
1430 .data = k3_pin_data,
1431 .npins = ARRAY_SIZE(k3_pin_desc),
1432 .pin_to_offset = spacemit_k3_pin_to_offset,
1433 .pin_to_io_pd_offset = spacemit_k3_pin_to_io_pd_offset,
1434 .dconf = &k3_drive_conf,
1435 };
1436
1437 static const struct of_device_id k1_pinctrl_ids[] = {
1438 { .compatible = "spacemit,k1-pinctrl", .data = &k1_pinctrl_data },
1439 { .compatible = "spacemit,k3-pinctrl", .data = &k3_pinctrl_data },
1440 { /* sentinel */ }
1441 };
1442 MODULE_DEVICE_TABLE(of, k1_pinctrl_ids);
1443
1444 static struct platform_driver k1_pinctrl_driver = {
1445 .probe = spacemit_pinctrl_probe,
1446 .driver = {
1447 .name = "k1-pinctrl",
1448 .suppress_bind_attrs = true,
1449 .of_match_table = k1_pinctrl_ids,
1450 },
1451 };
1452 builtin_platform_driver(k1_pinctrl_driver);
1453
1454 MODULE_AUTHOR("Yixun Lan <dlan@gentoo.org>");
1455 MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1/K3 SoC");
1456 MODULE_LICENSE("GPL");
1457