1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Abramo Bagnara <abramo@alsa-project.org> 5 * Cirrus Logic, Inc. 6 * Routines for control of Cirrus Logic CS461x chips 7 * 8 * KNOWN BUGS: 9 * - Sometimes the SPDIF input DSP tasks get's unsynchronized 10 * and the SPDIF get somewhat "distorcionated", or/and left right channel 11 * are swapped. To get around this problem when it happens, mute and unmute 12 * the SPDIF input mixer control. 13 * - On the Hercules Game Theater XP the amplifier are sometimes turned 14 * off on inadecuate moments which causes distorcions on sound. 15 * 16 * TODO: 17 * - Secondary CODEC on some soundcards 18 * - SPDIF input support for other sample rates then 48khz 19 * - Posibility to mix the SPDIF output with analog sources. 20 * - PCM channels for Center and LFE on secondary codec 21 * 22 * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which 23 * is default configuration), no SPDIF, no secondary codec, no 24 * multi channel PCM. But known to work. 25 * 26 * FINALLY: A credit to the developers Tom and Jordan 27 * at Cirrus for have helping me out with the DSP, however we 28 * still don't have sufficient documentation and technical 29 * references to be able to implement all fancy feutures 30 * supported by the cs46xx DSP's. 31 * Benny <benny@hostmobility.com> 32 */ 33 34 #include <linux/delay.h> 35 #include <linux/pci.h> 36 #include <linux/pm.h> 37 #include <linux/init.h> 38 #include <linux/interrupt.h> 39 #include <linux/slab.h> 40 #include <linux/gameport.h> 41 #include <linux/mutex.h> 42 #include <linux/export.h> 43 #include <linux/module.h> 44 #include <linux/firmware.h> 45 #include <linux/vmalloc.h> 46 #include <linux/io.h> 47 48 #include <sound/core.h> 49 #include <sound/control.h> 50 #include <sound/info.h> 51 #include <sound/pcm.h> 52 #include <sound/pcm_params.h> 53 #include "cs46xx.h" 54 55 #include "cs46xx_lib.h" 56 #include "dsp_spos.h" 57 58 static void amp_voyetra(struct snd_cs46xx *chip, int change); 59 60 #ifdef CONFIG_SND_CS46XX_NEW_DSP 61 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops; 62 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops; 63 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops; 64 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops; 65 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops; 66 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops; 67 #endif 68 69 static const struct snd_pcm_ops snd_cs46xx_playback_ops; 70 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops; 71 static const struct snd_pcm_ops snd_cs46xx_capture_ops; 72 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops; 73 74 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip, 75 unsigned short reg, 76 int codec_index) 77 { 78 int count; 79 unsigned short result,tmp; 80 u32 offset = 0; 81 82 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 83 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 84 return 0xffff; 85 86 chip->active_ctrl(chip, 1); 87 88 if (codec_index == CS46XX_SECONDARY_CODEC_INDEX) 89 offset = CS46XX_SECONDARY_CODEC_OFFSET; 90 91 /* 92 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 93 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 94 * 3. Write ACCTL = Control Register = 460h for initiating the write7---55 95 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h 96 * 5. if DCV not cleared, break and return error 97 * 6. Read ACSTS = Status Register = 464h, check VSTS bit 98 */ 99 100 snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); 101 102 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL); 103 if ((tmp & ACCTL_VFRM) == 0) { 104 dev_warn(chip->card->dev, "ACCTL_VFRM not set 0x%x\n", tmp); 105 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM ); 106 msleep(50); 107 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset); 108 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM ); 109 110 } 111 112 /* 113 * Setup the AC97 control registers on the CS461x to send the 114 * appropriate command to the AC97 to perform the read. 115 * ACCAD = Command Address Register = 46Ch 116 * ACCDA = Command Data Register = 470h 117 * ACCTL = Control Register = 460h 118 * set DCV - will clear when process completed 119 * set CRW - Read command 120 * set VFRM - valid frame enabled 121 * set ESYN - ASYNC generation enabled 122 * set RSTN - ARST# inactive, AC97 codec not reset 123 */ 124 125 snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg); 126 snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0); 127 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { 128 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW | 129 ACCTL_VFRM | ACCTL_ESYN | 130 ACCTL_RSTN); 131 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | 132 ACCTL_VFRM | ACCTL_ESYN | 133 ACCTL_RSTN); 134 } else { 135 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | 136 ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | 137 ACCTL_RSTN); 138 } 139 140 /* 141 * Wait for the read to occur. 142 */ 143 for (count = 0; count < 1000; count++) { 144 /* 145 * First, we want to wait for a short time. 146 */ 147 udelay(10); 148 /* 149 * Now, check to see if the read has completed. 150 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 151 */ 152 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) 153 goto ok1; 154 } 155 156 dev_err(chip->card->dev, 157 "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); 158 result = 0xffff; 159 goto end; 160 161 ok1: 162 /* 163 * Wait for the valid status bit to go active. 164 */ 165 for (count = 0; count < 100; count++) { 166 /* 167 * Read the AC97 status register. 168 * ACSTS = Status Register = 464h 169 * VSTS - Valid Status 170 */ 171 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS) 172 goto ok2; 173 udelay(10); 174 } 175 176 dev_err(chip->card->dev, 177 "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", 178 codec_index, reg); 179 result = 0xffff; 180 goto end; 181 182 ok2: 183 /* 184 * Read the data returned from the AC97 register. 185 * ACSDA = Status Data Register = 474h 186 */ 187 #if 0 188 dev_dbg(chip->card->dev, 189 "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg, 190 snd_cs46xx_peekBA0(chip, BA0_ACSDA), 191 snd_cs46xx_peekBA0(chip, BA0_ACCAD)); 192 #endif 193 194 //snd_cs46xx_peekBA0(chip, BA0_ACCAD); 195 result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset); 196 end: 197 chip->active_ctrl(chip, -1); 198 return result; 199 } 200 201 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97, 202 unsigned short reg) 203 { 204 struct snd_cs46xx *chip = ac97->private_data; 205 unsigned short val; 206 int codec_index = ac97->num; 207 208 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 209 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 210 return 0xffff; 211 212 val = snd_cs46xx_codec_read(chip, reg, codec_index); 213 214 return val; 215 } 216 217 218 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip, 219 unsigned short reg, 220 unsigned short val, 221 int codec_index) 222 { 223 int count; 224 225 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 226 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 227 return; 228 229 chip->active_ctrl(chip, 1); 230 231 /* 232 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 233 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 234 * 3. Write ACCTL = Control Register = 460h for initiating the write 235 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h 236 * 5. if DCV not cleared, break and return error 237 */ 238 239 /* 240 * Setup the AC97 control registers on the CS461x to send the 241 * appropriate command to the AC97 to perform the read. 242 * ACCAD = Command Address Register = 46Ch 243 * ACCDA = Command Data Register = 470h 244 * ACCTL = Control Register = 460h 245 * set DCV - will clear when process completed 246 * reset CRW - Write command 247 * set VFRM - valid frame enabled 248 * set ESYN - ASYNC generation enabled 249 * set RSTN - ARST# inactive, AC97 codec not reset 250 */ 251 snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg); 252 snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val); 253 snd_cs46xx_peekBA0(chip, BA0_ACCTL); 254 255 if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) { 256 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM | 257 ACCTL_ESYN | ACCTL_RSTN); 258 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | 259 ACCTL_ESYN | ACCTL_RSTN); 260 } else { 261 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC | 262 ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 263 } 264 265 for (count = 0; count < 4000; count++) { 266 /* 267 * First, we want to wait for a short time. 268 */ 269 udelay(10); 270 /* 271 * Now, check to see if the write has completed. 272 * ACCTL = 460h, DCV should be reset by now and 460h = 07h 273 */ 274 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) { 275 goto end; 276 } 277 } 278 dev_err(chip->card->dev, 279 "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", 280 codec_index, reg, val); 281 end: 282 chip->active_ctrl(chip, -1); 283 } 284 285 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97, 286 unsigned short reg, 287 unsigned short val) 288 { 289 struct snd_cs46xx *chip = ac97->private_data; 290 int codec_index = ac97->num; 291 292 if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX && 293 codec_index != CS46XX_SECONDARY_CODEC_INDEX)) 294 return; 295 296 snd_cs46xx_codec_write(chip, reg, val, codec_index); 297 } 298 299 300 /* 301 * Chip initialization 302 */ 303 304 int snd_cs46xx_download(struct snd_cs46xx *chip, 305 u32 *src, 306 unsigned long offset, 307 unsigned long len) 308 { 309 void __iomem *dst; 310 unsigned int bank = offset >> 16; 311 offset = offset & 0xffff; 312 313 if (snd_BUG_ON((offset & 3) || (len & 3))) 314 return -EINVAL; 315 dst = chip->region.idx[bank+1].remap_addr + offset; 316 len /= sizeof(u32); 317 318 /* writel already converts 32-bit value to right endianess */ 319 while (len-- > 0) { 320 writel(*src++, dst); 321 dst += sizeof(u32); 322 } 323 return 0; 324 } 325 326 static inline void memcpy_le32(void *dst, const void *src, unsigned int len) 327 { 328 #ifdef __LITTLE_ENDIAN 329 memcpy(dst, src, len); 330 #else 331 u32 *_dst = dst; 332 const __le32 *_src = src; 333 len /= 4; 334 while (len-- > 0) 335 *_dst++ = le32_to_cpu(*_src++); 336 #endif 337 } 338 339 #ifdef CONFIG_SND_CS46XX_NEW_DSP 340 341 static const char *module_names[CS46XX_DSP_MODULES] = { 342 "cwc4630", "cwcasync", "cwcsnoop", "cwcbinhack", "cwcdma" 343 }; 344 345 MODULE_FIRMWARE("cs46xx/cwc4630"); 346 MODULE_FIRMWARE("cs46xx/cwcasync"); 347 MODULE_FIRMWARE("cs46xx/cwcsnoop"); 348 MODULE_FIRMWARE("cs46xx/cwcbinhack"); 349 MODULE_FIRMWARE("cs46xx/cwcdma"); 350 351 static void free_module_desc(struct dsp_module_desc *module) 352 { 353 if (!module) 354 return; 355 kfree(module->module_name); 356 kfree(module->symbol_table.symbols); 357 if (module->segments) { 358 int i; 359 for (i = 0; i < module->nsegments; i++) 360 kfree(module->segments[i].data); 361 kfree(module->segments); 362 } 363 kfree(module); 364 } 365 366 /* firmware binary format: 367 * le32 nsymbols; 368 * struct { 369 * le32 address; 370 * char symbol_name[DSP_MAX_SYMBOL_NAME]; 371 * le32 symbol_type; 372 * } symbols[nsymbols]; 373 * le32 nsegments; 374 * struct { 375 * le32 segment_type; 376 * le32 offset; 377 * le32 size; 378 * le32 data[size]; 379 * } segments[nsegments]; 380 */ 381 382 static int load_firmware(struct snd_cs46xx *chip, 383 struct dsp_module_desc **module_ret, 384 const char *fw_name) 385 { 386 int i, err; 387 unsigned int nums, fwlen, fwsize; 388 const __le32 *fwdat; 389 struct dsp_module_desc *module = NULL; 390 const struct firmware *fw __free(firmware) = NULL; 391 char fw_path[32]; 392 393 sprintf(fw_path, "cs46xx/%s", fw_name); 394 err = request_firmware(&fw, fw_path, &chip->pci->dev); 395 if (err < 0) 396 return err; 397 fwsize = fw->size / 4; 398 if (fwsize < 2) 399 return -EINVAL; 400 401 err = -ENOMEM; 402 module = kzalloc_obj(*module); 403 if (!module) 404 goto error; 405 module->module_name = kstrdup(fw_name, GFP_KERNEL); 406 if (!module->module_name) 407 goto error; 408 409 fwlen = 0; 410 fwdat = (const __le32 *)fw->data; 411 nums = module->symbol_table.nsymbols = le32_to_cpu(fwdat[fwlen++]); 412 if (nums >= 40) 413 goto error_inval; 414 module->symbol_table.symbols = 415 kzalloc_objs(struct dsp_symbol_entry, nums); 416 if (!module->symbol_table.symbols) 417 goto error; 418 for (i = 0; i < nums; i++) { 419 struct dsp_symbol_entry *entry = 420 &module->symbol_table.symbols[i]; 421 if (fwlen + 2 + DSP_MAX_SYMBOL_NAME / 4 > fwsize) 422 goto error_inval; 423 entry->address = le32_to_cpu(fwdat[fwlen++]); 424 memcpy(entry->symbol_name, &fwdat[fwlen], DSP_MAX_SYMBOL_NAME - 1); 425 fwlen += DSP_MAX_SYMBOL_NAME / 4; 426 entry->symbol_type = le32_to_cpu(fwdat[fwlen++]); 427 } 428 429 if (fwlen >= fwsize) 430 goto error_inval; 431 nums = module->nsegments = le32_to_cpu(fwdat[fwlen++]); 432 if (nums > 10) 433 goto error_inval; 434 module->segments = 435 kzalloc_objs(struct dsp_segment_desc, nums); 436 if (!module->segments) 437 goto error; 438 for (i = 0; i < nums; i++) { 439 struct dsp_segment_desc *entry = &module->segments[i]; 440 if (fwlen + 3 > fwsize) 441 goto error_inval; 442 entry->segment_type = le32_to_cpu(fwdat[fwlen++]); 443 entry->offset = le32_to_cpu(fwdat[fwlen++]); 444 entry->size = le32_to_cpu(fwdat[fwlen++]); 445 if (fwlen + entry->size > fwsize) 446 goto error_inval; 447 entry->data = kmalloc_array(entry->size, 4, GFP_KERNEL); 448 if (!entry->data) 449 goto error; 450 memcpy_le32(entry->data, &fwdat[fwlen], entry->size * 4); 451 fwlen += entry->size; 452 } 453 454 *module_ret = module; 455 return 0; 456 457 error_inval: 458 err = -EINVAL; 459 error: 460 free_module_desc(module); 461 return err; 462 } 463 464 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip, 465 unsigned long offset, 466 unsigned long len) 467 { 468 void __iomem *dst; 469 unsigned int bank = offset >> 16; 470 offset = offset & 0xffff; 471 472 if (snd_BUG_ON((offset & 3) || (len & 3))) 473 return -EINVAL; 474 dst = chip->region.idx[bank+1].remap_addr + offset; 475 len /= sizeof(u32); 476 477 /* writel already converts 32-bit value to right endianess */ 478 while (len-- > 0) { 479 writel(0, dst); 480 dst += sizeof(u32); 481 } 482 return 0; 483 } 484 485 #else /* old DSP image */ 486 487 struct ba1_struct { 488 struct { 489 u32 offset; 490 u32 size; 491 } memory[BA1_MEMORY_COUNT]; 492 u32 map[BA1_DWORD_SIZE]; 493 }; 494 495 MODULE_FIRMWARE("cs46xx/ba1"); 496 497 static int load_firmware(struct snd_cs46xx *chip) 498 { 499 const struct firmware *fw __free(firmware) = NULL; 500 int i, size, err; 501 502 err = request_firmware(&fw, "cs46xx/ba1", &chip->pci->dev); 503 if (err < 0) 504 return err; 505 if (fw->size != sizeof(*chip->ba1)) 506 return -EINVAL; 507 508 chip->ba1 = vmalloc(sizeof(*chip->ba1)); 509 if (!chip->ba1) 510 return -ENOMEM; 511 512 memcpy_le32(chip->ba1, fw->data, sizeof(*chip->ba1)); 513 514 /* sanity check */ 515 size = 0; 516 for (i = 0; i < BA1_MEMORY_COUNT; i++) 517 size += chip->ba1->memory[i].size; 518 if (size > BA1_DWORD_SIZE * 4) 519 return -EINVAL; 520 521 return 0; 522 } 523 524 static __maybe_unused int snd_cs46xx_download_image(struct snd_cs46xx *chip) 525 { 526 int idx, err; 527 unsigned int offset = 0; 528 struct ba1_struct *ba1 = chip->ba1; 529 530 for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) { 531 err = snd_cs46xx_download(chip, 532 &ba1->map[offset], 533 ba1->memory[idx].offset, 534 ba1->memory[idx].size); 535 if (err < 0) 536 return err; 537 offset += ba1->memory[idx].size >> 2; 538 } 539 return 0; 540 } 541 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 542 543 /* 544 * Chip reset 545 */ 546 547 static void snd_cs46xx_reset(struct snd_cs46xx *chip) 548 { 549 int idx; 550 551 /* 552 * Write the reset bit of the SP control register. 553 */ 554 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP); 555 556 /* 557 * Write the control register. 558 */ 559 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN); 560 561 /* 562 * Clear the trap registers. 563 */ 564 for (idx = 0; idx < 8; idx++) { 565 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx); 566 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF); 567 } 568 snd_cs46xx_poke(chip, BA1_DREG, 0); 569 570 /* 571 * Set the frame timer to reflect the number of cycles per frame. 572 */ 573 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); 574 } 575 576 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout) 577 { 578 u32 i, status = 0; 579 /* 580 * Make sure the previous FIFO write operation has completed. 581 */ 582 for(i = 0; i < 50; i++){ 583 status = snd_cs46xx_peekBA0(chip, BA0_SERBST); 584 585 if( !(status & SERBST_WBSY) ) 586 break; 587 588 mdelay(retry_timeout); 589 } 590 591 if(status & SERBST_WBSY) { 592 dev_err(chip->card->dev, 593 "failure waiting for FIFO command to complete\n"); 594 return -EINVAL; 595 } 596 597 return 0; 598 } 599 600 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip) 601 { 602 int idx, powerdown = 0; 603 unsigned int tmp; 604 605 /* 606 * See if the devices are powered down. If so, we must power them up first 607 * or they will not respond. 608 */ 609 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); 610 if (!(tmp & CLKCR1_SWCE)) { 611 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); 612 powerdown = 1; 613 } 614 615 /* 616 * We want to clear out the serial port FIFOs so we don't end up playing 617 * whatever random garbage happens to be in them. We fill the sample FIFOS 618 * with zero (silence). 619 */ 620 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0); 621 622 /* 623 * Fill all 256 sample FIFO locations. 624 */ 625 for (idx = 0; idx < 0xFF; idx++) { 626 /* 627 * Make sure the previous FIFO write operation has completed. 628 */ 629 if (cs46xx_wait_for_fifo(chip,1)) { 630 dev_dbg(chip->card->dev, 631 "failed waiting for FIFO at addr (%02X)\n", 632 idx); 633 634 if (powerdown) 635 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 636 637 break; 638 } 639 /* 640 * Write the serial port FIFO index. 641 */ 642 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); 643 /* 644 * Tell the serial port to load the new value into the FIFO location. 645 */ 646 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); 647 } 648 /* 649 * Now, if we powered up the devices, then power them back down again. 650 * This is kinda ugly, but should never happen. 651 */ 652 if (powerdown) 653 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 654 } 655 656 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip) 657 { 658 int cnt; 659 660 /* 661 * Set the frame timer to reflect the number of cycles per frame. 662 */ 663 snd_cs46xx_poke(chip, BA1_FRMT, 0xadf); 664 /* 665 * Turn on the run, run at frame, and DMA enable bits in the local copy of 666 * the SP control register. 667 */ 668 snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN); 669 /* 670 * Wait until the run at frame bit resets itself in the SP control 671 * register. 672 */ 673 for (cnt = 0; cnt < 25; cnt++) { 674 udelay(50); 675 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)) 676 break; 677 } 678 679 if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR) 680 dev_err(chip->card->dev, "SPCR_RUNFR never reset\n"); 681 } 682 683 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip) 684 { 685 /* 686 * Turn off the run, run at frame, and DMA enable bits in the local copy of 687 * the SP control register. 688 */ 689 snd_cs46xx_poke(chip, BA1_SPCR, 0); 690 } 691 692 /* 693 * Sample rate routines 694 */ 695 696 #define GOF_PER_SEC 200 697 698 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate) 699 { 700 unsigned int tmp1, tmp2; 701 unsigned int phiIncr; 702 unsigned int correctionPerGOF, correctionPerSec; 703 704 /* 705 * Compute the values used to drive the actual sample rate conversion. 706 * The following formulas are being computed, using inline assembly 707 * since we need to use 64 bit arithmetic to compute the values: 708 * 709 * phiIncr = floor((Fs,in * 2^26) / Fs,out) 710 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / 711 * GOF_PER_SEC) 712 * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M 713 * GOF_PER_SEC * correctionPerGOF 714 * 715 * i.e. 716 * 717 * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out) 718 * correctionPerGOF:correctionPerSec = 719 * dividend:remainder(ulOther / GOF_PER_SEC) 720 */ 721 tmp1 = rate << 16; 722 phiIncr = tmp1 / 48000; 723 tmp1 -= phiIncr * 48000; 724 tmp1 <<= 10; 725 phiIncr <<= 10; 726 tmp2 = tmp1 / 48000; 727 phiIncr += tmp2; 728 tmp1 -= tmp2 * 48000; 729 correctionPerGOF = tmp1 / GOF_PER_SEC; 730 tmp1 -= correctionPerGOF * GOF_PER_SEC; 731 correctionPerSec = tmp1; 732 733 /* 734 * Fill in the SampleRateConverter control block. 735 */ 736 guard(spinlock_irqsave)(&chip->reg_lock); 737 snd_cs46xx_poke(chip, BA1_PSRC, 738 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); 739 snd_cs46xx_poke(chip, BA1_PPI, phiIncr); 740 } 741 742 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate) 743 { 744 unsigned int phiIncr, coeffIncr, tmp1, tmp2; 745 unsigned int correctionPerGOF, correctionPerSec, initialDelay; 746 unsigned int frameGroupLength, cnt; 747 748 /* 749 * We can only decimate by up to a factor of 1/9th the hardware rate. 750 * Correct the value if an attempt is made to stray outside that limit. 751 */ 752 if ((rate * 9) < 48000) 753 rate = 48000 / 9; 754 755 /* 756 * We can not capture at a rate greater than the Input Rate (48000). 757 * Return an error if an attempt is made to stray outside that limit. 758 */ 759 if (rate > 48000) 760 rate = 48000; 761 762 /* 763 * Compute the values used to drive the actual sample rate conversion. 764 * The following formulas are being computed, using inline assembly 765 * since we need to use 64 bit arithmetic to compute the values: 766 * 767 * coeffIncr = -floor((Fs,out * 2^23) / Fs,in) 768 * phiIncr = floor((Fs,in * 2^26) / Fs,out) 769 * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) / 770 * GOF_PER_SEC) 771 * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr - 772 * GOF_PER_SEC * correctionPerGOF 773 * initialDelay = ceil((24 * Fs,in) / Fs,out) 774 * 775 * i.e. 776 * 777 * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in)) 778 * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out) 779 * correctionPerGOF:correctionPerSec = 780 * dividend:remainder(ulOther / GOF_PER_SEC) 781 * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out) 782 */ 783 784 tmp1 = rate << 16; 785 coeffIncr = tmp1 / 48000; 786 tmp1 -= coeffIncr * 48000; 787 tmp1 <<= 7; 788 coeffIncr <<= 7; 789 coeffIncr += tmp1 / 48000; 790 coeffIncr ^= 0xFFFFFFFF; 791 coeffIncr++; 792 tmp1 = 48000 << 16; 793 phiIncr = tmp1 / rate; 794 tmp1 -= phiIncr * rate; 795 tmp1 <<= 10; 796 phiIncr <<= 10; 797 tmp2 = tmp1 / rate; 798 phiIncr += tmp2; 799 tmp1 -= tmp2 * rate; 800 correctionPerGOF = tmp1 / GOF_PER_SEC; 801 tmp1 -= correctionPerGOF * GOF_PER_SEC; 802 correctionPerSec = tmp1; 803 initialDelay = DIV_ROUND_UP(48000 * 24, rate); 804 805 /* 806 * Fill in the VariDecimate control block. 807 */ 808 scoped_guard(spinlock_irqsave, &chip->reg_lock) { 809 snd_cs46xx_poke(chip, BA1_CSRC, 810 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF)); 811 snd_cs46xx_poke(chip, BA1_CCI, coeffIncr); 812 snd_cs46xx_poke(chip, BA1_CD, 813 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80); 814 snd_cs46xx_poke(chip, BA1_CPI, phiIncr); 815 } 816 817 /* 818 * Figure out the frame group length for the write back task. Basically, 819 * this is just the factors of 24000 (2^6*3*5^3) that are not present in 820 * the output sample rate. 821 */ 822 frameGroupLength = 1; 823 for (cnt = 2; cnt <= 64; cnt *= 2) { 824 if (((rate / cnt) * cnt) != rate) 825 frameGroupLength *= 2; 826 } 827 if (((rate / 3) * 3) != rate) { 828 frameGroupLength *= 3; 829 } 830 for (cnt = 5; cnt <= 125; cnt *= 5) { 831 if (((rate / cnt) * cnt) != rate) 832 frameGroupLength *= 5; 833 } 834 835 /* 836 * Fill in the WriteBack control block. 837 */ 838 guard(spinlock_irqsave)(&chip->reg_lock); 839 snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength); 840 snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength)); 841 snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF); 842 snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000)); 843 snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF); 844 } 845 846 /* 847 * PCM part 848 */ 849 850 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream, 851 struct snd_pcm_indirect *rec, size_t bytes) 852 { 853 struct snd_pcm_runtime *runtime = substream->runtime; 854 struct snd_cs46xx_pcm * cpcm = runtime->private_data; 855 memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes); 856 } 857 858 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream) 859 { 860 struct snd_pcm_runtime *runtime = substream->runtime; 861 struct snd_cs46xx_pcm * cpcm = runtime->private_data; 862 return snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, 863 snd_cs46xx_pb_trans_copy); 864 } 865 866 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream, 867 struct snd_pcm_indirect *rec, size_t bytes) 868 { 869 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 870 struct snd_pcm_runtime *runtime = substream->runtime; 871 memcpy(runtime->dma_area + rec->sw_data, 872 chip->capt.hw_buf.area + rec->hw_data, bytes); 873 } 874 875 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream) 876 { 877 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 878 return snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, 879 snd_cs46xx_cp_trans_copy); 880 } 881 882 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream) 883 { 884 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 885 size_t ptr; 886 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 887 888 if (snd_BUG_ON(!cpcm->pcm_channel)) 889 return -ENXIO; 890 891 #ifdef CONFIG_SND_CS46XX_NEW_DSP 892 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); 893 #else 894 ptr = snd_cs46xx_peek(chip, BA1_PBA); 895 #endif 896 ptr -= cpcm->hw_buf.addr; 897 return ptr >> cpcm->shift; 898 } 899 900 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream) 901 { 902 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 903 size_t ptr; 904 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 905 906 #ifdef CONFIG_SND_CS46XX_NEW_DSP 907 if (snd_BUG_ON(!cpcm->pcm_channel)) 908 return -ENXIO; 909 ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2); 910 #else 911 ptr = snd_cs46xx_peek(chip, BA1_PBA); 912 #endif 913 ptr -= cpcm->hw_buf.addr; 914 return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr); 915 } 916 917 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream) 918 { 919 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 920 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; 921 return ptr >> chip->capt.shift; 922 } 923 924 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream) 925 { 926 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 927 size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr; 928 return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr); 929 } 930 931 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream, 932 int cmd) 933 { 934 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 935 /*struct snd_pcm_runtime *runtime = substream->runtime;*/ 936 int result = 0; 937 938 #ifdef CONFIG_SND_CS46XX_NEW_DSP 939 struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data; 940 if (! cpcm->pcm_channel) { 941 return -ENXIO; 942 } 943 #endif 944 switch (cmd) { 945 case SNDRV_PCM_TRIGGER_START: 946 case SNDRV_PCM_TRIGGER_RESUME: 947 #ifdef CONFIG_SND_CS46XX_NEW_DSP 948 /* magic value to unmute PCM stream playback volume */ 949 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 950 SCBVolumeCtrl) << 2, 0x80008000); 951 952 if (cpcm->pcm_channel->unlinked) 953 cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel); 954 955 if (substream->runtime->periods != CS46XX_FRAGS) 956 snd_cs46xx_playback_transfer(substream); 957 #else 958 scoped_guard(spinlock, &chip->reg_lock) { 959 unsigned int tmp; 960 if (substream->runtime->periods != CS46XX_FRAGS) 961 snd_cs46xx_playback_transfer(substream); 962 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 963 tmp &= 0x0000ffff; 964 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp); 965 } 966 #endif 967 break; 968 case SNDRV_PCM_TRIGGER_STOP: 969 case SNDRV_PCM_TRIGGER_SUSPEND: 970 #ifdef CONFIG_SND_CS46XX_NEW_DSP 971 /* magic mute channel */ 972 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 973 SCBVolumeCtrl) << 2, 0xffffffff); 974 975 if (!cpcm->pcm_channel->unlinked) 976 cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel); 977 #else 978 scoped_guard(spinlock, &chip->reg_lock) { 979 unsigned int tmp; 980 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 981 tmp &= 0x0000ffff; 982 snd_cs46xx_poke(chip, BA1_PCTL, tmp); 983 } 984 #endif 985 break; 986 default: 987 result = -EINVAL; 988 break; 989 } 990 991 return result; 992 } 993 994 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream, 995 int cmd) 996 { 997 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 998 unsigned int tmp; 999 1000 guard(spinlock)(&chip->reg_lock); 1001 switch (cmd) { 1002 case SNDRV_PCM_TRIGGER_START: 1003 case SNDRV_PCM_TRIGGER_RESUME: 1004 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 1005 tmp &= 0xffff0000; 1006 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp); 1007 break; 1008 case SNDRV_PCM_TRIGGER_STOP: 1009 case SNDRV_PCM_TRIGGER_SUSPEND: 1010 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 1011 tmp &= 0xffff0000; 1012 snd_cs46xx_poke(chip, BA1_CCTL, tmp); 1013 break; 1014 default: 1015 return -EINVAL; 1016 } 1017 return 0; 1018 } 1019 1020 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1021 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm, 1022 int sample_rate) 1023 { 1024 1025 /* If PCMReaderSCB and SrcTaskSCB not created yet ... */ 1026 if ( cpcm->pcm_channel == NULL) { 1027 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, 1028 cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id); 1029 if (cpcm->pcm_channel == NULL) { 1030 dev_err(chip->card->dev, 1031 "failed to create virtual PCM channel\n"); 1032 return -ENOMEM; 1033 } 1034 cpcm->pcm_channel->sample_rate = sample_rate; 1035 } else 1036 /* if sample rate is changed */ 1037 if ((int)cpcm->pcm_channel->sample_rate != sample_rate) { 1038 int unlinked = cpcm->pcm_channel->unlinked; 1039 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel); 1040 1041 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel(chip, sample_rate, cpcm, 1042 cpcm->hw_buf.addr, 1043 cpcm->pcm_channel_id); 1044 if (!cpcm->pcm_channel) { 1045 dev_err(chip->card->dev, 1046 "failed to re-create virtual PCM channel\n"); 1047 return -ENOMEM; 1048 } 1049 1050 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel); 1051 cpcm->pcm_channel->sample_rate = sample_rate; 1052 } 1053 1054 return 0; 1055 } 1056 #endif 1057 1058 1059 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream, 1060 struct snd_pcm_hw_params *hw_params) 1061 { 1062 struct snd_pcm_runtime *runtime = substream->runtime; 1063 struct snd_cs46xx_pcm *cpcm; 1064 int err; 1065 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1066 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1067 int sample_rate = params_rate(hw_params); 1068 int period_size = params_period_bytes(hw_params); 1069 #endif 1070 cpcm = runtime->private_data; 1071 1072 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1073 if (snd_BUG_ON(!sample_rate)) 1074 return -ENXIO; 1075 1076 guard(mutex)(&chip->spos_mutex); 1077 1078 if (_cs46xx_adjust_sample_rate(chip, cpcm, sample_rate)) 1079 return -ENXIO; 1080 1081 snd_BUG_ON(!cpcm->pcm_channel); 1082 if (!cpcm->pcm_channel) 1083 return -ENXIO; 1084 1085 if (cs46xx_dsp_pcm_channel_set_period(chip, cpcm->pcm_channel, period_size)) 1086 return -EINVAL; 1087 1088 dev_dbg(chip->card->dev, 1089 "period_size (%d), periods (%d) buffer_size(%d)\n", 1090 period_size, params_periods(hw_params), 1091 params_buffer_bytes(hw_params)); 1092 #endif 1093 1094 if (params_periods(hw_params) == CS46XX_FRAGS) { 1095 if (runtime->dma_area != cpcm->hw_buf.area) 1096 snd_pcm_lib_free_pages(substream); 1097 snd_pcm_set_runtime_buffer(substream, &cpcm->hw_buf); 1098 1099 1100 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1101 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { 1102 substream->ops = &snd_cs46xx_playback_ops; 1103 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { 1104 substream->ops = &snd_cs46xx_playback_rear_ops; 1105 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { 1106 substream->ops = &snd_cs46xx_playback_clfe_ops; 1107 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { 1108 substream->ops = &snd_cs46xx_playback_iec958_ops; 1109 } else { 1110 snd_BUG(); 1111 } 1112 #else 1113 substream->ops = &snd_cs46xx_playback_ops; 1114 #endif 1115 1116 } else { 1117 if (runtime->dma_area == cpcm->hw_buf.area) 1118 snd_pcm_set_runtime_buffer(substream, NULL); 1119 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 1120 if (err < 0) 1121 return err; 1122 1123 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1124 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) { 1125 substream->ops = &snd_cs46xx_playback_indirect_ops; 1126 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) { 1127 substream->ops = &snd_cs46xx_playback_indirect_rear_ops; 1128 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) { 1129 substream->ops = &snd_cs46xx_playback_indirect_clfe_ops; 1130 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) { 1131 substream->ops = &snd_cs46xx_playback_indirect_iec958_ops; 1132 } else { 1133 snd_BUG(); 1134 } 1135 #else 1136 substream->ops = &snd_cs46xx_playback_indirect_ops; 1137 #endif 1138 1139 } 1140 1141 return 0; 1142 } 1143 1144 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream) 1145 { 1146 /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/ 1147 struct snd_pcm_runtime *runtime = substream->runtime; 1148 struct snd_cs46xx_pcm *cpcm; 1149 1150 cpcm = runtime->private_data; 1151 1152 /* if play_back open fails, then this function 1153 is called and cpcm can actually be NULL here */ 1154 if (!cpcm) return -ENXIO; 1155 1156 if (runtime->dma_area != cpcm->hw_buf.area) 1157 snd_pcm_lib_free_pages(substream); 1158 1159 snd_pcm_set_runtime_buffer(substream, NULL); 1160 1161 return 0; 1162 } 1163 1164 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream) 1165 { 1166 unsigned int tmp; 1167 unsigned int pfie; 1168 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1169 struct snd_pcm_runtime *runtime = substream->runtime; 1170 struct snd_cs46xx_pcm *cpcm; 1171 1172 cpcm = runtime->private_data; 1173 1174 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1175 if (snd_BUG_ON(!cpcm->pcm_channel)) 1176 return -ENXIO; 1177 1178 pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 ); 1179 pfie &= ~0x0000f03f; 1180 #else 1181 /* old dsp */ 1182 pfie = snd_cs46xx_peek(chip, BA1_PFIE); 1183 pfie &= ~0x0000f03f; 1184 #endif 1185 1186 cpcm->shift = 2; 1187 /* if to convert from stereo to mono */ 1188 if (runtime->channels == 1) { 1189 cpcm->shift--; 1190 pfie |= 0x00002000; 1191 } 1192 /* if to convert from 8 bit to 16 bit */ 1193 if (snd_pcm_format_width(runtime->format) == 8) { 1194 cpcm->shift--; 1195 pfie |= 0x00001000; 1196 } 1197 /* if to convert to unsigned */ 1198 if (snd_pcm_format_unsigned(runtime->format)) 1199 pfie |= 0x00008000; 1200 1201 /* Never convert byte order when sample stream is 8 bit */ 1202 if (snd_pcm_format_width(runtime->format) != 8) { 1203 /* convert from big endian to little endian */ 1204 if (snd_pcm_format_big_endian(runtime->format)) 1205 pfie |= 0x00004000; 1206 } 1207 1208 memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec)); 1209 cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1210 cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift; 1211 1212 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1213 1214 tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2); 1215 tmp &= ~0x000003ff; 1216 tmp |= (4 << cpcm->shift) - 1; 1217 /* playback transaction count register */ 1218 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp); 1219 1220 /* playback format && interrupt enable */ 1221 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot); 1222 #else 1223 snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr); 1224 tmp = snd_cs46xx_peek(chip, BA1_PDTC); 1225 tmp &= ~0x000003ff; 1226 tmp |= (4 << cpcm->shift) - 1; 1227 snd_cs46xx_poke(chip, BA1_PDTC, tmp); 1228 snd_cs46xx_poke(chip, BA1_PFIE, pfie); 1229 snd_cs46xx_set_play_sample_rate(chip, runtime->rate); 1230 #endif 1231 1232 return 0; 1233 } 1234 1235 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream, 1236 struct snd_pcm_hw_params *hw_params) 1237 { 1238 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1239 struct snd_pcm_runtime *runtime = substream->runtime; 1240 int err; 1241 1242 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1243 cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params)); 1244 #endif 1245 if (runtime->periods == CS46XX_FRAGS) { 1246 if (runtime->dma_area != chip->capt.hw_buf.area) 1247 snd_pcm_lib_free_pages(substream); 1248 snd_pcm_set_runtime_buffer(substream, &chip->capt.hw_buf); 1249 substream->ops = &snd_cs46xx_capture_ops; 1250 } else { 1251 if (runtime->dma_area == chip->capt.hw_buf.area) 1252 snd_pcm_set_runtime_buffer(substream, NULL); 1253 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 1254 if (err < 0) 1255 return err; 1256 substream->ops = &snd_cs46xx_capture_indirect_ops; 1257 } 1258 1259 return 0; 1260 } 1261 1262 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream) 1263 { 1264 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1265 struct snd_pcm_runtime *runtime = substream->runtime; 1266 1267 if (runtime->dma_area != chip->capt.hw_buf.area) 1268 snd_pcm_lib_free_pages(substream); 1269 snd_pcm_set_runtime_buffer(substream, NULL); 1270 1271 return 0; 1272 } 1273 1274 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream) 1275 { 1276 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1277 struct snd_pcm_runtime *runtime = substream->runtime; 1278 1279 snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr); 1280 chip->capt.shift = 2; 1281 memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec)); 1282 chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1283 chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2; 1284 snd_cs46xx_set_capture_sample_rate(chip, runtime->rate); 1285 1286 return 0; 1287 } 1288 1289 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id) 1290 { 1291 struct snd_cs46xx *chip = dev_id; 1292 u32 status1; 1293 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1294 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1295 u32 status2; 1296 int i; 1297 struct snd_cs46xx_pcm *cpcm = NULL; 1298 #endif 1299 1300 /* 1301 * Read the Interrupt Status Register to clear the interrupt 1302 */ 1303 status1 = snd_cs46xx_peekBA0(chip, BA0_HISR); 1304 if ((status1 & 0x7fffffff) == 0) { 1305 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); 1306 return IRQ_NONE; 1307 } 1308 1309 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1310 status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0); 1311 1312 for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) { 1313 if (i <= 15) { 1314 if ( status1 & (1 << i) ) { 1315 if (i == CS46XX_DSP_CAPTURE_CHANNEL) { 1316 if (chip->capt.substream) 1317 snd_pcm_period_elapsed(chip->capt.substream); 1318 } else { 1319 if (ins->pcm_channels[i].active && 1320 ins->pcm_channels[i].private_data && 1321 !ins->pcm_channels[i].unlinked) { 1322 cpcm = ins->pcm_channels[i].private_data; 1323 snd_pcm_period_elapsed(cpcm->substream); 1324 } 1325 } 1326 } 1327 } else { 1328 if ( status2 & (1 << (i - 16))) { 1329 if (ins->pcm_channels[i].active && 1330 ins->pcm_channels[i].private_data && 1331 !ins->pcm_channels[i].unlinked) { 1332 cpcm = ins->pcm_channels[i].private_data; 1333 snd_pcm_period_elapsed(cpcm->substream); 1334 } 1335 } 1336 } 1337 } 1338 1339 #else 1340 /* old dsp */ 1341 if ((status1 & HISR_VC0) && chip->playback_pcm) { 1342 if (chip->playback_pcm->substream) 1343 snd_pcm_period_elapsed(chip->playback_pcm->substream); 1344 } 1345 if ((status1 & HISR_VC1) && chip->pcm) { 1346 if (chip->capt.substream) 1347 snd_pcm_period_elapsed(chip->capt.substream); 1348 } 1349 #endif 1350 1351 if ((status1 & HISR_MIDI) && chip->rmidi) { 1352 unsigned char c; 1353 1354 guard(spinlock)(&chip->reg_lock); 1355 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) { 1356 c = snd_cs46xx_peekBA0(chip, BA0_MIDRP); 1357 if ((chip->midcr & MIDCR_RIE) == 0) 1358 continue; 1359 snd_rawmidi_receive(chip->midi_input, &c, 1); 1360 } 1361 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { 1362 if ((chip->midcr & MIDCR_TIE) == 0) 1363 break; 1364 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { 1365 chip->midcr &= ~MIDCR_TIE; 1366 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1367 break; 1368 } 1369 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c); 1370 } 1371 } 1372 /* 1373 * EOI to the PCI part....reenables interrupts 1374 */ 1375 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV); 1376 1377 return IRQ_HANDLED; 1378 } 1379 1380 static const struct snd_pcm_hardware snd_cs46xx_playback = 1381 { 1382 .info = (SNDRV_PCM_INFO_MMAP | 1383 SNDRV_PCM_INFO_INTERLEAVED | 1384 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ 1385 /*SNDRV_PCM_INFO_RESUME*/ | 1386 SNDRV_PCM_INFO_SYNC_APPLPTR), 1387 .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 | 1388 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | 1389 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE), 1390 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1391 .rate_min = 5500, 1392 .rate_max = 48000, 1393 .channels_min = 1, 1394 .channels_max = 2, 1395 .buffer_bytes_max = (256 * 1024), 1396 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, 1397 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, 1398 .periods_min = CS46XX_FRAGS, 1399 .periods_max = 1024, 1400 .fifo_size = 0, 1401 }; 1402 1403 static const struct snd_pcm_hardware snd_cs46xx_capture = 1404 { 1405 .info = (SNDRV_PCM_INFO_MMAP | 1406 SNDRV_PCM_INFO_INTERLEAVED | 1407 SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/ 1408 /*SNDRV_PCM_INFO_RESUME*/ | 1409 SNDRV_PCM_INFO_SYNC_APPLPTR), 1410 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1411 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1412 .rate_min = 5500, 1413 .rate_max = 48000, 1414 .channels_min = 2, 1415 .channels_max = 2, 1416 .buffer_bytes_max = (256 * 1024), 1417 .period_bytes_min = CS46XX_MIN_PERIOD_SIZE, 1418 .period_bytes_max = CS46XX_MAX_PERIOD_SIZE, 1419 .periods_min = CS46XX_FRAGS, 1420 .periods_max = 1024, 1421 .fifo_size = 0, 1422 }; 1423 1424 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1425 1426 static const unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 }; 1427 1428 static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = { 1429 .count = ARRAY_SIZE(period_sizes), 1430 .list = period_sizes, 1431 .mask = 0 1432 }; 1433 1434 #endif 1435 1436 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime) 1437 { 1438 kfree(runtime->private_data); 1439 } 1440 1441 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id) 1442 { 1443 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1444 struct snd_cs46xx_pcm * cpcm; 1445 struct snd_pcm_runtime *runtime = substream->runtime; 1446 1447 cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL); 1448 if (cpcm == NULL) 1449 return -ENOMEM; 1450 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 1451 PAGE_SIZE, &cpcm->hw_buf) < 0) { 1452 kfree(cpcm); 1453 return -ENOMEM; 1454 } 1455 1456 runtime->hw = snd_cs46xx_playback; 1457 runtime->private_data = cpcm; 1458 runtime->private_free = snd_cs46xx_pcm_free_substream; 1459 1460 cpcm->substream = substream; 1461 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1462 scoped_guard(mutex, &chip->spos_mutex) { 1463 cpcm->pcm_channel = NULL; 1464 cpcm->pcm_channel_id = pcm_channel_id; 1465 } 1466 1467 snd_pcm_hw_constraint_list(runtime, 0, 1468 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1469 &hw_constraints_period_sizes); 1470 #else 1471 chip->playback_pcm = cpcm; /* HACK */ 1472 #endif 1473 1474 if (chip->accept_valid) 1475 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; 1476 chip->active_ctrl(chip, 1); 1477 1478 return 0; 1479 } 1480 1481 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream) 1482 { 1483 dev_dbg(substream->pcm->card->dev, "open front channel\n"); 1484 return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL); 1485 } 1486 1487 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1488 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream) 1489 { 1490 dev_dbg(substream->pcm->card->dev, "open rear channel\n"); 1491 return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL); 1492 } 1493 1494 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream) 1495 { 1496 dev_dbg(substream->pcm->card->dev, "open center - LFE channel\n"); 1497 return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL); 1498 } 1499 1500 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream) 1501 { 1502 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1503 1504 dev_dbg(chip->card->dev, "open raw iec958 channel\n"); 1505 1506 scoped_guard(mutex, &chip->spos_mutex) { 1507 cs46xx_iec958_pre_open(chip); 1508 } 1509 1510 return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL); 1511 } 1512 1513 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream); 1514 1515 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream) 1516 { 1517 int err; 1518 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1519 1520 dev_dbg(chip->card->dev, "close raw iec958 channel\n"); 1521 1522 err = snd_cs46xx_playback_close(substream); 1523 1524 scoped_guard(mutex, &chip->spos_mutex) { 1525 cs46xx_iec958_post_close(chip); 1526 } 1527 1528 return err; 1529 } 1530 #endif 1531 1532 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream) 1533 { 1534 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1535 1536 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 1537 PAGE_SIZE, &chip->capt.hw_buf) < 0) 1538 return -ENOMEM; 1539 chip->capt.substream = substream; 1540 substream->runtime->hw = snd_cs46xx_capture; 1541 1542 if (chip->accept_valid) 1543 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; 1544 1545 chip->active_ctrl(chip, 1); 1546 1547 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1548 snd_pcm_hw_constraint_list(substream->runtime, 0, 1549 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1550 &hw_constraints_period_sizes); 1551 #endif 1552 return 0; 1553 } 1554 1555 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream) 1556 { 1557 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1558 struct snd_pcm_runtime *runtime = substream->runtime; 1559 struct snd_cs46xx_pcm * cpcm; 1560 1561 cpcm = runtime->private_data; 1562 1563 /* when playback_open fails, then cpcm can be NULL */ 1564 if (!cpcm) return -ENXIO; 1565 1566 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1567 scoped_guard(mutex, &chip->spos_mutex) { 1568 if (cpcm->pcm_channel) { 1569 cs46xx_dsp_destroy_pcm_channel(chip, cpcm->pcm_channel); 1570 cpcm->pcm_channel = NULL; 1571 } 1572 } 1573 #else 1574 chip->playback_pcm = NULL; 1575 #endif 1576 1577 cpcm->substream = NULL; 1578 snd_dma_free_pages(&cpcm->hw_buf); 1579 chip->active_ctrl(chip, -1); 1580 1581 return 0; 1582 } 1583 1584 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream) 1585 { 1586 struct snd_cs46xx *chip = snd_pcm_substream_chip(substream); 1587 1588 chip->capt.substream = NULL; 1589 snd_dma_free_pages(&chip->capt.hw_buf); 1590 chip->active_ctrl(chip, -1); 1591 1592 return 0; 1593 } 1594 1595 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1596 static const struct snd_pcm_ops snd_cs46xx_playback_rear_ops = { 1597 .open = snd_cs46xx_playback_open_rear, 1598 .close = snd_cs46xx_playback_close, 1599 .hw_params = snd_cs46xx_playback_hw_params, 1600 .hw_free = snd_cs46xx_playback_hw_free, 1601 .prepare = snd_cs46xx_playback_prepare, 1602 .trigger = snd_cs46xx_playback_trigger, 1603 .pointer = snd_cs46xx_playback_direct_pointer, 1604 }; 1605 1606 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = { 1607 .open = snd_cs46xx_playback_open_rear, 1608 .close = snd_cs46xx_playback_close, 1609 .hw_params = snd_cs46xx_playback_hw_params, 1610 .hw_free = snd_cs46xx_playback_hw_free, 1611 .prepare = snd_cs46xx_playback_prepare, 1612 .trigger = snd_cs46xx_playback_trigger, 1613 .pointer = snd_cs46xx_playback_indirect_pointer, 1614 .ack = snd_cs46xx_playback_transfer, 1615 }; 1616 1617 static const struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = { 1618 .open = snd_cs46xx_playback_open_clfe, 1619 .close = snd_cs46xx_playback_close, 1620 .hw_params = snd_cs46xx_playback_hw_params, 1621 .hw_free = snd_cs46xx_playback_hw_free, 1622 .prepare = snd_cs46xx_playback_prepare, 1623 .trigger = snd_cs46xx_playback_trigger, 1624 .pointer = snd_cs46xx_playback_direct_pointer, 1625 }; 1626 1627 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = { 1628 .open = snd_cs46xx_playback_open_clfe, 1629 .close = snd_cs46xx_playback_close, 1630 .hw_params = snd_cs46xx_playback_hw_params, 1631 .hw_free = snd_cs46xx_playback_hw_free, 1632 .prepare = snd_cs46xx_playback_prepare, 1633 .trigger = snd_cs46xx_playback_trigger, 1634 .pointer = snd_cs46xx_playback_indirect_pointer, 1635 .ack = snd_cs46xx_playback_transfer, 1636 }; 1637 1638 static const struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = { 1639 .open = snd_cs46xx_playback_open_iec958, 1640 .close = snd_cs46xx_playback_close_iec958, 1641 .hw_params = snd_cs46xx_playback_hw_params, 1642 .hw_free = snd_cs46xx_playback_hw_free, 1643 .prepare = snd_cs46xx_playback_prepare, 1644 .trigger = snd_cs46xx_playback_trigger, 1645 .pointer = snd_cs46xx_playback_direct_pointer, 1646 }; 1647 1648 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = { 1649 .open = snd_cs46xx_playback_open_iec958, 1650 .close = snd_cs46xx_playback_close_iec958, 1651 .hw_params = snd_cs46xx_playback_hw_params, 1652 .hw_free = snd_cs46xx_playback_hw_free, 1653 .prepare = snd_cs46xx_playback_prepare, 1654 .trigger = snd_cs46xx_playback_trigger, 1655 .pointer = snd_cs46xx_playback_indirect_pointer, 1656 .ack = snd_cs46xx_playback_transfer, 1657 }; 1658 1659 #endif 1660 1661 static const struct snd_pcm_ops snd_cs46xx_playback_ops = { 1662 .open = snd_cs46xx_playback_open, 1663 .close = snd_cs46xx_playback_close, 1664 .hw_params = snd_cs46xx_playback_hw_params, 1665 .hw_free = snd_cs46xx_playback_hw_free, 1666 .prepare = snd_cs46xx_playback_prepare, 1667 .trigger = snd_cs46xx_playback_trigger, 1668 .pointer = snd_cs46xx_playback_direct_pointer, 1669 }; 1670 1671 static const struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = { 1672 .open = snd_cs46xx_playback_open, 1673 .close = snd_cs46xx_playback_close, 1674 .hw_params = snd_cs46xx_playback_hw_params, 1675 .hw_free = snd_cs46xx_playback_hw_free, 1676 .prepare = snd_cs46xx_playback_prepare, 1677 .trigger = snd_cs46xx_playback_trigger, 1678 .pointer = snd_cs46xx_playback_indirect_pointer, 1679 .ack = snd_cs46xx_playback_transfer, 1680 }; 1681 1682 static const struct snd_pcm_ops snd_cs46xx_capture_ops = { 1683 .open = snd_cs46xx_capture_open, 1684 .close = snd_cs46xx_capture_close, 1685 .hw_params = snd_cs46xx_capture_hw_params, 1686 .hw_free = snd_cs46xx_capture_hw_free, 1687 .prepare = snd_cs46xx_capture_prepare, 1688 .trigger = snd_cs46xx_capture_trigger, 1689 .pointer = snd_cs46xx_capture_direct_pointer, 1690 }; 1691 1692 static const struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = { 1693 .open = snd_cs46xx_capture_open, 1694 .close = snd_cs46xx_capture_close, 1695 .hw_params = snd_cs46xx_capture_hw_params, 1696 .hw_free = snd_cs46xx_capture_hw_free, 1697 .prepare = snd_cs46xx_capture_prepare, 1698 .trigger = snd_cs46xx_capture_trigger, 1699 .pointer = snd_cs46xx_capture_indirect_pointer, 1700 .ack = snd_cs46xx_capture_transfer, 1701 }; 1702 1703 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1704 #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1) 1705 #else 1706 #define MAX_PLAYBACK_CHANNELS 1 1707 #endif 1708 1709 int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device) 1710 { 1711 struct snd_pcm *pcm; 1712 int err; 1713 1714 err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm); 1715 if (err < 0) 1716 return err; 1717 1718 pcm->private_data = chip; 1719 1720 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops); 1721 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops); 1722 1723 /* global setup */ 1724 pcm->info_flags = 0; 1725 strscpy(pcm->name, "CS46xx"); 1726 chip->pcm = pcm; 1727 1728 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1729 &chip->pci->dev, 1730 64*1024, 256*1024); 1731 1732 return 0; 1733 } 1734 1735 1736 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1737 int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device) 1738 { 1739 struct snd_pcm *pcm; 1740 int err; 1741 1742 err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm); 1743 if (err < 0) 1744 return err; 1745 1746 pcm->private_data = chip; 1747 1748 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops); 1749 1750 /* global setup */ 1751 pcm->info_flags = 0; 1752 strscpy(pcm->name, "CS46xx - Rear"); 1753 chip->pcm_rear = pcm; 1754 1755 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1756 &chip->pci->dev, 1757 64*1024, 256*1024); 1758 1759 return 0; 1760 } 1761 1762 int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device) 1763 { 1764 struct snd_pcm *pcm; 1765 int err; 1766 1767 err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm); 1768 if (err < 0) 1769 return err; 1770 1771 pcm->private_data = chip; 1772 1773 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops); 1774 1775 /* global setup */ 1776 pcm->info_flags = 0; 1777 strscpy(pcm->name, "CS46xx - Center LFE"); 1778 chip->pcm_center_lfe = pcm; 1779 1780 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1781 &chip->pci->dev, 1782 64*1024, 256*1024); 1783 1784 return 0; 1785 } 1786 1787 int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device) 1788 { 1789 struct snd_pcm *pcm; 1790 int err; 1791 1792 err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm); 1793 if (err < 0) 1794 return err; 1795 1796 pcm->private_data = chip; 1797 1798 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops); 1799 1800 /* global setup */ 1801 pcm->info_flags = 0; 1802 strscpy(pcm->name, "CS46xx - IEC958"); 1803 chip->pcm_iec958 = pcm; 1804 1805 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1806 &chip->pci->dev, 1807 64*1024, 256*1024); 1808 1809 return 0; 1810 } 1811 #endif 1812 1813 /* 1814 * Mixer routines 1815 */ 1816 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97) 1817 { 1818 struct snd_cs46xx *chip = ac97->private_data; 1819 1820 if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] && 1821 ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX])) 1822 return; 1823 1824 if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) { 1825 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL; 1826 chip->eapd_switch = NULL; 1827 } 1828 else 1829 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL; 1830 } 1831 1832 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol, 1833 struct snd_ctl_elem_info *uinfo) 1834 { 1835 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1836 uinfo->count = 2; 1837 uinfo->value.integer.min = 0; 1838 uinfo->value.integer.max = 0x7fff; 1839 return 0; 1840 } 1841 1842 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1843 { 1844 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1845 int reg = kcontrol->private_value; 1846 unsigned int val = snd_cs46xx_peek(chip, reg); 1847 ucontrol->value.integer.value[0] = 0xffff - (val >> 16); 1848 ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff); 1849 return 0; 1850 } 1851 1852 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1853 { 1854 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1855 int reg = kcontrol->private_value; 1856 unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 | 1857 (0xffff - ucontrol->value.integer.value[1])); 1858 unsigned int old = snd_cs46xx_peek(chip, reg); 1859 int change = (old != val); 1860 1861 if (change) { 1862 snd_cs46xx_poke(chip, reg, val); 1863 } 1864 1865 return change; 1866 } 1867 1868 #ifdef CONFIG_SND_CS46XX_NEW_DSP 1869 1870 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1871 { 1872 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1873 1874 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left; 1875 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right; 1876 1877 return 0; 1878 } 1879 1880 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1881 { 1882 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1883 int change = 0; 1884 1885 if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] || 1886 chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) { 1887 cs46xx_dsp_set_dac_volume(chip, 1888 ucontrol->value.integer.value[0], 1889 ucontrol->value.integer.value[1]); 1890 change = 1; 1891 } 1892 1893 return change; 1894 } 1895 1896 #if 0 1897 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1898 { 1899 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1900 1901 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left; 1902 ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right; 1903 return 0; 1904 } 1905 1906 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1907 { 1908 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1909 int change = 0; 1910 1911 if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] || 1912 chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) { 1913 cs46xx_dsp_set_iec958_volume (chip, 1914 ucontrol->value.integer.value[0], 1915 ucontrol->value.integer.value[1]); 1916 change = 1; 1917 } 1918 1919 return change; 1920 } 1921 #endif 1922 1923 #define snd_mixer_boolean_info snd_ctl_boolean_mono_info 1924 1925 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol, 1926 struct snd_ctl_elem_value *ucontrol) 1927 { 1928 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1929 int reg = kcontrol->private_value; 1930 1931 if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT) 1932 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); 1933 else 1934 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in; 1935 1936 return 0; 1937 } 1938 1939 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol, 1940 struct snd_ctl_elem_value *ucontrol) 1941 { 1942 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1943 int change, res; 1944 1945 switch (kcontrol->private_value) { 1946 case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT: 1947 scoped_guard(mutex, &chip->spos_mutex) { 1948 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED); 1949 if (ucontrol->value.integer.value[0] && !change) 1950 cs46xx_dsp_enable_spdif_out(chip); 1951 else if (change && !ucontrol->value.integer.value[0]) 1952 cs46xx_dsp_disable_spdif_out(chip); 1953 1954 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED)); 1955 } 1956 break; 1957 case CS46XX_MIXER_SPDIF_INPUT_ELEMENT: 1958 change = chip->dsp_spos_instance->spdif_status_in; 1959 if (ucontrol->value.integer.value[0] && !change) { 1960 cs46xx_dsp_enable_spdif_in(chip); 1961 /* restore volume */ 1962 } 1963 else if (change && !ucontrol->value.integer.value[0]) 1964 cs46xx_dsp_disable_spdif_in(chip); 1965 1966 res = (change != chip->dsp_spos_instance->spdif_status_in); 1967 break; 1968 default: 1969 res = -EINVAL; 1970 snd_BUG(); /* should never happen ... */ 1971 } 1972 1973 return res; 1974 } 1975 1976 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol, 1977 struct snd_ctl_elem_value *ucontrol) 1978 { 1979 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1980 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1981 1982 if (ins->adc_input != NULL) 1983 ucontrol->value.integer.value[0] = 1; 1984 else 1985 ucontrol->value.integer.value[0] = 0; 1986 1987 return 0; 1988 } 1989 1990 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol, 1991 struct snd_ctl_elem_value *ucontrol) 1992 { 1993 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 1994 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 1995 int change = 0; 1996 1997 if (ucontrol->value.integer.value[0] && !ins->adc_input) { 1998 cs46xx_dsp_enable_adc_capture(chip); 1999 change = 1; 2000 } else if (!ucontrol->value.integer.value[0] && ins->adc_input) { 2001 cs46xx_dsp_disable_adc_capture(chip); 2002 change = 1; 2003 } 2004 return change; 2005 } 2006 2007 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol, 2008 struct snd_ctl_elem_value *ucontrol) 2009 { 2010 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2011 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2012 2013 if (ins->pcm_input != NULL) 2014 ucontrol->value.integer.value[0] = 1; 2015 else 2016 ucontrol->value.integer.value[0] = 0; 2017 2018 return 0; 2019 } 2020 2021 2022 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol, 2023 struct snd_ctl_elem_value *ucontrol) 2024 { 2025 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2026 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2027 int change = 0; 2028 2029 if (ucontrol->value.integer.value[0] && !ins->pcm_input) { 2030 cs46xx_dsp_enable_pcm_capture(chip); 2031 change = 1; 2032 } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) { 2033 cs46xx_dsp_disable_pcm_capture(chip); 2034 change = 1; 2035 } 2036 2037 return change; 2038 } 2039 2040 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol, 2041 struct snd_ctl_elem_value *ucontrol) 2042 { 2043 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2044 2045 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 2046 2047 if (val1 & EGPIODR_GPOE0) 2048 ucontrol->value.integer.value[0] = 1; 2049 else 2050 ucontrol->value.integer.value[0] = 0; 2051 2052 return 0; 2053 } 2054 2055 /* 2056 * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial. 2057 */ 2058 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol, 2059 struct snd_ctl_elem_value *ucontrol) 2060 { 2061 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2062 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 2063 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); 2064 2065 if (ucontrol->value.integer.value[0]) { 2066 /* optical is default */ 2067 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 2068 EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */ 2069 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 2070 EGPIOPTR_GPPT0 | val2); /* open-drain on output */ 2071 } else { 2072 /* coaxial */ 2073 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */ 2074 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */ 2075 } 2076 2077 /* checking diff from the EGPIO direction register 2078 should be enough */ 2079 return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR)); 2080 } 2081 2082 2083 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2084 { 2085 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2086 uinfo->count = 1; 2087 return 0; 2088 } 2089 2090 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol, 2091 struct snd_ctl_elem_value *ucontrol) 2092 { 2093 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2094 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2095 2096 guard(mutex)(&chip->spos_mutex); 2097 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff); 2098 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff); 2099 ucontrol->value.iec958.status[2] = 0; 2100 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff); 2101 2102 return 0; 2103 } 2104 2105 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol, 2106 struct snd_ctl_elem_value *ucontrol) 2107 { 2108 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); 2109 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2110 unsigned int val; 2111 int change; 2112 2113 guard(mutex)(&chip->spos_mutex); 2114 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | 2115 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) | 2116 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | 2117 /* left and right validity bit */ 2118 (1 << 13) | (1 << 12); 2119 2120 2121 change = (unsigned int)ins->spdif_csuv_default != val; 2122 ins->spdif_csuv_default = val; 2123 2124 if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) ) 2125 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); 2126 2127 return change; 2128 } 2129 2130 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol, 2131 struct snd_ctl_elem_value *ucontrol) 2132 { 2133 ucontrol->value.iec958.status[0] = 0xff; 2134 ucontrol->value.iec958.status[1] = 0xff; 2135 ucontrol->value.iec958.status[2] = 0x00; 2136 ucontrol->value.iec958.status[3] = 0xff; 2137 return 0; 2138 } 2139 2140 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol, 2141 struct snd_ctl_elem_value *ucontrol) 2142 { 2143 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2144 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2145 2146 guard(mutex)(&chip->spos_mutex); 2147 ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff); 2148 ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff); 2149 ucontrol->value.iec958.status[2] = 0; 2150 ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff); 2151 2152 return 0; 2153 } 2154 2155 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol, 2156 struct snd_ctl_elem_value *ucontrol) 2157 { 2158 struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol); 2159 struct dsp_spos_instance * ins = chip->dsp_spos_instance; 2160 unsigned int val; 2161 int change; 2162 2163 guard(mutex)(&chip->spos_mutex); 2164 val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) | 2165 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) | 2166 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) | 2167 /* left and right validity bit */ 2168 (1 << 13) | (1 << 12); 2169 2170 2171 change = ins->spdif_csuv_stream != val; 2172 ins->spdif_csuv_stream = val; 2173 2174 if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN ) 2175 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val); 2176 2177 return change; 2178 } 2179 2180 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 2181 2182 2183 static const struct snd_kcontrol_new snd_cs46xx_controls[] = { 2184 { 2185 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2186 .name = "DAC Volume", 2187 .info = snd_cs46xx_vol_info, 2188 #ifndef CONFIG_SND_CS46XX_NEW_DSP 2189 .get = snd_cs46xx_vol_get, 2190 .put = snd_cs46xx_vol_put, 2191 .private_value = BA1_PVOL, 2192 #else 2193 .get = snd_cs46xx_vol_dac_get, 2194 .put = snd_cs46xx_vol_dac_put, 2195 #endif 2196 }, 2197 2198 { 2199 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2200 .name = "ADC Volume", 2201 .info = snd_cs46xx_vol_info, 2202 .get = snd_cs46xx_vol_get, 2203 .put = snd_cs46xx_vol_put, 2204 #ifndef CONFIG_SND_CS46XX_NEW_DSP 2205 .private_value = BA1_CVOL, 2206 #else 2207 .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2, 2208 #endif 2209 }, 2210 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2211 { 2212 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2213 .name = "ADC Capture Switch", 2214 .info = snd_mixer_boolean_info, 2215 .get = snd_cs46xx_adc_capture_get, 2216 .put = snd_cs46xx_adc_capture_put 2217 }, 2218 { 2219 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2220 .name = "DAC Capture Switch", 2221 .info = snd_mixer_boolean_info, 2222 .get = snd_cs46xx_pcm_capture_get, 2223 .put = snd_cs46xx_pcm_capture_put 2224 }, 2225 { 2226 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2227 .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH), 2228 .info = snd_mixer_boolean_info, 2229 .get = snd_cs46xx_iec958_get, 2230 .put = snd_cs46xx_iec958_put, 2231 .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT, 2232 }, 2233 { 2234 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2235 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH), 2236 .info = snd_mixer_boolean_info, 2237 .get = snd_cs46xx_iec958_get, 2238 .put = snd_cs46xx_iec958_put, 2239 .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT, 2240 }, 2241 #if 0 2242 /* Input IEC958 volume does not work for the moment. (Benny) */ 2243 { 2244 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2245 .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME), 2246 .info = snd_cs46xx_vol_info, 2247 .get = snd_cs46xx_vol_iec958_get, 2248 .put = snd_cs46xx_vol_iec958_put, 2249 .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2, 2250 }, 2251 #endif 2252 { 2253 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2254 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2255 .info = snd_cs46xx_spdif_info, 2256 .get = snd_cs46xx_spdif_default_get, 2257 .put = snd_cs46xx_spdif_default_put, 2258 }, 2259 { 2260 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2261 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), 2262 .info = snd_cs46xx_spdif_info, 2263 .get = snd_cs46xx_spdif_mask_get, 2264 .access = SNDRV_CTL_ELEM_ACCESS_READ 2265 }, 2266 { 2267 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2268 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2269 .info = snd_cs46xx_spdif_info, 2270 .get = snd_cs46xx_spdif_stream_get, 2271 .put = snd_cs46xx_spdif_stream_put 2272 }, 2273 2274 #endif 2275 }; 2276 2277 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2278 /* set primary cs4294 codec into Extended Audio Mode */ 2279 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol, 2280 struct snd_ctl_elem_value *ucontrol) 2281 { 2282 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2283 unsigned short val; 2284 val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE); 2285 ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1; 2286 return 0; 2287 } 2288 2289 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol, 2290 struct snd_ctl_elem_value *ucontrol) 2291 { 2292 struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol); 2293 return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], 2294 AC97_CSR_ACMODE, 0x200, 2295 ucontrol->value.integer.value[0] ? 0 : 0x200); 2296 } 2297 2298 static const struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = { 2299 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2300 .name = "Duplicate Front", 2301 .info = snd_mixer_boolean_info, 2302 .get = snd_cs46xx_front_dup_get, 2303 .put = snd_cs46xx_front_dup_put, 2304 }; 2305 #endif 2306 2307 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2308 /* Only available on the Hercules Game Theater XP soundcard */ 2309 static const struct snd_kcontrol_new snd_hercules_controls[] = { 2310 { 2311 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2312 .name = "Optical/Coaxial SPDIF Input Switch", 2313 .info = snd_mixer_boolean_info, 2314 .get = snd_herc_spdif_select_get, 2315 .put = snd_herc_spdif_select_put, 2316 }, 2317 }; 2318 2319 2320 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97) 2321 { 2322 unsigned long end_time; 2323 int err; 2324 2325 /* reset to defaults */ 2326 snd_ac97_write(ac97, AC97_RESET, 0); 2327 2328 /* set the desired CODEC mode */ 2329 if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) { 2330 dev_dbg(ac97->bus->card->dev, "CODEC1 mode %04x\n", 0x0); 2331 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0); 2332 } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) { 2333 dev_dbg(ac97->bus->card->dev, "CODEC2 mode %04x\n", 0x3); 2334 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3); 2335 } else { 2336 snd_BUG(); /* should never happen ... */ 2337 } 2338 2339 udelay(50); 2340 2341 /* it's necessary to wait awhile until registers are accessible after RESET */ 2342 /* because the PCM or MASTER volume registers can be modified, */ 2343 /* the REC_GAIN register is used for tests */ 2344 end_time = jiffies + HZ; 2345 do { 2346 unsigned short ext_mid; 2347 2348 /* use preliminary reads to settle the communication */ 2349 snd_ac97_read(ac97, AC97_RESET); 2350 snd_ac97_read(ac97, AC97_VENDOR_ID1); 2351 snd_ac97_read(ac97, AC97_VENDOR_ID2); 2352 /* modem? */ 2353 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID); 2354 if (ext_mid != 0xffff && (ext_mid & 1) != 0) 2355 return; 2356 2357 /* test if we can write to the record gain volume register */ 2358 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05); 2359 err = snd_ac97_read(ac97, AC97_REC_GAIN); 2360 if (err == 0x8a05) 2361 return; 2362 2363 msleep(10); 2364 } while (time_after_eq(end_time, jiffies)); 2365 2366 dev_err(ac97->bus->card->dev, 2367 "CS46xx secondary codec doesn't respond!\n"); 2368 } 2369 #endif 2370 2371 static int cs46xx_detect_codec(struct snd_cs46xx *chip, int codec) 2372 { 2373 int idx, err; 2374 struct snd_ac97_template ac97; 2375 2376 memset(&ac97, 0, sizeof(ac97)); 2377 ac97.private_data = chip; 2378 ac97.private_free = snd_cs46xx_mixer_free_ac97; 2379 ac97.num = codec; 2380 if (chip->amplifier_ctrl == amp_voyetra) 2381 ac97.scaps = AC97_SCAP_INV_EAPD; 2382 2383 if (codec == CS46XX_SECONDARY_CODEC_INDEX) { 2384 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec); 2385 udelay(10); 2386 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) { 2387 dev_dbg(chip->card->dev, 2388 "secondary codec not present\n"); 2389 return -ENXIO; 2390 } 2391 } 2392 2393 snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec); 2394 for (idx = 0; idx < 100; ++idx) { 2395 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) { 2396 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]); 2397 return err; 2398 } 2399 msleep(10); 2400 } 2401 dev_dbg(chip->card->dev, "codec %d detection timeout\n", codec); 2402 return -ENXIO; 2403 } 2404 2405 int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device) 2406 { 2407 struct snd_card *card = chip->card; 2408 int err; 2409 unsigned int idx; 2410 static const struct snd_ac97_bus_ops ops = { 2411 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2412 .reset = snd_cs46xx_codec_reset, 2413 #endif 2414 .write = snd_cs46xx_ac97_write, 2415 .read = snd_cs46xx_ac97_read, 2416 }; 2417 2418 /* detect primary codec */ 2419 chip->nr_ac97_codecs = 0; 2420 dev_dbg(chip->card->dev, "detecting primary codec\n"); 2421 err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus); 2422 if (err < 0) 2423 return err; 2424 2425 if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0) 2426 return -ENXIO; 2427 chip->nr_ac97_codecs = 1; 2428 2429 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2430 dev_dbg(chip->card->dev, "detecting secondary codec\n"); 2431 /* try detect a secondary codec */ 2432 if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX)) 2433 chip->nr_ac97_codecs = 2; 2434 #endif /* CONFIG_SND_CS46XX_NEW_DSP */ 2435 2436 /* add cs4630 mixer controls */ 2437 for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) { 2438 struct snd_kcontrol *kctl; 2439 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip); 2440 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM) 2441 kctl->id.device = spdif_device; 2442 err = snd_ctl_add(card, kctl); 2443 if (err < 0) 2444 return err; 2445 } 2446 2447 /* get EAPD mixer switch (for voyetra hack) */ 2448 chip->eapd_switch = snd_ctl_find_id_mixer(chip->card, 2449 "External Amplifier"); 2450 2451 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2452 if (chip->nr_ac97_codecs == 1) { 2453 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff; 2454 if ((id2 & 0xfff0) == 0x5920) { /* CS4294 and CS4298 */ 2455 err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip)); 2456 if (err < 0) 2457 return err; 2458 snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], 2459 AC97_CSR_ACMODE, 0x200); 2460 } 2461 } 2462 /* do soundcard specific mixer setup */ 2463 if (chip->mixer_init) { 2464 dev_dbg(chip->card->dev, "calling chip->mixer_init(chip);\n"); 2465 chip->mixer_init(chip); 2466 } 2467 #endif 2468 2469 /* turn on amplifier */ 2470 chip->amplifier_ctrl(chip, 1); 2471 2472 return 0; 2473 } 2474 2475 /* 2476 * RawMIDI interface 2477 */ 2478 2479 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip) 2480 { 2481 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST); 2482 udelay(100); 2483 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2484 } 2485 2486 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream) 2487 { 2488 struct snd_cs46xx *chip = substream->rmidi->private_data; 2489 2490 chip->active_ctrl(chip, 1); 2491 guard(spinlock_irq)(&chip->reg_lock); 2492 chip->uartm |= CS46XX_MODE_INPUT; 2493 chip->midcr |= MIDCR_RXE; 2494 chip->midi_input = substream; 2495 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { 2496 snd_cs46xx_midi_reset(chip); 2497 } else { 2498 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2499 } 2500 return 0; 2501 } 2502 2503 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream) 2504 { 2505 struct snd_cs46xx *chip = substream->rmidi->private_data; 2506 2507 scoped_guard(spinlock_irq, &chip->reg_lock) { 2508 chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE); 2509 chip->midi_input = NULL; 2510 if (!(chip->uartm & CS46XX_MODE_OUTPUT)) { 2511 snd_cs46xx_midi_reset(chip); 2512 } else { 2513 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2514 } 2515 chip->uartm &= ~CS46XX_MODE_INPUT; 2516 } 2517 chip->active_ctrl(chip, -1); 2518 return 0; 2519 } 2520 2521 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream) 2522 { 2523 struct snd_cs46xx *chip = substream->rmidi->private_data; 2524 2525 chip->active_ctrl(chip, 1); 2526 2527 guard(spinlock_irq)(&chip->reg_lock); 2528 chip->uartm |= CS46XX_MODE_OUTPUT; 2529 chip->midcr |= MIDCR_TXE; 2530 chip->midi_output = substream; 2531 if (!(chip->uartm & CS46XX_MODE_INPUT)) { 2532 snd_cs46xx_midi_reset(chip); 2533 } else { 2534 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2535 } 2536 return 0; 2537 } 2538 2539 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream) 2540 { 2541 struct snd_cs46xx *chip = substream->rmidi->private_data; 2542 2543 scoped_guard(spinlock_irq, &chip->reg_lock) { 2544 chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE); 2545 chip->midi_output = NULL; 2546 if (!(chip->uartm & CS46XX_MODE_INPUT)) { 2547 snd_cs46xx_midi_reset(chip); 2548 } else { 2549 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2550 } 2551 chip->uartm &= ~CS46XX_MODE_OUTPUT; 2552 } 2553 chip->active_ctrl(chip, -1); 2554 return 0; 2555 } 2556 2557 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 2558 { 2559 struct snd_cs46xx *chip = substream->rmidi->private_data; 2560 2561 guard(spinlock_irqsave)(&chip->reg_lock); 2562 if (up) { 2563 if ((chip->midcr & MIDCR_RIE) == 0) { 2564 chip->midcr |= MIDCR_RIE; 2565 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2566 } 2567 } else { 2568 if (chip->midcr & MIDCR_RIE) { 2569 chip->midcr &= ~MIDCR_RIE; 2570 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2571 } 2572 } 2573 } 2574 2575 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 2576 { 2577 struct snd_cs46xx *chip = substream->rmidi->private_data; 2578 unsigned char byte; 2579 2580 guard(spinlock_irqsave)(&chip->reg_lock); 2581 if (up) { 2582 if ((chip->midcr & MIDCR_TIE) == 0) { 2583 chip->midcr |= MIDCR_TIE; 2584 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 2585 while ((chip->midcr & MIDCR_TIE) && 2586 (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) { 2587 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 2588 chip->midcr &= ~MIDCR_TIE; 2589 } else { 2590 snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte); 2591 } 2592 } 2593 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2594 } 2595 } else { 2596 if (chip->midcr & MIDCR_TIE) { 2597 chip->midcr &= ~MIDCR_TIE; 2598 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr); 2599 } 2600 } 2601 } 2602 2603 static const struct snd_rawmidi_ops snd_cs46xx_midi_output = 2604 { 2605 .open = snd_cs46xx_midi_output_open, 2606 .close = snd_cs46xx_midi_output_close, 2607 .trigger = snd_cs46xx_midi_output_trigger, 2608 }; 2609 2610 static const struct snd_rawmidi_ops snd_cs46xx_midi_input = 2611 { 2612 .open = snd_cs46xx_midi_input_open, 2613 .close = snd_cs46xx_midi_input_close, 2614 .trigger = snd_cs46xx_midi_input_trigger, 2615 }; 2616 2617 int snd_cs46xx_midi(struct snd_cs46xx *chip, int device) 2618 { 2619 struct snd_rawmidi *rmidi; 2620 int err; 2621 2622 err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi); 2623 if (err < 0) 2624 return err; 2625 strscpy(rmidi->name, "CS46XX"); 2626 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output); 2627 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input); 2628 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; 2629 rmidi->private_data = chip; 2630 chip->rmidi = rmidi; 2631 return 0; 2632 } 2633 2634 2635 /* 2636 * gameport interface 2637 */ 2638 2639 #if IS_REACHABLE(CONFIG_GAMEPORT) 2640 2641 static void snd_cs46xx_gameport_trigger(struct gameport *gameport) 2642 { 2643 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2644 2645 if (snd_BUG_ON(!chip)) 2646 return; 2647 snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF); 2648 } 2649 2650 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport) 2651 { 2652 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2653 2654 if (snd_BUG_ON(!chip)) 2655 return 0; 2656 return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io); 2657 } 2658 2659 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons) 2660 { 2661 struct snd_cs46xx *chip = gameport_get_port_data(gameport); 2662 unsigned js1, js2, jst; 2663 2664 if (snd_BUG_ON(!chip)) 2665 return 0; 2666 2667 js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1); 2668 js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2); 2669 jst = snd_cs46xx_peekBA0(chip, BA0_JSPT); 2670 2671 *buttons = (~jst >> 4) & 0x0F; 2672 2673 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; 2674 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; 2675 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; 2676 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; 2677 2678 for(jst=0;jst<4;++jst) 2679 if(axes[jst]==0xFFFF) axes[jst] = -1; 2680 return 0; 2681 } 2682 2683 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode) 2684 { 2685 switch (mode) { 2686 case GAMEPORT_MODE_COOKED: 2687 return 0; 2688 case GAMEPORT_MODE_RAW: 2689 return 0; 2690 default: 2691 return -1; 2692 } 2693 return 0; 2694 } 2695 2696 int snd_cs46xx_gameport(struct snd_cs46xx *chip) 2697 { 2698 struct gameport *gp; 2699 2700 chip->gameport = gp = gameport_allocate_port(); 2701 if (!gp) { 2702 dev_err(chip->card->dev, 2703 "cannot allocate memory for gameport\n"); 2704 return -ENOMEM; 2705 } 2706 2707 gameport_set_name(gp, "CS46xx Gameport"); 2708 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 2709 gameport_set_dev_parent(gp, &chip->pci->dev); 2710 gameport_set_port_data(gp, chip); 2711 2712 gp->open = snd_cs46xx_gameport_open; 2713 gp->read = snd_cs46xx_gameport_read; 2714 gp->trigger = snd_cs46xx_gameport_trigger; 2715 gp->cooked_read = snd_cs46xx_gameport_cooked_read; 2716 2717 snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ? 2718 snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); 2719 2720 gameport_register_port(gp); 2721 2722 return 0; 2723 } 2724 2725 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) 2726 { 2727 if (chip->gameport) { 2728 gameport_unregister_port(chip->gameport); 2729 chip->gameport = NULL; 2730 } 2731 } 2732 #else 2733 int snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; } 2734 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { } 2735 #endif /* CONFIG_GAMEPORT */ 2736 2737 #ifdef CONFIG_SND_PROC_FS 2738 /* 2739 * proc interface 2740 */ 2741 2742 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry, 2743 void *file_private_data, 2744 struct file *file, char __user *buf, 2745 size_t count, loff_t pos) 2746 { 2747 struct snd_cs46xx_region *region = entry->private_data; 2748 2749 if (copy_to_user_fromio(buf, region->remap_addr + pos, count)) 2750 return -EFAULT; 2751 return count; 2752 } 2753 2754 static const struct snd_info_entry_ops snd_cs46xx_proc_io_ops = { 2755 .read = snd_cs46xx_io_read, 2756 }; 2757 2758 static int snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip) 2759 { 2760 struct snd_info_entry *entry; 2761 int idx; 2762 2763 for (idx = 0; idx < 5; idx++) { 2764 struct snd_cs46xx_region *region = &chip->region.idx[idx]; 2765 if (! snd_card_proc_new(card, region->name, &entry)) { 2766 entry->content = SNDRV_INFO_CONTENT_DATA; 2767 entry->private_data = chip; 2768 entry->c.ops = &snd_cs46xx_proc_io_ops; 2769 entry->size = region->size; 2770 entry->mode = S_IFREG | 0400; 2771 } 2772 } 2773 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2774 cs46xx_dsp_proc_init(card, chip); 2775 #endif 2776 return 0; 2777 } 2778 2779 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip) 2780 { 2781 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2782 cs46xx_dsp_proc_done(chip); 2783 #endif 2784 return 0; 2785 } 2786 #else /* !CONFIG_SND_PROC_FS */ 2787 #define snd_cs46xx_proc_init(card, chip) 2788 #define snd_cs46xx_proc_done(chip) 2789 #endif 2790 2791 /* 2792 * stop the h/w 2793 */ 2794 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip) 2795 { 2796 unsigned int tmp; 2797 2798 tmp = snd_cs46xx_peek(chip, BA1_PFIE); 2799 tmp &= ~0x0000f03f; 2800 tmp |= 0x00000010; 2801 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */ 2802 2803 tmp = snd_cs46xx_peek(chip, BA1_CIE); 2804 tmp &= ~0x0000003f; 2805 tmp |= 0x00000011; 2806 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */ 2807 2808 /* 2809 * Stop playback DMA. 2810 */ 2811 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 2812 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); 2813 2814 /* 2815 * Stop capture DMA. 2816 */ 2817 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 2818 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 2819 2820 /* 2821 * Reset the processor. 2822 */ 2823 snd_cs46xx_reset(chip); 2824 2825 snd_cs46xx_proc_stop(chip); 2826 2827 /* 2828 * Power down the PLL. 2829 */ 2830 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); 2831 2832 /* 2833 * Turn off the Processor by turning off the software clock enable flag in 2834 * the clock control register. 2835 */ 2836 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; 2837 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 2838 } 2839 2840 2841 static void snd_cs46xx_free(struct snd_card *card) 2842 { 2843 struct snd_cs46xx *chip = card->private_data; 2844 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2845 int idx; 2846 #endif 2847 2848 if (chip->active_ctrl) 2849 chip->active_ctrl(chip, 1); 2850 2851 snd_cs46xx_remove_gameport(chip); 2852 2853 if (chip->amplifier_ctrl) 2854 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */ 2855 2856 snd_cs46xx_proc_done(chip); 2857 2858 snd_cs46xx_hw_stop(chip); 2859 2860 if (chip->active_ctrl) 2861 chip->active_ctrl(chip, -chip->amplifier); 2862 2863 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2864 if (chip->dsp_spos_instance) { 2865 cs46xx_dsp_spos_destroy(chip); 2866 chip->dsp_spos_instance = NULL; 2867 } 2868 for (idx = 0; idx < CS46XX_DSP_MODULES; idx++) 2869 free_module_desc(chip->modules[idx]); 2870 #else 2871 vfree(chip->ba1); 2872 #endif 2873 } 2874 2875 /* 2876 * initialize chip 2877 */ 2878 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip) 2879 { 2880 int timeout; 2881 2882 /* 2883 * First, blast the clock control register to zero so that the PLL starts 2884 * out in a known state, and blast the master serial port control register 2885 * to zero so that the serial ports also start out in a known state. 2886 */ 2887 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0); 2888 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0); 2889 2890 /* 2891 * If we are in AC97 mode, then we must set the part to a host controlled 2892 * AC-link. Otherwise, we won't be able to bring up the link. 2893 */ 2894 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2895 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 | 2896 SERACC_TWO_CODECS); /* 2.00 dual codecs */ 2897 /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */ 2898 #else 2899 snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */ 2900 #endif 2901 2902 /* 2903 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 2904 * spec) and then drive it high. This is done for non AC97 modes since 2905 * there might be logic external to the CS461x that uses the ARST# line 2906 * for a reset. 2907 */ 2908 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0); 2909 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2910 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0); 2911 #endif 2912 udelay(50); 2913 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN); 2914 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2915 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN); 2916 #endif 2917 2918 /* 2919 * The first thing we do here is to enable sync generation. As soon 2920 * as we start receiving bit clock, we'll start producing the SYNC 2921 * signal. 2922 */ 2923 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN); 2924 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2925 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN); 2926 #endif 2927 2928 /* 2929 * Now wait for a short while to allow the AC97 part to start 2930 * generating bit clock (so we don't try to start the PLL without an 2931 * input clock). 2932 */ 2933 mdelay(10); 2934 2935 /* 2936 * Set the serial port timing configuration, so that 2937 * the clock control circuit gets its clock from the correct place. 2938 */ 2939 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97); 2940 2941 /* 2942 * Write the selected clock control setup to the hardware. Do not turn on 2943 * SWCE yet (if requested), so that the devices clocked by the output of 2944 * PLL are not clocked until the PLL is stable. 2945 */ 2946 snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ); 2947 snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a); 2948 snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8); 2949 2950 /* 2951 * Power up the PLL. 2952 */ 2953 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP); 2954 2955 /* 2956 * Wait until the PLL has stabilized. 2957 */ 2958 msleep(100); 2959 2960 /* 2961 * Turn on clocking of the core so that we can setup the serial ports. 2962 */ 2963 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE); 2964 2965 /* 2966 * Enable FIFO Host Bypass 2967 */ 2968 snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP); 2969 2970 /* 2971 * Fill the serial port FIFOs with silence. 2972 */ 2973 snd_cs46xx_clear_serial_FIFOs(chip); 2974 2975 /* 2976 * Set the serial port FIFO pointer to the first sample in the FIFO. 2977 */ 2978 /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */ 2979 2980 /* 2981 * Write the serial port configuration to the part. The master 2982 * enable bit is not set until all other values have been written. 2983 */ 2984 snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN); 2985 snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN); 2986 snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE); 2987 2988 2989 #ifdef CONFIG_SND_CS46XX_NEW_DSP 2990 snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN); 2991 snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0); 2992 snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0); 2993 snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0); 2994 snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1); 2995 #endif 2996 2997 mdelay(5); 2998 2999 3000 /* 3001 * Wait for the codec ready signal from the AC97 codec. 3002 */ 3003 timeout = 150; 3004 while (timeout-- > 0) { 3005 /* 3006 * Read the AC97 status register to see if we've seen a CODEC READY 3007 * signal from the AC97 codec. 3008 */ 3009 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY) 3010 goto ok1; 3011 msleep(10); 3012 } 3013 3014 3015 dev_err(chip->card->dev, 3016 "create - never read codec ready from AC'97\n"); 3017 dev_err(chip->card->dev, 3018 "it is not probably bug, try to use CS4236 driver\n"); 3019 return -EIO; 3020 ok1: 3021 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3022 { 3023 int count; 3024 for (count = 0; count < 150; count++) { 3025 /* First, we want to wait for a short time. */ 3026 udelay(25); 3027 3028 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY) 3029 break; 3030 } 3031 3032 /* 3033 * Make sure CODEC is READY. 3034 */ 3035 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)) 3036 dev_dbg(chip->card->dev, 3037 "never read card ready from secondary AC'97\n"); 3038 } 3039 #endif 3040 3041 /* 3042 * Assert the vaid frame signal so that we can start sending commands 3043 * to the AC97 codec. 3044 */ 3045 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 3046 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3047 snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); 3048 #endif 3049 3050 3051 /* 3052 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 3053 * the codec is pumping ADC data across the AC-link. 3054 */ 3055 timeout = 150; 3056 while (timeout-- > 0) { 3057 /* 3058 * Read the input slot valid register and see if input slots 3 and 3059 * 4 are valid yet. 3060 */ 3061 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4)) 3062 goto ok2; 3063 msleep(10); 3064 } 3065 3066 #ifndef CONFIG_SND_CS46XX_NEW_DSP 3067 dev_err(chip->card->dev, 3068 "create - never read ISV3 & ISV4 from AC'97\n"); 3069 return -EIO; 3070 #else 3071 /* This may happen on a cold boot with a Terratec SiXPack 5.1. 3072 Reloading the driver may help, if there's other soundcards 3073 with the same problem I would like to know. (Benny) */ 3074 3075 dev_err(chip->card->dev, "never read ISV3 & ISV4 from AC'97\n"); 3076 dev_err(chip->card->dev, 3077 "Try reloading the ALSA driver, if you find something\n"); 3078 dev_err(chip->card->dev, 3079 "broken or not working on your soundcard upon\n"); 3080 dev_err(chip->card->dev, 3081 "this message please report to alsa-devel@alsa-project.org\n"); 3082 3083 return -EIO; 3084 #endif 3085 ok2: 3086 3087 /* 3088 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 3089 * commense the transfer of digital audio data to the AC97 codec. 3090 */ 3091 3092 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); 3093 3094 3095 /* 3096 * Power down the DAC and ADC. We will power them up (if) when we need 3097 * them. 3098 */ 3099 /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */ 3100 3101 /* 3102 * Turn off the Processor by turning off the software clock enable flag in 3103 * the clock control register. 3104 */ 3105 /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */ 3106 /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */ 3107 3108 return 0; 3109 } 3110 3111 /* 3112 * start and load DSP 3113 */ 3114 3115 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip) 3116 { 3117 unsigned int tmp; 3118 3119 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM); 3120 3121 tmp = snd_cs46xx_peek(chip, BA1_PFIE); 3122 tmp &= ~0x0000f03f; 3123 snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */ 3124 3125 tmp = snd_cs46xx_peek(chip, BA1_CIE); 3126 tmp &= ~0x0000003f; 3127 tmp |= 0x00000001; 3128 snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */ 3129 } 3130 3131 int snd_cs46xx_start_dsp(struct snd_cs46xx *chip) 3132 { 3133 unsigned int tmp; 3134 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3135 int i; 3136 #endif 3137 int err; 3138 3139 /* 3140 * Reset the processor. 3141 */ 3142 snd_cs46xx_reset(chip); 3143 /* 3144 * Download the image to the processor. 3145 */ 3146 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3147 for (i = 0; i < CS46XX_DSP_MODULES; i++) { 3148 err = load_firmware(chip, &chip->modules[i], module_names[i]); 3149 if (err < 0) { 3150 dev_err(chip->card->dev, "firmware load error [%s]\n", 3151 module_names[i]); 3152 return err; 3153 } 3154 err = cs46xx_dsp_load_module(chip, chip->modules[i]); 3155 if (err < 0) { 3156 dev_err(chip->card->dev, "image download error [%s]\n", 3157 module_names[i]); 3158 return err; 3159 } 3160 } 3161 3162 if (cs46xx_dsp_scb_and_task_init(chip) < 0) 3163 return -EIO; 3164 #else 3165 err = load_firmware(chip); 3166 if (err < 0) 3167 return err; 3168 3169 /* old image */ 3170 err = snd_cs46xx_download_image(chip); 3171 if (err < 0) { 3172 dev_err(chip->card->dev, "image download error\n"); 3173 return err; 3174 } 3175 3176 /* 3177 * Stop playback DMA. 3178 */ 3179 tmp = snd_cs46xx_peek(chip, BA1_PCTL); 3180 chip->play_ctl = tmp & 0xffff0000; 3181 snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff); 3182 #endif 3183 3184 /* 3185 * Stop capture DMA. 3186 */ 3187 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 3188 chip->capt.ctl = tmp & 0x0000ffff; 3189 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 3190 3191 mdelay(5); 3192 3193 snd_cs46xx_set_play_sample_rate(chip, 8000); 3194 snd_cs46xx_set_capture_sample_rate(chip, 8000); 3195 3196 snd_cs46xx_proc_start(chip); 3197 3198 cs46xx_enable_stream_irqs(chip); 3199 3200 #ifndef CONFIG_SND_CS46XX_NEW_DSP 3201 /* set the attenuation to 0dB */ 3202 snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000); 3203 snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000); 3204 #endif 3205 3206 return 0; 3207 } 3208 3209 3210 /* 3211 * AMP control - null AMP 3212 */ 3213 3214 static void amp_none(struct snd_cs46xx *chip, int change) 3215 { 3216 } 3217 3218 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3219 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip) 3220 { 3221 3222 u32 idx, valid_slots,tmp,powerdown = 0; 3223 u16 modem_power,pin_config,logic_type; 3224 3225 dev_dbg(chip->card->dev, "cs46xx_setup_eapd_slot()+\n"); 3226 3227 /* 3228 * See if the devices are powered down. If so, we must power them up first 3229 * or they will not respond. 3230 */ 3231 tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1); 3232 3233 if (!(tmp & CLKCR1_SWCE)) { 3234 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE); 3235 powerdown = 1; 3236 } 3237 3238 /* 3239 * Clear PRA. The Bonzo chip will be used for GPIO not for modem 3240 * stuff. 3241 */ 3242 if(chip->nr_ac97_codecs != 2) { 3243 dev_err(chip->card->dev, 3244 "cs46xx_setup_eapd_slot() - no secondary codec configured\n"); 3245 return -EINVAL; 3246 } 3247 3248 modem_power = snd_cs46xx_codec_read (chip, 3249 AC97_EXTENDED_MSTATUS, 3250 CS46XX_SECONDARY_CODEC_INDEX); 3251 modem_power &=0xFEFF; 3252 3253 snd_cs46xx_codec_write(chip, 3254 AC97_EXTENDED_MSTATUS, modem_power, 3255 CS46XX_SECONDARY_CODEC_INDEX); 3256 3257 /* 3258 * Set GPIO pin's 7 and 8 so that they are configured for output. 3259 */ 3260 pin_config = snd_cs46xx_codec_read (chip, 3261 AC97_GPIO_CFG, 3262 CS46XX_SECONDARY_CODEC_INDEX); 3263 pin_config &=0x27F; 3264 3265 snd_cs46xx_codec_write(chip, 3266 AC97_GPIO_CFG, pin_config, 3267 CS46XX_SECONDARY_CODEC_INDEX); 3268 3269 /* 3270 * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic. 3271 */ 3272 3273 logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY, 3274 CS46XX_SECONDARY_CODEC_INDEX); 3275 logic_type &=0x27F; 3276 3277 snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type, 3278 CS46XX_SECONDARY_CODEC_INDEX); 3279 3280 valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV); 3281 valid_slots |= 0x200; 3282 snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots); 3283 3284 if ( cs46xx_wait_for_fifo(chip,1) ) { 3285 dev_dbg(chip->card->dev, "FIFO is busy\n"); 3286 3287 return -EINVAL; 3288 } 3289 3290 /* 3291 * Fill slots 12 with the correct value for the GPIO pins. 3292 */ 3293 for(idx = 0x90; idx <= 0x9F; idx++) { 3294 /* 3295 * Initialize the fifo so that bits 7 and 8 are on. 3296 * 3297 * Remember that the GPIO pins in bonzo are shifted by 4 bits to 3298 * the left. 0x1800 corresponds to bits 7 and 8. 3299 */ 3300 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800); 3301 3302 /* 3303 * Wait for command to complete 3304 */ 3305 if ( cs46xx_wait_for_fifo(chip,200) ) { 3306 dev_dbg(chip->card->dev, 3307 "failed waiting for FIFO at addr (%02X)\n", 3308 idx); 3309 3310 return -EINVAL; 3311 } 3312 3313 /* 3314 * Write the serial port FIFO index. 3315 */ 3316 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx); 3317 3318 /* 3319 * Tell the serial port to load the new value into the FIFO location. 3320 */ 3321 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC); 3322 } 3323 3324 /* wait for last command to complete */ 3325 cs46xx_wait_for_fifo(chip,200); 3326 3327 /* 3328 * Now, if we powered up the devices, then power them back down again. 3329 * This is kinda ugly, but should never happen. 3330 */ 3331 if (powerdown) 3332 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); 3333 3334 return 0; 3335 } 3336 #endif 3337 3338 /* 3339 * Crystal EAPD mode 3340 */ 3341 3342 static void amp_voyetra(struct snd_cs46xx *chip, int change) 3343 { 3344 /* Manage the EAPD bit on the Crystal 4297 3345 and the Analog AD1885 */ 3346 3347 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3348 int old = chip->amplifier; 3349 #endif 3350 int oval, val; 3351 3352 chip->amplifier += change; 3353 oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN, 3354 CS46XX_PRIMARY_CODEC_INDEX); 3355 val = oval; 3356 if (chip->amplifier) { 3357 /* Turn the EAPD amp on */ 3358 val |= 0x8000; 3359 } else { 3360 /* Turn the EAPD amp off */ 3361 val &= ~0x8000; 3362 } 3363 if (val != oval) { 3364 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val, 3365 CS46XX_PRIMARY_CODEC_INDEX); 3366 if (chip->eapd_switch) 3367 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 3368 &chip->eapd_switch->id); 3369 } 3370 3371 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3372 if (chip->amplifier && !old) { 3373 voyetra_setup_eapd_slot(chip); 3374 } 3375 #endif 3376 } 3377 3378 static void hercules_init(struct snd_cs46xx *chip) 3379 { 3380 /* default: AMP off, and SPDIF input optical */ 3381 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); 3382 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); 3383 } 3384 3385 3386 /* 3387 * Game Theatre XP card - EGPIO[2] is used to enable the external amp. 3388 */ 3389 static void amp_hercules(struct snd_cs46xx *chip, int change) 3390 { 3391 int old = chip->amplifier; 3392 int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR); 3393 int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR); 3394 3395 chip->amplifier += change; 3396 if (chip->amplifier && !old) { 3397 dev_dbg(chip->card->dev, "Hercules amplifier ON\n"); 3398 3399 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, 3400 EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */ 3401 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, 3402 EGPIOPTR_GPPT2 | val2); /* open-drain on output */ 3403 } else if (old && !chip->amplifier) { 3404 dev_dbg(chip->card->dev, "Hercules amplifier OFF\n"); 3405 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */ 3406 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */ 3407 } 3408 } 3409 3410 static void voyetra_mixer_init (struct snd_cs46xx *chip) 3411 { 3412 dev_dbg(chip->card->dev, "initializing Voyetra mixer\n"); 3413 3414 /* Enable SPDIF out */ 3415 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0); 3416 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0); 3417 } 3418 3419 static void hercules_mixer_init (struct snd_cs46xx *chip) 3420 { 3421 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3422 unsigned int idx; 3423 int err; 3424 struct snd_card *card = chip->card; 3425 #endif 3426 3427 /* set EGPIO to default */ 3428 hercules_init(chip); 3429 3430 dev_dbg(chip->card->dev, "initializing Hercules mixer\n"); 3431 3432 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3433 if (chip->in_suspend) 3434 return; 3435 3436 for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) { 3437 struct snd_kcontrol *kctl; 3438 3439 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip); 3440 err = snd_ctl_add(card, kctl); 3441 if (err < 0) { 3442 dev_err(card->dev, 3443 "failed to initialize Hercules mixer (%d)\n", 3444 err); 3445 break; 3446 } 3447 } 3448 #endif 3449 } 3450 3451 3452 #if 0 3453 /* 3454 * Untested 3455 */ 3456 3457 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change) 3458 { 3459 chip->amplifier += change; 3460 3461 if (chip->amplifier) { 3462 /* Switch the GPIO pins 7 and 8 to open drain */ 3463 snd_cs46xx_codec_write(chip, 0x4C, 3464 snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F); 3465 snd_cs46xx_codec_write(chip, 0x4E, 3466 snd_cs46xx_codec_read(chip, 0x4E) | 0x0180); 3467 /* Now wake the AMP (this might be backwards) */ 3468 snd_cs46xx_codec_write(chip, 0x54, 3469 snd_cs46xx_codec_read(chip, 0x54) & ~0x0180); 3470 } else { 3471 snd_cs46xx_codec_write(chip, 0x54, 3472 snd_cs46xx_codec_read(chip, 0x54) | 0x0180); 3473 } 3474 } 3475 #endif 3476 3477 3478 /* 3479 * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support 3480 * whenever we need to beat on the chip. 3481 * 3482 * The original idea and code for this hack comes from David Kaiser at 3483 * Linuxcare. Perhaps one day Crystal will document their chips well 3484 * enough to make them useful. 3485 */ 3486 3487 static void clkrun_hack(struct snd_cs46xx *chip, int change) 3488 { 3489 u16 control, nval; 3490 3491 if (!chip->acpi_port) 3492 return; 3493 3494 chip->amplifier += change; 3495 3496 /* Read ACPI port */ 3497 nval = control = inw(chip->acpi_port + 0x10); 3498 3499 /* Flip CLKRUN off while running */ 3500 if (! chip->amplifier) 3501 nval |= 0x2000; 3502 else 3503 nval &= ~0x2000; 3504 if (nval != control) 3505 outw(nval, chip->acpi_port + 0x10); 3506 } 3507 3508 3509 /* 3510 * detect intel piix4 3511 */ 3512 static void clkrun_init(struct snd_cs46xx *chip) 3513 { 3514 struct pci_dev *pdev; 3515 u8 pp; 3516 3517 chip->acpi_port = 0; 3518 3519 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 3520 PCI_DEVICE_ID_INTEL_82371AB_3, NULL); 3521 if (pdev == NULL) 3522 return; /* Not a thinkpad thats for sure */ 3523 3524 /* Find the control port */ 3525 pci_read_config_byte(pdev, 0x41, &pp); 3526 chip->acpi_port = pp << 8; 3527 pci_dev_put(pdev); 3528 } 3529 3530 3531 /* 3532 * Card subid table 3533 */ 3534 3535 struct cs_card_type 3536 { 3537 u16 vendor; 3538 u16 id; 3539 char *name; 3540 void (*init)(struct snd_cs46xx *); 3541 void (*amp)(struct snd_cs46xx *, int); 3542 void (*active)(struct snd_cs46xx *, int); 3543 void (*mixer_init)(struct snd_cs46xx *); 3544 }; 3545 3546 static struct cs_card_type cards[] = { 3547 { 3548 .vendor = 0x1489, 3549 .id = 0x7001, 3550 .name = "Genius Soundmaker 128 value", 3551 /* nothing special */ 3552 }, 3553 { 3554 .vendor = 0x5053, 3555 .id = 0x3357, 3556 .name = "Voyetra", 3557 .amp = amp_voyetra, 3558 .mixer_init = voyetra_mixer_init, 3559 }, 3560 { 3561 .vendor = 0x1071, 3562 .id = 0x6003, 3563 .name = "Mitac MI6020/21", 3564 .amp = amp_voyetra, 3565 }, 3566 /* Hercules Game Theatre XP */ 3567 { 3568 .vendor = 0x14af, /* Guillemot Corporation */ 3569 .id = 0x0050, 3570 .name = "Hercules Game Theatre XP", 3571 .amp = amp_hercules, 3572 .mixer_init = hercules_mixer_init, 3573 }, 3574 { 3575 .vendor = 0x1681, 3576 .id = 0x0050, 3577 .name = "Hercules Game Theatre XP", 3578 .amp = amp_hercules, 3579 .mixer_init = hercules_mixer_init, 3580 }, 3581 { 3582 .vendor = 0x1681, 3583 .id = 0x0051, 3584 .name = "Hercules Game Theatre XP", 3585 .amp = amp_hercules, 3586 .mixer_init = hercules_mixer_init, 3587 3588 }, 3589 { 3590 .vendor = 0x1681, 3591 .id = 0x0052, 3592 .name = "Hercules Game Theatre XP", 3593 .amp = amp_hercules, 3594 .mixer_init = hercules_mixer_init, 3595 }, 3596 { 3597 .vendor = 0x1681, 3598 .id = 0x0053, 3599 .name = "Hercules Game Theatre XP", 3600 .amp = amp_hercules, 3601 .mixer_init = hercules_mixer_init, 3602 }, 3603 { 3604 .vendor = 0x1681, 3605 .id = 0x0054, 3606 .name = "Hercules Game Theatre XP", 3607 .amp = amp_hercules, 3608 .mixer_init = hercules_mixer_init, 3609 }, 3610 /* Herculess Fortissimo */ 3611 { 3612 .vendor = 0x1681, 3613 .id = 0xa010, 3614 .name = "Hercules Gamesurround Fortissimo II", 3615 }, 3616 { 3617 .vendor = 0x1681, 3618 .id = 0xa011, 3619 .name = "Hercules Gamesurround Fortissimo III 7.1", 3620 }, 3621 /* Teratec */ 3622 { 3623 .vendor = 0x153b, 3624 .id = 0x112e, 3625 .name = "Terratec DMX XFire 1024", 3626 }, 3627 { 3628 .vendor = 0x153b, 3629 .id = 0x1136, 3630 .name = "Terratec SiXPack 5.1", 3631 }, 3632 /* Not sure if the 570 needs the clkrun hack */ 3633 { 3634 .vendor = PCI_VENDOR_ID_IBM, 3635 .id = 0x0132, 3636 .name = "Thinkpad 570", 3637 .init = clkrun_init, 3638 .active = clkrun_hack, 3639 }, 3640 { 3641 .vendor = PCI_VENDOR_ID_IBM, 3642 .id = 0x0153, 3643 .name = "Thinkpad 600X/A20/T20", 3644 .init = clkrun_init, 3645 .active = clkrun_hack, 3646 }, 3647 { 3648 .vendor = PCI_VENDOR_ID_IBM, 3649 .id = 0x1010, 3650 .name = "Thinkpad 600E (unsupported)", 3651 }, 3652 {} /* terminator */ 3653 }; 3654 3655 3656 /* 3657 * APM support 3658 */ 3659 #ifdef CONFIG_PM_SLEEP 3660 static const unsigned int saved_regs[] = { 3661 BA0_ACOSV, 3662 /*BA0_ASER_FADDR,*/ 3663 BA0_ASER_MASTER, 3664 BA1_PVOL, 3665 BA1_CVOL, 3666 }; 3667 3668 static int snd_cs46xx_suspend(struct device *dev) 3669 { 3670 struct snd_card *card = dev_get_drvdata(dev); 3671 struct snd_cs46xx *chip = card->private_data; 3672 int i, amp_saved; 3673 3674 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 3675 chip->in_suspend = 1; 3676 // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL); 3677 // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE); 3678 3679 snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); 3680 snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); 3681 3682 /* save some registers */ 3683 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3684 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]); 3685 3686 amp_saved = chip->amplifier; 3687 /* turn off amp */ 3688 chip->amplifier_ctrl(chip, -chip->amplifier); 3689 snd_cs46xx_hw_stop(chip); 3690 /* disable CLKRUN */ 3691 chip->active_ctrl(chip, -chip->amplifier); 3692 chip->amplifier = amp_saved; /* restore the status */ 3693 return 0; 3694 } 3695 3696 static int snd_cs46xx_resume(struct device *dev) 3697 { 3698 struct snd_card *card = dev_get_drvdata(dev); 3699 struct snd_cs46xx *chip = card->private_data; 3700 int amp_saved; 3701 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3702 int i; 3703 #endif 3704 unsigned int tmp; 3705 3706 amp_saved = chip->amplifier; 3707 chip->amplifier = 0; 3708 chip->active_ctrl(chip, 1); /* force to on */ 3709 3710 snd_cs46xx_chip_init(chip); 3711 3712 snd_cs46xx_reset(chip); 3713 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3714 cs46xx_dsp_resume(chip); 3715 /* restore some registers */ 3716 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 3717 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]); 3718 #else 3719 snd_cs46xx_download_image(chip); 3720 #endif 3721 3722 #if 0 3723 snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE, 3724 chip->ac97_general_purpose); 3725 snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL, 3726 chip->ac97_powerdown); 3727 mdelay(10); 3728 snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN, 3729 chip->ac97_powerdown); 3730 mdelay(5); 3731 #endif 3732 3733 snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]); 3734 snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]); 3735 3736 /* 3737 * Stop capture DMA. 3738 */ 3739 tmp = snd_cs46xx_peek(chip, BA1_CCTL); 3740 chip->capt.ctl = tmp & 0x0000ffff; 3741 snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000); 3742 3743 mdelay(5); 3744 3745 /* reset playback/capture */ 3746 snd_cs46xx_set_play_sample_rate(chip, 8000); 3747 snd_cs46xx_set_capture_sample_rate(chip, 8000); 3748 snd_cs46xx_proc_start(chip); 3749 3750 cs46xx_enable_stream_irqs(chip); 3751 3752 if (amp_saved) 3753 chip->amplifier_ctrl(chip, 1); /* turn amp on */ 3754 else 3755 chip->active_ctrl(chip, -1); /* disable CLKRUN */ 3756 chip->amplifier = amp_saved; 3757 chip->in_suspend = 0; 3758 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 3759 return 0; 3760 } 3761 3762 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume); 3763 #endif /* CONFIG_PM_SLEEP */ 3764 3765 3766 /* 3767 */ 3768 3769 int snd_cs46xx_create(struct snd_card *card, 3770 struct pci_dev *pci, 3771 int external_amp, int thinkpad) 3772 { 3773 struct snd_cs46xx *chip = card->private_data; 3774 int err, idx; 3775 struct snd_cs46xx_region *region; 3776 struct cs_card_type *cp; 3777 u16 ss_card, ss_vendor; 3778 3779 /* enable PCI device */ 3780 err = pcim_enable_device(pci); 3781 if (err < 0) 3782 return err; 3783 3784 spin_lock_init(&chip->reg_lock); 3785 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3786 mutex_init(&chip->spos_mutex); 3787 #endif 3788 chip->card = card; 3789 chip->pci = pci; 3790 chip->irq = -1; 3791 3792 err = pcim_request_all_regions(pci, "CS46xx"); 3793 if (err < 0) 3794 return err; 3795 chip->ba0_addr = pci_resource_start(pci, 0); 3796 chip->ba1_addr = pci_resource_start(pci, 1); 3797 if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 || 3798 chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) { 3799 dev_err(chip->card->dev, 3800 "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n", 3801 chip->ba0_addr, chip->ba1_addr); 3802 return -ENOMEM; 3803 } 3804 3805 region = &chip->region.name.ba0; 3806 strscpy(region->name, "CS46xx_BA0"); 3807 region->base = chip->ba0_addr; 3808 region->size = CS46XX_BA0_SIZE; 3809 3810 region = &chip->region.name.data0; 3811 strscpy(region->name, "CS46xx_BA1_data0"); 3812 region->base = chip->ba1_addr + BA1_SP_DMEM0; 3813 region->size = CS46XX_BA1_DATA0_SIZE; 3814 3815 region = &chip->region.name.data1; 3816 strscpy(region->name, "CS46xx_BA1_data1"); 3817 region->base = chip->ba1_addr + BA1_SP_DMEM1; 3818 region->size = CS46XX_BA1_DATA1_SIZE; 3819 3820 region = &chip->region.name.pmem; 3821 strscpy(region->name, "CS46xx_BA1_pmem"); 3822 region->base = chip->ba1_addr + BA1_SP_PMEM; 3823 region->size = CS46XX_BA1_PRG_SIZE; 3824 3825 region = &chip->region.name.reg; 3826 strscpy(region->name, "CS46xx_BA1_reg"); 3827 region->base = chip->ba1_addr + BA1_SP_REG; 3828 region->size = CS46XX_BA1_REG_SIZE; 3829 3830 /* set up amp and clkrun hack */ 3831 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor); 3832 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card); 3833 3834 for (cp = &cards[0]; cp->name; cp++) { 3835 if (cp->vendor == ss_vendor && cp->id == ss_card) { 3836 dev_dbg(chip->card->dev, "hack for %s enabled\n", 3837 cp->name); 3838 3839 chip->amplifier_ctrl = cp->amp; 3840 chip->active_ctrl = cp->active; 3841 chip->mixer_init = cp->mixer_init; 3842 3843 if (cp->init) 3844 cp->init(chip); 3845 break; 3846 } 3847 } 3848 3849 if (external_amp) { 3850 dev_info(chip->card->dev, 3851 "Crystal EAPD support forced on.\n"); 3852 chip->amplifier_ctrl = amp_voyetra; 3853 } 3854 3855 if (thinkpad) { 3856 dev_info(chip->card->dev, 3857 "Activating CLKRUN hack for Thinkpad.\n"); 3858 chip->active_ctrl = clkrun_hack; 3859 clkrun_init(chip); 3860 } 3861 3862 if (chip->amplifier_ctrl == NULL) 3863 chip->amplifier_ctrl = amp_none; 3864 if (chip->active_ctrl == NULL) 3865 chip->active_ctrl = amp_none; 3866 3867 chip->active_ctrl(chip, 1); /* enable CLKRUN */ 3868 3869 pci_set_master(pci); 3870 3871 for (idx = 0; idx < 5; idx++) { 3872 region = &chip->region.idx[idx]; 3873 region->remap_addr = devm_ioremap(&pci->dev, region->base, 3874 region->size); 3875 if (region->remap_addr == NULL) { 3876 dev_err(chip->card->dev, 3877 "%s ioremap problem\n", region->name); 3878 return -ENOMEM; 3879 } 3880 } 3881 3882 if (devm_request_irq(&pci->dev, pci->irq, snd_cs46xx_interrupt, 3883 IRQF_SHARED, KBUILD_MODNAME, chip)) { 3884 dev_err(chip->card->dev, "unable to grab IRQ %d\n", pci->irq); 3885 return -EBUSY; 3886 } 3887 chip->irq = pci->irq; 3888 card->sync_irq = chip->irq; 3889 card->private_free = snd_cs46xx_free; 3890 3891 #ifdef CONFIG_SND_CS46XX_NEW_DSP 3892 chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip); 3893 if (!chip->dsp_spos_instance) 3894 return -ENOMEM; 3895 #endif 3896 3897 err = snd_cs46xx_chip_init(chip); 3898 if (err < 0) 3899 return err; 3900 3901 snd_cs46xx_proc_init(card, chip); 3902 3903 #ifdef CONFIG_PM_SLEEP 3904 chip->saved_regs = devm_kmalloc_array(&pci->dev, 3905 ARRAY_SIZE(saved_regs), 3906 sizeof(*chip->saved_regs), 3907 GFP_KERNEL); 3908 if (!chip->saved_regs) 3909 return -ENOMEM; 3910 #endif 3911 3912 chip->active_ctrl(chip, -1); /* disable CLKRUN */ 3913 return 0; 3914 } 3915