1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v2_0.h" 30 #include "jpeg_v4_0.h" 31 #include "mmsch_v4_0.h" 32 33 #include "vcn/vcn_4_0_0_offset.h" 34 #include "vcn/vcn_4_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 36 37 #define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 38 39 static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0[] = { 40 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), 41 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), 42 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR), 43 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR), 44 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL), 45 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE), 46 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS), 47 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), 48 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), 49 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), 50 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), 51 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), 52 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), 53 }; 54 55 static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev); 56 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev); 57 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev); 58 static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 59 enum amd_powergating_state state); 60 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev); 61 static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 62 63 /** 64 * jpeg_v4_0_early_init - set function pointers 65 * 66 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 67 * 68 * Set ring and irq function pointers 69 */ 70 static int jpeg_v4_0_early_init(struct amdgpu_ip_block *ip_block) 71 { 72 struct amdgpu_device *adev = ip_block->adev; 73 74 75 adev->jpeg.num_jpeg_inst = 1; 76 adev->jpeg.num_jpeg_rings = 1; 77 78 jpeg_v4_0_set_dec_ring_funcs(adev); 79 jpeg_v4_0_set_irq_funcs(adev); 80 jpeg_v4_0_set_ras_funcs(adev); 81 82 return 0; 83 } 84 85 /** 86 * jpeg_v4_0_sw_init - sw init for JPEG block 87 * 88 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 89 * 90 * Load firmware and sw initialization 91 */ 92 static int jpeg_v4_0_sw_init(struct amdgpu_ip_block *ip_block) 93 { 94 struct amdgpu_device *adev = ip_block->adev; 95 struct amdgpu_ring *ring; 96 int r; 97 98 /* JPEG TRAP */ 99 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 100 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 101 if (r) 102 return r; 103 104 /* JPEG DJPEG POISON EVENT */ 105 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 106 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 107 if (r) 108 return r; 109 110 /* JPEG EJPEG POISON EVENT */ 111 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 112 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 113 if (r) 114 return r; 115 116 r = amdgpu_jpeg_sw_init(adev); 117 if (r) 118 return r; 119 120 r = amdgpu_jpeg_resume(adev); 121 if (r) 122 return r; 123 124 ring = adev->jpeg.inst->ring_dec; 125 ring->use_doorbell = true; 126 ring->doorbell_index = amdgpu_sriov_vf(adev) ? (((adev->doorbell_index.vcn.vcn_ring0_1) << 1) + 4) : ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1); 127 ring->vm_hub = AMDGPU_MMHUB0(0); 128 129 sprintf(ring->name, "jpeg_dec"); 130 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 131 AMDGPU_RING_PRIO_DEFAULT, NULL); 132 if (r) 133 return r; 134 135 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; 136 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); 137 138 r = amdgpu_jpeg_ras_sw_init(adev); 139 if (r) 140 return r; 141 142 r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0, ARRAY_SIZE(jpeg_reg_list_4_0)); 143 if (r) 144 return r; 145 146 adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE; 147 r = amdgpu_jpeg_sysfs_reset_mask_init(adev); 148 149 return r; 150 } 151 152 /** 153 * jpeg_v4_0_sw_fini - sw fini for JPEG block 154 * 155 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 156 * 157 * JPEG suspend and free up sw allocation 158 */ 159 static int jpeg_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) 160 { 161 struct amdgpu_device *adev = ip_block->adev; 162 int r; 163 164 r = amdgpu_jpeg_suspend(adev); 165 if (r) 166 return r; 167 168 amdgpu_jpeg_sysfs_reset_mask_fini(adev); 169 r = amdgpu_jpeg_sw_fini(adev); 170 171 return r; 172 } 173 174 /** 175 * jpeg_v4_0_hw_init - start and test JPEG block 176 * 177 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 178 * 179 */ 180 static int jpeg_v4_0_hw_init(struct amdgpu_ip_block *ip_block) 181 { 182 struct amdgpu_device *adev = ip_block->adev; 183 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 184 int r; 185 186 if (amdgpu_sriov_vf(adev)) { 187 r = jpeg_v4_0_start_sriov(adev); 188 if (r) 189 return r; 190 ring->wptr = 0; 191 ring->wptr_old = 0; 192 jpeg_v4_0_dec_ring_set_wptr(ring); 193 ring->sched.ready = true; 194 } else { 195 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 196 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 197 198 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, 199 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 200 VCN_JPEG_DB_CTRL__EN_MASK); 201 202 r = amdgpu_ring_test_helper(ring); 203 if (r) 204 return r; 205 } 206 207 return 0; 208 } 209 210 /** 211 * jpeg_v4_0_hw_fini - stop the hardware block 212 * 213 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 214 * 215 * Stop the JPEG block, mark ring as not ready any more 216 */ 217 static int jpeg_v4_0_hw_fini(struct amdgpu_ip_block *ip_block) 218 { 219 struct amdgpu_device *adev = ip_block->adev; 220 221 cancel_delayed_work_sync(&adev->jpeg.idle_work); 222 if (!amdgpu_sriov_vf(adev)) { 223 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 224 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) 225 jpeg_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 226 } 227 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) 228 amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0); 229 230 return 0; 231 } 232 233 /** 234 * jpeg_v4_0_suspend - suspend JPEG block 235 * 236 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 237 * 238 * HW fini and suspend JPEG block 239 */ 240 static int jpeg_v4_0_suspend(struct amdgpu_ip_block *ip_block) 241 { 242 int r; 243 244 r = jpeg_v4_0_hw_fini(ip_block); 245 if (r) 246 return r; 247 248 r = amdgpu_jpeg_suspend(ip_block->adev); 249 250 return r; 251 } 252 253 /** 254 * jpeg_v4_0_resume - resume JPEG block 255 * 256 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 257 * 258 * Resume firmware and hw init JPEG block 259 */ 260 static int jpeg_v4_0_resume(struct amdgpu_ip_block *ip_block) 261 { 262 int r; 263 264 r = amdgpu_jpeg_resume(ip_block->adev); 265 if (r) 266 return r; 267 268 r = jpeg_v4_0_hw_init(ip_block); 269 270 return r; 271 } 272 273 static void jpeg_v4_0_disable_clock_gating(struct amdgpu_device *adev) 274 { 275 uint32_t data = 0; 276 277 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 278 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 279 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 280 data &= (~JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK); 281 } else { 282 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 283 } 284 285 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 286 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 287 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 288 289 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 290 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 291 | JPEG_CGC_GATE__JPEG2_DEC_MASK 292 | JPEG_CGC_GATE__JMCIF_MASK 293 | JPEG_CGC_GATE__JRBBM_MASK); 294 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 295 } 296 297 static void jpeg_v4_0_enable_clock_gating(struct amdgpu_device *adev) 298 { 299 uint32_t data = 0; 300 301 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 302 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 303 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 304 data |= JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK; 305 } else { 306 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 307 } 308 309 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 310 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 311 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 312 313 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 314 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 315 |JPEG_CGC_GATE__JPEG2_DEC_MASK 316 |JPEG_CGC_GATE__JMCIF_MASK 317 |JPEG_CGC_GATE__JRBBM_MASK); 318 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 319 } 320 321 static int jpeg_v4_0_disable_static_power_gating(struct amdgpu_device *adev) 322 { 323 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 324 uint32_t data = 0; 325 int r = 0; 326 327 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 328 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 329 330 r = SOC15_WAIT_ON_RREG(JPEG, 0, 331 regUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 332 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 333 334 if (r) { 335 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG disable power gating failed\n"); 336 return r; 337 } 338 } 339 340 /* disable anti hang mechanism */ 341 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 342 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 343 344 /* keep the JPEG in static PG mode */ 345 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 346 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 347 348 return 0; 349 } 350 351 static int jpeg_v4_0_enable_static_power_gating(struct amdgpu_device *adev) 352 { 353 /* enable anti hang mechanism */ 354 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 355 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 356 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 357 358 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 359 uint32_t data = 0; 360 int r = 0; 361 362 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 363 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 364 365 r = SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS, 366 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 367 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 368 369 if (r) { 370 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG enable power gating failed\n"); 371 return r; 372 } 373 } 374 375 return 0; 376 } 377 378 /** 379 * jpeg_v4_0_start - start JPEG block 380 * 381 * @adev: amdgpu_device pointer 382 * 383 * Setup and start the JPEG block 384 */ 385 static int jpeg_v4_0_start(struct amdgpu_device *adev) 386 { 387 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 388 int r; 389 390 if (adev->pm.dpm_enabled) 391 amdgpu_dpm_enable_jpeg(adev, true); 392 393 /* disable power gating */ 394 r = jpeg_v4_0_disable_static_power_gating(adev); 395 if (r) 396 return r; 397 398 /* JPEG disable CGC */ 399 jpeg_v4_0_disable_clock_gating(adev); 400 401 /* MJPEG global tiling registers */ 402 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, 403 adev->gfx.config.gb_addr_config); 404 405 406 /* enable JMI channel */ 407 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, 408 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 409 410 /* enable System Interrupt for JRBC */ 411 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), 412 JPEG_SYS_INT_EN__DJRBC_MASK, 413 ~JPEG_SYS_INT_EN__DJRBC_MASK); 414 415 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0); 416 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 417 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 418 lower_32_bits(ring->gpu_addr)); 419 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 420 upper_32_bits(ring->gpu_addr)); 421 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0); 422 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0); 423 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L); 424 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); 425 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 426 427 return 0; 428 } 429 430 static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev) 431 { 432 struct amdgpu_ring *ring; 433 uint64_t ctx_addr; 434 uint32_t param, resp, expected; 435 uint32_t tmp, timeout; 436 437 struct amdgpu_mm_table *table = &adev->virt.mm_table; 438 uint32_t *table_loc; 439 uint32_t table_size; 440 uint32_t size, size_dw; 441 uint32_t init_status; 442 443 struct mmsch_v4_0_cmd_direct_write 444 direct_wt = { {0} }; 445 struct mmsch_v4_0_cmd_end end = { {0} }; 446 struct mmsch_v4_0_init_header header; 447 448 direct_wt.cmd_header.command_type = 449 MMSCH_COMMAND__DIRECT_REG_WRITE; 450 end.cmd_header.command_type = 451 MMSCH_COMMAND__END; 452 453 size = sizeof(struct mmsch_v4_0_init_header); 454 table_loc = (uint32_t *)table->cpu_addr; 455 memcpy(&header, (void *)table_loc, size); 456 457 header.version = MMSCH_VERSION; 458 header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE); 459 460 header.jpegdec.init_status = 0; 461 header.jpegdec.table_offset = 0; 462 header.jpegdec.table_size = 0; 463 464 table_loc = (uint32_t *)table->cpu_addr; 465 table_loc += header.total_size; 466 467 table_size = 0; 468 469 ring = adev->jpeg.inst->ring_dec; 470 471 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, 472 regUVD_LMI_JRBC_RB_64BIT_BAR_LOW), 473 lower_32_bits(ring->gpu_addr)); 474 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, 475 regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH), 476 upper_32_bits(ring->gpu_addr)); 477 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, 478 regUVD_JRBC_RB_SIZE), ring->ring_size / 4); 479 480 /* add end packet */ 481 MMSCH_V4_0_INSERT_END(); 482 483 /* refine header */ 484 header.jpegdec.init_status = 0; 485 header.jpegdec.table_offset = header.total_size; 486 header.jpegdec.table_size = table_size; 487 header.total_size += table_size; 488 489 /* Update init table header in memory */ 490 size = sizeof(struct mmsch_v4_0_init_header); 491 table_loc = (uint32_t *)table->cpu_addr; 492 memcpy((void *)table_loc, &header, size); 493 494 /* Perform HDP flush before writing to MMSCH registers */ 495 amdgpu_device_flush_hdp(adev, NULL); 496 497 /* message MMSCH (in VCN[0]) to initialize this client 498 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 499 * of memory descriptor location 500 */ 501 ctx_addr = table->gpu_addr; 502 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 503 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 504 505 /* 2, update vmid of descriptor */ 506 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); 507 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 508 /* use domain0 for MM scheduler */ 509 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 510 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); 511 512 /* 3, notify mmsch about the size of this descriptor */ 513 size = header.total_size; 514 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); 515 516 /* 4, set resp to zero */ 517 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); 518 519 /* 5, kick off the initialization and wait until 520 * MMSCH_VF_MAILBOX_RESP becomes non-zero 521 */ 522 param = 0x00000001; 523 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); 524 tmp = 0; 525 timeout = 1000; 526 resp = 0; 527 expected = MMSCH_VF_MAILBOX_RESP__OK; 528 init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->jpegdec.init_status; 529 while (resp != expected) { 530 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); 531 532 if (resp != 0) 533 break; 534 udelay(10); 535 tmp = tmp + 10; 536 if (tmp >= timeout) { 537 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 538 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 539 "(expected=0x%08x, readback=0x%08x)\n", 540 tmp, expected, resp); 541 return -EBUSY; 542 } 543 } 544 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 545 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 546 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", resp, init_status); 547 return -EINVAL; 548 } 549 550 return 0; 551 552 } 553 554 /** 555 * jpeg_v4_0_stop - stop JPEG block 556 * 557 * @adev: amdgpu_device pointer 558 * 559 * stop the JPEG block 560 */ 561 static int jpeg_v4_0_stop(struct amdgpu_device *adev) 562 { 563 int r; 564 565 /* reset JMI */ 566 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 567 UVD_JMI_CNTL__SOFT_RESET_MASK, 568 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 569 570 jpeg_v4_0_enable_clock_gating(adev); 571 572 /* enable power gating */ 573 r = jpeg_v4_0_enable_static_power_gating(adev); 574 if (r) 575 return r; 576 577 if (adev->pm.dpm_enabled) 578 amdgpu_dpm_enable_jpeg(adev, false); 579 580 return 0; 581 } 582 583 /** 584 * jpeg_v4_0_dec_ring_get_rptr - get read pointer 585 * 586 * @ring: amdgpu_ring pointer 587 * 588 * Returns the current hardware read pointer 589 */ 590 static uint64_t jpeg_v4_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 591 { 592 struct amdgpu_device *adev = ring->adev; 593 594 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR); 595 } 596 597 /** 598 * jpeg_v4_0_dec_ring_get_wptr - get write pointer 599 * 600 * @ring: amdgpu_ring pointer 601 * 602 * Returns the current hardware write pointer 603 */ 604 static uint64_t jpeg_v4_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 605 { 606 struct amdgpu_device *adev = ring->adev; 607 608 if (ring->use_doorbell) 609 return *ring->wptr_cpu_addr; 610 else 611 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 612 } 613 614 /** 615 * jpeg_v4_0_dec_ring_set_wptr - set write pointer 616 * 617 * @ring: amdgpu_ring pointer 618 * 619 * Commits the write pointer to the hardware 620 */ 621 static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 622 { 623 struct amdgpu_device *adev = ring->adev; 624 625 if (ring->use_doorbell) { 626 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 627 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 628 } else { 629 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 630 } 631 } 632 633 static bool jpeg_v4_0_is_idle(struct amdgpu_ip_block *ip_block) 634 { 635 struct amdgpu_device *adev = ip_block->adev; 636 int ret = 1; 637 638 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) & 639 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 640 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 641 642 return ret; 643 } 644 645 static int jpeg_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 646 { 647 struct amdgpu_device *adev = ip_block->adev; 648 649 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, 650 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 651 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 652 } 653 654 static int jpeg_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 655 enum amd_clockgating_state state) 656 { 657 struct amdgpu_device *adev = ip_block->adev; 658 bool enable = state == AMD_CG_STATE_GATE; 659 660 if (enable) { 661 if (!jpeg_v4_0_is_idle(ip_block)) 662 return -EBUSY; 663 jpeg_v4_0_enable_clock_gating(adev); 664 } else { 665 jpeg_v4_0_disable_clock_gating(adev); 666 } 667 668 return 0; 669 } 670 671 static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 672 enum amd_powergating_state state) 673 { 674 struct amdgpu_device *adev = ip_block->adev; 675 int ret; 676 677 if (amdgpu_sriov_vf(adev)) { 678 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 679 return 0; 680 } 681 682 if (state == adev->jpeg.cur_state) 683 return 0; 684 685 if (state == AMD_PG_STATE_GATE) 686 ret = jpeg_v4_0_stop(adev); 687 else 688 ret = jpeg_v4_0_start(adev); 689 690 if (!ret) 691 adev->jpeg.cur_state = state; 692 693 return ret; 694 } 695 696 static int jpeg_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev, 697 struct amdgpu_irq_src *source, 698 unsigned int type, 699 enum amdgpu_interrupt_state state) 700 { 701 return 0; 702 } 703 704 static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev, 705 struct amdgpu_irq_src *source, 706 struct amdgpu_iv_entry *entry) 707 { 708 DRM_DEBUG("IH: JPEG TRAP\n"); 709 710 switch (entry->src_id) { 711 case VCN_4_0__SRCID__JPEG_DECODE: 712 amdgpu_fence_process(adev->jpeg.inst->ring_dec); 713 break; 714 default: 715 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 716 entry->src_id, entry->src_data[0]); 717 break; 718 } 719 720 return 0; 721 } 722 723 static int jpeg_v4_0_ring_reset(struct amdgpu_ring *ring, unsigned int vmid) 724 { 725 if (amdgpu_sriov_vf(ring->adev)) 726 return -EINVAL; 727 728 jpeg_v4_0_stop(ring->adev); 729 jpeg_v4_0_start(ring->adev); 730 return amdgpu_ring_test_helper(ring); 731 } 732 733 static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = { 734 .name = "jpeg_v4_0", 735 .early_init = jpeg_v4_0_early_init, 736 .sw_init = jpeg_v4_0_sw_init, 737 .sw_fini = jpeg_v4_0_sw_fini, 738 .hw_init = jpeg_v4_0_hw_init, 739 .hw_fini = jpeg_v4_0_hw_fini, 740 .suspend = jpeg_v4_0_suspend, 741 .resume = jpeg_v4_0_resume, 742 .is_idle = jpeg_v4_0_is_idle, 743 .wait_for_idle = jpeg_v4_0_wait_for_idle, 744 .set_clockgating_state = jpeg_v4_0_set_clockgating_state, 745 .set_powergating_state = jpeg_v4_0_set_powergating_state, 746 .dump_ip_state = amdgpu_jpeg_dump_ip_state, 747 .print_ip_state = amdgpu_jpeg_print_ip_state, 748 }; 749 750 static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = { 751 .type = AMDGPU_RING_TYPE_VCN_JPEG, 752 .align_mask = 0xf, 753 .get_rptr = jpeg_v4_0_dec_ring_get_rptr, 754 .get_wptr = jpeg_v4_0_dec_ring_get_wptr, 755 .set_wptr = jpeg_v4_0_dec_ring_set_wptr, 756 .parse_cs = jpeg_v2_dec_ring_parse_cs, 757 .emit_frame_size = 758 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 759 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 760 8 + /* jpeg_v4_0_dec_ring_emit_vm_flush */ 761 18 + 18 + /* jpeg_v4_0_dec_ring_emit_fence x2 vm fence */ 762 8 + 16, 763 .emit_ib_size = 22, /* jpeg_v4_0_dec_ring_emit_ib */ 764 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 765 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 766 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 767 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 768 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 769 .insert_nop = jpeg_v2_0_dec_ring_nop, 770 .insert_start = jpeg_v2_0_dec_ring_insert_start, 771 .insert_end = jpeg_v2_0_dec_ring_insert_end, 772 .pad_ib = amdgpu_ring_generic_pad_ib, 773 .begin_use = amdgpu_jpeg_ring_begin_use, 774 .end_use = amdgpu_jpeg_ring_end_use, 775 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 776 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 777 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 778 .reset = jpeg_v4_0_ring_reset, 779 }; 780 781 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev) 782 { 783 adev->jpeg.inst->ring_dec->funcs = &jpeg_v4_0_dec_ring_vm_funcs; 784 } 785 786 static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = { 787 .process = jpeg_v4_0_process_interrupt, 788 }; 789 790 static const struct amdgpu_irq_src_funcs jpeg_v4_0_ras_irq_funcs = { 791 .set = jpeg_v4_0_set_ras_interrupt_state, 792 .process = amdgpu_jpeg_process_poison_irq, 793 }; 794 795 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev) 796 { 797 adev->jpeg.inst->irq.num_types = 1; 798 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs; 799 800 adev->jpeg.inst->ras_poison_irq.num_types = 1; 801 adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_ras_irq_funcs; 802 } 803 804 const struct amdgpu_ip_block_version jpeg_v4_0_ip_block = { 805 .type = AMD_IP_BLOCK_TYPE_JPEG, 806 .major = 4, 807 .minor = 0, 808 .rev = 0, 809 .funcs = &jpeg_v4_0_ip_funcs, 810 }; 811 812 static uint32_t jpeg_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 813 uint32_t instance, uint32_t sub_block) 814 { 815 uint32_t poison_stat = 0, reg_value = 0; 816 817 switch (sub_block) { 818 case AMDGPU_JPEG_V4_0_JPEG0: 819 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS); 820 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 821 break; 822 case AMDGPU_JPEG_V4_0_JPEG1: 823 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS); 824 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 825 break; 826 default: 827 break; 828 } 829 830 if (poison_stat) 831 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 832 instance, sub_block); 833 834 return poison_stat; 835 } 836 837 static bool jpeg_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 838 { 839 uint32_t inst = 0, sub = 0, poison_stat = 0; 840 841 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 842 for (sub = 0; sub < AMDGPU_JPEG_V4_0_MAX_SUB_BLOCK; sub++) 843 poison_stat += 844 jpeg_v4_0_query_poison_by_instance(adev, inst, sub); 845 846 return !!poison_stat; 847 } 848 849 const struct amdgpu_ras_block_hw_ops jpeg_v4_0_ras_hw_ops = { 850 .query_poison_status = jpeg_v4_0_query_ras_poison_status, 851 }; 852 853 static struct amdgpu_jpeg_ras jpeg_v4_0_ras = { 854 .ras_block = { 855 .hw_ops = &jpeg_v4_0_ras_hw_ops, 856 .ras_late_init = amdgpu_jpeg_ras_late_init, 857 }, 858 }; 859 860 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev) 861 { 862 switch (amdgpu_ip_version(adev, JPEG_HWIP, 0)) { 863 case IP_VERSION(4, 0, 0): 864 adev->jpeg.ras = &jpeg_v4_0_ras; 865 break; 866 default: 867 break; 868 } 869 } 870