1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2024 Intel Corporation. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/vmalloc.h> 9 #include <linux/string.h> 10 #include <linux/in.h> 11 #include <linux/interrupt.h> 12 #include <linux/iopoll.h> 13 #include <linux/ip.h> 14 #include <linux/tcp.h> 15 #include <linux/sctp.h> 16 #include <linux/pkt_sched.h> 17 #include <linux/ipv6.h> 18 #include <linux/slab.h> 19 #include <net/checksum.h> 20 #include <net/ip6_checksum.h> 21 #include <linux/etherdevice.h> 22 #include <linux/ethtool.h> 23 #include <linux/if.h> 24 #include <linux/if_vlan.h> 25 #include <linux/if_macvlan.h> 26 #include <linux/if_bridge.h> 27 #include <linux/prefetch.h> 28 #include <linux/bpf.h> 29 #include <linux/bpf_trace.h> 30 #include <linux/atomic.h> 31 #include <linux/numa.h> 32 #include <generated/utsrelease.h> 33 #include <scsi/fc/fc_fcoe.h> 34 #include <net/udp_tunnel.h> 35 #include <net/pkt_cls.h> 36 #include <net/tc_act/tc_gact.h> 37 #include <net/tc_act/tc_mirred.h> 38 #include <net/vxlan.h> 39 #include <net/mpls.h> 40 #include <net/netdev_queues.h> 41 #include <net/xdp_sock_drv.h> 42 #include <net/xfrm.h> 43 44 #include "ixgbe.h" 45 #include "ixgbe_common.h" 46 #include "ixgbe_e610.h" 47 #include "ixgbe_dcb_82599.h" 48 #include "ixgbe_mbx.h" 49 #include "ixgbe_phy.h" 50 #include "ixgbe_sriov.h" 51 #include "ixgbe_model.h" 52 #include "ixgbe_txrx_common.h" 53 #include "devlink/devlink.h" 54 55 char ixgbe_driver_name[] = "ixgbe"; 56 static const char ixgbe_driver_string[] = 57 "Intel(R) 10 Gigabit PCI Express Network Driver"; 58 #ifdef IXGBE_FCOE 59 char ixgbe_default_device_descr[] = 60 "Intel(R) 10 Gigabit Network Connection"; 61 #else 62 static char ixgbe_default_device_descr[] = 63 "Intel(R) 10 Gigabit Network Connection"; 64 #endif 65 static const char ixgbe_copyright[] = 66 "Copyright (c) 1999-2016 Intel Corporation."; 67 68 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; 69 70 static const struct ixgbe_info *ixgbe_info_tbl[] = { 71 [board_82598] = &ixgbe_82598_info, 72 [board_82599] = &ixgbe_82599_info, 73 [board_X540] = &ixgbe_X540_info, 74 [board_X550] = &ixgbe_X550_info, 75 [board_X550EM_x] = &ixgbe_X550EM_x_info, 76 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info, 77 [board_x550em_a] = &ixgbe_x550em_a_info, 78 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info, 79 [board_e610] = &ixgbe_e610_info, 80 }; 81 82 /* ixgbe_pci_tbl - PCI Device ID Table 83 * 84 * Wildcard entries (PCI_ANY_ID) should come last 85 * Last entry must be all 0s 86 * 87 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 88 * Class, Class Mask, private data (not used) } 89 */ 90 static const struct pci_device_id ixgbe_pci_tbl[] = { 91 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), .driver_data = board_82598 }, 92 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), .driver_data = board_82598 }, 93 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), .driver_data = board_82598 }, 94 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), .driver_data = board_82598 }, 95 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), .driver_data = board_82598 }, 96 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), .driver_data = board_82598 }, 97 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), .driver_data = board_82598 }, 98 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), .driver_data = board_82598 }, 99 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), .driver_data = board_82598 }, 100 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), .driver_data = board_82598 }, 101 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), .driver_data = board_82598 }, 102 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), .driver_data = board_82598 }, 103 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), .driver_data = board_82599 }, 104 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), .driver_data = board_82599 }, 105 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), .driver_data = board_82599 }, 106 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), .driver_data = board_82599 }, 107 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), .driver_data = board_82599 }, 108 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), .driver_data = board_82599 }, 109 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), .driver_data = board_82599 }, 110 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), .driver_data = board_82599 }, 111 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), .driver_data = board_82599 }, 112 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), .driver_data = board_82599 }, 113 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), .driver_data = board_82599 }, 114 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), .driver_data = board_X540 }, 115 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), .driver_data = board_82599 }, 116 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), .driver_data = board_82599 }, 117 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), .driver_data = board_82599 }, 118 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), .driver_data = board_82599 }, 119 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), .driver_data = board_82599 }, 120 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), .driver_data = board_X540 }, 121 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), .driver_data = board_X550 }, 122 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), .driver_data = board_X550 }, 123 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), .driver_data = board_X550EM_x }, 124 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), .driver_data = board_X550EM_x }, 125 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), .driver_data = board_X550EM_x }, 126 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), .driver_data = board_X550EM_x }, 127 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), .driver_data = board_X550EM_x }, 128 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), .driver_data = board_x550em_x_fw }, 129 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), .driver_data = board_x550em_a }, 130 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), .driver_data = board_x550em_a }, 131 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), .driver_data = board_x550em_a }, 132 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), .driver_data = board_x550em_a }, 133 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), .driver_data = board_x550em_a }, 134 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), .driver_data = board_x550em_a }, 135 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), .driver_data = board_x550em_a }, 136 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), .driver_data = board_x550em_a_fw }, 137 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), .driver_data = board_x550em_a_fw }, 138 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_BACKPLANE), .driver_data = board_e610 }, 139 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_SFP), .driver_data = board_e610 }, 140 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_10G_T), .driver_data = board_e610 }, 141 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_2_5G_T), .driver_data = board_e610 }, 142 { PCI_VDEVICE(INTEL, IXGBE_DEV_ID_E610_SGMII), .driver_data = board_e610 }, 143 /* required last entry */ 144 { } 145 }; 146 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); 147 148 #ifdef CONFIG_IXGBE_DCA 149 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, 150 void *p); 151 static struct notifier_block dca_notifier = { 152 .notifier_call = ixgbe_notify_dca, 153 .next = NULL, 154 .priority = 0 155 }; 156 #endif 157 158 #ifdef CONFIG_PCI_IOV 159 static unsigned int max_vfs; 160 module_param(max_vfs, uint, 0); 161 MODULE_PARM_DESC(max_vfs, 162 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); 163 #endif /* CONFIG_PCI_IOV */ 164 165 static bool allow_unsupported_sfp; 166 module_param(allow_unsupported_sfp, bool, 0444); 167 MODULE_PARM_DESC(allow_unsupported_sfp, 168 "Allow unsupported and untested SFP+ modules on 82599-based adapters"); 169 170 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 171 static int debug = -1; 172 module_param(debug, int, 0); 173 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 174 175 MODULE_IMPORT_NS("LIBIE_FWLOG"); 176 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); 177 MODULE_LICENSE("GPL v2"); 178 179 DEFINE_STATIC_KEY_FALSE(ixgbe_xdp_locking_key); 180 EXPORT_SYMBOL(ixgbe_xdp_locking_key); 181 182 static struct workqueue_struct *ixgbe_wq; 183 184 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); 185 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *); 186 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *); 187 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *); 188 189 static const struct net_device_ops ixgbe_netdev_ops; 190 191 static bool netif_is_ixgbe(struct net_device *dev) 192 { 193 return dev && (dev->netdev_ops == &ixgbe_netdev_ops); 194 } 195 196 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, 197 u32 reg, u16 *value) 198 { 199 struct pci_dev *parent_dev; 200 struct pci_bus *parent_bus; 201 202 parent_bus = adapter->pdev->bus->parent; 203 if (!parent_bus) 204 return -1; 205 206 parent_dev = parent_bus->self; 207 if (!parent_dev) 208 return -1; 209 210 if (!pci_is_pcie(parent_dev)) 211 return -1; 212 213 pcie_capability_read_word(parent_dev, reg, value); 214 if (*value == IXGBE_FAILED_READ_CFG_WORD && 215 ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) 216 return -1; 217 return 0; 218 } 219 220 static int ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) 221 { 222 struct ixgbe_hw *hw = &adapter->hw; 223 u16 link_status = 0; 224 int err; 225 226 hw->bus.type = ixgbe_bus_type_pci_express; 227 228 /* Get the negotiated link width and speed from PCI config space of the 229 * parent, as this device is behind a switch 230 */ 231 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); 232 233 /* assume caller will handle error case */ 234 if (err) 235 return err; 236 237 hw->bus.width = ixgbe_convert_bus_width(link_status); 238 hw->bus.speed = ixgbe_convert_bus_speed(link_status); 239 240 return 0; 241 } 242 243 /** 244 * ixgbe_pcie_from_parent - Determine whether PCIe info should come from parent 245 * @hw: hw specific details 246 * 247 * This function is used by probe to determine whether a device's PCI-Express 248 * bandwidth details should be gathered from the parent bus instead of from the 249 * device. Used to ensure that various locations all have the correct device ID 250 * checks. 251 * 252 * Return: true if information should be collected from the parent bus, false 253 * otherwise 254 */ 255 static bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) 256 { 257 switch (hw->device_id) { 258 case IXGBE_DEV_ID_82599_SFP_SF_QP: 259 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 260 return true; 261 default: 262 return false; 263 } 264 } 265 266 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, 267 int expected_gts) 268 { 269 struct ixgbe_hw *hw = &adapter->hw; 270 struct pci_dev *pdev; 271 272 /* Some devices are not connected over PCIe and thus do not negotiate 273 * speed. These devices do not have valid bus info, and thus any report 274 * we generate may not be correct. 275 */ 276 if (hw->bus.type == ixgbe_bus_type_internal) 277 return; 278 279 /* determine whether to use the parent device */ 280 if (ixgbe_pcie_from_parent(&adapter->hw)) 281 pdev = adapter->pdev->bus->parent->self; 282 else 283 pdev = adapter->pdev; 284 285 pcie_print_link_status(pdev); 286 } 287 288 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) 289 { 290 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 291 !test_bit(__IXGBE_REMOVING, &adapter->state) && 292 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) 293 queue_work(ixgbe_wq, &adapter->service_task); 294 } 295 296 static void ixgbe_remove_adapter(struct ixgbe_hw *hw) 297 { 298 struct ixgbe_adapter *adapter = hw->back; 299 300 if (!hw->hw_addr) 301 return; 302 hw->hw_addr = NULL; 303 e_dev_err("Adapter removed\n"); 304 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 305 ixgbe_service_event_schedule(adapter); 306 } 307 308 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) 309 { 310 u8 __iomem *reg_addr; 311 u32 value; 312 int i; 313 314 reg_addr = READ_ONCE(hw->hw_addr); 315 if (ixgbe_removed(reg_addr)) 316 return IXGBE_FAILED_READ_REG; 317 318 /* Register read of 0xFFFFFFF can indicate the adapter has been removed, 319 * so perform several status register reads to determine if the adapter 320 * has been removed. 321 */ 322 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) { 323 value = readl(reg_addr + IXGBE_STATUS); 324 if (value != IXGBE_FAILED_READ_REG) 325 break; 326 mdelay(3); 327 } 328 329 if (value == IXGBE_FAILED_READ_REG) 330 ixgbe_remove_adapter(hw); 331 else 332 value = readl(reg_addr + reg); 333 return value; 334 } 335 336 /** 337 * ixgbe_read_reg - Read from device register 338 * @hw: hw specific details 339 * @reg: offset of register to read 340 * 341 * Returns : value read or IXGBE_FAILED_READ_REG if removed 342 * 343 * This function is used to read device registers. It checks for device 344 * removal by confirming any read that returns all ones by checking the 345 * status register value for all ones. This function avoids reading from 346 * the hardware if a removal was previously detected in which case it 347 * returns IXGBE_FAILED_READ_REG (all ones). 348 */ 349 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) 350 { 351 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr); 352 u32 value; 353 354 if (ixgbe_removed(reg_addr)) 355 return IXGBE_FAILED_READ_REG; 356 if (unlikely(hw->phy.nw_mng_if_sel & 357 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) { 358 struct ixgbe_adapter *adapter; 359 int i; 360 361 for (i = 0; i < 200; ++i) { 362 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); 363 if (likely(!value)) 364 goto writes_completed; 365 if (value == IXGBE_FAILED_READ_REG) { 366 ixgbe_remove_adapter(hw); 367 return IXGBE_FAILED_READ_REG; 368 } 369 udelay(5); 370 } 371 372 adapter = hw->back; 373 e_warn(hw, "register writes incomplete %08x\n", value); 374 } 375 376 writes_completed: 377 value = readl(reg_addr + reg); 378 if (unlikely(value == IXGBE_FAILED_READ_REG)) 379 value = ixgbe_check_remove(hw, reg); 380 return value; 381 } 382 383 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) 384 { 385 u16 value; 386 387 pci_read_config_word(pdev, PCI_VENDOR_ID, &value); 388 if (value == IXGBE_FAILED_READ_CFG_WORD) { 389 ixgbe_remove_adapter(hw); 390 return true; 391 } 392 return false; 393 } 394 395 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) 396 { 397 struct ixgbe_adapter *adapter = hw->back; 398 u16 value; 399 400 if (ixgbe_removed(hw->hw_addr)) 401 return IXGBE_FAILED_READ_CFG_WORD; 402 pci_read_config_word(adapter->pdev, reg, &value); 403 if (value == IXGBE_FAILED_READ_CFG_WORD && 404 ixgbe_check_cfg_remove(hw, adapter->pdev)) 405 return IXGBE_FAILED_READ_CFG_WORD; 406 return value; 407 } 408 409 #ifdef CONFIG_PCI_IOV 410 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) 411 { 412 struct ixgbe_adapter *adapter = hw->back; 413 u32 value; 414 415 if (ixgbe_removed(hw->hw_addr)) 416 return IXGBE_FAILED_READ_CFG_DWORD; 417 pci_read_config_dword(adapter->pdev, reg, &value); 418 if (value == IXGBE_FAILED_READ_CFG_DWORD && 419 ixgbe_check_cfg_remove(hw, adapter->pdev)) 420 return IXGBE_FAILED_READ_CFG_DWORD; 421 return value; 422 } 423 #endif /* CONFIG_PCI_IOV */ 424 425 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) 426 { 427 struct ixgbe_adapter *adapter = hw->back; 428 429 if (ixgbe_removed(hw->hw_addr)) 430 return; 431 pci_write_config_word(adapter->pdev, reg, value); 432 } 433 434 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) 435 { 436 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); 437 438 /* flush memory to make sure state is correct before next watchdog */ 439 smp_mb__before_atomic(); 440 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 441 } 442 443 struct ixgbe_reg_info { 444 u32 ofs; 445 char *name; 446 }; 447 448 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { 449 450 /* General Registers */ 451 {IXGBE_CTRL, "CTRL"}, 452 {IXGBE_STATUS, "STATUS"}, 453 {IXGBE_CTRL_EXT, "CTRL_EXT"}, 454 455 /* Interrupt Registers */ 456 {IXGBE_EICR, "EICR"}, 457 458 /* RX Registers */ 459 {IXGBE_SRRCTL(0), "SRRCTL"}, 460 {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, 461 {IXGBE_RDLEN(0), "RDLEN"}, 462 {IXGBE_RDH(0), "RDH"}, 463 {IXGBE_RDT(0), "RDT"}, 464 {IXGBE_RXDCTL(0), "RXDCTL"}, 465 {IXGBE_RDBAL(0), "RDBAL"}, 466 {IXGBE_RDBAH(0), "RDBAH"}, 467 468 /* TX Registers */ 469 {IXGBE_TDBAL(0), "TDBAL"}, 470 {IXGBE_TDBAH(0), "TDBAH"}, 471 {IXGBE_TDLEN(0), "TDLEN"}, 472 {IXGBE_TDH(0), "TDH"}, 473 {IXGBE_TDT(0), "TDT"}, 474 {IXGBE_TXDCTL(0), "TXDCTL"}, 475 476 /* List Terminator */ 477 { .name = NULL } 478 }; 479 480 481 /* 482 * ixgbe_regdump - register printout routine 483 */ 484 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) 485 { 486 int i; 487 char rname[16]; 488 u32 regs[64]; 489 490 switch (reginfo->ofs) { 491 case IXGBE_SRRCTL(0): 492 for (i = 0; i < 64; i++) 493 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); 494 break; 495 case IXGBE_DCA_RXCTRL(0): 496 for (i = 0; i < 64; i++) 497 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 498 break; 499 case IXGBE_RDLEN(0): 500 for (i = 0; i < 64; i++) 501 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); 502 break; 503 case IXGBE_RDH(0): 504 for (i = 0; i < 64; i++) 505 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); 506 break; 507 case IXGBE_RDT(0): 508 for (i = 0; i < 64; i++) 509 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); 510 break; 511 case IXGBE_RXDCTL(0): 512 for (i = 0; i < 64; i++) 513 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 514 break; 515 case IXGBE_RDBAL(0): 516 for (i = 0; i < 64; i++) 517 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); 518 break; 519 case IXGBE_RDBAH(0): 520 for (i = 0; i < 64; i++) 521 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); 522 break; 523 case IXGBE_TDBAL(0): 524 for (i = 0; i < 64; i++) 525 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); 526 break; 527 case IXGBE_TDBAH(0): 528 for (i = 0; i < 64; i++) 529 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); 530 break; 531 case IXGBE_TDLEN(0): 532 for (i = 0; i < 64; i++) 533 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); 534 break; 535 case IXGBE_TDH(0): 536 for (i = 0; i < 64; i++) 537 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); 538 break; 539 case IXGBE_TDT(0): 540 for (i = 0; i < 64; i++) 541 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); 542 break; 543 case IXGBE_TXDCTL(0): 544 for (i = 0; i < 64; i++) 545 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 546 break; 547 default: 548 pr_info("%-15s %08x\n", 549 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs)); 550 return; 551 } 552 553 i = 0; 554 while (i < 64) { 555 int j; 556 char buf[9 * 8 + 1]; 557 char *p = buf; 558 559 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7); 560 for (j = 0; j < 8; j++) 561 p += sprintf(p, " %08x", regs[i++]); 562 pr_err("%-15s%s\n", rname, buf); 563 } 564 565 } 566 567 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n) 568 { 569 struct ixgbe_tx_buffer *tx_buffer; 570 571 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean]; 572 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", 573 n, ring->next_to_use, ring->next_to_clean, 574 (u64)dma_unmap_addr(tx_buffer, dma), 575 dma_unmap_len(tx_buffer, len), 576 tx_buffer->next_to_watch, 577 (u64)tx_buffer->time_stamp); 578 } 579 580 /* 581 * ixgbe_dump - Print registers, tx-rings and rx-rings 582 */ 583 static void ixgbe_dump(struct ixgbe_adapter *adapter) 584 { 585 struct net_device *netdev = adapter->netdev; 586 struct ixgbe_hw *hw = &adapter->hw; 587 struct ixgbe_reg_info *reginfo; 588 int n = 0; 589 struct ixgbe_ring *ring; 590 struct ixgbe_tx_buffer *tx_buffer; 591 union ixgbe_adv_tx_desc *tx_desc; 592 struct my_u0 { u64 a; u64 b; } *u0; 593 struct ixgbe_ring *rx_ring; 594 union ixgbe_adv_rx_desc *rx_desc; 595 struct ixgbe_rx_buffer *rx_buffer_info; 596 int i = 0; 597 598 if (!netif_msg_hw(adapter)) 599 return; 600 601 /* Print netdevice Info */ 602 if (netdev) { 603 dev_info(&adapter->pdev->dev, "Net device Info\n"); 604 pr_info("Device Name state " 605 "trans_start\n"); 606 pr_info("%-15s %016lX %016lX\n", 607 netdev->name, 608 netdev->state, 609 dev_trans_start(netdev)); 610 } 611 612 /* Print Registers */ 613 dev_info(&adapter->pdev->dev, "Register Dump\n"); 614 pr_info(" Register Name Value\n"); 615 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; 616 reginfo->name; reginfo++) { 617 ixgbe_regdump(hw, reginfo); 618 } 619 620 /* Print TX Ring Summary */ 621 if (!netdev || !netif_running(netdev)) 622 return; 623 624 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 625 pr_info(" %s %s %s %s\n", 626 "Queue [NTU] [NTC] [bi(ntc)->dma ]", 627 "leng", "ntw", "timestamp"); 628 for (n = 0; n < adapter->num_tx_queues; n++) { 629 ring = adapter->tx_ring[n]; 630 ixgbe_print_buffer(ring, n); 631 } 632 633 for (n = 0; n < adapter->num_xdp_queues; n++) { 634 ring = adapter->xdp_ring[n]; 635 ixgbe_print_buffer(ring, n); 636 } 637 638 /* Print TX Rings */ 639 if (!netif_msg_tx_done(adapter)) 640 goto rx_ring_summary; 641 642 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 643 644 /* Transmit Descriptor Formats 645 * 646 * 82598 Advanced Transmit Descriptor 647 * +--------------------------------------------------------------+ 648 * 0 | Buffer Address [63:0] | 649 * +--------------------------------------------------------------+ 650 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | 651 * +--------------------------------------------------------------+ 652 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 653 * 654 * 82598 Advanced Transmit Descriptor (Write-Back Format) 655 * +--------------------------------------------------------------+ 656 * 0 | RSV [63:0] | 657 * +--------------------------------------------------------------+ 658 * 8 | RSV | STA | NXTSEQ | 659 * +--------------------------------------------------------------+ 660 * 63 36 35 32 31 0 661 * 662 * 82599+ Advanced Transmit Descriptor 663 * +--------------------------------------------------------------+ 664 * 0 | Buffer Address [63:0] | 665 * +--------------------------------------------------------------+ 666 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | 667 * +--------------------------------------------------------------+ 668 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 669 * 670 * 82599+ Advanced Transmit Descriptor (Write-Back Format) 671 * +--------------------------------------------------------------+ 672 * 0 | RSV [63:0] | 673 * +--------------------------------------------------------------+ 674 * 8 | RSV | STA | RSV | 675 * +--------------------------------------------------------------+ 676 * 63 36 35 32 31 0 677 */ 678 679 for (n = 0; n < adapter->num_tx_queues; n++) { 680 ring = adapter->tx_ring[n]; 681 pr_info("------------------------------------\n"); 682 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index); 683 pr_info("------------------------------------\n"); 684 pr_info("%s%s %s %s %s %s\n", 685 "T [desc] [address 63:0 ] ", 686 "[PlPOIdStDDt Ln] [bi->dma ] ", 687 "leng", "ntw", "timestamp", "bi->skb"); 688 689 for (i = 0; ring->desc && (i < ring->count); i++) { 690 tx_desc = IXGBE_TX_DESC(ring, i); 691 tx_buffer = &ring->tx_buffer_info[i]; 692 u0 = (struct my_u0 *)tx_desc; 693 if (dma_unmap_len(tx_buffer, len) > 0) { 694 const char *ring_desc; 695 696 if (i == ring->next_to_use && 697 i == ring->next_to_clean) 698 ring_desc = " NTC/U"; 699 else if (i == ring->next_to_use) 700 ring_desc = " NTU"; 701 else if (i == ring->next_to_clean) 702 ring_desc = " NTC"; 703 else 704 ring_desc = ""; 705 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s", 706 i, 707 le64_to_cpu((__force __le64)u0->a), 708 le64_to_cpu((__force __le64)u0->b), 709 (u64)dma_unmap_addr(tx_buffer, dma), 710 dma_unmap_len(tx_buffer, len), 711 tx_buffer->next_to_watch, 712 (u64)tx_buffer->time_stamp, 713 tx_buffer->skb, 714 ring_desc); 715 716 if (netif_msg_pktdata(adapter) && 717 tx_buffer->skb) 718 print_hex_dump(KERN_INFO, "", 719 DUMP_PREFIX_ADDRESS, 16, 1, 720 tx_buffer->skb->data, 721 dma_unmap_len(tx_buffer, len), 722 true); 723 } 724 } 725 } 726 727 /* Print RX Rings Summary */ 728 rx_ring_summary: 729 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 730 pr_info("Queue [NTU] [NTC]\n"); 731 for (n = 0; n < adapter->num_rx_queues; n++) { 732 rx_ring = adapter->rx_ring[n]; 733 pr_info("%5d %5X %5X\n", 734 n, rx_ring->next_to_use, rx_ring->next_to_clean); 735 } 736 737 /* Print RX Rings */ 738 if (!netif_msg_rx_status(adapter)) 739 return; 740 741 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 742 743 /* Receive Descriptor Formats 744 * 745 * 82598 Advanced Receive Descriptor (Read) Format 746 * 63 1 0 747 * +-----------------------------------------------------+ 748 * 0 | Packet Buffer Address [63:1] |A0/NSE| 749 * +----------------------------------------------+------+ 750 * 8 | Header Buffer Address [63:1] | DD | 751 * +-----------------------------------------------------+ 752 * 753 * 754 * 82598 Advanced Receive Descriptor (Write-Back) Format 755 * 756 * 63 48 47 32 31 30 21 20 16 15 4 3 0 757 * +------------------------------------------------------+ 758 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | 759 * | Packet | IP | | | | Type | Type | 760 * | Checksum | Ident | | | | | | 761 * +------------------------------------------------------+ 762 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 763 * +------------------------------------------------------+ 764 * 63 48 47 32 31 20 19 0 765 * 766 * 82599+ Advanced Receive Descriptor (Read) Format 767 * 63 1 0 768 * +-----------------------------------------------------+ 769 * 0 | Packet Buffer Address [63:1] |A0/NSE| 770 * +----------------------------------------------+------+ 771 * 8 | Header Buffer Address [63:1] | DD | 772 * +-----------------------------------------------------+ 773 * 774 * 775 * 82599+ Advanced Receive Descriptor (Write-Back) Format 776 * 777 * 63 48 47 32 31 30 21 20 17 16 4 3 0 778 * +------------------------------------------------------+ 779 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | 780 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | 781 * |/ Flow Dir Flt ID | | | | | | 782 * +------------------------------------------------------+ 783 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | 784 * +------------------------------------------------------+ 785 * 63 48 47 32 31 20 19 0 786 */ 787 788 for (n = 0; n < adapter->num_rx_queues; n++) { 789 rx_ring = adapter->rx_ring[n]; 790 pr_info("------------------------------------\n"); 791 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 792 pr_info("------------------------------------\n"); 793 pr_info("%s%s%s\n", 794 "R [desc] [ PktBuf A0] ", 795 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", 796 "<-- Adv Rx Read format"); 797 pr_info("%s%s%s\n", 798 "RWB[desc] [PcsmIpSHl PtRs] ", 799 "[vl er S cks ln] ---------------- [bi->skb ] ", 800 "<-- Adv Rx Write-Back format"); 801 802 for (i = 0; i < rx_ring->count; i++) { 803 const char *ring_desc; 804 805 if (i == rx_ring->next_to_use) 806 ring_desc = " NTU"; 807 else if (i == rx_ring->next_to_clean) 808 ring_desc = " NTC"; 809 else 810 ring_desc = ""; 811 812 rx_buffer_info = &rx_ring->rx_buffer_info[i]; 813 rx_desc = IXGBE_RX_DESC(rx_ring, i); 814 u0 = (struct my_u0 *)rx_desc; 815 if (rx_desc->wb.upper.length) { 816 /* Descriptor Done */ 817 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n", 818 i, 819 le64_to_cpu((__force __le64)u0->a), 820 le64_to_cpu((__force __le64)u0->b), 821 rx_buffer_info->skb, 822 ring_desc); 823 } else { 824 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n", 825 i, 826 le64_to_cpu((__force __le64)u0->a), 827 le64_to_cpu((__force __le64)u0->b), 828 (u64)rx_buffer_info->dma, 829 rx_buffer_info->skb, 830 ring_desc); 831 832 if (netif_msg_pktdata(adapter) && 833 rx_buffer_info->dma) { 834 print_hex_dump(KERN_INFO, "", 835 DUMP_PREFIX_ADDRESS, 16, 1, 836 page_address(rx_buffer_info->page) + 837 rx_buffer_info->page_offset, 838 ixgbe_rx_bufsz(rx_ring), true); 839 } 840 } 841 } 842 } 843 } 844 845 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) 846 { 847 u32 ctrl_ext; 848 849 /* Let firmware take over control of h/w */ 850 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 851 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 852 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); 853 } 854 855 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) 856 { 857 u32 ctrl_ext; 858 859 /* Let firmware know the driver has taken over */ 860 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); 861 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, 862 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); 863 } 864 865 /** 866 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 867 * @adapter: pointer to adapter struct 868 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 869 * @queue: queue to map the corresponding interrupt to 870 * @msix_vector: the vector to map to the corresponding queue 871 * 872 */ 873 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, 874 u8 queue, u8 msix_vector) 875 { 876 u32 ivar, index; 877 struct ixgbe_hw *hw = &adapter->hw; 878 switch (hw->mac.type) { 879 case ixgbe_mac_82598EB: 880 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 881 if (direction == -1) 882 direction = 0; 883 index = (((direction * 64) + queue) >> 2) & 0x1F; 884 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); 885 ivar &= ~(0xFF << (8 * (queue & 0x3))); 886 ivar |= (msix_vector << (8 * (queue & 0x3))); 887 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); 888 break; 889 case ixgbe_mac_82599EB: 890 case ixgbe_mac_X540: 891 case ixgbe_mac_X550: 892 case ixgbe_mac_X550EM_x: 893 case ixgbe_mac_x550em_a: 894 case ixgbe_mac_e610: 895 if (direction == -1) { 896 /* other causes */ 897 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 898 index = ((queue & 1) * 8); 899 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); 900 ivar &= ~(0xFF << index); 901 ivar |= (msix_vector << index); 902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); 903 break; 904 } else { 905 /* tx or rx causes */ 906 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 907 index = ((16 * (queue & 1)) + (8 * direction)); 908 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 909 ivar &= ~(0xFF << index); 910 ivar |= (msix_vector << index); 911 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); 912 break; 913 } 914 default: 915 break; 916 } 917 } 918 919 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, 920 u64 qmask) 921 { 922 u32 mask; 923 924 switch (adapter->hw.mac.type) { 925 case ixgbe_mac_82598EB: 926 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 927 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); 928 break; 929 case ixgbe_mac_82599EB: 930 case ixgbe_mac_X540: 931 case ixgbe_mac_X550: 932 case ixgbe_mac_X550EM_x: 933 case ixgbe_mac_x550em_a: 934 case ixgbe_mac_e610: 935 mask = (qmask & 0xFFFFFFFF); 936 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); 937 mask = (qmask >> 32); 938 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); 939 break; 940 default: 941 break; 942 } 943 } 944 945 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) 946 { 947 struct ixgbe_hw *hw = &adapter->hw; 948 struct ixgbe_hw_stats *hwstats = &adapter->stats; 949 int i; 950 u32 data; 951 952 if ((hw->fc.current_mode != ixgbe_fc_full) && 953 (hw->fc.current_mode != ixgbe_fc_rx_pause)) 954 return; 955 956 switch (hw->mac.type) { 957 case ixgbe_mac_82598EB: 958 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 959 break; 960 default: 961 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 962 } 963 hwstats->lxoffrxc += data; 964 965 /* refill credits (no tx hang) if we received xoff */ 966 if (!data) 967 return; 968 969 for (i = 0; i < adapter->num_tx_queues; i++) 970 clear_bit(__IXGBE_HANG_CHECK_ARMED, 971 adapter->tx_ring[i]->state); 972 } 973 974 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) 975 { 976 struct ixgbe_hw *hw = &adapter->hw; 977 struct ixgbe_hw_stats *hwstats = &adapter->stats; 978 u32 xoff[8] = {0}; 979 u8 tc; 980 int i; 981 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 982 983 if (adapter->ixgbe_ieee_pfc) 984 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 985 986 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { 987 ixgbe_update_xoff_rx_lfc(adapter); 988 return; 989 } 990 991 /* update stats for each tc, only valid with PFC enabled */ 992 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { 993 u32 pxoffrxc; 994 995 switch (hw->mac.type) { 996 case ixgbe_mac_82598EB: 997 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 998 break; 999 default: 1000 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 1001 } 1002 hwstats->pxoffrxc[i] += pxoffrxc; 1003 /* Get the TC for given UP */ 1004 tc = netdev_get_prio_tc_map(adapter->netdev, i); 1005 xoff[tc] += pxoffrxc; 1006 } 1007 1008 /* disarm tx queues that have received xoff frames */ 1009 for (i = 0; i < adapter->num_tx_queues; i++) { 1010 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 1011 1012 tc = tx_ring->dcb_tc; 1013 if (xoff[tc]) 1014 clear_bit(__IXGBE_HANG_CHECK_ARMED, tx_ring->state); 1015 } 1016 1017 for (i = 0; i < adapter->num_xdp_queues; i++) { 1018 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i]; 1019 1020 tc = xdp_ring->dcb_tc; 1021 if (xoff[tc]) 1022 clear_bit(__IXGBE_HANG_CHECK_ARMED, xdp_ring->state); 1023 } 1024 } 1025 1026 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) 1027 { 1028 return ring->stats.packets; 1029 } 1030 1031 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) 1032 { 1033 unsigned int head, tail; 1034 1035 head = ring->next_to_clean; 1036 tail = ring->next_to_use; 1037 1038 return ((head <= tail) ? tail : tail + ring->count) - head; 1039 } 1040 1041 /** 1042 * ixgbe_get_vf_idx - provide VF index number based on queue index 1043 * @adapter: pointer to the adapter struct 1044 * @queue: Tx queue identifier 1045 * @vf: output VF index 1046 * 1047 * Provide VF index number associated to the input queue. 1048 * 1049 * Returns: 0 if VF provided or error number. 1050 */ 1051 static int ixgbe_get_vf_idx(struct ixgbe_adapter *adapter, u16 queue, u16 *vf) 1052 { 1053 struct ixgbe_hw *hw = &adapter->hw; 1054 u8 queue_count; 1055 u32 reg; 1056 1057 if (queue >= adapter->num_tx_queues) 1058 return -EINVAL; 1059 1060 /* Determine number of queues by checking 1061 * number of virtual functions 1062 */ 1063 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 1064 switch (reg & IXGBE_GCR_EXT_VT_MODE_MASK) { 1065 case IXGBE_GCR_EXT_VT_MODE_64: 1066 queue_count = IXGBE_64VFS_QUEUES; 1067 break; 1068 case IXGBE_GCR_EXT_VT_MODE_32: 1069 queue_count = IXGBE_32VFS_QUEUES; 1070 break; 1071 case IXGBE_GCR_EXT_VT_MODE_16: 1072 queue_count = IXGBE_16VFS_QUEUES; 1073 break; 1074 default: 1075 return -EINVAL; 1076 } 1077 1078 *vf = queue / queue_count; 1079 1080 return 0; 1081 } 1082 1083 static bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) 1084 { 1085 u32 tx_done = ixgbe_get_tx_completed(tx_ring); 1086 u32 tx_done_old = tx_ring->tx_stats.tx_done_old; 1087 u32 tx_pending = ixgbe_get_tx_pending(tx_ring); 1088 1089 clear_check_for_tx_hang(tx_ring); 1090 1091 /* 1092 * Check for a hung queue, but be thorough. This verifies 1093 * that a transmit has been completed since the previous 1094 * check AND there is at least one packet pending. The 1095 * ARMED bit is set to indicate a potential hang. The 1096 * bit is cleared if a pause frame is received to remove 1097 * false hang detection due to PFC or 802.3x frames. By 1098 * requiring this to fail twice we avoid races with 1099 * pfc clearing the ARMED bit and conditions where we 1100 * run the check_tx_hang logic with a transmit completion 1101 * pending but without time to complete it yet. 1102 */ 1103 if (tx_done_old == tx_done && tx_pending) 1104 /* make sure it is true for two checks in a row */ 1105 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, 1106 tx_ring->state); 1107 /* update completed stats and continue */ 1108 tx_ring->tx_stats.tx_done_old = tx_done; 1109 /* reset the countdown */ 1110 clear_bit(__IXGBE_HANG_CHECK_ARMED, tx_ring->state); 1111 1112 return false; 1113 } 1114 1115 /** 1116 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout 1117 * @adapter: driver private struct 1118 **/ 1119 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) 1120 { 1121 1122 /* Do the reset outside of interrupt context */ 1123 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 1124 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 1125 e_warn(drv, "initiating reset due to tx timeout\n"); 1126 ixgbe_service_event_schedule(adapter); 1127 } 1128 } 1129 1130 /** 1131 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate 1132 * @netdev: network interface device structure 1133 * @queue_index: Tx queue to set 1134 * @maxrate: desired maximum transmit bitrate 1135 **/ 1136 static int ixgbe_tx_maxrate(struct net_device *netdev, 1137 int queue_index, u32 maxrate) 1138 { 1139 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 1140 struct ixgbe_hw *hw = &adapter->hw; 1141 u32 bcnrc_val = ixgbe_link_mbps(adapter); 1142 1143 if (!maxrate) 1144 return 0; 1145 1146 /* Calculate the rate factor values to set */ 1147 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; 1148 bcnrc_val /= maxrate; 1149 1150 /* clear everything but the rate factor */ 1151 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | 1152 IXGBE_RTTBCNRC_RF_DEC_MASK; 1153 1154 /* enable the rate scheduler */ 1155 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; 1156 1157 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); 1158 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 1159 1160 return 0; 1161 } 1162 1163 /** 1164 * ixgbe_update_tx_ring_stats - Update Tx ring specific counters 1165 * @tx_ring: ring to update 1166 * @q_vector: queue vector ring belongs to 1167 * @pkts: number of processed packets 1168 * @bytes: number of processed bytes 1169 */ 1170 void ixgbe_update_tx_ring_stats(struct ixgbe_ring *tx_ring, 1171 struct ixgbe_q_vector *q_vector, u64 pkts, 1172 u64 bytes) 1173 { 1174 u64_stats_update_begin(&tx_ring->syncp); 1175 tx_ring->stats.bytes += bytes; 1176 tx_ring->stats.packets += pkts; 1177 u64_stats_update_end(&tx_ring->syncp); 1178 q_vector->tx.total_bytes += bytes; 1179 q_vector->tx.total_packets += pkts; 1180 } 1181 1182 /** 1183 * ixgbe_update_rx_ring_stats - Update Rx ring specific counters 1184 * @rx_ring: ring to update 1185 * @q_vector: queue vector ring belongs to 1186 * @pkts: number of processed packets 1187 * @bytes: number of processed bytes 1188 */ 1189 void ixgbe_update_rx_ring_stats(struct ixgbe_ring *rx_ring, 1190 struct ixgbe_q_vector *q_vector, u64 pkts, 1191 u64 bytes) 1192 { 1193 u64_stats_update_begin(&rx_ring->syncp); 1194 rx_ring->stats.bytes += bytes; 1195 rx_ring->stats.packets += pkts; 1196 u64_stats_update_end(&rx_ring->syncp); 1197 q_vector->rx.total_bytes += bytes; 1198 q_vector->rx.total_packets += pkts; 1199 } 1200 1201 /** 1202 * ixgbe_pf_handle_tx_hang - handle Tx hang on PF 1203 * @tx_ring: tx ring number 1204 * @next: next ring 1205 * 1206 * Prints a message containing details about the tx hang. 1207 */ 1208 static void ixgbe_pf_handle_tx_hang(struct ixgbe_ring *tx_ring, 1209 unsigned int next) 1210 { 1211 struct ixgbe_adapter *adapter = netdev_priv(tx_ring->netdev); 1212 struct ixgbe_hw *hw = &adapter->hw; 1213 1214 e_err(drv, "Detected Tx Unit Hang\n" 1215 " Tx Queue <%d>\n" 1216 " TDH, TDT <%x>, <%x>\n" 1217 " next_to_use <%x>\n" 1218 " next_to_clean <%x>\n" 1219 "tx_buffer_info[next_to_clean]\n" 1220 " time_stamp <%lx>\n" 1221 " jiffies <%lx>\n", 1222 tx_ring->queue_index, 1223 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), 1224 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), 1225 tx_ring->next_to_use, next, 1226 tx_ring->tx_buffer_info[next].time_stamp, jiffies); 1227 1228 netif_stop_subqueue(tx_ring->netdev, 1229 tx_ring->queue_index); 1230 } 1231 1232 /** 1233 * ixgbe_vf_handle_tx_hang - handle Tx hang on VF 1234 * @adapter: structure containing ring specific data 1235 * @vf: VF index 1236 * 1237 * Print a message containing details about malicious driver detection. 1238 * Set malicious VF link down if the detection happened several times. 1239 */ 1240 static void ixgbe_vf_handle_tx_hang(struct ixgbe_adapter *adapter, u16 vf) 1241 { 1242 struct ixgbe_hw *hw = &adapter->hw; 1243 1244 if (adapter->hw.mac.type != ixgbe_mac_e610) 1245 return; 1246 1247 e_warn(drv, 1248 "Malicious Driver Detection tx hang detected on PF %d VF %d MAC: %pM", 1249 hw->bus.func, vf, adapter->vfinfo[vf].vf_mac_addresses); 1250 1251 adapter->tx_hang_count[vf]++; 1252 if (adapter->tx_hang_count[vf] == IXGBE_MAX_TX_VF_HANGS) { 1253 ixgbe_set_vf_link_state(adapter, vf, 1254 IFLA_VF_LINK_STATE_DISABLE); 1255 adapter->tx_hang_count[vf] = 0; 1256 } 1257 } 1258 1259 static u32 ixgbe_poll_tx_icache(struct ixgbe_hw *hw, u16 queue, u16 idx) 1260 { 1261 IXGBE_WRITE_REG(hw, IXGBE_TXDESCIC, queue * idx); 1262 return IXGBE_READ_REG(hw, IXGBE_TXDESCIC); 1263 } 1264 1265 /** 1266 * ixgbe_check_illegal_queue - search for queue with illegal packet 1267 * @adapter: structure containing ring specific data 1268 * @queue: queue index 1269 * 1270 * Check if tx descriptor connected with input queue 1271 * contains illegal packet. 1272 * 1273 * Returns: true if queue contain illegal packet. 1274 */ 1275 static bool ixgbe_check_illegal_queue(struct ixgbe_adapter *adapter, 1276 u16 queue) 1277 { 1278 u32 hdr_len_reg, mss_len_reg, type_reg; 1279 struct ixgbe_hw *hw = &adapter->hw; 1280 u32 mss_len, header_len, reg; 1281 1282 for (u16 i = 0; i < IXGBE_MAX_TX_DESCRIPTORS; i++) { 1283 /* HW will clear bit IXGBE_TXDESCIC_READY when address 1284 * is written to address field. HW will set this bit 1285 * when iCache read is done, and data is ready at TIC_DWx. 1286 * Set descriptor address. 1287 */ 1288 read_poll_timeout(ixgbe_poll_tx_icache, reg, 1289 !(reg & IXGBE_TXDESCIC_READY), 0, 0, false, 1290 hw, queue, i); 1291 1292 /* read tx descriptor access registers */ 1293 hdr_len_reg = IXGBE_READ_REG(hw, IXGBE_TIC_DW2(IXGBE_VLAN_MACIP_LENS_REG)); 1294 type_reg = IXGBE_READ_REG(hw, IXGBE_TIC_DW2(IXGBE_TYPE_TUCMD_MLHL)); 1295 mss_len_reg = IXGBE_READ_REG(hw, IXGBE_TIC_DW2(IXGBE_MSS_L4LEN_IDX)); 1296 1297 /* check if Advanced Context Descriptor */ 1298 if (FIELD_GET(IXGBE_ADVTXD_DTYP_MASK, type_reg) != 1299 IXGBE_ADVTXD_DTYP_CTXT) 1300 continue; 1301 1302 /* check for illegal MSS and Header length */ 1303 mss_len = FIELD_GET(IXGBE_ADVTXD_MSS_MASK, mss_len_reg); 1304 header_len = FIELD_GET(IXGBE_ADVTXD_HEADER_LEN_MASK, 1305 hdr_len_reg); 1306 if ((mss_len + header_len) > SZ_16K) { 1307 e_warn(probe, "mss len + header len too long\n"); 1308 return true; 1309 } 1310 } 1311 1312 return false; 1313 } 1314 1315 /** 1316 * ixgbe_handle_mdd_event - handle mdd event 1317 * @adapter: structure containing ring specific data 1318 * @tx_ring: tx descriptor ring to handle 1319 * 1320 * Reset VF driver if malicious vf detected or 1321 * illegal packet in an any queue detected. 1322 */ 1323 static void ixgbe_handle_mdd_event(struct ixgbe_adapter *adapter, 1324 struct ixgbe_ring *tx_ring) 1325 { 1326 u16 vf, q; 1327 1328 if (adapter->vfinfo && ixgbe_check_mdd_event(adapter)) { 1329 /* vf mdd info and malicious vf detected */ 1330 if (!ixgbe_get_vf_idx(adapter, tx_ring->queue_index, &vf)) 1331 ixgbe_vf_handle_tx_hang(adapter, vf); 1332 } else { 1333 /* malicious vf not detected */ 1334 for (q = 0; q < IXGBE_MAX_TX_QUEUES; q++) { 1335 if (ixgbe_check_illegal_queue(adapter, q) && 1336 !ixgbe_get_vf_idx(adapter, q, &vf)) 1337 /* illegal queue detected */ 1338 ixgbe_vf_handle_tx_hang(adapter, vf); 1339 } 1340 } 1341 } 1342 1343 /** 1344 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes 1345 * @q_vector: structure containing interrupt and ring information 1346 * @tx_ring: tx ring to clean 1347 * @napi_budget: Used to determine if we are in netpoll 1348 **/ 1349 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, 1350 struct ixgbe_ring *tx_ring, int napi_budget) 1351 { 1352 struct ixgbe_adapter *adapter = q_vector->adapter; 1353 struct ixgbe_tx_buffer *tx_buffer; 1354 union ixgbe_adv_tx_desc *tx_desc; 1355 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0; 1356 unsigned int budget = q_vector->tx.work_limit; 1357 unsigned int i = tx_ring->next_to_clean; 1358 struct netdev_queue *txq; 1359 1360 if (test_bit(__IXGBE_DOWN, &adapter->state)) 1361 return true; 1362 1363 tx_buffer = &tx_ring->tx_buffer_info[i]; 1364 tx_desc = IXGBE_TX_DESC(tx_ring, i); 1365 i -= tx_ring->count; 1366 1367 do { 1368 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 1369 1370 /* if next_to_watch is not set then there is no work pending */ 1371 if (!eop_desc) 1372 break; 1373 1374 /* prevent any other reads prior to eop_desc */ 1375 smp_rmb(); 1376 1377 /* if DD is not set pending work has not been completed */ 1378 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 1379 break; 1380 1381 /* clear next_to_watch to prevent false hangs */ 1382 tx_buffer->next_to_watch = NULL; 1383 1384 /* update the statistics for this packet */ 1385 total_bytes += tx_buffer->bytecount; 1386 total_packets += tx_buffer->gso_segs; 1387 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC) 1388 total_ipsec++; 1389 1390 /* free the skb */ 1391 if (ring_is_xdp(tx_ring)) 1392 xdp_return_frame(tx_buffer->xdpf); 1393 else 1394 napi_consume_skb(tx_buffer->skb, napi_budget); 1395 1396 /* unmap skb header data */ 1397 dma_unmap_single(tx_ring->dev, 1398 dma_unmap_addr(tx_buffer, dma), 1399 dma_unmap_len(tx_buffer, len), 1400 DMA_TO_DEVICE); 1401 1402 /* clear tx_buffer data */ 1403 dma_unmap_len_set(tx_buffer, len, 0); 1404 1405 /* unmap remaining buffers */ 1406 while (tx_desc != eop_desc) { 1407 tx_buffer++; 1408 tx_desc++; 1409 i++; 1410 if (unlikely(!i)) { 1411 i -= tx_ring->count; 1412 tx_buffer = tx_ring->tx_buffer_info; 1413 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1414 } 1415 1416 /* unmap any remaining paged data */ 1417 if (dma_unmap_len(tx_buffer, len)) { 1418 dma_unmap_page(tx_ring->dev, 1419 dma_unmap_addr(tx_buffer, dma), 1420 dma_unmap_len(tx_buffer, len), 1421 DMA_TO_DEVICE); 1422 dma_unmap_len_set(tx_buffer, len, 0); 1423 } 1424 } 1425 1426 /* move us one more past the eop_desc for start of next pkt */ 1427 tx_buffer++; 1428 tx_desc++; 1429 i++; 1430 if (unlikely(!i)) { 1431 i -= tx_ring->count; 1432 tx_buffer = tx_ring->tx_buffer_info; 1433 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 1434 } 1435 1436 /* issue prefetch for next Tx descriptor */ 1437 prefetch(tx_desc); 1438 1439 /* update budget accounting */ 1440 budget--; 1441 } while (likely(budget)); 1442 1443 i += tx_ring->count; 1444 tx_ring->next_to_clean = i; 1445 ixgbe_update_tx_ring_stats(tx_ring, q_vector, total_packets, 1446 total_bytes); 1447 adapter->tx_ipsec += total_ipsec; 1448 1449 if (ring_is_xdp(tx_ring)) 1450 return !!budget; 1451 1452 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { 1453 if (adapter->hw.mac.type == ixgbe_mac_e610) 1454 ixgbe_handle_mdd_event(adapter, tx_ring); 1455 1456 ixgbe_pf_handle_tx_hang(tx_ring, i); 1457 1458 e_info(probe, 1459 "tx hang %d detected on queue %d, resetting adapter\n", 1460 adapter->tx_timeout_count + 1, tx_ring->queue_index); 1461 1462 /* schedule immediate reset if we believe we hung */ 1463 ixgbe_tx_timeout_reset(adapter); 1464 1465 /* the adapter is about to reset, no point in enabling stuff */ 1466 return true; 1467 } 1468 1469 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 1470 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 1471 if (!__netif_txq_completed_wake(txq, total_packets, total_bytes, 1472 ixgbe_desc_unused(tx_ring), 1473 TX_WAKE_THRESHOLD, 1474 !netif_carrier_ok(tx_ring->netdev) || 1475 test_bit(__IXGBE_DOWN, &adapter->state))) 1476 ++tx_ring->tx_stats.restart_queue; 1477 1478 return !!budget; 1479 } 1480 1481 #ifdef CONFIG_IXGBE_DCA 1482 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 1483 struct ixgbe_ring *tx_ring, 1484 int cpu) 1485 { 1486 struct ixgbe_hw *hw = &adapter->hw; 1487 u32 txctrl = 0; 1488 u16 reg_offset; 1489 1490 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1491 txctrl = dca3_get_tag(tx_ring->dev, cpu); 1492 1493 switch (hw->mac.type) { 1494 case ixgbe_mac_82598EB: 1495 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); 1496 break; 1497 case ixgbe_mac_82599EB: 1498 case ixgbe_mac_X540: 1499 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); 1500 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; 1501 break; 1502 default: 1503 /* for unknown hardware do not write register */ 1504 return; 1505 } 1506 1507 /* 1508 * We can enable relaxed ordering for reads, but not writes when 1509 * DCA is enabled. This is due to a known issue in some chipsets 1510 * which will cause the DCA tag to be cleared. 1511 */ 1512 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | 1513 IXGBE_DCA_TXCTRL_DATA_RRO_EN | 1514 IXGBE_DCA_TXCTRL_DESC_DCA_EN; 1515 1516 IXGBE_WRITE_REG(hw, reg_offset, txctrl); 1517 } 1518 1519 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 1520 struct ixgbe_ring *rx_ring, 1521 int cpu) 1522 { 1523 struct ixgbe_hw *hw = &adapter->hw; 1524 u32 rxctrl = 0; 1525 u8 reg_idx = rx_ring->reg_idx; 1526 1527 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1528 rxctrl = dca3_get_tag(rx_ring->dev, cpu); 1529 1530 switch (hw->mac.type) { 1531 case ixgbe_mac_82599EB: 1532 case ixgbe_mac_X540: 1533 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; 1534 break; 1535 default: 1536 break; 1537 } 1538 1539 /* 1540 * We can enable relaxed ordering for reads, but not writes when 1541 * DCA is enabled. This is due to a known issue in some chipsets 1542 * which will cause the DCA tag to be cleared. 1543 */ 1544 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | 1545 IXGBE_DCA_RXCTRL_DATA_DCA_EN | 1546 IXGBE_DCA_RXCTRL_DESC_DCA_EN; 1547 1548 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); 1549 } 1550 1551 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) 1552 { 1553 struct ixgbe_adapter *adapter = q_vector->adapter; 1554 struct ixgbe_ring *ring; 1555 int cpu = get_cpu(); 1556 1557 if (q_vector->cpu == cpu) 1558 goto out_no_update; 1559 1560 ixgbe_for_each_ring(ring, q_vector->tx) 1561 ixgbe_update_tx_dca(adapter, ring, cpu); 1562 1563 ixgbe_for_each_ring(ring, q_vector->rx) 1564 ixgbe_update_rx_dca(adapter, ring, cpu); 1565 1566 q_vector->cpu = cpu; 1567 out_no_update: 1568 put_cpu(); 1569 } 1570 1571 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) 1572 { 1573 int i; 1574 1575 /* always use CB2 mode, difference is masked in the CB driver */ 1576 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1578 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1579 else 1580 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1581 IXGBE_DCA_CTRL_DCA_DISABLE); 1582 1583 for (i = 0; i < adapter->num_q_vectors; i++) { 1584 adapter->q_vector[i]->cpu = -1; 1585 ixgbe_update_dca(adapter->q_vector[i]); 1586 } 1587 } 1588 1589 static int __ixgbe_notify_dca(struct device *dev, void *data) 1590 { 1591 struct ixgbe_adapter *adapter = dev_get_drvdata(dev); 1592 unsigned long event = *(unsigned long *)data; 1593 1594 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) 1595 return 0; 1596 1597 switch (event) { 1598 case DCA_PROVIDER_ADD: 1599 /* if we're already enabled, don't do it again */ 1600 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 1601 break; 1602 if (dca_add_requester(dev) == 0) { 1603 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 1604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1605 IXGBE_DCA_CTRL_DCA_MODE_CB2); 1606 break; 1607 } 1608 fallthrough; /* DCA is disabled. */ 1609 case DCA_PROVIDER_REMOVE: 1610 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 1611 dca_remove_requester(dev); 1612 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 1613 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1614 IXGBE_DCA_CTRL_DCA_DISABLE); 1615 } 1616 break; 1617 } 1618 1619 return 0; 1620 } 1621 1622 #endif /* CONFIG_IXGBE_DCA */ 1623 1624 #define IXGBE_RSS_L4_TYPES_MASK \ 1625 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ 1626 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ 1627 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ 1628 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) 1629 1630 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, 1631 union ixgbe_adv_rx_desc *rx_desc, 1632 struct sk_buff *skb) 1633 { 1634 u16 rss_type; 1635 1636 if (!(ring->netdev->features & NETIF_F_RXHASH)) 1637 return; 1638 1639 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 1640 IXGBE_RXDADV_RSSTYPE_MASK; 1641 1642 if (!rss_type) 1643 return; 1644 1645 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 1646 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 1647 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 1648 } 1649 1650 #ifdef IXGBE_FCOE 1651 /** 1652 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type 1653 * @ring: structure containing ring specific data 1654 * @rx_desc: advanced rx descriptor 1655 * 1656 * Returns : true if it is FCoE pkt 1657 */ 1658 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, 1659 union ixgbe_adv_rx_desc *rx_desc) 1660 { 1661 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1662 1663 return test_bit(__IXGBE_RX_FCOE, ring->state) && 1664 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == 1665 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << 1666 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); 1667 } 1668 1669 #endif /* IXGBE_FCOE */ 1670 /** 1671 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum 1672 * @ring: structure containing ring specific data 1673 * @rx_desc: current Rx descriptor being processed 1674 * @skb: skb currently being received and modified 1675 **/ 1676 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, 1677 union ixgbe_adv_rx_desc *rx_desc, 1678 struct sk_buff *skb) 1679 { 1680 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; 1681 bool encap_pkt = false; 1682 1683 skb_checksum_none_assert(skb); 1684 1685 /* Rx csum disabled */ 1686 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 1687 return; 1688 1689 /* check for VXLAN and Geneve packets */ 1690 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) { 1691 encap_pkt = true; 1692 skb->encapsulation = 1; 1693 } 1694 1695 /* if IP and error */ 1696 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && 1697 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { 1698 ring->rx_stats.csum_err++; 1699 return; 1700 } 1701 1702 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) 1703 return; 1704 1705 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { 1706 /* 1707 * 82599 errata, UDP frames with a 0 checksum can be marked as 1708 * checksum errors. 1709 */ 1710 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && 1711 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, ring->state)) 1712 return; 1713 1714 ring->rx_stats.csum_err++; 1715 return; 1716 } 1717 1718 /* It must be a TCP or UDP packet with a valid checksum */ 1719 skb->ip_summed = CHECKSUM_UNNECESSARY; 1720 if (encap_pkt) { 1721 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) 1722 return; 1723 1724 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { 1725 skb->ip_summed = CHECKSUM_NONE; 1726 return; 1727 } 1728 /* If we checked the outer header let the stack know */ 1729 skb->csum_level = 1; 1730 } 1731 } 1732 1733 static unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring) 1734 { 1735 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0; 1736 } 1737 1738 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, 1739 struct ixgbe_rx_buffer *bi) 1740 { 1741 struct page *page = bi->page; 1742 dma_addr_t dma; 1743 1744 /* since we are recycling buffers we should seldom need to alloc */ 1745 if (likely(page)) 1746 return true; 1747 1748 /* alloc new page for storage */ 1749 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); 1750 if (unlikely(!page)) { 1751 rx_ring->rx_stats.alloc_rx_page_failed++; 1752 return false; 1753 } 1754 1755 /* map page for use */ 1756 dma = dma_map_page_attrs(rx_ring->dev, page, 0, 1757 ixgbe_rx_pg_size(rx_ring), 1758 DMA_FROM_DEVICE, 1759 IXGBE_RX_DMA_ATTR); 1760 1761 /* 1762 * if mapping failed free memory back to system since 1763 * there isn't much point in holding memory we can't use 1764 */ 1765 if (dma_mapping_error(rx_ring->dev, dma)) { 1766 __free_pages(page, ixgbe_rx_pg_order(rx_ring)); 1767 1768 rx_ring->rx_stats.alloc_rx_page_failed++; 1769 return false; 1770 } 1771 1772 bi->dma = dma; 1773 bi->page = page; 1774 bi->page_offset = rx_ring->rx_offset; 1775 page_ref_add(page, USHRT_MAX - 1); 1776 bi->pagecnt_bias = USHRT_MAX; 1777 rx_ring->rx_stats.alloc_rx_page++; 1778 1779 return true; 1780 } 1781 1782 /** 1783 * ixgbe_alloc_rx_buffers - Replace used receive buffers 1784 * @rx_ring: ring to place buffers on 1785 * @cleaned_count: number of buffers to replace 1786 **/ 1787 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) 1788 { 1789 union ixgbe_adv_rx_desc *rx_desc; 1790 struct ixgbe_rx_buffer *bi; 1791 u16 i = rx_ring->next_to_use; 1792 u16 bufsz; 1793 1794 /* nothing to do */ 1795 if (!cleaned_count) 1796 return; 1797 1798 rx_desc = IXGBE_RX_DESC(rx_ring, i); 1799 bi = &rx_ring->rx_buffer_info[i]; 1800 i -= rx_ring->count; 1801 1802 bufsz = ixgbe_rx_bufsz(rx_ring); 1803 1804 do { 1805 if (!ixgbe_alloc_mapped_page(rx_ring, bi)) 1806 break; 1807 1808 /* sync the buffer for use by the device */ 1809 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 1810 bi->page_offset, bufsz, 1811 DMA_FROM_DEVICE); 1812 1813 /* 1814 * Refresh the desc even if buffer_addrs didn't change 1815 * because each write-back erases this info. 1816 */ 1817 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 1818 1819 rx_desc++; 1820 bi++; 1821 i++; 1822 if (unlikely(!i)) { 1823 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 1824 bi = rx_ring->rx_buffer_info; 1825 i -= rx_ring->count; 1826 } 1827 1828 /* clear the length for the next_to_use descriptor */ 1829 rx_desc->wb.upper.length = 0; 1830 1831 cleaned_count--; 1832 } while (cleaned_count); 1833 1834 i += rx_ring->count; 1835 1836 if (rx_ring->next_to_use != i) { 1837 rx_ring->next_to_use = i; 1838 1839 /* update next to alloc since we have filled the ring */ 1840 rx_ring->next_to_alloc = i; 1841 1842 /* Force memory writes to complete before letting h/w 1843 * know there are new descriptors to fetch. (Only 1844 * applicable for weak-ordered memory model archs, 1845 * such as IA-64). 1846 */ 1847 wmb(); 1848 writel(i, rx_ring->tail); 1849 } 1850 } 1851 1852 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, 1853 struct sk_buff *skb) 1854 { 1855 u16 hdr_len = skb_headlen(skb); 1856 1857 /* set gso_size to avoid messing up TCP MSS */ 1858 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 1859 IXGBE_CB(skb)->append_cnt); 1860 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1861 } 1862 1863 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, 1864 struct sk_buff *skb) 1865 { 1866 /* if append_cnt is 0 then frame is not RSC */ 1867 if (!IXGBE_CB(skb)->append_cnt) 1868 return; 1869 1870 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; 1871 rx_ring->rx_stats.rsc_flush++; 1872 1873 ixgbe_set_rsc_gso_size(rx_ring, skb); 1874 1875 /* gso_size is computed using append_cnt so always clear it last */ 1876 IXGBE_CB(skb)->append_cnt = 0; 1877 } 1878 1879 /** 1880 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor 1881 * @rx_ring: rx descriptor ring packet is being transacted on 1882 * @rx_desc: pointer to the EOP Rx descriptor 1883 * @skb: pointer to current skb being populated 1884 * 1885 * This function checks the ring, descriptor, and packet information in 1886 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 1887 * other fields within the skb. 1888 **/ 1889 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, 1890 union ixgbe_adv_rx_desc *rx_desc, 1891 struct sk_buff *skb) 1892 { 1893 struct net_device *dev = rx_ring->netdev; 1894 u32 flags = rx_ring->q_vector->adapter->flags; 1895 1896 ixgbe_update_rsc_stats(rx_ring, skb); 1897 1898 ixgbe_rx_hash(rx_ring, rx_desc, skb); 1899 1900 ixgbe_rx_checksum(rx_ring, rx_desc, skb); 1901 1902 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) 1903 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 1904 1905 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 1906 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { 1907 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 1908 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1909 } 1910 1911 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP)) 1912 ixgbe_ipsec_rx(rx_ring, rx_desc, skb); 1913 1914 /* record Rx queue, or update MACVLAN statistics */ 1915 if (netif_is_ixgbe(dev)) 1916 skb_record_rx_queue(skb, rx_ring->queue_index); 1917 else 1918 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true, 1919 false); 1920 1921 skb->protocol = eth_type_trans(skb, dev); 1922 } 1923 1924 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, 1925 struct sk_buff *skb) 1926 { 1927 napi_gro_receive(&q_vector->napi, skb); 1928 } 1929 1930 /** 1931 * ixgbe_is_non_eop - process handling of non-EOP buffers 1932 * @rx_ring: Rx ring being processed 1933 * @rx_desc: Rx descriptor for current buffer 1934 * @skb: Current socket buffer containing buffer in progress 1935 * 1936 * This function updates next to clean. If the buffer is an EOP buffer 1937 * this function exits returning false, otherwise it will place the 1938 * sk_buff in the next buffer to be chained and return true indicating 1939 * that this is in fact a non-EOP buffer. 1940 **/ 1941 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, 1942 union ixgbe_adv_rx_desc *rx_desc, 1943 struct sk_buff *skb) 1944 { 1945 u32 ntc = rx_ring->next_to_clean + 1; 1946 1947 /* fetch, update, and store next to clean */ 1948 ntc = (ntc < rx_ring->count) ? ntc : 0; 1949 rx_ring->next_to_clean = ntc; 1950 1951 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 1952 1953 /* update RSC append count if present */ 1954 if (ring_is_rsc_enabled(rx_ring)) { 1955 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 1956 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); 1957 1958 if (unlikely(rsc_enabled)) { 1959 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 1960 1961 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; 1962 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; 1963 1964 /* update ntc based on RSC value */ 1965 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 1966 ntc &= IXGBE_RXDADV_NEXTP_MASK; 1967 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; 1968 } 1969 } 1970 1971 /* if we are the last buffer then there is nothing else to do */ 1972 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) 1973 return false; 1974 1975 /* place skb in next buffer to be received */ 1976 rx_ring->rx_buffer_info[ntc].skb = skb; 1977 rx_ring->rx_stats.non_eop_descs++; 1978 1979 return true; 1980 } 1981 1982 /** 1983 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail 1984 * @rx_ring: rx descriptor ring packet is being transacted on 1985 * @skb: pointer to current skb being adjusted 1986 * 1987 * This function is an ixgbe specific version of __pskb_pull_tail. The 1988 * main difference between this version and the original function is that 1989 * this function can make several assumptions about the state of things 1990 * that allow for significant optimizations versus the standard function. 1991 * As a result we can do things like drop a frag and maintain an accurate 1992 * truesize for the skb. 1993 */ 1994 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, 1995 struct sk_buff *skb) 1996 { 1997 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 1998 unsigned char *va; 1999 unsigned int pull_len; 2000 2001 /* 2002 * it is valid to use page_address instead of kmap since we are 2003 * working with pages allocated out of the lomem pool per 2004 * alloc_page(GFP_ATOMIC) 2005 */ 2006 va = skb_frag_address(frag); 2007 2008 /* 2009 * we need the header to contain the greater of either ETH_HLEN or 2010 * 60 bytes if the skb->len is less than 60 for skb_pad. 2011 */ 2012 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE); 2013 2014 /* align pull length to size of long to optimize memcpy performance */ 2015 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 2016 2017 /* update all of the pointers */ 2018 skb_frag_size_sub(frag, pull_len); 2019 skb_frag_off_add(frag, pull_len); 2020 skb->data_len -= pull_len; 2021 skb->tail += pull_len; 2022 } 2023 2024 /** 2025 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB 2026 * @rx_ring: rx descriptor ring packet is being transacted on 2027 * @skb: pointer to current skb being updated 2028 * 2029 * This function provides a basic DMA sync up for the first fragment of an 2030 * skb. The reason for doing this is that the first fragment cannot be 2031 * unmapped until we have reached the end of packet descriptor for a buffer 2032 * chain. 2033 */ 2034 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, 2035 struct sk_buff *skb) 2036 { 2037 if (ring_uses_build_skb(rx_ring)) { 2038 unsigned long mask = (unsigned long)ixgbe_rx_pg_size(rx_ring) - 1; 2039 unsigned long offset = (unsigned long)(skb->data) & mask; 2040 2041 dma_sync_single_range_for_cpu(rx_ring->dev, 2042 IXGBE_CB(skb)->dma, 2043 offset, 2044 skb_headlen(skb), 2045 DMA_FROM_DEVICE); 2046 } else { 2047 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 2048 2049 dma_sync_single_range_for_cpu(rx_ring->dev, 2050 IXGBE_CB(skb)->dma, 2051 skb_frag_off(frag), 2052 skb_frag_size(frag), 2053 DMA_FROM_DEVICE); 2054 } 2055 2056 /* If the page was released, just unmap it. */ 2057 if (unlikely(IXGBE_CB(skb)->page_released)) { 2058 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma, 2059 ixgbe_rx_pg_size(rx_ring), 2060 DMA_FROM_DEVICE, 2061 IXGBE_RX_DMA_ATTR); 2062 } 2063 } 2064 2065 /** 2066 * ixgbe_cleanup_headers - Correct corrupted or empty headers 2067 * @rx_ring: rx descriptor ring packet is being transacted on 2068 * @rx_desc: pointer to the EOP Rx descriptor 2069 * @skb: pointer to current skb being fixed 2070 * 2071 * Check if the skb is valid in the XDP case it will be an error pointer. 2072 * Return true in this case to abort processing and advance to next 2073 * descriptor. 2074 * 2075 * Check for corrupted packet headers caused by senders on the local L2 2076 * embedded NIC switch not setting up their Tx Descriptors right. These 2077 * should be very rare. 2078 * 2079 * Also address the case where we are pulling data in on pages only 2080 * and as such no data is present in the skb header. 2081 * 2082 * In addition if skb is not at least 60 bytes we need to pad it so that 2083 * it is large enough to qualify as a valid Ethernet frame. 2084 * 2085 * Returns true if an error was encountered and skb was freed. 2086 **/ 2087 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, 2088 union ixgbe_adv_rx_desc *rx_desc, 2089 struct sk_buff *skb) 2090 { 2091 struct net_device *netdev = rx_ring->netdev; 2092 2093 /* Verify netdev is present, and that packet does not have any 2094 * errors that would be unacceptable to the netdev. 2095 */ 2096 if (!netdev || 2097 (unlikely(ixgbe_test_staterr(rx_desc, 2098 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && 2099 !(netdev->features & NETIF_F_RXALL)))) { 2100 dev_kfree_skb_any(skb); 2101 return true; 2102 } 2103 2104 /* place header in linear portion of buffer */ 2105 if (!skb_headlen(skb)) 2106 ixgbe_pull_tail(rx_ring, skb); 2107 2108 #ifdef IXGBE_FCOE 2109 /* do not attempt to pad FCoE Frames as this will disrupt DDP */ 2110 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) 2111 return false; 2112 2113 #endif 2114 /* if eth_skb_pad returns an error the skb was freed */ 2115 if (eth_skb_pad(skb)) 2116 return true; 2117 2118 return false; 2119 } 2120 2121 /** 2122 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring 2123 * @rx_ring: rx descriptor ring to store buffers on 2124 * @old_buff: donor buffer to have page reused 2125 * 2126 * Synchronizes page for reuse by the adapter 2127 **/ 2128 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, 2129 struct ixgbe_rx_buffer *old_buff) 2130 { 2131 struct ixgbe_rx_buffer *new_buff; 2132 u16 nta = rx_ring->next_to_alloc; 2133 2134 new_buff = &rx_ring->rx_buffer_info[nta]; 2135 2136 /* update, and store next to alloc */ 2137 nta++; 2138 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 2139 2140 /* Transfer page from old buffer to new buffer. 2141 * Move each member individually to avoid possible store 2142 * forwarding stalls and unnecessary copy of skb. 2143 */ 2144 new_buff->dma = old_buff->dma; 2145 new_buff->page = old_buff->page; 2146 new_buff->page_offset = old_buff->page_offset; 2147 new_buff->pagecnt_bias = old_buff->pagecnt_bias; 2148 } 2149 2150 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer, 2151 int rx_buffer_pgcnt) 2152 { 2153 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; 2154 struct page *page = rx_buffer->page; 2155 2156 /* avoid re-using remote and pfmemalloc pages */ 2157 if (!dev_page_is_reusable(page)) 2158 return false; 2159 2160 #if (PAGE_SIZE < 8192) 2161 /* if we are only owner of page we can reuse it */ 2162 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1)) 2163 return false; 2164 #else 2165 /* The last offset is a bit aggressive in that we assume the 2166 * worst case of FCoE being enabled and using a 3K buffer. 2167 * However this should have minimal impact as the 1K extra is 2168 * still less than one buffer in size. 2169 */ 2170 #define IXGBE_LAST_OFFSET \ 2171 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K) 2172 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET) 2173 return false; 2174 #endif 2175 2176 /* If we have drained the page fragment pool we need to update 2177 * the pagecnt_bias and page count so that we fully restock the 2178 * number of references the driver holds. 2179 */ 2180 if (unlikely(pagecnt_bias == 1)) { 2181 page_ref_add(page, USHRT_MAX - 1); 2182 rx_buffer->pagecnt_bias = USHRT_MAX; 2183 } 2184 2185 return true; 2186 } 2187 2188 /** 2189 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff 2190 * @rx_ring: rx descriptor ring to transact packets on 2191 * @rx_buffer: buffer containing page to add 2192 * @skb: sk_buff to place the data into 2193 * @size: size of data in rx_buffer 2194 * 2195 * This function will add the data contained in rx_buffer->page to the skb. 2196 * This is done either through a direct copy if the data in the buffer is 2197 * less than the skb header size, otherwise it will just attach the page as 2198 * a frag to the skb. 2199 * 2200 * The function will then update the page offset if necessary and return 2201 * true if the buffer can be reused by the adapter. 2202 **/ 2203 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, 2204 struct ixgbe_rx_buffer *rx_buffer, 2205 struct sk_buff *skb, 2206 unsigned int size) 2207 { 2208 #if (PAGE_SIZE < 8192) 2209 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2210 #else 2211 unsigned int truesize = rx_ring->rx_offset ? 2212 SKB_DATA_ALIGN(rx_ring->rx_offset + size) : 2213 SKB_DATA_ALIGN(size); 2214 #endif 2215 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 2216 rx_buffer->page_offset, size, truesize); 2217 #if (PAGE_SIZE < 8192) 2218 rx_buffer->page_offset ^= truesize; 2219 #else 2220 rx_buffer->page_offset += truesize; 2221 #endif 2222 } 2223 2224 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring, 2225 union ixgbe_adv_rx_desc *rx_desc, 2226 struct sk_buff **skb, 2227 const unsigned int size, 2228 int *rx_buffer_pgcnt) 2229 { 2230 struct ixgbe_rx_buffer *rx_buffer; 2231 2232 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 2233 *rx_buffer_pgcnt = 2234 #if (PAGE_SIZE < 8192) 2235 page_count(rx_buffer->page); 2236 #else 2237 0; 2238 #endif 2239 prefetchw(rx_buffer->page); 2240 *skb = rx_buffer->skb; 2241 2242 /* Delay unmapping of the first packet. It carries the header 2243 * information, HW may still access the header after the writeback. 2244 * Only unmap it when EOP is reached 2245 */ 2246 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) { 2247 if (!*skb) 2248 goto skip_sync; 2249 } else { 2250 if (*skb) 2251 ixgbe_dma_sync_frag(rx_ring, *skb); 2252 } 2253 2254 /* we are reusing so sync this buffer for CPU use */ 2255 dma_sync_single_range_for_cpu(rx_ring->dev, 2256 rx_buffer->dma, 2257 rx_buffer->page_offset, 2258 size, 2259 DMA_FROM_DEVICE); 2260 skip_sync: 2261 rx_buffer->pagecnt_bias--; 2262 2263 return rx_buffer; 2264 } 2265 2266 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring, 2267 struct ixgbe_rx_buffer *rx_buffer, 2268 struct sk_buff *skb, 2269 int rx_buffer_pgcnt) 2270 { 2271 if (ixgbe_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) { 2272 /* hand second half of page back to the ring */ 2273 ixgbe_reuse_rx_page(rx_ring, rx_buffer); 2274 } else { 2275 if (skb && IXGBE_CB(skb)->dma == rx_buffer->dma) { 2276 /* the page has been released from the ring */ 2277 IXGBE_CB(skb)->page_released = true; 2278 } else { 2279 /* we are not reusing the buffer so unmap it */ 2280 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 2281 ixgbe_rx_pg_size(rx_ring), 2282 DMA_FROM_DEVICE, 2283 IXGBE_RX_DMA_ATTR); 2284 } 2285 __page_frag_cache_drain(rx_buffer->page, 2286 rx_buffer->pagecnt_bias); 2287 } 2288 2289 /* clear contents of rx_buffer */ 2290 rx_buffer->page = NULL; 2291 rx_buffer->skb = NULL; 2292 } 2293 2294 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring, 2295 struct ixgbe_rx_buffer *rx_buffer, 2296 struct xdp_buff *xdp, 2297 union ixgbe_adv_rx_desc *rx_desc) 2298 { 2299 unsigned int size = xdp->data_end - xdp->data; 2300 #if (PAGE_SIZE < 8192) 2301 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2302 #else 2303 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end - 2304 xdp->data_hard_start); 2305 #endif 2306 struct sk_buff *skb; 2307 2308 /* prefetch first cache line of first page */ 2309 net_prefetch(xdp->data); 2310 2311 /* Note, we get here by enabling legacy-rx via: 2312 * 2313 * ethtool --set-priv-flags <dev> legacy-rx on 2314 * 2315 * In this mode, we currently get 0 extra XDP headroom as 2316 * opposed to having legacy-rx off, where we process XDP 2317 * packets going to stack via ixgbe_build_skb(). The latter 2318 * provides us currently with 192 bytes of headroom. 2319 * 2320 * For ixgbe_construct_skb() mode it means that the 2321 * xdp->data_meta will always point to xdp->data, since 2322 * the helper cannot expand the head. Should this ever 2323 * change in future for legacy-rx mode on, then lets also 2324 * add xdp->data_meta handling here. 2325 */ 2326 2327 /* allocate a skb to store the frags */ 2328 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE); 2329 if (unlikely(!skb)) 2330 return NULL; 2331 2332 if (size > IXGBE_RX_HDR_SIZE) { 2333 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2334 IXGBE_CB(skb)->dma = rx_buffer->dma; 2335 2336 skb_add_rx_frag(skb, 0, rx_buffer->page, 2337 xdp->data - page_address(rx_buffer->page), 2338 size, truesize); 2339 #if (PAGE_SIZE < 8192) 2340 rx_buffer->page_offset ^= truesize; 2341 #else 2342 rx_buffer->page_offset += truesize; 2343 #endif 2344 } else { 2345 memcpy(__skb_put(skb, size), 2346 xdp->data, ALIGN(size, sizeof(long))); 2347 rx_buffer->pagecnt_bias++; 2348 } 2349 2350 return skb; 2351 } 2352 2353 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring, 2354 struct ixgbe_rx_buffer *rx_buffer, 2355 struct xdp_buff *xdp, 2356 union ixgbe_adv_rx_desc *rx_desc) 2357 { 2358 unsigned int metasize = xdp->data - xdp->data_meta; 2359 #if (PAGE_SIZE < 8192) 2360 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2; 2361 #else 2362 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 2363 SKB_DATA_ALIGN(xdp->data_end - 2364 xdp->data_hard_start); 2365 #endif 2366 struct sk_buff *skb; 2367 2368 /* Prefetch first cache line of first page. If xdp->data_meta 2369 * is unused, this points exactly as xdp->data, otherwise we 2370 * likely have a consumer accessing first few bytes of meta 2371 * data, and then actual data. 2372 */ 2373 net_prefetch(xdp->data_meta); 2374 2375 /* build an skb to around the page buffer */ 2376 skb = napi_build_skb(xdp->data_hard_start, truesize); 2377 if (unlikely(!skb)) 2378 return NULL; 2379 2380 /* update pointers within the skb to store the data */ 2381 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2382 __skb_put(skb, xdp->data_end - xdp->data); 2383 if (metasize) 2384 skb_metadata_set(skb, metasize); 2385 2386 /* record DMA address if this is the start of a chain of buffers */ 2387 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) 2388 IXGBE_CB(skb)->dma = rx_buffer->dma; 2389 2390 /* update buffer offset */ 2391 #if (PAGE_SIZE < 8192) 2392 rx_buffer->page_offset ^= truesize; 2393 #else 2394 rx_buffer->page_offset += truesize; 2395 #endif 2396 2397 return skb; 2398 } 2399 2400 static int ixgbe_run_xdp(struct ixgbe_adapter *adapter, 2401 struct ixgbe_ring *rx_ring, 2402 struct xdp_buff *xdp) 2403 { 2404 int err, result = IXGBE_XDP_PASS; 2405 struct bpf_prog *xdp_prog; 2406 struct ixgbe_ring *ring; 2407 struct xdp_frame *xdpf; 2408 u32 act; 2409 2410 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 2411 2412 if (!xdp_prog) 2413 goto xdp_out; 2414 2415 prefetchw(xdp->data_hard_start); /* xdp_frame write */ 2416 2417 act = bpf_prog_run_xdp(xdp_prog, xdp); 2418 switch (act) { 2419 case XDP_PASS: 2420 break; 2421 case XDP_TX: 2422 xdpf = xdp_convert_buff_to_frame(xdp); 2423 if (unlikely(!xdpf)) 2424 goto out_failure; 2425 ring = ixgbe_determine_xdp_ring(adapter); 2426 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 2427 spin_lock(&ring->tx_lock); 2428 result = ixgbe_xmit_xdp_ring(ring, xdpf); 2429 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 2430 spin_unlock(&ring->tx_lock); 2431 if (result == IXGBE_XDP_CONSUMED) 2432 goto out_failure; 2433 break; 2434 case XDP_REDIRECT: 2435 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog); 2436 if (err) 2437 goto out_failure; 2438 result = IXGBE_XDP_REDIR; 2439 break; 2440 default: 2441 bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act); 2442 fallthrough; 2443 case XDP_ABORTED: 2444 out_failure: 2445 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 2446 fallthrough; /* handle aborts by dropping packet */ 2447 case XDP_DROP: 2448 result = IXGBE_XDP_CONSUMED; 2449 break; 2450 } 2451 xdp_out: 2452 return result; 2453 } 2454 2455 static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring, 2456 unsigned int size) 2457 { 2458 unsigned int truesize; 2459 2460 #if (PAGE_SIZE < 8192) 2461 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 2462 #else 2463 truesize = rx_ring->rx_offset ? 2464 SKB_DATA_ALIGN(rx_ring->rx_offset + size) + 2465 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 2466 SKB_DATA_ALIGN(size); 2467 #endif 2468 return truesize; 2469 } 2470 2471 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring, 2472 struct ixgbe_rx_buffer *rx_buffer, 2473 unsigned int size) 2474 { 2475 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size); 2476 #if (PAGE_SIZE < 8192) 2477 rx_buffer->page_offset ^= truesize; 2478 #else 2479 rx_buffer->page_offset += truesize; 2480 #endif 2481 } 2482 2483 /** 2484 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 2485 * @q_vector: structure containing interrupt and ring information 2486 * @rx_ring: rx descriptor ring to transact packets on 2487 * @budget: Total limit on number of packets to process 2488 * 2489 * This function provides a "bounce buffer" approach to Rx interrupt 2490 * processing. The advantage to this is that on systems that have 2491 * expensive overhead for IOMMU access this provides a means of avoiding 2492 * it by maintaining the mapping of the page to the system. 2493 * 2494 * Returns amount of work completed 2495 **/ 2496 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, 2497 struct ixgbe_ring *rx_ring, 2498 const int budget) 2499 { 2500 unsigned int total_rx_bytes = 0, total_rx_packets = 0, frame_sz = 0; 2501 struct ixgbe_adapter *adapter = q_vector->adapter; 2502 #ifdef IXGBE_FCOE 2503 int ddp_bytes; 2504 unsigned int mss = 0; 2505 #endif /* IXGBE_FCOE */ 2506 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 2507 unsigned int offset = rx_ring->rx_offset; 2508 unsigned int xdp_xmit = 0; 2509 struct xdp_buff xdp; 2510 int xdp_res = 0; 2511 2512 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 2513 #if (PAGE_SIZE < 8192) 2514 frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0); 2515 #endif 2516 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 2517 2518 while (likely(total_rx_packets < budget)) { 2519 union ixgbe_adv_rx_desc *rx_desc; 2520 struct ixgbe_rx_buffer *rx_buffer; 2521 struct sk_buff *skb; 2522 int rx_buffer_pgcnt; 2523 unsigned int size; 2524 2525 /* return some buffers to hardware, one at a time is too slow */ 2526 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 2527 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); 2528 cleaned_count = 0; 2529 } 2530 2531 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 2532 size = le16_to_cpu(rx_desc->wb.upper.length); 2533 if (!size) 2534 break; 2535 2536 /* This memory barrier is needed to keep us from reading 2537 * any other fields out of the rx_desc until we know the 2538 * descriptor has been written back 2539 */ 2540 dma_rmb(); 2541 2542 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size, &rx_buffer_pgcnt); 2543 2544 /* retrieve a buffer from the ring */ 2545 if (!skb) { 2546 unsigned char *hard_start; 2547 2548 hard_start = page_address(rx_buffer->page) + 2549 rx_buffer->page_offset - offset; 2550 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 2551 xdp_buff_clear_frags_flag(&xdp); 2552 #if (PAGE_SIZE > 4096) 2553 /* At larger PAGE_SIZE, frame_sz depend on len size */ 2554 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size); 2555 #endif 2556 xdp_res = ixgbe_run_xdp(adapter, rx_ring, &xdp); 2557 } 2558 2559 if (xdp_res) { 2560 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) { 2561 xdp_xmit |= xdp_res; 2562 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size); 2563 } else { 2564 rx_buffer->pagecnt_bias++; 2565 } 2566 total_rx_packets++; 2567 total_rx_bytes += size; 2568 } else if (skb) { 2569 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size); 2570 } else if (ring_uses_build_skb(rx_ring)) { 2571 skb = ixgbe_build_skb(rx_ring, rx_buffer, 2572 &xdp, rx_desc); 2573 } else { 2574 skb = ixgbe_construct_skb(rx_ring, rx_buffer, 2575 &xdp, rx_desc); 2576 } 2577 2578 /* exit if we failed to retrieve a buffer */ 2579 if (!xdp_res && !skb) { 2580 rx_ring->rx_stats.alloc_rx_buff_failed++; 2581 rx_buffer->pagecnt_bias++; 2582 break; 2583 } 2584 2585 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 2586 cleaned_count++; 2587 2588 /* place incomplete frames back on ring for completion */ 2589 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) 2590 continue; 2591 2592 /* verify the packet layout is correct */ 2593 if (xdp_res || ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) 2594 continue; 2595 2596 /* probably a little skewed due to removing CRC */ 2597 total_rx_bytes += skb->len; 2598 2599 /* populate checksum, timestamp, VLAN, and protocol */ 2600 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 2601 2602 #ifdef IXGBE_FCOE 2603 /* if ddp, not passing to ULD unless for FCP_RSP or error */ 2604 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { 2605 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); 2606 /* include DDPed FCoE data */ 2607 if (ddp_bytes > 0) { 2608 if (!mss) { 2609 mss = rx_ring->netdev->mtu - 2610 sizeof(struct fcoe_hdr) - 2611 sizeof(struct fc_frame_header) - 2612 sizeof(struct fcoe_crc_eof); 2613 if (mss > 512) 2614 mss &= ~511; 2615 } 2616 total_rx_bytes += ddp_bytes; 2617 total_rx_packets += DIV_ROUND_UP(ddp_bytes, 2618 mss); 2619 } 2620 if (!ddp_bytes) { 2621 dev_kfree_skb_any(skb); 2622 continue; 2623 } 2624 } 2625 2626 #endif /* IXGBE_FCOE */ 2627 ixgbe_rx_skb(q_vector, skb); 2628 2629 /* update budget accounting */ 2630 total_rx_packets++; 2631 } 2632 2633 if (xdp_xmit & IXGBE_XDP_REDIR) 2634 xdp_do_flush(); 2635 2636 if (xdp_xmit & IXGBE_XDP_TX) { 2637 struct ixgbe_ring *ring = ixgbe_determine_xdp_ring(adapter); 2638 2639 ixgbe_xdp_ring_update_tail_locked(ring); 2640 } 2641 2642 ixgbe_update_rx_ring_stats(rx_ring, q_vector, total_rx_packets, 2643 total_rx_bytes); 2644 2645 return total_rx_packets; 2646 } 2647 2648 /** 2649 * ixgbe_configure_msix - Configure MSI-X hardware 2650 * @adapter: board private structure 2651 * 2652 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X 2653 * interrupts. 2654 **/ 2655 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) 2656 { 2657 struct ixgbe_q_vector *q_vector; 2658 int v_idx; 2659 u32 mask; 2660 2661 /* Populate MSIX to EITR Select */ 2662 if (adapter->num_vfs > 32) { 2663 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; 2664 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); 2665 } 2666 2667 /* 2668 * Populate the IVAR table and set the ITR values to the 2669 * corresponding register. 2670 */ 2671 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 2672 struct ixgbe_ring *ring; 2673 q_vector = adapter->q_vector[v_idx]; 2674 2675 ixgbe_for_each_ring(ring, q_vector->rx) 2676 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); 2677 2678 ixgbe_for_each_ring(ring, q_vector->tx) 2679 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); 2680 2681 ixgbe_write_eitr(q_vector); 2682 } 2683 2684 switch (adapter->hw.mac.type) { 2685 case ixgbe_mac_82598EB: 2686 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, 2687 v_idx); 2688 break; 2689 case ixgbe_mac_82599EB: 2690 case ixgbe_mac_X540: 2691 case ixgbe_mac_X550: 2692 case ixgbe_mac_X550EM_x: 2693 case ixgbe_mac_x550em_a: 2694 case ixgbe_mac_e610: 2695 ixgbe_set_ivar(adapter, -1, 1, v_idx); 2696 break; 2697 default: 2698 break; 2699 } 2700 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); 2701 2702 /* set up to autoclear timer, and the vectors */ 2703 mask = IXGBE_EIMS_ENABLE_MASK; 2704 mask &= ~(IXGBE_EIMS_OTHER | 2705 IXGBE_EIMS_MAILBOX | 2706 IXGBE_EIMS_LSC); 2707 2708 if (adapter->hw.mac.type == ixgbe_mac_e610) 2709 mask &= ~IXGBE_EIMS_FW_EVENT; 2710 2711 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); 2712 } 2713 2714 /** 2715 * ixgbe_update_itr - update the dynamic ITR value based on statistics 2716 * @q_vector: structure containing interrupt and ring information 2717 * @ring_container: structure containing ring performance data 2718 * 2719 * Stores a new ITR value based on packets and byte 2720 * counts during the last interrupt. The advantage of per interrupt 2721 * computation is faster updates and more accurate ITR for the current 2722 * traffic pattern. Constants in this function were computed 2723 * based on theoretical maximum wire speed and thresholds were set based 2724 * on testing data as well as attempting to minimize response time 2725 * while increasing bulk throughput. 2726 **/ 2727 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, 2728 struct ixgbe_ring_container *ring_container) 2729 { 2730 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS | 2731 IXGBE_ITR_ADAPTIVE_LATENCY; 2732 unsigned int avg_wire_size, packets, bytes; 2733 unsigned long next_update = jiffies; 2734 2735 /* If we don't have any rings just leave ourselves set for maximum 2736 * possible latency so we take ourselves out of the equation. 2737 */ 2738 if (!ring_container->ring) 2739 return; 2740 2741 /* If we didn't update within up to 1 - 2 jiffies we can assume 2742 * that either packets are coming in so slow there hasn't been 2743 * any work, or that there is so much work that NAPI is dealing 2744 * with interrupt moderation and we don't need to do anything. 2745 */ 2746 if (time_after(next_update, ring_container->next_update)) 2747 goto clear_counts; 2748 2749 packets = ring_container->total_packets; 2750 2751 /* We have no packets to actually measure against. This means 2752 * either one of the other queues on this vector is active or 2753 * we are a Tx queue doing TSO with too high of an interrupt rate. 2754 * 2755 * When this occurs just tick up our delay by the minimum value 2756 * and hope that this extra delay will prevent us from being called 2757 * without any work on our queue. 2758 */ 2759 if (!packets) { 2760 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2761 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2762 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2763 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY; 2764 goto clear_counts; 2765 } 2766 2767 bytes = ring_container->total_bytes; 2768 2769 /* If packets are less than 4 or bytes are less than 9000 assume 2770 * insufficient data to use bulk rate limiting approach. We are 2771 * likely latency driven. 2772 */ 2773 if (packets < 4 && bytes < 9000) { 2774 itr = IXGBE_ITR_ADAPTIVE_LATENCY; 2775 goto adjust_by_size; 2776 } 2777 2778 /* Between 4 and 48 we can assume that our current interrupt delay 2779 * is only slightly too low. As such we should increase it by a small 2780 * fixed amount. 2781 */ 2782 if (packets < 48) { 2783 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC; 2784 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS) 2785 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS; 2786 goto clear_counts; 2787 } 2788 2789 /* Between 48 and 96 is our "goldilocks" zone where we are working 2790 * out "just right". Just report that our current ITR is good for us. 2791 */ 2792 if (packets < 96) { 2793 itr = q_vector->itr >> 2; 2794 goto clear_counts; 2795 } 2796 2797 /* If packet count is 96 or greater we are likely looking at a slight 2798 * overrun of the delay we want. Try halving our delay to see if that 2799 * will cut the number of packets in half per interrupt. 2800 */ 2801 if (packets < 256) { 2802 itr = q_vector->itr >> 3; 2803 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS) 2804 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS; 2805 goto clear_counts; 2806 } 2807 2808 /* The paths below assume we are dealing with a bulk ITR since number 2809 * of packets is 256 or greater. We are just going to have to compute 2810 * a value and try to bring the count under control, though for smaller 2811 * packet sizes there isn't much we can do as NAPI polling will likely 2812 * be kicking in sooner rather than later. 2813 */ 2814 itr = IXGBE_ITR_ADAPTIVE_BULK; 2815 2816 adjust_by_size: 2817 /* If packet counts are 256 or greater we can assume we have a gross 2818 * overestimation of what the rate should be. Instead of trying to fine 2819 * tune it just use the formula below to try and dial in an exact value 2820 * give the current packet size of the frame. 2821 */ 2822 avg_wire_size = bytes / packets; 2823 2824 /* The following is a crude approximation of: 2825 * wmem_default / (size + overhead) = desired_pkts_per_int 2826 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate 2827 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value 2828 * 2829 * Assuming wmem_default is 212992 and overhead is 640 bytes per 2830 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the 2831 * formula down to 2832 * 2833 * (170 * (size + 24)) / (size + 640) = ITR 2834 * 2835 * We first do some math on the packet size and then finally bitshift 2836 * by 8 after rounding up. We also have to account for PCIe link speed 2837 * difference as ITR scales based on this. 2838 */ 2839 if (avg_wire_size <= 60) { 2840 /* Start at 50k ints/sec */ 2841 avg_wire_size = 5120; 2842 } else if (avg_wire_size <= 316) { 2843 /* 50K ints/sec to 16K ints/sec */ 2844 avg_wire_size *= 40; 2845 avg_wire_size += 2720; 2846 } else if (avg_wire_size <= 1084) { 2847 /* 16K ints/sec to 9.2K ints/sec */ 2848 avg_wire_size *= 15; 2849 avg_wire_size += 11452; 2850 } else if (avg_wire_size < 1968) { 2851 /* 9.2K ints/sec to 8K ints/sec */ 2852 avg_wire_size *= 5; 2853 avg_wire_size += 22420; 2854 } else { 2855 /* plateau at a limit of 8K ints/sec */ 2856 avg_wire_size = 32256; 2857 } 2858 2859 /* If we are in low latency mode half our delay which doubles the rate 2860 * to somewhere between 100K to 16K ints/sec 2861 */ 2862 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY) 2863 avg_wire_size >>= 1; 2864 2865 /* Resultant value is 256 times larger than it needs to be. This 2866 * gives us room to adjust the value as needed to either increase 2867 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc. 2868 * 2869 * Use addition as we have already recorded the new latency flag 2870 * for the ITR value. 2871 */ 2872 switch (q_vector->adapter->link_speed) { 2873 case IXGBE_LINK_SPEED_10GB_FULL: 2874 case IXGBE_LINK_SPEED_100_FULL: 2875 default: 2876 itr += DIV_ROUND_UP(avg_wire_size, 2877 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) * 2878 IXGBE_ITR_ADAPTIVE_MIN_INC; 2879 break; 2880 case IXGBE_LINK_SPEED_2_5GB_FULL: 2881 case IXGBE_LINK_SPEED_1GB_FULL: 2882 case IXGBE_LINK_SPEED_10_FULL: 2883 if (avg_wire_size > 8064) 2884 avg_wire_size = 8064; 2885 itr += DIV_ROUND_UP(avg_wire_size, 2886 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) * 2887 IXGBE_ITR_ADAPTIVE_MIN_INC; 2888 break; 2889 } 2890 2891 clear_counts: 2892 /* write back value */ 2893 ring_container->itr = itr; 2894 2895 /* next update should occur within next jiffy */ 2896 ring_container->next_update = next_update + 1; 2897 2898 ring_container->total_bytes = 0; 2899 ring_container->total_packets = 0; 2900 } 2901 2902 /** 2903 * ixgbe_write_eitr - write EITR register in hardware specific way 2904 * @q_vector: structure containing interrupt and ring information 2905 * 2906 * This function is made to be called by ethtool and by the driver 2907 * when it needs to update EITR registers at runtime. Hardware 2908 * specific quirks/differences are taken care of here. 2909 */ 2910 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) 2911 { 2912 struct ixgbe_adapter *adapter = q_vector->adapter; 2913 struct ixgbe_hw *hw = &adapter->hw; 2914 int v_idx = q_vector->v_idx; 2915 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; 2916 2917 switch (adapter->hw.mac.type) { 2918 case ixgbe_mac_82598EB: 2919 /* must write high and low 16 bits to reset counter */ 2920 itr_reg |= (itr_reg << 16); 2921 break; 2922 case ixgbe_mac_82599EB: 2923 case ixgbe_mac_X540: 2924 case ixgbe_mac_X550: 2925 case ixgbe_mac_X550EM_x: 2926 case ixgbe_mac_x550em_a: 2927 case ixgbe_mac_e610: 2928 /* 2929 * set the WDIS bit to not clear the timer bits and cause an 2930 * immediate assertion of the interrupt 2931 */ 2932 itr_reg |= IXGBE_EITR_CNT_WDIS; 2933 break; 2934 default: 2935 break; 2936 } 2937 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); 2938 } 2939 2940 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) 2941 { 2942 u32 new_itr; 2943 2944 ixgbe_update_itr(q_vector, &q_vector->tx); 2945 ixgbe_update_itr(q_vector, &q_vector->rx); 2946 2947 /* use the smallest value of new ITR delay calculations */ 2948 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 2949 2950 /* Clear latency flag if set, shift into correct position */ 2951 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY; 2952 new_itr <<= 2; 2953 2954 if (new_itr != q_vector->itr) { 2955 /* save the algorithm value here */ 2956 q_vector->itr = new_itr; 2957 2958 ixgbe_write_eitr(q_vector); 2959 } 2960 } 2961 2962 /** 2963 * ixgbe_check_overtemp_subtask - check for over temperature 2964 * @adapter: pointer to adapter 2965 **/ 2966 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) 2967 { 2968 struct ixgbe_hw *hw = &adapter->hw; 2969 u32 eicr = adapter->interrupt_event; 2970 2971 if (test_bit(__IXGBE_DOWN, &adapter->state)) 2972 return; 2973 2974 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) 2975 return; 2976 2977 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; 2978 2979 switch (hw->device_id) { 2980 case IXGBE_DEV_ID_82599_T3_LOM: 2981 /* 2982 * Since the warning interrupt is for both ports 2983 * we don't have to check if: 2984 * - This interrupt wasn't for our port. 2985 * - We may have missed the interrupt so always have to 2986 * check if we got a LSC 2987 */ 2988 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && 2989 !(eicr & IXGBE_EICR_LSC)) 2990 return; 2991 2992 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { 2993 u32 speed; 2994 bool link_up = false; 2995 2996 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2997 2998 if (link_up) 2999 return; 3000 } 3001 3002 /* Check if this is not due to overtemp */ 3003 if (!hw->phy.ops.check_overtemp(hw)) 3004 return; 3005 3006 break; 3007 case IXGBE_DEV_ID_X550EM_A_1G_T: 3008 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3009 if (!hw->phy.ops.check_overtemp(hw)) 3010 return; 3011 break; 3012 default: 3013 if (adapter->hw.mac.type >= ixgbe_mac_X540) 3014 return; 3015 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) 3016 return; 3017 break; 3018 } 3019 e_crit(drv, "%s\n", ixgbe_overheat_msg); 3020 3021 adapter->interrupt_event = 0; 3022 } 3023 3024 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) 3025 { 3026 struct ixgbe_hw *hw = &adapter->hw; 3027 3028 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && 3029 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 3030 e_crit(probe, "Fan has stopped, replace the adapter\n"); 3031 /* write to clear the interrupt */ 3032 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 3033 } 3034 } 3035 3036 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) 3037 { 3038 struct ixgbe_hw *hw = &adapter->hw; 3039 3040 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) 3041 return; 3042 3043 switch (adapter->hw.mac.type) { 3044 case ixgbe_mac_82599EB: 3045 /* 3046 * Need to check link state so complete overtemp check 3047 * on service task 3048 */ 3049 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || 3050 (eicr & IXGBE_EICR_LSC)) && 3051 (!test_bit(__IXGBE_DOWN, &adapter->state))) { 3052 adapter->interrupt_event = eicr; 3053 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 3054 ixgbe_service_event_schedule(adapter); 3055 return; 3056 } 3057 return; 3058 case ixgbe_mac_x550em_a: 3059 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) { 3060 adapter->interrupt_event = eicr; 3061 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; 3062 ixgbe_service_event_schedule(adapter); 3063 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 3064 IXGBE_EICR_GPI_SDP0_X550EM_a); 3065 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR, 3066 IXGBE_EICR_GPI_SDP0_X550EM_a); 3067 } 3068 return; 3069 case ixgbe_mac_X550: 3070 case ixgbe_mac_X540: 3071 if (!(eicr & IXGBE_EICR_TS)) 3072 return; 3073 break; 3074 default: 3075 return; 3076 } 3077 3078 e_crit(drv, "%s\n", ixgbe_overheat_msg); 3079 } 3080 3081 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) 3082 { 3083 switch (hw->mac.type) { 3084 case ixgbe_mac_82598EB: 3085 if (hw->phy.type == ixgbe_phy_nl) 3086 return true; 3087 return false; 3088 case ixgbe_mac_82599EB: 3089 case ixgbe_mac_X550EM_x: 3090 case ixgbe_mac_x550em_a: 3091 switch (hw->mac.ops.get_media_type(hw)) { 3092 case ixgbe_media_type_fiber: 3093 case ixgbe_media_type_fiber_qsfp: 3094 return true; 3095 default: 3096 return false; 3097 } 3098 default: 3099 return false; 3100 } 3101 } 3102 3103 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) 3104 { 3105 struct ixgbe_hw *hw = &adapter->hw; 3106 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); 3107 3108 if (!ixgbe_is_sfp(hw)) 3109 return; 3110 3111 /* Later MAC's use different SDP */ 3112 if (hw->mac.type >= ixgbe_mac_X540) 3113 eicr_mask = IXGBE_EICR_GPI_SDP0_X540; 3114 3115 if (eicr & eicr_mask) { 3116 /* Clear the interrupt */ 3117 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); 3118 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 3119 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 3120 adapter->sfp_poll_time = 0; 3121 ixgbe_service_event_schedule(adapter); 3122 } 3123 } 3124 3125 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 3126 (eicr & IXGBE_EICR_GPI_SDP1(hw))) { 3127 /* Clear the interrupt */ 3128 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); 3129 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 3130 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 3131 ixgbe_service_event_schedule(adapter); 3132 } 3133 } 3134 } 3135 3136 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) 3137 { 3138 struct ixgbe_hw *hw = &adapter->hw; 3139 3140 adapter->lsc_int++; 3141 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 3142 adapter->link_check_timeout = jiffies; 3143 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 3144 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); 3145 IXGBE_WRITE_FLUSH(hw); 3146 ixgbe_service_event_schedule(adapter); 3147 } 3148 } 3149 3150 /** 3151 * ixgbe_check_phy_fw_load - check if PHY FW load failed 3152 * @adapter: pointer to adapter structure 3153 * @link_cfg_err: bitmap from the link info structure 3154 * 3155 * Check if external PHY FW load failed and print an error message if it did. 3156 */ 3157 static void ixgbe_check_phy_fw_load(struct ixgbe_adapter *adapter, 3158 u8 link_cfg_err) 3159 { 3160 if (!(link_cfg_err & IXGBE_ACI_LINK_EXTERNAL_PHY_LOAD_FAILURE)) { 3161 adapter->flags2 &= ~IXGBE_FLAG2_PHY_FW_LOAD_FAILED; 3162 return; 3163 } 3164 3165 if (adapter->flags2 & IXGBE_FLAG2_PHY_FW_LOAD_FAILED) 3166 return; 3167 3168 if (link_cfg_err & IXGBE_ACI_LINK_EXTERNAL_PHY_LOAD_FAILURE) { 3169 netdev_err(adapter->netdev, "Device failed to load the FW for the external PHY. Please download and install the latest NVM for your device and try again\n"); 3170 adapter->flags2 |= IXGBE_FLAG2_PHY_FW_LOAD_FAILED; 3171 } 3172 } 3173 3174 /** 3175 * ixgbe_check_module_power - check module power level 3176 * @adapter: pointer to adapter structure 3177 * @link_cfg_err: bitmap from the link info structure 3178 * 3179 * Check module power level returned by a previous call to aci_get_link_info 3180 * and print error messages if module power level is not supported. 3181 */ 3182 static void ixgbe_check_module_power(struct ixgbe_adapter *adapter, 3183 u8 link_cfg_err) 3184 { 3185 /* If module power level is supported, clear the flag. */ 3186 if (!(link_cfg_err & (IXGBE_ACI_LINK_INVAL_MAX_POWER_LIMIT | 3187 IXGBE_ACI_LINK_MODULE_POWER_UNSUPPORTED))) { 3188 adapter->flags2 &= ~IXGBE_FLAG2_MOD_POWER_UNSUPPORTED; 3189 return; 3190 } 3191 3192 /* If IXGBE_FLAG2_MOD_POWER_UNSUPPORTED was previously set and the 3193 * above block didn't clear this bit, there's nothing to do. 3194 */ 3195 if (adapter->flags2 & IXGBE_FLAG2_MOD_POWER_UNSUPPORTED) 3196 return; 3197 3198 if (link_cfg_err & IXGBE_ACI_LINK_INVAL_MAX_POWER_LIMIT) { 3199 netdev_err(adapter->netdev, "The installed module is incompatible with the device's NVM image. Cannot start link.\n"); 3200 adapter->flags2 |= IXGBE_FLAG2_MOD_POWER_UNSUPPORTED; 3201 } else if (link_cfg_err & IXGBE_ACI_LINK_MODULE_POWER_UNSUPPORTED) { 3202 netdev_err(adapter->netdev, "The module's power requirements exceed the device's power supply. Cannot start link.\n"); 3203 adapter->flags2 |= IXGBE_FLAG2_MOD_POWER_UNSUPPORTED; 3204 } 3205 } 3206 3207 /** 3208 * ixgbe_check_link_cfg_err - check if link configuration failed 3209 * @adapter: pointer to adapter structure 3210 * @link_cfg_err: bitmap from the link info structure 3211 * 3212 * Print if any link configuration failure happens due to the value in the 3213 * link_cfg_err parameter in the link info structure. 3214 */ 3215 static void ixgbe_check_link_cfg_err(struct ixgbe_adapter *adapter, 3216 u8 link_cfg_err) 3217 { 3218 ixgbe_check_module_power(adapter, link_cfg_err); 3219 ixgbe_check_phy_fw_load(adapter, link_cfg_err); 3220 } 3221 3222 /** 3223 * ixgbe_process_link_status_event - process the link event 3224 * @adapter: pointer to adapter structure 3225 * @link_up: true if the physical link is up and false if it is down 3226 * @link_speed: current link speed received from the link event 3227 * 3228 * Return: 0 on success or negative value on failure. 3229 */ 3230 static int 3231 ixgbe_process_link_status_event(struct ixgbe_adapter *adapter, bool link_up, 3232 u16 link_speed) 3233 { 3234 struct ixgbe_hw *hw = &adapter->hw; 3235 int status; 3236 3237 /* Update the link info structures and re-enable link events, 3238 * don't bail on failure due to other book keeping needed. 3239 */ 3240 status = ixgbe_update_link_info(hw); 3241 if (status) 3242 e_dev_err("Failed to update link status, err %d aq_err %d\n", 3243 status, hw->aci.last_status); 3244 3245 ixgbe_check_link_cfg_err(adapter, hw->link.link_info.link_cfg_err); 3246 3247 /* Check if the link state is up after updating link info, and treat 3248 * this event as an UP event since the link is actually UP now. 3249 */ 3250 if (hw->link.link_info.link_info & IXGBE_ACI_LINK_UP) 3251 link_up = true; 3252 3253 /* Turn off PHY if media was removed. */ 3254 if (!(adapter->flags2 & IXGBE_FLAG2_NO_MEDIA) && 3255 !(hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE)) 3256 adapter->flags2 |= IXGBE_FLAG2_NO_MEDIA; 3257 3258 if (link_up == adapter->link_up && 3259 link_up == netif_carrier_ok(adapter->netdev) && 3260 link_speed == adapter->link_speed) 3261 return 0; 3262 3263 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 3264 adapter->link_check_timeout = jiffies; 3265 ixgbe_watchdog_update_link(adapter); 3266 3267 if (link_up) 3268 ixgbe_watchdog_link_is_up(adapter); 3269 else 3270 ixgbe_watchdog_link_is_down(adapter); 3271 3272 return 0; 3273 } 3274 3275 /** 3276 * ixgbe_handle_link_status_event - handle link status event via ACI 3277 * @adapter: pointer to adapter structure 3278 * @e: event structure containing link status info 3279 */ 3280 static void 3281 ixgbe_handle_link_status_event(struct ixgbe_adapter *adapter, 3282 struct ixgbe_aci_event *e) 3283 { 3284 struct ixgbe_aci_cmd_get_link_status_data *link_data; 3285 u16 link_speed; 3286 bool link_up; 3287 3288 link_data = (struct ixgbe_aci_cmd_get_link_status_data *)e->msg_buf; 3289 3290 link_up = !!(link_data->link_info & IXGBE_ACI_LINK_UP); 3291 link_speed = le16_to_cpu(link_data->link_speed); 3292 3293 if (ixgbe_process_link_status_event(adapter, link_up, link_speed)) 3294 e_dev_warn("Could not process link status event"); 3295 } 3296 3297 /** 3298 * ixgbe_schedule_fw_event - schedule Firmware event 3299 * @adapter: pointer to the adapter structure 3300 * 3301 * If the adapter is not in down, removing or resetting state, 3302 * an event is scheduled. 3303 */ 3304 static void ixgbe_schedule_fw_event(struct ixgbe_adapter *adapter) 3305 { 3306 if (!test_bit(__IXGBE_DOWN, &adapter->state) && 3307 !test_bit(__IXGBE_REMOVING, &adapter->state) && 3308 !test_bit(__IXGBE_RESETTING, &adapter->state)) { 3309 adapter->flags2 |= IXGBE_FLAG2_FW_ASYNC_EVENT; 3310 ixgbe_service_event_schedule(adapter); 3311 } 3312 } 3313 3314 /** 3315 * ixgbe_aci_event_cleanup - release msg_buf memory 3316 * @event: pointer to the event holding msg_buf to be released 3317 * 3318 * Clean memory allocated for event's msg_buf. Implements auto memory cleanup. 3319 */ 3320 static void ixgbe_aci_event_cleanup(struct ixgbe_aci_event *event) 3321 { 3322 kfree(event->msg_buf); 3323 } 3324 3325 /** 3326 * ixgbe_handle_fw_event - handle Firmware event 3327 * @adapter: pointer to the adapter structure 3328 * 3329 * Obtain an event from the ACI and then and then process it according to the 3330 * type of the event and the opcode. 3331 */ 3332 static void ixgbe_handle_fw_event(struct ixgbe_adapter *adapter) 3333 { 3334 struct ixgbe_aci_event event __cleanup(ixgbe_aci_event_cleanup); 3335 struct ixgbe_hw *hw = &adapter->hw; 3336 bool pending = false; 3337 int err; 3338 3339 if (adapter->flags2 & IXGBE_FLAG2_FW_ASYNC_EVENT) 3340 adapter->flags2 &= ~IXGBE_FLAG2_FW_ASYNC_EVENT; 3341 event.buf_len = IXGBE_ACI_MAX_BUFFER_SIZE; 3342 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL); 3343 if (!event.msg_buf) 3344 return; 3345 3346 do { 3347 err = ixgbe_aci_get_event(hw, &event, &pending); 3348 if (err) 3349 break; 3350 3351 switch (le16_to_cpu(event.desc.opcode)) { 3352 case ixgbe_aci_opc_get_link_status: 3353 ixgbe_handle_link_status_event(adapter, &event); 3354 break; 3355 case ixgbe_aci_opc_temp_tca_event: 3356 e_crit(drv, "%s\n", ixgbe_overheat_msg); 3357 ixgbe_down(adapter); 3358 break; 3359 case libie_aqc_opc_fw_logs_event: 3360 libie_get_fwlog_data(&hw->fwlog, event.msg_buf, 3361 le16_to_cpu(event.desc.datalen)); 3362 break; 3363 default: 3364 e_warn(hw, "unknown FW async event captured\n"); 3365 break; 3366 } 3367 } while (pending); 3368 } 3369 3370 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, 3371 u64 qmask) 3372 { 3373 struct ixgbe_hw *hw = &adapter->hw; 3374 u32 mask; 3375 3376 switch (hw->mac.type) { 3377 case ixgbe_mac_82598EB: 3378 mask = (IXGBE_EIMS_RTX_QUEUE & qmask); 3379 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); 3380 break; 3381 case ixgbe_mac_82599EB: 3382 case ixgbe_mac_X540: 3383 case ixgbe_mac_X550: 3384 case ixgbe_mac_X550EM_x: 3385 case ixgbe_mac_x550em_a: 3386 case ixgbe_mac_e610: 3387 mask = (qmask & 0xFFFFFFFF); 3388 if (mask) 3389 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 3390 mask = (qmask >> 32); 3391 if (mask) 3392 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 3393 break; 3394 default: 3395 break; 3396 } 3397 /* skip the flush */ 3398 } 3399 3400 /** 3401 * ixgbe_irq_enable - Enable default interrupt generation settings 3402 * @adapter: board private structure 3403 * @queues: enable irqs for queues 3404 * @flush: flush register write 3405 **/ 3406 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, 3407 bool flush) 3408 { 3409 struct ixgbe_hw *hw = &adapter->hw; 3410 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); 3411 3412 /* don't reenable LSC while waiting for link */ 3413 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 3414 mask &= ~IXGBE_EIMS_LSC; 3415 3416 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) 3417 switch (adapter->hw.mac.type) { 3418 case ixgbe_mac_82599EB: 3419 mask |= IXGBE_EIMS_GPI_SDP0(hw); 3420 break; 3421 case ixgbe_mac_X540: 3422 case ixgbe_mac_X550: 3423 case ixgbe_mac_X550EM_x: 3424 case ixgbe_mac_x550em_a: 3425 mask |= IXGBE_EIMS_TS; 3426 break; 3427 default: 3428 break; 3429 } 3430 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 3431 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3432 switch (adapter->hw.mac.type) { 3433 case ixgbe_mac_82599EB: 3434 mask |= IXGBE_EIMS_GPI_SDP1(hw); 3435 mask |= IXGBE_EIMS_GPI_SDP2(hw); 3436 fallthrough; 3437 case ixgbe_mac_X540: 3438 case ixgbe_mac_X550: 3439 case ixgbe_mac_X550EM_x: 3440 case ixgbe_mac_e610: 3441 mask |= IXGBE_EIMS_FW_EVENT; 3442 fallthrough; 3443 case ixgbe_mac_x550em_a: 3444 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || 3445 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || 3446 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) 3447 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); 3448 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) 3449 mask |= IXGBE_EICR_GPI_SDP0_X540; 3450 mask |= IXGBE_EIMS_ECC; 3451 mask |= IXGBE_EIMS_MAILBOX; 3452 break; 3453 default: 3454 break; 3455 } 3456 3457 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && 3458 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 3459 mask |= IXGBE_EIMS_FLOW_DIR; 3460 3461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); 3462 if (queues) 3463 ixgbe_irq_enable_queues(adapter, ~0); 3464 if (flush) 3465 IXGBE_WRITE_FLUSH(&adapter->hw); 3466 } 3467 3468 static irqreturn_t ixgbe_msix_other(int irq, void *data) 3469 { 3470 struct ixgbe_adapter *adapter = data; 3471 struct ixgbe_hw *hw = &adapter->hw; 3472 u32 eicr; 3473 3474 /* 3475 * Workaround for Silicon errata. Use clear-by-write instead 3476 * of clear-by-read. Reading with EICS will return the 3477 * interrupt causes without clearing, which later be done 3478 * with the write to EICR. 3479 */ 3480 eicr = IXGBE_READ_REG(hw, IXGBE_EICS); 3481 3482 /* The lower 16bits of the EICR register are for the queue interrupts 3483 * which should be masked here in order to not accidentally clear them if 3484 * the bits are high when ixgbe_msix_other is called. There is a race 3485 * condition otherwise which results in possible performance loss 3486 * especially if the ixgbe_msix_other interrupt is triggering 3487 * consistently (as it would when PPS is turned on for the X540 device) 3488 */ 3489 eicr &= 0xFFFF0000; 3490 3491 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); 3492 3493 if (eicr & IXGBE_EICR_LSC) 3494 ixgbe_check_lsc(adapter); 3495 3496 if (eicr & IXGBE_EICR_MAILBOX) 3497 ixgbe_msg_task(adapter); 3498 3499 if (eicr & IXGBE_EICR_FW_EVENT) 3500 ixgbe_schedule_fw_event(adapter); 3501 3502 switch (hw->mac.type) { 3503 case ixgbe_mac_82599EB: 3504 case ixgbe_mac_X540: 3505 case ixgbe_mac_X550: 3506 case ixgbe_mac_X550EM_x: 3507 case ixgbe_mac_x550em_a: 3508 case ixgbe_mac_e610: 3509 if (hw->phy.type == ixgbe_phy_x550em_ext_t && 3510 (eicr & IXGBE_EICR_GPI_SDP0_X540)) { 3511 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; 3512 ixgbe_service_event_schedule(adapter); 3513 IXGBE_WRITE_REG(hw, IXGBE_EICR, 3514 IXGBE_EICR_GPI_SDP0_X540); 3515 } 3516 if (eicr & IXGBE_EICR_ECC) { 3517 e_info(link, "Received ECC Err, initiating reset\n"); 3518 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3519 ixgbe_service_event_schedule(adapter); 3520 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3521 } 3522 /* Handle Flow Director Full threshold interrupt */ 3523 if (eicr & IXGBE_EICR_FLOW_DIR) { 3524 int reinit_count = 0; 3525 int i; 3526 for (i = 0; i < adapter->num_tx_queues; i++) { 3527 struct ixgbe_ring *ring = adapter->tx_ring[i]; 3528 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, 3529 ring->state)) 3530 reinit_count++; 3531 } 3532 if (reinit_count) { 3533 /* no more flow director interrupts until after init */ 3534 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); 3535 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 3536 ixgbe_service_event_schedule(adapter); 3537 } 3538 } 3539 ixgbe_check_sfp_event(adapter, eicr); 3540 ixgbe_check_overtemp_event(adapter, eicr); 3541 break; 3542 default: 3543 break; 3544 } 3545 3546 ixgbe_check_fan_failure(adapter, eicr); 3547 3548 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3549 ixgbe_ptp_check_pps_event(adapter); 3550 3551 /* re-enable the original interrupt state, no lsc, no queues */ 3552 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3553 ixgbe_irq_enable(adapter, false, false); 3554 3555 return IRQ_HANDLED; 3556 } 3557 3558 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) 3559 { 3560 struct ixgbe_q_vector *q_vector = data; 3561 3562 /* EIAM disabled interrupts (on this vector) for us */ 3563 3564 if (q_vector->rx.ring || q_vector->tx.ring) 3565 napi_schedule_irqoff(&q_vector->napi); 3566 3567 return IRQ_HANDLED; 3568 } 3569 3570 /** 3571 * ixgbe_poll - NAPI Rx polling callback 3572 * @napi: structure for representing this polling device 3573 * @budget: how many packets driver is allowed to clean 3574 * 3575 * This function is used for legacy and MSI, NAPI mode 3576 **/ 3577 int ixgbe_poll(struct napi_struct *napi, int budget) 3578 { 3579 struct ixgbe_q_vector *q_vector = 3580 container_of(napi, struct ixgbe_q_vector, napi); 3581 struct ixgbe_adapter *adapter = q_vector->adapter; 3582 struct ixgbe_ring *ring; 3583 int per_ring_budget, work_done = 0; 3584 bool clean_complete = true; 3585 3586 #ifdef CONFIG_IXGBE_DCA 3587 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) 3588 ixgbe_update_dca(q_vector); 3589 #endif 3590 3591 ixgbe_for_each_ring(ring, q_vector->tx) { 3592 bool wd = ring->xsk_pool ? 3593 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) : 3594 ixgbe_clean_tx_irq(q_vector, ring, budget); 3595 3596 if (!wd) 3597 clean_complete = false; 3598 } 3599 3600 /* Exit if we are called by netpoll */ 3601 if (budget <= 0) 3602 return budget; 3603 3604 /* attempt to distribute budget to each queue fairly, but don't allow 3605 * the budget to go below 1 because we'll exit polling */ 3606 if (q_vector->rx.count > 1) 3607 per_ring_budget = max(budget/q_vector->rx.count, 1); 3608 else 3609 per_ring_budget = budget; 3610 3611 ixgbe_for_each_ring(ring, q_vector->rx) { 3612 int cleaned = ring->xsk_pool ? 3613 ixgbe_clean_rx_irq_zc(q_vector, ring, 3614 per_ring_budget) : 3615 ixgbe_clean_rx_irq(q_vector, ring, 3616 per_ring_budget); 3617 3618 work_done += cleaned; 3619 if (cleaned >= per_ring_budget) 3620 clean_complete = false; 3621 } 3622 3623 /* If all work not completed, return budget and keep polling */ 3624 if (!clean_complete) 3625 return budget; 3626 3627 /* all work done, exit the polling mode */ 3628 if (likely(napi_complete_done(napi, work_done))) { 3629 if (adapter->rx_itr_setting & 1) 3630 ixgbe_set_itr(q_vector); 3631 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3632 ixgbe_irq_enable_queues(adapter, 3633 BIT_ULL(q_vector->v_idx)); 3634 } 3635 3636 return min(work_done, budget - 1); 3637 } 3638 3639 /** 3640 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts 3641 * @adapter: board private structure 3642 * 3643 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests 3644 * interrupts from the kernel. 3645 **/ 3646 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 3647 { 3648 struct net_device *netdev = adapter->netdev; 3649 unsigned int ri = 0, ti = 0; 3650 int vector, err; 3651 3652 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3653 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3654 struct msix_entry *entry = &adapter->msix_entries[vector]; 3655 3656 if (q_vector->tx.ring && q_vector->rx.ring) { 3657 snprintf(q_vector->name, sizeof(q_vector->name), 3658 "%s-TxRx-%u", netdev->name, ri++); 3659 ti++; 3660 } else if (q_vector->rx.ring) { 3661 snprintf(q_vector->name, sizeof(q_vector->name), 3662 "%s-rx-%u", netdev->name, ri++); 3663 } else if (q_vector->tx.ring) { 3664 snprintf(q_vector->name, sizeof(q_vector->name), 3665 "%s-tx-%u", netdev->name, ti++); 3666 } else { 3667 /* skip this unused q_vector */ 3668 continue; 3669 } 3670 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, 3671 q_vector->name, q_vector); 3672 if (err) { 3673 e_err(probe, "request_irq failed for MSIX interrupt " 3674 "Error: %d\n", err); 3675 goto free_queue_irqs; 3676 } 3677 /* If Flow Director is enabled, set interrupt affinity */ 3678 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3679 /* assign the mask for this irq */ 3680 irq_update_affinity_hint(entry->vector, 3681 &q_vector->affinity_mask); 3682 } 3683 } 3684 3685 err = request_irq(adapter->msix_entries[vector].vector, 3686 ixgbe_msix_other, 0, netdev->name, adapter); 3687 if (err) { 3688 e_err(probe, "request_irq for msix_other failed: %d\n", err); 3689 goto free_queue_irqs; 3690 } 3691 3692 return 0; 3693 3694 free_queue_irqs: 3695 while (vector) { 3696 vector--; 3697 irq_update_affinity_hint(adapter->msix_entries[vector].vector, 3698 NULL); 3699 free_irq(adapter->msix_entries[vector].vector, 3700 adapter->q_vector[vector]); 3701 } 3702 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; 3703 pci_disable_msix(adapter->pdev); 3704 kfree(adapter->msix_entries); 3705 adapter->msix_entries = NULL; 3706 return err; 3707 } 3708 3709 /** 3710 * ixgbe_intr - legacy mode Interrupt Handler 3711 * @irq: interrupt number 3712 * @data: pointer to a network interface device structure 3713 **/ 3714 static irqreturn_t ixgbe_intr(int irq, void *data) 3715 { 3716 struct ixgbe_adapter *adapter = data; 3717 struct ixgbe_hw *hw = &adapter->hw; 3718 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3719 u32 eicr; 3720 3721 /* 3722 * Workaround for silicon errata #26 on 82598. Mask the interrupt 3723 * before the read of EICR. 3724 */ 3725 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 3726 3727 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read 3728 * therefore no explicit interrupt disable is necessary */ 3729 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 3730 if (!eicr) { 3731 /* 3732 * shared interrupt alert! 3733 * make sure interrupts are enabled because the read will 3734 * have disabled interrupts due to EIAM 3735 * finish the workaround of silicon errata on 82598. Unmask 3736 * the interrupt that we masked before the EICR read. 3737 */ 3738 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3739 ixgbe_irq_enable(adapter, true, true); 3740 return IRQ_NONE; /* Not our interrupt */ 3741 } 3742 3743 if (eicr & IXGBE_EICR_LSC) 3744 ixgbe_check_lsc(adapter); 3745 3746 if (eicr & IXGBE_EICR_FW_EVENT) 3747 ixgbe_schedule_fw_event(adapter); 3748 3749 switch (hw->mac.type) { 3750 case ixgbe_mac_82599EB: 3751 ixgbe_check_sfp_event(adapter, eicr); 3752 fallthrough; 3753 case ixgbe_mac_X540: 3754 case ixgbe_mac_X550: 3755 case ixgbe_mac_X550EM_x: 3756 case ixgbe_mac_x550em_a: 3757 case ixgbe_mac_e610: 3758 if (eicr & IXGBE_EICR_ECC) { 3759 e_info(link, "Received ECC Err, initiating reset\n"); 3760 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 3761 ixgbe_service_event_schedule(adapter); 3762 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); 3763 } 3764 ixgbe_check_overtemp_event(adapter, eicr); 3765 break; 3766 default: 3767 break; 3768 } 3769 3770 ixgbe_check_fan_failure(adapter, eicr); 3771 if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) 3772 ixgbe_ptp_check_pps_event(adapter); 3773 3774 /* would disable interrupts here but EIAM disabled it */ 3775 napi_schedule_irqoff(&q_vector->napi); 3776 3777 /* 3778 * re-enable link(maybe) and non-queue interrupts, no flush. 3779 * ixgbe_poll will re-enable the queue interrupts 3780 */ 3781 if (!test_bit(__IXGBE_DOWN, &adapter->state)) 3782 ixgbe_irq_enable(adapter, false, false); 3783 3784 return IRQ_HANDLED; 3785 } 3786 3787 /** 3788 * ixgbe_request_irq - initialize interrupts 3789 * @adapter: board private structure 3790 * 3791 * Attempts to configure interrupts using the best available 3792 * capabilities of the hardware and kernel. 3793 **/ 3794 static int ixgbe_request_irq(struct ixgbe_adapter *adapter) 3795 { 3796 struct net_device *netdev = adapter->netdev; 3797 int err; 3798 3799 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 3800 err = ixgbe_request_msix_irqs(adapter); 3801 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) 3802 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, 3803 netdev->name, adapter); 3804 else 3805 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, 3806 netdev->name, adapter); 3807 3808 if (err) 3809 e_err(probe, "request_irq failed, Error %d\n", err); 3810 3811 return err; 3812 } 3813 3814 static void ixgbe_free_irq(struct ixgbe_adapter *adapter) 3815 { 3816 int vector; 3817 3818 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 3819 free_irq(adapter->pdev->irq, adapter); 3820 return; 3821 } 3822 3823 if (!adapter->msix_entries) 3824 return; 3825 3826 for (vector = 0; vector < adapter->num_q_vectors; vector++) { 3827 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; 3828 struct msix_entry *entry = &adapter->msix_entries[vector]; 3829 3830 /* free only the irqs that were actually requested */ 3831 if (!q_vector->rx.ring && !q_vector->tx.ring) 3832 continue; 3833 3834 /* clear the affinity_mask in the IRQ descriptor */ 3835 irq_update_affinity_hint(entry->vector, NULL); 3836 3837 free_irq(entry->vector, q_vector); 3838 } 3839 3840 free_irq(adapter->msix_entries[vector].vector, adapter); 3841 } 3842 3843 /** 3844 * ixgbe_irq_disable - Mask off interrupt generation on the NIC 3845 * @adapter: board private structure 3846 **/ 3847 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) 3848 { 3849 switch (adapter->hw.mac.type) { 3850 case ixgbe_mac_82598EB: 3851 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); 3852 break; 3853 case ixgbe_mac_82599EB: 3854 case ixgbe_mac_X540: 3855 case ixgbe_mac_X550: 3856 case ixgbe_mac_X550EM_x: 3857 case ixgbe_mac_x550em_a: 3858 case ixgbe_mac_e610: 3859 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); 3860 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); 3861 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); 3862 break; 3863 default: 3864 break; 3865 } 3866 IXGBE_WRITE_FLUSH(&adapter->hw); 3867 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 3868 int vector; 3869 3870 for (vector = 0; vector < adapter->num_q_vectors; vector++) 3871 synchronize_irq(adapter->msix_entries[vector].vector); 3872 3873 synchronize_irq(adapter->msix_entries[vector++].vector); 3874 } else { 3875 synchronize_irq(adapter->pdev->irq); 3876 } 3877 } 3878 3879 /** 3880 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts 3881 * @adapter: board private structure 3882 * 3883 **/ 3884 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) 3885 { 3886 struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; 3887 3888 ixgbe_write_eitr(q_vector); 3889 3890 ixgbe_set_ivar(adapter, 0, 0, 0); 3891 ixgbe_set_ivar(adapter, 1, 0, 0); 3892 3893 e_info(hw, "Legacy interrupt IVAR setup done\n"); 3894 } 3895 3896 /** 3897 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset 3898 * @adapter: board private structure 3899 * @ring: structure containing ring specific data 3900 * 3901 * Configure the Tx descriptor ring after a reset. 3902 **/ 3903 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, 3904 struct ixgbe_ring *ring) 3905 { 3906 struct ixgbe_hw *hw = &adapter->hw; 3907 u64 tdba = ring->dma; 3908 int wait_loop = 10; 3909 u32 txdctl = IXGBE_TXDCTL_ENABLE; 3910 u8 reg_idx = ring->reg_idx; 3911 3912 ring->xsk_pool = NULL; 3913 if (ring_is_xdp(ring)) 3914 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 3915 3916 /* disable queue to avoid issues while updating state */ 3917 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); 3918 IXGBE_WRITE_FLUSH(hw); 3919 3920 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), 3921 (tdba & DMA_BIT_MASK(32))); 3922 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); 3923 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), 3924 ring->count * sizeof(union ixgbe_adv_tx_desc)); 3925 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); 3926 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); 3927 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); 3928 3929 /* 3930 * set WTHRESH to encourage burst writeback, it should not be set 3931 * higher than 1 when: 3932 * - ITR is 0 as it could cause false TX hangs 3933 * - ITR is set to > 100k int/sec and BQL is enabled 3934 * 3935 * In order to avoid issues WTHRESH + PTHRESH should always be equal 3936 * to or less than the number of on chip descriptors, which is 3937 * currently 40. 3938 */ 3939 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) 3940 txdctl |= 1u << 16; /* WTHRESH = 1 */ 3941 else 3942 txdctl |= 8u << 16; /* WTHRESH = 8 */ 3943 3944 /* 3945 * Setting PTHRESH to 32 both improves performance 3946 * and avoids a TX hang with DFP enabled 3947 */ 3948 txdctl |= (1u << 8) | /* HTHRESH = 1 */ 3949 32; /* PTHRESH = 32 */ 3950 3951 /* reinitialize flowdirector state */ 3952 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 3953 ring->atr_sample_rate = adapter->atr_sample_rate; 3954 ring->atr_count = 0; 3955 set_bit(__IXGBE_TX_FDIR_INIT_DONE, ring->state); 3956 } else { 3957 ring->atr_sample_rate = 0; 3958 } 3959 3960 /* initialize XPS */ 3961 if (!ring_is_xdp(ring) && 3962 !test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, ring->state)) { 3963 struct ixgbe_q_vector *q_vector = ring->q_vector; 3964 3965 if (q_vector) 3966 netif_set_xps_queue(ring->netdev, 3967 &q_vector->affinity_mask, 3968 ring->queue_index); 3969 } 3970 3971 clear_bit(__IXGBE_HANG_CHECK_ARMED, ring->state); 3972 3973 /* reinitialize tx_buffer_info */ 3974 memset(ring->tx_buffer_info, 0, 3975 sizeof(struct ixgbe_tx_buffer) * ring->count); 3976 3977 /* enable queue */ 3978 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); 3979 3980 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 3981 if (hw->mac.type == ixgbe_mac_82598EB && 3982 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 3983 return; 3984 3985 /* poll to verify queue is enabled */ 3986 do { 3987 usleep_range(1000, 2000); 3988 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 3989 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); 3990 if (!wait_loop) 3991 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); 3992 } 3993 3994 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) 3995 { 3996 struct ixgbe_hw *hw = &adapter->hw; 3997 u32 rttdcs, mtqc; 3998 u8 tcs = adapter->hw_tcs; 3999 4000 if (hw->mac.type == ixgbe_mac_82598EB) 4001 return; 4002 4003 /* disable the arbiter while setting MTQC */ 4004 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); 4005 rttdcs |= IXGBE_RTTDCS_ARBDIS; 4006 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 4007 4008 /* set transmit pool layout */ 4009 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 4010 mtqc = IXGBE_MTQC_VT_ENA; 4011 if (tcs > 4) 4012 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 4013 else if (tcs > 1) 4014 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 4015 else if (adapter->ring_feature[RING_F_VMDQ].mask == 4016 IXGBE_82599_VMDQ_4Q_MASK) 4017 mtqc |= IXGBE_MTQC_32VF; 4018 else 4019 mtqc |= IXGBE_MTQC_64VF; 4020 } else { 4021 if (tcs > 4) { 4022 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; 4023 } else if (tcs > 1) { 4024 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 4025 } else { 4026 u8 max_txq = adapter->num_tx_queues + 4027 adapter->num_xdp_queues; 4028 if (max_txq > 63) 4029 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; 4030 else 4031 mtqc = IXGBE_MTQC_64Q_1PB; 4032 } 4033 } 4034 4035 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); 4036 4037 /* Enable Security TX Buffer IFG for multiple pb */ 4038 if (tcs) { 4039 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); 4040 sectx |= IXGBE_SECTX_DCB; 4041 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); 4042 } 4043 4044 /* re-enable the arbiter */ 4045 rttdcs &= ~IXGBE_RTTDCS_ARBDIS; 4046 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); 4047 } 4048 4049 /** 4050 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset 4051 * @adapter: board private structure 4052 * 4053 * Configure the Tx unit of the MAC after a reset. 4054 **/ 4055 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) 4056 { 4057 struct ixgbe_hw *hw = &adapter->hw; 4058 u32 dmatxctl; 4059 u32 i; 4060 4061 ixgbe_setup_mtqc(adapter); 4062 4063 if (hw->mac.type != ixgbe_mac_82598EB) { 4064 /* DMATXCTL.EN must be before Tx queues are enabled */ 4065 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 4066 dmatxctl |= IXGBE_DMATXCTL_TE; 4067 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); 4068 } 4069 4070 /* Setup the HW Tx Head and Tail descriptor pointers */ 4071 for (i = 0; i < adapter->num_tx_queues; i++) 4072 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); 4073 for (i = 0; i < adapter->num_xdp_queues; i++) 4074 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]); 4075 } 4076 4077 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, 4078 struct ixgbe_ring *ring) 4079 { 4080 struct ixgbe_hw *hw = &adapter->hw; 4081 u8 reg_idx = ring->reg_idx; 4082 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 4083 4084 srrctl |= IXGBE_SRRCTL_DROP_EN; 4085 4086 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 4087 } 4088 4089 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, 4090 struct ixgbe_ring *ring) 4091 { 4092 struct ixgbe_hw *hw = &adapter->hw; 4093 u8 reg_idx = ring->reg_idx; 4094 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); 4095 4096 srrctl &= ~IXGBE_SRRCTL_DROP_EN; 4097 4098 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 4099 } 4100 4101 #ifdef CONFIG_IXGBE_DCB 4102 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 4103 #else 4104 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) 4105 #endif 4106 { 4107 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 4108 struct ixgbe_hw *hw = &adapter->hw; 4109 int i; 4110 4111 if (hw->mac.ops.disable_mdd) 4112 hw->mac.ops.disable_mdd(hw); 4113 4114 if (adapter->ixgbe_ieee_pfc) 4115 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 4116 4117 /* 4118 * We should set the drop enable bit if: 4119 * SR-IOV is enabled 4120 * or 4121 * Number of Rx queues > 1 and flow control is disabled 4122 * 4123 * This allows us to avoid head of line blocking for security 4124 * and performance reasons. 4125 */ 4126 if (adapter->num_vfs || (adapter->num_rx_queues > 1 && 4127 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { 4128 for (i = 0; i < adapter->num_rx_queues; i++) 4129 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); 4130 } else { 4131 for (i = 0; i < adapter->num_rx_queues; i++) 4132 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); 4133 } 4134 4135 if (hw->mac.ops.enable_mdd) 4136 hw->mac.ops.enable_mdd(hw); 4137 } 4138 4139 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 4140 4141 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 4142 struct ixgbe_ring *rx_ring) 4143 { 4144 struct ixgbe_hw *hw = &adapter->hw; 4145 u32 srrctl; 4146 u8 reg_idx = rx_ring->reg_idx; 4147 4148 if (hw->mac.type == ixgbe_mac_82598EB) { 4149 u16 mask = adapter->ring_feature[RING_F_RSS].mask; 4150 4151 /* 4152 * if VMDq is not active we must program one srrctl register 4153 * per RSS queue since we have enabled RDRXCTL.MVMEN 4154 */ 4155 reg_idx &= mask; 4156 } 4157 4158 /* configure header buffer length, needed for RSC */ 4159 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 4160 4161 /* configure the packet buffer length */ 4162 if (rx_ring->xsk_pool) { 4163 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(rx_ring->xsk_pool); 4164 4165 /* If the MAC support setting RXDCTL.RLPML, the 4166 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and 4167 * RXDCTL.RLPML is set to the actual UMEM buffer 4168 * size. If not, then we are stuck with a 1k buffer 4169 * size resolution. In this case frames larger than 4170 * the UMEM buffer size viewed in a 1k resolution will 4171 * be dropped. 4172 */ 4173 if (hw->mac.type != ixgbe_mac_82599EB) 4174 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 4175 else 4176 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 4177 } else if (test_bit(__IXGBE_RX_3K_BUFFER, rx_ring->state)) { 4178 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 4179 } else { 4180 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 4181 } 4182 4183 /* configure descriptor type */ 4184 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; 4185 4186 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); 4187 } 4188 4189 /** 4190 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries 4191 * @adapter: device handle 4192 * 4193 * - 82598/82599/X540: 128 4194 * - X550(non-SRIOV mode): 512 4195 * - X550(SRIOV mode): 64 4196 */ 4197 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) 4198 { 4199 if (adapter->hw.mac.type < ixgbe_mac_X550) 4200 return 128; 4201 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 4202 return 64; 4203 else 4204 return 512; 4205 } 4206 4207 /** 4208 * ixgbe_store_key - Write the RSS key to HW 4209 * @adapter: device handle 4210 * 4211 * Write the RSS key stored in adapter.rss_key to HW. 4212 */ 4213 void ixgbe_store_key(struct ixgbe_adapter *adapter) 4214 { 4215 struct ixgbe_hw *hw = &adapter->hw; 4216 int i; 4217 4218 for (i = 0; i < 10; i++) 4219 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); 4220 } 4221 4222 /** 4223 * ixgbe_init_rss_key - Initialize adapter RSS key 4224 * @adapter: device handle 4225 * 4226 * Allocates and initializes the RSS key if it is not allocated. 4227 **/ 4228 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter) 4229 { 4230 u32 *rss_key; 4231 4232 if (!adapter->rss_key) { 4233 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL); 4234 if (unlikely(!rss_key)) 4235 return -ENOMEM; 4236 4237 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE); 4238 adapter->rss_key = rss_key; 4239 } 4240 4241 return 0; 4242 } 4243 4244 /** 4245 * ixgbe_store_reta - Write the RETA table to HW 4246 * @adapter: device handle 4247 * 4248 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 4249 */ 4250 void ixgbe_store_reta(struct ixgbe_adapter *adapter) 4251 { 4252 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 4253 struct ixgbe_hw *hw = &adapter->hw; 4254 u32 reta = 0; 4255 u32 indices_multi; 4256 u8 *indir_tbl = adapter->rss_indir_tbl; 4257 4258 /* Fill out the redirection table as follows: 4259 * - 82598: 8 bit wide entries containing pair of 4 bit RSS 4260 * indices. 4261 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index 4262 * - X550: 8 bit wide entries containing 6 bit RSS index 4263 */ 4264 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 4265 indices_multi = 0x11; 4266 else 4267 indices_multi = 0x1; 4268 4269 /* Write redirection table to HW */ 4270 for (i = 0; i < reta_entries; i++) { 4271 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; 4272 if ((i & 3) == 3) { 4273 if (i < 128) 4274 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); 4275 else 4276 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), 4277 reta); 4278 reta = 0; 4279 } 4280 } 4281 } 4282 4283 /** 4284 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) 4285 * @adapter: device handle 4286 * 4287 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. 4288 */ 4289 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) 4290 { 4291 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 4292 struct ixgbe_hw *hw = &adapter->hw; 4293 u32 vfreta = 0; 4294 4295 /* Write redirection table to HW */ 4296 for (i = 0; i < reta_entries; i++) { 4297 u16 pool = adapter->num_rx_pools; 4298 4299 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; 4300 if ((i & 3) != 3) 4301 continue; 4302 4303 while (pool--) 4304 IXGBE_WRITE_REG(hw, 4305 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)), 4306 vfreta); 4307 vfreta = 0; 4308 } 4309 } 4310 4311 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) 4312 { 4313 u32 i, j; 4314 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); 4315 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 4316 4317 /* Program table for at least 4 queues w/ SR-IOV so that VFs can 4318 * make full use of any rings they may have. We will use the 4319 * PSRTYPE register to control how many rings we use within the PF. 4320 */ 4321 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4)) 4322 rss_i = 4; 4323 4324 /* Fill out hash function seeds */ 4325 ixgbe_store_key(adapter); 4326 4327 /* Fill out redirection table */ 4328 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); 4329 4330 for (i = 0, j = 0; i < reta_entries; i++, j++) { 4331 if (j == rss_i) 4332 j = 0; 4333 4334 adapter->rss_indir_tbl[i] = j; 4335 } 4336 4337 ixgbe_store_reta(adapter); 4338 } 4339 4340 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) 4341 { 4342 struct ixgbe_hw *hw = &adapter->hw; 4343 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 4344 int i, j; 4345 4346 /* Fill out hash function seeds */ 4347 for (i = 0; i < 10; i++) { 4348 u16 pool = adapter->num_rx_pools; 4349 4350 while (pool--) 4351 IXGBE_WRITE_REG(hw, 4352 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)), 4353 *(adapter->rss_key + i)); 4354 } 4355 4356 /* Fill out the redirection table */ 4357 for (i = 0, j = 0; i < 64; i++, j++) { 4358 if (j == rss_i) 4359 j = 0; 4360 4361 adapter->rss_indir_tbl[i] = j; 4362 } 4363 4364 ixgbe_store_vfreta(adapter); 4365 } 4366 4367 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 4368 { 4369 struct ixgbe_hw *hw = &adapter->hw; 4370 u32 mrqc = 0, rss_field = 0, vfmrqc = 0; 4371 u32 rxcsum; 4372 4373 /* Disable indicating checksum in descriptor, enables RSS hash */ 4374 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); 4375 rxcsum |= IXGBE_RXCSUM_PCSD; 4376 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); 4377 4378 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 4379 if (adapter->ring_feature[RING_F_RSS].mask) 4380 mrqc = IXGBE_MRQC_RSSEN; 4381 } else { 4382 u8 tcs = adapter->hw_tcs; 4383 4384 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 4385 if (tcs > 4) 4386 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ 4387 else if (tcs > 1) 4388 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ 4389 else if (adapter->ring_feature[RING_F_VMDQ].mask == 4390 IXGBE_82599_VMDQ_4Q_MASK) 4391 mrqc = IXGBE_MRQC_VMDQRSS32EN; 4392 else 4393 mrqc = IXGBE_MRQC_VMDQRSS64EN; 4394 4395 /* Enable L3/L4 for Tx Switched packets only for X550, 4396 * older devices do not support this feature 4397 */ 4398 if (hw->mac.type >= ixgbe_mac_X550) 4399 mrqc |= IXGBE_MRQC_L3L4TXSWEN; 4400 } else { 4401 if (tcs > 4) 4402 mrqc = IXGBE_MRQC_RTRSS8TCEN; 4403 else if (tcs > 1) 4404 mrqc = IXGBE_MRQC_RTRSS4TCEN; 4405 else 4406 mrqc = IXGBE_MRQC_RSSEN; 4407 } 4408 } 4409 4410 /* Perform hash on these packet types */ 4411 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | 4412 IXGBE_MRQC_RSS_FIELD_IPV4_TCP | 4413 IXGBE_MRQC_RSS_FIELD_IPV6 | 4414 IXGBE_MRQC_RSS_FIELD_IPV6_TCP; 4415 4416 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) 4417 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; 4418 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) 4419 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; 4420 4421 if ((hw->mac.type >= ixgbe_mac_X550) && 4422 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { 4423 u16 pool = adapter->num_rx_pools; 4424 4425 /* Enable VF RSS mode */ 4426 mrqc |= IXGBE_MRQC_MULTIPLE_RSS; 4427 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4428 4429 /* Setup RSS through the VF registers */ 4430 ixgbe_setup_vfreta(adapter); 4431 vfmrqc = IXGBE_MRQC_RSSEN; 4432 vfmrqc |= rss_field; 4433 4434 while (pool--) 4435 IXGBE_WRITE_REG(hw, 4436 IXGBE_PFVFMRQC(VMDQ_P(pool)), 4437 vfmrqc); 4438 } else { 4439 ixgbe_setup_reta(adapter); 4440 mrqc |= rss_field; 4441 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); 4442 } 4443 } 4444 4445 /** 4446 * ixgbe_configure_rscctl - enable RSC for the indicated ring 4447 * @adapter: address of board private structure 4448 * @ring: structure containing ring specific data 4449 **/ 4450 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, 4451 struct ixgbe_ring *ring) 4452 { 4453 struct ixgbe_hw *hw = &adapter->hw; 4454 u32 rscctrl; 4455 u8 reg_idx = ring->reg_idx; 4456 4457 if (!ring_is_rsc_enabled(ring)) 4458 return; 4459 4460 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); 4461 rscctrl |= IXGBE_RSCCTL_RSCEN; 4462 /* 4463 * we must limit the number of descriptors so that the 4464 * total size of max desc * buf_len is not greater 4465 * than 65536 4466 */ 4467 rscctrl |= IXGBE_RSCCTL_MAXDESC_16; 4468 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); 4469 } 4470 4471 #define IXGBE_MAX_RX_DESC_POLL 10 4472 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, 4473 struct ixgbe_ring *ring) 4474 { 4475 struct ixgbe_hw *hw = &adapter->hw; 4476 int wait_loop = IXGBE_MAX_RX_DESC_POLL; 4477 u32 rxdctl; 4478 u8 reg_idx = ring->reg_idx; 4479 4480 if (ixgbe_removed(hw->hw_addr)) 4481 return; 4482 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ 4483 if (hw->mac.type == ixgbe_mac_82598EB && 4484 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 4485 return; 4486 4487 do { 4488 usleep_range(1000, 2000); 4489 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4490 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); 4491 4492 if (!wait_loop) { 4493 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " 4494 "the polling period\n", reg_idx); 4495 } 4496 } 4497 4498 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, 4499 struct ixgbe_ring *ring) 4500 { 4501 struct ixgbe_hw *hw = &adapter->hw; 4502 union ixgbe_adv_rx_desc *rx_desc; 4503 u64 rdba = ring->dma; 4504 u32 rxdctl; 4505 u8 reg_idx = ring->reg_idx; 4506 4507 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); 4508 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring); 4509 if (ring->xsk_pool) { 4510 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4511 MEM_TYPE_XSK_BUFF_POOL, 4512 NULL)); 4513 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); 4514 } else { 4515 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, 4516 MEM_TYPE_PAGE_SHARED, NULL)); 4517 } 4518 4519 /* disable queue to avoid use of these values while updating state */ 4520 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 4521 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 4522 4523 /* write value back with RXDCTL.ENABLE bit cleared */ 4524 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4525 IXGBE_WRITE_FLUSH(hw); 4526 4527 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); 4528 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); 4529 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), 4530 ring->count * sizeof(union ixgbe_adv_rx_desc)); 4531 /* Force flushing of IXGBE_RDLEN to prevent MDD */ 4532 IXGBE_WRITE_FLUSH(hw); 4533 4534 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); 4535 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); 4536 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); 4537 4538 ixgbe_configure_srrctl(adapter, ring); 4539 ixgbe_configure_rscctl(adapter, ring); 4540 4541 if (hw->mac.type == ixgbe_mac_82598EB) { 4542 /* 4543 * enable cache line friendly hardware writes: 4544 * PTHRESH=32 descriptors (half the internal cache), 4545 * this also removes ugly rx_no_buffer_count increment 4546 * HTHRESH=4 descriptors (to minimize latency on fetch) 4547 * WTHRESH=8 burst writeback up to two cache lines 4548 */ 4549 rxdctl &= ~0x3FFFFF; 4550 rxdctl |= 0x080420; 4551 #if (PAGE_SIZE < 8192) 4552 /* RXDCTL.RLPML does not work on 82599 */ 4553 } else if (hw->mac.type != ixgbe_mac_82599EB) { 4554 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4555 IXGBE_RXDCTL_RLPML_EN); 4556 4557 /* Limit the maximum frame size so we don't overrun the skb. 4558 * This can happen in SRIOV mode when the MTU of the VF is 4559 * higher than the MTU of the PF. 4560 */ 4561 if (ring_uses_build_skb(ring) && 4562 !test_bit(__IXGBE_RX_3K_BUFFER, ring->state)) 4563 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB | 4564 IXGBE_RXDCTL_RLPML_EN; 4565 #endif 4566 } 4567 4568 ring->rx_offset = ixgbe_rx_offset(ring); 4569 4570 if (ring->xsk_pool && hw->mac.type != ixgbe_mac_82599EB) { 4571 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool); 4572 4573 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK | 4574 IXGBE_RXDCTL_RLPML_EN); 4575 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN; 4576 4577 ring->rx_buf_len = xsk_buf_len; 4578 } 4579 4580 /* initialize rx_buffer_info */ 4581 memset(ring->rx_buffer_info, 0, 4582 sizeof(struct ixgbe_rx_buffer) * ring->count); 4583 4584 /* initialize Rx descriptor 0 */ 4585 rx_desc = IXGBE_RX_DESC(ring, 0); 4586 rx_desc->wb.upper.length = 0; 4587 4588 /* enable receive descriptor ring */ 4589 rxdctl |= IXGBE_RXDCTL_ENABLE; 4590 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 4591 4592 ixgbe_rx_desc_queue_enable(adapter, ring); 4593 if (ring->xsk_pool) 4594 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring)); 4595 else 4596 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); 4597 } 4598 4599 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) 4600 { 4601 struct ixgbe_hw *hw = &adapter->hw; 4602 int rss_i = adapter->ring_feature[RING_F_RSS].indices; 4603 u16 pool = adapter->num_rx_pools; 4604 4605 /* PSRTYPE must be initialized in non 82598 adapters */ 4606 u32 psrtype = IXGBE_PSRTYPE_TCPHDR | 4607 IXGBE_PSRTYPE_UDPHDR | 4608 IXGBE_PSRTYPE_IPV4HDR | 4609 IXGBE_PSRTYPE_L2HDR | 4610 IXGBE_PSRTYPE_IPV6HDR; 4611 4612 if (hw->mac.type == ixgbe_mac_82598EB) 4613 return; 4614 4615 if (rss_i > 3) 4616 psrtype |= 2u << 29; 4617 else if (rss_i > 1) 4618 psrtype |= 1u << 29; 4619 4620 while (pool--) 4621 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); 4622 } 4623 4624 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) 4625 { 4626 struct ixgbe_hw *hw = &adapter->hw; 4627 u16 pool = adapter->num_rx_pools; 4628 u32 reg_offset, vf_shift, vmolr; 4629 u32 gcr_ext, vmdctl; 4630 int i; 4631 4632 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 4633 return; 4634 4635 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 4636 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; 4637 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; 4638 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; 4639 vmdctl |= IXGBE_VT_CTL_REPLEN; 4640 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); 4641 4642 /* accept untagged packets until a vlan tag is 4643 * specifically set for the VMDQ queue/pool 4644 */ 4645 vmolr = IXGBE_VMOLR_AUPE; 4646 while (pool--) 4647 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr); 4648 4649 vf_shift = VMDQ_P(0) % 32; 4650 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; 4651 4652 /* Enable only the PF's pool for Tx/Rx */ 4653 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); 4654 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); 4655 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); 4656 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); 4657 if (adapter->bridge_mode == BRIDGE_MODE_VEB) 4658 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 4659 4660 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ 4661 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); 4662 4663 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 4664 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 4665 4666 /* 4667 * Set up VF register offsets for selected VT Mode, 4668 * i.e. 32 or 64 VFs for SR-IOV 4669 */ 4670 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 4671 case IXGBE_82599_VMDQ_8Q_MASK: 4672 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; 4673 break; 4674 case IXGBE_82599_VMDQ_4Q_MASK: 4675 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; 4676 break; 4677 default: 4678 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; 4679 break; 4680 } 4681 4682 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4683 4684 for (i = 0; i < adapter->num_vfs; i++) { 4685 /* configure spoof checking */ 4686 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, 4687 adapter->vfinfo[i].spoofchk_enabled); 4688 4689 /* Enable/Disable RSS query feature */ 4690 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, 4691 adapter->vfinfo[i].rss_query_enabled); 4692 } 4693 } 4694 4695 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) 4696 { 4697 struct ixgbe_hw *hw = &adapter->hw; 4698 struct net_device *netdev = adapter->netdev; 4699 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 4700 struct ixgbe_ring *rx_ring; 4701 int i; 4702 u32 mhadd, hlreg0; 4703 4704 #ifdef IXGBE_FCOE 4705 /* adjust max frame to be able to do baby jumbo for FCoE */ 4706 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && 4707 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) 4708 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; 4709 4710 #endif /* IXGBE_FCOE */ 4711 4712 /* adjust max frame to be at least the size of a standard frame */ 4713 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 4714 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 4715 4716 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); 4717 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { 4718 mhadd &= ~IXGBE_MHADD_MFS_MASK; 4719 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; 4720 4721 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); 4722 } 4723 4724 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4725 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ 4726 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4727 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4728 4729 /* 4730 * Setup the HW Rx Head and Tail Descriptor Pointers and 4731 * the Base and Length of the Rx Descriptor Ring 4732 */ 4733 for (i = 0; i < adapter->num_rx_queues; i++) { 4734 rx_ring = adapter->rx_ring[i]; 4735 4736 clear_ring_rsc_enabled(rx_ring); 4737 clear_bit(__IXGBE_RX_3K_BUFFER, rx_ring->state); 4738 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, rx_ring->state); 4739 4740 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4741 set_ring_rsc_enabled(rx_ring); 4742 4743 if (test_bit(__IXGBE_RX_FCOE, rx_ring->state)) 4744 set_bit(__IXGBE_RX_3K_BUFFER, rx_ring->state); 4745 4746 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 4747 continue; 4748 4749 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, rx_ring->state); 4750 4751 #if (PAGE_SIZE < 8192) 4752 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 4753 set_bit(__IXGBE_RX_3K_BUFFER, rx_ring->state); 4754 4755 if (IXGBE_2K_TOO_SMALL_WITH_PADDING || 4756 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) 4757 set_bit(__IXGBE_RX_3K_BUFFER, rx_ring->state); 4758 #endif 4759 } 4760 } 4761 4762 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) 4763 { 4764 struct ixgbe_hw *hw = &adapter->hw; 4765 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 4766 4767 switch (hw->mac.type) { 4768 case ixgbe_mac_82598EB: 4769 /* 4770 * For VMDq support of different descriptor types or 4771 * buffer sizes through the use of multiple SRRCTL 4772 * registers, RDRXCTL.MVMEN must be set to 1 4773 * 4774 * also, the manual doesn't mention it clearly but DCA hints 4775 * will only use queue 0's tags unless this bit is set. Side 4776 * effects of setting this bit are only that SRRCTL must be 4777 * fully programmed [0..15] 4778 */ 4779 rdrxctl |= IXGBE_RDRXCTL_MVMEN; 4780 break; 4781 case ixgbe_mac_X550: 4782 case ixgbe_mac_X550EM_x: 4783 case ixgbe_mac_x550em_a: 4784 case ixgbe_mac_e610: 4785 if (adapter->num_vfs) 4786 rdrxctl |= IXGBE_RDRXCTL_PSP; 4787 fallthrough; 4788 case ixgbe_mac_82599EB: 4789 case ixgbe_mac_X540: 4790 /* Disable RSC for ACK packets */ 4791 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, 4792 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); 4793 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; 4794 /* hardware requires some bits to be set by default */ 4795 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); 4796 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; 4797 break; 4798 default: 4799 /* We should do nothing since we don't know this hardware */ 4800 return; 4801 } 4802 4803 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); 4804 } 4805 4806 /** 4807 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset 4808 * @adapter: board private structure 4809 * 4810 * Configure the Rx unit of the MAC after a reset. 4811 **/ 4812 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 4813 { 4814 struct ixgbe_hw *hw = &adapter->hw; 4815 int i; 4816 u32 rxctrl, rfctl; 4817 4818 /* disable receives while setting up the descriptors */ 4819 hw->mac.ops.disable_rx(hw); 4820 4821 ixgbe_setup_psrtype(adapter); 4822 ixgbe_setup_rdrxctl(adapter); 4823 4824 /* RSC Setup */ 4825 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); 4826 rfctl &= ~IXGBE_RFCTL_RSC_DIS; 4827 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) 4828 rfctl |= IXGBE_RFCTL_RSC_DIS; 4829 4830 /* disable NFS filtering */ 4831 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS); 4832 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); 4833 4834 /* Program registers for the distribution of queues */ 4835 ixgbe_setup_mrqc(adapter); 4836 4837 /* set_rx_buffer_len must be called before ring initialization */ 4838 ixgbe_set_rx_buffer_len(adapter); 4839 4840 /* 4841 * Setup the HW Rx Head and Tail Descriptor Pointers and 4842 * the Base and Length of the Rx Descriptor Ring 4843 */ 4844 for (i = 0; i < adapter->num_rx_queues; i++) 4845 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); 4846 4847 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 4848 /* disable drop enable for 82598 parts */ 4849 if (hw->mac.type == ixgbe_mac_82598EB) 4850 rxctrl |= IXGBE_RXCTRL_DMBYPS; 4851 4852 /* enable all receives */ 4853 rxctrl |= IXGBE_RXCTRL_RXEN; 4854 hw->mac.ops.enable_rx_dma(hw, rxctrl); 4855 } 4856 4857 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, 4858 __be16 proto, u16 vid) 4859 { 4860 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 4861 struct ixgbe_hw *hw = &adapter->hw; 4862 4863 /* add VID to filter table */ 4864 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4865 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); 4866 4867 set_bit(vid, adapter->active_vlans); 4868 4869 return 0; 4870 } 4871 4872 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) 4873 { 4874 u32 vlvf; 4875 int idx; 4876 4877 /* short cut the special case */ 4878 if (vlan == 0) 4879 return 0; 4880 4881 /* Search for the vlan id in the VLVF entries */ 4882 for (idx = IXGBE_VLVF_ENTRIES; --idx;) { 4883 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); 4884 if ((vlvf & VLAN_VID_MASK) == vlan) 4885 break; 4886 } 4887 4888 return idx; 4889 } 4890 4891 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) 4892 { 4893 struct ixgbe_hw *hw = &adapter->hw; 4894 u32 bits, word; 4895 int idx; 4896 4897 idx = ixgbe_find_vlvf_entry(hw, vid); 4898 if (!idx) 4899 return; 4900 4901 /* See if any other pools are set for this VLAN filter 4902 * entry other than the PF. 4903 */ 4904 word = idx * 2 + (VMDQ_P(0) / 32); 4905 bits = ~BIT(VMDQ_P(0) % 32); 4906 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 4907 4908 /* Disable the filter so this falls into the default pool. */ 4909 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { 4910 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4911 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); 4912 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); 4913 } 4914 } 4915 4916 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, 4917 __be16 proto, u16 vid) 4918 { 4919 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 4920 struct ixgbe_hw *hw = &adapter->hw; 4921 4922 /* remove VID from filter table */ 4923 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 4924 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); 4925 4926 clear_bit(vid, adapter->active_vlans); 4927 4928 return 0; 4929 } 4930 4931 /** 4932 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping 4933 * @adapter: driver data 4934 */ 4935 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) 4936 { 4937 struct ixgbe_hw *hw = &adapter->hw; 4938 u32 vlnctrl; 4939 int i, j; 4940 4941 switch (hw->mac.type) { 4942 case ixgbe_mac_82598EB: 4943 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4944 vlnctrl &= ~IXGBE_VLNCTRL_VME; 4945 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4946 break; 4947 case ixgbe_mac_82599EB: 4948 case ixgbe_mac_X540: 4949 case ixgbe_mac_X550: 4950 case ixgbe_mac_X550EM_x: 4951 case ixgbe_mac_x550em_a: 4952 case ixgbe_mac_e610: 4953 for (i = 0; i < adapter->num_rx_queues; i++) { 4954 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4955 4956 if (!netif_is_ixgbe(ring->netdev)) 4957 continue; 4958 4959 j = ring->reg_idx; 4960 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 4961 vlnctrl &= ~IXGBE_RXDCTL_VME; 4962 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 4963 } 4964 break; 4965 default: 4966 break; 4967 } 4968 } 4969 4970 /** 4971 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping 4972 * @adapter: driver data 4973 */ 4974 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) 4975 { 4976 struct ixgbe_hw *hw = &adapter->hw; 4977 u32 vlnctrl; 4978 int i, j; 4979 4980 switch (hw->mac.type) { 4981 case ixgbe_mac_82598EB: 4982 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 4983 vlnctrl |= IXGBE_VLNCTRL_VME; 4984 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 4985 break; 4986 case ixgbe_mac_82599EB: 4987 case ixgbe_mac_X540: 4988 case ixgbe_mac_X550: 4989 case ixgbe_mac_X550EM_x: 4990 case ixgbe_mac_x550em_a: 4991 case ixgbe_mac_e610: 4992 for (i = 0; i < adapter->num_rx_queues; i++) { 4993 struct ixgbe_ring *ring = adapter->rx_ring[i]; 4994 4995 if (!netif_is_ixgbe(ring->netdev)) 4996 continue; 4997 4998 j = ring->reg_idx; 4999 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); 5000 vlnctrl |= IXGBE_RXDCTL_VME; 5001 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); 5002 } 5003 break; 5004 default: 5005 break; 5006 } 5007 } 5008 5009 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) 5010 { 5011 struct ixgbe_hw *hw = &adapter->hw; 5012 u32 vlnctrl, i; 5013 5014 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 5015 5016 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) { 5017 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */ 5018 vlnctrl |= IXGBE_VLNCTRL_VFE; 5019 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 5020 } else { 5021 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 5022 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 5023 return; 5024 } 5025 5026 /* Nothing to do for 82598 */ 5027 if (hw->mac.type == ixgbe_mac_82598EB) 5028 return; 5029 5030 /* We are already in VLAN promisc, nothing to do */ 5031 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) 5032 return; 5033 5034 /* Set flag so we don't redo unnecessary work */ 5035 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; 5036 5037 /* Add PF to all active pools */ 5038 for (i = IXGBE_VLVF_ENTRIES; --i;) { 5039 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); 5040 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); 5041 5042 vlvfb |= BIT(VMDQ_P(0) % 32); 5043 IXGBE_WRITE_REG(hw, reg_offset, vlvfb); 5044 } 5045 5046 /* Set all bits in the VLAN filter table array */ 5047 for (i = hw->mac.vft_size; i--;) 5048 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); 5049 } 5050 5051 #define VFTA_BLOCK_SIZE 8 5052 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) 5053 { 5054 struct ixgbe_hw *hw = &adapter->hw; 5055 u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; 5056 u32 vid_start = vfta_offset * 32; 5057 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); 5058 u32 i, vid, word, bits; 5059 5060 for (i = IXGBE_VLVF_ENTRIES; --i;) { 5061 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); 5062 5063 /* pull VLAN ID from VLVF */ 5064 vid = vlvf & VLAN_VID_MASK; 5065 5066 /* only concern ourselves with a certain range */ 5067 if (vid < vid_start || vid >= vid_end) 5068 continue; 5069 5070 if (vlvf) { 5071 /* record VLAN ID in VFTA */ 5072 vfta[(vid - vid_start) / 32] |= BIT(vid % 32); 5073 5074 /* if PF is part of this then continue */ 5075 if (test_bit(vid, adapter->active_vlans)) 5076 continue; 5077 } 5078 5079 /* remove PF from the pool */ 5080 word = i * 2 + VMDQ_P(0) / 32; 5081 bits = ~BIT(VMDQ_P(0) % 32); 5082 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); 5083 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); 5084 } 5085 5086 /* extract values from active_vlans and write back to VFTA */ 5087 for (i = VFTA_BLOCK_SIZE; i--;) { 5088 vid = (vfta_offset + i) * 32; 5089 word = vid / BITS_PER_LONG; 5090 bits = vid % BITS_PER_LONG; 5091 5092 vfta[i] |= adapter->active_vlans[word] >> bits; 5093 5094 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); 5095 } 5096 } 5097 5098 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) 5099 { 5100 struct ixgbe_hw *hw = &adapter->hw; 5101 u32 vlnctrl, i; 5102 5103 /* Set VLAN filtering to enabled */ 5104 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 5105 vlnctrl |= IXGBE_VLNCTRL_VFE; 5106 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 5107 5108 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) || 5109 hw->mac.type == ixgbe_mac_82598EB) 5110 return; 5111 5112 /* We are not in VLAN promisc, nothing to do */ 5113 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) 5114 return; 5115 5116 /* Set flag so we don't redo unnecessary work */ 5117 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; 5118 5119 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) 5120 ixgbe_scrub_vfta(adapter, i); 5121 } 5122 5123 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) 5124 { 5125 u16 vid = 1; 5126 5127 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); 5128 5129 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) 5130 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 5131 } 5132 5133 /** 5134 * ixgbe_write_mc_addr_list - write multicast addresses to MTA 5135 * @netdev: network interface device structure 5136 * 5137 * Writes multicast address list to the MTA hash table. 5138 * Returns: -ENOMEM on failure 5139 * 0 on no addresses written 5140 * X on writing X addresses to MTA 5141 **/ 5142 static int ixgbe_write_mc_addr_list(struct net_device *netdev) 5143 { 5144 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 5145 struct ixgbe_hw *hw = &adapter->hw; 5146 5147 if (!netif_running(netdev)) 5148 return 0; 5149 5150 if (hw->mac.ops.update_mc_addr_list) 5151 hw->mac.ops.update_mc_addr_list(hw, netdev); 5152 else 5153 return -ENOMEM; 5154 5155 #ifdef CONFIG_PCI_IOV 5156 ixgbe_restore_vf_multicasts(adapter); 5157 #endif 5158 5159 return netdev_mc_count(netdev); 5160 } 5161 5162 #ifdef CONFIG_PCI_IOV 5163 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) 5164 { 5165 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5166 struct ixgbe_hw *hw = &adapter->hw; 5167 int i; 5168 5169 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5170 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 5171 5172 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 5173 hw->mac.ops.set_rar(hw, i, 5174 mac_table->addr, 5175 mac_table->pool, 5176 IXGBE_RAH_AV); 5177 else 5178 hw->mac.ops.clear_rar(hw, i); 5179 } 5180 } 5181 5182 #endif 5183 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) 5184 { 5185 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5186 struct ixgbe_hw *hw = &adapter->hw; 5187 int i; 5188 5189 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5190 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) 5191 continue; 5192 5193 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; 5194 5195 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 5196 hw->mac.ops.set_rar(hw, i, 5197 mac_table->addr, 5198 mac_table->pool, 5199 IXGBE_RAH_AV); 5200 else 5201 hw->mac.ops.clear_rar(hw, i); 5202 } 5203 } 5204 5205 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) 5206 { 5207 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5208 struct ixgbe_hw *hw = &adapter->hw; 5209 int i; 5210 5211 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5212 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 5213 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 5214 } 5215 5216 ixgbe_sync_mac_table(adapter); 5217 } 5218 5219 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) 5220 { 5221 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5222 struct ixgbe_hw *hw = &adapter->hw; 5223 int i, count = 0; 5224 5225 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5226 /* do not count default RAR as available */ 5227 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) 5228 continue; 5229 5230 /* only count unused and addresses that belong to us */ 5231 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { 5232 if (mac_table->pool != pool) 5233 continue; 5234 } 5235 5236 count++; 5237 } 5238 5239 return count; 5240 } 5241 5242 /* this function destroys the first RAR entry */ 5243 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) 5244 { 5245 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5246 struct ixgbe_hw *hw = &adapter->hw; 5247 5248 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); 5249 mac_table->pool = VMDQ_P(0); 5250 5251 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; 5252 5253 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, 5254 IXGBE_RAH_AV); 5255 } 5256 5257 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, 5258 const u8 *addr, u16 pool) 5259 { 5260 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5261 struct ixgbe_hw *hw = &adapter->hw; 5262 int i; 5263 5264 if (is_zero_ether_addr(addr)) 5265 return -EINVAL; 5266 5267 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5268 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) 5269 continue; 5270 5271 ether_addr_copy(mac_table->addr, addr); 5272 mac_table->pool = pool; 5273 5274 mac_table->state |= IXGBE_MAC_STATE_MODIFIED | 5275 IXGBE_MAC_STATE_IN_USE; 5276 5277 ixgbe_sync_mac_table(adapter); 5278 5279 return i; 5280 } 5281 5282 return -ENOMEM; 5283 } 5284 5285 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, 5286 const u8 *addr, u16 pool) 5287 { 5288 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; 5289 struct ixgbe_hw *hw = &adapter->hw; 5290 int i; 5291 5292 if (is_zero_ether_addr(addr)) 5293 return -EINVAL; 5294 5295 /* search table for addr, if found clear IN_USE flag and sync */ 5296 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { 5297 /* we can only delete an entry if it is in use */ 5298 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) 5299 continue; 5300 /* we only care about entries that belong to the given pool */ 5301 if (mac_table->pool != pool) 5302 continue; 5303 /* we only care about a specific MAC address */ 5304 if (!ether_addr_equal(addr, mac_table->addr)) 5305 continue; 5306 5307 mac_table->state |= IXGBE_MAC_STATE_MODIFIED; 5308 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; 5309 5310 ixgbe_sync_mac_table(adapter); 5311 5312 return 0; 5313 } 5314 5315 return -ENOMEM; 5316 } 5317 5318 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) 5319 { 5320 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 5321 int ret; 5322 5323 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); 5324 5325 return min_t(int, ret, 0); 5326 } 5327 5328 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) 5329 { 5330 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 5331 5332 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); 5333 5334 return 0; 5335 } 5336 5337 /** 5338 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set 5339 * @netdev: network interface device structure 5340 * 5341 * The set_rx_method entry point is called whenever the unicast/multicast 5342 * address list or the network interface flags are updated. This routine is 5343 * responsible for configuring the hardware for proper unicast, multicast and 5344 * promiscuous mode. 5345 **/ 5346 void ixgbe_set_rx_mode(struct net_device *netdev) 5347 { 5348 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 5349 struct ixgbe_hw *hw = &adapter->hw; 5350 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 5351 netdev_features_t features = netdev->features; 5352 int count; 5353 5354 /* Check for Promiscuous and All Multicast modes */ 5355 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 5356 5357 /* set all bits that we expect to always be set */ 5358 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 5359 fctrl |= IXGBE_FCTRL_BAM; 5360 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ 5361 fctrl |= IXGBE_FCTRL_PMCF; 5362 5363 /* clear the bits we are changing the status of */ 5364 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 5365 if (netdev->flags & IFF_PROMISC) { 5366 hw->addr_ctrl.user_set_promisc = true; 5367 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 5368 vmolr |= IXGBE_VMOLR_MPE; 5369 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 5370 } else { 5371 if (netdev->flags & IFF_ALLMULTI) { 5372 fctrl |= IXGBE_FCTRL_MPE; 5373 vmolr |= IXGBE_VMOLR_MPE; 5374 } 5375 hw->addr_ctrl.user_set_promisc = false; 5376 } 5377 5378 /* 5379 * Write addresses to available RAR registers, if there is not 5380 * sufficient space to store all the addresses then enable 5381 * unicast promiscuous mode 5382 */ 5383 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { 5384 fctrl |= IXGBE_FCTRL_UPE; 5385 vmolr |= IXGBE_VMOLR_ROPE; 5386 } 5387 5388 /* Write addresses to the MTA, if the attempt fails 5389 * then we should just turn on promiscuous mode so 5390 * that we can at least receive multicast traffic 5391 */ 5392 count = ixgbe_write_mc_addr_list(netdev); 5393 if (count < 0) { 5394 fctrl |= IXGBE_FCTRL_MPE; 5395 vmolr |= IXGBE_VMOLR_MPE; 5396 } else if (count) { 5397 vmolr |= IXGBE_VMOLR_ROMPE; 5398 } 5399 5400 if (hw->mac.type != ixgbe_mac_82598EB) { 5401 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & 5402 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 5403 IXGBE_VMOLR_ROPE); 5404 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); 5405 } 5406 5407 /* This is useful for sniffing bad packets. */ 5408 if (features & NETIF_F_RXALL) { 5409 /* UPE and MPE will be handled by normal PROMISC logic 5410 * in e1000e_set_rx_mode */ 5411 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ 5412 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ 5413 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ 5414 5415 fctrl &= ~(IXGBE_FCTRL_DPF); 5416 /* NOTE: VLAN filtering is disabled by setting PROMISC */ 5417 } 5418 5419 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 5420 5421 if (features & NETIF_F_HW_VLAN_CTAG_RX) 5422 ixgbe_vlan_strip_enable(adapter); 5423 else 5424 ixgbe_vlan_strip_disable(adapter); 5425 5426 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 5427 ixgbe_vlan_promisc_disable(adapter); 5428 else 5429 ixgbe_vlan_promisc_enable(adapter); 5430 } 5431 5432 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) 5433 { 5434 int q_idx; 5435 5436 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5437 napi_enable(&adapter->q_vector[q_idx]->napi); 5438 } 5439 5440 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) 5441 { 5442 int q_idx; 5443 5444 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) 5445 napi_disable(&adapter->q_vector[q_idx]->napi); 5446 } 5447 5448 static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table) 5449 { 5450 struct ixgbe_adapter *adapter = ixgbe_from_netdev(dev); 5451 struct ixgbe_hw *hw = &adapter->hw; 5452 struct udp_tunnel_info ti; 5453 5454 udp_tunnel_nic_get_port(dev, table, 0, &ti); 5455 if (ti.type == UDP_TUNNEL_TYPE_VXLAN) 5456 adapter->vxlan_port = ti.port; 5457 else 5458 adapter->geneve_port = ti.port; 5459 5460 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, 5461 ntohs(adapter->vxlan_port) | 5462 ntohs(adapter->geneve_port) << 5463 IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT); 5464 return 0; 5465 } 5466 5467 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = { 5468 .sync_table = ixgbe_udp_tunnel_sync, 5469 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5470 .tables = { 5471 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5472 }, 5473 }; 5474 5475 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = { 5476 .sync_table = ixgbe_udp_tunnel_sync, 5477 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY, 5478 .tables = { 5479 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 5480 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 5481 }, 5482 }; 5483 5484 #ifdef CONFIG_IXGBE_DCB 5485 /** 5486 * ixgbe_configure_dcb - Configure DCB hardware 5487 * @adapter: ixgbe adapter struct 5488 * 5489 * This is called by the driver on open to configure the DCB hardware. 5490 * This is also called by the gennetlink interface when reconfiguring 5491 * the DCB state. 5492 */ 5493 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) 5494 { 5495 struct ixgbe_hw *hw = &adapter->hw; 5496 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 5497 5498 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { 5499 if (hw->mac.type == ixgbe_mac_82598EB) 5500 netif_set_tso_max_size(adapter->netdev, 65536); 5501 return; 5502 } 5503 5504 if (hw->mac.type == ixgbe_mac_82598EB) 5505 netif_set_tso_max_size(adapter->netdev, 32768); 5506 5507 #ifdef IXGBE_FCOE 5508 if (adapter->netdev->fcoe_mtu) 5509 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); 5510 #endif 5511 5512 /* reconfigure the hardware */ 5513 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { 5514 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5515 DCB_TX_CONFIG); 5516 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, 5517 DCB_RX_CONFIG); 5518 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); 5519 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { 5520 ixgbe_dcb_hw_ets(&adapter->hw, 5521 adapter->ixgbe_ieee_ets, 5522 max_frame); 5523 ixgbe_dcb_hw_pfc_config(&adapter->hw, 5524 adapter->ixgbe_ieee_pfc->pfc_en, 5525 adapter->ixgbe_ieee_ets->prio_tc); 5526 } 5527 5528 /* Enable RSS Hash per TC */ 5529 if (hw->mac.type != ixgbe_mac_82598EB) { 5530 u32 msb = 0; 5531 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; 5532 5533 while (rss_i) { 5534 msb++; 5535 rss_i >>= 1; 5536 } 5537 5538 /* write msb to all 8 TCs in one write */ 5539 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); 5540 } 5541 } 5542 #endif 5543 5544 /* Additional bittime to account for IXGBE framing */ 5545 #define IXGBE_ETH_FRAMING 20 5546 5547 /** 5548 * ixgbe_hpbthresh - calculate high water mark for flow control 5549 * 5550 * @adapter: board private structure to calculate for 5551 * @pb: packet buffer to calculate 5552 */ 5553 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) 5554 { 5555 struct ixgbe_hw *hw = &adapter->hw; 5556 struct net_device *dev = adapter->netdev; 5557 int link, tc, kb, marker; 5558 u32 dv_id, rx_pba; 5559 5560 /* Calculate max LAN frame size */ 5561 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; 5562 5563 #ifdef IXGBE_FCOE 5564 /* FCoE traffic class uses FCOE jumbo frames */ 5565 if (dev->fcoe_mtu && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE && 5566 (pb == ixgbe_fcoe_get_tc(adapter))) 5567 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5568 #endif 5569 5570 /* Calculate delay value for device */ 5571 switch (hw->mac.type) { 5572 case ixgbe_mac_X540: 5573 case ixgbe_mac_X550: 5574 case ixgbe_mac_X550EM_x: 5575 case ixgbe_mac_x550em_a: 5576 case ixgbe_mac_e610: 5577 dv_id = IXGBE_DV_X540(link, tc); 5578 break; 5579 default: 5580 dv_id = IXGBE_DV(link, tc); 5581 break; 5582 } 5583 5584 /* Loopback switch introduces additional latency */ 5585 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 5586 dv_id += IXGBE_B2BT(tc); 5587 5588 /* Delay value is calculated in bit times convert to KB */ 5589 kb = IXGBE_BT2KB(dv_id); 5590 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; 5591 5592 marker = rx_pba - kb; 5593 5594 /* It is possible that the packet buffer is not large enough 5595 * to provide required headroom. In this case throw an error 5596 * to user and a do the best we can. 5597 */ 5598 if (marker < 0) { 5599 e_warn(drv, "Packet Buffer(%i) can not provide enough" 5600 "headroom to support flow control." 5601 "Decrease MTU or number of traffic classes\n", pb); 5602 marker = tc + 1; 5603 } 5604 5605 return marker; 5606 } 5607 5608 /** 5609 * ixgbe_lpbthresh - calculate low water mark for flow control 5610 * 5611 * @adapter: board private structure to calculate for 5612 * @pb: packet buffer to calculate 5613 */ 5614 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) 5615 { 5616 struct ixgbe_hw *hw = &adapter->hw; 5617 struct net_device *dev = adapter->netdev; 5618 int tc; 5619 u32 dv_id; 5620 5621 /* Calculate max LAN frame size */ 5622 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 5623 5624 #ifdef IXGBE_FCOE 5625 /* FCoE traffic class uses FCOE jumbo frames */ 5626 if (dev->fcoe_mtu && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE && 5627 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) 5628 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; 5629 #endif 5630 5631 /* Calculate delay value for device */ 5632 switch (hw->mac.type) { 5633 case ixgbe_mac_X540: 5634 case ixgbe_mac_X550: 5635 case ixgbe_mac_X550EM_x: 5636 case ixgbe_mac_x550em_a: 5637 case ixgbe_mac_e610: 5638 dv_id = IXGBE_LOW_DV_X540(tc); 5639 break; 5640 default: 5641 dv_id = IXGBE_LOW_DV(tc); 5642 break; 5643 } 5644 5645 /* Delay value is calculated in bit times convert to KB */ 5646 return IXGBE_BT2KB(dv_id); 5647 } 5648 5649 /* 5650 * ixgbe_pbthresh_setup - calculate and setup high low water marks 5651 */ 5652 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) 5653 { 5654 struct ixgbe_hw *hw = &adapter->hw; 5655 int num_tc = adapter->hw_tcs; 5656 int i; 5657 5658 if (!num_tc) 5659 num_tc = 1; 5660 5661 for (i = 0; i < num_tc; i++) { 5662 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); 5663 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); 5664 5665 /* Low water marks must not be larger than high water marks */ 5666 if (hw->fc.low_water[i] > hw->fc.high_water[i]) 5667 hw->fc.low_water[i] = 0; 5668 } 5669 5670 for (; i < MAX_TRAFFIC_CLASS; i++) 5671 hw->fc.high_water[i] = 0; 5672 } 5673 5674 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) 5675 { 5676 struct ixgbe_hw *hw = &adapter->hw; 5677 int hdrm; 5678 u8 tc = adapter->hw_tcs; 5679 5680 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || 5681 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 5682 hdrm = 32 << adapter->fdir_pballoc; 5683 else 5684 hdrm = 0; 5685 5686 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); 5687 ixgbe_pbthresh_setup(adapter); 5688 } 5689 5690 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) 5691 { 5692 struct ixgbe_hw *hw = &adapter->hw; 5693 struct hlist_node *node2; 5694 struct ixgbe_fdir_filter *filter; 5695 u8 queue; 5696 5697 spin_lock(&adapter->fdir_perfect_lock); 5698 5699 if (!hlist_empty(&adapter->fdir_filter_list)) 5700 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); 5701 5702 hlist_for_each_entry_safe(filter, node2, 5703 &adapter->fdir_filter_list, fdir_node) { 5704 if (filter->action == IXGBE_FDIR_DROP_QUEUE) { 5705 queue = IXGBE_FDIR_DROP_QUEUE; 5706 } else { 5707 u32 ring = ethtool_get_flow_spec_ring(filter->action); 5708 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action); 5709 5710 if (!vf && (ring >= adapter->num_rx_queues)) { 5711 e_err(drv, "FDIR restore failed without VF, ring: %u\n", 5712 ring); 5713 continue; 5714 } else if (vf && 5715 ((vf > adapter->num_vfs) || 5716 ring >= adapter->num_rx_queues_per_pool)) { 5717 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n", 5718 vf, ring); 5719 continue; 5720 } 5721 5722 /* Map the ring onto the absolute queue index */ 5723 if (!vf) 5724 queue = adapter->rx_ring[ring]->reg_idx; 5725 else 5726 queue = ((vf - 1) * 5727 adapter->num_rx_queues_per_pool) + ring; 5728 } 5729 5730 ixgbe_fdir_write_perfect_filter_82599(hw, 5731 &filter->filter, filter->sw_idx, queue); 5732 } 5733 5734 spin_unlock(&adapter->fdir_perfect_lock); 5735 } 5736 5737 /** 5738 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue 5739 * @rx_ring: ring to free buffers from 5740 **/ 5741 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) 5742 { 5743 u16 i = rx_ring->next_to_clean; 5744 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; 5745 5746 if (rx_ring->xsk_pool) { 5747 ixgbe_xsk_clean_rx_ring(rx_ring); 5748 goto skip_free; 5749 } 5750 5751 /* Free all the Rx ring sk_buffs */ 5752 while (i != rx_ring->next_to_alloc) { 5753 if (rx_buffer->skb) { 5754 struct sk_buff *skb = rx_buffer->skb; 5755 if (IXGBE_CB(skb)->page_released) 5756 dma_unmap_page_attrs(rx_ring->dev, 5757 IXGBE_CB(skb)->dma, 5758 ixgbe_rx_pg_size(rx_ring), 5759 DMA_FROM_DEVICE, 5760 IXGBE_RX_DMA_ATTR); 5761 dev_kfree_skb(skb); 5762 } 5763 5764 /* Invalidate cache lines that may have been written to by 5765 * device so that we avoid corrupting memory. 5766 */ 5767 dma_sync_single_range_for_cpu(rx_ring->dev, 5768 rx_buffer->dma, 5769 rx_buffer->page_offset, 5770 ixgbe_rx_bufsz(rx_ring), 5771 DMA_FROM_DEVICE); 5772 5773 /* free resources associated with mapping */ 5774 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, 5775 ixgbe_rx_pg_size(rx_ring), 5776 DMA_FROM_DEVICE, 5777 IXGBE_RX_DMA_ATTR); 5778 __page_frag_cache_drain(rx_buffer->page, 5779 rx_buffer->pagecnt_bias); 5780 5781 i++; 5782 rx_buffer++; 5783 if (i == rx_ring->count) { 5784 i = 0; 5785 rx_buffer = rx_ring->rx_buffer_info; 5786 } 5787 } 5788 5789 skip_free: 5790 rx_ring->next_to_alloc = 0; 5791 rx_ring->next_to_clean = 0; 5792 rx_ring->next_to_use = 0; 5793 } 5794 5795 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter, 5796 struct ixgbe_fwd_adapter *accel) 5797 { 5798 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; 5799 int num_tc = netdev_get_num_tc(adapter->netdev); 5800 struct net_device *vdev = accel->netdev; 5801 int i, baseq, err; 5802 5803 baseq = accel->pool * adapter->num_rx_queues_per_pool; 5804 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n", 5805 accel->pool, adapter->num_rx_pools, 5806 baseq, baseq + adapter->num_rx_queues_per_pool); 5807 5808 accel->rx_base_queue = baseq; 5809 accel->tx_base_queue = baseq; 5810 5811 /* record configuration for macvlan interface in vdev */ 5812 for (i = 0; i < num_tc; i++) 5813 netdev_bind_sb_channel_queue(adapter->netdev, vdev, 5814 i, rss_i, baseq + (rss_i * i)); 5815 5816 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5817 adapter->rx_ring[baseq + i]->netdev = vdev; 5818 5819 /* Guarantee all rings are updated before we update the 5820 * MAC address filter. 5821 */ 5822 wmb(); 5823 5824 /* ixgbe_add_mac_filter will return an index if it succeeds, so we 5825 * need to only treat it as an error value if it is negative. 5826 */ 5827 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr, 5828 VMDQ_P(accel->pool)); 5829 if (err >= 0) 5830 return 0; 5831 5832 /* if we cannot add the MAC rule then disable the offload */ 5833 macvlan_release_l2fw_offload(vdev); 5834 5835 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) 5836 adapter->rx_ring[baseq + i]->netdev = NULL; 5837 5838 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n"); 5839 5840 /* unbind the queues and drop the subordinate channel config */ 5841 netdev_unbind_sb_channel(adapter->netdev, vdev); 5842 netdev_set_sb_channel(vdev, 0); 5843 5844 clear_bit(accel->pool, adapter->fwd_bitmask); 5845 kfree(accel); 5846 5847 return err; 5848 } 5849 5850 static int ixgbe_macvlan_up(struct net_device *vdev, 5851 struct netdev_nested_priv *priv) 5852 { 5853 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 5854 struct ixgbe_fwd_adapter *accel; 5855 5856 if (!netif_is_macvlan(vdev)) 5857 return 0; 5858 5859 accel = macvlan_accel_priv(vdev); 5860 if (!accel) 5861 return 0; 5862 5863 ixgbe_fwd_ring_up(adapter, accel); 5864 5865 return 0; 5866 } 5867 5868 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) 5869 { 5870 struct netdev_nested_priv priv = { 5871 .data = (void *)adapter, 5872 }; 5873 5874 netdev_walk_all_upper_dev_rcu(adapter->netdev, 5875 ixgbe_macvlan_up, &priv); 5876 } 5877 5878 static void ixgbe_configure(struct ixgbe_adapter *adapter) 5879 { 5880 struct ixgbe_hw *hw = &adapter->hw; 5881 5882 ixgbe_configure_pb(adapter); 5883 #ifdef CONFIG_IXGBE_DCB 5884 ixgbe_configure_dcb(adapter); 5885 #endif 5886 /* 5887 * We must restore virtualization before VLANs or else 5888 * the VLVF registers will not be populated 5889 */ 5890 ixgbe_configure_virtualization(adapter); 5891 5892 ixgbe_set_rx_mode(adapter->netdev); 5893 ixgbe_restore_vlan(adapter); 5894 ixgbe_ipsec_restore(adapter); 5895 5896 switch (hw->mac.type) { 5897 case ixgbe_mac_82599EB: 5898 case ixgbe_mac_X540: 5899 hw->mac.ops.disable_rx_buff(hw); 5900 break; 5901 default: 5902 break; 5903 } 5904 5905 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { 5906 ixgbe_init_fdir_signature_82599(&adapter->hw, 5907 adapter->fdir_pballoc); 5908 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { 5909 ixgbe_init_fdir_perfect_82599(&adapter->hw, 5910 adapter->fdir_pballoc); 5911 ixgbe_fdir_filter_restore(adapter); 5912 } 5913 5914 switch (hw->mac.type) { 5915 case ixgbe_mac_82599EB: 5916 case ixgbe_mac_X540: 5917 hw->mac.ops.enable_rx_buff(hw); 5918 break; 5919 default: 5920 break; 5921 } 5922 5923 #ifdef CONFIG_IXGBE_DCA 5924 /* configure DCA */ 5925 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) 5926 ixgbe_setup_dca(adapter); 5927 #endif /* CONFIG_IXGBE_DCA */ 5928 5929 #ifdef IXGBE_FCOE 5930 /* configure FCoE L2 filters, redirection table, and Rx control */ 5931 ixgbe_configure_fcoe(adapter); 5932 5933 #endif /* IXGBE_FCOE */ 5934 ixgbe_configure_tx(adapter); 5935 ixgbe_configure_rx(adapter); 5936 ixgbe_configure_dfwd(adapter); 5937 } 5938 5939 /** 5940 * ixgbe_enable_link_status_events - enable link status events 5941 * @adapter: pointer to the adapter structure 5942 * @mask: event mask to be set 5943 * 5944 * Enables link status events by invoking ixgbe_configure_lse() 5945 * 5946 * Return: the exit code of the operation. 5947 */ 5948 static int ixgbe_enable_link_status_events(struct ixgbe_adapter *adapter, 5949 u16 mask) 5950 { 5951 int err; 5952 5953 err = ixgbe_configure_lse(&adapter->hw, true, mask); 5954 if (err) 5955 return err; 5956 5957 adapter->lse_mask = mask; 5958 return 0; 5959 } 5960 5961 /** 5962 * ixgbe_disable_link_status_events - disable link status events 5963 * @adapter: pointer to the adapter structure 5964 * 5965 * Disables link status events by invoking ixgbe_configure_lse() 5966 * 5967 * Return: the exit code of the operation. 5968 */ 5969 static int ixgbe_disable_link_status_events(struct ixgbe_adapter *adapter) 5970 { 5971 int err; 5972 5973 err = ixgbe_configure_lse(&adapter->hw, false, adapter->lse_mask); 5974 if (err) 5975 return err; 5976 5977 adapter->lse_mask = 0; 5978 return 0; 5979 } 5980 5981 /** 5982 * ixgbe_sfp_link_config - set up SFP+ link 5983 * @adapter: pointer to private adapter struct 5984 **/ 5985 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) 5986 { 5987 /* 5988 * We are assuming the worst case scenario here, and that 5989 * is that an SFP was inserted/removed after the reset 5990 * but before SFP detection was enabled. As such the best 5991 * solution is to just start searching as soon as we start 5992 */ 5993 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 5994 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 5995 5996 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 5997 adapter->sfp_poll_time = 0; 5998 } 5999 6000 /** 6001 * ixgbe_non_sfp_link_config - set up non-SFP+ link 6002 * @hw: pointer to private hardware struct 6003 * 6004 * Configure non-SFP link. 6005 * 6006 * Return: 0 on success, negative on failure 6007 **/ 6008 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) 6009 { 6010 struct ixgbe_adapter *adapter = container_of(hw, struct ixgbe_adapter, 6011 hw); 6012 u16 mask = ~((u16)(IXGBE_ACI_LINK_EVENT_UPDOWN | 6013 IXGBE_ACI_LINK_EVENT_MEDIA_NA | 6014 IXGBE_ACI_LINK_EVENT_MODULE_QUAL_FAIL | 6015 IXGBE_ACI_LINK_EVENT_PHY_FW_LOAD_FAIL)); 6016 bool autoneg, link_up = false; 6017 int ret = -EIO; 6018 u32 speed; 6019 6020 if (hw->mac.ops.check_link) 6021 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); 6022 6023 if (ret) 6024 return ret; 6025 6026 speed = hw->phy.autoneg_advertised; 6027 if (!speed && hw->mac.ops.get_link_capabilities) { 6028 ret = hw->mac.ops.get_link_capabilities(hw, &speed, 6029 &autoneg); 6030 /* remove NBASE-T speeds from default autonegotiation 6031 * to accommodate broken network switches in the field 6032 * which cannot cope with advertised NBASE-T speeds 6033 */ 6034 speed &= ~(IXGBE_LINK_SPEED_5GB_FULL | 6035 IXGBE_LINK_SPEED_2_5GB_FULL); 6036 } 6037 6038 if (ret) 6039 return ret; 6040 6041 if (hw->mac.ops.setup_link) { 6042 if (adapter->hw.mac.type == ixgbe_mac_e610) { 6043 ret = ixgbe_enable_link_status_events(adapter, mask); 6044 if (ret) 6045 return ret; 6046 } 6047 ret = hw->mac.ops.setup_link(hw, speed, link_up); 6048 } 6049 6050 return ret; 6051 } 6052 6053 /** 6054 * ixgbe_check_media_subtask - check for media 6055 * @adapter: pointer to adapter structure 6056 * 6057 * If media is available then initialize PHY user configuration. Configure the 6058 * PHY if the interface is up. 6059 */ 6060 static void ixgbe_check_media_subtask(struct ixgbe_adapter *adapter) 6061 { 6062 struct ixgbe_hw *hw = &adapter->hw; 6063 6064 /* No need to check for media if it's already present */ 6065 if (!(adapter->flags2 & IXGBE_FLAG2_NO_MEDIA)) 6066 return; 6067 6068 /* Refresh link info and check if media is present */ 6069 if (ixgbe_update_link_info(hw)) 6070 return; 6071 6072 ixgbe_check_link_cfg_err(adapter, hw->link.link_info.link_cfg_err); 6073 6074 if (hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE) { 6075 /* PHY settings are reset on media insertion, reconfigure 6076 * PHY to preserve settings. 6077 */ 6078 if (!(ixgbe_non_sfp_link_config(&adapter->hw))) 6079 adapter->flags2 &= ~IXGBE_FLAG2_NO_MEDIA; 6080 6081 /* A Link Status Event will be generated; the event handler 6082 * will complete bringing the interface up 6083 */ 6084 } 6085 } 6086 6087 /** 6088 * ixgbe_clear_vf_stats_counters - Clear out VF stats after reset 6089 * @adapter: board private structure 6090 * 6091 * On a reset we need to clear out the VF stats or accounting gets 6092 * messed up because they're not clear on read. 6093 **/ 6094 static void ixgbe_clear_vf_stats_counters(struct ixgbe_adapter *adapter) 6095 { 6096 struct ixgbe_hw *hw = &adapter->hw; 6097 int i; 6098 6099 for (i = 0; i < adapter->num_vfs; i++) { 6100 adapter->vfinfo[i].last_vfstats.gprc = 6101 IXGBE_READ_REG(hw, IXGBE_PVFGPRC(i)); 6102 adapter->vfinfo[i].saved_rst_vfstats.gprc += 6103 adapter->vfinfo[i].vfstats.gprc; 6104 adapter->vfinfo[i].vfstats.gprc = 0; 6105 adapter->vfinfo[i].last_vfstats.gptc = 6106 IXGBE_READ_REG(hw, IXGBE_PVFGPTC(i)); 6107 adapter->vfinfo[i].saved_rst_vfstats.gptc += 6108 adapter->vfinfo[i].vfstats.gptc; 6109 adapter->vfinfo[i].vfstats.gptc = 0; 6110 adapter->vfinfo[i].last_vfstats.gorc = 6111 IXGBE_READ_REG(hw, IXGBE_PVFGORC_LSB(i)); 6112 adapter->vfinfo[i].saved_rst_vfstats.gorc += 6113 adapter->vfinfo[i].vfstats.gorc; 6114 adapter->vfinfo[i].vfstats.gorc = 0; 6115 adapter->vfinfo[i].last_vfstats.gotc = 6116 IXGBE_READ_REG(hw, IXGBE_PVFGOTC_LSB(i)); 6117 adapter->vfinfo[i].saved_rst_vfstats.gotc += 6118 adapter->vfinfo[i].vfstats.gotc; 6119 adapter->vfinfo[i].vfstats.gotc = 0; 6120 adapter->vfinfo[i].last_vfstats.mprc = 6121 IXGBE_READ_REG(hw, IXGBE_PVFMPRC(i)); 6122 adapter->vfinfo[i].saved_rst_vfstats.mprc += 6123 adapter->vfinfo[i].vfstats.mprc; 6124 adapter->vfinfo[i].vfstats.mprc = 0; 6125 } 6126 } 6127 6128 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) 6129 { 6130 struct ixgbe_hw *hw = &adapter->hw; 6131 u32 gpie = 0; 6132 6133 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { 6134 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 6135 IXGBE_GPIE_OCD; 6136 gpie |= IXGBE_GPIE_EIAME; 6137 /* 6138 * use EIAM to auto-mask when MSI-X interrupt is asserted 6139 * this saves a register write for every interrupt 6140 */ 6141 switch (hw->mac.type) { 6142 case ixgbe_mac_82598EB: 6143 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 6144 break; 6145 case ixgbe_mac_82599EB: 6146 case ixgbe_mac_X540: 6147 case ixgbe_mac_X550: 6148 case ixgbe_mac_X550EM_x: 6149 case ixgbe_mac_x550em_a: 6150 case ixgbe_mac_e610: 6151 default: 6152 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 6153 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 6154 break; 6155 } 6156 } else { 6157 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 6158 * specifically only auto mask tx and rx interrupts */ 6159 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 6160 } 6161 6162 /* XXX: to interrupt immediately for EICS writes, enable this */ 6163 /* gpie |= IXGBE_GPIE_EIMEN; */ 6164 6165 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 6166 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 6167 6168 switch (adapter->ring_feature[RING_F_VMDQ].mask) { 6169 case IXGBE_82599_VMDQ_8Q_MASK: 6170 gpie |= IXGBE_GPIE_VTMODE_16; 6171 break; 6172 case IXGBE_82599_VMDQ_4Q_MASK: 6173 gpie |= IXGBE_GPIE_VTMODE_32; 6174 break; 6175 default: 6176 gpie |= IXGBE_GPIE_VTMODE_64; 6177 break; 6178 } 6179 } 6180 6181 /* Enable Thermal over heat sensor interrupt */ 6182 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { 6183 switch (adapter->hw.mac.type) { 6184 case ixgbe_mac_82599EB: 6185 gpie |= IXGBE_SDP0_GPIEN_8259X; 6186 break; 6187 default: 6188 break; 6189 } 6190 } 6191 6192 /* Enable fan failure interrupt */ 6193 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) 6194 gpie |= IXGBE_SDP1_GPIEN(hw); 6195 6196 switch (hw->mac.type) { 6197 case ixgbe_mac_82599EB: 6198 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; 6199 break; 6200 case ixgbe_mac_X550EM_x: 6201 case ixgbe_mac_x550em_a: 6202 gpie |= IXGBE_SDP0_GPIEN_X540; 6203 break; 6204 default: 6205 break; 6206 } 6207 6208 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 6209 } 6210 6211 static void ixgbe_up_complete(struct ixgbe_adapter *adapter) 6212 { 6213 struct ixgbe_hw *hw = &adapter->hw; 6214 int err; 6215 u32 ctrl_ext; 6216 6217 ixgbe_get_hw_control(adapter); 6218 ixgbe_setup_gpie(adapter); 6219 6220 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 6221 ixgbe_configure_msix(adapter); 6222 else 6223 ixgbe_configure_msi_and_legacy(adapter); 6224 6225 /* enable the optics for 82599 SFP+ fiber */ 6226 if (hw->mac.ops.enable_tx_laser) 6227 hw->mac.ops.enable_tx_laser(hw); 6228 6229 if (hw->phy.ops.set_phy_power) 6230 hw->phy.ops.set_phy_power(hw, true); 6231 6232 smp_mb__before_atomic(); 6233 clear_bit(__IXGBE_DOWN, &adapter->state); 6234 ixgbe_napi_enable_all(adapter); 6235 6236 if (ixgbe_is_sfp(hw)) { 6237 ixgbe_sfp_link_config(adapter); 6238 } else { 6239 err = ixgbe_non_sfp_link_config(hw); 6240 if (err) 6241 e_err(probe, "link_config FAILED %d\n", err); 6242 } 6243 6244 /* clear any pending interrupts, may auto mask */ 6245 IXGBE_READ_REG(hw, IXGBE_EICR); 6246 ixgbe_irq_enable(adapter, true, true); 6247 6248 /* 6249 * If this adapter has a fan, check to see if we had a failure 6250 * before we enabled the interrupt. 6251 */ 6252 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 6253 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 6254 if (esdp & IXGBE_ESDP_SDP1) 6255 e_crit(drv, "Fan has stopped, replace the adapter\n"); 6256 } 6257 6258 /* bring the link up in the watchdog, this could race with our first 6259 * link up interrupt but shouldn't be a problem */ 6260 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 6261 adapter->link_check_timeout = jiffies; 6262 mod_timer(&adapter->service_timer, jiffies); 6263 6264 ixgbe_clear_vf_stats_counters(adapter); 6265 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 6266 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 6267 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 6268 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 6269 6270 /* update setting rx tx for all active vfs */ 6271 ixgbe_set_all_vfs(adapter); 6272 } 6273 6274 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) 6275 { 6276 /* put off any impending NetWatchDogTimeout */ 6277 netif_trans_update(adapter->netdev); 6278 6279 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) 6280 usleep_range(1000, 2000); 6281 if (adapter->hw.phy.type == ixgbe_phy_fw) 6282 ixgbe_watchdog_link_is_down(adapter); 6283 ixgbe_down(adapter); 6284 /* 6285 * If SR-IOV enabled then wait a bit before bringing the adapter 6286 * back up to give the VFs time to respond to the reset. The 6287 * two second wait is based upon the watchdog timer cycle in 6288 * the VF driver. 6289 */ 6290 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 6291 msleep(2000); 6292 ixgbe_up(adapter); 6293 6294 /* E610 has no FW event to notify all PFs of an EMPR reset, so 6295 * refresh the FW version here to pick up any new FW version after 6296 * a hardware reset (e.g. EMPR triggered by another PF's devlink 6297 * reload). ixgbe_refresh_fw_version() updates both hw->flash and 6298 * adapter->eeprom_id so ethtool -i reports the correct string. 6299 */ 6300 if (adapter->hw.mac.type == ixgbe_mac_e610) 6301 (void)ixgbe_refresh_fw_version(adapter); 6302 6303 clear_bit(__IXGBE_RESETTING, &adapter->state); 6304 } 6305 6306 void ixgbe_up(struct ixgbe_adapter *adapter) 6307 { 6308 /* hardware has been reset, we need to reload some things */ 6309 ixgbe_configure(adapter); 6310 6311 ixgbe_up_complete(adapter); 6312 } 6313 6314 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter) 6315 { 6316 u16 devctl2; 6317 6318 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2); 6319 6320 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) { 6321 case IXGBE_PCIDEVCTRL2_17_34s: 6322 case IXGBE_PCIDEVCTRL2_4_8s: 6323 /* For now we cap the upper limit on delay to 2 seconds 6324 * as we end up going up to 34 seconds of delay in worst 6325 * case timeout value. 6326 */ 6327 case IXGBE_PCIDEVCTRL2_1_2s: 6328 return 2000000ul; /* 2.0 s */ 6329 case IXGBE_PCIDEVCTRL2_260_520ms: 6330 return 520000ul; /* 520 ms */ 6331 case IXGBE_PCIDEVCTRL2_65_130ms: 6332 return 130000ul; /* 130 ms */ 6333 case IXGBE_PCIDEVCTRL2_16_32ms: 6334 return 32000ul; /* 32 ms */ 6335 case IXGBE_PCIDEVCTRL2_1_2ms: 6336 return 2000ul; /* 2 ms */ 6337 case IXGBE_PCIDEVCTRL2_50_100us: 6338 return 100ul; /* 100 us */ 6339 case IXGBE_PCIDEVCTRL2_16_32ms_def: 6340 return 32000ul; /* 32 ms */ 6341 default: 6342 break; 6343 } 6344 6345 /* We shouldn't need to hit this path, but just in case default as 6346 * though completion timeout is not supported and support 32ms. 6347 */ 6348 return 32000ul; 6349 } 6350 6351 void ixgbe_disable_rx(struct ixgbe_adapter *adapter) 6352 { 6353 unsigned long wait_delay, delay_interval; 6354 struct ixgbe_hw *hw = &adapter->hw; 6355 int i, wait_loop; 6356 u32 rxdctl; 6357 6358 /* disable receives */ 6359 hw->mac.ops.disable_rx(hw); 6360 6361 if (ixgbe_removed(hw->hw_addr)) 6362 return; 6363 6364 /* disable all enabled Rx queues */ 6365 for (i = 0; i < adapter->num_rx_queues; i++) { 6366 struct ixgbe_ring *ring = adapter->rx_ring[i]; 6367 u8 reg_idx = ring->reg_idx; 6368 6369 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 6370 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 6371 rxdctl |= IXGBE_RXDCTL_SWFLSH; 6372 6373 /* write value back with RXDCTL.ENABLE bit cleared */ 6374 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 6375 } 6376 6377 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 6378 if (hw->mac.type == ixgbe_mac_82598EB && 6379 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 6380 return; 6381 6382 /* Determine our minimum delay interval. We will increase this value 6383 * with each subsequent test. This way if the device returns quickly 6384 * we should spend as little time as possible waiting, however as 6385 * the time increases we will wait for larger periods of time. 6386 * 6387 * The trick here is that we increase the interval using the 6388 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 6389 * of that wait is that it totals up to 100x whatever interval we 6390 * choose. Since our minimum wait is 100us we can just divide the 6391 * total timeout by 100 to get our minimum delay interval. 6392 */ 6393 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 6394 6395 wait_loop = IXGBE_MAX_RX_DESC_POLL; 6396 wait_delay = delay_interval; 6397 6398 while (wait_loop--) { 6399 usleep_range(wait_delay, wait_delay + 10); 6400 wait_delay += delay_interval * 2; 6401 rxdctl = 0; 6402 6403 /* OR together the reading of all the active RXDCTL registers, 6404 * and then test the result. We need the disable to complete 6405 * before we start freeing the memory and invalidating the 6406 * DMA mappings. 6407 */ 6408 for (i = 0; i < adapter->num_rx_queues; i++) { 6409 struct ixgbe_ring *ring = adapter->rx_ring[i]; 6410 u8 reg_idx = ring->reg_idx; 6411 6412 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 6413 } 6414 6415 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 6416 return; 6417 } 6418 6419 e_err(drv, 6420 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 6421 } 6422 6423 void ixgbe_disable_tx(struct ixgbe_adapter *adapter) 6424 { 6425 unsigned long wait_delay, delay_interval; 6426 struct ixgbe_hw *hw = &adapter->hw; 6427 int i, wait_loop; 6428 u32 txdctl; 6429 6430 if (ixgbe_removed(hw->hw_addr)) 6431 return; 6432 6433 /* disable all enabled Tx queues */ 6434 for (i = 0; i < adapter->num_tx_queues; i++) { 6435 struct ixgbe_ring *ring = adapter->tx_ring[i]; 6436 u8 reg_idx = ring->reg_idx; 6437 6438 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 6439 } 6440 6441 /* disable all enabled XDP Tx queues */ 6442 for (i = 0; i < adapter->num_xdp_queues; i++) { 6443 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 6444 u8 reg_idx = ring->reg_idx; 6445 6446 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 6447 } 6448 6449 /* If the link is not up there shouldn't be much in the way of 6450 * pending transactions. Those that are left will be flushed out 6451 * when the reset logic goes through the flush sequence to clean out 6452 * the pending Tx transactions. 6453 */ 6454 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 6455 goto dma_engine_disable; 6456 6457 /* Determine our minimum delay interval. We will increase this value 6458 * with each subsequent test. This way if the device returns quickly 6459 * we should spend as little time as possible waiting, however as 6460 * the time increases we will wait for larger periods of time. 6461 * 6462 * The trick here is that we increase the interval using the 6463 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result 6464 * of that wait is that it totals up to 100x whatever interval we 6465 * choose. Since our minimum wait is 100us we can just divide the 6466 * total timeout by 100 to get our minimum delay interval. 6467 */ 6468 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 6469 6470 wait_loop = IXGBE_MAX_RX_DESC_POLL; 6471 wait_delay = delay_interval; 6472 6473 while (wait_loop--) { 6474 usleep_range(wait_delay, wait_delay + 10); 6475 wait_delay += delay_interval * 2; 6476 txdctl = 0; 6477 6478 /* OR together the reading of all the active TXDCTL registers, 6479 * and then test the result. We need the disable to complete 6480 * before we start freeing the memory and invalidating the 6481 * DMA mappings. 6482 */ 6483 for (i = 0; i < adapter->num_tx_queues; i++) { 6484 struct ixgbe_ring *ring = adapter->tx_ring[i]; 6485 u8 reg_idx = ring->reg_idx; 6486 6487 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 6488 } 6489 for (i = 0; i < adapter->num_xdp_queues; i++) { 6490 struct ixgbe_ring *ring = adapter->xdp_ring[i]; 6491 u8 reg_idx = ring->reg_idx; 6492 6493 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 6494 } 6495 6496 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 6497 goto dma_engine_disable; 6498 } 6499 6500 e_err(drv, 6501 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n"); 6502 6503 dma_engine_disable: 6504 /* Disable the Tx DMA engine on 82599 and later MAC */ 6505 switch (hw->mac.type) { 6506 case ixgbe_mac_82599EB: 6507 case ixgbe_mac_X540: 6508 case ixgbe_mac_X550: 6509 case ixgbe_mac_X550EM_x: 6510 case ixgbe_mac_x550em_a: 6511 case ixgbe_mac_e610: 6512 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, 6513 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & 6514 ~IXGBE_DMATXCTL_TE)); 6515 fallthrough; 6516 default: 6517 break; 6518 } 6519 } 6520 6521 void ixgbe_reset(struct ixgbe_adapter *adapter) 6522 { 6523 struct ixgbe_hw *hw = &adapter->hw; 6524 struct net_device *netdev = adapter->netdev; 6525 int err; 6526 6527 if (ixgbe_removed(hw->hw_addr)) 6528 return; 6529 /* lock SFP init bit to prevent race conditions with the watchdog */ 6530 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 6531 usleep_range(1000, 2000); 6532 6533 /* clear all SFP and link config related flags while holding SFP_INIT */ 6534 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | 6535 IXGBE_FLAG2_SFP_NEEDS_RESET); 6536 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 6537 6538 err = hw->mac.ops.init_hw(hw); 6539 switch (err) { 6540 case 0: 6541 case -ENOENT: 6542 case -EOPNOTSUPP: 6543 break; 6544 case -EALREADY: 6545 e_dev_err("primary disable timed out\n"); 6546 break; 6547 case -EACCES: 6548 /* We are running on a pre-production device, log a warning */ 6549 e_dev_warn("This device is a pre-production adapter/LOM. " 6550 "Please be aware there may be issues associated with " 6551 "your hardware. If you are experiencing problems " 6552 "please contact your Intel or hardware " 6553 "representative who provided you with this " 6554 "hardware.\n"); 6555 break; 6556 default: 6557 e_dev_err("Hardware Error: %d\n", err); 6558 } 6559 6560 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 6561 6562 /* flush entries out of MAC table */ 6563 ixgbe_flush_sw_mac_table(adapter); 6564 __dev_uc_unsync(netdev, NULL); 6565 6566 /* do not flush user set addresses */ 6567 ixgbe_mac_set_default_filter(adapter); 6568 6569 /* update SAN MAC vmdq pool selection */ 6570 if (hw->mac.san_mac_rar_index) 6571 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 6572 6573 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 6574 ixgbe_ptp_reset(adapter); 6575 6576 if (hw->phy.ops.set_phy_power) { 6577 if (!netif_running(adapter->netdev) && !adapter->wol) 6578 hw->phy.ops.set_phy_power(hw, false); 6579 else 6580 hw->phy.ops.set_phy_power(hw, true); 6581 } 6582 } 6583 6584 /** 6585 * ixgbe_clean_tx_ring - Free Tx Buffers 6586 * @tx_ring: ring to be cleaned 6587 **/ 6588 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) 6589 { 6590 u16 i = tx_ring->next_to_clean; 6591 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i]; 6592 6593 if (tx_ring->xsk_pool) { 6594 ixgbe_xsk_clean_tx_ring(tx_ring); 6595 goto out; 6596 } 6597 6598 while (i != tx_ring->next_to_use) { 6599 union ixgbe_adv_tx_desc *eop_desc, *tx_desc; 6600 6601 /* Free all the Tx ring sk_buffs */ 6602 if (ring_is_xdp(tx_ring)) 6603 xdp_return_frame(tx_buffer->xdpf); 6604 else 6605 dev_kfree_skb_any(tx_buffer->skb); 6606 6607 /* unmap skb header data */ 6608 dma_unmap_single(tx_ring->dev, 6609 dma_unmap_addr(tx_buffer, dma), 6610 dma_unmap_len(tx_buffer, len), 6611 DMA_TO_DEVICE); 6612 6613 /* check for eop_desc to determine the end of the packet */ 6614 eop_desc = tx_buffer->next_to_watch; 6615 tx_desc = IXGBE_TX_DESC(tx_ring, i); 6616 6617 /* unmap remaining buffers */ 6618 while (tx_desc != eop_desc) { 6619 tx_buffer++; 6620 tx_desc++; 6621 i++; 6622 if (unlikely(i == tx_ring->count)) { 6623 i = 0; 6624 tx_buffer = tx_ring->tx_buffer_info; 6625 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 6626 } 6627 6628 /* unmap any remaining paged data */ 6629 if (dma_unmap_len(tx_buffer, len)) 6630 dma_unmap_page(tx_ring->dev, 6631 dma_unmap_addr(tx_buffer, dma), 6632 dma_unmap_len(tx_buffer, len), 6633 DMA_TO_DEVICE); 6634 } 6635 6636 /* move us one more past the eop_desc for start of next pkt */ 6637 tx_buffer++; 6638 i++; 6639 if (unlikely(i == tx_ring->count)) { 6640 i = 0; 6641 tx_buffer = tx_ring->tx_buffer_info; 6642 } 6643 } 6644 6645 /* reset BQL for queue */ 6646 if (!ring_is_xdp(tx_ring)) 6647 netdev_tx_reset_queue(txring_txq(tx_ring)); 6648 6649 out: 6650 /* reset next_to_use and next_to_clean */ 6651 tx_ring->next_to_use = 0; 6652 tx_ring->next_to_clean = 0; 6653 } 6654 6655 /** 6656 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues 6657 * @adapter: board private structure 6658 **/ 6659 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) 6660 { 6661 int i; 6662 6663 for (i = 0; i < adapter->num_rx_queues; i++) 6664 ixgbe_clean_rx_ring(adapter->rx_ring[i]); 6665 } 6666 6667 /** 6668 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues 6669 * @adapter: board private structure 6670 **/ 6671 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) 6672 { 6673 int i; 6674 6675 for (i = 0; i < adapter->num_tx_queues; i++) 6676 ixgbe_clean_tx_ring(adapter->tx_ring[i]); 6677 for (i = 0; i < adapter->num_xdp_queues; i++) 6678 ixgbe_clean_tx_ring(adapter->xdp_ring[i]); 6679 } 6680 6681 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) 6682 { 6683 struct hlist_node *node2; 6684 struct ixgbe_fdir_filter *filter; 6685 6686 spin_lock(&adapter->fdir_perfect_lock); 6687 6688 hlist_for_each_entry_safe(filter, node2, 6689 &adapter->fdir_filter_list, fdir_node) { 6690 hlist_del(&filter->fdir_node); 6691 kfree(filter); 6692 } 6693 adapter->fdir_filter_count = 0; 6694 6695 spin_unlock(&adapter->fdir_perfect_lock); 6696 } 6697 6698 void ixgbe_down(struct ixgbe_adapter *adapter) 6699 { 6700 struct net_device *netdev = adapter->netdev; 6701 struct ixgbe_hw *hw = &adapter->hw; 6702 int i; 6703 6704 /* signal that we are down to the interrupt handler */ 6705 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) 6706 return; /* do nothing if already down */ 6707 6708 /* Shut off incoming Tx traffic */ 6709 netif_tx_stop_all_queues(netdev); 6710 6711 /* call carrier off first to avoid false dev_watchdog timeouts */ 6712 netif_carrier_off(netdev); 6713 netif_tx_disable(netdev); 6714 6715 /* Disable Rx */ 6716 ixgbe_disable_rx(adapter); 6717 6718 /* synchronize_rcu() needed for pending XDP buffers to drain */ 6719 if (adapter->xdp_ring[0]) 6720 synchronize_rcu(); 6721 6722 ixgbe_irq_disable(adapter); 6723 6724 ixgbe_napi_disable_all(adapter); 6725 6726 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 6727 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 6728 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 6729 6730 timer_delete_sync(&adapter->service_timer); 6731 6732 if (adapter->num_vfs) { 6733 /* Clear EITR Select mapping */ 6734 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); 6735 6736 /* Mark all the VFs as inactive */ 6737 for (i = 0 ; i < adapter->num_vfs; i++) 6738 adapter->vfinfo[i].clear_to_send = false; 6739 6740 /* update setting rx tx for all active vfs */ 6741 ixgbe_set_all_vfs(adapter); 6742 } 6743 6744 /* disable transmits in the hardware now that interrupts are off */ 6745 ixgbe_disable_tx(adapter); 6746 6747 if (!pci_channel_offline(adapter->pdev)) 6748 ixgbe_reset(adapter); 6749 6750 /* power down the optics for 82599 SFP+ fiber */ 6751 if (hw->mac.ops.disable_tx_laser) 6752 hw->mac.ops.disable_tx_laser(hw); 6753 6754 ixgbe_clean_all_tx_rings(adapter); 6755 ixgbe_clean_all_rx_rings(adapter); 6756 if (adapter->hw.mac.type == ixgbe_mac_e610) 6757 ixgbe_disable_link_status_events(adapter); 6758 } 6759 6760 /** 6761 * ixgbe_set_eee_capable - helper function to determine EEE support on X550 6762 * and E610 6763 * @adapter: board private structure 6764 */ 6765 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter) 6766 { 6767 struct ixgbe_hw *hw = &adapter->hw; 6768 6769 switch (hw->device_id) { 6770 case IXGBE_DEV_ID_X550EM_A_1G_T: 6771 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6772 if (!hw->phy.eee_speeds_supported) 6773 break; 6774 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6775 if (!hw->phy.eee_speeds_advertised) 6776 break; 6777 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6778 break; 6779 case IXGBE_DEV_ID_E610_BACKPLANE: 6780 case IXGBE_DEV_ID_E610_SFP: 6781 case IXGBE_DEV_ID_E610_10G_T: 6782 case IXGBE_DEV_ID_E610_2_5G_T: 6783 if (hw->dev_caps.common_cap.eee_support && 6784 hw->phy.eee_speeds_supported) { 6785 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE; 6786 /* For E610 adapters EEE should be enabled by default 6787 * if the feature is supported by FW. 6788 */ 6789 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED; 6790 break; 6791 } 6792 fallthrough; 6793 default: 6794 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE; 6795 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED; 6796 break; 6797 } 6798 } 6799 6800 /** 6801 * ixgbe_tx_timeout - Respond to a Tx Hang 6802 * @netdev: network interface device structure 6803 * @txqueue: queue number that timed out 6804 **/ 6805 static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue) 6806 { 6807 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 6808 6809 /* Do the reset outside of interrupt context */ 6810 ixgbe_tx_timeout_reset(adapter); 6811 } 6812 6813 #ifdef CONFIG_IXGBE_DCB 6814 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) 6815 { 6816 struct ixgbe_hw *hw = &adapter->hw; 6817 struct tc_configuration *tc; 6818 int j; 6819 6820 switch (hw->mac.type) { 6821 case ixgbe_mac_82598EB: 6822 case ixgbe_mac_82599EB: 6823 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; 6824 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; 6825 break; 6826 case ixgbe_mac_X540: 6827 case ixgbe_mac_X550: 6828 case ixgbe_mac_e610: 6829 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; 6830 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; 6831 break; 6832 case ixgbe_mac_X550EM_x: 6833 case ixgbe_mac_x550em_a: 6834 default: 6835 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; 6836 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; 6837 break; 6838 } 6839 6840 /* Configure DCB traffic classes */ 6841 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { 6842 tc = &adapter->dcb_cfg.tc_config[j]; 6843 tc->path[DCB_TX_CONFIG].bwg_id = 0; 6844 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); 6845 tc->path[DCB_RX_CONFIG].bwg_id = 0; 6846 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); 6847 tc->dcb_pfc = pfc_disabled; 6848 } 6849 6850 /* Initialize default user to priority mapping, UPx->TC0 */ 6851 tc = &adapter->dcb_cfg.tc_config[0]; 6852 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 6853 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 6854 6855 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; 6856 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; 6857 adapter->dcb_cfg.pfc_mode_enable = false; 6858 adapter->dcb_set_bitmap = 0x00; 6859 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 6860 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; 6861 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, 6862 sizeof(adapter->temp_dcb_cfg)); 6863 } 6864 #endif 6865 6866 /** 6867 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 6868 * @adapter: board private structure to initialize 6869 * @ii: pointer to ixgbe_info for device 6870 * 6871 * ixgbe_sw_init initializes the Adapter private data structure. 6872 * Fields are initialized based on PCI device information and 6873 * OS network device settings (MTU size). 6874 **/ 6875 static int ixgbe_sw_init(struct ixgbe_adapter *adapter, 6876 const struct ixgbe_info *ii) 6877 { 6878 struct ixgbe_hw *hw = &adapter->hw; 6879 struct pci_dev *pdev = adapter->pdev; 6880 unsigned int rss, fdir; 6881 u32 fwsm; 6882 int i; 6883 6884 /* PCI config space info */ 6885 6886 hw->vendor_id = pdev->vendor; 6887 hw->device_id = pdev->device; 6888 hw->revision_id = pdev->revision; 6889 hw->subsystem_vendor_id = pdev->subsystem_vendor; 6890 hw->subsystem_device_id = pdev->subsystem_device; 6891 6892 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 6893 6894 /* get_invariants needs the device IDs */ 6895 ii->get_invariants(hw); 6896 6897 /* Set common capability flags and settings */ 6898 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); 6899 adapter->ring_feature[RING_F_RSS].limit = rss; 6900 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; 6901 adapter->max_q_vectors = MAX_Q_VECTORS_82599; 6902 adapter->atr_sample_rate = 20; 6903 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); 6904 adapter->ring_feature[RING_F_FDIR].limit = fdir; 6905 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; 6906 adapter->ring_feature[RING_F_VMDQ].limit = 1; 6907 #ifdef CONFIG_IXGBE_DCA 6908 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; 6909 #endif 6910 #ifdef CONFIG_IXGBE_DCB 6911 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; 6912 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 6913 #endif 6914 #ifdef IXGBE_FCOE 6915 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; 6916 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6917 #ifdef CONFIG_IXGBE_DCB 6918 /* Default traffic class to use for FCoE */ 6919 adapter->fcoe.up = IXGBE_FCOE_DEFTC; 6920 #endif /* CONFIG_IXGBE_DCB */ 6921 #endif /* IXGBE_FCOE */ 6922 6923 /* initialize static ixgbe jump table entries */ 6924 adapter->jump_tables[0] = kzalloc_obj(*adapter->jump_tables[0]); 6925 if (!adapter->jump_tables[0]) 6926 return -ENOMEM; 6927 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; 6928 6929 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) 6930 adapter->jump_tables[i] = NULL; 6931 6932 adapter->mac_table = kzalloc_objs(struct ixgbe_mac_addr, 6933 hw->mac.num_rar_entries); 6934 if (!adapter->mac_table) 6935 return -ENOMEM; 6936 6937 if (ixgbe_init_rss_key(adapter)) 6938 return -ENOMEM; 6939 6940 adapter->af_xdp_zc_qps = bitmap_zalloc(IXGBE_MAX_XDP_QS, GFP_KERNEL); 6941 if (!adapter->af_xdp_zc_qps) 6942 return -ENOMEM; 6943 6944 /* Set MAC specific capability flags and exceptions */ 6945 switch (hw->mac.type) { 6946 case ixgbe_mac_82598EB: 6947 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; 6948 6949 if (hw->device_id == IXGBE_DEV_ID_82598AT) 6950 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; 6951 6952 adapter->max_q_vectors = MAX_Q_VECTORS_82598; 6953 adapter->ring_feature[RING_F_FDIR].limit = 0; 6954 adapter->atr_sample_rate = 0; 6955 adapter->fdir_pballoc = 0; 6956 #ifdef IXGBE_FCOE 6957 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6958 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; 6959 #ifdef CONFIG_IXGBE_DCB 6960 adapter->fcoe.up = 0; 6961 #endif /* IXGBE_DCB */ 6962 #endif /* IXGBE_FCOE */ 6963 break; 6964 case ixgbe_mac_82599EB: 6965 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) 6966 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6967 break; 6968 case ixgbe_mac_X540: 6969 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 6970 if (fwsm & IXGBE_FWSM_TS_ENABLED) 6971 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6972 break; 6973 case ixgbe_mac_x550em_a: 6974 switch (hw->device_id) { 6975 case IXGBE_DEV_ID_X550EM_A_1G_T: 6976 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 6977 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6978 break; 6979 default: 6980 break; 6981 } 6982 fallthrough; 6983 case ixgbe_mac_X550EM_x: 6984 #ifdef CONFIG_IXGBE_DCB 6985 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; 6986 #endif 6987 #ifdef IXGBE_FCOE 6988 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 6989 #ifdef CONFIG_IXGBE_DCB 6990 adapter->fcoe.up = 0; 6991 #endif /* IXGBE_DCB */ 6992 #endif /* IXGBE_FCOE */ 6993 fallthrough; 6994 case ixgbe_mac_X550: 6995 if (hw->mac.type == ixgbe_mac_X550) 6996 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; 6997 #ifdef CONFIG_IXGBE_DCA 6998 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; 6999 #endif 7000 break; 7001 default: 7002 break; 7003 } 7004 7005 /* Make sure the SWFW semaphore is in a valid state */ 7006 if (hw->mac.ops.init_swfw_sync) 7007 hw->mac.ops.init_swfw_sync(hw); 7008 7009 if (hw->mac.type == ixgbe_mac_e610) 7010 mutex_init(&hw->aci.lock); 7011 7012 #ifdef IXGBE_FCOE 7013 /* FCoE support exists, always init the FCoE lock */ 7014 spin_lock_init(&adapter->fcoe.lock); 7015 7016 #endif 7017 /* n-tuple support exists, always init our spinlock */ 7018 spin_lock_init(&adapter->fdir_perfect_lock); 7019 7020 /* init spinlock to avoid concurrency of VF resources */ 7021 spin_lock_init(&adapter->vfs_lock); 7022 7023 #ifdef CONFIG_IXGBE_DCB 7024 ixgbe_init_dcb(adapter); 7025 #endif 7026 ixgbe_init_ipsec_offload(adapter); 7027 7028 /* default flow control settings */ 7029 hw->fc.requested_mode = ixgbe_fc_full; 7030 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ 7031 ixgbe_pbthresh_setup(adapter); 7032 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; 7033 hw->fc.send_xon = true; 7034 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); 7035 7036 #ifdef CONFIG_PCI_IOV 7037 if (max_vfs > 0) 7038 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); 7039 7040 /* assign number of SR-IOV VFs */ 7041 if (hw->mac.type != ixgbe_mac_82598EB) { 7042 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { 7043 max_vfs = 0; 7044 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); 7045 } 7046 } 7047 #endif /* CONFIG_PCI_IOV */ 7048 7049 /* enable itr by default in dynamic mode */ 7050 adapter->rx_itr_setting = 1; 7051 adapter->tx_itr_setting = 1; 7052 7053 /* set default ring sizes */ 7054 adapter->tx_ring_count = IXGBE_DEFAULT_TXD; 7055 adapter->rx_ring_count = IXGBE_DEFAULT_RXD; 7056 7057 /* set default work limits */ 7058 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; 7059 7060 /* initialize eeprom parameters */ 7061 if (hw->eeprom.ops.init_params(hw)) { 7062 e_dev_err("EEPROM initialization failed\n"); 7063 return -EIO; 7064 } 7065 7066 /* PF holds first pool slot */ 7067 set_bit(0, adapter->fwd_bitmask); 7068 set_bit(__IXGBE_DOWN, &adapter->state); 7069 7070 /* enable locking for XDP_TX if we have more CPUs than queues */ 7071 if (nr_cpu_ids > IXGBE_MAX_XDP_QS) 7072 static_branch_enable(&ixgbe_xdp_locking_key); 7073 7074 return 0; 7075 } 7076 7077 /** 7078 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) 7079 * @tx_ring: tx descriptor ring (for a specific queue) to setup 7080 * 7081 * Return 0 on success, negative on failure 7082 **/ 7083 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) 7084 { 7085 struct device *dev = tx_ring->dev; 7086 int orig_node = dev_to_node(dev); 7087 int ring_node = NUMA_NO_NODE; 7088 int size; 7089 7090 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; 7091 7092 if (tx_ring->q_vector) 7093 ring_node = tx_ring->q_vector->numa_node; 7094 7095 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node); 7096 if (!tx_ring->tx_buffer_info) 7097 tx_ring->tx_buffer_info = vmalloc(size); 7098 if (!tx_ring->tx_buffer_info) 7099 goto err; 7100 7101 /* round up to nearest 4K */ 7102 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); 7103 tx_ring->size = ALIGN(tx_ring->size, 4096); 7104 7105 set_dev_node(dev, ring_node); 7106 tx_ring->desc = dma_alloc_coherent(dev, 7107 tx_ring->size, 7108 &tx_ring->dma, 7109 GFP_KERNEL); 7110 set_dev_node(dev, orig_node); 7111 if (!tx_ring->desc) 7112 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 7113 &tx_ring->dma, GFP_KERNEL); 7114 if (!tx_ring->desc) 7115 goto err; 7116 7117 tx_ring->next_to_use = 0; 7118 tx_ring->next_to_clean = 0; 7119 return 0; 7120 7121 err: 7122 vfree(tx_ring->tx_buffer_info); 7123 tx_ring->tx_buffer_info = NULL; 7124 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 7125 return -ENOMEM; 7126 } 7127 7128 /** 7129 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources 7130 * @adapter: board private structure 7131 * 7132 * If this function returns with an error, then it's possible one or 7133 * more of the rings is populated (while the rest are not). It is the 7134 * callers duty to clean those orphaned rings. 7135 * 7136 * Return 0 on success, negative on failure 7137 **/ 7138 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) 7139 { 7140 int i, j = 0, err = 0; 7141 7142 for (i = 0; i < adapter->num_tx_queues; i++) { 7143 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); 7144 if (!err) 7145 continue; 7146 7147 e_err(probe, "Allocation for Tx Queue %u failed\n", i); 7148 goto err_setup_tx; 7149 } 7150 for (j = 0; j < adapter->num_xdp_queues; j++) { 7151 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]); 7152 if (!err) 7153 continue; 7154 7155 e_err(probe, "Allocation for Tx Queue %u failed\n", j); 7156 goto err_setup_tx; 7157 } 7158 7159 return 0; 7160 err_setup_tx: 7161 /* rewind the index freeing the rings as we go */ 7162 while (j--) 7163 ixgbe_free_tx_resources(adapter->xdp_ring[j]); 7164 while (i--) 7165 ixgbe_free_tx_resources(adapter->tx_ring[i]); 7166 return err; 7167 } 7168 7169 static int ixgbe_rx_napi_id(struct ixgbe_ring *rx_ring) 7170 { 7171 struct ixgbe_q_vector *q_vector = rx_ring->q_vector; 7172 7173 return q_vector ? q_vector->napi.napi_id : 0; 7174 } 7175 7176 /** 7177 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) 7178 * @adapter: pointer to ixgbe_adapter 7179 * @rx_ring: rx descriptor ring (for a specific queue) to setup 7180 * 7181 * Returns 0 on success, negative on failure 7182 **/ 7183 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter, 7184 struct ixgbe_ring *rx_ring) 7185 { 7186 struct device *dev = rx_ring->dev; 7187 int orig_node = dev_to_node(dev); 7188 int ring_node = NUMA_NO_NODE; 7189 int size; 7190 7191 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; 7192 7193 if (rx_ring->q_vector) 7194 ring_node = rx_ring->q_vector->numa_node; 7195 7196 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node); 7197 if (!rx_ring->rx_buffer_info) 7198 rx_ring->rx_buffer_info = vmalloc(size); 7199 if (!rx_ring->rx_buffer_info) 7200 goto err; 7201 7202 /* Round up to nearest 4K */ 7203 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); 7204 rx_ring->size = ALIGN(rx_ring->size, 4096); 7205 7206 set_dev_node(dev, ring_node); 7207 rx_ring->desc = dma_alloc_coherent(dev, 7208 rx_ring->size, 7209 &rx_ring->dma, 7210 GFP_KERNEL); 7211 set_dev_node(dev, orig_node); 7212 if (!rx_ring->desc) 7213 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 7214 &rx_ring->dma, GFP_KERNEL); 7215 if (!rx_ring->desc) 7216 goto err; 7217 7218 rx_ring->next_to_clean = 0; 7219 rx_ring->next_to_use = 0; 7220 7221 /* XDP RX-queue info */ 7222 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev, 7223 rx_ring->queue_index, ixgbe_rx_napi_id(rx_ring)) < 0) 7224 goto err; 7225 7226 WRITE_ONCE(rx_ring->xdp_prog, adapter->xdp_prog); 7227 7228 return 0; 7229 err: 7230 vfree(rx_ring->rx_buffer_info); 7231 rx_ring->rx_buffer_info = NULL; 7232 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 7233 return -ENOMEM; 7234 } 7235 7236 /** 7237 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources 7238 * @adapter: board private structure 7239 * 7240 * If this function returns with an error, then it's possible one or 7241 * more of the rings is populated (while the rest are not). It is the 7242 * callers duty to clean those orphaned rings. 7243 * 7244 * Return 0 on success, negative on failure 7245 **/ 7246 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) 7247 { 7248 int i, err = 0; 7249 7250 for (i = 0; i < adapter->num_rx_queues; i++) { 7251 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]); 7252 if (!err) 7253 continue; 7254 7255 e_err(probe, "Allocation for Rx Queue %u failed\n", i); 7256 goto err_setup_rx; 7257 } 7258 7259 #ifdef IXGBE_FCOE 7260 err = ixgbe_setup_fcoe_ddp_resources(adapter); 7261 if (!err) 7262 #endif 7263 return 0; 7264 err_setup_rx: 7265 /* rewind the index freeing the rings as we go */ 7266 while (i--) 7267 ixgbe_free_rx_resources(adapter->rx_ring[i]); 7268 return err; 7269 } 7270 7271 /** 7272 * ixgbe_free_tx_resources - Free Tx Resources per Queue 7273 * @tx_ring: Tx descriptor ring for a specific queue 7274 * 7275 * Free all transmit software resources 7276 **/ 7277 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) 7278 { 7279 ixgbe_clean_tx_ring(tx_ring); 7280 7281 vfree(tx_ring->tx_buffer_info); 7282 tx_ring->tx_buffer_info = NULL; 7283 7284 /* if not set, then don't free */ 7285 if (!tx_ring->desc) 7286 return; 7287 7288 dma_free_coherent(tx_ring->dev, tx_ring->size, 7289 tx_ring->desc, tx_ring->dma); 7290 7291 tx_ring->desc = NULL; 7292 } 7293 7294 /** 7295 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues 7296 * @adapter: board private structure 7297 * 7298 * Free all transmit software resources 7299 **/ 7300 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) 7301 { 7302 int i; 7303 7304 for (i = 0; i < adapter->num_tx_queues; i++) 7305 if (adapter->tx_ring[i]->desc) 7306 ixgbe_free_tx_resources(adapter->tx_ring[i]); 7307 for (i = 0; i < adapter->num_xdp_queues; i++) 7308 if (adapter->xdp_ring[i]->desc) 7309 ixgbe_free_tx_resources(adapter->xdp_ring[i]); 7310 } 7311 7312 /** 7313 * ixgbe_free_rx_resources - Free Rx Resources 7314 * @rx_ring: ring to clean the resources from 7315 * 7316 * Free all receive software resources 7317 **/ 7318 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) 7319 { 7320 ixgbe_clean_rx_ring(rx_ring); 7321 7322 rx_ring->xdp_prog = NULL; 7323 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 7324 vfree(rx_ring->rx_buffer_info); 7325 rx_ring->rx_buffer_info = NULL; 7326 7327 /* if not set, then don't free */ 7328 if (!rx_ring->desc) 7329 return; 7330 7331 dma_free_coherent(rx_ring->dev, rx_ring->size, 7332 rx_ring->desc, rx_ring->dma); 7333 7334 rx_ring->desc = NULL; 7335 } 7336 7337 /** 7338 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues 7339 * @adapter: board private structure 7340 * 7341 * Free all receive software resources 7342 **/ 7343 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) 7344 { 7345 int i; 7346 7347 #ifdef IXGBE_FCOE 7348 ixgbe_free_fcoe_ddp_resources(adapter); 7349 7350 #endif 7351 for (i = 0; i < adapter->num_rx_queues; i++) 7352 if (adapter->rx_ring[i]->desc) 7353 ixgbe_free_rx_resources(adapter->rx_ring[i]); 7354 } 7355 7356 /** 7357 * ixgbe_max_xdp_frame_size - returns the maximum allowed frame size for XDP 7358 * @adapter: device handle, pointer to adapter 7359 */ 7360 static int ixgbe_max_xdp_frame_size(struct ixgbe_adapter *adapter) 7361 { 7362 if (PAGE_SIZE >= 8192 || adapter->flags2 & IXGBE_FLAG2_RX_LEGACY) 7363 return IXGBE_RXBUFFER_2K; 7364 else 7365 return IXGBE_RXBUFFER_3K; 7366 } 7367 7368 /** 7369 * ixgbe_change_mtu - Change the Maximum Transfer Unit 7370 * @netdev: network interface device structure 7371 * @new_mtu: new value for maximum frame size 7372 * 7373 * Returns 0 on success, negative on failure 7374 **/ 7375 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) 7376 { 7377 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 7378 7379 if (ixgbe_enabled_xdp_adapter(adapter)) { 7380 int new_frame_size = new_mtu + IXGBE_PKT_HDR_PAD; 7381 7382 if (new_frame_size > ixgbe_max_xdp_frame_size(adapter)) { 7383 e_warn(probe, "Requested MTU size is not supported with XDP\n"); 7384 return -EINVAL; 7385 } 7386 } 7387 7388 /* 7389 * For 82599EB we cannot allow legacy VFs to enable their receive 7390 * paths when MTU greater than 1500 is configured. So display a 7391 * warning that legacy VFs will be disabled. 7392 */ 7393 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && 7394 (adapter->hw.mac.type == ixgbe_mac_82599EB) && 7395 (new_mtu > ETH_DATA_LEN)) 7396 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); 7397 7398 netdev_dbg(netdev, "changing MTU from %d to %d\n", 7399 netdev->mtu, new_mtu); 7400 7401 /* must set new MTU before calling down or up */ 7402 WRITE_ONCE(netdev->mtu, new_mtu); 7403 7404 if (netif_running(netdev)) 7405 ixgbe_reinit_locked(adapter); 7406 7407 return 0; 7408 } 7409 7410 /** 7411 * ixgbe_open - Called when a network interface is made active 7412 * @netdev: network interface device structure 7413 * 7414 * Returns 0 on success, negative value on failure 7415 * 7416 * The open entry point is called when a network interface is made 7417 * active by the system (IFF_UP). At this point all resources needed 7418 * for transmit and receive operations are allocated, the interrupt 7419 * handler is registered with the OS, the watchdog timer is started, 7420 * and the stack is notified that the interface is ready. 7421 **/ 7422 int ixgbe_open(struct net_device *netdev) 7423 { 7424 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 7425 struct ixgbe_hw *hw = &adapter->hw; 7426 int err, queues; 7427 7428 /* disallow open during test */ 7429 if (test_bit(__IXGBE_TESTING, &adapter->state)) 7430 return -EBUSY; 7431 7432 netif_carrier_off(netdev); 7433 7434 /* allocate transmit descriptors */ 7435 err = ixgbe_setup_all_tx_resources(adapter); 7436 if (err) 7437 goto err_setup_tx; 7438 7439 /* allocate receive descriptors */ 7440 err = ixgbe_setup_all_rx_resources(adapter); 7441 if (err) 7442 goto err_setup_rx; 7443 7444 ixgbe_configure(adapter); 7445 7446 err = ixgbe_request_irq(adapter); 7447 if (err) 7448 goto err_req_irq; 7449 7450 /* Notify the stack of the actual queue counts. */ 7451 queues = adapter->num_tx_queues; 7452 err = netif_set_real_num_tx_queues(netdev, queues); 7453 if (err) 7454 goto err_set_queues; 7455 7456 queues = adapter->num_rx_queues; 7457 err = netif_set_real_num_rx_queues(netdev, queues); 7458 if (err) 7459 goto err_set_queues; 7460 7461 ixgbe_ptp_init(adapter); 7462 7463 ixgbe_up_complete(adapter); 7464 7465 udp_tunnel_nic_reset_ntf(netdev); 7466 if (adapter->hw.mac.type == ixgbe_mac_e610) { 7467 int err = ixgbe_update_link_info(&adapter->hw); 7468 7469 if (err) 7470 e_dev_err("Failed to update link info, err %d.\n", err); 7471 7472 ixgbe_check_link_cfg_err(adapter, 7473 adapter->hw.link.link_info.link_cfg_err); 7474 7475 err = ixgbe_non_sfp_link_config(&adapter->hw); 7476 if (err) 7477 e_dev_err("Link setup failed, err %d.\n", err); 7478 } 7479 7480 return 0; 7481 7482 err_set_queues: 7483 ixgbe_free_irq(adapter); 7484 err_req_irq: 7485 ixgbe_free_all_rx_resources(adapter); 7486 if (hw->phy.ops.set_phy_power && !adapter->wol) 7487 hw->phy.ops.set_phy_power(&adapter->hw, false); 7488 err_setup_rx: 7489 ixgbe_free_all_tx_resources(adapter); 7490 err_setup_tx: 7491 ixgbe_reset(adapter); 7492 7493 return err; 7494 } 7495 7496 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) 7497 { 7498 ixgbe_ptp_suspend(adapter); 7499 7500 if (adapter->hw.phy.ops.enter_lplu) { 7501 adapter->hw.phy.reset_disable = true; 7502 ixgbe_down(adapter); 7503 adapter->hw.phy.ops.enter_lplu(&adapter->hw); 7504 adapter->hw.phy.reset_disable = false; 7505 } else { 7506 ixgbe_down(adapter); 7507 } 7508 7509 ixgbe_free_irq(adapter); 7510 7511 ixgbe_free_all_tx_resources(adapter); 7512 ixgbe_free_all_rx_resources(adapter); 7513 } 7514 7515 /** 7516 * ixgbe_close - Disables a network interface 7517 * @netdev: network interface device structure 7518 * 7519 * Returns 0, this is not allowed to fail 7520 * 7521 * The close entry point is called when an interface is de-activated 7522 * by the OS. The hardware is still under the drivers control, but 7523 * needs to be disabled. A global MAC reset is issued to stop the 7524 * hardware, and all transmit and receive resources are freed. 7525 **/ 7526 int ixgbe_close(struct net_device *netdev) 7527 { 7528 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 7529 7530 ixgbe_ptp_stop(adapter); 7531 7532 if (netif_device_present(netdev)) 7533 ixgbe_close_suspend(adapter); 7534 7535 ixgbe_fdir_filter_exit(adapter); 7536 7537 ixgbe_release_hw_control(adapter); 7538 7539 return 0; 7540 } 7541 7542 static int ixgbe_resume(struct device *dev_d) 7543 { 7544 struct pci_dev *pdev = to_pci_dev(dev_d); 7545 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 7546 struct net_device *netdev = adapter->netdev; 7547 u32 err; 7548 7549 adapter->hw.hw_addr = adapter->io_addr; 7550 7551 err = pci_enable_device_mem(pdev); 7552 if (err) { 7553 e_dev_err("Cannot enable PCI device from suspend\n"); 7554 return err; 7555 } 7556 smp_mb__before_atomic(); 7557 clear_bit(__IXGBE_DISABLED, &adapter->state); 7558 pci_set_master(pdev); 7559 7560 device_wakeup_disable(dev_d); 7561 7562 ixgbe_reset(adapter); 7563 7564 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 7565 7566 rtnl_lock(); 7567 err = ixgbe_init_interrupt_scheme(adapter); 7568 if (!err && netif_running(netdev)) 7569 err = ixgbe_open(netdev); 7570 7571 7572 if (!err) 7573 netif_device_attach(netdev); 7574 rtnl_unlock(); 7575 7576 return err; 7577 } 7578 7579 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) 7580 { 7581 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 7582 struct net_device *netdev = adapter->netdev; 7583 struct ixgbe_hw *hw = &adapter->hw; 7584 u32 ctrl; 7585 u32 wufc = adapter->wol; 7586 7587 rtnl_lock(); 7588 netif_device_detach(netdev); 7589 7590 if (netif_running(netdev)) 7591 ixgbe_close_suspend(adapter); 7592 7593 ixgbe_clear_interrupt_scheme(adapter); 7594 rtnl_unlock(); 7595 7596 if (hw->mac.ops.stop_link_on_d3) 7597 hw->mac.ops.stop_link_on_d3(hw); 7598 7599 if (wufc) { 7600 u32 fctrl; 7601 7602 ixgbe_set_rx_mode(netdev); 7603 7604 /* enable the optics for 82599 SFP+ fiber as we can WoL */ 7605 if (hw->mac.ops.enable_tx_laser) 7606 hw->mac.ops.enable_tx_laser(hw); 7607 7608 /* enable the reception of multicast packets */ 7609 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 7610 fctrl |= IXGBE_FCTRL_MPE; 7611 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 7612 7613 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 7614 ctrl |= IXGBE_CTRL_GIO_DIS; 7615 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 7616 7617 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); 7618 } else { 7619 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); 7620 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); 7621 } 7622 7623 switch (hw->mac.type) { 7624 case ixgbe_mac_82598EB: 7625 pci_wake_from_d3(pdev, false); 7626 break; 7627 case ixgbe_mac_82599EB: 7628 case ixgbe_mac_X540: 7629 case ixgbe_mac_X550: 7630 case ixgbe_mac_X550EM_x: 7631 case ixgbe_mac_x550em_a: 7632 case ixgbe_mac_e610: 7633 pci_wake_from_d3(pdev, !!wufc); 7634 break; 7635 default: 7636 break; 7637 } 7638 7639 *enable_wake = !!wufc; 7640 if (hw->phy.ops.set_phy_power && !*enable_wake) 7641 hw->phy.ops.set_phy_power(hw, false); 7642 7643 ixgbe_release_hw_control(adapter); 7644 7645 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 7646 pci_disable_device(pdev); 7647 7648 return 0; 7649 } 7650 7651 static int ixgbe_suspend(struct device *dev_d) 7652 { 7653 struct pci_dev *pdev = to_pci_dev(dev_d); 7654 int retval; 7655 bool wake; 7656 7657 retval = __ixgbe_shutdown(pdev, &wake); 7658 7659 device_set_wakeup_enable(dev_d, wake); 7660 7661 return retval; 7662 } 7663 7664 static void ixgbe_shutdown(struct pci_dev *pdev) 7665 { 7666 bool wake; 7667 7668 __ixgbe_shutdown(pdev, &wake); 7669 7670 if (system_state == SYSTEM_POWER_OFF) { 7671 pci_wake_from_d3(pdev, wake); 7672 pci_set_power_state(pdev, PCI_D3hot); 7673 } 7674 } 7675 7676 /** 7677 * ixgbe_update_stats - Update the board statistics counters. 7678 * @adapter: board private structure 7679 **/ 7680 void ixgbe_update_stats(struct ixgbe_adapter *adapter) 7681 { 7682 struct net_device *netdev = adapter->netdev; 7683 struct ixgbe_hw *hw = &adapter->hw; 7684 struct ixgbe_hw_stats *hwstats = &adapter->stats; 7685 u64 total_mpc = 0; 7686 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; 7687 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; 7688 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; 7689 u64 alloc_rx_page = 0; 7690 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; 7691 7692 if (test_bit(__IXGBE_DOWN, &adapter->state) || 7693 test_bit(__IXGBE_RESETTING, &adapter->state)) 7694 return; 7695 7696 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { 7697 u64 rsc_count = 0; 7698 u64 rsc_flush = 0; 7699 for (i = 0; i < adapter->num_rx_queues; i++) { 7700 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; 7701 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; 7702 } 7703 adapter->rsc_total_count = rsc_count; 7704 adapter->rsc_total_flush = rsc_flush; 7705 } 7706 7707 for (i = 0; i < adapter->num_rx_queues; i++) { 7708 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]); 7709 7710 if (!rx_ring) 7711 continue; 7712 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 7713 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page; 7714 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; 7715 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 7716 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 7717 bytes += rx_ring->stats.bytes; 7718 packets += rx_ring->stats.packets; 7719 } 7720 adapter->non_eop_descs = non_eop_descs; 7721 adapter->alloc_rx_page = alloc_rx_page; 7722 adapter->alloc_rx_page_failed = alloc_rx_page_failed; 7723 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; 7724 adapter->hw_csum_rx_error = hw_csum_rx_error; 7725 netdev->stats.rx_bytes = bytes; 7726 netdev->stats.rx_packets = packets; 7727 7728 bytes = 0; 7729 packets = 0; 7730 /* gather some stats to the adapter struct that are per queue */ 7731 for (i = 0; i < adapter->num_tx_queues; i++) { 7732 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]); 7733 7734 if (!tx_ring) 7735 continue; 7736 restart_queue += tx_ring->tx_stats.restart_queue; 7737 tx_busy += tx_ring->tx_stats.tx_busy; 7738 bytes += tx_ring->stats.bytes; 7739 packets += tx_ring->stats.packets; 7740 } 7741 for (i = 0; i < adapter->num_xdp_queues; i++) { 7742 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]); 7743 7744 if (!xdp_ring) 7745 continue; 7746 restart_queue += xdp_ring->tx_stats.restart_queue; 7747 tx_busy += xdp_ring->tx_stats.tx_busy; 7748 bytes += xdp_ring->stats.bytes; 7749 packets += xdp_ring->stats.packets; 7750 } 7751 adapter->restart_queue = restart_queue; 7752 adapter->tx_busy = tx_busy; 7753 netdev->stats.tx_bytes = bytes; 7754 netdev->stats.tx_packets = packets; 7755 7756 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 7757 7758 /* 8 register reads */ 7759 for (i = 0; i < 8; i++) { 7760 /* for packet buffers not used, the register should read 0 */ 7761 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 7762 missed_rx += mpc; 7763 hwstats->mpc[i] += mpc; 7764 total_mpc += hwstats->mpc[i]; 7765 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 7766 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 7767 switch (hw->mac.type) { 7768 case ixgbe_mac_82598EB: 7769 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 7770 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 7771 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 7772 hwstats->pxonrxc[i] += 7773 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 7774 break; 7775 case ixgbe_mac_82599EB: 7776 case ixgbe_mac_X540: 7777 case ixgbe_mac_X550: 7778 case ixgbe_mac_X550EM_x: 7779 case ixgbe_mac_x550em_a: 7780 case ixgbe_mac_e610: 7781 hwstats->pxonrxc[i] += 7782 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 7783 break; 7784 default: 7785 break; 7786 } 7787 } 7788 7789 /*16 register reads */ 7790 for (i = 0; i < 16; i++) { 7791 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 7792 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 7793 if (hw->mac.type == ixgbe_mac_82599EB || 7794 hw->mac.type == ixgbe_mac_X540 || 7795 hw->mac.type == ixgbe_mac_X550 || 7796 hw->mac.type == ixgbe_mac_X550EM_x || 7797 hw->mac.type == ixgbe_mac_x550em_a || 7798 hw->mac.type == ixgbe_mac_e610) { 7799 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 7800 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ 7801 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 7802 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ 7803 } 7804 } 7805 7806 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); 7807 /* work around hardware counting issue */ 7808 hwstats->gprc -= missed_rx; 7809 7810 ixgbe_update_xoff_received(adapter); 7811 7812 /* 82598 hardware only has a 32 bit counter in the high register */ 7813 switch (hw->mac.type) { 7814 case ixgbe_mac_82598EB: 7815 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 7816 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 7817 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 7818 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 7819 break; 7820 case ixgbe_mac_X540: 7821 case ixgbe_mac_X550: 7822 case ixgbe_mac_X550EM_x: 7823 case ixgbe_mac_x550em_a: 7824 case ixgbe_mac_e610: 7825 /* OS2BMC stats are X540 and later */ 7826 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); 7827 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); 7828 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); 7829 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); 7830 fallthrough; 7831 case ixgbe_mac_82599EB: 7832 for (i = 0; i < 16; i++) 7833 adapter->hw_rx_no_dma_resources += 7834 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 7835 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 7836 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ 7837 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 7838 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ 7839 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 7840 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ 7841 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 7842 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 7843 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 7844 #ifdef IXGBE_FCOE 7845 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 7846 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 7847 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 7848 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 7849 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 7850 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 7851 /* Add up per cpu counters for total ddp aloc fail */ 7852 if (adapter->fcoe.ddp_pool) { 7853 struct ixgbe_fcoe *fcoe = &adapter->fcoe; 7854 struct ixgbe_fcoe_ddp_pool *ddp_pool; 7855 unsigned int cpu; 7856 u64 noddp = 0, noddp_ext_buff = 0; 7857 for_each_possible_cpu(cpu) { 7858 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); 7859 noddp += ddp_pool->noddp; 7860 noddp_ext_buff += ddp_pool->noddp_ext_buff; 7861 } 7862 hwstats->fcoe_noddp = noddp; 7863 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; 7864 } 7865 #endif /* IXGBE_FCOE */ 7866 break; 7867 default: 7868 break; 7869 } 7870 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 7871 hwstats->bprc += bprc; 7872 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 7873 if (hw->mac.type == ixgbe_mac_82598EB) 7874 hwstats->mprc -= bprc; 7875 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 7876 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 7877 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 7878 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 7879 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 7880 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 7881 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 7882 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 7883 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 7884 hwstats->lxontxc += lxon; 7885 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 7886 hwstats->lxofftxc += lxoff; 7887 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); 7888 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 7889 /* 7890 * 82598 errata - tx of flow control packets is included in tx counters 7891 */ 7892 xon_off_tot = lxon + lxoff; 7893 hwstats->gptc -= xon_off_tot; 7894 hwstats->mptc -= xon_off_tot; 7895 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); 7896 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 7897 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 7898 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 7899 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 7900 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 7901 hwstats->ptc64 -= xon_off_tot; 7902 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 7903 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 7904 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 7905 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 7906 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 7907 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 7908 7909 /* Fill out the OS statistics structure */ 7910 netdev->stats.multicast = hwstats->mprc; 7911 7912 /* Rx Errors */ 7913 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; 7914 netdev->stats.rx_dropped = 0; 7915 netdev->stats.rx_length_errors = hwstats->rlec; 7916 netdev->stats.rx_crc_errors = hwstats->crcerrs; 7917 netdev->stats.rx_missed_errors = total_mpc; 7918 7919 /* VF Stats Collection - skip while resetting because these 7920 * are not clear on read and otherwise you'll sometimes get 7921 * crazy values. 7922 */ 7923 if (!test_bit(__IXGBE_RESETTING, &adapter->state)) { 7924 for (i = 0; i < adapter->num_vfs; i++) { 7925 UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPRC(i), 7926 adapter->vfinfo[i].last_vfstats.gprc, 7927 adapter->vfinfo[i].vfstats.gprc); 7928 UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPTC(i), 7929 adapter->vfinfo[i].last_vfstats.gptc, 7930 adapter->vfinfo[i].vfstats.gptc); 7931 UPDATE_VF_COUNTER_36bit(IXGBE_PVFGORC_LSB(i), 7932 IXGBE_PVFGORC_MSB(i), 7933 adapter->vfinfo[i].last_vfstats.gorc, 7934 adapter->vfinfo[i].vfstats.gorc); 7935 UPDATE_VF_COUNTER_36bit(IXGBE_PVFGOTC_LSB(i), 7936 IXGBE_PVFGOTC_MSB(i), 7937 adapter->vfinfo[i].last_vfstats.gotc, 7938 adapter->vfinfo[i].vfstats.gotc); 7939 UPDATE_VF_COUNTER_32bit(IXGBE_PVFMPRC(i), 7940 adapter->vfinfo[i].last_vfstats.mprc, 7941 adapter->vfinfo[i].vfstats.mprc); 7942 } 7943 } 7944 } 7945 7946 /** 7947 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table 7948 * @adapter: pointer to the device adapter structure 7949 **/ 7950 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) 7951 { 7952 struct ixgbe_hw *hw = &adapter->hw; 7953 int i; 7954 7955 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) 7956 return; 7957 7958 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; 7959 7960 /* if interface is down do nothing */ 7961 if (test_bit(__IXGBE_DOWN, &adapter->state)) 7962 return; 7963 7964 /* do nothing if we are not using signature filters */ 7965 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) 7966 return; 7967 7968 adapter->fdir_overflow++; 7969 7970 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { 7971 for (i = 0; i < adapter->num_tx_queues; i++) 7972 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7973 adapter->tx_ring[i]->state); 7974 for (i = 0; i < adapter->num_xdp_queues; i++) 7975 set_bit(__IXGBE_TX_FDIR_INIT_DONE, 7976 adapter->xdp_ring[i]->state); 7977 /* re-enable flow director interrupts */ 7978 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); 7979 } else { 7980 e_err(probe, "failed to finish FDIR re-initialization, " 7981 "ignored adding FDIR ATR filters\n"); 7982 } 7983 } 7984 7985 /** 7986 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts 7987 * @adapter: pointer to the device adapter structure 7988 * 7989 * This function serves two purposes. First it strobes the interrupt lines 7990 * in order to make certain interrupts are occurring. Secondly it sets the 7991 * bits needed to check for TX hangs. As a result we should immediately 7992 * determine if a hang has occurred. 7993 */ 7994 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) 7995 { 7996 struct ixgbe_hw *hw = &adapter->hw; 7997 u64 eics = 0; 7998 int i; 7999 8000 /* If we're down, removing or resetting, just bail */ 8001 if (test_bit(__IXGBE_DOWN, &adapter->state) || 8002 test_bit(__IXGBE_REMOVING, &adapter->state) || 8003 test_bit(__IXGBE_RESETTING, &adapter->state)) 8004 return; 8005 8006 /* Force detection of hung controller */ 8007 if (netif_carrier_ok(adapter->netdev)) 8008 for (i = 0; i < adapter->num_tx_queues; i++) 8009 set_check_for_tx_hang(adapter->tx_ring[i]); 8010 8011 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { 8012 /* 8013 * for legacy and MSI interrupts don't set any bits 8014 * that are enabled for EIAM, because this operation 8015 * would set *both* EIMS and EICS for any bit in EIAM 8016 */ 8017 IXGBE_WRITE_REG(hw, IXGBE_EICS, 8018 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); 8019 } else { 8020 /* get one bit for every active tx/rx interrupt vector */ 8021 for (i = 0; i < adapter->num_q_vectors; i++) { 8022 struct ixgbe_q_vector *qv = adapter->q_vector[i]; 8023 if (qv->rx.ring || qv->tx.ring) 8024 eics |= BIT_ULL(i); 8025 } 8026 } 8027 8028 /* Cause software interrupt to ensure rings are cleaned */ 8029 ixgbe_irq_rearm_queues(adapter, eics); 8030 } 8031 8032 /** 8033 * ixgbe_watchdog_update_link - update the link status 8034 * @adapter: pointer to the device adapter structure 8035 **/ 8036 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) 8037 { 8038 struct ixgbe_hw *hw = &adapter->hw; 8039 u32 link_speed = adapter->link_speed; 8040 bool link_up = adapter->link_up; 8041 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; 8042 8043 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) 8044 return; 8045 8046 if (hw->mac.ops.check_link) { 8047 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 8048 } else { 8049 /* always assume link is up, if no check link function */ 8050 link_speed = IXGBE_LINK_SPEED_10GB_FULL; 8051 link_up = true; 8052 } 8053 8054 if (adapter->ixgbe_ieee_pfc) 8055 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); 8056 8057 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { 8058 hw->mac.ops.fc_enable(hw); 8059 ixgbe_set_rx_drop_en(adapter); 8060 } 8061 8062 if (link_up || 8063 time_after(jiffies, (adapter->link_check_timeout + 8064 IXGBE_TRY_LINK_TIMEOUT))) { 8065 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 8066 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); 8067 IXGBE_WRITE_FLUSH(hw); 8068 } 8069 8070 adapter->link_up = link_up; 8071 adapter->link_speed = link_speed; 8072 } 8073 8074 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) 8075 { 8076 #ifdef CONFIG_IXGBE_DCB 8077 struct net_device *netdev = adapter->netdev; 8078 struct dcb_app app = { 8079 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, 8080 .protocol = 0, 8081 }; 8082 u8 up = 0; 8083 8084 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) 8085 up = dcb_ieee_getapp_mask(netdev, &app); 8086 8087 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; 8088 #endif 8089 } 8090 8091 /** 8092 * ixgbe_watchdog_link_is_up - update netif_carrier status and 8093 * print link up message 8094 * @adapter: pointer to the device adapter structure 8095 **/ 8096 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) 8097 { 8098 struct net_device *netdev = adapter->netdev; 8099 struct ixgbe_hw *hw = &adapter->hw; 8100 u32 link_speed = adapter->link_speed; 8101 struct ethtool_keee keee = {}; 8102 const char *speed_str; 8103 bool flow_rx, flow_tx; 8104 8105 /* only continue if link was previously down */ 8106 if (netif_carrier_ok(netdev)) 8107 return; 8108 8109 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 8110 8111 switch (hw->mac.type) { 8112 case ixgbe_mac_82598EB: { 8113 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 8114 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); 8115 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); 8116 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); 8117 } 8118 break; 8119 case ixgbe_mac_X540: 8120 case ixgbe_mac_X550: 8121 case ixgbe_mac_X550EM_x: 8122 case ixgbe_mac_x550em_a: 8123 case ixgbe_mac_e610: 8124 case ixgbe_mac_82599EB: { 8125 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 8126 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 8127 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); 8128 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); 8129 } 8130 break; 8131 default: 8132 flow_tx = false; 8133 flow_rx = false; 8134 break; 8135 } 8136 8137 adapter->last_rx_ptp_check = jiffies; 8138 8139 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 8140 ixgbe_ptp_start_cyclecounter(adapter); 8141 8142 netdev->ethtool_ops->get_eee(netdev, &keee); 8143 8144 switch (link_speed) { 8145 case IXGBE_LINK_SPEED_10GB_FULL: 8146 speed_str = "10 Gbps"; 8147 break; 8148 case IXGBE_LINK_SPEED_5GB_FULL: 8149 speed_str = "5 Gbps"; 8150 break; 8151 case IXGBE_LINK_SPEED_2_5GB_FULL: 8152 speed_str = "2.5 Gbps"; 8153 break; 8154 case IXGBE_LINK_SPEED_1GB_FULL: 8155 speed_str = "1 Gbps"; 8156 break; 8157 case IXGBE_LINK_SPEED_100_FULL: 8158 speed_str = "100 Mbps"; 8159 break; 8160 case IXGBE_LINK_SPEED_10_FULL: 8161 speed_str = "10 Mbps"; 8162 break; 8163 default: 8164 speed_str = "unknown speed"; 8165 break; 8166 } 8167 e_info(drv, "NIC Link is Up %s, Flow Control: %s, EEE: %s\n", speed_str, 8168 ((flow_rx && flow_tx) ? "RX/TX" : 8169 (flow_rx ? "RX" : 8170 (flow_tx ? "TX" : "None"))), 8171 str_on_off(keee.eee_enabled)); 8172 8173 netif_carrier_on(netdev); 8174 ixgbe_check_vf_rate_limit(adapter); 8175 8176 if (adapter->num_vfs && hw->mac.ops.enable_mdd) 8177 hw->mac.ops.enable_mdd(hw); 8178 8179 /* enable transmits */ 8180 netif_tx_wake_all_queues(adapter->netdev); 8181 8182 /* update the default user priority for VFs */ 8183 ixgbe_update_default_up(adapter); 8184 8185 /* ping all the active vfs to let them know link has changed */ 8186 ixgbe_ping_all_vfs(adapter); 8187 } 8188 8189 /** 8190 * ixgbe_watchdog_link_is_down - update netif_carrier status and 8191 * print link down message 8192 * @adapter: pointer to the adapter structure 8193 **/ 8194 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) 8195 { 8196 struct net_device *netdev = adapter->netdev; 8197 struct ixgbe_hw *hw = &adapter->hw; 8198 8199 adapter->link_up = false; 8200 adapter->link_speed = 0; 8201 8202 /* only continue if link was up previously */ 8203 if (!netif_carrier_ok(netdev)) 8204 return; 8205 8206 adapter->link_down_events++; 8207 8208 /* poll for SFP+ cable when link is down */ 8209 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) 8210 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; 8211 8212 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 8213 ixgbe_ptp_start_cyclecounter(adapter); 8214 8215 e_info(drv, "NIC Link is Down\n"); 8216 netif_carrier_off(netdev); 8217 8218 /* ping all the active vfs to let them know link has changed */ 8219 ixgbe_ping_all_vfs(adapter); 8220 } 8221 8222 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) 8223 { 8224 int i; 8225 8226 for (i = 0; i < adapter->num_tx_queues; i++) { 8227 struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; 8228 8229 if (tx_ring->next_to_use != tx_ring->next_to_clean) 8230 return true; 8231 } 8232 8233 return false; 8234 } 8235 8236 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) 8237 { 8238 struct ixgbe_hw *hw = &adapter->hw; 8239 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 8240 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); 8241 8242 int i, j; 8243 8244 if (!adapter->num_vfs) 8245 return false; 8246 8247 /* resetting the PF is only needed for MAC before X550 */ 8248 if (hw->mac.type >= ixgbe_mac_X550) 8249 return false; 8250 8251 for (i = 0; i < adapter->num_vfs; i++) { 8252 for (j = 0; j < q_per_pool; j++) { 8253 u32 h, t; 8254 8255 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); 8256 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); 8257 8258 if (h != t) 8259 return true; 8260 } 8261 } 8262 8263 return false; 8264 } 8265 8266 /** 8267 * ixgbe_watchdog_flush_tx - flush queues on link down 8268 * @adapter: pointer to the device adapter structure 8269 **/ 8270 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) 8271 { 8272 if (!netif_carrier_ok(adapter->netdev)) { 8273 if (ixgbe_ring_tx_pending(adapter) || 8274 ixgbe_vf_tx_pending(adapter)) { 8275 /* We've lost link, so the controller stops DMA, 8276 * but we've got queued Tx work that's never going 8277 * to get done, so reset controller to flush Tx. 8278 * (Do the reset outside of interrupt context). 8279 */ 8280 e_warn(drv, "initiating reset to clear Tx work after link loss\n"); 8281 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state); 8282 } 8283 } 8284 } 8285 8286 #ifdef CONFIG_PCI_IOV 8287 static void ixgbe_bad_vf_abort(struct ixgbe_adapter *adapter, u32 vf) 8288 { 8289 struct ixgbe_hw *hw = &adapter->hw; 8290 8291 if (adapter->hw.mac.type == ixgbe_mac_82599EB && 8292 adapter->flags2 & IXGBE_FLAG2_AUTO_DISABLE_VF) { 8293 adapter->vfinfo[vf].primary_abort_count++; 8294 if (adapter->vfinfo[vf].primary_abort_count == 8295 IXGBE_PRIMARY_ABORT_LIMIT) { 8296 ixgbe_set_vf_link_state(adapter, vf, 8297 IFLA_VF_LINK_STATE_DISABLE); 8298 adapter->vfinfo[vf].primary_abort_count = 0; 8299 8300 e_info(drv, 8301 "Malicious Driver Detection event detected on PF %d VF %d MAC: %pM mdd-disable-vf=on", 8302 hw->bus.func, vf, 8303 adapter->vfinfo[vf].vf_mac_addresses); 8304 } 8305 } 8306 } 8307 8308 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) 8309 { 8310 struct ixgbe_hw *hw = &adapter->hw; 8311 struct pci_dev *pdev = adapter->pdev; 8312 unsigned int vf; 8313 u32 gpc; 8314 8315 if (!(netif_carrier_ok(adapter->netdev))) 8316 return; 8317 8318 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); 8319 if (gpc) /* If incrementing then no need for the check below */ 8320 return; 8321 /* Check to see if a bad DMA write target from an errant or 8322 * malicious VF has caused a PCIe error. If so then we can 8323 * issue a VFLR to the offending VF(s) and then resume without 8324 * requesting a full slot reset. 8325 */ 8326 8327 if (!pdev) 8328 return; 8329 8330 /* check status reg for all VFs owned by this PF */ 8331 for (vf = 0; vf < adapter->num_vfs; ++vf) { 8332 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; 8333 u16 status_reg; 8334 8335 if (!vfdev) 8336 continue; 8337 pci_read_config_word(vfdev, PCI_STATUS, &status_reg); 8338 if (status_reg != IXGBE_FAILED_READ_CFG_WORD && 8339 status_reg & PCI_STATUS_REC_MASTER_ABORT) { 8340 ixgbe_bad_vf_abort(adapter, vf); 8341 pcie_flr(vfdev); 8342 } 8343 } 8344 } 8345 8346 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) 8347 { 8348 u32 ssvpc; 8349 8350 /* Do not perform spoof check for 82598 or if not in IOV mode */ 8351 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 8352 adapter->num_vfs == 0) 8353 return; 8354 8355 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); 8356 8357 /* 8358 * ssvpc register is cleared on read, if zero then no 8359 * spoofed packets in the last interval. 8360 */ 8361 if (!ssvpc) 8362 return; 8363 8364 e_warn(drv, "%u Spoofed packets detected\n", ssvpc); 8365 } 8366 #else 8367 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) 8368 { 8369 } 8370 8371 static void 8372 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) 8373 { 8374 } 8375 #endif /* CONFIG_PCI_IOV */ 8376 8377 8378 /** 8379 * ixgbe_watchdog_subtask - check and bring link up 8380 * @adapter: pointer to the device adapter structure 8381 **/ 8382 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) 8383 { 8384 /* if interface is down, removing or resetting, do nothing */ 8385 if (test_bit(__IXGBE_DOWN, &adapter->state) || 8386 test_bit(__IXGBE_REMOVING, &adapter->state) || 8387 test_bit(__IXGBE_RESETTING, &adapter->state)) 8388 return; 8389 8390 ixgbe_watchdog_update_link(adapter); 8391 8392 if (adapter->link_up) 8393 ixgbe_watchdog_link_is_up(adapter); 8394 else 8395 ixgbe_watchdog_link_is_down(adapter); 8396 8397 ixgbe_check_for_bad_vf(adapter); 8398 ixgbe_spoof_check(adapter); 8399 ixgbe_update_stats(adapter); 8400 8401 ixgbe_watchdog_flush_tx(adapter); 8402 } 8403 8404 /** 8405 * ixgbe_sfp_detection_subtask - poll for SFP+ cable 8406 * @adapter: the ixgbe adapter structure 8407 **/ 8408 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) 8409 { 8410 struct ixgbe_hw *hw = &adapter->hw; 8411 int err; 8412 8413 /* not searching for SFP so there is nothing to do here */ 8414 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && 8415 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 8416 return; 8417 8418 if (adapter->sfp_poll_time && 8419 time_after(adapter->sfp_poll_time, jiffies)) 8420 return; /* If not yet time to poll for SFP */ 8421 8422 /* someone else is in init, wait until next service event */ 8423 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 8424 return; 8425 8426 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; 8427 8428 err = hw->phy.ops.identify_sfp(hw); 8429 if (err == -EOPNOTSUPP) 8430 goto sfp_out; 8431 8432 if (err == -ENOENT) { 8433 /* If no cable is present, then we need to reset 8434 * the next time we find a good cable. */ 8435 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; 8436 } 8437 8438 /* exit on error */ 8439 if (err) 8440 goto sfp_out; 8441 8442 /* exit if reset not needed */ 8443 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) 8444 goto sfp_out; 8445 8446 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; 8447 8448 /* 8449 * A module may be identified correctly, but the EEPROM may not have 8450 * support for that module. setup_sfp() will fail in that case, so 8451 * we should not allow that module to load. 8452 */ 8453 if (hw->mac.type == ixgbe_mac_82598EB) 8454 err = hw->phy.ops.reset(hw); 8455 else 8456 err = hw->mac.ops.setup_sfp(hw); 8457 8458 if (err == -EOPNOTSUPP) 8459 goto sfp_out; 8460 8461 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 8462 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); 8463 8464 sfp_out: 8465 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 8466 8467 if (err == -EOPNOTSUPP && 8468 adapter->netdev->reg_state == NETREG_REGISTERED) { 8469 e_dev_err("failed to initialize because an unsupported " 8470 "SFP+ module type was detected.\n"); 8471 e_dev_err("Reload the driver after installing a " 8472 "supported module.\n"); 8473 unregister_netdev(adapter->netdev); 8474 } 8475 } 8476 8477 /** 8478 * ixgbe_sfp_link_config_subtask - set up link SFP after module install 8479 * @adapter: the ixgbe adapter structure 8480 **/ 8481 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) 8482 { 8483 struct ixgbe_hw *hw = &adapter->hw; 8484 u32 cap_speed; 8485 u32 speed; 8486 bool autoneg = false; 8487 8488 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) 8489 return; 8490 8491 /* someone else is in init, wait until next service event */ 8492 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) 8493 return; 8494 8495 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 8496 8497 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg); 8498 8499 /* advertise highest capable link speed */ 8500 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL)) 8501 speed = IXGBE_LINK_SPEED_10GB_FULL; 8502 else 8503 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL | 8504 IXGBE_LINK_SPEED_1GB_FULL); 8505 8506 if (hw->mac.ops.setup_link) 8507 hw->mac.ops.setup_link(hw, speed, true); 8508 8509 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 8510 adapter->link_check_timeout = jiffies; 8511 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); 8512 } 8513 8514 /** 8515 * ixgbe_service_timer - Timer Call-back 8516 * @t: pointer to timer_list structure 8517 **/ 8518 static void ixgbe_service_timer(struct timer_list *t) 8519 { 8520 struct ixgbe_adapter *adapter = timer_container_of(adapter, t, 8521 service_timer); 8522 unsigned long next_event_offset; 8523 8524 /* poll faster when waiting for link */ 8525 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) 8526 next_event_offset = HZ / 10; 8527 else 8528 next_event_offset = HZ * 2; 8529 8530 /* Reset the timer */ 8531 mod_timer(&adapter->service_timer, next_event_offset + jiffies); 8532 8533 ixgbe_service_event_schedule(adapter); 8534 } 8535 8536 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) 8537 { 8538 struct ixgbe_hw *hw = &adapter->hw; 8539 bool overtemp; 8540 8541 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) 8542 return; 8543 8544 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; 8545 8546 if (!hw->phy.ops.handle_lasi) 8547 return; 8548 8549 hw->phy.ops.handle_lasi(&adapter->hw, &overtemp); 8550 if (overtemp) 8551 e_crit(drv, "%s\n", ixgbe_overheat_msg); 8552 } 8553 8554 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) 8555 { 8556 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state)) 8557 return; 8558 8559 rtnl_lock(); 8560 /* If we're already down, removing or resetting, just bail */ 8561 if (test_bit(__IXGBE_DOWN, &adapter->state) || 8562 test_bit(__IXGBE_REMOVING, &adapter->state) || 8563 test_bit(__IXGBE_RESETTING, &adapter->state)) { 8564 rtnl_unlock(); 8565 return; 8566 } 8567 8568 ixgbe_dump(adapter); 8569 netdev_err(adapter->netdev, "Reset adapter\n"); 8570 adapter->tx_timeout_count++; 8571 8572 ixgbe_reinit_locked(adapter); 8573 rtnl_unlock(); 8574 } 8575 8576 static int ixgbe_check_fw_api_mismatch(struct ixgbe_adapter *adapter) 8577 { 8578 struct ixgbe_hw *hw = &adapter->hw; 8579 8580 if (hw->mac.type != ixgbe_mac_e610) 8581 return 0; 8582 8583 if (hw->mac.ops.get_fw_ver && hw->mac.ops.get_fw_ver(hw)) 8584 return 0; 8585 8586 if (hw->api_maj_ver > IXGBE_FW_API_VER_MAJOR) { 8587 e_dev_err("The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n"); 8588 8589 adapter->flags2 |= IXGBE_FLAG2_API_MISMATCH; 8590 return -EOPNOTSUPP; 8591 } else if (hw->api_maj_ver == IXGBE_FW_API_VER_MAJOR && 8592 hw->api_min_ver > IXGBE_FW_API_VER_MINOR + IXGBE_FW_API_VER_DIFF_ALLOWED) { 8593 e_dev_info("The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n"); 8594 adapter->flags2 |= IXGBE_FLAG2_API_MISMATCH; 8595 } else if (hw->api_maj_ver < IXGBE_FW_API_VER_MAJOR || 8596 hw->api_min_ver < IXGBE_FW_API_VER_MINOR - IXGBE_FW_API_VER_DIFF_ALLOWED) { 8597 e_dev_info("The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n"); 8598 adapter->flags2 |= IXGBE_FLAG2_API_MISMATCH; 8599 } 8600 8601 return 0; 8602 } 8603 8604 /** 8605 * ixgbe_check_fw_error - Check firmware for errors 8606 * @adapter: the adapter private structure 8607 * 8608 * Check firmware errors in register FWSM 8609 */ 8610 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter) 8611 { 8612 struct ixgbe_hw *hw = &adapter->hw; 8613 u32 fwsm; 8614 int err; 8615 8616 /* read fwsm.ext_err_ind register and log errors */ 8617 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 8618 8619 /* skip if E610's FW is reloading, warning in that case may be misleading */ 8620 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK || 8621 (!(fwsm & IXGBE_FWSM_FW_VAL_BIT) && !(hw->mac.type == ixgbe_mac_e610))) 8622 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n", 8623 fwsm); 8624 8625 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 8626 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); 8627 return true; 8628 } 8629 if (!(adapter->flags2 & IXGBE_FLAG2_API_MISMATCH)) { 8630 err = ixgbe_check_fw_api_mismatch(adapter); 8631 if (err) 8632 return true; 8633 } 8634 8635 /* return here if FW rollback mode has been already detected */ 8636 if (adapter->flags2 & IXGBE_FLAG2_FW_ROLLBACK) 8637 return false; 8638 8639 if (hw->mac.ops.fw_rollback_mode && hw->mac.ops.fw_rollback_mode(hw)) { 8640 struct ixgbe_nvm_info *nvm_info = &adapter->hw.flash.nvm; 8641 char ver_buff[64] = ""; 8642 8643 if (hw->mac.ops.get_fw_ver && hw->mac.ops.get_fw_ver(hw)) 8644 goto no_version; 8645 8646 if (hw->mac.ops.get_nvm_ver && 8647 hw->mac.ops.get_nvm_ver(hw, nvm_info)) 8648 goto no_version; 8649 8650 snprintf(ver_buff, sizeof(ver_buff), 8651 "Current version is NVM:%x.%x.%x, FW:%d.%d. ", 8652 nvm_info->major, nvm_info->minor, nvm_info->eetrack, 8653 hw->fw_maj_ver, hw->fw_maj_ver); 8654 no_version: 8655 e_dev_warn("Firmware rollback mode detected. %sDevice may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode.", 8656 ver_buff); 8657 8658 adapter->flags2 |= IXGBE_FLAG2_FW_ROLLBACK; 8659 } 8660 8661 return false; 8662 } 8663 8664 static void ixgbe_recovery_service_task(struct work_struct *work) 8665 { 8666 struct ixgbe_adapter *adapter = container_of(work, 8667 struct ixgbe_adapter, 8668 service_task); 8669 8670 ixgbe_handle_fw_event(adapter); 8671 ixgbe_service_event_complete(adapter); 8672 8673 mod_timer(&adapter->service_timer, jiffies + msecs_to_jiffies(100)); 8674 } 8675 8676 /** 8677 * ixgbe_service_task - manages and runs subtasks 8678 * @work: pointer to work_struct containing our data 8679 **/ 8680 static void ixgbe_service_task(struct work_struct *work) 8681 { 8682 struct ixgbe_adapter *adapter = container_of(work, 8683 struct ixgbe_adapter, 8684 service_task); 8685 if (ixgbe_removed(adapter->hw.hw_addr)) { 8686 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 8687 rtnl_lock(); 8688 ixgbe_down(adapter); 8689 rtnl_unlock(); 8690 } 8691 ixgbe_service_event_complete(adapter); 8692 return; 8693 } 8694 if (ixgbe_check_fw_error(adapter)) { 8695 if (!test_bit(__IXGBE_DOWN, &adapter->state)) { 8696 if (adapter->mii_bus) { 8697 mdiobus_unregister(adapter->mii_bus); 8698 adapter->mii_bus = NULL; 8699 } 8700 unregister_netdev(adapter->netdev); 8701 } 8702 ixgbe_service_event_complete(adapter); 8703 return; 8704 } 8705 if (adapter->hw.mac.type == ixgbe_mac_e610) { 8706 if (adapter->flags2 & IXGBE_FLAG2_FW_ASYNC_EVENT) 8707 ixgbe_handle_fw_event(adapter); 8708 ixgbe_check_media_subtask(adapter); 8709 } 8710 ixgbe_reset_subtask(adapter); 8711 ixgbe_phy_interrupt_subtask(adapter); 8712 ixgbe_sfp_detection_subtask(adapter); 8713 ixgbe_sfp_link_config_subtask(adapter); 8714 ixgbe_check_overtemp_subtask(adapter); 8715 ixgbe_watchdog_subtask(adapter); 8716 ixgbe_fdir_reinit_subtask(adapter); 8717 ixgbe_check_hang_subtask(adapter); 8718 8719 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { 8720 ixgbe_ptp_overflow_check(adapter); 8721 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER) 8722 ixgbe_ptp_rx_hang(adapter); 8723 ixgbe_ptp_tx_hang(adapter); 8724 } 8725 8726 ixgbe_service_event_complete(adapter); 8727 } 8728 8729 static int ixgbe_tso(struct ixgbe_ring *tx_ring, 8730 struct ixgbe_tx_buffer *first, 8731 u8 *hdr_len, 8732 struct ixgbe_ipsec_tx_data *itd) 8733 { 8734 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 8735 struct sk_buff *skb = first->skb; 8736 union { 8737 struct iphdr *v4; 8738 struct ipv6hdr *v6; 8739 unsigned char *hdr; 8740 } ip; 8741 union { 8742 struct tcphdr *tcp; 8743 struct udphdr *udp; 8744 unsigned char *hdr; 8745 } l4; 8746 u32 paylen, l4_offset; 8747 u32 fceof_saidx = 0; 8748 int err; 8749 8750 if (skb->ip_summed != CHECKSUM_PARTIAL) 8751 return 0; 8752 8753 if (!skb_is_gso(skb)) 8754 return 0; 8755 8756 err = skb_cow_head(skb, 0); 8757 if (err < 0) 8758 return err; 8759 8760 if (eth_p_mpls(first->protocol)) 8761 ip.hdr = skb_inner_network_header(skb); 8762 else 8763 ip.hdr = skb_network_header(skb); 8764 l4.hdr = skb_checksum_start(skb); 8765 8766 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 8767 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ? 8768 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP; 8769 8770 /* initialize outer IP header fields */ 8771 if (ip.v4->version == 4) { 8772 unsigned char *csum_start = skb_checksum_start(skb); 8773 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4); 8774 int len = csum_start - trans_start; 8775 8776 /* IP header will have to cancel out any data that 8777 * is not a part of the outer IP header, so set to 8778 * a reverse csum if needed, else init check to 0. 8779 */ 8780 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ? 8781 csum_fold(csum_partial(trans_start, 8782 len, 0)) : 0; 8783 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; 8784 8785 ip.v4->tot_len = 0; 8786 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 8787 IXGBE_TX_FLAGS_CSUM | 8788 IXGBE_TX_FLAGS_IPV4; 8789 } else { 8790 ip.v6->payload_len = 0; 8791 first->tx_flags |= IXGBE_TX_FLAGS_TSO | 8792 IXGBE_TX_FLAGS_CSUM; 8793 } 8794 8795 /* determine offset of inner transport header */ 8796 l4_offset = l4.hdr - skb->data; 8797 8798 /* remove payload length from inner checksum */ 8799 paylen = skb->len - l4_offset; 8800 8801 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) { 8802 /* compute length of segmentation header */ 8803 *hdr_len = (l4.tcp->doff * 4) + l4_offset; 8804 csum_replace_by_diff(&l4.tcp->check, 8805 (__force __wsum)htonl(paylen)); 8806 } else { 8807 /* compute length of segmentation header */ 8808 *hdr_len = sizeof(*l4.udp) + l4_offset; 8809 csum_replace_by_diff(&l4.udp->check, 8810 (__force __wsum)htonl(paylen)); 8811 } 8812 8813 /* update gso size and bytecount with header size */ 8814 first->gso_segs = skb_shinfo(skb)->gso_segs; 8815 first->bytecount += (first->gso_segs - 1) * *hdr_len; 8816 8817 /* mss_l4len_id: use 0 as index for TSO */ 8818 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; 8819 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; 8820 8821 fceof_saidx |= itd->sa_idx; 8822 type_tucmd |= itd->flags | itd->trailer_len; 8823 8824 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 8825 vlan_macip_lens = l4.hdr - ip.hdr; 8826 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; 8827 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8828 8829 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 8830 mss_l4len_idx); 8831 8832 return 1; 8833 } 8834 8835 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, 8836 struct ixgbe_tx_buffer *first, 8837 struct ixgbe_ipsec_tx_data *itd) 8838 { 8839 struct sk_buff *skb = first->skb; 8840 u32 vlan_macip_lens = 0; 8841 u32 fceof_saidx = 0; 8842 u32 type_tucmd = 0; 8843 8844 if (skb->ip_summed != CHECKSUM_PARTIAL) { 8845 csum_failed: 8846 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | 8847 IXGBE_TX_FLAGS_CC))) 8848 return; 8849 goto no_csum; 8850 } 8851 8852 switch (skb->csum_offset) { 8853 case offsetof(struct tcphdr, check): 8854 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; 8855 fallthrough; 8856 case offsetof(struct udphdr, check): 8857 break; 8858 case offsetof(struct sctphdr, checksum): 8859 /* validate that this is actually an SCTP request */ 8860 if (skb_csum_is_sctp(skb)) { 8861 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; 8862 break; 8863 } 8864 fallthrough; 8865 default: 8866 skb_checksum_help(skb); 8867 goto csum_failed; 8868 } 8869 8870 /* update TX checksum flag */ 8871 first->tx_flags |= IXGBE_TX_FLAGS_CSUM; 8872 vlan_macip_lens = skb_checksum_start_offset(skb) - 8873 skb_network_offset(skb); 8874 no_csum: 8875 /* vlan_macip_lens: MACLEN, VLAN tag */ 8876 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; 8877 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; 8878 8879 fceof_saidx |= itd->sa_idx; 8880 type_tucmd |= itd->flags | itd->trailer_len; 8881 8882 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0); 8883 } 8884 8885 #define IXGBE_SET_FLAG(_input, _flag, _result) \ 8886 ((_flag <= _result) ? \ 8887 ((u32)(_input & _flag) * (_result / _flag)) : \ 8888 ((u32)(_input & _flag) / (_flag / _result))) 8889 8890 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 8891 { 8892 /* set type for advanced descriptor with frame checksum insertion */ 8893 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 8894 IXGBE_ADVTXD_DCMD_DEXT | 8895 IXGBE_ADVTXD_DCMD_IFCS; 8896 8897 /* set HW vlan bit if vlan is present */ 8898 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, 8899 IXGBE_ADVTXD_DCMD_VLE); 8900 8901 /* set segmentation enable bits for TSO/FSO */ 8902 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, 8903 IXGBE_ADVTXD_DCMD_TSE); 8904 8905 /* set timestamp bit if present */ 8906 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, 8907 IXGBE_ADVTXD_MAC_TSTAMP); 8908 8909 /* insert frame checksum */ 8910 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); 8911 8912 return cmd_type; 8913 } 8914 8915 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, 8916 u32 tx_flags, unsigned int paylen) 8917 { 8918 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; 8919 8920 /* enable L4 checksum for TSO and TX checksum offload */ 8921 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8922 IXGBE_TX_FLAGS_CSUM, 8923 IXGBE_ADVTXD_POPTS_TXSM); 8924 8925 /* enable IPv4 checksum for TSO */ 8926 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8927 IXGBE_TX_FLAGS_IPV4, 8928 IXGBE_ADVTXD_POPTS_IXSM); 8929 8930 /* enable IPsec */ 8931 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8932 IXGBE_TX_FLAGS_IPSEC, 8933 IXGBE_ADVTXD_POPTS_IPSEC); 8934 8935 /* 8936 * Check Context must be set if Tx switch is enabled, which it 8937 * always is for case where virtual functions are running 8938 */ 8939 olinfo_status |= IXGBE_SET_FLAG(tx_flags, 8940 IXGBE_TX_FLAGS_CC, 8941 IXGBE_ADVTXD_CC); 8942 8943 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 8944 } 8945 8946 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8947 { 8948 if (!netif_subqueue_try_stop(tx_ring->netdev, tx_ring->queue_index, 8949 ixgbe_desc_unused(tx_ring), size)) 8950 return -EBUSY; 8951 8952 ++tx_ring->tx_stats.restart_queue; 8953 return 0; 8954 } 8955 8956 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) 8957 { 8958 if (likely(ixgbe_desc_unused(tx_ring) >= size)) 8959 return 0; 8960 8961 return __ixgbe_maybe_stop_tx(tx_ring, size); 8962 } 8963 8964 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring, 8965 struct ixgbe_tx_buffer *first, 8966 const u8 hdr_len) 8967 { 8968 struct sk_buff *skb = first->skb; 8969 struct ixgbe_tx_buffer *tx_buffer; 8970 union ixgbe_adv_tx_desc *tx_desc; 8971 skb_frag_t *frag; 8972 dma_addr_t dma; 8973 unsigned int data_len, size; 8974 u32 tx_flags = first->tx_flags; 8975 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); 8976 u16 i = tx_ring->next_to_use; 8977 8978 tx_desc = IXGBE_TX_DESC(tx_ring, i); 8979 8980 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 8981 8982 size = skb_headlen(skb); 8983 data_len = skb->data_len; 8984 8985 #ifdef IXGBE_FCOE 8986 if (tx_flags & IXGBE_TX_FLAGS_FCOE) { 8987 if (data_len < sizeof(struct fcoe_crc_eof)) { 8988 size -= sizeof(struct fcoe_crc_eof) - data_len; 8989 data_len = 0; 8990 } else { 8991 data_len -= sizeof(struct fcoe_crc_eof); 8992 } 8993 } 8994 8995 #endif 8996 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 8997 8998 tx_buffer = first; 8999 9000 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 9001 if (dma_mapping_error(tx_ring->dev, dma)) 9002 goto dma_error; 9003 9004 /* record length, and DMA address */ 9005 dma_unmap_len_set(tx_buffer, len, size); 9006 dma_unmap_addr_set(tx_buffer, dma, dma); 9007 9008 tx_desc->read.buffer_addr = cpu_to_le64(dma); 9009 9010 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { 9011 tx_desc->read.cmd_type_len = 9012 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); 9013 9014 i++; 9015 tx_desc++; 9016 if (i == tx_ring->count) { 9017 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 9018 i = 0; 9019 } 9020 tx_desc->read.olinfo_status = 0; 9021 9022 dma += IXGBE_MAX_DATA_PER_TXD; 9023 size -= IXGBE_MAX_DATA_PER_TXD; 9024 9025 tx_desc->read.buffer_addr = cpu_to_le64(dma); 9026 } 9027 9028 if (likely(!data_len)) 9029 break; 9030 9031 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 9032 9033 i++; 9034 tx_desc++; 9035 if (i == tx_ring->count) { 9036 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 9037 i = 0; 9038 } 9039 tx_desc->read.olinfo_status = 0; 9040 9041 #ifdef IXGBE_FCOE 9042 size = min_t(unsigned int, data_len, skb_frag_size(frag)); 9043 #else 9044 size = skb_frag_size(frag); 9045 #endif 9046 data_len -= size; 9047 9048 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 9049 DMA_TO_DEVICE); 9050 9051 tx_buffer = &tx_ring->tx_buffer_info[i]; 9052 } 9053 9054 /* write last descriptor with RS and EOP bits */ 9055 cmd_type |= size | IXGBE_TXD_CMD; 9056 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 9057 9058 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 9059 9060 /* set the timestamp */ 9061 first->time_stamp = jiffies; 9062 9063 skb_tx_timestamp(skb); 9064 9065 /* 9066 * Force memory writes to complete before letting h/w know there 9067 * are new descriptors to fetch. (Only applicable for weak-ordered 9068 * memory model archs, such as IA-64). 9069 * 9070 * We also need this memory barrier to make certain all of the 9071 * status bits have been updated before next_to_watch is written. 9072 */ 9073 wmb(); 9074 9075 /* set next_to_watch value indicating a packet is present */ 9076 first->next_to_watch = tx_desc; 9077 9078 i++; 9079 if (i == tx_ring->count) 9080 i = 0; 9081 9082 tx_ring->next_to_use = i; 9083 9084 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); 9085 9086 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) { 9087 writel(i, tx_ring->tail); 9088 } 9089 9090 return 0; 9091 dma_error: 9092 dev_err(tx_ring->dev, "TX DMA map failed\n"); 9093 9094 /* clear dma mappings for failed tx_buffer_info map */ 9095 for (;;) { 9096 tx_buffer = &tx_ring->tx_buffer_info[i]; 9097 if (dma_unmap_len(tx_buffer, len)) 9098 dma_unmap_page(tx_ring->dev, 9099 dma_unmap_addr(tx_buffer, dma), 9100 dma_unmap_len(tx_buffer, len), 9101 DMA_TO_DEVICE); 9102 dma_unmap_len_set(tx_buffer, len, 0); 9103 if (tx_buffer == first) 9104 break; 9105 if (i == 0) 9106 i += tx_ring->count; 9107 i--; 9108 } 9109 9110 dev_kfree_skb_any(first->skb); 9111 first->skb = NULL; 9112 9113 tx_ring->next_to_use = i; 9114 9115 return -1; 9116 } 9117 9118 static void ixgbe_atr(struct ixgbe_ring *ring, 9119 struct ixgbe_tx_buffer *first) 9120 { 9121 struct ixgbe_q_vector *q_vector = ring->q_vector; 9122 union ixgbe_atr_hash_dword input = { .dword = 0 }; 9123 union ixgbe_atr_hash_dword common = { .dword = 0 }; 9124 union { 9125 unsigned char *network; 9126 struct iphdr *ipv4; 9127 struct ipv6hdr *ipv6; 9128 } hdr; 9129 struct tcphdr *th; 9130 unsigned int hlen; 9131 struct sk_buff *skb; 9132 __be16 vlan_id; 9133 int l4_proto; 9134 9135 /* if ring doesn't have a interrupt vector, cannot perform ATR */ 9136 if (!q_vector) 9137 return; 9138 9139 /* do nothing if sampling is disabled */ 9140 if (!ring->atr_sample_rate) 9141 return; 9142 9143 ring->atr_count++; 9144 9145 /* currently only IPv4/IPv6 with TCP is supported */ 9146 if ((first->protocol != htons(ETH_P_IP)) && 9147 (first->protocol != htons(ETH_P_IPV6))) 9148 return; 9149 9150 /* snag network header to get L4 type and address */ 9151 skb = first->skb; 9152 hdr.network = skb_network_header(skb); 9153 if (unlikely(hdr.network <= skb->data)) 9154 return; 9155 if (skb->encapsulation && 9156 first->protocol == htons(ETH_P_IP) && 9157 hdr.ipv4->protocol == IPPROTO_UDP) { 9158 struct ixgbe_adapter *adapter = q_vector->adapter; 9159 9160 if (unlikely(skb_tail_pointer(skb) < hdr.network + 9161 vxlan_headroom(0))) 9162 return; 9163 9164 /* verify the port is recognized as VXLAN */ 9165 if (adapter->vxlan_port && 9166 udp_hdr(skb)->dest == adapter->vxlan_port) 9167 hdr.network = skb_inner_network_header(skb); 9168 9169 if (adapter->geneve_port && 9170 udp_hdr(skb)->dest == adapter->geneve_port) 9171 hdr.network = skb_inner_network_header(skb); 9172 } 9173 9174 /* Make sure we have at least [minimum IPv4 header + TCP] 9175 * or [IPv6 header] bytes 9176 */ 9177 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40)) 9178 return; 9179 9180 /* Currently only IPv4/IPv6 with TCP is supported */ 9181 switch (hdr.ipv4->version) { 9182 case IPVERSION: 9183 /* access ihl as u8 to avoid unaligned access on ia64 */ 9184 hlen = (hdr.network[0] & 0x0F) << 2; 9185 l4_proto = hdr.ipv4->protocol; 9186 break; 9187 case 6: 9188 hlen = hdr.network - skb->data; 9189 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); 9190 hlen -= hdr.network - skb->data; 9191 break; 9192 default: 9193 return; 9194 } 9195 9196 if (l4_proto != IPPROTO_TCP) 9197 return; 9198 9199 if (unlikely(skb_tail_pointer(skb) < hdr.network + 9200 hlen + sizeof(struct tcphdr))) 9201 return; 9202 9203 th = (struct tcphdr *)(hdr.network + hlen); 9204 9205 /* skip this packet since the socket is closing */ 9206 if (th->fin) 9207 return; 9208 9209 /* sample on all syn packets or once every atr sample count */ 9210 if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) 9211 return; 9212 9213 /* reset sample count */ 9214 ring->atr_count = 0; 9215 9216 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); 9217 9218 /* 9219 * src and dst are inverted, think how the receiver sees them 9220 * 9221 * The input is broken into two sections, a non-compressed section 9222 * containing vm_pool, vlan_id, and flow_type. The rest of the data 9223 * is XORed together and stored in the compressed dword. 9224 */ 9225 input.formatted.vlan_id = vlan_id; 9226 9227 /* 9228 * since src port and flex bytes occupy the same word XOR them together 9229 * and write the value to source port portion of compressed dword 9230 */ 9231 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) 9232 common.port.src ^= th->dest ^ htons(ETH_P_8021Q); 9233 else 9234 common.port.src ^= th->dest ^ first->protocol; 9235 common.port.dst ^= th->source; 9236 9237 switch (hdr.ipv4->version) { 9238 case IPVERSION: 9239 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; 9240 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; 9241 break; 9242 case 6: 9243 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; 9244 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ 9245 hdr.ipv6->saddr.s6_addr32[1] ^ 9246 hdr.ipv6->saddr.s6_addr32[2] ^ 9247 hdr.ipv6->saddr.s6_addr32[3] ^ 9248 hdr.ipv6->daddr.s6_addr32[0] ^ 9249 hdr.ipv6->daddr.s6_addr32[1] ^ 9250 hdr.ipv6->daddr.s6_addr32[2] ^ 9251 hdr.ipv6->daddr.s6_addr32[3]; 9252 break; 9253 default: 9254 break; 9255 } 9256 9257 if (hdr.network != skb_network_header(skb)) 9258 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; 9259 9260 /* This assumes the Rx queue and Tx queue are bound to the same CPU */ 9261 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, 9262 input, common, ring->queue_index); 9263 } 9264 9265 #ifdef IXGBE_FCOE 9266 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, 9267 struct net_device *sb_dev) 9268 { 9269 struct ixgbe_adapter *adapter; 9270 struct ixgbe_ring_feature *f; 9271 int txq; 9272 9273 if (sb_dev) { 9274 u8 tc = netdev_get_prio_tc_map(dev, skb->priority); 9275 struct net_device *vdev = sb_dev; 9276 9277 txq = vdev->tc_to_txq[tc].offset; 9278 txq += reciprocal_scale(skb_get_hash(skb), 9279 vdev->tc_to_txq[tc].count); 9280 9281 return txq; 9282 } 9283 9284 /* 9285 * only execute the code below if protocol is FCoE 9286 * or FIP and we have FCoE enabled on the adapter 9287 */ 9288 switch (vlan_get_protocol(skb)) { 9289 case htons(ETH_P_FCOE): 9290 case htons(ETH_P_FIP): 9291 adapter = ixgbe_from_netdev(dev); 9292 9293 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) 9294 break; 9295 fallthrough; 9296 default: 9297 return netdev_pick_tx(dev, skb, sb_dev); 9298 } 9299 9300 f = &adapter->ring_feature[RING_F_FCOE]; 9301 9302 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : 9303 smp_processor_id(); 9304 9305 while (txq >= f->indices) 9306 txq -= f->indices; 9307 9308 return txq + f->offset; 9309 } 9310 9311 #endif 9312 int ixgbe_xmit_xdp_ring(struct ixgbe_ring *ring, 9313 struct xdp_frame *xdpf) 9314 { 9315 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 9316 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 9317 u16 i = 0, index = ring->next_to_use; 9318 struct ixgbe_tx_buffer *tx_head = &ring->tx_buffer_info[index]; 9319 struct ixgbe_tx_buffer *tx_buff = tx_head; 9320 union ixgbe_adv_tx_desc *tx_desc = IXGBE_TX_DESC(ring, index); 9321 u32 cmd_type, len = xdpf->len; 9322 void *data = xdpf->data; 9323 9324 if (unlikely(ixgbe_desc_unused(ring) < 1 + nr_frags)) 9325 return IXGBE_XDP_CONSUMED; 9326 9327 tx_head->bytecount = xdp_get_frame_len(xdpf); 9328 tx_head->gso_segs = 1; 9329 tx_head->xdpf = xdpf; 9330 9331 tx_desc->read.olinfo_status = 9332 cpu_to_le32(tx_head->bytecount << IXGBE_ADVTXD_PAYLEN_SHIFT); 9333 9334 for (;;) { 9335 dma_addr_t dma; 9336 9337 dma = dma_map_single(ring->dev, data, len, DMA_TO_DEVICE); 9338 if (dma_mapping_error(ring->dev, dma)) 9339 goto unmap; 9340 9341 dma_unmap_len_set(tx_buff, len, len); 9342 dma_unmap_addr_set(tx_buff, dma, dma); 9343 9344 cmd_type = IXGBE_ADVTXD_DTYP_DATA | IXGBE_ADVTXD_DCMD_DEXT | 9345 IXGBE_ADVTXD_DCMD_IFCS | len; 9346 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 9347 tx_desc->read.buffer_addr = cpu_to_le64(dma); 9348 tx_buff->protocol = 0; 9349 9350 if (++index == ring->count) 9351 index = 0; 9352 9353 if (i == nr_frags) 9354 break; 9355 9356 tx_buff = &ring->tx_buffer_info[index]; 9357 tx_desc = IXGBE_TX_DESC(ring, index); 9358 tx_desc->read.olinfo_status = 0; 9359 9360 data = skb_frag_address(&sinfo->frags[i]); 9361 len = skb_frag_size(&sinfo->frags[i]); 9362 i++; 9363 } 9364 /* put descriptor type bits */ 9365 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD); 9366 9367 /* Avoid any potential race with xdp_xmit and cleanup */ 9368 smp_wmb(); 9369 9370 tx_head->next_to_watch = tx_desc; 9371 ring->next_to_use = index; 9372 9373 return IXGBE_XDP_TX; 9374 9375 unmap: 9376 for (;;) { 9377 tx_buff = &ring->tx_buffer_info[index]; 9378 if (dma_unmap_len(tx_buff, len)) 9379 dma_unmap_page(ring->dev, dma_unmap_addr(tx_buff, dma), 9380 dma_unmap_len(tx_buff, len), 9381 DMA_TO_DEVICE); 9382 dma_unmap_len_set(tx_buff, len, 0); 9383 if (tx_buff == tx_head) 9384 break; 9385 9386 if (!index) 9387 index += ring->count; 9388 index--; 9389 } 9390 9391 return IXGBE_XDP_CONSUMED; 9392 } 9393 9394 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, 9395 struct ixgbe_adapter *adapter, 9396 struct ixgbe_ring *tx_ring) 9397 { 9398 struct ixgbe_tx_buffer *first; 9399 int tso; 9400 u32 tx_flags = 0; 9401 unsigned short f; 9402 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 9403 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 }; 9404 __be16 protocol = skb->protocol; 9405 u8 hdr_len = 0; 9406 9407 /* 9408 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, 9409 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, 9410 * + 2 desc gap to keep tail from touching head, 9411 * + 1 desc for context descriptor, 9412 * otherwise try next time 9413 */ 9414 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 9415 count += TXD_USE_COUNT(skb_frag_size( 9416 &skb_shinfo(skb)->frags[f])); 9417 9418 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { 9419 tx_ring->tx_stats.tx_busy++; 9420 return NETDEV_TX_BUSY; 9421 } 9422 9423 /* record the location of the first descriptor for this packet */ 9424 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 9425 first->skb = skb; 9426 first->bytecount = skb->len; 9427 first->gso_segs = 1; 9428 9429 /* if we have a HW VLAN tag being added default to the HW one */ 9430 if (skb_vlan_tag_present(skb)) { 9431 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; 9432 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 9433 /* else if it is a SW VLAN check the next protocol and store the tag */ 9434 } else if (protocol == htons(ETH_P_8021Q)) { 9435 struct vlan_hdr *vhdr, _vhdr; 9436 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); 9437 if (!vhdr) 9438 goto out_drop; 9439 9440 tx_flags |= ntohs(vhdr->h_vlan_TCI) << 9441 IXGBE_TX_FLAGS_VLAN_SHIFT; 9442 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; 9443 } 9444 protocol = vlan_get_protocol(skb); 9445 9446 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 9447 adapter->ptp_clock) { 9448 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON && 9449 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, 9450 &adapter->state)) { 9451 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 9452 tx_flags |= IXGBE_TX_FLAGS_TSTAMP; 9453 9454 /* schedule check for Tx timestamp */ 9455 adapter->ptp_tx_skb = skb_get(skb); 9456 adapter->ptp_tx_start = jiffies; 9457 schedule_work(&adapter->ptp_tx_work); 9458 } else { 9459 adapter->tx_hwtstamp_skipped++; 9460 } 9461 } 9462 9463 #ifdef CONFIG_PCI_IOV 9464 /* 9465 * Use the l2switch_enable flag - would be false if the DMA 9466 * Tx switch had been disabled. 9467 */ 9468 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 9469 tx_flags |= IXGBE_TX_FLAGS_CC; 9470 9471 #endif 9472 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ 9473 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 9474 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || 9475 (skb->priority != TC_PRIO_CONTROL))) { 9476 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; 9477 tx_flags |= (skb->priority & 0x7) << 9478 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; 9479 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { 9480 struct vlan_ethhdr *vhdr; 9481 9482 if (skb_cow_head(skb, 0)) 9483 goto out_drop; 9484 vhdr = skb_vlan_eth_hdr(skb); 9485 vhdr->h_vlan_TCI = htons(tx_flags >> 9486 IXGBE_TX_FLAGS_VLAN_SHIFT); 9487 } else { 9488 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; 9489 } 9490 } 9491 9492 /* record initial flags and protocol */ 9493 first->tx_flags = tx_flags; 9494 first->protocol = protocol; 9495 9496 #ifdef IXGBE_FCOE 9497 /* setup tx offload for FCoE */ 9498 if ((protocol == htons(ETH_P_FCOE)) && 9499 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { 9500 tso = ixgbe_fso(tx_ring, first, &hdr_len); 9501 if (tso < 0) 9502 goto out_drop; 9503 9504 goto xmit_fcoe; 9505 } 9506 9507 #endif /* IXGBE_FCOE */ 9508 9509 #ifdef CONFIG_IXGBE_IPSEC 9510 if (xfrm_offload(skb) && 9511 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx)) 9512 goto out_drop; 9513 #endif 9514 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx); 9515 if (tso < 0) 9516 goto out_drop; 9517 else if (!tso) 9518 ixgbe_tx_csum(tx_ring, first, &ipsec_tx); 9519 9520 /* add the ATR filter if ATR is on */ 9521 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, tx_ring->state)) 9522 ixgbe_atr(tx_ring, first); 9523 9524 #ifdef IXGBE_FCOE 9525 xmit_fcoe: 9526 #endif /* IXGBE_FCOE */ 9527 if (ixgbe_tx_map(tx_ring, first, hdr_len)) 9528 goto cleanup_tx_timestamp; 9529 9530 return NETDEV_TX_OK; 9531 9532 out_drop: 9533 dev_kfree_skb_any(first->skb); 9534 first->skb = NULL; 9535 cleanup_tx_timestamp: 9536 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) { 9537 dev_kfree_skb_any(adapter->ptp_tx_skb); 9538 adapter->ptp_tx_skb = NULL; 9539 cancel_work_sync(&adapter->ptp_tx_work); 9540 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 9541 } 9542 9543 return NETDEV_TX_OK; 9544 } 9545 9546 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, 9547 struct net_device *netdev, 9548 struct ixgbe_ring *ring) 9549 { 9550 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 9551 struct ixgbe_ring *tx_ring; 9552 9553 /* 9554 * The minimum packet size for olinfo paylen is 17 so pad the skb 9555 * in order to meet this minimum size requirement. 9556 */ 9557 if (skb_put_padto(skb, 17)) 9558 return NETDEV_TX_OK; 9559 9560 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)]; 9561 if (unlikely(test_bit(__IXGBE_TX_DISABLED, tx_ring->state))) 9562 return NETDEV_TX_BUSY; 9563 9564 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); 9565 } 9566 9567 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, 9568 struct net_device *netdev) 9569 { 9570 return __ixgbe_xmit_frame(skb, netdev, NULL); 9571 } 9572 9573 /** 9574 * ixgbe_set_mac - Change the Ethernet Address of the NIC 9575 * @netdev: network interface device structure 9576 * @p: pointer to an address structure 9577 * 9578 * Returns 0 on success, negative on failure 9579 **/ 9580 static int ixgbe_set_mac(struct net_device *netdev, void *p) 9581 { 9582 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 9583 struct ixgbe_hw *hw = &adapter->hw; 9584 struct sockaddr *addr = p; 9585 9586 if (!is_valid_ether_addr(addr->sa_data)) 9587 return -EADDRNOTAVAIL; 9588 9589 eth_hw_addr_set(netdev, addr->sa_data); 9590 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 9591 9592 ixgbe_mac_set_default_filter(adapter); 9593 9594 return 0; 9595 } 9596 9597 static int 9598 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) 9599 { 9600 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 9601 struct ixgbe_hw *hw = &adapter->hw; 9602 u16 value; 9603 int rc; 9604 9605 if (adapter->mii_bus) { 9606 int regnum = addr; 9607 9608 if (devad != MDIO_DEVAD_NONE) 9609 return mdiobus_c45_read(adapter->mii_bus, prtad, 9610 devad, regnum); 9611 9612 return mdiobus_read(adapter->mii_bus, prtad, regnum); 9613 } 9614 9615 if (prtad != hw->phy.mdio.prtad) 9616 return -EINVAL; 9617 rc = hw->phy.ops.read_reg(hw, addr, devad, &value); 9618 if (!rc) 9619 rc = value; 9620 return rc; 9621 } 9622 9623 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, 9624 u16 addr, u16 value) 9625 { 9626 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 9627 struct ixgbe_hw *hw = &adapter->hw; 9628 9629 if (adapter->mii_bus) { 9630 int regnum = addr; 9631 9632 if (devad != MDIO_DEVAD_NONE) 9633 return mdiobus_c45_write(adapter->mii_bus, prtad, devad, 9634 regnum, value); 9635 9636 return mdiobus_write(adapter->mii_bus, prtad, regnum, value); 9637 } 9638 9639 if (prtad != hw->phy.mdio.prtad) 9640 return -EINVAL; 9641 return hw->phy.ops.write_reg(hw, addr, devad, value); 9642 } 9643 9644 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 9645 { 9646 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 9647 9648 switch (cmd) { 9649 case SIOCGMIIPHY: 9650 if (!adapter->hw.phy.ops.read_reg) 9651 return -EOPNOTSUPP; 9652 fallthrough; 9653 default: 9654 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); 9655 } 9656 } 9657 9658 /** 9659 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding 9660 * netdev->dev_addrs 9661 * @dev: network interface device structure 9662 * 9663 * Returns non-zero on failure 9664 **/ 9665 static int ixgbe_add_sanmac_netdev(struct net_device *dev) 9666 { 9667 int err = 0; 9668 struct ixgbe_adapter *adapter = ixgbe_from_netdev(dev); 9669 struct ixgbe_hw *hw = &adapter->hw; 9670 9671 if (is_valid_ether_addr(hw->mac.san_addr)) { 9672 rtnl_lock(); 9673 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); 9674 rtnl_unlock(); 9675 9676 /* update SAN MAC vmdq pool selection */ 9677 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); 9678 } 9679 return err; 9680 } 9681 9682 /** 9683 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding 9684 * netdev->dev_addrs 9685 * @dev: network interface device structure 9686 * 9687 * Returns non-zero on failure 9688 **/ 9689 static int ixgbe_del_sanmac_netdev(struct net_device *dev) 9690 { 9691 int err = 0; 9692 struct ixgbe_adapter *adapter = ixgbe_from_netdev(dev); 9693 struct ixgbe_mac_info *mac = &adapter->hw.mac; 9694 9695 if (is_valid_ether_addr(mac->san_addr)) { 9696 rtnl_lock(); 9697 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); 9698 rtnl_unlock(); 9699 } 9700 return err; 9701 } 9702 9703 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats, 9704 struct ixgbe_ring *ring) 9705 { 9706 u64 bytes, packets; 9707 unsigned int start; 9708 9709 if (ring) { 9710 do { 9711 start = u64_stats_fetch_begin(&ring->syncp); 9712 packets = ring->stats.packets; 9713 bytes = ring->stats.bytes; 9714 } while (u64_stats_fetch_retry(&ring->syncp, start)); 9715 stats->tx_packets += packets; 9716 stats->tx_bytes += bytes; 9717 } 9718 } 9719 9720 static void ixgbe_get_stats64(struct net_device *netdev, 9721 struct rtnl_link_stats64 *stats) 9722 { 9723 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 9724 int i; 9725 9726 rcu_read_lock(); 9727 for (i = 0; i < adapter->num_rx_queues; i++) { 9728 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]); 9729 u64 bytes, packets; 9730 unsigned int start; 9731 9732 if (ring) { 9733 do { 9734 start = u64_stats_fetch_begin(&ring->syncp); 9735 packets = ring->stats.packets; 9736 bytes = ring->stats.bytes; 9737 } while (u64_stats_fetch_retry(&ring->syncp, start)); 9738 stats->rx_packets += packets; 9739 stats->rx_bytes += bytes; 9740 } 9741 } 9742 9743 for (i = 0; i < adapter->num_tx_queues; i++) { 9744 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]); 9745 9746 ixgbe_get_ring_stats64(stats, ring); 9747 } 9748 for (i = 0; i < adapter->num_xdp_queues; i++) { 9749 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]); 9750 9751 ixgbe_get_ring_stats64(stats, ring); 9752 } 9753 rcu_read_unlock(); 9754 9755 /* following stats updated by ixgbe_watchdog_task() */ 9756 stats->multicast = netdev->stats.multicast; 9757 stats->rx_errors = netdev->stats.rx_errors; 9758 stats->rx_length_errors = netdev->stats.rx_length_errors; 9759 stats->rx_crc_errors = netdev->stats.rx_crc_errors; 9760 stats->rx_missed_errors = netdev->stats.rx_missed_errors; 9761 } 9762 9763 static int ixgbe_ndo_get_vf_stats(struct net_device *netdev, int vf, 9764 struct ifla_vf_stats *vf_stats) 9765 { 9766 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 9767 9768 if (vf < 0 || vf >= adapter->num_vfs) 9769 return -EINVAL; 9770 9771 vf_stats->rx_packets = adapter->vfinfo[vf].vfstats.gprc; 9772 vf_stats->rx_bytes = adapter->vfinfo[vf].vfstats.gorc; 9773 vf_stats->tx_packets = adapter->vfinfo[vf].vfstats.gptc; 9774 vf_stats->tx_bytes = adapter->vfinfo[vf].vfstats.gotc; 9775 vf_stats->multicast = adapter->vfinfo[vf].vfstats.mprc; 9776 9777 return 0; 9778 } 9779 9780 #ifdef CONFIG_IXGBE_DCB 9781 /** 9782 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. 9783 * @adapter: pointer to ixgbe_adapter 9784 * @tc: number of traffic classes currently enabled 9785 * 9786 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm 9787 * 802.1Q priority maps to a packet buffer that exists. 9788 */ 9789 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) 9790 { 9791 struct ixgbe_hw *hw = &adapter->hw; 9792 u32 reg, rsave; 9793 int i; 9794 9795 /* 82598 have a static priority to TC mapping that can not 9796 * be changed so no validation is needed. 9797 */ 9798 if (hw->mac.type == ixgbe_mac_82598EB) 9799 return; 9800 9801 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 9802 rsave = reg; 9803 9804 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { 9805 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); 9806 9807 /* If up2tc is out of bounds default to zero */ 9808 if (up2tc > tc) 9809 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); 9810 } 9811 9812 if (reg != rsave) 9813 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 9814 9815 return; 9816 } 9817 9818 /** 9819 * ixgbe_set_prio_tc_map - Configure netdev prio tc map 9820 * @adapter: Pointer to adapter struct 9821 * 9822 * Populate the netdev user priority to tc map 9823 */ 9824 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) 9825 { 9826 struct net_device *dev = adapter->netdev; 9827 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; 9828 struct ieee_ets *ets = adapter->ixgbe_ieee_ets; 9829 u8 prio; 9830 9831 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { 9832 u8 tc = 0; 9833 9834 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) 9835 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); 9836 else if (ets) 9837 tc = ets->prio_tc[prio]; 9838 9839 netdev_set_prio_tc_map(dev, prio, tc); 9840 } 9841 } 9842 9843 #endif /* CONFIG_IXGBE_DCB */ 9844 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev, 9845 struct netdev_nested_priv *priv) 9846 { 9847 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data; 9848 struct ixgbe_fwd_adapter *accel; 9849 int pool; 9850 9851 /* we only care about macvlans... */ 9852 if (!netif_is_macvlan(vdev)) 9853 return 0; 9854 9855 /* that have hardware offload enabled... */ 9856 accel = macvlan_accel_priv(vdev); 9857 if (!accel) 9858 return 0; 9859 9860 /* If we can relocate to a different bit do so */ 9861 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 9862 if (pool < adapter->num_rx_pools) { 9863 set_bit(pool, adapter->fwd_bitmask); 9864 accel->pool = pool; 9865 return 0; 9866 } 9867 9868 /* if we cannot find a free pool then disable the offload */ 9869 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n"); 9870 macvlan_release_l2fw_offload(vdev); 9871 9872 /* unbind the queues and drop the subordinate channel config */ 9873 netdev_unbind_sb_channel(adapter->netdev, vdev); 9874 netdev_set_sb_channel(vdev, 0); 9875 9876 kfree(accel); 9877 9878 return 0; 9879 } 9880 9881 static void ixgbe_defrag_macvlan_pools(struct net_device *dev) 9882 { 9883 struct ixgbe_adapter *adapter = ixgbe_from_netdev(dev); 9884 struct netdev_nested_priv priv = { 9885 .data = (void *)adapter, 9886 }; 9887 9888 /* flush any stale bits out of the fwd bitmask */ 9889 bitmap_clear(adapter->fwd_bitmask, 1, 63); 9890 9891 /* walk through upper devices reassigning pools */ 9892 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool, 9893 &priv); 9894 } 9895 9896 /** 9897 * ixgbe_setup_tc - configure net_device for multiple traffic classes 9898 * 9899 * @dev: net device to configure 9900 * @tc: number of traffic classes to enable 9901 */ 9902 int ixgbe_setup_tc(struct net_device *dev, u8 tc) 9903 { 9904 struct ixgbe_adapter *adapter = ixgbe_from_netdev(dev); 9905 struct ixgbe_hw *hw = &adapter->hw; 9906 9907 /* Hardware supports up to 8 traffic classes */ 9908 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) 9909 return -EINVAL; 9910 9911 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) 9912 return -EINVAL; 9913 9914 /* Hardware has to reinitialize queues and interrupts to 9915 * match packet buffer alignment. Unfortunately, the 9916 * hardware is not flexible enough to do this dynamically. 9917 */ 9918 if (netif_running(dev)) 9919 ixgbe_close(dev); 9920 else 9921 ixgbe_reset(adapter); 9922 9923 ixgbe_clear_interrupt_scheme(adapter); 9924 9925 #ifdef CONFIG_IXGBE_DCB 9926 if (tc) { 9927 if (adapter->xdp_prog) { 9928 e_warn(probe, "DCB is not supported with XDP\n"); 9929 9930 ixgbe_init_interrupt_scheme(adapter); 9931 if (netif_running(dev)) 9932 ixgbe_open(dev); 9933 return -EINVAL; 9934 } 9935 9936 netdev_set_num_tc(dev, tc); 9937 ixgbe_set_prio_tc_map(adapter); 9938 9939 adapter->hw_tcs = tc; 9940 adapter->flags |= IXGBE_FLAG_DCB_ENABLED; 9941 9942 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { 9943 adapter->last_lfc_mode = adapter->hw.fc.requested_mode; 9944 adapter->hw.fc.requested_mode = ixgbe_fc_none; 9945 } 9946 } else { 9947 netdev_reset_tc(dev); 9948 9949 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 9950 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; 9951 9952 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; 9953 adapter->hw_tcs = tc; 9954 9955 adapter->temp_dcb_cfg.pfc_mode_enable = false; 9956 adapter->dcb_cfg.pfc_mode_enable = false; 9957 } 9958 9959 ixgbe_validate_rtr(adapter, tc); 9960 9961 #endif /* CONFIG_IXGBE_DCB */ 9962 ixgbe_init_interrupt_scheme(adapter); 9963 9964 ixgbe_defrag_macvlan_pools(dev); 9965 9966 if (netif_running(dev)) 9967 return ixgbe_open(dev); 9968 9969 return 0; 9970 } 9971 9972 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, 9973 struct tc_cls_u32_offload *cls) 9974 { 9975 u32 hdl = cls->knode.handle; 9976 u32 uhtid = TC_U32_USERHTID(cls->knode.handle); 9977 u32 loc = cls->knode.handle & 0xfffff; 9978 int err = 0, i, j; 9979 struct ixgbe_jump_table *jump = NULL; 9980 9981 if (loc > IXGBE_MAX_HW_ENTRIES) 9982 return -EINVAL; 9983 9984 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) 9985 return -EINVAL; 9986 9987 /* Clear this filter in the link data it is associated with */ 9988 if (uhtid != 0x800) { 9989 jump = adapter->jump_tables[uhtid]; 9990 if (!jump) 9991 return -EINVAL; 9992 if (!test_bit(loc - 1, jump->child_loc_map)) 9993 return -EINVAL; 9994 clear_bit(loc - 1, jump->child_loc_map); 9995 } 9996 9997 /* Check if the filter being deleted is a link */ 9998 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 9999 jump = adapter->jump_tables[i]; 10000 if (jump && jump->link_hdl == hdl) { 10001 /* Delete filters in the hardware in the child hash 10002 * table associated with this link 10003 */ 10004 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) { 10005 if (!test_bit(j, jump->child_loc_map)) 10006 continue; 10007 spin_lock(&adapter->fdir_perfect_lock); 10008 err = ixgbe_update_ethtool_fdir_entry(adapter, 10009 NULL, 10010 j + 1); 10011 spin_unlock(&adapter->fdir_perfect_lock); 10012 clear_bit(j, jump->child_loc_map); 10013 } 10014 /* Remove resources for this link */ 10015 kfree(jump->input); 10016 kfree(jump->mask); 10017 kfree(jump); 10018 adapter->jump_tables[i] = NULL; 10019 return err; 10020 } 10021 } 10022 10023 spin_lock(&adapter->fdir_perfect_lock); 10024 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); 10025 spin_unlock(&adapter->fdir_perfect_lock); 10026 return err; 10027 } 10028 10029 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, 10030 struct tc_cls_u32_offload *cls) 10031 { 10032 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 10033 10034 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 10035 return -EINVAL; 10036 10037 /* This ixgbe devices do not support hash tables at the moment 10038 * so abort when given hash tables. 10039 */ 10040 if (cls->hnode.divisor > 0) 10041 return -EINVAL; 10042 10043 set_bit(uhtid - 1, &adapter->tables); 10044 return 0; 10045 } 10046 10047 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, 10048 struct tc_cls_u32_offload *cls) 10049 { 10050 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); 10051 10052 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 10053 return -EINVAL; 10054 10055 clear_bit(uhtid - 1, &adapter->tables); 10056 return 0; 10057 } 10058 10059 #ifdef CONFIG_NET_CLS_ACT 10060 struct upper_walk_data { 10061 struct ixgbe_adapter *adapter; 10062 u64 action; 10063 int ifindex; 10064 u8 queue; 10065 }; 10066 10067 static int get_macvlan_queue(struct net_device *upper, 10068 struct netdev_nested_priv *priv) 10069 { 10070 if (netif_is_macvlan(upper)) { 10071 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper); 10072 struct ixgbe_adapter *adapter; 10073 struct upper_walk_data *data; 10074 int ifindex; 10075 10076 data = (struct upper_walk_data *)priv->data; 10077 ifindex = data->ifindex; 10078 adapter = data->adapter; 10079 if (vadapter && upper->ifindex == ifindex) { 10080 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; 10081 data->action = data->queue; 10082 return 1; 10083 } 10084 } 10085 10086 return 0; 10087 } 10088 10089 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, 10090 u8 *queue, u64 *action) 10091 { 10092 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; 10093 unsigned int num_vfs = adapter->num_vfs, vf; 10094 struct netdev_nested_priv priv; 10095 struct upper_walk_data data; 10096 struct net_device *upper; 10097 10098 /* redirect to a SRIOV VF */ 10099 for (vf = 0; vf < num_vfs; ++vf) { 10100 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); 10101 if (upper->ifindex == ifindex) { 10102 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask); 10103 *action = vf + 1; 10104 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; 10105 return 0; 10106 } 10107 } 10108 10109 /* redirect to a offloaded macvlan netdev */ 10110 data.adapter = adapter; 10111 data.ifindex = ifindex; 10112 data.action = 0; 10113 data.queue = 0; 10114 priv.data = (void *)&data; 10115 if (netdev_walk_all_upper_dev_rcu(adapter->netdev, 10116 get_macvlan_queue, &priv)) { 10117 *action = data.action; 10118 *queue = data.queue; 10119 10120 return 0; 10121 } 10122 10123 return -EINVAL; 10124 } 10125 10126 static int parse_tc_actions(struct ixgbe_adapter *adapter, 10127 struct tcf_exts *exts, u64 *action, u8 *queue) 10128 { 10129 const struct tc_action *a; 10130 int i; 10131 10132 if (!tcf_exts_has_actions(exts)) 10133 return -EINVAL; 10134 10135 tcf_exts_for_each_action(i, a, exts) { 10136 /* Drop action */ 10137 if (is_tcf_gact_shot(a)) { 10138 *action = IXGBE_FDIR_DROP_QUEUE; 10139 *queue = IXGBE_FDIR_DROP_QUEUE; 10140 return 0; 10141 } 10142 10143 /* Redirect to a VF or a offloaded macvlan */ 10144 if (is_tcf_mirred_egress_redirect(a)) { 10145 struct net_device *dev = tcf_mirred_dev(a); 10146 10147 if (!dev) 10148 return -EINVAL; 10149 return handle_redirect_action(adapter, dev->ifindex, 10150 queue, action); 10151 } 10152 10153 return -EINVAL; 10154 } 10155 10156 return -EINVAL; 10157 } 10158 #else 10159 static int parse_tc_actions(struct ixgbe_adapter *adapter, 10160 struct tcf_exts *exts, u64 *action, u8 *queue) 10161 { 10162 return -EINVAL; 10163 } 10164 #endif /* CONFIG_NET_CLS_ACT */ 10165 10166 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, 10167 union ixgbe_atr_input *mask, 10168 struct tc_cls_u32_offload *cls, 10169 struct ixgbe_mat_field *field_ptr, 10170 struct ixgbe_nexthdr *nexthdr) 10171 { 10172 int i, j, off; 10173 __be32 val, m; 10174 bool found_entry = false, found_jump_field = false; 10175 10176 for (i = 0; i < cls->knode.sel->nkeys; i++) { 10177 off = cls->knode.sel->keys[i].off; 10178 val = cls->knode.sel->keys[i].val; 10179 m = cls->knode.sel->keys[i].mask; 10180 10181 for (j = 0; field_ptr[j].val; j++) { 10182 if (field_ptr[j].off == off) { 10183 field_ptr[j].val(input, mask, (__force u32)val, 10184 (__force u32)m); 10185 input->filter.formatted.flow_type |= 10186 field_ptr[j].type; 10187 found_entry = true; 10188 break; 10189 } 10190 } 10191 if (nexthdr) { 10192 if (nexthdr->off == cls->knode.sel->keys[i].off && 10193 nexthdr->val == 10194 (__force u32)cls->knode.sel->keys[i].val && 10195 nexthdr->mask == 10196 (__force u32)cls->knode.sel->keys[i].mask) 10197 found_jump_field = true; 10198 else 10199 continue; 10200 } 10201 } 10202 10203 if (nexthdr && !found_jump_field) 10204 return -EINVAL; 10205 10206 if (!found_entry) 10207 return 0; 10208 10209 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | 10210 IXGBE_ATR_L4TYPE_MASK; 10211 10212 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) 10213 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; 10214 10215 return 0; 10216 } 10217 10218 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, 10219 struct tc_cls_u32_offload *cls) 10220 { 10221 __be16 protocol = cls->common.protocol; 10222 u32 loc = cls->knode.handle & 0xfffff; 10223 struct ixgbe_hw *hw = &adapter->hw; 10224 struct ixgbe_mat_field *field_ptr; 10225 struct ixgbe_fdir_filter *input = NULL; 10226 union ixgbe_atr_input *mask = NULL; 10227 struct ixgbe_jump_table *jump = NULL; 10228 int i, err = -EINVAL; 10229 u8 queue; 10230 u32 uhtid, link_uhtid; 10231 10232 uhtid = TC_U32_USERHTID(cls->knode.handle); 10233 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); 10234 10235 /* At the moment cls_u32 jumps to network layer and skips past 10236 * L2 headers. The canonical method to match L2 frames is to use 10237 * negative values. However this is error prone at best but really 10238 * just broken because there is no way to "know" what sort of hdr 10239 * is in front of the network layer. Fix cls_u32 to support L2 10240 * headers when needed. 10241 */ 10242 if (protocol != htons(ETH_P_IP)) 10243 return err; 10244 10245 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { 10246 e_err(drv, "Location out of range\n"); 10247 return err; 10248 } 10249 10250 /* cls u32 is a graph starting at root node 0x800. The driver tracks 10251 * links and also the fields used to advance the parser across each 10252 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map 10253 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h 10254 * To add support for new nodes update ixgbe_model.h parse structures 10255 * this function _should_ be generic try not to hardcode values here. 10256 */ 10257 if (uhtid == 0x800) { 10258 field_ptr = (adapter->jump_tables[0])->mat; 10259 } else { 10260 if (uhtid >= IXGBE_MAX_LINK_HANDLE) 10261 return err; 10262 if (!adapter->jump_tables[uhtid]) 10263 return err; 10264 field_ptr = (adapter->jump_tables[uhtid])->mat; 10265 } 10266 10267 if (!field_ptr) 10268 return err; 10269 10270 /* At this point we know the field_ptr is valid and need to either 10271 * build cls_u32 link or attach filter. Because adding a link to 10272 * a handle that does not exist is invalid and the same for adding 10273 * rules to handles that don't exist. 10274 */ 10275 10276 if (link_uhtid) { 10277 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; 10278 10279 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) 10280 return err; 10281 10282 if (!test_bit(link_uhtid - 1, &adapter->tables)) 10283 return err; 10284 10285 /* Multiple filters as links to the same hash table are not 10286 * supported. To add a new filter with the same next header 10287 * but different match/jump conditions, create a new hash table 10288 * and link to it. 10289 */ 10290 if (adapter->jump_tables[link_uhtid] && 10291 (adapter->jump_tables[link_uhtid])->link_hdl) { 10292 e_err(drv, "Link filter exists for link: %x\n", 10293 link_uhtid); 10294 return err; 10295 } 10296 10297 for (i = 0; nexthdr[i].jump; i++) { 10298 if (nexthdr[i].o != cls->knode.sel->offoff || 10299 nexthdr[i].s != cls->knode.sel->offshift || 10300 nexthdr[i].m != 10301 (__force u32)cls->knode.sel->offmask) 10302 return err; 10303 10304 jump = kzalloc_obj(*jump); 10305 if (!jump) 10306 return -ENOMEM; 10307 input = kzalloc_obj(*input); 10308 if (!input) { 10309 err = -ENOMEM; 10310 goto free_jump; 10311 } 10312 mask = kzalloc_obj(*mask); 10313 if (!mask) { 10314 err = -ENOMEM; 10315 goto free_input; 10316 } 10317 jump->input = input; 10318 jump->mask = mask; 10319 jump->link_hdl = cls->knode.handle; 10320 10321 err = ixgbe_clsu32_build_input(input, mask, cls, 10322 field_ptr, &nexthdr[i]); 10323 if (!err) { 10324 jump->mat = nexthdr[i].jump; 10325 adapter->jump_tables[link_uhtid] = jump; 10326 break; 10327 } else { 10328 kfree(mask); 10329 kfree(input); 10330 kfree(jump); 10331 } 10332 } 10333 return 0; 10334 } 10335 10336 input = kzalloc_obj(*input); 10337 if (!input) 10338 return -ENOMEM; 10339 mask = kzalloc_obj(*mask); 10340 if (!mask) { 10341 err = -ENOMEM; 10342 goto free_input; 10343 } 10344 10345 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { 10346 if ((adapter->jump_tables[uhtid])->input) 10347 memcpy(input, (adapter->jump_tables[uhtid])->input, 10348 sizeof(*input)); 10349 if ((adapter->jump_tables[uhtid])->mask) 10350 memcpy(mask, (adapter->jump_tables[uhtid])->mask, 10351 sizeof(*mask)); 10352 10353 /* Lookup in all child hash tables if this location is already 10354 * filled with a filter 10355 */ 10356 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) { 10357 struct ixgbe_jump_table *link = adapter->jump_tables[i]; 10358 10359 if (link && (test_bit(loc - 1, link->child_loc_map))) { 10360 e_err(drv, "Filter exists in location: %x\n", 10361 loc); 10362 err = -EINVAL; 10363 goto err_out; 10364 } 10365 } 10366 } 10367 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); 10368 if (err) 10369 goto err_out; 10370 10371 err = parse_tc_actions(adapter, cls->knode.exts, &input->action, 10372 &queue); 10373 if (err < 0) 10374 goto err_out; 10375 10376 input->sw_idx = loc; 10377 10378 spin_lock(&adapter->fdir_perfect_lock); 10379 10380 if (hlist_empty(&adapter->fdir_filter_list)) { 10381 memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); 10382 err = ixgbe_fdir_set_input_mask_82599(hw, mask); 10383 if (err) 10384 goto err_out_w_lock; 10385 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { 10386 err = -EINVAL; 10387 goto err_out_w_lock; 10388 } 10389 10390 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); 10391 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, 10392 input->sw_idx, queue); 10393 if (err) 10394 goto err_out_w_lock; 10395 10396 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); 10397 spin_unlock(&adapter->fdir_perfect_lock); 10398 10399 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) 10400 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map); 10401 10402 kfree(mask); 10403 return err; 10404 err_out_w_lock: 10405 spin_unlock(&adapter->fdir_perfect_lock); 10406 err_out: 10407 kfree(mask); 10408 free_input: 10409 kfree(input); 10410 free_jump: 10411 kfree(jump); 10412 return err; 10413 } 10414 10415 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter, 10416 struct tc_cls_u32_offload *cls_u32) 10417 { 10418 switch (cls_u32->command) { 10419 case TC_CLSU32_NEW_KNODE: 10420 case TC_CLSU32_REPLACE_KNODE: 10421 return ixgbe_configure_clsu32(adapter, cls_u32); 10422 case TC_CLSU32_DELETE_KNODE: 10423 return ixgbe_delete_clsu32(adapter, cls_u32); 10424 case TC_CLSU32_NEW_HNODE: 10425 case TC_CLSU32_REPLACE_HNODE: 10426 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32); 10427 case TC_CLSU32_DELETE_HNODE: 10428 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32); 10429 default: 10430 return -EOPNOTSUPP; 10431 } 10432 } 10433 10434 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 10435 void *cb_priv) 10436 { 10437 struct ixgbe_adapter *adapter = cb_priv; 10438 10439 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data)) 10440 return -EOPNOTSUPP; 10441 10442 switch (type) { 10443 case TC_SETUP_CLSU32: 10444 return ixgbe_setup_tc_cls_u32(adapter, type_data); 10445 default: 10446 return -EOPNOTSUPP; 10447 } 10448 } 10449 10450 static int ixgbe_setup_tc_mqprio(struct net_device *dev, 10451 struct tc_mqprio_qopt *mqprio) 10452 { 10453 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 10454 return ixgbe_setup_tc(dev, mqprio->num_tc); 10455 } 10456 10457 static LIST_HEAD(ixgbe_block_cb_list); 10458 10459 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type, 10460 void *type_data) 10461 { 10462 struct ixgbe_adapter *adapter = ixgbe_from_netdev(dev); 10463 10464 switch (type) { 10465 case TC_SETUP_BLOCK: 10466 return flow_block_cb_setup_simple(type_data, 10467 &ixgbe_block_cb_list, 10468 ixgbe_setup_tc_block_cb, 10469 adapter, adapter, true); 10470 case TC_SETUP_QDISC_MQPRIO: 10471 return ixgbe_setup_tc_mqprio(dev, type_data); 10472 default: 10473 return -EOPNOTSUPP; 10474 } 10475 } 10476 10477 #ifdef CONFIG_PCI_IOV 10478 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) 10479 { 10480 struct net_device *netdev = adapter->netdev; 10481 10482 rtnl_lock(); 10483 ixgbe_setup_tc(netdev, adapter->hw_tcs); 10484 rtnl_unlock(); 10485 } 10486 10487 #endif 10488 void ixgbe_do_reset(struct net_device *netdev) 10489 { 10490 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 10491 10492 if (netif_running(netdev)) 10493 ixgbe_reinit_locked(adapter); 10494 else 10495 ixgbe_reset(adapter); 10496 } 10497 10498 static netdev_features_t ixgbe_fix_features(struct net_device *netdev, 10499 netdev_features_t features) 10500 { 10501 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 10502 10503 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 10504 if (!(features & NETIF_F_RXCSUM)) 10505 features &= ~NETIF_F_LRO; 10506 10507 /* Turn off LRO if not RSC capable */ 10508 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) 10509 features &= ~NETIF_F_LRO; 10510 10511 if (adapter->xdp_prog && (features & NETIF_F_LRO)) { 10512 e_dev_err("LRO is not supported with XDP\n"); 10513 features &= ~NETIF_F_LRO; 10514 } 10515 10516 return features; 10517 } 10518 10519 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter) 10520 { 10521 int rss = min_t(int, ixgbe_max_rss_indices(adapter), 10522 num_online_cpus()); 10523 10524 /* go back to full RSS if we're not running SR-IOV */ 10525 if (!adapter->ring_feature[RING_F_VMDQ].offset) 10526 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED | 10527 IXGBE_FLAG_SRIOV_ENABLED); 10528 10529 adapter->ring_feature[RING_F_RSS].limit = rss; 10530 adapter->ring_feature[RING_F_VMDQ].limit = 1; 10531 10532 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs); 10533 } 10534 10535 static int ixgbe_set_features(struct net_device *netdev, 10536 netdev_features_t features) 10537 { 10538 struct ixgbe_adapter *adapter = ixgbe_from_netdev(netdev); 10539 netdev_features_t changed = netdev->features ^ features; 10540 bool need_reset = false; 10541 10542 /* Make sure RSC matches LRO, reset if change */ 10543 if (!(features & NETIF_F_LRO)) { 10544 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 10545 need_reset = true; 10546 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; 10547 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && 10548 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { 10549 if (adapter->rx_itr_setting == 1 || 10550 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { 10551 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; 10552 need_reset = true; 10553 } else if ((changed ^ features) & NETIF_F_LRO) { 10554 e_info(probe, "rx-usecs set too low, " 10555 "disabling RSC\n"); 10556 } 10557 } 10558 10559 /* 10560 * Check if Flow Director n-tuple support or hw_tc support was 10561 * enabled or disabled. If the state changed, we need to reset. 10562 */ 10563 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { 10564 /* turn off ATR, enable perfect filters and reset */ 10565 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) 10566 need_reset = true; 10567 10568 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; 10569 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 10570 } else { 10571 /* turn off perfect filters, enable ATR and reset */ 10572 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) 10573 need_reset = true; 10574 10575 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; 10576 10577 /* We cannot enable ATR if SR-IOV is enabled */ 10578 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || 10579 /* We cannot enable ATR if we have 2 or more tcs */ 10580 (adapter->hw_tcs > 1) || 10581 /* We cannot enable ATR if RSS is disabled */ 10582 (adapter->ring_feature[RING_F_RSS].limit <= 1) || 10583 /* A sample rate of 0 indicates ATR disabled */ 10584 (!adapter->atr_sample_rate)) 10585 ; /* do nothing not supported */ 10586 else /* otherwise supported and set the flag */ 10587 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; 10588 } 10589 10590 if (changed & NETIF_F_RXALL) 10591 need_reset = true; 10592 10593 netdev->features = features; 10594 10595 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1) 10596 ixgbe_reset_l2fw_offload(adapter); 10597 else if (need_reset) 10598 ixgbe_do_reset(netdev); 10599 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | 10600 NETIF_F_HW_VLAN_CTAG_FILTER)) 10601 ixgbe_set_rx_mode(netdev); 10602 10603 return 1; 10604 } 10605 10606 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 10607 struct net_device *dev, 10608 const unsigned char *addr, u16 vid, 10609 u16 flags, bool *notified, 10610 struct netlink_ext_ack *extack) 10611 { 10612 /* guarantee we can provide a unique filter for the unicast address */ 10613 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { 10614 struct ixgbe_adapter *adapter = ixgbe_from_netdev(dev); 10615 u16 pool = VMDQ_P(0); 10616 10617 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) 10618 return -ENOMEM; 10619 } 10620 10621 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); 10622 } 10623 10624 /** 10625 * ixgbe_configure_bridge_mode - set various bridge modes 10626 * @adapter: the private structure 10627 * @mode: requested bridge mode 10628 * 10629 * Configure some settings require for various bridge modes. 10630 **/ 10631 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, 10632 __u16 mode) 10633 { 10634 struct ixgbe_hw *hw = &adapter->hw; 10635 unsigned int p, num_pools; 10636 u32 vmdctl; 10637 10638 switch (mode) { 10639 case BRIDGE_MODE_VEPA: 10640 /* disable Tx loopback, rely on switch hairpin mode */ 10641 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); 10642 10643 /* must enable Rx switching replication to allow multicast 10644 * packet reception on all VFs, and to enable source address 10645 * pruning. 10646 */ 10647 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 10648 vmdctl |= IXGBE_VT_CTL_REPLEN; 10649 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 10650 10651 /* enable Rx source address pruning. Note, this requires 10652 * replication to be enabled or else it does nothing. 10653 */ 10654 num_pools = adapter->num_vfs + adapter->num_rx_pools; 10655 for (p = 0; p < num_pools; p++) { 10656 if (hw->mac.ops.set_source_address_pruning) 10657 hw->mac.ops.set_source_address_pruning(hw, 10658 true, 10659 p); 10660 } 10661 break; 10662 case BRIDGE_MODE_VEB: 10663 /* enable Tx loopback for internal VF/PF communication */ 10664 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 10665 IXGBE_PFDTXGSWC_VT_LBEN); 10666 10667 /* disable Rx switching replication unless we have SR-IOV 10668 * virtual functions 10669 */ 10670 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); 10671 if (!adapter->num_vfs) 10672 vmdctl &= ~IXGBE_VT_CTL_REPLEN; 10673 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); 10674 10675 /* disable Rx source address pruning, since we don't expect to 10676 * be receiving external loopback of our transmitted frames. 10677 */ 10678 num_pools = adapter->num_vfs + adapter->num_rx_pools; 10679 for (p = 0; p < num_pools; p++) { 10680 if (hw->mac.ops.set_source_address_pruning) 10681 hw->mac.ops.set_source_address_pruning(hw, 10682 false, 10683 p); 10684 } 10685 break; 10686 default: 10687 return -EINVAL; 10688 } 10689 10690 adapter->bridge_mode = mode; 10691 10692 e_info(drv, "enabling bridge mode: %s\n", 10693 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); 10694 10695 return 0; 10696 } 10697 10698 static int ixgbe_ndo_bridge_setlink(struct net_device *dev, 10699 struct nlmsghdr *nlh, u16 flags, 10700 struct netlink_ext_ack *extack) 10701 { 10702 struct ixgbe_adapter *adapter = ixgbe_from_netdev(dev); 10703 struct nlattr *attr, *br_spec; 10704 int rem; 10705 10706 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10707 return -EOPNOTSUPP; 10708 10709 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 10710 if (!br_spec) 10711 return -EINVAL; 10712 10713 nla_for_each_nested_type(attr, IFLA_BRIDGE_MODE, br_spec, rem) { 10714 __u16 mode = nla_get_u16(attr); 10715 int status = ixgbe_configure_bridge_mode(adapter, mode); 10716 10717 if (status) 10718 return status; 10719 10720 break; 10721 } 10722 10723 return 0; 10724 } 10725 10726 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 10727 struct net_device *dev, 10728 u32 filter_mask, int nlflags) 10729 { 10730 struct ixgbe_adapter *adapter = ixgbe_from_netdev(dev); 10731 10732 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) 10733 return 0; 10734 10735 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 10736 adapter->bridge_mode, 0, 0, nlflags, 10737 filter_mask, NULL); 10738 } 10739 10740 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) 10741 { 10742 struct ixgbe_adapter *adapter = ixgbe_from_netdev(pdev); 10743 struct ixgbe_fwd_adapter *accel; 10744 int tcs = adapter->hw_tcs ? : 1; 10745 int pool, err; 10746 10747 if (adapter->xdp_prog) { 10748 e_warn(probe, "L2FW offload is not supported with XDP\n"); 10749 return ERR_PTR(-EINVAL); 10750 } 10751 10752 /* The hardware supported by ixgbe only filters on the destination MAC 10753 * address. In order to avoid issues we only support offloading modes 10754 * where the hardware can actually provide the functionality. 10755 */ 10756 if (!macvlan_supports_dest_filter(vdev)) 10757 return ERR_PTR(-EMEDIUMTYPE); 10758 10759 /* We need to lock down the macvlan to be a single queue device so that 10760 * we can reuse the tc_to_txq field in the macvlan netdev to represent 10761 * the queue mapping to our netdev. 10762 */ 10763 if (netif_is_multiqueue(vdev)) 10764 return ERR_PTR(-ERANGE); 10765 10766 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools); 10767 if (pool == adapter->num_rx_pools) { 10768 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools; 10769 u16 reserved_pools; 10770 10771 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && 10772 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) || 10773 adapter->num_rx_pools > IXGBE_MAX_MACVLANS) 10774 return ERR_PTR(-EBUSY); 10775 10776 /* Hardware has a limited number of available pools. Each VF, 10777 * and the PF require a pool. Check to ensure we don't 10778 * attempt to use more then the available number of pools. 10779 */ 10780 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) 10781 return ERR_PTR(-EBUSY); 10782 10783 /* Enable VMDq flag so device will be set in VM mode */ 10784 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | 10785 IXGBE_FLAG_SRIOV_ENABLED; 10786 10787 /* Try to reserve as many queues per pool as possible, 10788 * we start with the configurations that support 4 queues 10789 * per pools, followed by 2, and then by just 1 per pool. 10790 */ 10791 if (used_pools < 32 && adapter->num_rx_pools < 16) 10792 reserved_pools = min_t(u16, 10793 32 - used_pools, 10794 16 - adapter->num_rx_pools); 10795 else if (adapter->num_rx_pools < 32) 10796 reserved_pools = min_t(u16, 10797 64 - used_pools, 10798 32 - adapter->num_rx_pools); 10799 else 10800 reserved_pools = 64 - used_pools; 10801 10802 10803 if (!reserved_pools) 10804 return ERR_PTR(-EBUSY); 10805 10806 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools; 10807 10808 /* Force reinit of ring allocation with VMDQ enabled */ 10809 err = ixgbe_setup_tc(pdev, adapter->hw_tcs); 10810 if (err) 10811 return ERR_PTR(err); 10812 10813 if (pool >= adapter->num_rx_pools) 10814 return ERR_PTR(-ENOMEM); 10815 } 10816 10817 accel = kzalloc_obj(*accel); 10818 if (!accel) 10819 return ERR_PTR(-ENOMEM); 10820 10821 set_bit(pool, adapter->fwd_bitmask); 10822 netdev_set_sb_channel(vdev, pool); 10823 accel->pool = pool; 10824 accel->netdev = vdev; 10825 10826 if (!netif_running(pdev)) 10827 return accel; 10828 10829 err = ixgbe_fwd_ring_up(adapter, accel); 10830 if (err) 10831 return ERR_PTR(err); 10832 10833 return accel; 10834 } 10835 10836 static void ixgbe_fwd_del(struct net_device *pdev, void *priv) 10837 { 10838 struct ixgbe_fwd_adapter *accel = priv; 10839 struct ixgbe_adapter *adapter = ixgbe_from_netdev(pdev); 10840 unsigned int rxbase = accel->rx_base_queue; 10841 unsigned int i; 10842 10843 /* delete unicast filter associated with offloaded interface */ 10844 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr, 10845 VMDQ_P(accel->pool)); 10846 10847 /* Allow remaining Rx packets to get flushed out of the 10848 * Rx FIFO before we drop the netdev for the ring. 10849 */ 10850 usleep_range(10000, 20000); 10851 10852 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { 10853 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i]; 10854 struct ixgbe_q_vector *qv = ring->q_vector; 10855 10856 /* Make sure we aren't processing any packets and clear 10857 * netdev to shut down the ring. 10858 */ 10859 if (netif_running(adapter->netdev)) 10860 napi_synchronize(&qv->napi); 10861 ring->netdev = NULL; 10862 } 10863 10864 /* unbind the queues and drop the subordinate channel config */ 10865 netdev_unbind_sb_channel(pdev, accel->netdev); 10866 netdev_set_sb_channel(accel->netdev, 0); 10867 10868 clear_bit(accel->pool, adapter->fwd_bitmask); 10869 kfree(accel); 10870 } 10871 10872 #define IXGBE_MAX_MAC_HDR_LEN 127 10873 #define IXGBE_MAX_NETWORK_HDR_LEN 511 10874 10875 static netdev_features_t 10876 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, 10877 netdev_features_t features) 10878 { 10879 unsigned int network_hdr_len, mac_hdr_len; 10880 10881 /* Make certain the headers can be described by a context descriptor */ 10882 mac_hdr_len = skb_network_offset(skb); 10883 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) 10884 return features & ~(NETIF_F_HW_CSUM | 10885 NETIF_F_SCTP_CRC | 10886 NETIF_F_GSO_UDP_L4 | 10887 NETIF_F_HW_VLAN_CTAG_TX | 10888 NETIF_F_TSO | 10889 NETIF_F_TSO6); 10890 10891 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); 10892 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) 10893 return features & ~(NETIF_F_HW_CSUM | 10894 NETIF_F_SCTP_CRC | 10895 NETIF_F_GSO_UDP_L4 | 10896 NETIF_F_TSO | 10897 NETIF_F_TSO6); 10898 10899 /* We can only support IPV4 TSO in tunnels if we can mangle the 10900 * inner IP ID field, so strip TSO if MANGLEID is not supported. 10901 * IPsec offoad sets skb->encapsulation but still can handle 10902 * the TSO, so it's the exception. 10903 */ 10904 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) { 10905 #ifdef CONFIG_IXGBE_IPSEC 10906 if (!secpath_exists(skb)) 10907 #endif 10908 features &= ~NETIF_F_TSO; 10909 } 10910 10911 return features; 10912 } 10913 10914 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog) 10915 { 10916 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 10917 struct ixgbe_adapter *adapter = ixgbe_from_netdev(dev); 10918 struct bpf_prog *old_prog; 10919 bool need_reset; 10920 int num_queues; 10921 10922 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) 10923 return -EINVAL; 10924 10925 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) 10926 return -EINVAL; 10927 10928 /* verify ixgbe ring attributes are sufficient for XDP */ 10929 for (i = 0; i < adapter->num_rx_queues; i++) { 10930 struct ixgbe_ring *ring = adapter->rx_ring[i]; 10931 10932 if (ring_is_rsc_enabled(ring)) 10933 return -EINVAL; 10934 10935 if (frame_size > ixgbe_rx_bufsz(ring)) 10936 return -EINVAL; 10937 } 10938 10939 /* if the number of cpus is much larger than the maximum of queues, 10940 * we should stop it and then return with ENOMEM like before. 10941 */ 10942 if (nr_cpu_ids > IXGBE_MAX_XDP_QS * 2) 10943 return -ENOMEM; 10944 10945 old_prog = xchg(&adapter->xdp_prog, prog); 10946 need_reset = (!!prog != !!old_prog); 10947 10948 /* If transitioning XDP modes reconfigure rings */ 10949 if (need_reset) { 10950 int err; 10951 10952 if (!prog) 10953 /* Wait until ndo_xsk_wakeup completes. */ 10954 synchronize_rcu(); 10955 err = ixgbe_setup_tc(dev, adapter->hw_tcs); 10956 10957 if (err) 10958 return -EINVAL; 10959 if (!prog) 10960 xdp_features_clear_redirect_target(dev); 10961 } else { 10962 for (i = 0; i < adapter->num_rx_queues; i++) { 10963 WRITE_ONCE(adapter->rx_ring[i]->xdp_prog, 10964 adapter->xdp_prog); 10965 } 10966 } 10967 10968 if (old_prog) 10969 bpf_prog_put(old_prog); 10970 10971 /* Kick start the NAPI context if there is an AF_XDP socket open 10972 * on that queue id. This so that receiving will start. 10973 */ 10974 if (need_reset && prog) { 10975 num_queues = min_t(int, adapter->num_rx_queues, 10976 adapter->num_xdp_queues); 10977 for (i = 0; i < num_queues; i++) 10978 if (adapter->xdp_ring[i]->xsk_pool) 10979 (void)ixgbe_xsk_wakeup(adapter->netdev, i, 10980 XDP_WAKEUP_RX); 10981 xdp_features_set_redirect_target(dev, true); 10982 } 10983 10984 return 0; 10985 } 10986 10987 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp) 10988 { 10989 struct ixgbe_adapter *adapter = ixgbe_from_netdev(dev); 10990 10991 switch (xdp->command) { 10992 case XDP_SETUP_PROG: 10993 return ixgbe_xdp_setup(dev, xdp->prog); 10994 case XDP_SETUP_XSK_POOL: 10995 return ixgbe_xsk_pool_setup(adapter, xdp->xsk.pool, 10996 xdp->xsk.queue_id); 10997 10998 default: 10999 return -EINVAL; 11000 } 11001 } 11002 11003 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring) 11004 { 11005 /* Force memory writes to complete before letting h/w know there 11006 * are new descriptors to fetch. 11007 */ 11008 wmb(); 11009 writel(ring->next_to_use, ring->tail); 11010 } 11011 11012 void ixgbe_xdp_ring_update_tail_locked(struct ixgbe_ring *ring) 11013 { 11014 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 11015 spin_lock(&ring->tx_lock); 11016 ixgbe_xdp_ring_update_tail(ring); 11017 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 11018 spin_unlock(&ring->tx_lock); 11019 } 11020 11021 static int ixgbe_xdp_xmit(struct net_device *dev, int n, 11022 struct xdp_frame **frames, u32 flags) 11023 { 11024 struct ixgbe_adapter *adapter = ixgbe_from_netdev(dev); 11025 struct ixgbe_ring *ring; 11026 int nxmit = 0; 11027 int i; 11028 11029 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state))) 11030 return -ENETDOWN; 11031 11032 if (!netif_carrier_ok(adapter->netdev) || 11033 !netif_running(adapter->netdev)) 11034 return -ENETDOWN; 11035 11036 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 11037 return -EINVAL; 11038 11039 /* During program transitions its possible adapter->xdp_prog is assigned 11040 * but ring has not been configured yet. In this case simply abort xmit. 11041 */ 11042 ring = adapter->xdp_prog ? ixgbe_determine_xdp_ring(adapter) : NULL; 11043 if (unlikely(!ring)) 11044 return -ENXIO; 11045 11046 if (unlikely(test_bit(__IXGBE_TX_DISABLED, ring->state))) 11047 return -ENXIO; 11048 11049 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 11050 spin_lock(&ring->tx_lock); 11051 11052 for (i = 0; i < n; i++) { 11053 struct xdp_frame *xdpf = frames[i]; 11054 int err; 11055 11056 err = ixgbe_xmit_xdp_ring(ring, xdpf); 11057 if (err != IXGBE_XDP_TX) 11058 break; 11059 nxmit++; 11060 } 11061 11062 if (unlikely(flags & XDP_XMIT_FLUSH)) 11063 ixgbe_xdp_ring_update_tail(ring); 11064 11065 if (static_branch_unlikely(&ixgbe_xdp_locking_key)) 11066 spin_unlock(&ring->tx_lock); 11067 11068 return nxmit; 11069 } 11070 11071 static const struct net_device_ops ixgbe_netdev_ops = { 11072 .ndo_open = ixgbe_open, 11073 .ndo_stop = ixgbe_close, 11074 .ndo_start_xmit = ixgbe_xmit_frame, 11075 .ndo_set_rx_mode = ixgbe_set_rx_mode, 11076 .ndo_validate_addr = eth_validate_addr, 11077 .ndo_set_mac_address = ixgbe_set_mac, 11078 .ndo_change_mtu = ixgbe_change_mtu, 11079 .ndo_tx_timeout = ixgbe_tx_timeout, 11080 .ndo_set_tx_maxrate = ixgbe_tx_maxrate, 11081 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, 11082 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, 11083 .ndo_eth_ioctl = ixgbe_ioctl, 11084 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, 11085 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, 11086 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, 11087 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, 11088 .ndo_set_vf_link_state = ixgbe_ndo_set_vf_link_state, 11089 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, 11090 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, 11091 .ndo_get_vf_config = ixgbe_ndo_get_vf_config, 11092 .ndo_get_vf_stats = ixgbe_ndo_get_vf_stats, 11093 .ndo_get_stats64 = ixgbe_get_stats64, 11094 .ndo_setup_tc = __ixgbe_setup_tc, 11095 #ifdef IXGBE_FCOE 11096 .ndo_select_queue = ixgbe_select_queue, 11097 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, 11098 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, 11099 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, 11100 .ndo_fcoe_enable = ixgbe_fcoe_enable, 11101 .ndo_fcoe_disable = ixgbe_fcoe_disable, 11102 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, 11103 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, 11104 #endif /* IXGBE_FCOE */ 11105 .ndo_set_features = ixgbe_set_features, 11106 .ndo_fix_features = ixgbe_fix_features, 11107 .ndo_fdb_add = ixgbe_ndo_fdb_add, 11108 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, 11109 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, 11110 .ndo_dfwd_add_station = ixgbe_fwd_add, 11111 .ndo_dfwd_del_station = ixgbe_fwd_del, 11112 .ndo_features_check = ixgbe_features_check, 11113 .ndo_bpf = ixgbe_xdp, 11114 .ndo_xdp_xmit = ixgbe_xdp_xmit, 11115 .ndo_xsk_wakeup = ixgbe_xsk_wakeup, 11116 .ndo_hwtstamp_get = ixgbe_ptp_hwtstamp_get, 11117 .ndo_hwtstamp_set = ixgbe_ptp_hwtstamp_set, 11118 }; 11119 11120 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter, 11121 struct ixgbe_ring *tx_ring) 11122 { 11123 unsigned long wait_delay, delay_interval; 11124 struct ixgbe_hw *hw = &adapter->hw; 11125 u8 reg_idx = tx_ring->reg_idx; 11126 int wait_loop; 11127 u32 txdctl; 11128 11129 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); 11130 11131 /* delay mechanism from ixgbe_disable_tx */ 11132 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 11133 11134 wait_loop = IXGBE_MAX_RX_DESC_POLL; 11135 wait_delay = delay_interval; 11136 11137 while (wait_loop--) { 11138 usleep_range(wait_delay, wait_delay + 10); 11139 wait_delay += delay_interval * 2; 11140 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); 11141 11142 if (!(txdctl & IXGBE_TXDCTL_ENABLE)) 11143 return; 11144 } 11145 11146 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n"); 11147 } 11148 11149 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter, 11150 struct ixgbe_ring *tx_ring) 11151 { 11152 set_bit(__IXGBE_TX_DISABLED, tx_ring->state); 11153 ixgbe_disable_txr_hw(adapter, tx_ring); 11154 } 11155 11156 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter, 11157 struct ixgbe_ring *rx_ring) 11158 { 11159 unsigned long wait_delay, delay_interval; 11160 struct ixgbe_hw *hw = &adapter->hw; 11161 u8 reg_idx = rx_ring->reg_idx; 11162 int wait_loop; 11163 u32 rxdctl; 11164 11165 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 11166 rxdctl &= ~IXGBE_RXDCTL_ENABLE; 11167 rxdctl |= IXGBE_RXDCTL_SWFLSH; 11168 11169 /* write value back with RXDCTL.ENABLE bit cleared */ 11170 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); 11171 11172 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */ 11173 if (hw->mac.type == ixgbe_mac_82598EB && 11174 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) 11175 return; 11176 11177 /* delay mechanism from ixgbe_disable_rx */ 11178 delay_interval = ixgbe_get_completion_timeout(adapter) / 100; 11179 11180 wait_loop = IXGBE_MAX_RX_DESC_POLL; 11181 wait_delay = delay_interval; 11182 11183 while (wait_loop--) { 11184 usleep_range(wait_delay, wait_delay + 10); 11185 wait_delay += delay_interval * 2; 11186 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); 11187 11188 if (!(rxdctl & IXGBE_RXDCTL_ENABLE)) 11189 return; 11190 } 11191 11192 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n"); 11193 } 11194 11195 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring) 11196 { 11197 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats)); 11198 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats)); 11199 } 11200 11201 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring) 11202 { 11203 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats)); 11204 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats)); 11205 } 11206 11207 /** 11208 * ixgbe_irq_disable_single - Disable single IRQ vector 11209 * @adapter: adapter structure 11210 * @ring: ring index 11211 **/ 11212 static void ixgbe_irq_disable_single(struct ixgbe_adapter *adapter, u32 ring) 11213 { 11214 struct ixgbe_hw *hw = &adapter->hw; 11215 u64 qmask = BIT_ULL(ring); 11216 u32 mask; 11217 11218 switch (adapter->hw.mac.type) { 11219 case ixgbe_mac_82598EB: 11220 mask = qmask & IXGBE_EIMC_RTX_QUEUE; 11221 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask); 11222 break; 11223 case ixgbe_mac_82599EB: 11224 case ixgbe_mac_X540: 11225 case ixgbe_mac_X550: 11226 case ixgbe_mac_X550EM_x: 11227 case ixgbe_mac_x550em_a: 11228 mask = (qmask & 0xFFFFFFFF); 11229 if (mask) 11230 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 11231 mask = (qmask >> 32); 11232 if (mask) 11233 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 11234 break; 11235 default: 11236 break; 11237 } 11238 IXGBE_WRITE_FLUSH(&adapter->hw); 11239 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) 11240 synchronize_irq(adapter->msix_entries[ring].vector); 11241 else 11242 synchronize_irq(adapter->pdev->irq); 11243 } 11244 11245 /** 11246 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings 11247 * @adapter: adapter structure 11248 * @ring: ring index 11249 * 11250 * This function disables a certain Rx/Tx/XDP Tx ring. The function 11251 * assumes that the netdev is running. 11252 **/ 11253 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring) 11254 { 11255 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 11256 11257 rx_ring = adapter->rx_ring[ring]; 11258 tx_ring = adapter->tx_ring[ring]; 11259 xdp_ring = adapter->xdp_ring[ring]; 11260 11261 ixgbe_irq_disable_single(adapter, ring); 11262 11263 /* Rx/Tx/XDP Tx share the same napi context. */ 11264 napi_disable(&rx_ring->q_vector->napi); 11265 11266 ixgbe_disable_txr(adapter, tx_ring); 11267 if (xdp_ring) 11268 ixgbe_disable_txr(adapter, xdp_ring); 11269 ixgbe_disable_rxr_hw(adapter, rx_ring); 11270 11271 if (xdp_ring) 11272 synchronize_rcu(); 11273 11274 ixgbe_clean_tx_ring(tx_ring); 11275 if (xdp_ring) 11276 ixgbe_clean_tx_ring(xdp_ring); 11277 ixgbe_clean_rx_ring(rx_ring); 11278 11279 ixgbe_reset_txr_stats(tx_ring); 11280 if (xdp_ring) 11281 ixgbe_reset_txr_stats(xdp_ring); 11282 ixgbe_reset_rxr_stats(rx_ring); 11283 } 11284 11285 /** 11286 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings 11287 * @adapter: adapter structure 11288 * @ring: ring index 11289 * 11290 * This function enables a certain Rx/Tx/XDP Tx ring. The function 11291 * assumes that the netdev is running. 11292 **/ 11293 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring) 11294 { 11295 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring; 11296 11297 rx_ring = adapter->rx_ring[ring]; 11298 tx_ring = adapter->tx_ring[ring]; 11299 xdp_ring = adapter->xdp_ring[ring]; 11300 11301 ixgbe_configure_tx_ring(adapter, tx_ring); 11302 if (xdp_ring) 11303 ixgbe_configure_tx_ring(adapter, xdp_ring); 11304 ixgbe_configure_rx_ring(adapter, rx_ring); 11305 11306 clear_bit(__IXGBE_TX_DISABLED, tx_ring->state); 11307 if (xdp_ring) 11308 clear_bit(__IXGBE_TX_DISABLED, xdp_ring->state); 11309 11310 /* Rx/Tx/XDP Tx share the same napi context. */ 11311 napi_enable(&rx_ring->q_vector->napi); 11312 ixgbe_irq_enable_queues(adapter, BIT_ULL(ring)); 11313 IXGBE_WRITE_FLUSH(&adapter->hw); 11314 } 11315 11316 /** 11317 * ixgbe_enumerate_functions - Get the number of ports this device has 11318 * @adapter: adapter structure 11319 * 11320 * This function enumerates the physical functions co-located on a single slot, 11321 * in order to determine how many ports a device has. This is most useful in 11322 * determining the required GT/s of PCIe bandwidth necessary for optimal 11323 * performance. 11324 **/ 11325 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) 11326 { 11327 struct pci_dev *entry, *pdev = adapter->pdev; 11328 int physfns = 0; 11329 11330 /* Some cards can not use the generic count PCIe functions method, 11331 * because they are behind a parent switch, so we hardcode these with 11332 * the correct number of functions. 11333 */ 11334 if (ixgbe_pcie_from_parent(&adapter->hw)) 11335 physfns = 4; 11336 11337 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { 11338 /* don't count virtual functions */ 11339 if (entry->is_virtfn) 11340 continue; 11341 11342 /* When the devices on the bus don't all match our device ID, 11343 * we can't reliably determine the correct number of 11344 * functions. This can occur if a function has been direct 11345 * attached to a virtual machine using VT-d, for example. In 11346 * this case, simply return -1 to indicate this. 11347 */ 11348 if ((entry->vendor != pdev->vendor) || 11349 (entry->device != pdev->device)) 11350 return -1; 11351 11352 physfns++; 11353 } 11354 11355 return physfns; 11356 } 11357 11358 /** 11359 * ixgbe_wol_supported - Check whether device supports WoL 11360 * @adapter: the adapter private structure 11361 * @device_id: the device ID 11362 * @subdevice_id: the subsystem device ID 11363 * 11364 * This function is used by probe and ethtool to determine 11365 * which devices have WoL support 11366 * 11367 **/ 11368 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, 11369 u16 subdevice_id) 11370 { 11371 struct ixgbe_hw *hw = &adapter->hw; 11372 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; 11373 11374 /* WOL not supported on 82598 */ 11375 if (hw->mac.type == ixgbe_mac_82598EB) 11376 return false; 11377 11378 /* check eeprom to see if WOL is enabled for X540 and newer */ 11379 if (hw->mac.type >= ixgbe_mac_X540) { 11380 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || 11381 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && 11382 (hw->bus.func == 0))) 11383 return true; 11384 } 11385 11386 /* WOL is determined based on device IDs for 82599 MACs */ 11387 switch (device_id) { 11388 case IXGBE_DEV_ID_82599_SFP: 11389 /* Only these subdevices could supports WOL */ 11390 switch (subdevice_id) { 11391 case IXGBE_SUBDEV_ID_82599_560FLR: 11392 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: 11393 case IXGBE_SUBDEV_ID_82599_SFP_WOL0: 11394 case IXGBE_SUBDEV_ID_82599_SFP_2OCP: 11395 /* only support first port */ 11396 if (hw->bus.func != 0) 11397 break; 11398 fallthrough; 11399 case IXGBE_SUBDEV_ID_82599_SP_560FLR: 11400 case IXGBE_SUBDEV_ID_82599_SFP: 11401 case IXGBE_SUBDEV_ID_82599_RNDC: 11402 case IXGBE_SUBDEV_ID_82599_ECNA_DP: 11403 case IXGBE_SUBDEV_ID_82599_SFP_1OCP: 11404 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: 11405 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: 11406 return true; 11407 } 11408 break; 11409 case IXGBE_DEV_ID_82599EN_SFP: 11410 /* Only these subdevices support WOL */ 11411 switch (subdevice_id) { 11412 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: 11413 return true; 11414 } 11415 break; 11416 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 11417 /* All except this subdevice support WOL */ 11418 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) 11419 return true; 11420 break; 11421 case IXGBE_DEV_ID_82599_KX4: 11422 return true; 11423 default: 11424 break; 11425 } 11426 11427 return false; 11428 } 11429 11430 /** 11431 * ixgbe_set_fw_version_e610 - Set FW version specifically on E610 adapters 11432 * @adapter: the adapter private structure 11433 * 11434 * This function is used by probe and ethtool to determine the FW version to 11435 * format to display. The FW version is taken from the EEPROM/NVM. 11436 * 11437 */ 11438 void ixgbe_set_fw_version_e610(struct ixgbe_adapter *adapter) 11439 { 11440 struct ixgbe_orom_info *orom = &adapter->hw.flash.orom; 11441 struct ixgbe_nvm_info *nvm = &adapter->hw.flash.nvm; 11442 11443 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 11444 "%x.%02x 0x%x %d.%d.%d", nvm->major, nvm->minor, 11445 nvm->eetrack, orom->major, orom->build, orom->patch); 11446 } 11447 11448 /** 11449 * ixgbe_set_fw_version - Set FW version 11450 * @adapter: the adapter private structure 11451 * 11452 * This function is used by probe and ethtool to determine the FW version to 11453 * format to display. The FW version is taken from the EEPROM/NVM. 11454 */ 11455 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter) 11456 { 11457 struct ixgbe_hw *hw = &adapter->hw; 11458 struct ixgbe_nvm_version nvm_ver; 11459 11460 if (adapter->hw.mac.type == ixgbe_mac_e610) { 11461 ixgbe_set_fw_version_e610(adapter); 11462 return; 11463 } 11464 11465 ixgbe_get_oem_prod_version(hw, &nvm_ver); 11466 if (nvm_ver.oem_valid) { 11467 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 11468 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor, 11469 nvm_ver.oem_release); 11470 return; 11471 } 11472 11473 ixgbe_get_etk_id(hw, &nvm_ver); 11474 ixgbe_get_orom_version(hw, &nvm_ver); 11475 11476 if (nvm_ver.or_valid) { 11477 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 11478 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major, 11479 nvm_ver.or_build, nvm_ver.or_patch); 11480 return; 11481 } 11482 11483 /* Set ETrack ID format */ 11484 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id), 11485 "0x%08x", nvm_ver.etk_id); 11486 } 11487 11488 /** 11489 * ixgbe_recovery_probe - Handle FW recovery mode during probe 11490 * @adapter: the adapter private structure 11491 * 11492 * Perform limited driver initialization when FW error is detected. 11493 * 11494 * Return: 0 on successful probe for E610, -EIO if recovery mode is detected 11495 * for non-E610 adapter, error status code on any other case. 11496 */ 11497 static int ixgbe_recovery_probe(struct ixgbe_adapter *adapter) 11498 { 11499 struct pci_dev *pdev = adapter->pdev; 11500 struct ixgbe_hw *hw = &adapter->hw; 11501 int err = -EIO; 11502 11503 if (hw->mac.type != ixgbe_mac_e610) 11504 return err; 11505 11506 ixgbe_get_hw_control(adapter); 11507 err = ixgbe_get_flash_data(&adapter->hw); 11508 if (err) 11509 goto err_release_hw_control; 11510 11511 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 11512 INIT_WORK(&adapter->service_task, ixgbe_recovery_service_task); 11513 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 11514 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 11515 11516 if (hw->mac.ops.get_bus_info) 11517 hw->mac.ops.get_bus_info(hw); 11518 11519 pci_set_drvdata(pdev, adapter); 11520 /* We are creating devlink interface so NIC can be managed, 11521 * e.g. new NVM image loaded 11522 */ 11523 devl_lock(adapter->devlink); 11524 ixgbe_devlink_register_port(adapter); 11525 SET_NETDEV_DEVLINK_PORT(adapter->netdev, 11526 &adapter->devlink_port); 11527 ixgbe_devlink_init_regions(adapter); 11528 devl_register(adapter->devlink); 11529 devl_unlock(adapter->devlink); 11530 11531 return 0; 11532 err_release_hw_control: 11533 ixgbe_release_hw_control(adapter); 11534 return err; 11535 } 11536 11537 /** 11538 * ixgbe_probe - Device Initialization Routine 11539 * @pdev: PCI device information struct 11540 * @ent: entry in ixgbe_pci_tbl 11541 * 11542 * Returns 0 on success, negative on failure 11543 * 11544 * ixgbe_probe initializes an adapter identified by a pci_dev structure. 11545 * The OS initialization, configuring of the adapter private structure, 11546 * and a hardware reset occur. 11547 **/ 11548 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 11549 { 11550 struct net_device *netdev; 11551 struct ixgbe_netdevice_priv *netdev_priv_wrapper; 11552 struct ixgbe_adapter *adapter = NULL; 11553 struct ixgbe_hw *hw; 11554 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; 11555 unsigned int indices = MAX_TX_QUEUES; 11556 u8 part_str[IXGBE_PBANUM_LENGTH]; 11557 int i, err, expected_gts; 11558 bool disable_dev = false; 11559 #ifdef IXGBE_FCOE 11560 u16 device_caps; 11561 #endif 11562 u32 eec; 11563 11564 /* Catch broken hardware that put the wrong VF device ID in 11565 * the PCIe SR-IOV capability. 11566 */ 11567 if (pdev->is_virtfn) { 11568 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 11569 pci_name(pdev), pdev->vendor, pdev->device); 11570 return -EINVAL; 11571 } 11572 11573 err = pci_enable_device_mem(pdev); 11574 if (err) 11575 return err; 11576 11577 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 11578 if (err) { 11579 dev_err(&pdev->dev, 11580 "No usable DMA configuration, aborting\n"); 11581 goto err_dma; 11582 } 11583 11584 err = pci_request_mem_regions(pdev, ixgbe_driver_name); 11585 if (err) { 11586 dev_err(&pdev->dev, 11587 "pci_request_selected_regions failed 0x%x\n", err); 11588 goto err_pci_reg; 11589 } 11590 11591 pci_set_master(pdev); 11592 pci_save_state(pdev); 11593 11594 if (ii->mac == ixgbe_mac_82598EB) { 11595 #ifdef CONFIG_IXGBE_DCB 11596 /* 8 TC w/ 4 queues per TC */ 11597 indices = 4 * MAX_TRAFFIC_CLASS; 11598 #else 11599 indices = IXGBE_MAX_RSS_INDICES; 11600 #endif 11601 } else if (ii->mac == ixgbe_mac_e610) { 11602 indices = IXGBE_MAX_RSS_INDICES_X550; 11603 } 11604 11605 adapter = ixgbe_allocate_devlink(&pdev->dev); 11606 if (IS_ERR(adapter)) { 11607 err = PTR_ERR(adapter); 11608 goto err_devlink; 11609 } 11610 11611 netdev = alloc_etherdev_mq(sizeof(*netdev_priv_wrapper), indices); 11612 if (!netdev) { 11613 err = -ENOMEM; 11614 goto err_alloc_etherdev; 11615 } 11616 11617 SET_NETDEV_DEV(netdev, &pdev->dev); 11618 11619 netdev_priv_wrapper = netdev_priv(netdev); 11620 netdev_priv_wrapper->adapter = adapter; 11621 11622 adapter->netdev = netdev; 11623 adapter->pdev = pdev; 11624 hw = &adapter->hw; 11625 hw->back = adapter; 11626 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 11627 11628 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), 11629 pci_resource_len(pdev, 0)); 11630 adapter->io_addr = hw->hw_addr; 11631 if (!hw->hw_addr) { 11632 err = -EIO; 11633 goto err_ioremap; 11634 } 11635 11636 /* Setup hw api */ 11637 hw->mac.ops = *ii->mac_ops; 11638 hw->mac.type = ii->mac; 11639 hw->mvals = ii->mvals; 11640 if (ii->link_ops) 11641 hw->link.ops = *ii->link_ops; 11642 11643 /* EEPROM */ 11644 hw->eeprom.ops = *ii->eeprom_ops; 11645 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 11646 if (ixgbe_removed(hw->hw_addr)) { 11647 err = -EIO; 11648 goto err_ioremap; 11649 } 11650 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ 11651 if (!(eec & BIT(8))) 11652 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; 11653 11654 /* PHY */ 11655 hw->phy.ops = *ii->phy_ops; 11656 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 11657 /* ixgbe_identify_phy_generic will set prtad and mmds properly */ 11658 hw->phy.mdio.prtad = MDIO_PRTAD_NONE; 11659 hw->phy.mdio.mmds = 0; 11660 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; 11661 hw->phy.mdio.dev = netdev; 11662 hw->phy.mdio.mdio_read = ixgbe_mdio_read; 11663 hw->phy.mdio.mdio_write = ixgbe_mdio_write; 11664 11665 netdev->netdev_ops = &ixgbe_netdev_ops; 11666 ixgbe_set_ethtool_ops(netdev); 11667 netdev->watchdog_timeo = 5 * HZ; 11668 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); 11669 11670 /* setup the private structure */ 11671 err = ixgbe_sw_init(adapter, ii); 11672 if (err) 11673 goto err_sw_init; 11674 11675 if (ixgbe_check_fw_error(adapter)) { 11676 err = ixgbe_recovery_probe(adapter); 11677 if (err) 11678 goto err_sw_init; 11679 11680 return 0; 11681 } 11682 11683 if (adapter->hw.mac.type == ixgbe_mac_e610) { 11684 err = ixgbe_get_caps(&adapter->hw); 11685 if (err) 11686 dev_err(&pdev->dev, "ixgbe_get_caps failed %d\n", err); 11687 11688 err = ixgbe_get_flash_data(&adapter->hw); 11689 if (err) 11690 goto err_sw_init; 11691 } 11692 11693 if (adapter->hw.mac.type == ixgbe_mac_82599EB) 11694 adapter->flags2 |= IXGBE_FLAG2_AUTO_DISABLE_VF; 11695 11696 switch (adapter->hw.mac.type) { 11697 case ixgbe_mac_X550: 11698 case ixgbe_mac_X550EM_x: 11699 case ixgbe_mac_e610: 11700 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550; 11701 break; 11702 case ixgbe_mac_x550em_a: 11703 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a; 11704 break; 11705 default: 11706 break; 11707 } 11708 11709 /* Make it possible the adapter to be woken up via WOL */ 11710 switch (adapter->hw.mac.type) { 11711 case ixgbe_mac_82599EB: 11712 case ixgbe_mac_X540: 11713 case ixgbe_mac_X550: 11714 case ixgbe_mac_X550EM_x: 11715 case ixgbe_mac_x550em_a: 11716 case ixgbe_mac_e610: 11717 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 11718 break; 11719 default: 11720 break; 11721 } 11722 11723 /* 11724 * If there is a fan on this device and it has failed log the 11725 * failure. 11726 */ 11727 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { 11728 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 11729 if (esdp & IXGBE_ESDP_SDP1) 11730 e_crit(probe, "Fan has stopped, replace the adapter\n"); 11731 } 11732 11733 if (allow_unsupported_sfp) 11734 hw->allow_unsupported_sfp = allow_unsupported_sfp; 11735 11736 /* reset_hw fills in the perm_addr as well */ 11737 hw->phy.reset_if_overtemp = true; 11738 err = hw->mac.ops.reset_hw(hw); 11739 hw->phy.reset_if_overtemp = false; 11740 ixgbe_set_eee_capable(adapter); 11741 if (err == -ENOENT) { 11742 err = 0; 11743 } else if (err == -EOPNOTSUPP) { 11744 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); 11745 e_dev_err("Reload the driver after installing a supported module.\n"); 11746 goto err_sw_init; 11747 } else if (err) { 11748 e_dev_err("HW Init failed: %d\n", err); 11749 goto err_sw_init; 11750 } 11751 11752 #ifdef CONFIG_PCI_IOV 11753 /* SR-IOV not supported on the 82598 */ 11754 if (adapter->hw.mac.type == ixgbe_mac_82598EB) 11755 goto skip_sriov; 11756 /* Mailbox */ 11757 ixgbe_init_mbx_params_pf(hw); 11758 hw->mbx.ops = ii->mbx_ops; 11759 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); 11760 ixgbe_enable_sriov(adapter, max_vfs); 11761 skip_sriov: 11762 11763 #endif 11764 netdev->features = NETIF_F_SG | 11765 NETIF_F_TSO | 11766 NETIF_F_TSO6 | 11767 NETIF_F_RXHASH | 11768 NETIF_F_RXCSUM | 11769 NETIF_F_HW_CSUM; 11770 11771 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ 11772 NETIF_F_GSO_GRE_CSUM | \ 11773 NETIF_F_GSO_IPXIP4 | \ 11774 NETIF_F_GSO_IPXIP6 | \ 11775 NETIF_F_GSO_UDP_TUNNEL | \ 11776 NETIF_F_GSO_UDP_TUNNEL_CSUM) 11777 11778 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; 11779 netdev->features |= NETIF_F_GSO_PARTIAL | 11780 IXGBE_GSO_PARTIAL_FEATURES; 11781 11782 if (hw->mac.type >= ixgbe_mac_82599EB) 11783 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4; 11784 11785 #ifdef CONFIG_IXGBE_IPSEC 11786 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \ 11787 NETIF_F_HW_ESP_TX_CSUM | \ 11788 NETIF_F_GSO_ESP) 11789 11790 if (adapter->ipsec) 11791 netdev->features |= IXGBE_ESP_FEATURES; 11792 #endif 11793 /* copy netdev features into list of user selectable features */ 11794 netdev->hw_features |= netdev->features | 11795 NETIF_F_HW_VLAN_CTAG_FILTER | 11796 NETIF_F_HW_VLAN_CTAG_RX | 11797 NETIF_F_HW_VLAN_CTAG_TX | 11798 NETIF_F_RXALL | 11799 NETIF_F_HW_L2FW_DOFFLOAD; 11800 11801 if (hw->mac.type >= ixgbe_mac_82599EB) 11802 netdev->hw_features |= NETIF_F_NTUPLE | 11803 NETIF_F_HW_TC; 11804 11805 netdev->features |= NETIF_F_HIGHDMA; 11806 11807 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 11808 netdev->hw_enc_features |= netdev->vlan_features; 11809 netdev->mpls_features |= NETIF_F_SG | 11810 NETIF_F_TSO | 11811 NETIF_F_TSO6 | 11812 NETIF_F_HW_CSUM; 11813 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES; 11814 11815 /* set this bit last since it cannot be part of vlan_features */ 11816 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | 11817 NETIF_F_HW_VLAN_CTAG_RX | 11818 NETIF_F_HW_VLAN_CTAG_TX; 11819 11820 netdev->priv_flags |= IFF_UNICAST_FLT; 11821 netdev->priv_flags |= IFF_SUPP_NOFCS; 11822 11823 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 11824 NETDEV_XDP_ACT_XSK_ZEROCOPY; 11825 11826 /* MTU range: 68 - 9710 */ 11827 netdev->min_mtu = ETH_MIN_MTU; 11828 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN); 11829 11830 #ifdef CONFIG_IXGBE_DCB 11831 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) 11832 netdev->dcbnl_ops = &ixgbe_dcbnl_ops; 11833 #endif 11834 11835 #ifdef IXGBE_FCOE 11836 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { 11837 unsigned int fcoe_l; 11838 11839 if (hw->mac.ops.get_device_caps) { 11840 hw->mac.ops.get_device_caps(hw, &device_caps); 11841 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) 11842 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; 11843 } 11844 11845 11846 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); 11847 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; 11848 11849 netdev->features |= NETIF_F_FSO | 11850 NETIF_F_FCOE_CRC; 11851 11852 netdev->vlan_features |= NETIF_F_FSO | 11853 NETIF_F_FCOE_CRC; 11854 } 11855 #endif /* IXGBE_FCOE */ 11856 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) 11857 netdev->hw_features |= NETIF_F_LRO; 11858 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) 11859 netdev->features |= NETIF_F_LRO; 11860 11861 /* make sure the EEPROM is good */ 11862 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { 11863 e_dev_err("The EEPROM Checksum Is Not Valid\n"); 11864 err = -EIO; 11865 goto err_sw_init; 11866 } 11867 11868 eth_platform_get_mac_address(&adapter->pdev->dev, 11869 adapter->hw.mac.perm_addr); 11870 11871 eth_hw_addr_set(netdev, hw->mac.perm_addr); 11872 11873 if (!is_valid_ether_addr(netdev->dev_addr)) { 11874 e_dev_err("invalid MAC address\n"); 11875 err = -EIO; 11876 goto err_sw_init; 11877 } 11878 11879 /* Set hw->mac.addr to permanent MAC address */ 11880 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); 11881 ixgbe_mac_set_default_filter(adapter); 11882 11883 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0); 11884 11885 if (ixgbe_removed(hw->hw_addr)) { 11886 err = -EIO; 11887 goto err_sw_init; 11888 } 11889 INIT_WORK(&adapter->service_task, ixgbe_service_task); 11890 set_bit(__IXGBE_SERVICE_INITED, &adapter->state); 11891 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); 11892 11893 err = ixgbe_init_interrupt_scheme(adapter); 11894 if (err) 11895 goto err_sw_init; 11896 11897 for (i = 0; i < adapter->num_rx_queues; i++) 11898 u64_stats_init(&adapter->rx_ring[i]->syncp); 11899 for (i = 0; i < adapter->num_tx_queues; i++) 11900 u64_stats_init(&adapter->tx_ring[i]->syncp); 11901 for (i = 0; i < adapter->num_xdp_queues; i++) 11902 u64_stats_init(&adapter->xdp_ring[i]->syncp); 11903 11904 /* WOL not supported for all devices */ 11905 adapter->wol = 0; 11906 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); 11907 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, 11908 pdev->subsystem_device); 11909 if (hw->wol_enabled) 11910 adapter->wol = IXGBE_WUFC_MAG; 11911 11912 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 11913 11914 /* save off EEPROM version number */ 11915 ixgbe_set_fw_version(adapter); 11916 11917 /* pick up the PCI bus settings for reporting later */ 11918 if (ixgbe_pcie_from_parent(hw)) 11919 ixgbe_get_parent_bus_info(adapter); 11920 else 11921 hw->mac.ops.get_bus_info(hw); 11922 11923 /* calculate the expected PCIe bandwidth required for optimal 11924 * performance. Note that some older parts will never have enough 11925 * bandwidth due to being older generation PCIe parts. We clamp these 11926 * parts to ensure no warning is displayed if it can't be fixed. 11927 */ 11928 switch (hw->mac.type) { 11929 case ixgbe_mac_82598EB: 11930 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); 11931 break; 11932 default: 11933 expected_gts = ixgbe_enumerate_functions(adapter) * 10; 11934 break; 11935 } 11936 11937 /* don't check link if we failed to enumerate functions */ 11938 if (expected_gts > 0) 11939 ixgbe_check_minimum_link(adapter, expected_gts); 11940 11941 err = hw->eeprom.ops.read_pba_string(hw, part_str, sizeof(part_str)); 11942 if (err) 11943 strscpy(part_str, "Unknown", sizeof(part_str)); 11944 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 11945 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", 11946 hw->mac.type, hw->phy.type, hw->phy.sfp_type, 11947 part_str); 11948 else 11949 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", 11950 hw->mac.type, hw->phy.type, part_str); 11951 11952 e_dev_info("%pM\n", netdev->dev_addr); 11953 11954 /* reset the hardware with the new settings */ 11955 err = hw->mac.ops.start_hw(hw); 11956 if (err == -EACCES) { 11957 /* We are running on a pre-production device, log a warning */ 11958 e_dev_warn("This device is a pre-production adapter/LOM. " 11959 "Please be aware there may be issues associated " 11960 "with your hardware. If you are experiencing " 11961 "problems please contact your Intel or hardware " 11962 "representative who provided you with this " 11963 "hardware.\n"); 11964 } 11965 strcpy(netdev->name, "eth%d"); 11966 pci_set_drvdata(pdev, adapter); 11967 11968 devl_lock(adapter->devlink); 11969 ixgbe_devlink_register_port(adapter); 11970 SET_NETDEV_DEVLINK_PORT(adapter->netdev, &adapter->devlink_port); 11971 11972 err = register_netdev(netdev); 11973 if (err) 11974 goto err_register; 11975 11976 11977 /* power down the optics for 82599 SFP+ fiber */ 11978 if (hw->mac.ops.disable_tx_laser) 11979 hw->mac.ops.disable_tx_laser(hw); 11980 11981 /* carrier off reporting is important to ethtool even BEFORE open */ 11982 netif_carrier_off(netdev); 11983 11984 #ifdef CONFIG_IXGBE_DCA 11985 if (dca_add_requester(&pdev->dev) == 0) { 11986 adapter->flags |= IXGBE_FLAG_DCA_ENABLED; 11987 ixgbe_setup_dca(adapter); 11988 } 11989 #endif 11990 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { 11991 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); 11992 for (i = 0; i < adapter->num_vfs; i++) 11993 ixgbe_vf_configuration(pdev, (i | 0x10000000)); 11994 } 11995 11996 /* firmware requires driver version to be 0xFFFFFFFF 11997 * since os does not support feature 11998 */ 11999 if (hw->mac.ops.set_fw_drv_ver) 12000 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF, 12001 sizeof(UTS_RELEASE) - 1, 12002 UTS_RELEASE); 12003 12004 /* add san mac addr to netdev */ 12005 ixgbe_add_sanmac_netdev(netdev); 12006 12007 e_dev_info("%s\n", ixgbe_default_device_descr); 12008 12009 #ifdef CONFIG_IXGBE_HWMON 12010 if (ixgbe_sysfs_init(adapter)) 12011 e_err(probe, "failed to allocate sysfs resources\n"); 12012 #endif /* CONFIG_IXGBE_HWMON */ 12013 12014 ixgbe_dbg_adapter_init(adapter); 12015 12016 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ 12017 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) 12018 hw->mac.ops.setup_link(hw, 12019 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, 12020 true); 12021 12022 err = ixgbe_mii_bus_init(hw); 12023 if (err) 12024 goto err_netdev; 12025 12026 if (hw->mac.type == ixgbe_mac_e610 && 12027 (adapter->flags2 & IXGBE_FLAG2_EEE_CAPABLE)) { 12028 bool eee_enable = adapter->flags2 & IXGBE_FLAG2_EEE_ENABLED; 12029 12030 hw->mac.ops.setup_eee(hw, eee_enable); 12031 } 12032 12033 ixgbe_devlink_init_regions(adapter); 12034 devl_register(adapter->devlink); 12035 devl_unlock(adapter->devlink); 12036 12037 if (ixgbe_fwlog_init(hw)) 12038 e_dev_info("Firmware logging not supported\n"); 12039 12040 return 0; 12041 12042 err_netdev: 12043 unregister_netdev(netdev); 12044 err_register: 12045 devl_port_unregister(&adapter->devlink_port); 12046 devl_unlock(adapter->devlink); 12047 ixgbe_release_hw_control(adapter); 12048 ixgbe_clear_interrupt_scheme(adapter); 12049 err_sw_init: 12050 if (hw->mac.type == ixgbe_mac_e610) 12051 mutex_destroy(&adapter->hw.aci.lock); 12052 ixgbe_disable_sriov(adapter); 12053 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; 12054 iounmap(adapter->io_addr); 12055 kfree(adapter->jump_tables[0]); 12056 kfree(adapter->mac_table); 12057 kfree(adapter->rss_key); 12058 bitmap_free(adapter->af_xdp_zc_qps); 12059 err_ioremap: 12060 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 12061 free_netdev(netdev); 12062 err_alloc_etherdev: 12063 devlink_free(adapter->devlink); 12064 pci_release_mem_regions(pdev); 12065 err_devlink: 12066 err_pci_reg: 12067 err_dma: 12068 if (!adapter || disable_dev) 12069 pci_disable_device(pdev); 12070 return err; 12071 } 12072 12073 /** 12074 * ixgbe_remove - Device Removal Routine 12075 * @pdev: PCI device information struct 12076 * 12077 * ixgbe_remove is called by the PCI subsystem to alert the driver 12078 * that it should release a PCI device. This could be caused by a 12079 * Hot-Plug event, or because the driver is going to be removed from 12080 * memory. 12081 **/ 12082 static void ixgbe_remove(struct pci_dev *pdev) 12083 { 12084 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 12085 struct net_device *netdev; 12086 bool disable_dev; 12087 int i; 12088 12089 /* if !adapter then we already cleaned up in probe */ 12090 if (!adapter) 12091 return; 12092 12093 netdev = adapter->netdev; 12094 devl_lock(adapter->devlink); 12095 devl_unregister(adapter->devlink); 12096 ixgbe_devlink_destroy_regions(adapter); 12097 ixgbe_fwlog_deinit(&adapter->hw); 12098 ixgbe_dbg_adapter_exit(adapter); 12099 12100 set_bit(__IXGBE_REMOVING, &adapter->state); 12101 cancel_work_sync(&adapter->service_task); 12102 12103 if (adapter->hw.mac.type == ixgbe_mac_e610) 12104 ixgbe_disable_link_status_events(adapter); 12105 12106 if (adapter->mii_bus) 12107 mdiobus_unregister(adapter->mii_bus); 12108 12109 #ifdef CONFIG_IXGBE_DCA 12110 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { 12111 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; 12112 dca_remove_requester(&pdev->dev); 12113 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 12114 IXGBE_DCA_CTRL_DCA_DISABLE); 12115 } 12116 12117 #endif 12118 #ifdef CONFIG_IXGBE_HWMON 12119 ixgbe_sysfs_exit(adapter); 12120 #endif /* CONFIG_IXGBE_HWMON */ 12121 12122 /* remove the added san mac */ 12123 ixgbe_del_sanmac_netdev(netdev); 12124 12125 #ifdef CONFIG_PCI_IOV 12126 ixgbe_disable_sriov(adapter); 12127 #endif 12128 if (netdev->reg_state == NETREG_REGISTERED) 12129 unregister_netdev(netdev); 12130 12131 devl_port_unregister(&adapter->devlink_port); 12132 devl_unlock(adapter->devlink); 12133 12134 ixgbe_stop_ipsec_offload(adapter); 12135 ixgbe_clear_interrupt_scheme(adapter); 12136 12137 ixgbe_release_hw_control(adapter); 12138 12139 #ifdef CONFIG_DCB 12140 kfree(adapter->ixgbe_ieee_pfc); 12141 kfree(adapter->ixgbe_ieee_ets); 12142 12143 #endif 12144 iounmap(adapter->io_addr); 12145 pci_release_mem_regions(pdev); 12146 12147 e_dev_info("complete\n"); 12148 12149 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { 12150 if (adapter->jump_tables[i]) { 12151 kfree(adapter->jump_tables[i]->input); 12152 kfree(adapter->jump_tables[i]->mask); 12153 } 12154 kfree(adapter->jump_tables[i]); 12155 } 12156 12157 kfree(adapter->mac_table); 12158 kfree(adapter->rss_key); 12159 bitmap_free(adapter->af_xdp_zc_qps); 12160 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); 12161 free_netdev(netdev); 12162 12163 if (adapter->hw.mac.type == ixgbe_mac_e610) 12164 mutex_destroy(&adapter->hw.aci.lock); 12165 12166 if (disable_dev) 12167 pci_disable_device(pdev); 12168 12169 devlink_free(adapter->devlink); 12170 } 12171 12172 /** 12173 * ixgbe_io_error_detected - called when PCI error is detected 12174 * @pdev: Pointer to PCI device 12175 * @state: The current pci connection state 12176 * 12177 * This function is called after a PCI bus error affecting 12178 * this device has been detected. 12179 */ 12180 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, 12181 pci_channel_state_t state) 12182 { 12183 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 12184 struct net_device *netdev = adapter->netdev; 12185 12186 #ifdef CONFIG_PCI_IOV 12187 struct ixgbe_hw *hw = &adapter->hw; 12188 struct pci_dev *bdev, *vfdev; 12189 u32 dw0, dw1, dw2, dw3; 12190 int vf, pos; 12191 u16 req_id, pf_func; 12192 12193 if (adapter->hw.mac.type == ixgbe_mac_82598EB || 12194 adapter->num_vfs == 0) 12195 goto skip_bad_vf_detection; 12196 12197 bdev = pdev->bus->self; 12198 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) 12199 bdev = bdev->bus->self; 12200 12201 if (!bdev) 12202 goto skip_bad_vf_detection; 12203 12204 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); 12205 if (!pos) 12206 goto skip_bad_vf_detection; 12207 12208 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); 12209 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); 12210 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); 12211 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); 12212 if (ixgbe_removed(hw->hw_addr)) 12213 goto skip_bad_vf_detection; 12214 12215 req_id = dw1 >> 16; 12216 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ 12217 if (!(req_id & 0x0080)) 12218 goto skip_bad_vf_detection; 12219 12220 pf_func = req_id & 0x01; 12221 if ((pf_func & 1) == (pdev->devfn & 1)) { 12222 unsigned int device_id; 12223 12224 vf = FIELD_GET(0x7F, req_id); 12225 e_dev_err("VF %d has caused a PCIe error\n", vf); 12226 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " 12227 "%8.8x\tdw3: %8.8x\n", 12228 dw0, dw1, dw2, dw3); 12229 switch (adapter->hw.mac.type) { 12230 case ixgbe_mac_82599EB: 12231 device_id = IXGBE_82599_VF_DEVICE_ID; 12232 break; 12233 case ixgbe_mac_X540: 12234 device_id = IXGBE_X540_VF_DEVICE_ID; 12235 break; 12236 case ixgbe_mac_X550: 12237 device_id = IXGBE_DEV_ID_X550_VF; 12238 break; 12239 case ixgbe_mac_X550EM_x: 12240 device_id = IXGBE_DEV_ID_X550EM_X_VF; 12241 break; 12242 case ixgbe_mac_x550em_a: 12243 device_id = IXGBE_DEV_ID_X550EM_A_VF; 12244 break; 12245 case ixgbe_mac_e610: 12246 device_id = IXGBE_DEV_ID_E610_VF; 12247 break; 12248 default: 12249 device_id = 0; 12250 break; 12251 } 12252 12253 /* Find the pci device of the offending VF */ 12254 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); 12255 while (vfdev) { 12256 if (vfdev->devfn == (req_id & 0xFF)) 12257 break; 12258 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, 12259 device_id, vfdev); 12260 } 12261 /* 12262 * There's a slim chance the VF could have been hot plugged, 12263 * so if it is no longer present we don't need to issue the 12264 * VFLR. Just clean up the AER in that case. 12265 */ 12266 if (vfdev) { 12267 pcie_flr(vfdev); 12268 /* Free device reference count */ 12269 pci_dev_put(vfdev); 12270 } 12271 } 12272 12273 /* 12274 * Even though the error may have occurred on the other port 12275 * we still need to increment the vf error reference count for 12276 * both ports because the I/O resume function will be called 12277 * for both of them. 12278 */ 12279 adapter->vferr_refcount++; 12280 12281 return PCI_ERS_RESULT_RECOVERED; 12282 12283 skip_bad_vf_detection: 12284 #endif /* CONFIG_PCI_IOV */ 12285 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) 12286 return PCI_ERS_RESULT_DISCONNECT; 12287 12288 if (!netif_device_present(netdev)) 12289 return PCI_ERS_RESULT_DISCONNECT; 12290 12291 rtnl_lock(); 12292 netif_device_detach(netdev); 12293 12294 if (netif_running(netdev)) 12295 ixgbe_close_suspend(adapter); 12296 12297 if (state == pci_channel_io_perm_failure) { 12298 rtnl_unlock(); 12299 return PCI_ERS_RESULT_DISCONNECT; 12300 } 12301 12302 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) 12303 pci_disable_device(pdev); 12304 rtnl_unlock(); 12305 12306 /* Request a slot reset. */ 12307 return PCI_ERS_RESULT_NEED_RESET; 12308 } 12309 12310 /** 12311 * ixgbe_io_slot_reset - called after the pci bus has been reset. 12312 * @pdev: Pointer to PCI device 12313 * 12314 * Restart the card from scratch, as if from a cold-boot. 12315 */ 12316 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) 12317 { 12318 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 12319 pci_ers_result_t result; 12320 12321 if (pci_enable_device_mem(pdev)) { 12322 e_err(probe, "Cannot re-enable PCI device after reset.\n"); 12323 result = PCI_ERS_RESULT_DISCONNECT; 12324 } else { 12325 smp_mb__before_atomic(); 12326 clear_bit(__IXGBE_DISABLED, &adapter->state); 12327 adapter->hw.hw_addr = adapter->io_addr; 12328 pci_set_master(pdev); 12329 pci_restore_state(pdev); 12330 12331 pci_wake_from_d3(pdev, false); 12332 12333 ixgbe_reset(adapter); 12334 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); 12335 result = PCI_ERS_RESULT_RECOVERED; 12336 } 12337 12338 return result; 12339 } 12340 12341 /** 12342 * ixgbe_io_resume - called when traffic can start flowing again. 12343 * @pdev: Pointer to PCI device 12344 * 12345 * This callback is called when the error recovery driver tells us that 12346 * its OK to resume normal operation. 12347 */ 12348 static void ixgbe_io_resume(struct pci_dev *pdev) 12349 { 12350 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); 12351 struct net_device *netdev = adapter->netdev; 12352 12353 #ifdef CONFIG_PCI_IOV 12354 if (adapter->vferr_refcount) { 12355 e_info(drv, "Resuming after VF err\n"); 12356 adapter->vferr_refcount--; 12357 return; 12358 } 12359 12360 #endif 12361 rtnl_lock(); 12362 if (netif_running(netdev)) 12363 ixgbe_open(netdev); 12364 12365 netif_device_attach(netdev); 12366 rtnl_unlock(); 12367 } 12368 12369 static const struct pci_error_handlers ixgbe_err_handler = { 12370 .error_detected = ixgbe_io_error_detected, 12371 .slot_reset = ixgbe_io_slot_reset, 12372 .resume = ixgbe_io_resume, 12373 }; 12374 12375 static DEFINE_SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume); 12376 12377 static struct pci_driver ixgbe_driver = { 12378 .name = ixgbe_driver_name, 12379 .id_table = ixgbe_pci_tbl, 12380 .probe = ixgbe_probe, 12381 .remove = ixgbe_remove, 12382 .driver.pm = pm_sleep_ptr(&ixgbe_pm_ops), 12383 .shutdown = ixgbe_shutdown, 12384 .sriov_configure = ixgbe_pci_sriov_configure, 12385 .err_handler = &ixgbe_err_handler 12386 }; 12387 12388 /** 12389 * ixgbe_init_module - Driver Registration Routine 12390 * 12391 * ixgbe_init_module is the first routine called when the driver is 12392 * loaded. All it does is register with the PCI subsystem. 12393 **/ 12394 static int __init ixgbe_init_module(void) 12395 { 12396 int ret; 12397 pr_info("%s\n", ixgbe_driver_string); 12398 pr_info("%s\n", ixgbe_copyright); 12399 12400 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); 12401 if (!ixgbe_wq) { 12402 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); 12403 return -ENOMEM; 12404 } 12405 12406 ixgbe_dbg_init(); 12407 12408 ret = pci_register_driver(&ixgbe_driver); 12409 if (ret) { 12410 destroy_workqueue(ixgbe_wq); 12411 ixgbe_dbg_exit(); 12412 return ret; 12413 } 12414 12415 #ifdef CONFIG_IXGBE_DCA 12416 dca_register_notify(&dca_notifier); 12417 #endif 12418 12419 return 0; 12420 } 12421 12422 module_init(ixgbe_init_module); 12423 12424 /** 12425 * ixgbe_exit_module - Driver Exit Cleanup Routine 12426 * 12427 * ixgbe_exit_module is called just before the driver is removed 12428 * from memory. 12429 **/ 12430 static void __exit ixgbe_exit_module(void) 12431 { 12432 #ifdef CONFIG_IXGBE_DCA 12433 dca_unregister_notify(&dca_notifier); 12434 #endif 12435 pci_unregister_driver(&ixgbe_driver); 12436 12437 ixgbe_dbg_exit(); 12438 if (ixgbe_wq) { 12439 destroy_workqueue(ixgbe_wq); 12440 ixgbe_wq = NULL; 12441 } 12442 } 12443 12444 #ifdef CONFIG_IXGBE_DCA 12445 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, 12446 void *p) 12447 { 12448 int ret_val; 12449 12450 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, 12451 __ixgbe_notify_dca); 12452 12453 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 12454 } 12455 12456 #endif /* CONFIG_IXGBE_DCA */ 12457 12458 module_exit(ixgbe_exit_module); 12459 12460 /* ixgbe_main.c */ 12461