1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2003-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7 #include <linux/sched.h>
8 #include <linux/wait.h>
9 #include <linux/gfp.h>
10
11 #include "iwl-prph.h"
12 #include "iwl-io.h"
13 #include "internal.h"
14 #include "iwl-op-mode.h"
15 #include "pcie/iwl-context-info-v2.h"
16 #include "fw/dbg.h"
17
18 /******************************************************************************
19 *
20 * RX path functions
21 *
22 ******************************************************************************/
23
24 /*
25 * Rx theory of operation
26 *
27 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
28 * each of which point to Receive Buffers to be filled by the NIC. These get
29 * used not only for Rx frames, but for any command response or notification
30 * from the NIC. The driver and NIC manage the Rx buffers by means
31 * of indexes into the circular buffer.
32 *
33 * Rx Queue Indexes
34 * The host/firmware share two index registers for managing the Rx buffers.
35 *
36 * The READ index maps to the first position that the firmware may be writing
37 * to -- the driver can read up to (but not including) this position and get
38 * good data.
39 * The READ index is managed by the firmware once the card is enabled.
40 *
41 * The WRITE index maps to the last position the driver has read from -- the
42 * position preceding WRITE is the last slot the firmware can place a packet.
43 *
44 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
45 * WRITE = READ.
46 *
47 * During initialization, the host sets up the READ queue position to the first
48 * INDEX position, and WRITE to the last (READ - 1 wrapped)
49 *
50 * When the firmware places a packet in a buffer, it will advance the READ index
51 * and fire the RX interrupt. The driver can then query the READ index and
52 * process as many packets as possible, moving the WRITE index forward as it
53 * resets the Rx queue buffers with new memory.
54 *
55 * The management in the driver is as follows:
56 * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free.
57 * When the interrupt handler is called, the request is processed.
58 * The page is either stolen - transferred to the upper layer
59 * or reused - added immediately to the iwl->rxq->rx_free list.
60 * + When the page is stolen - the driver updates the matching queue's used
61 * count, detaches the RBD and transfers it to the queue used list.
62 * When there are two used RBDs - they are transferred to the allocator empty
63 * list. Work is then scheduled for the allocator to start allocating
64 * eight buffers.
65 * When there are another 6 used RBDs - they are transferred to the allocator
66 * empty list and the driver tries to claim the pre-allocated buffers and
67 * add them to iwl->rxq->rx_free. If it fails - it continues to claim them
68 * until ready.
69 * When there are 8+ buffers in the free list - either from allocation or from
70 * 8 reused unstolen pages - restock is called to update the FW and indexes.
71 * + In order to make sure the allocator always has RBDs to use for allocation
72 * the allocator has initial pool in the size of num_queues*(8-2) - the
73 * maximum missing RBDs per allocation request (request posted with 2
74 * empty RBDs, there is no guarantee when the other 6 RBDs are supplied).
75 * The queues supplies the recycle of the rest of the RBDs.
76 * + A received packet is processed and handed to the kernel network stack,
77 * detached from the iwl->rxq. The driver 'processed' index is updated.
78 * + If there are no allocated buffers in iwl->rxq->rx_free,
79 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
80 * If there were enough free buffers and RX_STALLED is set it is cleared.
81 *
82 *
83 * Driver sequence:
84 *
85 * iwl_rxq_alloc() Allocates rx_free
86 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
87 * iwl_pcie_rxq_restock.
88 * Used only during initialization.
89 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
90 * queue, updates firmware pointers, and updates
91 * the WRITE index.
92 * iwl_pcie_rx_allocator() Background work for allocating pages.
93 *
94 * -- enable interrupts --
95 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
96 * READ INDEX, detaching the SKB from the pool.
97 * Moves the packet buffer from queue to rx_used.
98 * Posts and claims requests to the allocator.
99 * Calls iwl_pcie_rxq_restock to refill any empty
100 * slots.
101 *
102 * RBD life-cycle:
103 *
104 * Init:
105 * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue
106 *
107 * Regular Receive interrupt:
108 * Page Stolen:
109 * rxq.queue -> rxq.rx_used -> allocator.rbd_empty ->
110 * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue
111 * Page not Stolen:
112 * rxq.queue -> rxq.rx_free -> rxq.queue
113 * ...
114 *
115 */
116
117 /*
118 * iwl_rxq_space - Return number of free slots available in queue.
119 */
iwl_rxq_space(const struct iwl_rxq * rxq)120 static int iwl_rxq_space(const struct iwl_rxq *rxq)
121 {
122 /* Make sure rx queue size is a power of 2 */
123 WARN_ON(rxq->queue_size & (rxq->queue_size - 1));
124
125 /*
126 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
127 * between empty and completely full queues.
128 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
129 * defined for negative dividends.
130 */
131 return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1);
132 }
133
134 /*
135 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
136 */
iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)137 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
138 {
139 return cpu_to_le32((u32)(dma_addr >> 8));
140 }
141
142 /*
143 * iwl_pcie_rx_stop - stops the Rx DMA
144 */
iwl_pcie_rx_stop(struct iwl_trans * trans)145 int iwl_pcie_rx_stop(struct iwl_trans *trans)
146 {
147 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
148 /* TODO: remove this once fw does it */
149 iwl_write_umac_prph(trans, RFH_RXF_DMA_CFG_AX210, 0);
150 return iwl_poll_umac_prph_bit(trans, RFH_GEN_STATUS_AX210,
151 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
152 } else if (trans->mac_cfg->mq_rx_supported) {
153 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
154 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS,
155 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
156 } else {
157 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
158 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
159 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
160 1000);
161 }
162 }
163
164 /*
165 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
166 */
iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans * trans,struct iwl_rxq * rxq)167 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
168 struct iwl_rxq *rxq)
169 {
170 u32 reg;
171
172 lockdep_assert_held(&rxq->lock);
173
174 /*
175 * explicitly wake up the NIC if:
176 * 1. shadow registers aren't enabled
177 * 2. there is a chance that the NIC is asleep
178 */
179 if (!trans->mac_cfg->base->shadow_reg_enable &&
180 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
181 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
182
183 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
184 IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
185 reg);
186 iwl_set_bit(trans, CSR_GP_CNTRL,
187 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
188 rxq->need_update = true;
189 return;
190 }
191 }
192
193 rxq->write_actual = round_down(rxq->write, 8);
194 if (!trans->mac_cfg->mq_rx_supported)
195 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
196 else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
197 iwl_write32(trans, HBUS_TARG_WRPTR, rxq->write_actual |
198 HBUS_TARG_WRPTR_RX_Q(rxq->id));
199 else
200 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
201 rxq->write_actual);
202 }
203
iwl_pcie_rxq_check_wrptr(struct iwl_trans * trans)204 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
205 {
206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
207 int i;
208
209 for (i = 0; i < trans->info.num_rxqs; i++) {
210 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
211
212 if (!rxq->need_update)
213 continue;
214 spin_lock_bh(&rxq->lock);
215 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
216 rxq->need_update = false;
217 spin_unlock_bh(&rxq->lock);
218 }
219 }
220
iwl_pcie_restock_bd(struct iwl_trans * trans,struct iwl_rxq * rxq,struct iwl_rx_mem_buffer * rxb)221 static void iwl_pcie_restock_bd(struct iwl_trans *trans,
222 struct iwl_rxq *rxq,
223 struct iwl_rx_mem_buffer *rxb)
224 {
225 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
226 struct iwl_rx_transfer_desc *bd = rxq->bd;
227
228 BUILD_BUG_ON(sizeof(*bd) != 2 * sizeof(u64));
229
230 bd[rxq->write].addr = cpu_to_le64(rxb->page_dma);
231 bd[rxq->write].rbid = cpu_to_le16(rxb->vid);
232 } else {
233 __le64 *bd = rxq->bd;
234
235 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid);
236 }
237
238 IWL_DEBUG_RX(trans, "Assigned virtual RB ID %u to queue %d index %d\n",
239 (u32)rxb->vid, rxq->id, rxq->write);
240 }
241
242 /*
243 * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx
244 */
iwl_pcie_rxmq_restock(struct iwl_trans * trans,struct iwl_rxq * rxq)245 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans,
246 struct iwl_rxq *rxq)
247 {
248 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
249 struct iwl_rx_mem_buffer *rxb;
250
251 /*
252 * If the device isn't enabled - no need to try to add buffers...
253 * This can happen when we stop the device and still have an interrupt
254 * pending. We stop the APM before we sync the interrupts because we
255 * have to (see comment there). On the other hand, since the APM is
256 * stopped, we cannot access the HW (in particular not prph).
257 * So don't try to restock if the APM has been already stopped.
258 */
259 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
260 return;
261
262 spin_lock_bh(&rxq->lock);
263 while (rxq->free_count) {
264 /* Get next free Rx buffer, remove from free list */
265 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
266 list);
267 list_del(&rxb->list);
268 rxb->invalid = false;
269 /* some low bits are expected to be unset (depending on hw) */
270 WARN_ON(rxb->page_dma & trans_pcie->supported_dma_mask);
271 /* Point to Rx buffer via next RBD in circular buffer */
272 iwl_pcie_restock_bd(trans, rxq, rxb);
273 rxq->write = (rxq->write + 1) & (rxq->queue_size - 1);
274 rxq->free_count--;
275 }
276 spin_unlock_bh(&rxq->lock);
277
278 /*
279 * If we've added more space for the firmware to place data, tell it.
280 * Increment device's write pointer in multiples of 8.
281 */
282 if (rxq->write_actual != (rxq->write & ~0x7)) {
283 spin_lock_bh(&rxq->lock);
284 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
285 spin_unlock_bh(&rxq->lock);
286 }
287 }
288
289 /*
290 * iwl_pcie_rxsq_restock - restock implementation for single queue rx
291 */
iwl_pcie_rxsq_restock(struct iwl_trans * trans,struct iwl_rxq * rxq)292 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans,
293 struct iwl_rxq *rxq)
294 {
295 struct iwl_rx_mem_buffer *rxb;
296
297 /*
298 * If the device isn't enabled - not need to try to add buffers...
299 * This can happen when we stop the device and still have an interrupt
300 * pending. We stop the APM before we sync the interrupts because we
301 * have to (see comment there). On the other hand, since the APM is
302 * stopped, we cannot access the HW (in particular not prph).
303 * So don't try to restock if the APM has been already stopped.
304 */
305 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
306 return;
307
308 spin_lock_bh(&rxq->lock);
309 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
310 __le32 *bd = (__le32 *)rxq->bd;
311 /* The overwritten rxb must be a used one */
312 rxb = rxq->queue[rxq->write];
313 BUG_ON(rxb && rxb->page);
314
315 /* Get next free Rx buffer, remove from free list */
316 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
317 list);
318 list_del(&rxb->list);
319 rxb->invalid = false;
320
321 /* Point to Rx buffer via next RBD in circular buffer */
322 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
323 rxq->queue[rxq->write] = rxb;
324 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
325 rxq->free_count--;
326 }
327 spin_unlock_bh(&rxq->lock);
328
329 /* If we've added more space for the firmware to place data, tell it.
330 * Increment device's write pointer in multiples of 8. */
331 if (rxq->write_actual != (rxq->write & ~0x7)) {
332 spin_lock_bh(&rxq->lock);
333 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
334 spin_unlock_bh(&rxq->lock);
335 }
336 }
337
338 /*
339 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
340 *
341 * If there are slots in the RX queue that need to be restocked,
342 * and we have free pre-allocated buffers, fill the ranks as much
343 * as we can, pulling from rx_free.
344 *
345 * This moves the 'write' index forward to catch up with 'processed', and
346 * also updates the memory address in the firmware to reference the new
347 * target buffer.
348 */
349 static
iwl_pcie_rxq_restock(struct iwl_trans * trans,struct iwl_rxq * rxq)350 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq)
351 {
352 if (trans->mac_cfg->mq_rx_supported)
353 iwl_pcie_rxmq_restock(trans, rxq);
354 else
355 iwl_pcie_rxsq_restock(trans, rxq);
356 }
357
358 /*
359 * iwl_pcie_rx_alloc_page - allocates and returns a page.
360 *
361 */
iwl_pcie_rx_alloc_page(struct iwl_trans * trans,u32 * offset,gfp_t priority)362 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans,
363 u32 *offset, gfp_t priority)
364 {
365 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
366 unsigned int allocsize = PAGE_SIZE << trans_pcie->rx_page_order;
367 unsigned int rbsize = trans_pcie->rx_buf_bytes;
368 struct page *page;
369 gfp_t gfp_mask = priority;
370
371 if (trans_pcie->rx_page_order > 0)
372 gfp_mask |= __GFP_COMP;
373
374 if (trans_pcie->alloc_page) {
375 spin_lock_bh(&trans_pcie->alloc_page_lock);
376 /* recheck */
377 if (trans_pcie->alloc_page) {
378 *offset = trans_pcie->alloc_page_used;
379 page = trans_pcie->alloc_page;
380 trans_pcie->alloc_page_used += rbsize;
381 if (trans_pcie->alloc_page_used >= allocsize)
382 trans_pcie->alloc_page = NULL;
383 else
384 get_page(page);
385 spin_unlock_bh(&trans_pcie->alloc_page_lock);
386 return page;
387 }
388 spin_unlock_bh(&trans_pcie->alloc_page_lock);
389 }
390
391 /* Alloc a new receive buffer */
392 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
393 if (!page) {
394 if (net_ratelimit())
395 IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n",
396 trans_pcie->rx_page_order);
397 /*
398 * Issue an error if we don't have enough pre-allocated
399 * buffers.
400 */
401 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit())
402 IWL_CRIT(trans,
403 "Failed to alloc_pages\n");
404 return NULL;
405 }
406
407 if (2 * rbsize <= allocsize) {
408 spin_lock_bh(&trans_pcie->alloc_page_lock);
409 if (!trans_pcie->alloc_page) {
410 get_page(page);
411 trans_pcie->alloc_page = page;
412 trans_pcie->alloc_page_used = rbsize;
413 }
414 spin_unlock_bh(&trans_pcie->alloc_page_lock);
415 }
416
417 *offset = 0;
418 return page;
419 }
420
421 /*
422 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
423 *
424 * A used RBD is an Rx buffer that has been given to the stack. To use it again
425 * a page must be allocated and the RBD must point to the page. This function
426 * doesn't change the HW pointer but handles the list of pages that is used by
427 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
428 * allocated buffers.
429 */
iwl_pcie_rxq_alloc_rbs(struct iwl_trans * trans,gfp_t priority,struct iwl_rxq * rxq)430 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
431 struct iwl_rxq *rxq)
432 {
433 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
434 struct iwl_rx_mem_buffer *rxb;
435 struct page *page;
436
437 while (1) {
438 unsigned int offset;
439
440 spin_lock_bh(&rxq->lock);
441 if (list_empty(&rxq->rx_used)) {
442 spin_unlock_bh(&rxq->lock);
443 return;
444 }
445 spin_unlock_bh(&rxq->lock);
446
447 page = iwl_pcie_rx_alloc_page(trans, &offset, priority);
448 if (!page)
449 return;
450
451 spin_lock_bh(&rxq->lock);
452
453 if (list_empty(&rxq->rx_used)) {
454 spin_unlock_bh(&rxq->lock);
455 __free_pages(page, trans_pcie->rx_page_order);
456 return;
457 }
458 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
459 list);
460 list_del(&rxb->list);
461 spin_unlock_bh(&rxq->lock);
462
463 BUG_ON(rxb->page);
464 rxb->page = page;
465 rxb->offset = offset;
466 /* Get physical address of the RB */
467 rxb->page_dma =
468 dma_map_page(trans->dev, page, rxb->offset,
469 trans_pcie->rx_buf_bytes,
470 DMA_FROM_DEVICE);
471 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
472 rxb->page = NULL;
473 spin_lock_bh(&rxq->lock);
474 list_add(&rxb->list, &rxq->rx_used);
475 spin_unlock_bh(&rxq->lock);
476 __free_pages(page, trans_pcie->rx_page_order);
477 return;
478 }
479
480 spin_lock_bh(&rxq->lock);
481
482 list_add_tail(&rxb->list, &rxq->rx_free);
483 rxq->free_count++;
484
485 spin_unlock_bh(&rxq->lock);
486 }
487 }
488
iwl_pcie_free_rbs_pool(struct iwl_trans * trans)489 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
490 {
491 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
492 int i;
493
494 if (!trans_pcie->rx_pool)
495 return;
496
497 for (i = 0; i < RX_POOL_SIZE(trans_pcie->num_rx_bufs); i++) {
498 if (!trans_pcie->rx_pool[i].page)
499 continue;
500 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma,
501 trans_pcie->rx_buf_bytes, DMA_FROM_DEVICE);
502 __free_pages(trans_pcie->rx_pool[i].page,
503 trans_pcie->rx_page_order);
504 trans_pcie->rx_pool[i].page = NULL;
505 }
506 }
507
508 /*
509 * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues
510 *
511 * Allocates for each received request 8 pages
512 * Called as a scheduled work item.
513 */
iwl_pcie_rx_allocator(struct iwl_trans * trans)514 static void iwl_pcie_rx_allocator(struct iwl_trans *trans)
515 {
516 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
517 struct iwl_rb_allocator *rba = &trans_pcie->rba;
518 struct list_head local_empty;
519 int pending = atomic_read(&rba->req_pending);
520
521 IWL_DEBUG_TPT(trans, "Pending allocation requests = %d\n", pending);
522
523 /* If we were scheduled - there is at least one request */
524 spin_lock_bh(&rba->lock);
525 /* swap out the rba->rbd_empty to a local list */
526 list_replace_init(&rba->rbd_empty, &local_empty);
527 spin_unlock_bh(&rba->lock);
528
529 while (pending) {
530 int i;
531 LIST_HEAD(local_allocated);
532 gfp_t gfp_mask = GFP_KERNEL;
533
534 /* Do not post a warning if there are only a few requests */
535 if (pending < RX_PENDING_WATERMARK)
536 gfp_mask |= __GFP_NOWARN;
537
538 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) {
539 struct iwl_rx_mem_buffer *rxb;
540 struct page *page;
541
542 /* List should never be empty - each reused RBD is
543 * returned to the list, and initial pool covers any
544 * possible gap between the time the page is allocated
545 * to the time the RBD is added.
546 */
547 BUG_ON(list_empty(&local_empty));
548 /* Get the first rxb from the rbd list */
549 rxb = list_first_entry(&local_empty,
550 struct iwl_rx_mem_buffer, list);
551 BUG_ON(rxb->page);
552
553 /* Alloc a new receive buffer */
554 page = iwl_pcie_rx_alloc_page(trans, &rxb->offset,
555 gfp_mask);
556 if (!page)
557 continue;
558 rxb->page = page;
559
560 /* Get physical address of the RB */
561 rxb->page_dma = dma_map_page(trans->dev, page,
562 rxb->offset,
563 trans_pcie->rx_buf_bytes,
564 DMA_FROM_DEVICE);
565 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
566 rxb->page = NULL;
567 __free_pages(page, trans_pcie->rx_page_order);
568 continue;
569 }
570
571 /* move the allocated entry to the out list */
572 list_move(&rxb->list, &local_allocated);
573 i++;
574 }
575
576 atomic_dec(&rba->req_pending);
577 pending--;
578
579 if (!pending) {
580 pending = atomic_read(&rba->req_pending);
581 if (pending)
582 IWL_DEBUG_TPT(trans,
583 "Got more pending allocation requests = %d\n",
584 pending);
585 }
586
587 spin_lock_bh(&rba->lock);
588 /* add the allocated rbds to the allocator allocated list */
589 list_splice_tail(&local_allocated, &rba->rbd_allocated);
590 /* get more empty RBDs for current pending requests */
591 list_splice_tail_init(&rba->rbd_empty, &local_empty);
592 spin_unlock_bh(&rba->lock);
593
594 atomic_inc(&rba->req_ready);
595
596 }
597
598 spin_lock_bh(&rba->lock);
599 /* return unused rbds to the allocator empty list */
600 list_splice_tail(&local_empty, &rba->rbd_empty);
601 spin_unlock_bh(&rba->lock);
602
603 IWL_DEBUG_TPT(trans, "%s, exit.\n", __func__);
604 }
605
606 /*
607 * iwl_pcie_rx_allocator_get - returns the pre-allocated pages
608 .*
609 .* Called by queue when the queue posted allocation request and
610 * has freed 8 RBDs in order to restock itself.
611 * This function directly moves the allocated RBs to the queue's ownership
612 * and updates the relevant counters.
613 */
iwl_pcie_rx_allocator_get(struct iwl_trans * trans,struct iwl_rxq * rxq)614 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans,
615 struct iwl_rxq *rxq)
616 {
617 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
618 struct iwl_rb_allocator *rba = &trans_pcie->rba;
619 int i;
620
621 lockdep_assert_held(&rxq->lock);
622
623 /*
624 * atomic_dec_if_positive returns req_ready - 1 for any scenario.
625 * If req_ready is 0 atomic_dec_if_positive will return -1 and this
626 * function will return early, as there are no ready requests.
627 * atomic_dec_if_positive will perofrm the *actual* decrement only if
628 * req_ready > 0, i.e. - there are ready requests and the function
629 * hands one request to the caller.
630 */
631 if (atomic_dec_if_positive(&rba->req_ready) < 0)
632 return;
633
634 spin_lock(&rba->lock);
635 for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) {
636 /* Get next free Rx buffer, remove it from free list */
637 struct iwl_rx_mem_buffer *rxb =
638 list_first_entry(&rba->rbd_allocated,
639 struct iwl_rx_mem_buffer, list);
640
641 list_move(&rxb->list, &rxq->rx_free);
642 }
643 spin_unlock(&rba->lock);
644
645 rxq->used_count -= RX_CLAIM_REQ_ALLOC;
646 rxq->free_count += RX_CLAIM_REQ_ALLOC;
647 }
648
iwl_pcie_rx_allocator_work(struct work_struct * data)649 void iwl_pcie_rx_allocator_work(struct work_struct *data)
650 {
651 struct iwl_rb_allocator *rba_p =
652 container_of(data, struct iwl_rb_allocator, rx_alloc);
653 struct iwl_trans_pcie *trans_pcie =
654 container_of(rba_p, struct iwl_trans_pcie, rba);
655
656 iwl_pcie_rx_allocator(trans_pcie->trans);
657 }
658
iwl_pcie_free_bd_size(struct iwl_trans * trans)659 static int iwl_pcie_free_bd_size(struct iwl_trans *trans)
660 {
661 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
662 return sizeof(struct iwl_rx_transfer_desc);
663
664 return trans->mac_cfg->mq_rx_supported ?
665 sizeof(__le64) : sizeof(__le32);
666 }
667
iwl_pcie_used_bd_size(struct iwl_trans * trans)668 static int iwl_pcie_used_bd_size(struct iwl_trans *trans)
669 {
670 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
671 return sizeof(struct iwl_rx_completion_desc_bz);
672
673 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
674 return sizeof(struct iwl_rx_completion_desc);
675
676 return sizeof(__le32);
677 }
678
iwl_pcie_free_rxq_dma(struct iwl_trans * trans,struct iwl_rxq * rxq)679 static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans,
680 struct iwl_rxq *rxq)
681 {
682 int free_size = iwl_pcie_free_bd_size(trans);
683
684 if (rxq->bd)
685 dma_free_coherent(trans->dev,
686 free_size * rxq->queue_size,
687 rxq->bd, rxq->bd_dma);
688 rxq->bd_dma = 0;
689 rxq->bd = NULL;
690
691 rxq->rb_stts_dma = 0;
692 rxq->rb_stts = NULL;
693
694 if (rxq->used_bd)
695 dma_free_coherent(trans->dev,
696 iwl_pcie_used_bd_size(trans) *
697 rxq->queue_size,
698 rxq->used_bd, rxq->used_bd_dma);
699 rxq->used_bd_dma = 0;
700 rxq->used_bd = NULL;
701 }
702
iwl_pcie_rb_stts_size(struct iwl_trans * trans)703 static size_t iwl_pcie_rb_stts_size(struct iwl_trans *trans)
704 {
705 bool use_rx_td = (trans->mac_cfg->device_family >=
706 IWL_DEVICE_FAMILY_AX210);
707
708 if (use_rx_td)
709 return sizeof(__le16);
710
711 return sizeof(struct iwl_rb_status);
712 }
713
iwl_pcie_alloc_rxq_dma(struct iwl_trans * trans,struct iwl_rxq * rxq)714 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans,
715 struct iwl_rxq *rxq)
716 {
717 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
718 size_t rb_stts_size = iwl_pcie_rb_stts_size(trans);
719 struct device *dev = trans->dev;
720 int i;
721 int free_size;
722
723 spin_lock_init(&rxq->lock);
724 if (trans->mac_cfg->mq_rx_supported)
725 rxq->queue_size = iwl_trans_get_num_rbds(trans);
726 else
727 rxq->queue_size = RX_QUEUE_SIZE;
728
729 free_size = iwl_pcie_free_bd_size(trans);
730
731 /*
732 * Allocate the circular buffer of Read Buffer Descriptors
733 * (RBDs)
734 */
735 rxq->bd = dma_alloc_coherent(dev, free_size * rxq->queue_size,
736 &rxq->bd_dma, GFP_KERNEL);
737 if (!rxq->bd)
738 goto err;
739
740 if (trans->mac_cfg->mq_rx_supported) {
741 rxq->used_bd = dma_alloc_coherent(dev,
742 iwl_pcie_used_bd_size(trans) *
743 rxq->queue_size,
744 &rxq->used_bd_dma,
745 GFP_KERNEL);
746 if (!rxq->used_bd)
747 goto err;
748 }
749
750 rxq->rb_stts = (u8 *)trans_pcie->base_rb_stts + rxq->id * rb_stts_size;
751 rxq->rb_stts_dma =
752 trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size;
753
754 return 0;
755
756 err:
757 for (i = 0; i < trans->info.num_rxqs; i++) {
758 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
759
760 iwl_pcie_free_rxq_dma(trans, rxq);
761 }
762
763 return -ENOMEM;
764 }
765
iwl_pcie_rx_alloc(struct iwl_trans * trans)766 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
767 {
768 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
769 size_t rb_stts_size = iwl_pcie_rb_stts_size(trans);
770 struct iwl_rb_allocator *rba = &trans_pcie->rba;
771 int i, ret;
772
773 if (WARN_ON(trans_pcie->rxq))
774 return -EINVAL;
775
776 trans_pcie->rxq = kcalloc(trans->info.num_rxqs, sizeof(struct iwl_rxq),
777 GFP_KERNEL);
778 trans_pcie->rx_pool = kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs),
779 sizeof(trans_pcie->rx_pool[0]),
780 GFP_KERNEL);
781 trans_pcie->global_table =
782 kcalloc(RX_POOL_SIZE(trans_pcie->num_rx_bufs),
783 sizeof(trans_pcie->global_table[0]),
784 GFP_KERNEL);
785 if (!trans_pcie->rxq || !trans_pcie->rx_pool ||
786 !trans_pcie->global_table) {
787 ret = -ENOMEM;
788 goto err;
789 }
790
791 spin_lock_init(&rba->lock);
792
793 /*
794 * Allocate the driver's pointer to receive buffer status.
795 * Allocate for all queues continuously (HW requirement).
796 */
797 trans_pcie->base_rb_stts =
798 dma_alloc_coherent(trans->dev,
799 rb_stts_size * trans->info.num_rxqs,
800 &trans_pcie->base_rb_stts_dma,
801 GFP_KERNEL);
802 if (!trans_pcie->base_rb_stts) {
803 ret = -ENOMEM;
804 goto err;
805 }
806
807 for (i = 0; i < trans->info.num_rxqs; i++) {
808 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
809
810 rxq->id = i;
811 ret = iwl_pcie_alloc_rxq_dma(trans, rxq);
812 if (ret)
813 goto err;
814 }
815 return 0;
816
817 err:
818 if (trans_pcie->base_rb_stts) {
819 dma_free_coherent(trans->dev,
820 rb_stts_size * trans->info.num_rxqs,
821 trans_pcie->base_rb_stts,
822 trans_pcie->base_rb_stts_dma);
823 trans_pcie->base_rb_stts = NULL;
824 trans_pcie->base_rb_stts_dma = 0;
825 }
826 kfree(trans_pcie->rx_pool);
827 trans_pcie->rx_pool = NULL;
828 kfree(trans_pcie->global_table);
829 trans_pcie->global_table = NULL;
830 kfree(trans_pcie->rxq);
831 trans_pcie->rxq = NULL;
832
833 return ret;
834 }
835
iwl_pcie_rx_hw_init(struct iwl_trans * trans,struct iwl_rxq * rxq)836 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
837 {
838 u32 rb_size;
839 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
840
841 switch (trans->conf.rx_buf_size) {
842 case IWL_AMSDU_4K:
843 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
844 break;
845 case IWL_AMSDU_8K:
846 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
847 break;
848 case IWL_AMSDU_12K:
849 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K;
850 break;
851 default:
852 WARN_ON(1);
853 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
854 }
855
856 if (!iwl_trans_grab_nic_access(trans))
857 return;
858
859 /* Stop Rx DMA */
860 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
861 /* reset and flush pointers */
862 iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
863 iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
864 iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
865
866 /* Reset driver's Rx queue write index */
867 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
868
869 /* Tell device where to find RBD circular buffer in DRAM */
870 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
871 (u32)(rxq->bd_dma >> 8));
872
873 /* Tell device where in DRAM to update its Rx status */
874 iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
875 rxq->rb_stts_dma >> 4);
876
877 /* Enable Rx DMA
878 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
879 * the credit mechanism in 5000 HW RX FIFO
880 * Direct rx interrupts to hosts
881 * Rx buffer size 4 or 8k or 12k
882 * RB timeout 0x10
883 * 256 RBDs
884 */
885 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
886 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
887 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
888 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
889 rb_size |
890 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
891 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
892
893 iwl_trans_release_nic_access(trans);
894
895 /* Set interrupt coalescing timer to default (2048 usecs) */
896 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
897
898 /* W/A for interrupt coalescing bug in 7260 and 3160 */
899 if (trans->cfg->host_interrupt_operation_mode)
900 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
901 }
902
iwl_pcie_rx_mq_hw_init(struct iwl_trans * trans)903 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
904 {
905 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
906 u32 rb_size, enabled = 0;
907 int i;
908
909 switch (trans->conf.rx_buf_size) {
910 case IWL_AMSDU_2K:
911 rb_size = RFH_RXF_DMA_RB_SIZE_2K;
912 break;
913 case IWL_AMSDU_4K:
914 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
915 break;
916 case IWL_AMSDU_8K:
917 rb_size = RFH_RXF_DMA_RB_SIZE_8K;
918 break;
919 case IWL_AMSDU_12K:
920 rb_size = RFH_RXF_DMA_RB_SIZE_12K;
921 break;
922 default:
923 WARN_ON(1);
924 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
925 }
926
927 if (!iwl_trans_grab_nic_access(trans))
928 return;
929
930 /* Stop Rx DMA */
931 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
932 /* disable free amd used rx queue operation */
933 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
934
935 for (i = 0; i < trans->info.num_rxqs; i++) {
936 /* Tell device where to find RBD free table in DRAM */
937 iwl_write_prph64_no_grab(trans,
938 RFH_Q_FRBDCB_BA_LSB(i),
939 trans_pcie->rxq[i].bd_dma);
940 /* Tell device where to find RBD used table in DRAM */
941 iwl_write_prph64_no_grab(trans,
942 RFH_Q_URBDCB_BA_LSB(i),
943 trans_pcie->rxq[i].used_bd_dma);
944 /* Tell device where in DRAM to update its Rx status */
945 iwl_write_prph64_no_grab(trans,
946 RFH_Q_URBD_STTS_WPTR_LSB(i),
947 trans_pcie->rxq[i].rb_stts_dma);
948 /* Reset device indice tables */
949 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
950 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
951 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
952
953 enabled |= BIT(i) | BIT(i + 16);
954 }
955
956 /*
957 * Enable Rx DMA
958 * Rx buffer size 4 or 8k or 12k
959 * Min RB size 4 or 8
960 * Drop frames that exceed RB size
961 * 512 RBDs
962 */
963 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
964 RFH_DMA_EN_ENABLE_VAL | rb_size |
965 RFH_RXF_DMA_MIN_RB_4_8 |
966 RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
967 RFH_RXF_DMA_RBDCB_SIZE_512);
968
969 /*
970 * Activate DMA snooping.
971 * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe
972 * Default queue is 0
973 */
974 iwl_write_prph_no_grab(trans, RFH_GEN_CFG,
975 RFH_GEN_CFG_RFH_DMA_SNOOP |
976 RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) |
977 RFH_GEN_CFG_SERVICE_DMA_SNOOP |
978 RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,
979 trans->mac_cfg->integrated ?
980 RFH_GEN_CFG_RB_CHUNK_SIZE_64 :
981 RFH_GEN_CFG_RB_CHUNK_SIZE_128));
982 /* Enable the relevant rx queues */
983 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
984
985 iwl_trans_release_nic_access(trans);
986
987 /* Set interrupt coalescing timer to default (2048 usecs) */
988 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
989 }
990
iwl_pcie_rx_init_rxb_lists(struct iwl_rxq * rxq)991 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
992 {
993 lockdep_assert_held(&rxq->lock);
994
995 INIT_LIST_HEAD(&rxq->rx_free);
996 INIT_LIST_HEAD(&rxq->rx_used);
997 rxq->free_count = 0;
998 rxq->used_count = 0;
999 }
1000
1001 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget);
1002
iwl_netdev_to_trans_pcie(struct net_device * dev)1003 static inline struct iwl_trans_pcie *iwl_netdev_to_trans_pcie(struct net_device *dev)
1004 {
1005 return *(struct iwl_trans_pcie **)netdev_priv(dev);
1006 }
1007
iwl_pcie_napi_poll(struct napi_struct * napi,int budget)1008 static int iwl_pcie_napi_poll(struct napi_struct *napi, int budget)
1009 {
1010 struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi);
1011 struct iwl_trans_pcie *trans_pcie;
1012 struct iwl_trans *trans;
1013 int ret;
1014
1015 trans_pcie = iwl_netdev_to_trans_pcie(napi->dev);
1016 trans = trans_pcie->trans;
1017
1018 ret = iwl_pcie_rx_handle(trans, rxq->id, budget);
1019
1020 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n",
1021 rxq->id, ret, budget);
1022
1023 if (ret < budget) {
1024 spin_lock(&trans_pcie->irq_lock);
1025 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1026 _iwl_enable_interrupts(trans);
1027 spin_unlock(&trans_pcie->irq_lock);
1028
1029 napi_complete_done(&rxq->napi, ret);
1030 }
1031
1032 return ret;
1033 }
1034
iwl_pcie_napi_poll_msix(struct napi_struct * napi,int budget)1035 static int iwl_pcie_napi_poll_msix(struct napi_struct *napi, int budget)
1036 {
1037 struct iwl_rxq *rxq = container_of(napi, struct iwl_rxq, napi);
1038 struct iwl_trans_pcie *trans_pcie;
1039 struct iwl_trans *trans;
1040 int ret;
1041
1042 trans_pcie = iwl_netdev_to_trans_pcie(napi->dev);
1043 trans = trans_pcie->trans;
1044
1045 ret = iwl_pcie_rx_handle(trans, rxq->id, budget);
1046 IWL_DEBUG_ISR(trans, "[%d] handled %d, budget %d\n", rxq->id, ret,
1047 budget);
1048
1049 if (ret < budget) {
1050 int irq_line = rxq->id;
1051
1052 /* FIRST_RSS is shared with line 0 */
1053 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS &&
1054 rxq->id == 1)
1055 irq_line = 0;
1056
1057 spin_lock(&trans_pcie->irq_lock);
1058 iwl_pcie_clear_irq(trans, irq_line);
1059 spin_unlock(&trans_pcie->irq_lock);
1060
1061 napi_complete_done(&rxq->napi, ret);
1062 }
1063
1064 return ret;
1065 }
1066
iwl_pcie_rx_napi_sync(struct iwl_trans * trans)1067 void iwl_pcie_rx_napi_sync(struct iwl_trans *trans)
1068 {
1069 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1070 int i;
1071
1072 if (unlikely(!trans_pcie->rxq))
1073 return;
1074
1075 for (i = 0; i < trans->info.num_rxqs; i++) {
1076 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1077
1078 if (rxq && rxq->napi.poll)
1079 napi_synchronize(&rxq->napi);
1080 }
1081 }
1082
_iwl_pcie_rx_init(struct iwl_trans * trans)1083 static int _iwl_pcie_rx_init(struct iwl_trans *trans)
1084 {
1085 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1086 struct iwl_rxq *def_rxq;
1087 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1088 int i, err, queue_size, allocator_pool_size, num_alloc;
1089
1090 if (!trans_pcie->rxq) {
1091 err = iwl_pcie_rx_alloc(trans);
1092 if (err)
1093 return err;
1094 }
1095 def_rxq = trans_pcie->rxq;
1096
1097 cancel_work_sync(&rba->rx_alloc);
1098
1099 spin_lock_bh(&rba->lock);
1100 atomic_set(&rba->req_pending, 0);
1101 atomic_set(&rba->req_ready, 0);
1102 INIT_LIST_HEAD(&rba->rbd_allocated);
1103 INIT_LIST_HEAD(&rba->rbd_empty);
1104 spin_unlock_bh(&rba->lock);
1105
1106 /* free all first - we overwrite everything here */
1107 iwl_pcie_free_rbs_pool(trans);
1108
1109 for (i = 0; i < RX_QUEUE_SIZE; i++)
1110 def_rxq->queue[i] = NULL;
1111
1112 for (i = 0; i < trans->info.num_rxqs; i++) {
1113 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1114
1115 spin_lock_bh(&rxq->lock);
1116 /*
1117 * Set read write pointer to reflect that we have processed
1118 * and used all buffers, but have not restocked the Rx queue
1119 * with fresh buffers
1120 */
1121 rxq->read = 0;
1122 rxq->write = 0;
1123 rxq->write_actual = 0;
1124 memset(rxq->rb_stts, 0,
1125 (trans->mac_cfg->device_family >=
1126 IWL_DEVICE_FAMILY_AX210) ?
1127 sizeof(__le16) : sizeof(struct iwl_rb_status));
1128
1129 iwl_pcie_rx_init_rxb_lists(rxq);
1130
1131 spin_unlock_bh(&rxq->lock);
1132
1133 if (!rxq->napi.poll) {
1134 int (*poll)(struct napi_struct *, int) = iwl_pcie_napi_poll;
1135
1136 if (trans_pcie->msix_enabled)
1137 poll = iwl_pcie_napi_poll_msix;
1138
1139 netif_napi_add(trans_pcie->napi_dev, &rxq->napi,
1140 poll);
1141 napi_enable(&rxq->napi);
1142 }
1143
1144 }
1145
1146 /* move the pool to the default queue and allocator ownerships */
1147 queue_size = trans->mac_cfg->mq_rx_supported ?
1148 trans_pcie->num_rx_bufs - 1 : RX_QUEUE_SIZE;
1149 allocator_pool_size = trans->info.num_rxqs *
1150 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC);
1151 num_alloc = queue_size + allocator_pool_size;
1152
1153 for (i = 0; i < num_alloc; i++) {
1154 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i];
1155
1156 if (i < allocator_pool_size)
1157 list_add(&rxb->list, &rba->rbd_empty);
1158 else
1159 list_add(&rxb->list, &def_rxq->rx_used);
1160 trans_pcie->global_table[i] = rxb;
1161 rxb->vid = (u16)(i + 1);
1162 rxb->invalid = true;
1163 }
1164
1165 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq);
1166
1167 return 0;
1168 }
1169
iwl_pcie_rx_init(struct iwl_trans * trans)1170 int iwl_pcie_rx_init(struct iwl_trans *trans)
1171 {
1172 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1173 int ret = _iwl_pcie_rx_init(trans);
1174
1175 if (ret)
1176 return ret;
1177
1178 if (trans->mac_cfg->mq_rx_supported)
1179 iwl_pcie_rx_mq_hw_init(trans);
1180 else
1181 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq);
1182
1183 iwl_pcie_rxq_restock(trans, trans_pcie->rxq);
1184
1185 spin_lock_bh(&trans_pcie->rxq->lock);
1186 iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq);
1187 spin_unlock_bh(&trans_pcie->rxq->lock);
1188
1189 return 0;
1190 }
1191
iwl_pcie_gen2_rx_init(struct iwl_trans * trans)1192 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans)
1193 {
1194 /* Set interrupt coalescing timer to default (2048 usecs) */
1195 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
1196
1197 /*
1198 * We don't configure the RFH.
1199 * Restock will be done at alive, after firmware configured the RFH.
1200 */
1201 return _iwl_pcie_rx_init(trans);
1202 }
1203
iwl_pcie_rx_free(struct iwl_trans * trans)1204 void iwl_pcie_rx_free(struct iwl_trans *trans)
1205 {
1206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1207 size_t rb_stts_size = iwl_pcie_rb_stts_size(trans);
1208 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1209 int i;
1210
1211 /*
1212 * if rxq is NULL, it means that nothing has been allocated,
1213 * exit now
1214 */
1215 if (!trans_pcie->rxq) {
1216 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
1217 return;
1218 }
1219
1220 cancel_work_sync(&rba->rx_alloc);
1221
1222 iwl_pcie_free_rbs_pool(trans);
1223
1224 if (trans_pcie->base_rb_stts) {
1225 dma_free_coherent(trans->dev,
1226 rb_stts_size * trans->info.num_rxqs,
1227 trans_pcie->base_rb_stts,
1228 trans_pcie->base_rb_stts_dma);
1229 trans_pcie->base_rb_stts = NULL;
1230 trans_pcie->base_rb_stts_dma = 0;
1231 }
1232
1233 for (i = 0; i < trans->info.num_rxqs; i++) {
1234 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1235
1236 iwl_pcie_free_rxq_dma(trans, rxq);
1237
1238 if (rxq->napi.poll) {
1239 napi_disable(&rxq->napi);
1240 netif_napi_del(&rxq->napi);
1241 }
1242 }
1243 kfree(trans_pcie->rx_pool);
1244 kfree(trans_pcie->global_table);
1245 kfree(trans_pcie->rxq);
1246
1247 if (trans_pcie->alloc_page)
1248 __free_pages(trans_pcie->alloc_page, trans_pcie->rx_page_order);
1249 }
1250
iwl_pcie_rx_move_to_allocator(struct iwl_rxq * rxq,struct iwl_rb_allocator * rba)1251 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq,
1252 struct iwl_rb_allocator *rba)
1253 {
1254 spin_lock(&rba->lock);
1255 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);
1256 spin_unlock(&rba->lock);
1257 }
1258
1259 /*
1260 * iwl_pcie_rx_reuse_rbd - Recycle used RBDs
1261 *
1262 * Called when a RBD can be reused. The RBD is transferred to the allocator.
1263 * When there are 2 empty RBDs - a request for allocation is posted
1264 */
iwl_pcie_rx_reuse_rbd(struct iwl_trans * trans,struct iwl_rx_mem_buffer * rxb,struct iwl_rxq * rxq,bool emergency)1265 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans,
1266 struct iwl_rx_mem_buffer *rxb,
1267 struct iwl_rxq *rxq, bool emergency)
1268 {
1269 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1270 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1271
1272 /* Move the RBD to the used list, will be moved to allocator in batches
1273 * before claiming or posting a request*/
1274 list_add_tail(&rxb->list, &rxq->rx_used);
1275
1276 if (unlikely(emergency))
1277 return;
1278
1279 /* Count the allocator owned RBDs */
1280 rxq->used_count++;
1281
1282 /* If we have RX_POST_REQ_ALLOC new released rx buffers -
1283 * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is
1284 * used for the case we failed to claim RX_CLAIM_REQ_ALLOC,
1285 * after but we still need to post another request.
1286 */
1287 if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) {
1288 /* Move the 2 RBDs to the allocator ownership.
1289 Allocator has another 6 from pool for the request completion*/
1290 iwl_pcie_rx_move_to_allocator(rxq, rba);
1291
1292 atomic_inc(&rba->req_pending);
1293 queue_work(rba->alloc_wq, &rba->rx_alloc);
1294 }
1295 }
1296
iwl_pcie_rx_handle_rb(struct iwl_trans * trans,struct iwl_rxq * rxq,struct iwl_rx_mem_buffer * rxb,bool emergency,int i)1297 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
1298 struct iwl_rxq *rxq,
1299 struct iwl_rx_mem_buffer *rxb,
1300 bool emergency,
1301 int i)
1302 {
1303 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1304 struct iwl_txq *txq = trans_pcie->txqs.txq[trans->conf.cmd_queue];
1305 bool page_stolen = false;
1306 int max_len = trans_pcie->rx_buf_bytes;
1307 u32 offset = 0;
1308
1309 if (WARN_ON(!rxb))
1310 return;
1311
1312 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
1313
1314 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
1315 struct iwl_rx_packet *pkt;
1316 bool reclaim;
1317 int len;
1318 struct iwl_rx_cmd_buffer rxcb = {
1319 ._offset = rxb->offset + offset,
1320 ._rx_page_order = trans_pcie->rx_page_order,
1321 ._page = rxb->page,
1322 ._page_stolen = false,
1323 .truesize = max_len,
1324 };
1325
1326 pkt = rxb_addr(&rxcb);
1327
1328 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) {
1329 IWL_DEBUG_RX(trans,
1330 "Q %d: RB end marker at offset %d\n",
1331 rxq->id, offset);
1332 break;
1333 }
1334
1335 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1336 FH_RSCSR_RXQ_POS != rxq->id,
1337 "frame on invalid queue - is on %d and indicates %d\n",
1338 rxq->id,
1339 (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1340 FH_RSCSR_RXQ_POS);
1341
1342 IWL_DEBUG_RX(trans,
1343 "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n",
1344 rxq->id, offset,
1345 iwl_get_cmd_string(trans,
1346 WIDE_ID(pkt->hdr.group_id, pkt->hdr.cmd)),
1347 pkt->hdr.group_id, pkt->hdr.cmd,
1348 le16_to_cpu(pkt->hdr.sequence));
1349
1350 len = iwl_rx_packet_len(pkt);
1351 len += sizeof(u32); /* account for status word */
1352
1353 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
1354
1355 /* check that what the device tells us made sense */
1356 if (len < sizeof(*pkt) || offset > max_len)
1357 break;
1358
1359 maybe_trace_iwlwifi_dev_rx(trans, pkt, len);
1360
1361 /* Reclaim a command buffer only if this packet is a response
1362 * to a (driver-originated) command.
1363 * If the packet (e.g. Rx frame) originated from uCode,
1364 * there is no command buffer to reclaim.
1365 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1366 * but apparently a few don't get set; catch them here. */
1367 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
1368 if (reclaim && !pkt->hdr.group_id) {
1369 int i;
1370
1371 for (i = 0; i < trans->conf.n_no_reclaim_cmds; i++) {
1372 if (trans->conf.no_reclaim_cmds[i] ==
1373 pkt->hdr.cmd) {
1374 reclaim = false;
1375 break;
1376 }
1377 }
1378 }
1379
1380 if (rxq->id == IWL_DEFAULT_RX_QUEUE)
1381 iwl_op_mode_rx(trans->op_mode, &rxq->napi,
1382 &rxcb);
1383 else
1384 iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi,
1385 &rxcb, rxq->id);
1386
1387 /*
1388 * After here, we should always check rxcb._page_stolen,
1389 * if it is true then one of the handlers took the page.
1390 */
1391
1392 if (reclaim && txq) {
1393 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1394 int index = SEQ_TO_INDEX(sequence);
1395 int cmd_index = iwl_txq_get_cmd_index(txq, index);
1396
1397 kfree_sensitive(txq->entries[cmd_index].free_buf);
1398 txq->entries[cmd_index].free_buf = NULL;
1399
1400 /* Invoke any callbacks, transfer the buffer to caller,
1401 * and fire off the (possibly) blocking
1402 * iwl_trans_send_cmd()
1403 * as we reclaim the driver command queue */
1404 if (!rxcb._page_stolen)
1405 iwl_pcie_hcmd_complete(trans, &rxcb);
1406 else
1407 IWL_WARN(trans, "Claim null rxb?\n");
1408 }
1409
1410 page_stolen |= rxcb._page_stolen;
1411 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1412 break;
1413 }
1414
1415 /* page was stolen from us -- free our reference */
1416 if (page_stolen) {
1417 __free_pages(rxb->page, trans_pcie->rx_page_order);
1418 rxb->page = NULL;
1419 }
1420
1421 /* Reuse the page if possible. For notification packets and
1422 * SKBs that fail to Rx correctly, add them back into the
1423 * rx_free list for reuse later. */
1424 if (rxb->page != NULL) {
1425 rxb->page_dma =
1426 dma_map_page(trans->dev, rxb->page, rxb->offset,
1427 trans_pcie->rx_buf_bytes,
1428 DMA_FROM_DEVICE);
1429 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
1430 /*
1431 * free the page(s) as well to not break
1432 * the invariant that the items on the used
1433 * list have no page(s)
1434 */
1435 __free_pages(rxb->page, trans_pcie->rx_page_order);
1436 rxb->page = NULL;
1437 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1438 } else {
1439 list_add_tail(&rxb->list, &rxq->rx_free);
1440 rxq->free_count++;
1441 }
1442 } else
1443 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1444 }
1445
iwl_pcie_get_rxb(struct iwl_trans * trans,struct iwl_rxq * rxq,int i,bool * join)1446 static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans,
1447 struct iwl_rxq *rxq, int i,
1448 bool *join)
1449 {
1450 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1451 struct iwl_rx_mem_buffer *rxb;
1452 u16 vid;
1453
1454 BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc) != 32);
1455 BUILD_BUG_ON(sizeof(struct iwl_rx_completion_desc_bz) != 4);
1456
1457 if (!trans->mac_cfg->mq_rx_supported) {
1458 rxb = rxq->queue[i];
1459 rxq->queue[i] = NULL;
1460 return rxb;
1461 }
1462
1463 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
1464 struct iwl_rx_completion_desc_bz *cd = rxq->used_bd;
1465
1466 vid = le16_to_cpu(cd[i].rbid);
1467 *join = cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED;
1468 } else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1469 struct iwl_rx_completion_desc *cd = rxq->used_bd;
1470
1471 vid = le16_to_cpu(cd[i].rbid);
1472 *join = cd[i].flags & IWL_RX_CD_FLAGS_FRAGMENTED;
1473 } else {
1474 __le32 *cd = rxq->used_bd;
1475
1476 vid = le32_to_cpu(cd[i]) & 0x0FFF; /* 12-bit VID */
1477 }
1478
1479 if (!vid || vid > RX_POOL_SIZE(trans_pcie->num_rx_bufs))
1480 goto out_err;
1481
1482 rxb = trans_pcie->global_table[vid - 1];
1483 if (rxb->invalid)
1484 goto out_err;
1485
1486 IWL_DEBUG_RX(trans, "Got virtual RB ID %u\n", (u32)rxb->vid);
1487
1488 rxb->invalid = true;
1489
1490 return rxb;
1491
1492 out_err:
1493 WARN(1, "Invalid rxb from HW %u\n", (u32)vid);
1494 iwl_force_nmi(trans);
1495 return NULL;
1496 }
1497
1498 /*
1499 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
1500 */
iwl_pcie_rx_handle(struct iwl_trans * trans,int queue,int budget)1501 static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget)
1502 {
1503 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1504 struct iwl_rxq *rxq;
1505 u32 r, i, count = 0, handled = 0;
1506 bool emergency = false;
1507
1508 if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd))
1509 return budget;
1510
1511 rxq = &trans_pcie->rxq[queue];
1512
1513 restart:
1514 spin_lock(&rxq->lock);
1515 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1516 * buffer that the driver may process (last buffer filled by ucode). */
1517 r = iwl_get_closed_rb_stts(trans, rxq);
1518 i = rxq->read;
1519
1520 /* W/A 9000 device step A0 wrap-around bug */
1521 r &= (rxq->queue_size - 1);
1522
1523 /* Rx interrupt, but nothing sent from uCode */
1524 if (i == r)
1525 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r);
1526
1527 while (i != r && ++handled < budget) {
1528 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1529 struct iwl_rx_mem_buffer *rxb;
1530 /* number of RBDs still waiting for page allocation */
1531 u32 rb_pending_alloc =
1532 atomic_read(&trans_pcie->rba.req_pending) *
1533 RX_CLAIM_REQ_ALLOC;
1534 bool join = false;
1535
1536 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 &&
1537 !emergency)) {
1538 iwl_pcie_rx_move_to_allocator(rxq, rba);
1539 emergency = true;
1540 IWL_DEBUG_TPT(trans,
1541 "RX path is in emergency. Pending allocations %d\n",
1542 rb_pending_alloc);
1543 }
1544
1545 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i);
1546
1547 rxb = iwl_pcie_get_rxb(trans, rxq, i, &join);
1548 if (!rxb)
1549 goto out;
1550
1551 if (unlikely(join || rxq->next_rb_is_fragment)) {
1552 rxq->next_rb_is_fragment = join;
1553 /*
1554 * We can only get a multi-RB in the following cases:
1555 * - firmware issue, sending a too big notification
1556 * - sniffer mode with a large A-MSDU
1557 * - large MTU frames (>2k)
1558 * since the multi-RB functionality is limited to newer
1559 * hardware that cannot put multiple entries into a
1560 * single RB.
1561 *
1562 * Right now, the higher layers aren't set up to deal
1563 * with that, so discard all of these.
1564 */
1565 list_add_tail(&rxb->list, &rxq->rx_free);
1566 rxq->free_count++;
1567 } else {
1568 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i);
1569 }
1570
1571 i = (i + 1) & (rxq->queue_size - 1);
1572
1573 /*
1574 * If we have RX_CLAIM_REQ_ALLOC released rx buffers -
1575 * try to claim the pre-allocated buffers from the allocator.
1576 * If not ready - will try to reclaim next time.
1577 * There is no need to reschedule work - allocator exits only
1578 * on success
1579 */
1580 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC)
1581 iwl_pcie_rx_allocator_get(trans, rxq);
1582
1583 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) {
1584 /* Add the remaining empty RBDs for allocator use */
1585 iwl_pcie_rx_move_to_allocator(rxq, rba);
1586 } else if (emergency) {
1587 count++;
1588 if (count == 8) {
1589 count = 0;
1590 if (rb_pending_alloc < rxq->queue_size / 3) {
1591 IWL_DEBUG_TPT(trans,
1592 "RX path exited emergency. Pending allocations %d\n",
1593 rb_pending_alloc);
1594 emergency = false;
1595 }
1596
1597 rxq->read = i;
1598 spin_unlock(&rxq->lock);
1599 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1600 iwl_pcie_rxq_restock(trans, rxq);
1601 goto restart;
1602 }
1603 }
1604 }
1605 out:
1606 /* Backtrack one entry */
1607 rxq->read = i;
1608 spin_unlock(&rxq->lock);
1609
1610 /*
1611 * handle a case where in emergency there are some unallocated RBDs.
1612 * those RBDs are in the used list, but are not tracked by the queue's
1613 * used_count which counts allocator owned RBDs.
1614 * unallocated emergency RBDs must be allocated on exit, otherwise
1615 * when called again the function may not be in emergency mode and
1616 * they will be handed to the allocator with no tracking in the RBD
1617 * allocator counters, which will lead to them never being claimed back
1618 * by the queue.
1619 * by allocating them here, they are now in the queue free list, and
1620 * will be restocked by the next call of iwl_pcie_rxq_restock.
1621 */
1622 if (unlikely(emergency && count))
1623 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1624
1625 iwl_pcie_rxq_restock(trans, rxq);
1626
1627 return handled;
1628 }
1629
iwl_pcie_get_trans_pcie(struct msix_entry * entry)1630 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry)
1631 {
1632 u8 queue = entry->entry;
1633 struct msix_entry *entries = entry - queue;
1634
1635 return container_of(entries, struct iwl_trans_pcie, msix_entries[0]);
1636 }
1637
1638 /*
1639 * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw
1640 * This interrupt handler should be used with RSS queue only.
1641 */
iwl_pcie_irq_rx_msix_handler(int irq,void * dev_id)1642 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id)
1643 {
1644 struct msix_entry *entry = dev_id;
1645 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
1646 struct iwl_trans *trans = trans_pcie->trans;
1647 struct iwl_rxq *rxq;
1648
1649 trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0);
1650
1651 if (WARN_ON(entry->entry >= trans->info.num_rxqs))
1652 return IRQ_NONE;
1653
1654 if (!trans_pcie->rxq) {
1655 if (net_ratelimit())
1656 IWL_ERR(trans,
1657 "[%d] Got MSI-X interrupt before we have Rx queues\n",
1658 entry->entry);
1659 return IRQ_NONE;
1660 }
1661
1662 rxq = &trans_pcie->rxq[entry->entry];
1663 lock_map_acquire(&trans->sync_cmd_lockdep_map);
1664 IWL_DEBUG_ISR(trans, "[%d] Got interrupt\n", entry->entry);
1665
1666 local_bh_disable();
1667 if (!napi_schedule(&rxq->napi))
1668 iwl_pcie_clear_irq(trans, entry->entry);
1669 local_bh_enable();
1670
1671 lock_map_release(&trans->sync_cmd_lockdep_map);
1672
1673 return IRQ_HANDLED;
1674 }
1675
1676 /*
1677 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
1678 */
iwl_pcie_irq_handle_error(struct iwl_trans * trans)1679 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
1680 {
1681 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1682 int i;
1683
1684 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
1685 if (trans->cfg->internal_wimax_coex &&
1686 !trans->mac_cfg->base->apmg_not_supported &&
1687 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
1688 APMS_CLK_VAL_MRB_FUNC_MODE) ||
1689 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
1690 APMG_PS_CTRL_VAL_RESET_REQ))) {
1691 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1692 iwl_op_mode_wimax_active(trans->op_mode);
1693 wake_up(&trans_pcie->wait_command_queue);
1694 return;
1695 }
1696
1697 for (i = 0; i < trans->mac_cfg->base->num_of_queues; i++) {
1698 if (!trans_pcie->txqs.txq[i])
1699 continue;
1700 timer_delete(&trans_pcie->txqs.txq[i]->stuck_timer);
1701 }
1702
1703 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_SC) {
1704 u32 val = iwl_read32(trans, CSR_IPC_STATE);
1705
1706 if (val & CSR_IPC_STATE_TOP_RESET_REQ) {
1707 IWL_ERR(trans, "FW requested TOP reset for FSEQ\n");
1708 trans->do_top_reset = 1;
1709 }
1710 }
1711
1712 /* The STATUS_FW_ERROR bit is set in this function. This must happen
1713 * before we wake up the command caller, to ensure a proper cleanup. */
1714 iwl_trans_fw_error(trans, IWL_ERR_TYPE_IRQ);
1715
1716 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1717 wake_up(&trans_pcie->wait_command_queue);
1718 }
1719
iwl_pcie_int_cause_non_ict(struct iwl_trans * trans)1720 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
1721 {
1722 u32 inta;
1723
1724 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock);
1725
1726 trace_iwlwifi_dev_irq(trans->dev);
1727
1728 /* Discover which interrupts are active/pending */
1729 inta = iwl_read32(trans, CSR_INT);
1730
1731 /* the thread will service interrupts and re-enable them */
1732 return inta;
1733 }
1734
1735 /* a device (PCI-E) page is 4096 bytes long */
1736 #define ICT_SHIFT 12
1737 #define ICT_SIZE (1 << ICT_SHIFT)
1738 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1739
1740 /* interrupt handler using ict table, with this interrupt driver will
1741 * stop using INTA register to get device's interrupt, reading this register
1742 * is expensive, device will write interrupts in ICT dram table, increment
1743 * index then will fire interrupt to driver, driver will OR all ICT table
1744 * entries from current index up to table entry with 0 value. the result is
1745 * the interrupt we need to service, driver will set the entries back to 0 and
1746 * set index.
1747 */
iwl_pcie_int_cause_ict(struct iwl_trans * trans)1748 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
1749 {
1750 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1751 u32 inta;
1752 u32 val = 0;
1753 u32 read;
1754
1755 trace_iwlwifi_dev_irq(trans->dev);
1756
1757 /* Ignore interrupt if there's nothing in NIC to service.
1758 * This may be due to IRQ shared with another device,
1759 * or due to sporadic interrupts thrown from our NIC. */
1760 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1761 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1762 if (!read)
1763 return 0;
1764
1765 /*
1766 * Collect all entries up to the first 0, starting from ict_index;
1767 * note we already read at ict_index.
1768 */
1769 do {
1770 val |= read;
1771 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1772 trans_pcie->ict_index, read);
1773 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1774 trans_pcie->ict_index =
1775 ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1));
1776
1777 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1778 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1779 read);
1780 } while (read);
1781
1782 /* We should not get this value, just ignore it. */
1783 if (val == 0xffffffff)
1784 val = 0;
1785
1786 /*
1787 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1788 * (bit 15 before shifting it to 31) to clear when using interrupt
1789 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1790 * so we use them to decide on the real state of the Rx bit.
1791 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1792 */
1793 if (val & 0xC0000)
1794 val |= 0x8000;
1795
1796 inta = (0xff & val) | ((0xff00 & val) << 16);
1797 return inta;
1798 }
1799
iwl_pcie_handle_rfkill_irq(struct iwl_trans * trans,bool from_irq)1800 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans, bool from_irq)
1801 {
1802 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1803 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1804 bool hw_rfkill, prev, report;
1805
1806 mutex_lock(&trans_pcie->mutex);
1807 prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1808 hw_rfkill = iwl_is_rfkill_set(trans);
1809 if (hw_rfkill) {
1810 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1811 set_bit(STATUS_RFKILL_HW, &trans->status);
1812 }
1813 if (trans_pcie->opmode_down)
1814 report = hw_rfkill;
1815 else
1816 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1817
1818 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1819 hw_rfkill ? "disable radio" : "enable radio");
1820
1821 isr_stats->rfkill++;
1822
1823 if (prev != report)
1824 iwl_trans_pcie_rf_kill(trans, report, from_irq);
1825 mutex_unlock(&trans_pcie->mutex);
1826
1827 if (hw_rfkill) {
1828 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
1829 &trans->status))
1830 IWL_DEBUG_RF_KILL(trans,
1831 "Rfkill while SYNC HCMD in flight\n");
1832 wake_up(&trans_pcie->wait_command_queue);
1833 } else {
1834 clear_bit(STATUS_RFKILL_HW, &trans->status);
1835 if (trans_pcie->opmode_down)
1836 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1837 }
1838 }
1839
iwl_trans_pcie_handle_reset_interrupt(struct iwl_trans * trans)1840 static void iwl_trans_pcie_handle_reset_interrupt(struct iwl_trans *trans)
1841 {
1842 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1843 u32 state;
1844
1845 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_SC) {
1846 u32 val = iwl_read32(trans, CSR_IPC_STATE);
1847
1848 state = u32_get_bits(val, CSR_IPC_STATE_RESET);
1849 IWL_DEBUG_ISR(trans, "IPC state = 0x%x/%d\n", val, state);
1850 } else {
1851 state = CSR_IPC_STATE_RESET_SW_READY;
1852 }
1853
1854 switch (state) {
1855 case CSR_IPC_STATE_RESET_SW_READY:
1856 if (trans_pcie->fw_reset_state == FW_RESET_REQUESTED) {
1857 IWL_DEBUG_ISR(trans, "Reset flow completed\n");
1858 trans_pcie->fw_reset_state = FW_RESET_OK;
1859 wake_up(&trans_pcie->fw_reset_waitq);
1860 break;
1861 }
1862 fallthrough;
1863 case CSR_IPC_STATE_RESET_TOP_READY:
1864 if (trans_pcie->fw_reset_state == FW_RESET_TOP_REQUESTED) {
1865 IWL_DEBUG_ISR(trans, "TOP Reset continues\n");
1866 trans_pcie->fw_reset_state = FW_RESET_OK;
1867 wake_up(&trans_pcie->fw_reset_waitq);
1868 break;
1869 }
1870 fallthrough;
1871 case CSR_IPC_STATE_RESET_NONE:
1872 IWL_FW_CHECK_FAILED(trans,
1873 "Invalid reset interrupt (state=%d)!\n",
1874 state);
1875 break;
1876 case CSR_IPC_STATE_RESET_TOP_FOLLOWER:
1877 if (trans_pcie->fw_reset_state == FW_RESET_REQUESTED) {
1878 /* if we were in reset, wake that up */
1879 IWL_INFO(trans,
1880 "TOP reset from BT while doing reset\n");
1881 trans_pcie->fw_reset_state = FW_RESET_OK;
1882 wake_up(&trans_pcie->fw_reset_waitq);
1883 } else {
1884 IWL_INFO(trans, "TOP reset from BT\n");
1885 trans->state = IWL_TRANS_NO_FW;
1886 iwl_trans_schedule_reset(trans,
1887 IWL_ERR_TYPE_TOP_RESET_BY_BT);
1888 }
1889 break;
1890 }
1891 }
1892
iwl_pcie_irq_handler(int irq,void * dev_id)1893 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
1894 {
1895 struct iwl_trans *trans = dev_id;
1896 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1897 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1898 u32 inta = 0;
1899 u32 handled = 0;
1900 bool polling = false;
1901
1902 lock_map_acquire(&trans->sync_cmd_lockdep_map);
1903
1904 spin_lock_bh(&trans_pcie->irq_lock);
1905
1906 /* dram interrupt table not set yet,
1907 * use legacy interrupt.
1908 */
1909 if (likely(trans_pcie->use_ict))
1910 inta = iwl_pcie_int_cause_ict(trans);
1911 else
1912 inta = iwl_pcie_int_cause_non_ict(trans);
1913
1914 if (iwl_have_debug_level(IWL_DL_ISR)) {
1915 IWL_DEBUG_ISR(trans,
1916 "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
1917 inta, trans_pcie->inta_mask,
1918 iwl_read32(trans, CSR_INT_MASK),
1919 iwl_read32(trans, CSR_FH_INT_STATUS));
1920 if (inta & (~trans_pcie->inta_mask))
1921 IWL_DEBUG_ISR(trans,
1922 "We got a masked interrupt (0x%08x)\n",
1923 inta & (~trans_pcie->inta_mask));
1924 }
1925
1926 inta &= trans_pcie->inta_mask;
1927
1928 /*
1929 * Ignore interrupt if there's nothing in NIC to service.
1930 * This may be due to IRQ shared with another device,
1931 * or due to sporadic interrupts thrown from our NIC.
1932 */
1933 if (unlikely(!inta)) {
1934 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1935 /*
1936 * Re-enable interrupts here since we don't
1937 * have anything to service
1938 */
1939 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1940 _iwl_enable_interrupts(trans);
1941 spin_unlock_bh(&trans_pcie->irq_lock);
1942 lock_map_release(&trans->sync_cmd_lockdep_map);
1943 return IRQ_NONE;
1944 }
1945
1946 if (unlikely(inta == 0xFFFFFFFF || iwl_trans_is_hw_error_value(inta))) {
1947 /*
1948 * Hardware disappeared. It might have
1949 * already raised an interrupt.
1950 */
1951 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1952 spin_unlock_bh(&trans_pcie->irq_lock);
1953 goto out;
1954 }
1955
1956 /* Ack/clear/reset pending uCode interrupts.
1957 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1958 */
1959 /* There is a hardware bug in the interrupt mask function that some
1960 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1961 * they are disabled in the CSR_INT_MASK register. Furthermore the
1962 * ICT interrupt handling mechanism has another bug that might cause
1963 * these unmasked interrupts fail to be detected. We workaround the
1964 * hardware bugs here by ACKing all the possible interrupts so that
1965 * interrupt coalescing can still be achieved.
1966 */
1967 iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
1968
1969 if (iwl_have_debug_level(IWL_DL_ISR))
1970 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1971 inta, iwl_read32(trans, CSR_INT_MASK));
1972
1973 spin_unlock_bh(&trans_pcie->irq_lock);
1974
1975 /* Now service all interrupt bits discovered above. */
1976 if (inta & CSR_INT_BIT_HW_ERR) {
1977 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
1978
1979 /* Tell the device to stop sending interrupts */
1980 iwl_disable_interrupts(trans);
1981
1982 isr_stats->hw++;
1983 iwl_pcie_irq_handle_error(trans);
1984
1985 handled |= CSR_INT_BIT_HW_ERR;
1986
1987 goto out;
1988 }
1989
1990 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1991 if (inta & CSR_INT_BIT_SCD) {
1992 IWL_DEBUG_ISR(trans,
1993 "Scheduler finished to transmit the frame/frames.\n");
1994 isr_stats->sch++;
1995 }
1996
1997 /* Alive notification via Rx interrupt will do the real work */
1998 if (inta & CSR_INT_BIT_ALIVE) {
1999 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
2000 isr_stats->alive++;
2001 if (trans->mac_cfg->gen2) {
2002 /*
2003 * We can restock, since firmware configured
2004 * the RFH
2005 */
2006 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
2007 }
2008
2009 handled |= CSR_INT_BIT_ALIVE;
2010 }
2011
2012 if (inta & CSR_INT_BIT_RESET_DONE) {
2013 iwl_trans_pcie_handle_reset_interrupt(trans);
2014 handled |= CSR_INT_BIT_RESET_DONE;
2015 }
2016
2017 /* Safely ignore these bits for debug checks below */
2018 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
2019
2020 /* HW RF KILL switch toggled */
2021 if (inta & CSR_INT_BIT_RF_KILL) {
2022 iwl_pcie_handle_rfkill_irq(trans, true);
2023 handled |= CSR_INT_BIT_RF_KILL;
2024 }
2025
2026 /* Chip got too hot and stopped itself */
2027 if (inta & CSR_INT_BIT_CT_KILL) {
2028 IWL_ERR(trans, "Microcode CT kill error detected.\n");
2029 isr_stats->ctkill++;
2030 handled |= CSR_INT_BIT_CT_KILL;
2031 }
2032
2033 /* Error detected by uCode */
2034 if (inta & CSR_INT_BIT_SW_ERR) {
2035 IWL_ERR(trans, "Microcode SW error detected. "
2036 " Restarting 0x%X.\n", inta);
2037 isr_stats->sw++;
2038 if (trans_pcie->fw_reset_state == FW_RESET_REQUESTED) {
2039 trans_pcie->fw_reset_state = FW_RESET_ERROR;
2040 wake_up(&trans_pcie->fw_reset_waitq);
2041 } else {
2042 iwl_pcie_irq_handle_error(trans);
2043 }
2044 handled |= CSR_INT_BIT_SW_ERR;
2045 }
2046
2047 /* uCode wakes up after power-down sleep */
2048 if (inta & CSR_INT_BIT_WAKEUP) {
2049 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
2050 iwl_pcie_rxq_check_wrptr(trans);
2051 iwl_pcie_txq_check_wrptrs(trans);
2052
2053 isr_stats->wakeup++;
2054
2055 handled |= CSR_INT_BIT_WAKEUP;
2056 }
2057
2058 /* All uCode command responses, including Tx command responses,
2059 * Rx "responses" (frame-received notification), and other
2060 * notifications from uCode come through here*/
2061 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
2062 CSR_INT_BIT_RX_PERIODIC)) {
2063 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
2064 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
2065 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
2066 iwl_write32(trans, CSR_FH_INT_STATUS,
2067 CSR_FH_INT_RX_MASK);
2068 }
2069 if (inta & CSR_INT_BIT_RX_PERIODIC) {
2070 handled |= CSR_INT_BIT_RX_PERIODIC;
2071 iwl_write32(trans,
2072 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
2073 }
2074 /* Sending RX interrupt require many steps to be done in the
2075 * device:
2076 * 1- write interrupt to current index in ICT table.
2077 * 2- dma RX frame.
2078 * 3- update RX shared data to indicate last write index.
2079 * 4- send interrupt.
2080 * This could lead to RX race, driver could receive RX interrupt
2081 * but the shared data changes does not reflect this;
2082 * periodic interrupt will detect any dangling Rx activity.
2083 */
2084
2085 /* Disable periodic interrupt; we use it as just a one-shot. */
2086 iwl_write8(trans, CSR_INT_PERIODIC_REG,
2087 CSR_INT_PERIODIC_DIS);
2088
2089 /*
2090 * Enable periodic interrupt in 8 msec only if we received
2091 * real RX interrupt (instead of just periodic int), to catch
2092 * any dangling Rx interrupt. If it was just the periodic
2093 * interrupt, there was no dangling Rx activity, and no need
2094 * to extend the periodic interrupt; one-shot is enough.
2095 */
2096 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
2097 iwl_write8(trans, CSR_INT_PERIODIC_REG,
2098 CSR_INT_PERIODIC_ENA);
2099
2100 isr_stats->rx++;
2101
2102 local_bh_disable();
2103 if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) {
2104 polling = true;
2105 __napi_schedule(&trans_pcie->rxq[0].napi);
2106 }
2107 local_bh_enable();
2108 }
2109
2110 /* This "Tx" DMA channel is used only for loading uCode */
2111 if (inta & CSR_INT_BIT_FH_TX) {
2112 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
2113 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2114 isr_stats->tx++;
2115 handled |= CSR_INT_BIT_FH_TX;
2116 /* Wake up uCode load routine, now that load is complete */
2117 trans_pcie->ucode_write_complete = true;
2118 wake_up(&trans_pcie->ucode_write_waitq);
2119 /* Wake up IMR write routine, now that write to SRAM is complete */
2120 if (trans_pcie->imr_status == IMR_D2S_REQUESTED) {
2121 trans_pcie->imr_status = IMR_D2S_COMPLETED;
2122 wake_up(&trans_pcie->ucode_write_waitq);
2123 }
2124 }
2125
2126 if (inta & ~handled) {
2127 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
2128 isr_stats->unhandled++;
2129 }
2130
2131 if (inta & ~(trans_pcie->inta_mask)) {
2132 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
2133 inta & ~trans_pcie->inta_mask);
2134 }
2135
2136 if (!polling) {
2137 spin_lock_bh(&trans_pcie->irq_lock);
2138 /* only Re-enable all interrupt if disabled by irq */
2139 if (test_bit(STATUS_INT_ENABLED, &trans->status))
2140 _iwl_enable_interrupts(trans);
2141 /* we are loading the firmware, enable FH_TX interrupt only */
2142 else if (handled & CSR_INT_BIT_FH_TX)
2143 iwl_enable_fw_load_int(trans);
2144 /* Re-enable RF_KILL if it occurred */
2145 else if (handled & CSR_INT_BIT_RF_KILL)
2146 iwl_enable_rfkill_int(trans);
2147 /* Re-enable the ALIVE / Rx interrupt if it occurred */
2148 else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX))
2149 iwl_enable_fw_load_int_ctx_info(trans, false);
2150 spin_unlock_bh(&trans_pcie->irq_lock);
2151 }
2152
2153 out:
2154 lock_map_release(&trans->sync_cmd_lockdep_map);
2155 return IRQ_HANDLED;
2156 }
2157
2158 /******************************************************************************
2159 *
2160 * ICT functions
2161 *
2162 ******************************************************************************/
2163
2164 /* Free dram table */
iwl_pcie_free_ict(struct iwl_trans * trans)2165 void iwl_pcie_free_ict(struct iwl_trans *trans)
2166 {
2167 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2168
2169 if (trans_pcie->ict_tbl) {
2170 dma_free_coherent(trans->dev, ICT_SIZE,
2171 trans_pcie->ict_tbl,
2172 trans_pcie->ict_tbl_dma);
2173 trans_pcie->ict_tbl = NULL;
2174 trans_pcie->ict_tbl_dma = 0;
2175 }
2176 }
2177
2178 /*
2179 * allocate dram shared table, it is an aligned memory
2180 * block of ICT_SIZE.
2181 * also reset all data related to ICT table interrupt.
2182 */
iwl_pcie_alloc_ict(struct iwl_trans * trans)2183 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
2184 {
2185 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2186
2187 trans_pcie->ict_tbl =
2188 dma_alloc_coherent(trans->dev, ICT_SIZE,
2189 &trans_pcie->ict_tbl_dma, GFP_KERNEL);
2190 if (!trans_pcie->ict_tbl)
2191 return -ENOMEM;
2192
2193 /* just an API sanity check ... it is guaranteed to be aligned */
2194 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
2195 iwl_pcie_free_ict(trans);
2196 return -EINVAL;
2197 }
2198
2199 return 0;
2200 }
2201
2202 /* Device is going up inform it about using ICT interrupt table,
2203 * also we need to tell the driver to start using ICT interrupt.
2204 */
iwl_pcie_reset_ict(struct iwl_trans * trans)2205 void iwl_pcie_reset_ict(struct iwl_trans *trans)
2206 {
2207 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2208 u32 val;
2209
2210 if (!trans_pcie->ict_tbl)
2211 return;
2212
2213 spin_lock_bh(&trans_pcie->irq_lock);
2214 _iwl_disable_interrupts(trans);
2215
2216 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
2217
2218 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
2219
2220 val |= CSR_DRAM_INT_TBL_ENABLE |
2221 CSR_DRAM_INIT_TBL_WRAP_CHECK |
2222 CSR_DRAM_INIT_TBL_WRITE_POINTER;
2223
2224 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
2225
2226 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
2227 trans_pcie->use_ict = true;
2228 trans_pcie->ict_index = 0;
2229 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
2230 _iwl_enable_interrupts(trans);
2231 spin_unlock_bh(&trans_pcie->irq_lock);
2232 }
2233
2234 /* Device is going down disable ict interrupt usage */
iwl_pcie_disable_ict(struct iwl_trans * trans)2235 void iwl_pcie_disable_ict(struct iwl_trans *trans)
2236 {
2237 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2238
2239 spin_lock_bh(&trans_pcie->irq_lock);
2240 trans_pcie->use_ict = false;
2241 spin_unlock_bh(&trans_pcie->irq_lock);
2242 }
2243
iwl_pcie_isr(int irq,void * data)2244 irqreturn_t iwl_pcie_isr(int irq, void *data)
2245 {
2246 struct iwl_trans *trans = data;
2247
2248 if (!trans)
2249 return IRQ_NONE;
2250
2251 /* Disable (but don't clear!) interrupts here to avoid
2252 * back-to-back ISRs and sporadic interrupts from our NIC.
2253 * If we have something to service, the tasklet will re-enable ints.
2254 * If we *don't* have something, we'll re-enable before leaving here.
2255 */
2256 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
2257
2258 return IRQ_WAKE_THREAD;
2259 }
2260
iwl_pcie_msix_isr(int irq,void * data)2261 irqreturn_t iwl_pcie_msix_isr(int irq, void *data)
2262 {
2263 return IRQ_WAKE_THREAD;
2264 }
2265
iwl_pcie_irq_msix_handler(int irq,void * dev_id)2266 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
2267 {
2268 struct msix_entry *entry = dev_id;
2269 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
2270 struct iwl_trans *trans = trans_pcie->trans;
2271 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2272 u32 inta_fh_msk = ~MSIX_FH_INT_CAUSES_DATA_QUEUE;
2273 u32 inta_fh, inta_hw;
2274 bool polling = false;
2275 bool sw_err;
2276
2277 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
2278 inta_fh_msk |= MSIX_FH_INT_CAUSES_Q0;
2279
2280 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
2281 inta_fh_msk |= MSIX_FH_INT_CAUSES_Q1;
2282
2283 lock_map_acquire(&trans->sync_cmd_lockdep_map);
2284
2285 spin_lock_bh(&trans_pcie->irq_lock);
2286 inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
2287 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
2288 /*
2289 * Clear causes registers to avoid being handling the same cause.
2290 */
2291 iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk);
2292 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
2293 spin_unlock_bh(&trans_pcie->irq_lock);
2294
2295 trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw);
2296
2297 if (unlikely(!(inta_fh | inta_hw))) {
2298 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
2299 lock_map_release(&trans->sync_cmd_lockdep_map);
2300 return IRQ_NONE;
2301 }
2302
2303 if (iwl_have_debug_level(IWL_DL_ISR)) {
2304 IWL_DEBUG_ISR(trans,
2305 "ISR[%d] inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2306 entry->entry, inta_fh, trans_pcie->fh_mask,
2307 iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
2308 if (inta_fh & ~trans_pcie->fh_mask)
2309 IWL_DEBUG_ISR(trans,
2310 "We got a masked interrupt (0x%08x)\n",
2311 inta_fh & ~trans_pcie->fh_mask);
2312 }
2313
2314 inta_fh &= trans_pcie->fh_mask;
2315
2316 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) &&
2317 inta_fh & MSIX_FH_INT_CAUSES_Q0) {
2318 local_bh_disable();
2319 if (napi_schedule_prep(&trans_pcie->rxq[0].napi)) {
2320 polling = true;
2321 __napi_schedule(&trans_pcie->rxq[0].napi);
2322 }
2323 local_bh_enable();
2324 }
2325
2326 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) &&
2327 inta_fh & MSIX_FH_INT_CAUSES_Q1) {
2328 local_bh_disable();
2329 if (napi_schedule_prep(&trans_pcie->rxq[1].napi)) {
2330 polling = true;
2331 __napi_schedule(&trans_pcie->rxq[1].napi);
2332 }
2333 local_bh_enable();
2334 }
2335
2336 /* This "Tx" DMA channel is used only for loading uCode */
2337 if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM &&
2338 trans_pcie->imr_status == IMR_D2S_REQUESTED) {
2339 IWL_DEBUG_ISR(trans, "IMR Complete interrupt\n");
2340 isr_stats->tx++;
2341
2342 /* Wake up IMR routine once write to SRAM is complete */
2343 if (trans_pcie->imr_status == IMR_D2S_REQUESTED) {
2344 trans_pcie->imr_status = IMR_D2S_COMPLETED;
2345 wake_up(&trans_pcie->ucode_write_waitq);
2346 }
2347 } else if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) {
2348 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2349 isr_stats->tx++;
2350 /*
2351 * Wake up uCode load routine,
2352 * now that load is complete
2353 */
2354 trans_pcie->ucode_write_complete = true;
2355 wake_up(&trans_pcie->ucode_write_waitq);
2356
2357 /* Wake up IMR routine once write to SRAM is complete */
2358 if (trans_pcie->imr_status == IMR_D2S_REQUESTED) {
2359 trans_pcie->imr_status = IMR_D2S_COMPLETED;
2360 wake_up(&trans_pcie->ucode_write_waitq);
2361 }
2362 }
2363
2364 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
2365 sw_err = inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ;
2366 else
2367 sw_err = inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR;
2368
2369 if (inta_hw & MSIX_HW_INT_CAUSES_REG_TOP_FATAL_ERR) {
2370 IWL_ERR(trans, "TOP Fatal error detected, inta_hw=0x%x.\n",
2371 inta_hw);
2372 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
2373 trans->request_top_reset = 1;
2374 iwl_op_mode_nic_error(trans->op_mode,
2375 IWL_ERR_TYPE_TOP_FATAL_ERROR);
2376 iwl_trans_schedule_reset(trans,
2377 IWL_ERR_TYPE_TOP_FATAL_ERROR);
2378 }
2379 }
2380
2381 /* Error detected by uCode */
2382 if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) || sw_err) {
2383 IWL_ERR(trans,
2384 "Microcode SW error detected. Restarting 0x%X.\n",
2385 inta_fh);
2386 isr_stats->sw++;
2387 /* during FW reset flow report errors from there */
2388 if (trans_pcie->imr_status == IMR_D2S_REQUESTED) {
2389 trans_pcie->imr_status = IMR_D2S_ERROR;
2390 wake_up(&trans_pcie->imr_waitq);
2391 } else if (trans_pcie->fw_reset_state == FW_RESET_REQUESTED) {
2392 trans_pcie->fw_reset_state = FW_RESET_ERROR;
2393 wake_up(&trans_pcie->fw_reset_waitq);
2394 } else {
2395 iwl_pcie_irq_handle_error(trans);
2396 }
2397
2398 if (trans_pcie->sx_state == IWL_SX_WAITING) {
2399 trans_pcie->sx_state = IWL_SX_ERROR;
2400 wake_up(&trans_pcie->sx_waitq);
2401 }
2402 }
2403
2404 /* After checking FH register check HW register */
2405 if (iwl_have_debug_level(IWL_DL_ISR)) {
2406 IWL_DEBUG_ISR(trans,
2407 "ISR[%d] inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2408 entry->entry, inta_hw, trans_pcie->hw_mask,
2409 iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
2410 if (inta_hw & ~trans_pcie->hw_mask)
2411 IWL_DEBUG_ISR(trans,
2412 "We got a masked interrupt 0x%08x\n",
2413 inta_hw & ~trans_pcie->hw_mask);
2414 }
2415
2416 inta_hw &= trans_pcie->hw_mask;
2417
2418 /* Alive notification via Rx interrupt will do the real work */
2419 if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) {
2420 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
2421 isr_stats->alive++;
2422 if (trans->mac_cfg->gen2) {
2423 /* We can restock, since firmware configured the RFH */
2424 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
2425 }
2426 }
2427
2428 /*
2429 * In some rare cases when the HW is in a bad state, we may
2430 * get this interrupt too early, when prph_info is still NULL.
2431 * So make sure that it's not NULL to prevent crashing.
2432 */
2433 if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP && trans_pcie->prph_info) {
2434 u32 sleep_notif =
2435 le32_to_cpu(trans_pcie->prph_info->sleep_notif);
2436
2437 if (sleep_notif == IWL_D3_SLEEP_STATUS_SUSPEND ||
2438 sleep_notif == IWL_D3_SLEEP_STATUS_RESUME) {
2439 IWL_DEBUG_ISR(trans,
2440 "Sx interrupt: sleep notification = 0x%x\n",
2441 sleep_notif);
2442 if (trans_pcie->sx_state == IWL_SX_WAITING) {
2443 trans_pcie->sx_state = IWL_SX_COMPLETE;
2444 wake_up(&trans_pcie->sx_waitq);
2445 } else {
2446 IWL_ERR(trans,
2447 "unexpected Sx interrupt (0x%x)\n",
2448 sleep_notif);
2449 }
2450 } else {
2451 /* uCode wakes up after power-down sleep */
2452 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
2453 iwl_pcie_rxq_check_wrptr(trans);
2454 iwl_pcie_txq_check_wrptrs(trans);
2455
2456 isr_stats->wakeup++;
2457 }
2458 }
2459
2460 /* Chip got too hot and stopped itself */
2461 if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) {
2462 IWL_ERR(trans, "Microcode CT kill error detected.\n");
2463 isr_stats->ctkill++;
2464 }
2465
2466 /* HW RF KILL switch toggled */
2467 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL)
2468 iwl_pcie_handle_rfkill_irq(trans, true);
2469
2470 if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) {
2471 IWL_ERR(trans,
2472 "Hardware error detected. Restarting.\n");
2473
2474 isr_stats->hw++;
2475 trans->dbg.hw_error = true;
2476 iwl_pcie_irq_handle_error(trans);
2477 }
2478
2479 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE)
2480 iwl_trans_pcie_handle_reset_interrupt(trans);
2481
2482 if (!polling)
2483 iwl_pcie_clear_irq(trans, entry->entry);
2484
2485 lock_map_release(&trans->sync_cmd_lockdep_map);
2486
2487 return IRQ_HANDLED;
2488 }
2489