1 /*-
2 * Copyright (C) 2006-2012 Semihalf
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
19 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
21 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
23 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25 /*-
26 * Copyright (C) 2001 Benno Rice
27 * All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 * 1. Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * 2. Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in the
36 * documentation and/or other materials provided with the distribution.
37 *
38 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
39 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
40 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
41 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
43 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
44 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
45 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
46 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
47 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
49 */
50 /*-
51 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
52 * Copyright (C) 1995, 1996 TooLs GmbH.
53 * All rights reserved.
54 *
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
57 * are met:
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
63 * 3. All advertising materials mentioning features or use of this software
64 * must display the following acknowledgement:
65 * This product includes software developed by TooLs GmbH.
66 * 4. The name of TooLs GmbH may not be used to endorse or promote products
67 * derived from this software without specific prior written permission.
68 *
69 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
72 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
73 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
74 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
75 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
76 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
77 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
78 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
79 */
80
81 #include <sys/cdefs.h>
82 #include "opt_ddb.h"
83 #include "opt_hwpmc_hooks.h"
84 #include "opt_kstack_pages.h"
85 #include "opt_platform.h"
86
87 #include <sys/types.h>
88 #include <sys/param.h>
89 #include <sys/proc.h>
90 #include <sys/systm.h>
91 #include <sys/time.h>
92 #include <sys/bio.h>
93 #include <sys/buf.h>
94 #include <sys/bus.h>
95 #include <sys/cons.h>
96 #include <sys/cpu.h>
97 #include <sys/kdb.h>
98 #include <sys/kernel.h>
99 #include <sys/lock.h>
100 #include <sys/mutex.h>
101 #include <sys/rwlock.h>
102 #include <sys/sysctl.h>
103 #include <sys/exec.h>
104 #include <sys/ktr.h>
105 #include <sys/syscallsubr.h>
106 #include <sys/sysproto.h>
107 #include <sys/signalvar.h>
108 #include <sys/sysent.h>
109 #include <sys/imgact.h>
110 #include <sys/msgbuf.h>
111 #include <sys/ptrace.h>
112
113 #include <vm/vm.h>
114 #include <vm/pmap.h>
115 #include <vm/vm_extern.h>
116 #include <vm/vm_page.h>
117 #include <vm/vm_object.h>
118 #include <vm/vm_pager.h>
119
120 #include <machine/cpu.h>
121 #include <machine/kdb.h>
122 #include <machine/vmparam.h>
123 #include <machine/spr.h>
124 #include <machine/hid.h>
125 #include <machine/psl.h>
126 #include <machine/trap.h>
127 #include <machine/md_var.h>
128 #include <machine/mmuvar.h>
129 #include <machine/sigframe.h>
130 #include <machine/machdep.h>
131 #include <machine/metadata.h>
132 #include <machine/platform.h>
133
134 #include <sys/linker.h>
135 #include <sys/reboot.h>
136
137 #include <contrib/libfdt/libfdt.h>
138 #include <dev/fdt/fdt_common.h>
139 #include <dev/ofw/openfirm.h>
140
141 #ifdef DDB
142 #include <ddb/ddb.h>
143 #endif
144
145 #ifdef DEBUG
146 #define debugf(fmt, args...) printf(fmt, ##args)
147 #else
148 #define debugf(fmt, args...)
149 #endif
150
151 extern unsigned char _etext[];
152 extern unsigned char _edata[];
153 extern unsigned char __bss_start[];
154 extern unsigned char __sbss_start[];
155 extern unsigned char __sbss_end[];
156 extern unsigned char _end[];
157 extern vm_offset_t __endkernel;
158 extern vm_paddr_t kernload;
159
160 /*
161 * Bootinfo is passed to us by legacy loaders. Save the address of the
162 * structure to handle backward compatibility.
163 */
164 uint32_t *bootinfo;
165
166 void print_kernel_section_addr(void);
167 void print_kenv(void);
168 uintptr_t booke_init(u_long, u_long);
169 void ivor_setup(void);
170
171 extern void *interrupt_vector_base;
172 extern void *int_critical_input;
173 extern void *int_machine_check;
174 extern void *int_data_storage;
175 extern void *int_instr_storage;
176 extern void *int_external_input;
177 extern void *int_alignment;
178 extern void *int_fpu;
179 extern void *int_program;
180 extern void *int_syscall;
181 extern void *int_decrementer;
182 extern void *int_fixed_interval_timer;
183 extern void *int_watchdog;
184 extern void *int_data_tlb_error;
185 extern void *int_inst_tlb_error;
186 extern void *int_debug;
187 extern void *int_debug_ed;
188 extern void *int_vec;
189 extern void *int_vecast;
190 #ifdef HWPMC_HOOKS
191 extern void *int_performance_counter;
192 #endif
193
194 #define SET_TRAP(ivor, handler) \
195 KASSERT(((uintptr_t)(&handler) & ~0xffffUL) == \
196 ((uintptr_t)(&interrupt_vector_base) & ~0xffffUL), \
197 ("Handler " #handler " too far from interrupt vector base")); \
198 mtspr(ivor, (uintptr_t)(&handler) & 0xffffUL);
199
200 uintptr_t powerpc_init(vm_offset_t fdt, vm_offset_t, vm_offset_t, void *mdp,
201 uint32_t mdp_cookie);
202 void booke_cpu_init(void);
203
204 void
booke_cpu_init(void)205 booke_cpu_init(void)
206 {
207
208 cpu_features |= PPC_FEATURE_BOOKE;
209
210 psl_kernset = PSL_CE | PSL_ME | PSL_EE;
211 #ifdef __powerpc64__
212 psl_kernset |= PSL_CM;
213 #endif
214 psl_userset = psl_kernset | PSL_PR;
215 #ifdef __powerpc64__
216 psl_userset32 = psl_userset & ~PSL_CM;
217 #endif
218 /*
219 * Zeroed bits in this variable signify that the value of the bit
220 * in its position is allowed to vary between userspace contexts.
221 *
222 * All other bits are required to be identical for every userspace
223 * context. The actual *value* of the bit is determined by
224 * psl_userset and/or psl_userset32, and is not allowed to change.
225 *
226 * Remember to update this set when implementing support for
227 * *conditionally* enabling a processor facility. Failing to do
228 * this will cause swapcontext() in userspace to break when a
229 * process uses a conditionally-enabled facility.
230 *
231 * When *unconditionally* implementing support for a processor
232 * facility, update psl_userset / psl_userset32 instead.
233 *
234 * See the access control check in set_mcontext().
235 */
236 psl_userstatic = ~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1);
237
238 pmap_mmu_install(MMU_TYPE_BOOKE, BUS_PROBE_GENERIC);
239 }
240
241 void
ivor_setup(void)242 ivor_setup(void)
243 {
244
245 mtspr(SPR_IVPR, ((uintptr_t)&interrupt_vector_base) & ~0xffffUL);
246
247 SET_TRAP(SPR_IVOR0, int_critical_input);
248 SET_TRAP(SPR_IVOR1, int_machine_check);
249 SET_TRAP(SPR_IVOR2, int_data_storage);
250 SET_TRAP(SPR_IVOR3, int_instr_storage);
251 SET_TRAP(SPR_IVOR4, int_external_input);
252 SET_TRAP(SPR_IVOR5, int_alignment);
253 SET_TRAP(SPR_IVOR6, int_program);
254 SET_TRAP(SPR_IVOR8, int_syscall);
255 SET_TRAP(SPR_IVOR10, int_decrementer);
256 SET_TRAP(SPR_IVOR11, int_fixed_interval_timer);
257 SET_TRAP(SPR_IVOR12, int_watchdog);
258 SET_TRAP(SPR_IVOR13, int_data_tlb_error);
259 SET_TRAP(SPR_IVOR14, int_inst_tlb_error);
260 SET_TRAP(SPR_IVOR15, int_debug);
261 #ifdef HWPMC_HOOKS
262 SET_TRAP(SPR_IVOR35, int_performance_counter);
263 #endif
264 switch ((mfpvr() >> 16) & 0xffff) {
265 case FSL_E6500:
266 SET_TRAP(SPR_IVOR32, int_vec);
267 SET_TRAP(SPR_IVOR33, int_vecast);
268 /* FALLTHROUGH */
269 case FSL_E500mc:
270 case FSL_E5500:
271 SET_TRAP(SPR_IVOR7, int_fpu);
272 SET_TRAP(SPR_IVOR15, int_debug_ed);
273 break;
274 case FSL_E500v1:
275 case FSL_E500v2:
276 SET_TRAP(SPR_IVOR32, int_vec);
277 break;
278 }
279
280 #ifdef __powerpc64__
281 /* Set 64-bit interrupt mode. */
282 mtspr(SPR_EPCR, mfspr(SPR_EPCR) | EPCR_ICM);
283 #endif
284 }
285
286 static int
booke_check_for_fdt(uint32_t arg1,vm_offset_t * dtbp)287 booke_check_for_fdt(uint32_t arg1, vm_offset_t *dtbp)
288 {
289 void *ptr;
290 int fdt_size;
291
292 if (arg1 % 8 != 0)
293 return (-1);
294
295 ptr = (void *)pmap_early_io_map(arg1, PAGE_SIZE);
296 if (fdt_check_header(ptr) != 0)
297 return (-1);
298
299 /*
300 * Read FDT total size from the header of FDT.
301 * This for sure hits within first page which is
302 * already mapped.
303 */
304 fdt_size = fdt_totalsize((void *)ptr);
305
306 /*
307 * Ok, arg1 points to FDT, so we need to map it in.
308 * First, unmap this page and then map FDT again with full size
309 */
310 pmap_early_io_unmap((vm_offset_t)ptr, PAGE_SIZE);
311 ptr = (void *)pmap_early_io_map(arg1, fdt_size);
312 *dtbp = (vm_offset_t)ptr;
313
314 return (0);
315 }
316
317 uintptr_t
booke_init(u_long arg1,u_long arg2)318 booke_init(u_long arg1, u_long arg2)
319 {
320 uintptr_t ret;
321 void *mdp;
322 vm_offset_t dtbp, end;
323
324 end = (uintptr_t)_end;
325 dtbp = (vm_offset_t)NULL;
326
327 /* Set up TLB initially */
328 bootinfo = NULL;
329 bzero(__sbss_start, __sbss_end - __sbss_start);
330 bzero(__bss_start, _end - __bss_start);
331 tlb1_init();
332
333 /*
334 * Handle the various ways we can get loaded and started:
335 * - FreeBSD's loader passes the pointer to the metadata
336 * in arg1, with arg2 undefined. arg1 has a value that's
337 * relative to the kernel's link address (i.e. larger
338 * than 0xc0000000).
339 * - Juniper's loader passes the metadata pointer in arg2
340 * and sets arg1 to zero. This is to signal that the
341 * loader maps the kernel and starts it at its link
342 * address (unlike the FreeBSD loader).
343 * - U-Boot passes the standard argc and argv parameters
344 * in arg1 and arg2 (resp). arg1 is between 1 and some
345 * relatively small number, such as 64K. arg2 is the
346 * physical address of the argv vector.
347 * - ePAPR loaders pass an FDT blob in r3 (arg1) and the magic hex
348 * string 0x45504150 ('EPAP') in r6 (which has been lost by now).
349 * r4 (arg2) is supposed to be set to zero, but is not always.
350 */
351
352 if (arg1 == 0) /* Juniper loader */
353 mdp = (void *)arg2;
354 else if (booke_check_for_fdt(arg1, &dtbp) == 0) { /* ePAPR */
355 end = roundup(end, 8);
356 memmove((void *)end, (void *)dtbp, fdt_totalsize((void *)dtbp));
357 dtbp = end;
358 end += fdt_totalsize((void *)dtbp);
359 __endkernel = end;
360 mdp = NULL;
361 } else if (arg1 > (uintptr_t)kernload) /* FreeBSD loader */
362 mdp = (void *)arg1;
363 else /* U-Boot */
364 mdp = NULL;
365
366 /* Default to 32 byte cache line size. */
367 switch ((mfpvr()) >> 16) {
368 case FSL_E500mc:
369 case FSL_E5500:
370 case FSL_E6500:
371 cacheline_size = 64;
372 break;
373 }
374
375 /*
376 * Last element is a magic cookie that indicates that the metadata
377 * pointer is meaningful.
378 */
379 ret = powerpc_init(dtbp, 0, 0, mdp, (mdp == NULL) ? 0 : 0xfb5d104d);
380
381 /* Enable caches */
382 booke_enable_l1_cache();
383 booke_enable_l2_cache();
384
385 booke_enable_bpred();
386
387 return (ret);
388 }
389
390 #define RES_GRANULE cacheline_size
391 extern uintptr_t tlb0_miss_locks[];
392
393 /* Initialise a struct pcpu. */
394 void
cpu_pcpu_init(struct pcpu * pcpu,int cpuid,size_t sz)395 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
396 {
397
398 pcpu->pc_booke.tid_next = TID_MIN;
399
400 #ifdef SMP
401 uintptr_t *ptr;
402 int words_per_gran = RES_GRANULE / sizeof(uintptr_t);
403
404 ptr = &tlb0_miss_locks[cpuid * words_per_gran];
405 pcpu->pc_booke.tlb_lock = ptr;
406 *ptr = TLB_UNLOCKED;
407 *(ptr + 1) = 0; /* recurse counter */
408 #endif
409 }
410
411 /* Shutdown the CPU as much as possible. */
412 void
cpu_halt(void)413 cpu_halt(void)
414 {
415
416 mtmsr(mfmsr() & ~(PSL_CE | PSL_EE | PSL_ME | PSL_DE));
417 while (1)
418 ;
419 }
420
421 int
ptrace_single_step(struct thread * td)422 ptrace_single_step(struct thread *td)
423 {
424 struct trapframe *tf;
425
426 tf = td->td_frame;
427 tf->srr1 |= PSL_DE;
428 tf->cpu.booke.dbcr0 |= (DBCR0_IDM | DBCR0_IC);
429 return (0);
430 }
431
432 int
ptrace_clear_single_step(struct thread * td)433 ptrace_clear_single_step(struct thread *td)
434 {
435 struct trapframe *tf;
436
437 tf = td->td_frame;
438 tf->srr1 &= ~PSL_DE;
439 tf->cpu.booke.dbcr0 &= ~(DBCR0_IDM | DBCR0_IC);
440 return (0);
441 }
442
443 void
kdb_cpu_clear_singlestep(void)444 kdb_cpu_clear_singlestep(void)
445 {
446 register_t r;
447
448 r = mfspr(SPR_DBCR0);
449 mtspr(SPR_DBCR0, r & ~DBCR0_IC);
450 kdb_frame->srr1 &= ~PSL_DE;
451 }
452
453 void
kdb_cpu_set_singlestep(void)454 kdb_cpu_set_singlestep(void)
455 {
456 register_t r;
457
458 r = mfspr(SPR_DBCR0);
459 mtspr(SPR_DBCR0, r | DBCR0_IC | DBCR0_IDM);
460 kdb_frame->srr1 |= PSL_DE;
461 }
462