1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * i2c_adap_pxa.c
4 *
5 * I2C adapter for the PXA I2C bus access.
6 *
7 * Copyright (C) 2002 Intrinsyc Software Inc.
8 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
9 *
10 * History:
11 * Apr 2002: Initial version [CS]
12 * Jun 2002: Properly separated algo/adap [FB]
13 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
14 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
15 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
16 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
17 * Feb 2005: Rework slave mode handling [RMK]
18 */
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/errno.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/i2c.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/platform_device.h>
34 #include <linux/platform_data/i2c-pxa.h>
35 #include <linux/property.h>
36 #include <linux/slab.h>
37
38 /* I2C register field definitions */
39 #define IBMR_SDAS (1 << 0)
40 #define IBMR_SCLS (1 << 1)
41
42 #define ICR_START (1 << 0) /* start bit */
43 #define ICR_STOP (1 << 1) /* stop bit */
44 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
45 #define ICR_TB (1 << 3) /* transfer byte bit */
46 #define ICR_MA (1 << 4) /* master abort */
47 #define ICR_SCLE (1 << 5) /* master clock enable */
48 #define ICR_IUE (1 << 6) /* unit enable */
49 #define ICR_GCD (1 << 7) /* general call disable */
50 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
51 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
52 #define ICR_BEIE (1 << 10) /* enable bus error ints */
53 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
54 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
55 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
56 #define ICR_UR (1 << 14) /* unit reset */
57 #define ICR_FM (1 << 15) /* fast mode */
58 #define ICR_HS (1 << 16) /* High Speed mode */
59 #define ICR_A3700_FM (1 << 16) /* fast mode for armada-3700 */
60 #define ICR_A3700_HS (1 << 17) /* high speed mode for armada-3700 */
61 #define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
62
63 #define ISR_RWM (1 << 0) /* read/write mode */
64 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
65 #define ISR_UB (1 << 2) /* unit busy */
66 #define ISR_IBB (1 << 3) /* bus busy */
67 #define ISR_SSD (1 << 4) /* slave stop detected */
68 #define ISR_ALD (1 << 5) /* arbitration loss detected */
69 #define ISR_ITE (1 << 6) /* tx buffer empty */
70 #define ISR_IRF (1 << 7) /* rx buffer full */
71 #define ISR_GCAD (1 << 8) /* general call address detected */
72 #define ISR_SAD (1 << 9) /* slave address detected */
73 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
74 #define ISR_A3700_EBB (1 << 11) /* early bus busy for armada 3700 */
75
76 #define ILCR_SLV_SHIFT 0
77 #define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
78 #define ILCR_FLV_SHIFT 9
79 #define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
80 #define ILCR_HLVL_SHIFT 18
81 #define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
82 #define ILCR_HLVH_SHIFT 27
83 #define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
84
85 #define IWCR_CNT_SHIFT 0
86 #define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
87 #define IWCR_HS_CNT1_SHIFT 5
88 #define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
89 #define IWCR_HS_CNT2_SHIFT 10
90 #define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
91
92 /* need a longer timeout if we're dealing with the fact we may well be
93 * looking at a multi-master environment
94 */
95 #define DEF_TIMEOUT 32
96
97 #define NO_SLAVE (-ENXIO)
98 #define BUS_ERROR (-EREMOTEIO)
99 #define XFER_NAKED (-ECONNREFUSED)
100 #define I2C_RETRY (-2000) /* an error has occurred retry transmit */
101
102 /* ICR initialize bit values
103 *
104 * 15 FM 0 (100 kHz operation)
105 * 14 UR 0 (No unit reset)
106 * 13 SADIE 0 (Disables the unit from interrupting on slave addresses
107 * matching its slave address)
108 * 12 ALDIE 0 (Disables the unit from interrupt when it loses arbitration
109 * in master mode)
110 * 11 SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode)
111 * 10 BEIE 1 (Enable interrupts from detected bus errors, no ACK sent)
112 * 9 IRFIE 1 (Enable interrupts from full buffer received)
113 * 8 ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty)
114 * 7 GCD 1 (Disables i2c unit response to general call messages as a slave)
115 * 6 IUE 0 (Disable unit until we change settings)
116 * 5 SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
117 * 4 MA 0 (Only send stop with the ICR stop bit)
118 * 3 TB 0 (We are not transmitting a byte initially)
119 * 2 ACKNAK 0 (Send an ACK after the unit receives a byte)
120 * 1 STOP 0 (Do not send a STOP)
121 * 0 START 0 (Do not send a START)
122 */
123 #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
124
125 /* I2C status register init values
126 *
127 * 10 BED 1 (Clear bus error detected)
128 * 9 SAD 1 (Clear slave address detected)
129 * 7 IRF 1 (Clear IDBR Receive Full)
130 * 6 ITE 1 (Clear IDBR Transmit Empty)
131 * 5 ALD 1 (Clear Arbitration Loss Detected)
132 * 4 SSD 1 (Clear Slave Stop Detected)
133 */
134 #define I2C_ISR_INIT 0x7FF /* status register init */
135
136 struct pxa_reg_layout {
137 u32 ibmr;
138 u32 idbr;
139 u32 icr;
140 u32 isr;
141 u32 isar;
142 u32 ilcr;
143 u32 iwcr;
144 u32 fm;
145 u32 hs;
146 };
147
148 enum pxa_i2c_types {
149 REGS_PXA2XX,
150 REGS_PXA3XX,
151 REGS_CE4100,
152 REGS_PXA910,
153 REGS_A3700,
154 };
155
156 /* I2C register layout definitions */
157 static struct pxa_reg_layout pxa_reg_layout[] = {
158 [REGS_PXA2XX] = {
159 .ibmr = 0x00,
160 .idbr = 0x08,
161 .icr = 0x10,
162 .isr = 0x18,
163 .isar = 0x20,
164 .fm = ICR_FM,
165 .hs = ICR_HS,
166 },
167 [REGS_PXA3XX] = {
168 .ibmr = 0x00,
169 .idbr = 0x04,
170 .icr = 0x08,
171 .isr = 0x0c,
172 .isar = 0x10,
173 .fm = ICR_FM,
174 .hs = ICR_HS,
175 },
176 [REGS_CE4100] = {
177 .ibmr = 0x14,
178 .idbr = 0x0c,
179 .icr = 0x00,
180 .isr = 0x04,
181 /* no isar register */
182 .fm = ICR_FM,
183 .hs = ICR_HS,
184 },
185 [REGS_PXA910] = {
186 .ibmr = 0x00,
187 .idbr = 0x08,
188 .icr = 0x10,
189 .isr = 0x18,
190 .isar = 0x20,
191 .ilcr = 0x28,
192 .iwcr = 0x30,
193 .fm = ICR_FM,
194 .hs = ICR_HS,
195 },
196 [REGS_A3700] = {
197 .ibmr = 0x00,
198 .idbr = 0x04,
199 .icr = 0x08,
200 .isr = 0x0c,
201 .isar = 0x10,
202 .fm = ICR_A3700_FM,
203 .hs = ICR_A3700_HS,
204 },
205 };
206
207 static const struct of_device_id i2c_pxa_dt_ids[] = {
208 { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
209 { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
210 { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
211 { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
212 {}
213 };
214 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
215
216 static const struct platform_device_id i2c_pxa_id_table[] = {
217 { "pxa2xx-i2c", REGS_PXA2XX },
218 { "pxa3xx-pwri2c", REGS_PXA3XX },
219 { "ce4100-i2c", REGS_CE4100 },
220 { "pxa910-i2c", REGS_PXA910 },
221 { "armada-3700-i2c", REGS_A3700 },
222 { }
223 };
224 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
225
226 struct pxa_i2c {
227 spinlock_t lock;
228 wait_queue_head_t wait;
229 struct i2c_msg *msg;
230 unsigned int msg_num;
231 unsigned int msg_idx;
232 unsigned int msg_ptr;
233 unsigned int slave_addr;
234 unsigned int req_slave_addr;
235
236 struct i2c_adapter adap;
237 struct clk *clk;
238 #ifdef CONFIG_I2C_PXA_SLAVE
239 struct i2c_client *slave;
240 #endif
241
242 unsigned int irqlogidx;
243 u32 isrlog[32];
244 u32 icrlog[32];
245
246 void __iomem *reg_base;
247 void __iomem *reg_ibmr;
248 void __iomem *reg_idbr;
249 void __iomem *reg_icr;
250 void __iomem *reg_isr;
251 void __iomem *reg_isar;
252 void __iomem *reg_ilcr;
253 void __iomem *reg_iwcr;
254
255 unsigned long iobase;
256 unsigned long iosize;
257
258 int irq;
259 unsigned int use_pio :1;
260 unsigned int fast_mode :1;
261 unsigned int high_mode:1;
262 unsigned char master_code;
263 unsigned long rate;
264 bool highmode_enter;
265 u32 fm_mask;
266 u32 hs_mask;
267 u32 busy_mask;
268
269 struct i2c_bus_recovery_info recovery;
270 struct pinctrl *pinctrl;
271 struct pinctrl_state *pinctrl_default;
272 struct pinctrl_state *pinctrl_recovery;
273 bool reset_before_xfer;
274 };
275
276 #define _IBMR(i2c) ((i2c)->reg_ibmr)
277 #define _IDBR(i2c) ((i2c)->reg_idbr)
278 #define _ICR(i2c) ((i2c)->reg_icr)
279 #define _ISR(i2c) ((i2c)->reg_isr)
280 #define _ISAR(i2c) ((i2c)->reg_isar)
281 #define _ILCR(i2c) ((i2c)->reg_ilcr)
282 #define _IWCR(i2c) ((i2c)->reg_iwcr)
283
284 /*
285 * I2C Slave mode address
286 */
287 #define I2C_PXA_SLAVE_ADDR 0x1
288
289 #ifdef DEBUG
290
291 struct bits {
292 u32 mask;
293 const char *set;
294 const char *unset;
295 };
296 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
297
298 static inline void
decode_bits(const char * prefix,const struct bits * bits,int num,u32 val)299 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
300 {
301 printk("%s %08x:", prefix, val);
302 while (num--) {
303 const char *str = val & bits->mask ? bits->set : bits->unset;
304 if (str)
305 pr_cont(" %s", str);
306 bits++;
307 }
308 pr_cont("\n");
309 }
310
311 static const struct bits isr_bits[] = {
312 PXA_BIT(ISR_RWM, "RX", "TX"),
313 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
314 PXA_BIT(ISR_UB, "Bsy", "Rdy"),
315 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
316 PXA_BIT(ISR_SSD, "SlaveStop", NULL),
317 PXA_BIT(ISR_ALD, "ALD", NULL),
318 PXA_BIT(ISR_ITE, "TxEmpty", NULL),
319 PXA_BIT(ISR_IRF, "RxFull", NULL),
320 PXA_BIT(ISR_GCAD, "GenCall", NULL),
321 PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
322 PXA_BIT(ISR_BED, "BusErr", NULL),
323 };
324
decode_ISR(unsigned int val)325 static void decode_ISR(unsigned int val)
326 {
327 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
328 }
329
330 #ifdef CONFIG_I2C_PXA_SLAVE
331 static const struct bits icr_bits[] = {
332 PXA_BIT(ICR_START, "START", NULL),
333 PXA_BIT(ICR_STOP, "STOP", NULL),
334 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
335 PXA_BIT(ICR_TB, "TB", NULL),
336 PXA_BIT(ICR_MA, "MA", NULL),
337 PXA_BIT(ICR_SCLE, "SCLE", "scle"),
338 PXA_BIT(ICR_IUE, "IUE", "iue"),
339 PXA_BIT(ICR_GCD, "GCD", NULL),
340 PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
341 PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
342 PXA_BIT(ICR_BEIE, "BEIE", NULL),
343 PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
344 PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
345 PXA_BIT(ICR_SADIE, "SADIE", NULL),
346 PXA_BIT(ICR_UR, "UR", "ur"),
347 };
348
decode_ICR(unsigned int val)349 static void decode_ICR(unsigned int val)
350 {
351 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
352 }
353 #endif
354
355 static unsigned int i2c_debug = DEBUG;
356
i2c_pxa_show_state(struct pxa_i2c * i2c,int lno,const char * fname)357 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
358 {
359 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
360 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
361 }
362
363 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
364
i2c_pxa_scream_blue_murder(struct pxa_i2c * i2c,const char * why)365 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
366 {
367 unsigned int i;
368 struct device *dev = &i2c->adap.dev;
369
370 dev_err(dev, "slave_0x%x error: %s\n",
371 i2c->req_slave_addr >> 1, why);
372 dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
373 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
374 dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
375 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
376 readl(_ISR(i2c)));
377 dev_err(dev, "log:");
378 for (i = 0; i < i2c->irqlogidx; i++)
379 pr_cont(" [%03x:%05x]", i2c->isrlog[i], i2c->icrlog[i]);
380 pr_cont("\n");
381 }
382
383 #else /* ifdef DEBUG */
384
385 #define i2c_debug 0
386
387 #define show_state(i2c) do { } while (0)
388 #define decode_ISR(val) do { } while (0)
389 #define decode_ICR(val) do { } while (0)
390 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
391
392 #endif /* ifdef DEBUG / else */
393
394 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
395
i2c_pxa_is_slavemode(struct pxa_i2c * i2c)396 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
397 {
398 return !(readl(_ICR(i2c)) & ICR_SCLE);
399 }
400
i2c_pxa_abort(struct pxa_i2c * i2c)401 static void i2c_pxa_abort(struct pxa_i2c *i2c)
402 {
403 int i = 250;
404
405 if (i2c_pxa_is_slavemode(i2c)) {
406 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
407 return;
408 }
409
410 while ((i > 0) && (readl(_IBMR(i2c)) & IBMR_SDAS) == 0) {
411 unsigned long icr = readl(_ICR(i2c));
412
413 icr &= ~ICR_START;
414 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
415
416 writel(icr, _ICR(i2c));
417
418 show_state(i2c);
419
420 mdelay(1);
421 i --;
422 }
423
424 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
425 _ICR(i2c));
426 }
427
i2c_pxa_wait_bus_not_busy(struct pxa_i2c * i2c)428 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
429 {
430 int timeout = DEF_TIMEOUT;
431 u32 isr;
432
433 while (1) {
434 isr = readl(_ISR(i2c));
435 if (!(isr & i2c->busy_mask))
436 return 0;
437
438 if (isr & ISR_SAD)
439 timeout += 4;
440
441 if (!timeout--)
442 break;
443
444 msleep(2);
445 show_state(i2c);
446 }
447
448 show_state(i2c);
449
450 return I2C_RETRY;
451 }
452
i2c_pxa_wait_master(struct pxa_i2c * i2c)453 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
454 {
455 unsigned long timeout = jiffies + HZ*4;
456
457 while (time_before(jiffies, timeout)) {
458 if (i2c_debug > 1)
459 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
460 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
461
462 if (readl(_ISR(i2c)) & ISR_SAD) {
463 if (i2c_debug > 0)
464 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
465 goto out;
466 }
467
468 /* wait for unit and bus being not busy, and we also do a
469 * quick check of the i2c lines themselves to ensure they've
470 * gone high...
471 */
472 if ((readl(_ISR(i2c)) & i2c->busy_mask) == 0 &&
473 readl(_IBMR(i2c)) == (IBMR_SCLS | IBMR_SDAS)) {
474 if (i2c_debug > 0)
475 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
476 return 1;
477 }
478
479 msleep(1);
480 }
481
482 if (i2c_debug > 0)
483 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
484 out:
485 return 0;
486 }
487
i2c_pxa_set_master(struct pxa_i2c * i2c)488 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
489 {
490 if (i2c_debug)
491 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
492
493 if ((readl(_ISR(i2c)) & i2c->busy_mask) != 0) {
494 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
495 if (!i2c_pxa_wait_master(i2c)) {
496 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
497 return I2C_RETRY;
498 }
499 }
500
501 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
502 return 0;
503 }
504
505 #ifdef CONFIG_I2C_PXA_SLAVE
i2c_pxa_wait_slave(struct pxa_i2c * i2c)506 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
507 {
508 unsigned long timeout = jiffies + HZ*1;
509
510 /* wait for stop */
511
512 show_state(i2c);
513
514 while (time_before(jiffies, timeout)) {
515 if (i2c_debug > 1)
516 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
517 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
518
519 if ((readl(_ISR(i2c)) & i2c->busy_mask) == 0 ||
520 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
521 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
522 if (i2c_debug > 1)
523 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
524 return 1;
525 }
526
527 msleep(1);
528 }
529
530 if (i2c_debug > 0)
531 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
532 return 0;
533 }
534
535 /*
536 * clear the hold on the bus, and take of anything else
537 * that has been configured
538 */
i2c_pxa_set_slave(struct pxa_i2c * i2c,int errcode)539 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
540 {
541 show_state(i2c);
542
543 if (errcode < 0) {
544 udelay(100); /* simple delay */
545 } else {
546 /* we need to wait for the stop condition to end */
547
548 /* if we where in stop, then clear... */
549 if (readl(_ICR(i2c)) & ICR_STOP) {
550 udelay(100);
551 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
552 }
553
554 if (!i2c_pxa_wait_slave(i2c)) {
555 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
556 __func__);
557 return;
558 }
559 }
560
561 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
562 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
563
564 if (i2c_debug) {
565 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
566 decode_ICR(readl(_ICR(i2c)));
567 }
568 }
569 #else
570 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
571 #endif
572
i2c_pxa_do_reset(struct pxa_i2c * i2c)573 static void i2c_pxa_do_reset(struct pxa_i2c *i2c)
574 {
575 /* reset according to 9.8 */
576 writel(ICR_UR, _ICR(i2c));
577 writel(I2C_ISR_INIT, _ISR(i2c));
578 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
579
580 if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
581 writel(i2c->slave_addr, _ISAR(i2c));
582
583 /* set control register values */
584 writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
585 writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
586
587 #ifdef CONFIG_I2C_PXA_SLAVE
588 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
589 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
590 #endif
591
592 i2c_pxa_set_slave(i2c, 0);
593 }
594
i2c_pxa_enable(struct pxa_i2c * i2c)595 static void i2c_pxa_enable(struct pxa_i2c *i2c)
596 {
597 /* enable unit */
598 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
599 udelay(100);
600 }
601
i2c_pxa_reset(struct pxa_i2c * i2c)602 static void i2c_pxa_reset(struct pxa_i2c *i2c)
603 {
604 pr_debug("Resetting I2C Controller Unit\n");
605
606 /* abort any transfer currently under way */
607 i2c_pxa_abort(i2c);
608 i2c_pxa_do_reset(i2c);
609 i2c_pxa_enable(i2c);
610 }
611
612
613 #ifdef CONFIG_I2C_PXA_SLAVE
614 /*
615 * PXA I2C Slave mode
616 */
617
i2c_pxa_slave_txempty(struct pxa_i2c * i2c,u32 isr)618 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
619 {
620 if (isr & ISR_BED) {
621 /* what should we do here? */
622 } else {
623 u8 byte = 0;
624
625 if (i2c->slave != NULL)
626 i2c_slave_event(i2c->slave, I2C_SLAVE_READ_PROCESSED,
627 &byte);
628
629 writel(byte, _IDBR(i2c));
630 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
631 }
632 }
633
i2c_pxa_slave_rxfull(struct pxa_i2c * i2c,u32 isr)634 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
635 {
636 u8 byte = readl(_IDBR(i2c));
637
638 if (i2c->slave != NULL)
639 i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_RECEIVED, &byte);
640
641 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
642 }
643
i2c_pxa_slave_start(struct pxa_i2c * i2c,u32 isr)644 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
645 {
646 int timeout;
647
648 if (i2c_debug > 0)
649 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
650 (isr & ISR_RWM) ? 'r' : 't');
651
652 if (i2c->slave != NULL) {
653 if (isr & ISR_RWM) {
654 u8 byte = 0;
655
656 i2c_slave_event(i2c->slave, I2C_SLAVE_READ_REQUESTED,
657 &byte);
658 writel(byte, _IDBR(i2c));
659 } else {
660 i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_REQUESTED,
661 NULL);
662 }
663 }
664
665 /*
666 * slave could interrupt in the middle of us generating a
667 * start condition... if this happens, we'd better back off
668 * and stop holding the poor thing up
669 */
670 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
671 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
672
673 timeout = 0x10000;
674
675 while (1) {
676 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
677 break;
678
679 timeout--;
680
681 if (timeout <= 0) {
682 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
683 break;
684 }
685 }
686
687 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
688 }
689
i2c_pxa_slave_stop(struct pxa_i2c * i2c)690 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
691 {
692 if (i2c_debug > 2)
693 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
694
695 if (i2c->slave != NULL)
696 i2c_slave_event(i2c->slave, I2C_SLAVE_STOP, NULL);
697
698 if (i2c_debug > 2)
699 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
700
701 /*
702 * If we have a master-mode message waiting,
703 * kick it off now that the slave has completed.
704 */
705 if (i2c->msg)
706 i2c_pxa_master_complete(i2c, I2C_RETRY);
707 }
708
i2c_pxa_slave_reg(struct i2c_client * slave)709 static int i2c_pxa_slave_reg(struct i2c_client *slave)
710 {
711 struct pxa_i2c *i2c = slave->adapter->algo_data;
712
713 if (i2c->slave)
714 return -EBUSY;
715
716 if (!i2c->reg_isar)
717 return -EAFNOSUPPORT;
718
719 i2c->slave = slave;
720 i2c->slave_addr = slave->addr;
721
722 writel(i2c->slave_addr, _ISAR(i2c));
723
724 return 0;
725 }
726
i2c_pxa_slave_unreg(struct i2c_client * slave)727 static int i2c_pxa_slave_unreg(struct i2c_client *slave)
728 {
729 struct pxa_i2c *i2c = slave->adapter->algo_data;
730
731 WARN_ON(!i2c->slave);
732
733 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
734 writel(i2c->slave_addr, _ISAR(i2c));
735
736 i2c->slave = NULL;
737
738 return 0;
739 }
740 #else
i2c_pxa_slave_txempty(struct pxa_i2c * i2c,u32 isr)741 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
742 {
743 if (isr & ISR_BED) {
744 /* what should we do here? */
745 } else {
746 writel(0, _IDBR(i2c));
747 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
748 }
749 }
750
i2c_pxa_slave_rxfull(struct pxa_i2c * i2c,u32 isr)751 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
752 {
753 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
754 }
755
i2c_pxa_slave_start(struct pxa_i2c * i2c,u32 isr)756 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
757 {
758 int timeout;
759
760 /*
761 * slave could interrupt in the middle of us generating a
762 * start condition... if this happens, we'd better back off
763 * and stop holding the poor thing up
764 */
765 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
766 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
767
768 timeout = 0x10000;
769
770 while (1) {
771 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
772 break;
773
774 timeout--;
775
776 if (timeout <= 0) {
777 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
778 break;
779 }
780 }
781
782 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
783 }
784
i2c_pxa_slave_stop(struct pxa_i2c * i2c)785 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
786 {
787 if (i2c->msg)
788 i2c_pxa_master_complete(i2c, I2C_RETRY);
789 }
790 #endif
791
792 /*
793 * PXA I2C Master mode
794 */
795
i2c_pxa_start_message(struct pxa_i2c * i2c)796 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
797 {
798 u32 icr;
799
800 /*
801 * Step 1: target slave address into IDBR
802 */
803 i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
804 writel(i2c->req_slave_addr, _IDBR(i2c));
805
806 /*
807 * Step 2: initiate the write.
808 */
809 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
810 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
811 }
812
i2c_pxa_stop_message(struct pxa_i2c * i2c)813 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
814 {
815 u32 icr;
816
817 /* Clear the START, STOP, ACK, TB and MA flags */
818 icr = readl(_ICR(i2c));
819 icr &= ~(ICR_START | ICR_STOP | ICR_ACKNAK | ICR_TB | ICR_MA);
820 writel(icr, _ICR(i2c));
821 }
822
823 /*
824 * PXA I2C send master code
825 * 1. Load master code to IDBR and send it.
826 * Note for HS mode, set ICR [GPIOEN].
827 * 2. Wait until win arbitration.
828 */
i2c_pxa_send_mastercode(struct pxa_i2c * i2c)829 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
830 {
831 u32 icr;
832 long time_left;
833
834 spin_lock_irq(&i2c->lock);
835 i2c->highmode_enter = true;
836 writel(i2c->master_code, _IDBR(i2c));
837
838 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
839 icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
840 writel(icr, _ICR(i2c));
841
842 spin_unlock_irq(&i2c->lock);
843 time_left = wait_event_timeout(i2c->wait,
844 i2c->highmode_enter == false, HZ * 1);
845
846 i2c->highmode_enter = false;
847
848 return (time_left == 0) ? I2C_RETRY : 0;
849 }
850
851 /*
852 * i2c_pxa_master_complete - complete the message and wake up.
853 */
i2c_pxa_master_complete(struct pxa_i2c * i2c,int ret)854 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
855 {
856 i2c->msg_ptr = 0;
857 i2c->msg = NULL;
858 i2c->msg_idx ++;
859 i2c->msg_num = 0;
860 if (ret)
861 i2c->msg_idx = ret;
862 if (!i2c->use_pio)
863 wake_up(&i2c->wait);
864 }
865
i2c_pxa_irq_txempty(struct pxa_i2c * i2c,u32 isr)866 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
867 {
868 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
869
870 again:
871 /*
872 * If ISR_ALD is set, we lost arbitration.
873 */
874 if (isr & ISR_ALD) {
875 /*
876 * Do we need to do anything here? The PXA docs
877 * are vague about what happens.
878 */
879 i2c_pxa_scream_blue_murder(i2c, "ALD set");
880
881 /*
882 * We ignore this error. We seem to see spurious ALDs
883 * for seemingly no reason. If we handle them as I think
884 * they should, we end up causing an I2C error, which
885 * is painful for some systems.
886 */
887 return; /* ignore */
888 }
889
890 if ((isr & ISR_BED) &&
891 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
892 (isr & ISR_ACKNAK)))) {
893 int ret = BUS_ERROR;
894
895 /*
896 * I2C bus error - either the device NAK'd us, or
897 * something more serious happened. If we were NAK'd
898 * on the initial address phase, we can retry.
899 */
900 if (isr & ISR_ACKNAK) {
901 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
902 ret = NO_SLAVE;
903 else
904 ret = XFER_NAKED;
905 }
906 i2c_pxa_master_complete(i2c, ret);
907 } else if (isr & ISR_RWM) {
908 /*
909 * Read mode. We have just sent the address byte, and
910 * now we must initiate the transfer.
911 */
912 if (i2c->msg_ptr == i2c->msg->len - 1 &&
913 i2c->msg_idx == i2c->msg_num - 1)
914 icr |= ICR_STOP | ICR_ACKNAK;
915
916 icr |= ICR_ALDIE | ICR_TB;
917 } else if (i2c->msg_ptr < i2c->msg->len) {
918 /*
919 * Write mode. Write the next data byte.
920 */
921 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
922
923 icr |= ICR_ALDIE | ICR_TB;
924
925 /*
926 * If this is the last byte of the last message or last byte
927 * of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
928 */
929 if ((i2c->msg_ptr == i2c->msg->len) &&
930 ((i2c->msg->flags & I2C_M_STOP) ||
931 (i2c->msg_idx == i2c->msg_num - 1)))
932 icr |= ICR_STOP;
933
934 } else if (i2c->msg_idx < i2c->msg_num - 1) {
935 /*
936 * Next segment of the message.
937 */
938 i2c->msg_ptr = 0;
939 i2c->msg_idx ++;
940 i2c->msg++;
941
942 /*
943 * If we aren't doing a repeated start and address,
944 * go back and try to send the next byte. Note that
945 * we do not support switching the R/W direction here.
946 */
947 if (i2c->msg->flags & I2C_M_NOSTART)
948 goto again;
949
950 /*
951 * Write the next address.
952 */
953 i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
954 writel(i2c->req_slave_addr, _IDBR(i2c));
955
956 /*
957 * And trigger a repeated start, and send the byte.
958 */
959 icr &= ~ICR_ALDIE;
960 icr |= ICR_START | ICR_TB;
961 } else {
962 if (i2c->msg->len == 0)
963 icr |= ICR_MA;
964 i2c_pxa_master_complete(i2c, 0);
965 }
966
967 i2c->icrlog[i2c->irqlogidx-1] = icr;
968
969 writel(icr, _ICR(i2c));
970 show_state(i2c);
971 }
972
i2c_pxa_irq_rxfull(struct pxa_i2c * i2c,u32 isr)973 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
974 {
975 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
976
977 /*
978 * Read the byte.
979 */
980 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
981
982 if (i2c->msg_ptr < i2c->msg->len) {
983 /*
984 * If this is the last byte of the last
985 * message, send a STOP.
986 */
987 if (i2c->msg_ptr == i2c->msg->len - 1)
988 icr |= ICR_STOP | ICR_ACKNAK;
989
990 icr |= ICR_ALDIE | ICR_TB;
991 } else {
992 i2c_pxa_master_complete(i2c, 0);
993 }
994
995 i2c->icrlog[i2c->irqlogidx-1] = icr;
996
997 writel(icr, _ICR(i2c));
998 }
999
1000 #define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
1001 ISR_SAD | ISR_BED)
i2c_pxa_handler(int this_irq,void * dev_id)1002 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
1003 {
1004 struct pxa_i2c *i2c = dev_id;
1005 u32 isr = readl(_ISR(i2c));
1006
1007 if (!(isr & VALID_INT_SOURCE))
1008 return IRQ_NONE;
1009
1010 if (i2c_debug > 2 && 0) {
1011 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1012 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1013 decode_ISR(isr);
1014 }
1015
1016 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1017 i2c->isrlog[i2c->irqlogidx++] = isr;
1018
1019 show_state(i2c);
1020
1021 /*
1022 * Always clear all pending IRQs.
1023 */
1024 writel(isr & VALID_INT_SOURCE, _ISR(i2c));
1025
1026 if (isr & ISR_SAD)
1027 i2c_pxa_slave_start(i2c, isr);
1028 if (isr & ISR_SSD)
1029 i2c_pxa_slave_stop(i2c);
1030
1031 if (i2c_pxa_is_slavemode(i2c)) {
1032 if (isr & ISR_ITE)
1033 i2c_pxa_slave_txempty(i2c, isr);
1034 if (isr & ISR_IRF)
1035 i2c_pxa_slave_rxfull(i2c, isr);
1036 } else if (i2c->msg && (!i2c->highmode_enter)) {
1037 if (isr & ISR_ITE)
1038 i2c_pxa_irq_txempty(i2c, isr);
1039 if (isr & ISR_IRF)
1040 i2c_pxa_irq_rxfull(i2c, isr);
1041 } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1042 i2c->highmode_enter = false;
1043 wake_up(&i2c->wait);
1044 } else {
1045 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1046 }
1047
1048 return IRQ_HANDLED;
1049 }
1050
1051 /*
1052 * We are protected by the adapter bus mutex.
1053 */
i2c_pxa_do_xfer(struct pxa_i2c * i2c,struct i2c_msg * msg,int num)1054 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
1055 {
1056 long time_left;
1057 int ret;
1058
1059 /*
1060 * Wait for the bus to become free.
1061 */
1062 ret = i2c_pxa_wait_bus_not_busy(i2c);
1063 if (ret) {
1064 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
1065 i2c_recover_bus(&i2c->adap);
1066 goto out;
1067 }
1068
1069 /*
1070 * Set master mode.
1071 */
1072 ret = i2c_pxa_set_master(i2c);
1073 if (ret) {
1074 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
1075 goto out;
1076 }
1077
1078 if (i2c->high_mode) {
1079 ret = i2c_pxa_send_mastercode(i2c);
1080 if (ret) {
1081 dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
1082 goto out;
1083 }
1084 }
1085
1086 spin_lock_irq(&i2c->lock);
1087
1088 i2c->msg = msg;
1089 i2c->msg_num = num;
1090 i2c->msg_idx = 0;
1091 i2c->msg_ptr = 0;
1092 i2c->irqlogidx = 0;
1093
1094 i2c_pxa_start_message(i2c);
1095
1096 spin_unlock_irq(&i2c->lock);
1097
1098 /*
1099 * The rest of the processing occurs in the interrupt handler.
1100 */
1101 time_left = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
1102 i2c_pxa_stop_message(i2c);
1103
1104 /*
1105 * We place the return code in i2c->msg_idx.
1106 */
1107 ret = i2c->msg_idx;
1108
1109 if (!time_left && i2c->msg_num) {
1110 i2c_pxa_scream_blue_murder(i2c, "timeout with active message");
1111 i2c_recover_bus(&i2c->adap);
1112 ret = I2C_RETRY;
1113 }
1114
1115 out:
1116 return ret;
1117 }
1118
i2c_pxa_internal_xfer(struct pxa_i2c * i2c,struct i2c_msg * msgs,int num,int (* xfer)(struct pxa_i2c *,struct i2c_msg *,int num))1119 static int i2c_pxa_internal_xfer(struct pxa_i2c *i2c,
1120 struct i2c_msg *msgs, int num,
1121 int (*xfer)(struct pxa_i2c *,
1122 struct i2c_msg *, int num))
1123 {
1124 int ret, i;
1125
1126 for (i = 0; ; ) {
1127 ret = xfer(i2c, msgs, num);
1128 if (ret != I2C_RETRY && ret != NO_SLAVE)
1129 goto out;
1130 if (++i >= i2c->adap.retries)
1131 break;
1132
1133 if (i2c_debug)
1134 dev_dbg(&i2c->adap.dev, "Retrying transmission\n");
1135 udelay(100);
1136 }
1137 if (ret != NO_SLAVE)
1138 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1139 ret = -EREMOTEIO;
1140 out:
1141 i2c_pxa_set_slave(i2c, ret);
1142 return ret;
1143 }
1144
i2c_pxa_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1145 static int i2c_pxa_xfer(struct i2c_adapter *adap,
1146 struct i2c_msg msgs[], int num)
1147 {
1148 struct pxa_i2c *i2c = adap->algo_data;
1149
1150 if (i2c->reset_before_xfer) {
1151 i2c_pxa_reset(i2c);
1152 i2c->reset_before_xfer = false;
1153 }
1154
1155 return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_xfer);
1156 }
1157
i2c_pxa_functionality(struct i2c_adapter * adap)1158 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1159 {
1160 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1161 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1162 }
1163
1164 static const struct i2c_algorithm i2c_pxa_algorithm = {
1165 .xfer = i2c_pxa_xfer,
1166 .functionality = i2c_pxa_functionality,
1167 #ifdef CONFIG_I2C_PXA_SLAVE
1168 .reg_slave = i2c_pxa_slave_reg,
1169 .unreg_slave = i2c_pxa_slave_unreg,
1170 #endif
1171 };
1172
1173 /* Non-interrupt mode support */
i2c_pxa_pio_set_master(struct pxa_i2c * i2c)1174 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
1175 {
1176 /* make timeout the same as for interrupt based functions */
1177 long timeout = 2 * DEF_TIMEOUT;
1178
1179 /*
1180 * Wait for the bus to become free.
1181 */
1182 while (timeout-- && readl(_ISR(i2c)) & i2c->busy_mask)
1183 udelay(1000);
1184
1185 if (timeout < 0) {
1186 show_state(i2c);
1187 dev_err(&i2c->adap.dev,
1188 "i2c_pxa: timeout waiting for bus free (set_master)\n");
1189 return I2C_RETRY;
1190 }
1191
1192 /*
1193 * Set master mode.
1194 */
1195 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
1196
1197 return 0;
1198 }
1199
i2c_pxa_do_pio_xfer(struct pxa_i2c * i2c,struct i2c_msg * msg,int num)1200 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
1201 struct i2c_msg *msg, int num)
1202 {
1203 unsigned long timeout = 500000; /* 5 seconds */
1204 int ret = 0;
1205
1206 ret = i2c_pxa_pio_set_master(i2c);
1207 if (ret)
1208 goto out;
1209
1210 i2c->msg = msg;
1211 i2c->msg_num = num;
1212 i2c->msg_idx = 0;
1213 i2c->msg_ptr = 0;
1214 i2c->irqlogidx = 0;
1215
1216 i2c_pxa_start_message(i2c);
1217
1218 while (i2c->msg_num > 0 && --timeout) {
1219 i2c_pxa_handler(0, i2c);
1220 udelay(10);
1221 }
1222
1223 i2c_pxa_stop_message(i2c);
1224
1225 /*
1226 * We place the return code in i2c->msg_idx.
1227 */
1228 ret = i2c->msg_idx;
1229
1230 out:
1231 if (timeout == 0) {
1232 i2c_pxa_scream_blue_murder(i2c, "timeout (do_pio_xfer)");
1233 ret = I2C_RETRY;
1234 }
1235
1236 return ret;
1237 }
1238
i2c_pxa_pio_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1239 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
1240 struct i2c_msg msgs[], int num)
1241 {
1242 struct pxa_i2c *i2c = adap->algo_data;
1243
1244 /* If the I2C controller is disabled we need to reset it
1245 (probably due to a suspend/resume destroying state). We do
1246 this here as we can then avoid worrying about resuming the
1247 controller before its users. */
1248 if (!(readl(_ICR(i2c)) & ICR_IUE))
1249 i2c_pxa_reset(i2c);
1250
1251 return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_pio_xfer);
1252 }
1253
1254 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1255 .xfer = i2c_pxa_pio_xfer,
1256 .functionality = i2c_pxa_functionality,
1257 #ifdef CONFIG_I2C_PXA_SLAVE
1258 .reg_slave = i2c_pxa_slave_reg,
1259 .unreg_slave = i2c_pxa_slave_unreg,
1260 #endif
1261 };
1262
i2c_pxa_probe_dt(struct platform_device * pdev,struct pxa_i2c * i2c,enum pxa_i2c_types * i2c_types)1263 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1264 enum pxa_i2c_types *i2c_types)
1265 {
1266 struct device_node *np = pdev->dev.of_node;
1267
1268 if (!pdev->dev.of_node)
1269 return 1;
1270
1271 /* For device tree we always use the dynamic or alias-assigned ID */
1272 i2c->adap.nr = -1;
1273
1274 i2c->use_pio = of_property_read_bool(np, "mrvl,i2c-polling");
1275 i2c->fast_mode = of_property_read_bool(np, "mrvl,i2c-fast-mode");
1276
1277 *i2c_types = (kernel_ulong_t)device_get_match_data(&pdev->dev);
1278
1279 return 0;
1280 }
1281
i2c_pxa_probe_pdata(struct platform_device * pdev,struct pxa_i2c * i2c,enum pxa_i2c_types * i2c_types)1282 static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1283 struct pxa_i2c *i2c,
1284 enum pxa_i2c_types *i2c_types)
1285 {
1286 struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev);
1287 const struct platform_device_id *id = platform_get_device_id(pdev);
1288
1289 *i2c_types = id->driver_data;
1290 if (plat) {
1291 i2c->use_pio = plat->use_pio;
1292 i2c->fast_mode = plat->fast_mode;
1293 i2c->high_mode = plat->high_mode;
1294 i2c->master_code = plat->master_code;
1295 if (!i2c->master_code)
1296 i2c->master_code = 0xe;
1297 i2c->rate = plat->rate;
1298 }
1299 return 0;
1300 }
1301
i2c_pxa_prepare_recovery(struct i2c_adapter * adap)1302 static void i2c_pxa_prepare_recovery(struct i2c_adapter *adap)
1303 {
1304 struct pxa_i2c *i2c = adap->algo_data;
1305 u32 ibmr = readl(_IBMR(i2c));
1306
1307 /*
1308 * Program the GPIOs to reflect the current I2C bus state while
1309 * we transition to recovery; this avoids glitching the bus.
1310 */
1311 gpiod_set_value(i2c->recovery.scl_gpiod, ibmr & IBMR_SCLS);
1312 gpiod_set_value(i2c->recovery.sda_gpiod, ibmr & IBMR_SDAS);
1313
1314 WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery));
1315 }
1316
i2c_pxa_unprepare_recovery(struct i2c_adapter * adap)1317 static void i2c_pxa_unprepare_recovery(struct i2c_adapter *adap)
1318 {
1319 struct pxa_i2c *i2c = adap->algo_data;
1320 u32 isr;
1321
1322 /*
1323 * The bus should now be free. Clear up the I2C controller before
1324 * handing control of the bus back to avoid the bus changing state.
1325 */
1326 isr = readl(_ISR(i2c));
1327 if (isr & i2c->busy_mask) {
1328 dev_dbg(&i2c->adap.dev,
1329 "recovery: resetting controller, ISR=0x%08x\n", isr);
1330 i2c_pxa_do_reset(i2c);
1331 }
1332
1333 WARN_ON(pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default));
1334
1335 dev_dbg(&i2c->adap.dev, "recovery: IBMR 0x%08x ISR 0x%08x\n",
1336 readl(_IBMR(i2c)), readl(_ISR(i2c)));
1337
1338 i2c_pxa_enable(i2c);
1339 }
1340
i2c_pxa_init_recovery(struct pxa_i2c * i2c)1341 static int i2c_pxa_init_recovery(struct pxa_i2c *i2c)
1342 {
1343 struct i2c_bus_recovery_info *bri = &i2c->recovery;
1344 struct device *dev = i2c->adap.dev.parent;
1345
1346 /*
1347 * When slave mode is enabled, we are not the only master on the bus.
1348 * Bus recovery can only be performed when we are the master, which
1349 * we can't be certain of. Therefore, when slave mode is enabled, do
1350 * not configure bus recovery.
1351 */
1352 if (IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
1353 return 0;
1354
1355 i2c->pinctrl = devm_pinctrl_get(dev);
1356 if (PTR_ERR(i2c->pinctrl) == -ENODEV)
1357 i2c->pinctrl = NULL;
1358 if (IS_ERR(i2c->pinctrl))
1359 return PTR_ERR(i2c->pinctrl);
1360
1361 if (!i2c->pinctrl)
1362 return 0;
1363
1364 i2c->pinctrl_default = pinctrl_lookup_state(i2c->pinctrl,
1365 PINCTRL_STATE_DEFAULT);
1366 i2c->pinctrl_recovery = pinctrl_lookup_state(i2c->pinctrl, "recovery");
1367
1368 if (IS_ERR(i2c->pinctrl_default) || IS_ERR(i2c->pinctrl_recovery)) {
1369 dev_info(dev, "missing pinmux recovery information: %ld %ld\n",
1370 PTR_ERR(i2c->pinctrl_default),
1371 PTR_ERR(i2c->pinctrl_recovery));
1372 return 0;
1373 }
1374
1375 /*
1376 * Claiming GPIOs can influence the pinmux state, and may glitch the
1377 * I2C bus. Do this carefully.
1378 */
1379 bri->scl_gpiod = devm_gpiod_get(dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1380 if (bri->scl_gpiod == ERR_PTR(-EPROBE_DEFER))
1381 return -EPROBE_DEFER;
1382 if (IS_ERR(bri->scl_gpiod)) {
1383 dev_info(dev, "missing scl gpio recovery information: %pe\n",
1384 bri->scl_gpiod);
1385 return 0;
1386 }
1387
1388 /*
1389 * We have SCL. Pull SCL low and wait a bit so that SDA glitches
1390 * have no effect.
1391 */
1392 gpiod_direction_output(bri->scl_gpiod, 0);
1393 udelay(10);
1394 bri->sda_gpiod = devm_gpiod_get(dev, "sda", GPIOD_OUT_HIGH_OPEN_DRAIN);
1395
1396 /* Wait a bit in case of a SDA glitch, and then release SCL. */
1397 udelay(10);
1398 gpiod_direction_output(bri->scl_gpiod, 1);
1399
1400 if (bri->sda_gpiod == ERR_PTR(-EPROBE_DEFER))
1401 return -EPROBE_DEFER;
1402
1403 if (IS_ERR(bri->sda_gpiod)) {
1404 dev_info(dev, "missing sda gpio recovery information: %pe\n",
1405 bri->sda_gpiod);
1406 return 0;
1407 }
1408
1409 bri->prepare_recovery = i2c_pxa_prepare_recovery;
1410 bri->unprepare_recovery = i2c_pxa_unprepare_recovery;
1411 bri->recover_bus = i2c_generic_scl_recovery;
1412
1413 i2c->adap.bus_recovery_info = bri;
1414
1415 /*
1416 * Claiming GPIOs can change the pinmux state, which confuses the
1417 * pinctrl since pinctrl's idea of the current setting is unaffected
1418 * by the pinmux change caused by claiming the GPIO. Work around that
1419 * by switching pinctrl to the GPIO state here. We do it this way to
1420 * avoid glitching the I2C bus.
1421 */
1422 pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_recovery);
1423
1424 return pinctrl_select_state(i2c->pinctrl, i2c->pinctrl_default);
1425 }
1426
i2c_pxa_probe(struct platform_device * dev)1427 static int i2c_pxa_probe(struct platform_device *dev)
1428 {
1429 struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
1430 enum pxa_i2c_types i2c_type;
1431 struct pxa_i2c *i2c;
1432 struct resource *res;
1433 int ret, irq;
1434
1435 i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1436 if (!i2c)
1437 return -ENOMEM;
1438
1439 /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1440 i2c->adap.nr = dev->id;
1441 i2c->adap.owner = THIS_MODULE;
1442 i2c->adap.retries = 5;
1443 i2c->adap.algo_data = i2c;
1444 i2c->adap.dev.parent = &dev->dev;
1445 #ifdef CONFIG_OF
1446 i2c->adap.dev.of_node = dev->dev.of_node;
1447 #endif
1448
1449 i2c->reg_base = devm_platform_get_and_ioremap_resource(dev, 0, &res);
1450 if (IS_ERR(i2c->reg_base))
1451 return PTR_ERR(i2c->reg_base);
1452
1453 irq = platform_get_irq(dev, 0);
1454 if (irq < 0)
1455 return irq;
1456
1457 ret = i2c_pxa_init_recovery(i2c);
1458 if (ret)
1459 return ret;
1460
1461 ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1462 if (ret > 0)
1463 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1464 if (ret < 0)
1465 return ret;
1466
1467 spin_lock_init(&i2c->lock);
1468 init_waitqueue_head(&i2c->wait);
1469
1470 strscpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1471
1472 i2c->clk = devm_clk_get(&dev->dev, NULL);
1473 if (IS_ERR(i2c->clk))
1474 return dev_err_probe(&dev->dev, PTR_ERR(i2c->clk),
1475 "failed to get the clk\n");
1476
1477 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1478 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1479 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1480 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1481 i2c->fm_mask = pxa_reg_layout[i2c_type].fm;
1482 i2c->hs_mask = pxa_reg_layout[i2c_type].hs;
1483
1484 i2c->busy_mask = ISR_UB | ISR_IBB;
1485 if (i2c_type == REGS_A3700)
1486 i2c->busy_mask |= ISR_A3700_EBB;
1487
1488 if (i2c_type != REGS_CE4100)
1489 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1490
1491 if (i2c_type == REGS_PXA910) {
1492 i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr;
1493 i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr;
1494 }
1495
1496 i2c->iobase = res->start;
1497 i2c->iosize = resource_size(res);
1498
1499 i2c->irq = irq;
1500
1501 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1502 i2c->highmode_enter = false;
1503
1504 if (plat) {
1505 i2c->adap.class = plat->class;
1506 }
1507
1508 if (i2c->high_mode) {
1509 if (i2c->rate) {
1510 clk_set_rate(i2c->clk, i2c->rate);
1511 pr_info("i2c: <%s> set rate to %ld\n",
1512 i2c->adap.name, clk_get_rate(i2c->clk));
1513 } else
1514 pr_warn("i2c: <%s> clock rate not set\n",
1515 i2c->adap.name);
1516 }
1517
1518 ret = clk_prepare_enable(i2c->clk);
1519 if (ret)
1520 return dev_err_probe(&dev->dev, ret,
1521 "failed to enable clock\n");
1522
1523 if (i2c->use_pio) {
1524 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1525 } else {
1526 i2c->adap.algo = &i2c_pxa_algorithm;
1527 ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1528 IRQF_SHARED | IRQF_NO_SUSPEND,
1529 dev_name(&dev->dev), i2c);
1530 if (ret) {
1531 dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1532 goto ereqirq;
1533 }
1534 }
1535
1536 /*
1537 * Skip reset on Armada 3700 when recovery is used to avoid
1538 * controller hang due to the pinctrl state changes done by
1539 * the generic recovery initialization code. The reset will
1540 * be performed later, prior to the first transfer.
1541 */
1542 if (i2c_type == REGS_A3700 && i2c->adap.bus_recovery_info)
1543 i2c->reset_before_xfer = true;
1544 else
1545 i2c_pxa_reset(i2c);
1546
1547 ret = i2c_add_numbered_adapter(&i2c->adap);
1548 if (ret < 0)
1549 goto ereqirq;
1550
1551 platform_set_drvdata(dev, i2c);
1552
1553 #ifdef CONFIG_I2C_PXA_SLAVE
1554 dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1555 i2c->slave_addr);
1556 #else
1557 dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1558 #endif
1559 return 0;
1560
1561 ereqirq:
1562 clk_disable_unprepare(i2c->clk);
1563 return ret;
1564 }
1565
i2c_pxa_remove(struct platform_device * dev)1566 static void i2c_pxa_remove(struct platform_device *dev)
1567 {
1568 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1569
1570 i2c_del_adapter(&i2c->adap);
1571
1572 clk_disable_unprepare(i2c->clk);
1573 }
1574
i2c_pxa_suspend_noirq(struct device * dev)1575 static int i2c_pxa_suspend_noirq(struct device *dev)
1576 {
1577 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1578
1579 clk_disable(i2c->clk);
1580
1581 return 0;
1582 }
1583
i2c_pxa_resume_noirq(struct device * dev)1584 static int i2c_pxa_resume_noirq(struct device *dev)
1585 {
1586 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1587
1588 clk_enable(i2c->clk);
1589 i2c_pxa_reset(i2c);
1590
1591 return 0;
1592 }
1593
1594 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1595 .suspend_noirq = i2c_pxa_suspend_noirq,
1596 .resume_noirq = i2c_pxa_resume_noirq,
1597 };
1598
1599 static struct platform_driver i2c_pxa_driver = {
1600 .probe = i2c_pxa_probe,
1601 .remove = i2c_pxa_remove,
1602 .driver = {
1603 .name = "pxa2xx-i2c",
1604 .pm = pm_sleep_ptr(&i2c_pxa_dev_pm_ops),
1605 .of_match_table = i2c_pxa_dt_ids,
1606 },
1607 .id_table = i2c_pxa_id_table,
1608 };
1609
i2c_adap_pxa_init(void)1610 static int __init i2c_adap_pxa_init(void)
1611 {
1612 return platform_driver_register(&i2c_pxa_driver);
1613 }
1614
i2c_adap_pxa_exit(void)1615 static void __exit i2c_adap_pxa_exit(void)
1616 {
1617 platform_driver_unregister(&i2c_pxa_driver);
1618 }
1619
1620 MODULE_DESCRIPTION("Intel PXA2XX I2C adapter");
1621 MODULE_LICENSE("GPL");
1622
1623 subsys_initcall(i2c_adap_pxa_init);
1624 module_exit(i2c_adap_pxa_exit);
1625