1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34 #define AMDGPU_MES_MAX_GFX_PIPES 2 35 #define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37 #define AMDGPU_MES_API_VERSION_SHIFT 12 38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40 #define AMDGPU_MES_VERSION_MASK 0x00000fff 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 #define AMDGPU_MES_MSCRATCH_SIZE 0x40000 44 #define AMDGPU_MES_INVALID_DB_OFFSET 0xffffffff 45 46 enum amdgpu_mes_priority_level { 47 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 48 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 49 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 50 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 51 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 52 AMDGPU_MES_PRIORITY_NUM_LEVELS 53 }; 54 55 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 56 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 57 58 struct amdgpu_mes_funcs; 59 60 enum amdgpu_mes_pipe { 61 AMDGPU_MES_PIPE_0 = 0, 62 AMDGPU_MES_PIPE_1, 63 AMDGPU_MAX_MES_PIPES = 2, 64 }; 65 66 #define AMDGPU_MES_SCHED_PIPE AMDGPU_MES_PIPE_0 67 #define AMDGPU_MES_KIQ_PIPE AMDGPU_MES_PIPE_1 68 69 #define AMDGPU_MAX_MES_INST_PIPES \ 70 (AMDGPU_MAX_MES_PIPES * AMDGPU_MAX_GC_INSTANCES) 71 72 #define MES_PIPE_INST(xcc_id, pipe_id) \ 73 (xcc_id * AMDGPU_MAX_MES_PIPES + pipe_id) 74 75 struct amdgpu_mes { 76 struct amdgpu_device *adev; 77 78 struct mutex mutex_hidden; 79 80 struct ida doorbell_ida; 81 82 spinlock_t queue_id_lock; 83 84 uint32_t sched_version; 85 uint32_t kiq_version; 86 uint32_t fw_version[AMDGPU_MAX_MES_PIPES]; 87 bool enable_legacy_queue_map; 88 89 uint32_t total_max_queue; 90 uint32_t max_doorbell_slices; 91 92 uint64_t default_process_quantum; 93 uint64_t default_gang_quantum; 94 95 struct amdgpu_ring ring[AMDGPU_MAX_MES_INST_PIPES]; 96 spinlock_t ring_lock[AMDGPU_MAX_MES_INST_PIPES]; 97 98 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 99 100 /* mes ucode */ 101 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 102 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 103 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 104 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 105 106 /* mes ucode data */ 107 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; 108 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 109 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; 110 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 111 112 /* eop gpu obj */ 113 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; 114 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 115 116 void *mqd_backup[AMDGPU_MAX_MES_INST_PIPES]; 117 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_INST_PIPES]; 118 119 uint32_t vmid_mask_gfxhub; 120 uint32_t vmid_mask_mmhub; 121 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 122 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 123 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 124 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 125 126 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_INST_PIPES]; 127 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 128 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_INST_PIPES]; 129 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_INST_PIPES]; 130 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 131 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_INST_PIPES]; 132 133 uint32_t saved_flags; 134 135 /* initialize kiq pipe */ 136 int (*kiq_hw_init)(struct amdgpu_device *adev, 137 uint32_t xcc_id); 138 int (*kiq_hw_fini)(struct amdgpu_device *adev, 139 uint32_t xcc_id); 140 141 /* MES doorbells */ 142 uint32_t db_start_dw_offset; 143 uint32_t num_mes_dbs; 144 unsigned long *doorbell_bitmap; 145 146 /* MES event log buffer */ 147 uint32_t event_log_size; 148 struct amdgpu_bo *event_log_gpu_obj; 149 uint64_t event_log_gpu_addr; 150 void *event_log_cpu_addr; 151 152 /* ip specific functions */ 153 const struct amdgpu_mes_funcs *funcs; 154 155 /* mes resource_1 bo*/ 156 struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES]; 157 uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES]; 158 void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; 159 160 int hung_queue_db_array_size; 161 int hung_queue_hqd_info_offset; 162 struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_PIPES]; 163 uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_PIPES]; 164 void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_PIPES]; 165 166 /* cooperative dispatch */ 167 bool enable_coop_mode; 168 int master_xcc_ids[AMDGPU_MAX_MES_INST_PIPES]; 169 struct amdgpu_bo *shared_cmd_buf_obj[AMDGPU_MAX_MES_INST_PIPES]; 170 uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; 171 }; 172 173 struct amdgpu_mes_gang { 174 int gang_id; 175 int priority; 176 int inprocess_gang_priority; 177 int global_priority_level; 178 struct list_head list; 179 struct amdgpu_mes_process *process; 180 struct amdgpu_bo *gang_ctx_bo; 181 uint64_t gang_ctx_gpu_addr; 182 void *gang_ctx_cpu_ptr; 183 uint64_t gang_quantum; 184 struct list_head queue_list; 185 }; 186 187 struct amdgpu_mes_queue { 188 struct list_head list; 189 struct amdgpu_mes_gang *gang; 190 int queue_id; 191 uint64_t doorbell_off; 192 struct amdgpu_bo *mqd_obj; 193 void *mqd_cpu_ptr; 194 uint64_t mqd_gpu_addr; 195 uint64_t wptr_gpu_addr; 196 int queue_type; 197 int paging; 198 struct amdgpu_ring *ring; 199 }; 200 201 struct amdgpu_mes_queue_properties { 202 int queue_type; 203 uint64_t hqd_base_gpu_addr; 204 uint64_t rptr_gpu_addr; 205 uint64_t wptr_gpu_addr; 206 uint64_t wptr_mc_addr; 207 uint32_t queue_size; 208 uint64_t eop_gpu_addr; 209 uint32_t hqd_pipe_priority; 210 uint32_t hqd_queue_priority; 211 bool paging; 212 struct amdgpu_ring *ring; 213 /* out */ 214 uint64_t doorbell_off; 215 }; 216 217 struct amdgpu_mes_gang_properties { 218 uint32_t priority; 219 uint32_t gang_quantum; 220 uint32_t inprocess_gang_priority; 221 uint32_t priority_level; 222 int global_priority_level; 223 }; 224 225 struct mes_add_queue_input { 226 uint32_t xcc_id; 227 uint32_t process_id; 228 uint64_t page_table_base_addr; 229 uint64_t process_va_start; 230 uint64_t process_va_end; 231 uint64_t process_quantum; 232 uint64_t process_context_addr; 233 uint64_t gang_quantum; 234 uint64_t gang_context_addr; 235 uint32_t inprocess_gang_priority; 236 uint32_t gang_global_priority_level; 237 uint32_t doorbell_offset; 238 uint64_t mqd_addr; 239 uint64_t wptr_addr; 240 uint64_t wptr_mc_addr; 241 uint32_t queue_type; 242 uint32_t paging; 243 uint32_t gws_base; 244 uint32_t gws_size; 245 uint64_t tba_addr; 246 uint64_t tma_addr; 247 uint32_t trap_en; 248 uint32_t skip_process_ctx_clear; 249 uint32_t is_kfd_process; 250 uint32_t is_aql_queue; 251 uint32_t queue_size; 252 uint32_t exclusively_scheduled; 253 uint32_t sh_mem_config_data; 254 uint32_t vm_cntx_cntl; 255 }; 256 257 struct mes_remove_queue_input { 258 uint32_t xcc_id; 259 uint32_t doorbell_offset; 260 uint64_t gang_context_addr; 261 bool remove_queue_after_reset; 262 }; 263 264 struct mes_map_legacy_queue_input { 265 uint32_t xcc_id; 266 uint32_t queue_type; 267 uint32_t doorbell_offset; 268 uint32_t pipe_id; 269 uint32_t queue_id; 270 uint64_t mqd_addr; 271 uint64_t wptr_addr; 272 }; 273 274 struct mes_unmap_legacy_queue_input { 275 uint32_t xcc_id; 276 enum amdgpu_unmap_queues_action action; 277 uint32_t queue_type; 278 uint32_t doorbell_offset; 279 uint32_t pipe_id; 280 uint32_t queue_id; 281 uint64_t trail_fence_addr; 282 uint64_t trail_fence_data; 283 }; 284 285 struct mes_suspend_gang_input { 286 uint32_t xcc_id; 287 bool suspend_all_gangs; 288 uint64_t gang_context_addr; 289 uint64_t suspend_fence_addr; 290 uint32_t suspend_fence_value; 291 }; 292 293 struct mes_resume_gang_input { 294 uint32_t xcc_id; 295 bool resume_all_gangs; 296 uint64_t gang_context_addr; 297 }; 298 299 struct mes_reset_queue_input { 300 uint32_t xcc_id; 301 uint32_t queue_type; 302 uint32_t doorbell_offset; 303 bool use_mmio; 304 uint32_t me_id; 305 uint32_t pipe_id; 306 uint32_t queue_id; 307 uint64_t mqd_addr; 308 uint64_t wptr_addr; 309 uint32_t vmid; 310 bool legacy_gfx; 311 bool is_kq; 312 }; 313 314 struct mes_detect_and_reset_queue_input { 315 uint32_t queue_type; 316 bool detect_only; 317 }; 318 319 struct mes_inv_tlbs_pasid_input { 320 uint32_t xcc_id; 321 uint16_t pasid; 322 uint8_t hub_id; 323 uint8_t flush_type; 324 }; 325 326 enum mes_misc_opcode { 327 MES_MISC_OP_WRITE_REG, 328 MES_MISC_OP_READ_REG, 329 MES_MISC_OP_WRM_REG_WAIT, 330 MES_MISC_OP_WRM_REG_WR_WAIT, 331 MES_MISC_OP_SET_SHADER_DEBUGGER, 332 MES_MISC_OP_CHANGE_CONFIG, 333 }; 334 335 struct mes_misc_op_input { 336 uint32_t xcc_id; 337 enum mes_misc_opcode op; 338 339 union { 340 struct { 341 uint32_t reg_offset; 342 uint64_t buffer_addr; 343 } read_reg; 344 345 struct { 346 uint32_t reg_offset; 347 uint32_t reg_value; 348 } write_reg; 349 350 struct { 351 uint32_t ref; 352 uint32_t mask; 353 uint32_t reg0; 354 uint32_t reg1; 355 } wrm_reg; 356 357 struct { 358 uint64_t process_context_addr; 359 union { 360 struct { 361 uint32_t single_memop : 1; 362 uint32_t single_alu_op : 1; 363 uint32_t reserved: 29; 364 uint32_t process_ctx_flush: 1; 365 }; 366 uint32_t u32all; 367 } flags; 368 uint32_t spi_gdbg_per_vmid_cntl; 369 uint32_t tcp_watch_cntl[4]; 370 uint32_t trap_en; 371 } set_shader_debugger; 372 373 struct { 374 union { 375 struct { 376 uint32_t limit_single_process : 1; 377 uint32_t enable_hws_logging_buffer : 1; 378 uint32_t reserved : 30; 379 }; 380 uint32_t all; 381 } option; 382 struct { 383 uint32_t tdr_level; 384 uint32_t tdr_delay; 385 } tdr_config; 386 } change_config; 387 }; 388 }; 389 390 struct amdgpu_mes_funcs { 391 int (*add_hw_queue)(struct amdgpu_mes *mes, 392 struct mes_add_queue_input *input); 393 394 int (*remove_hw_queue)(struct amdgpu_mes *mes, 395 struct mes_remove_queue_input *input); 396 397 int (*map_legacy_queue)(struct amdgpu_mes *mes, 398 struct mes_map_legacy_queue_input *input); 399 400 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 401 struct mes_unmap_legacy_queue_input *input); 402 403 int (*suspend_gang)(struct amdgpu_mes *mes, 404 struct mes_suspend_gang_input *input); 405 406 int (*resume_gang)(struct amdgpu_mes *mes, 407 struct mes_resume_gang_input *input); 408 409 int (*misc_op)(struct amdgpu_mes *mes, 410 struct mes_misc_op_input *input); 411 412 int (*reset_hw_queue)(struct amdgpu_mes *mes, 413 struct mes_reset_queue_input *input); 414 415 int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes, 416 struct mes_detect_and_reset_queue_input *input); 417 418 419 int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, 420 struct mes_inv_tlbs_pasid_input *input); 421 }; 422 423 #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ 424 (adev)->mes.kiq_hw_init((adev), (xcc_id)) 425 #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ 426 (adev)->mes.kiq_hw_fini((adev), (xcc_id)) 427 428 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 429 int amdgpu_mes_init(struct amdgpu_device *adev); 430 void amdgpu_mes_fini(struct amdgpu_device *adev); 431 432 int amdgpu_mes_suspend(struct amdgpu_device *adev); 433 int amdgpu_mes_resume(struct amdgpu_device *adev); 434 435 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 436 struct amdgpu_ring *ring, uint32_t xcc_id); 437 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 438 struct amdgpu_ring *ring, 439 enum amdgpu_unmap_queues_action action, 440 u64 gpu_addr, u64 seq, uint32_t xcc_id); 441 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 442 struct amdgpu_ring *ring, 443 unsigned int vmid, 444 bool use_mmio, 445 uint32_t xcc_id); 446 447 int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev); 448 int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, 449 int queue_type, 450 bool detect_only, 451 unsigned int *hung_db_num, 452 u32 *hung_db_array, 453 uint32_t xcc_id); 454 455 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, 456 uint32_t xcc_id); 457 int amdgpu_mes_wreg(struct amdgpu_device *adev, 458 uint32_t reg, uint32_t val, uint32_t xcc_id); 459 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 460 uint32_t reg0, uint32_t reg1, 461 uint32_t ref, uint32_t mask, uint32_t xcc_id); 462 int amdgpu_mes_hdp_flush(struct amdgpu_device *adev); 463 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 464 uint64_t process_context_addr, 465 uint32_t spi_gdbg_per_vmid_cntl, 466 const uint32_t *tcp_watch_cntl, 467 uint32_t flags, 468 bool trap_en, 469 uint32_t xcc_id); 470 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 471 uint64_t process_context_addr, uint32_t xcc_id); 472 473 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 474 enum amdgpu_mes_priority_level prio); 475 476 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 477 478 /* 479 * MES lock can be taken in MMU notifiers. 480 * 481 * A bit more detail about why to set no-FS reclaim with MES lock: 482 * 483 * The purpose of the MMU notifier is to stop GPU access to memory so 484 * that the Linux VM subsystem can move pages around safely. This is 485 * done by preempting user mode queues for the affected process. When 486 * MES is used, MES lock needs to be taken to preempt the queues. 487 * 488 * The MMU notifier callback entry point in the driver is 489 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 490 * there is: 491 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 492 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 493 * 494 * The last part of the chain is a function pointer where we take the 495 * MES lock. 496 * 497 * The problem with taking locks in the MMU notifier is, that MMU 498 * notifiers can be called in reclaim-FS context. That's where the 499 * kernel frees up pages to make room for new page allocations under 500 * memory pressure. While we are running in reclaim-FS context, we must 501 * not trigger another memory reclaim operation because that would 502 * recursively reenter the reclaim code and cause a deadlock. The 503 * memalloc_nofs_save/restore calls guarantee that. 504 * 505 * In addition we also need to avoid lock dependencies on other locks taken 506 * under the MES lock, for example reservation locks. Here is a possible 507 * scenario of a deadlock: 508 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 509 * MMU notifier | blocks trying to take MES lock 510 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 511 * 512 * In this scenario Thread B gets involved in a deadlock even without 513 * triggering a reclaim-FS operation itself. 514 * To fix this and break the lock dependency chain you'd need to either: 515 * 1. protect reservation locks with memalloc_nofs_save/restore, or 516 * 2. avoid taking reservation locks under the MES lock. 517 * 518 * Reservation locks are taken all over the kernel in different subsystems, we 519 * have no control over them and their lock dependencies.So the only workable 520 * solution is to avoid taking other locks under the MES lock. 521 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 522 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 523 */ 524 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 525 { 526 mutex_lock(&mes->mutex_hidden); 527 mes->saved_flags = memalloc_noreclaim_save(); 528 } 529 530 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 531 { 532 memalloc_noreclaim_restore(mes->saved_flags); 533 mutex_unlock(&mes->mutex_hidden); 534 } 535 536 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); 537 538 int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev); 539 540 #endif /* __AMDGPU_MES_H__ */ 541