1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ALSA SoC Synopsys I2S Audio Layer 4 * 5 * sound/soc/dwc/designware_i2s.c 6 * 7 * Copyright (C) 2010 ST Microelectronics 8 * Rajeev Kumar <rajeevkumar.linux@gmail.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/interrupt.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/module.h> 18 #include <linux/reset.h> 19 #include <linux/slab.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/property.h> 22 #include <sound/designware_i2s.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/dmaengine_pcm.h> 27 #include "local.h" 28 29 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val) 30 { 31 writel(val, io_base + reg); 32 } 33 34 static inline u32 i2s_read_reg(void __iomem *io_base, int reg) 35 { 36 return readl(io_base + reg); 37 } 38 39 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream) 40 { 41 u32 i = 0; 42 43 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 44 for (i = 0; i < 4; i++) 45 i2s_write_reg(dev->i2s_base, TER(i), 0); 46 } else { 47 for (i = 0; i < 4; i++) 48 i2s_write_reg(dev->i2s_base, RER(i), 0); 49 } 50 } 51 52 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream) 53 { 54 u32 i = 0; 55 56 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 57 for (i = 0; i < 4; i++) 58 i2s_read_reg(dev->i2s_base, TOR(i)); 59 } else { 60 for (i = 0; i < 4; i++) 61 i2s_read_reg(dev->i2s_base, ROR(i)); 62 } 63 } 64 65 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream, 66 int chan_nr) 67 { 68 u32 i, irq; 69 70 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 71 for (i = 0; i < (chan_nr / 2); i++) { 72 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 73 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); 74 } 75 } else { 76 for (i = 0; i < (chan_nr / 2); i++) { 77 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 78 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); 79 } 80 } 81 } 82 83 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream, 84 int chan_nr) 85 { 86 u32 i, irq; 87 88 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 89 for (i = 0; i < (chan_nr / 2); i++) { 90 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 91 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); 92 } 93 } else { 94 for (i = 0; i < (chan_nr / 2); i++) { 95 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 96 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); 97 } 98 } 99 } 100 101 static irqreturn_t i2s_irq_handler(int irq, void *dev_id) 102 { 103 struct dw_i2s_dev *dev = dev_id; 104 bool irq_valid = false; 105 u32 isr[4]; 106 int i; 107 108 for (i = 0; i < 4; i++) 109 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i)); 110 111 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK); 112 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE); 113 114 for (i = 0; i < 4; i++) { 115 /* 116 * Check if TX fifo is empty. If empty fill FIFO with samples 117 * NOTE: Only two channels supported 118 */ 119 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) { 120 dw_pcm_push_tx(dev); 121 irq_valid = true; 122 } 123 124 /* 125 * Data available. Retrieve samples from FIFO 126 * NOTE: Only two channels supported 127 */ 128 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) { 129 dw_pcm_pop_rx(dev); 130 irq_valid = true; 131 } 132 133 /* Error Handling: TX */ 134 if (isr[i] & ISR_TXFO) { 135 dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i); 136 irq_valid = true; 137 } 138 139 /* Error Handling: TX */ 140 if (isr[i] & ISR_RXFO) { 141 dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i); 142 irq_valid = true; 143 } 144 } 145 146 if (irq_valid) 147 return IRQ_HANDLED; 148 else 149 return IRQ_NONE; 150 } 151 152 static void i2s_enable_dma(struct dw_i2s_dev *dev, u32 stream) 153 { 154 u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR); 155 156 /* Enable DMA handshake for stream */ 157 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 158 dma_reg |= I2S_DMAEN_TXBLOCK; 159 else 160 dma_reg |= I2S_DMAEN_RXBLOCK; 161 162 i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); 163 } 164 165 static void i2s_disable_dma(struct dw_i2s_dev *dev, u32 stream) 166 { 167 u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR); 168 169 /* Disable DMA handshake for stream */ 170 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 171 dma_reg &= ~I2S_DMAEN_TXBLOCK; 172 i2s_write_reg(dev->i2s_base, I2S_RTXDMA, 1); 173 } else { 174 dma_reg &= ~I2S_DMAEN_RXBLOCK; 175 i2s_write_reg(dev->i2s_base, I2S_RRXDMA, 1); 176 } 177 i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); 178 } 179 180 static void i2s_start(struct dw_i2s_dev *dev, 181 struct snd_pcm_substream *substream) 182 { 183 struct i2s_clk_config_data *config = &dev->config; 184 185 u32 reg = IER_IEN; 186 187 if (dev->tdm_slots) { 188 reg |= (dev->tdm_slots - 1) << IER_TDM_SLOTS_SHIFT; 189 reg |= IER_INTF_TYPE; 190 reg |= dev->frame_offset << IER_FRAME_OFF_SHIFT; 191 } 192 193 i2s_write_reg(dev->i2s_base, IER, reg); 194 195 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 196 i2s_write_reg(dev->i2s_base, ITER, 1); 197 else 198 i2s_write_reg(dev->i2s_base, IRER, 1); 199 200 if (!(dev->use_pio || dev->is_jh7110)) 201 i2s_enable_dma(dev, substream->stream); 202 203 i2s_enable_irqs(dev, substream->stream, config->chan_nr); 204 i2s_write_reg(dev->i2s_base, CER, 1); 205 } 206 207 static void i2s_stop(struct dw_i2s_dev *dev, 208 struct snd_pcm_substream *substream) 209 { 210 211 i2s_clear_irqs(dev, substream->stream); 212 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 213 i2s_write_reg(dev->i2s_base, ITER, 0); 214 else 215 i2s_write_reg(dev->i2s_base, IRER, 0); 216 217 if (!(dev->use_pio || dev->is_jh7110)) 218 i2s_disable_dma(dev, substream->stream); 219 220 i2s_disable_irqs(dev, substream->stream, 8); 221 222 223 if (!dev->active) { 224 i2s_write_reg(dev->i2s_base, CER, 0); 225 i2s_write_reg(dev->i2s_base, IER, 0); 226 } 227 } 228 229 static int dw_i2s_startup(struct snd_pcm_substream *substream, 230 struct snd_soc_dai *cpu_dai) 231 { 232 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 233 234 if (dev->is_jh7110) { 235 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 236 struct snd_soc_dai_link *dai_link = rtd->dai_link; 237 238 dai_link->trigger_stop = SND_SOC_TRIGGER_ORDER_LDC; 239 } 240 241 return 0; 242 } 243 244 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream) 245 { 246 u32 ch_reg; 247 struct i2s_clk_config_data *config = &dev->config; 248 249 250 i2s_disable_channels(dev, stream); 251 252 for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { 253 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 254 i2s_write_reg(dev->i2s_base, TCR(ch_reg), 255 dev->xfer_resolution); 256 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 257 dev->fifo_th - 1); 258 i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN | 259 dev->tdm_mask << TER_TXSLOT_SHIFT); 260 } else { 261 i2s_write_reg(dev->i2s_base, RCR(ch_reg), 262 dev->xfer_resolution); 263 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 264 dev->fifo_th - 1); 265 i2s_write_reg(dev->i2s_base, RER(ch_reg), RER_RXCHEN | 266 dev->tdm_mask << RER_RXSLOT_SHIFT); 267 } 268 269 } 270 } 271 272 static int dw_i2s_hw_params(struct snd_pcm_substream *substream, 273 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 274 { 275 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 276 struct i2s_clk_config_data *config = &dev->config; 277 int ret; 278 279 switch (params_format(params)) { 280 case SNDRV_PCM_FORMAT_S16_LE: 281 config->data_width = 16; 282 dev->ccr = 0x00; 283 dev->xfer_resolution = 0x02; 284 break; 285 286 case SNDRV_PCM_FORMAT_S24_LE: 287 config->data_width = 24; 288 dev->ccr = 0x08; 289 dev->xfer_resolution = 0x04; 290 break; 291 292 case SNDRV_PCM_FORMAT_S32_LE: 293 config->data_width = 32; 294 dev->ccr = 0x10; 295 dev->xfer_resolution = 0x05; 296 break; 297 298 default: 299 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt"); 300 return -EINVAL; 301 } 302 303 if (dev->tdm_slots) 304 config->data_width = 32; 305 306 config->chan_nr = params_channels(params); 307 308 switch (config->chan_nr) { 309 case EIGHT_CHANNEL_SUPPORT: 310 case SIX_CHANNEL_SUPPORT: 311 case FOUR_CHANNEL_SUPPORT: 312 case TWO_CHANNEL_SUPPORT: 313 break; 314 default: 315 dev_err(dev->dev, "channel not supported\n"); 316 return -EINVAL; 317 } 318 319 dw_i2s_config(dev, substream->stream); 320 321 i2s_write_reg(dev->i2s_base, CCR, dev->ccr); 322 323 config->sample_rate = params_rate(params); 324 325 if (dev->capability & DW_I2S_MASTER) { 326 if (dev->i2s_clk_cfg) { 327 ret = dev->i2s_clk_cfg(config); 328 if (ret < 0) { 329 dev_err(dev->dev, "runtime audio clk config fail\n"); 330 return ret; 331 } 332 } else { 333 u32 bitclk = config->sample_rate * 334 config->data_width * 2; 335 336 ret = clk_set_rate(dev->clk, bitclk); 337 if (ret) { 338 dev_err(dev->dev, "Can't set I2S clock rate: %d\n", 339 ret); 340 return ret; 341 } 342 } 343 } 344 return 0; 345 } 346 347 static int dw_i2s_prepare(struct snd_pcm_substream *substream, 348 struct snd_soc_dai *dai) 349 { 350 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 351 352 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 353 i2s_write_reg(dev->i2s_base, TXFFR, 1); 354 else 355 i2s_write_reg(dev->i2s_base, RXFFR, 1); 356 357 return 0; 358 } 359 360 static int dw_i2s_trigger(struct snd_pcm_substream *substream, 361 int cmd, struct snd_soc_dai *dai) 362 { 363 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 364 int ret = 0; 365 366 switch (cmd) { 367 case SNDRV_PCM_TRIGGER_START: 368 case SNDRV_PCM_TRIGGER_RESUME: 369 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 370 dev->active++; 371 i2s_start(dev, substream); 372 break; 373 374 case SNDRV_PCM_TRIGGER_STOP: 375 case SNDRV_PCM_TRIGGER_SUSPEND: 376 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 377 dev->active--; 378 i2s_stop(dev, substream); 379 break; 380 default: 381 ret = -EINVAL; 382 break; 383 } 384 return ret; 385 } 386 387 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 388 { 389 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 390 int ret = 0; 391 392 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 393 case SND_SOC_DAIFMT_BC_FC: 394 if (dev->capability & DW_I2S_SLAVE) 395 ret = 0; 396 else 397 ret = -EINVAL; 398 break; 399 case SND_SOC_DAIFMT_BP_FP: 400 if (dev->capability & DW_I2S_MASTER) 401 ret = 0; 402 else 403 ret = -EINVAL; 404 break; 405 case SND_SOC_DAIFMT_BC_FP: 406 case SND_SOC_DAIFMT_BP_FC: 407 ret = -EINVAL; 408 break; 409 default: 410 dev_dbg(dev->dev, "dwc : Invalid clock provider format\n"); 411 ret = -EINVAL; 412 break; 413 } 414 415 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 416 case SND_SOC_DAIFMT_I2S: 417 case SND_SOC_DAIFMT_LEFT_J: 418 case SND_SOC_DAIFMT_RIGHT_J: 419 break; 420 case SND_SOC_DAIFMT_DSP_A: 421 dev->frame_offset = 1; 422 break; 423 case SND_SOC_DAIFMT_DSP_B: 424 dev->frame_offset = 0; 425 break; 426 default: 427 dev_err(dev->dev, "DAI format unsupported"); 428 return -EINVAL; 429 } 430 431 return ret; 432 } 433 434 static int dw_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai, unsigned int tx_mask, 435 unsigned int rx_mask, int slots, int slot_width) 436 { 437 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 438 439 if (slot_width != 32) 440 return -EINVAL; 441 442 if (slots < 0 || slots > 16) 443 return -EINVAL; 444 445 if (rx_mask != tx_mask) 446 return -EINVAL; 447 448 if (!rx_mask) 449 return -EINVAL; 450 451 dev->tdm_slots = slots; 452 dev->tdm_mask = rx_mask; 453 454 dev->l_reg = RSLOT_TSLOT(ffs(rx_mask) - 1); 455 dev->r_reg = RSLOT_TSLOT(fls(rx_mask) - 1); 456 457 return 0; 458 } 459 460 static int dw_i2s_dai_probe(struct snd_soc_dai *dai) 461 { 462 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 463 464 snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data); 465 return 0; 466 } 467 468 static const u64 dw_i2s_selectable_formats = 469 SND_SOC_POSSIBLE_DAIFMT_I2S | 470 SND_SOC_POSSIBLE_DAIFMT_RIGHT_J | 471 SND_SOC_POSSIBLE_DAIFMT_LEFT_J | 472 SND_SOC_POSSIBLE_DAIFMT_DSP_A | 473 SND_SOC_POSSIBLE_DAIFMT_DSP_B; 474 475 static const struct snd_soc_dai_ops dw_i2s_dai_ops = { 476 .probe = dw_i2s_dai_probe, 477 .startup = dw_i2s_startup, 478 .hw_params = dw_i2s_hw_params, 479 .prepare = dw_i2s_prepare, 480 .trigger = dw_i2s_trigger, 481 .set_fmt = dw_i2s_set_fmt, 482 .set_tdm_slot = dw_i2s_set_tdm_slot, 483 .auto_selectable_formats = &dw_i2s_selectable_formats, 484 .num_auto_selectable_formats = 1, 485 }; 486 487 static int dw_i2s_runtime_suspend(struct device *dev) 488 { 489 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); 490 491 if (dw_dev->capability & DW_I2S_MASTER) 492 clk_disable(dw_dev->clk); 493 return 0; 494 } 495 496 static int dw_i2s_runtime_resume(struct device *dev) 497 { 498 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); 499 int ret; 500 501 if (dw_dev->capability & DW_I2S_MASTER) { 502 ret = clk_enable(dw_dev->clk); 503 if (ret) 504 return ret; 505 } 506 return 0; 507 } 508 509 #ifdef CONFIG_PM 510 static int dw_i2s_suspend(struct snd_soc_component *component) 511 { 512 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component); 513 514 if (dev->capability & DW_I2S_MASTER) 515 clk_disable(dev->clk); 516 return 0; 517 } 518 519 static int dw_i2s_resume(struct snd_soc_component *component) 520 { 521 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component); 522 struct snd_soc_dai *dai; 523 int stream, ret; 524 525 if (dev->capability & DW_I2S_MASTER) { 526 ret = clk_enable(dev->clk); 527 if (ret) 528 return ret; 529 } 530 531 for_each_component_dais(component, dai) { 532 for_each_pcm_streams(stream) 533 if (snd_soc_dai_stream_active(dai, stream)) 534 dw_i2s_config(dev, stream); 535 } 536 537 return 0; 538 } 539 540 #else 541 #define dw_i2s_suspend NULL 542 #define dw_i2s_resume NULL 543 #endif 544 545 static const struct snd_soc_component_driver dw_i2s_component = { 546 .name = "dw-i2s", 547 .suspend = dw_i2s_suspend, 548 .resume = dw_i2s_resume, 549 .legacy_dai_naming = 1, 550 }; 551 552 /* 553 * The following tables allow a direct lookup of various parameters 554 * defined in the I2S block's configuration in terms of sound system 555 * parameters. Each table is sized to the number of entries possible 556 * according to the number of configuration bits describing an I2S 557 * block parameter. 558 */ 559 560 /* Maximum bit resolution of a channel - not uniformly spaced */ 561 static const u32 fifo_width[COMP_MAX_WORDSIZE] = { 562 12, 16, 20, 24, 32, 0, 0, 0 563 }; 564 565 /* Width of (DMA) bus */ 566 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = { 567 DMA_SLAVE_BUSWIDTH_1_BYTE, 568 DMA_SLAVE_BUSWIDTH_2_BYTES, 569 DMA_SLAVE_BUSWIDTH_4_BYTES, 570 DMA_SLAVE_BUSWIDTH_UNDEFINED 571 }; 572 573 /* PCM format to support channel resolution */ 574 static const u32 formats[COMP_MAX_WORDSIZE] = { 575 SNDRV_PCM_FMTBIT_S16_LE, 576 SNDRV_PCM_FMTBIT_S16_LE, 577 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 578 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 579 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 580 0, 581 0, 582 0 583 }; 584 585 static int dw_configure_dai(struct dw_i2s_dev *dev, 586 struct snd_soc_dai_driver *dw_i2s_dai, 587 unsigned int rates) 588 { 589 /* 590 * Read component parameter registers to extract 591 * the I2S block's configuration. 592 */ 593 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); 594 u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); 595 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); 596 u32 idx; 597 598 if (dev->capability & DWC_I2S_RECORD && 599 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) 600 comp1 = comp1 & ~BIT(5); 601 602 if (dev->capability & DWC_I2S_PLAY && 603 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) 604 comp1 = comp1 & ~BIT(6); 605 606 if (COMP1_TX_ENABLED(comp1)) { 607 dev_dbg(dev->dev, " designware: play supported\n"); 608 idx = COMP1_TX_WORDSIZE_0(comp1); 609 if (WARN_ON(idx >= ARRAY_SIZE(formats))) 610 return -EINVAL; 611 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 612 idx = 1; 613 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM; 614 dw_i2s_dai->playback.channels_max = 615 1 << (COMP1_TX_CHANNELS(comp1) + 1); 616 dw_i2s_dai->playback.formats = formats[idx]; 617 dw_i2s_dai->playback.rates = rates; 618 } 619 620 if (COMP1_RX_ENABLED(comp1)) { 621 dev_dbg(dev->dev, "designware: record supported\n"); 622 idx = COMP2_RX_WORDSIZE_0(comp2); 623 if (WARN_ON(idx >= ARRAY_SIZE(formats))) 624 return -EINVAL; 625 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 626 idx = 1; 627 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM; 628 dw_i2s_dai->capture.channels_max = 629 1 << (COMP1_RX_CHANNELS(comp1) + 1); 630 dw_i2s_dai->capture.formats = formats[idx]; 631 dw_i2s_dai->capture.rates = rates; 632 } 633 634 if (COMP1_MODE_EN(comp1)) { 635 dev_dbg(dev->dev, "designware: i2s master mode supported\n"); 636 dev->capability |= DW_I2S_MASTER; 637 } else { 638 dev_dbg(dev->dev, "designware: i2s slave mode supported\n"); 639 dev->capability |= DW_I2S_SLAVE; 640 } 641 642 dev->fifo_th = fifo_depth / 2; 643 return 0; 644 } 645 646 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev, 647 struct snd_soc_dai_driver *dw_i2s_dai, 648 struct resource *res, 649 const struct i2s_platform_data *pdata) 650 { 651 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); 652 u32 idx = COMP1_APB_DATA_WIDTH(comp1); 653 int ret; 654 655 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths))) 656 return -EINVAL; 657 658 ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates); 659 if (ret < 0) 660 return ret; 661 662 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 663 idx = 1; 664 665 if (dev->is_jh7110) { 666 /* Use platform data and snd_dmaengine_dai_dma_data struct at the same time */ 667 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); 668 u32 idx2; 669 670 if (COMP1_TX_ENABLED(comp1)) { 671 idx2 = COMP1_TX_WORDSIZE_0(comp1); 672 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; 673 dev->play_dma_data.dt.fifo_size = dev->fifo_th * 2 * 674 (fifo_width[idx2]) >> 8; 675 dev->play_dma_data.dt.maxburst = 16; 676 } 677 if (COMP1_RX_ENABLED(comp1)) { 678 idx2 = COMP2_RX_WORDSIZE_0(comp2); 679 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; 680 dev->capture_dma_data.dt.fifo_size = dev->fifo_th * 2 * 681 (fifo_width[idx2] >> 8); 682 dev->capture_dma_data.dt.maxburst = 16; 683 } 684 } else { 685 /* Set DMA slaves info */ 686 dev->play_dma_data.pd.data = pdata->play_dma_data; 687 dev->capture_dma_data.pd.data = pdata->capture_dma_data; 688 dev->play_dma_data.pd.addr = res->start + I2S_TXDMA; 689 dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA; 690 dev->play_dma_data.pd.max_burst = 16; 691 dev->capture_dma_data.pd.max_burst = 16; 692 dev->play_dma_data.pd.addr_width = bus_widths[idx]; 693 dev->capture_dma_data.pd.addr_width = bus_widths[idx]; 694 dev->play_dma_data.pd.filter = pdata->filter; 695 dev->capture_dma_data.pd.filter = pdata->filter; 696 } 697 698 return 0; 699 } 700 701 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev, 702 struct snd_soc_dai_driver *dw_i2s_dai, 703 struct resource *res) 704 { 705 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); 706 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); 707 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); 708 u32 idx2; 709 int ret; 710 711 ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000); 712 if (ret < 0) 713 return ret; 714 715 if (COMP1_TX_ENABLED(comp1)) { 716 idx2 = COMP1_TX_WORDSIZE_0(comp1); 717 718 dev->capability |= DWC_I2S_PLAY; 719 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; 720 dev->play_dma_data.dt.fifo_size = fifo_depth * 721 (fifo_width[idx2]) >> 8; 722 dev->play_dma_data.dt.maxburst = 16; 723 } 724 if (COMP1_RX_ENABLED(comp1)) { 725 idx2 = COMP2_RX_WORDSIZE_0(comp2); 726 727 dev->capability |= DWC_I2S_RECORD; 728 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; 729 dev->capture_dma_data.dt.fifo_size = fifo_depth * 730 (fifo_width[idx2] >> 8); 731 dev->capture_dma_data.dt.maxburst = 16; 732 } 733 734 return 0; 735 736 } 737 738 #ifdef CONFIG_OF 739 /* clocks initialization with master mode on JH7110 SoC */ 740 static int jh7110_i2s_crg_master_init(struct dw_i2s_dev *dev) 741 { 742 static struct clk_bulk_data clks[] = { 743 { .id = "mclk" }, 744 { .id = "mclk_ext" }, 745 { .id = "mclk_inner" }, 746 { .id = "apb" }, 747 { .id = "i2sclk" }, 748 }; 749 struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev); 750 int ret; 751 struct clk *pclk; 752 struct clk *bclk_mst; 753 struct clk *mclk; 754 struct clk *mclk_ext; 755 struct clk *mclk_inner; 756 757 if (IS_ERR(resets)) 758 return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n"); 759 760 ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks); 761 if (ret) 762 return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n"); 763 764 mclk = clks[0].clk; 765 mclk_ext = clks[1].clk; 766 mclk_inner = clks[2].clk; 767 pclk = clks[3].clk; 768 bclk_mst = clks[4].clk; 769 770 ret = clk_prepare_enable(pclk); 771 if (ret) 772 goto exit; 773 774 /* Use inner mclk first and avoid uninitialized gpio for external mclk */ 775 ret = clk_set_parent(mclk, mclk_inner); 776 if (ret) 777 goto err_dis_pclk; 778 779 ret = clk_prepare_enable(bclk_mst); 780 if (ret) 781 goto err_dis_pclk; 782 783 /* deassert resets before set clock parent */ 784 ret = reset_control_deassert(resets); 785 if (ret) 786 goto err_dis_all; 787 788 /* external clock (12.288MHz) for Audio */ 789 ret = clk_set_parent(mclk, mclk_ext); 790 if (ret) 791 goto err_dis_all; 792 793 /* i2sclk will be got and enabled repeatedly later and should be disabled now. */ 794 clk_disable_unprepare(bclk_mst); 795 clk_bulk_put(ARRAY_SIZE(clks), clks); 796 dev->is_jh7110 = true; 797 798 return 0; 799 800 err_dis_all: 801 clk_disable_unprepare(bclk_mst); 802 err_dis_pclk: 803 clk_disable_unprepare(pclk); 804 exit: 805 clk_bulk_put(ARRAY_SIZE(clks), clks); 806 return ret; 807 } 808 809 /* clocks initialization with slave mode on JH7110 SoC */ 810 static int jh7110_i2s_crg_slave_init(struct dw_i2s_dev *dev) 811 { 812 static struct clk_bulk_data clks[] = { 813 { .id = "mclk" }, 814 { .id = "mclk_ext" }, 815 { .id = "apb" }, 816 { .id = "bclk_ext" }, 817 { .id = "lrck_ext" }, 818 { .id = "bclk" }, 819 { .id = "lrck" }, 820 { .id = "mclk_inner" }, 821 { .id = "i2sclk" }, 822 }; 823 struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev); 824 int ret; 825 struct clk *pclk; 826 struct clk *bclk_mst; 827 struct clk *bclk_ext; 828 struct clk *lrck_ext; 829 struct clk *bclk; 830 struct clk *lrck; 831 struct clk *mclk; 832 struct clk *mclk_ext; 833 struct clk *mclk_inner; 834 835 if (IS_ERR(resets)) 836 return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n"); 837 838 ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks); 839 if (ret) 840 return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n"); 841 842 mclk = clks[0].clk; 843 mclk_ext = clks[1].clk; 844 pclk = clks[2].clk; 845 bclk_ext = clks[3].clk; 846 lrck_ext = clks[4].clk; 847 bclk = clks[5].clk; 848 lrck = clks[6].clk; 849 mclk_inner = clks[7].clk; 850 bclk_mst = clks[8].clk; 851 852 ret = clk_prepare_enable(pclk); 853 if (ret) 854 goto exit; 855 856 ret = clk_set_parent(mclk, mclk_inner); 857 if (ret) 858 goto err_dis_pclk; 859 860 ret = clk_prepare_enable(bclk_mst); 861 if (ret) 862 goto err_dis_pclk; 863 864 ret = reset_control_deassert(resets); 865 if (ret) 866 goto err_dis_all; 867 868 /* The sources of BCLK and LRCK are the external codec. */ 869 ret = clk_set_parent(bclk, bclk_ext); 870 if (ret) 871 goto err_dis_all; 872 873 ret = clk_set_parent(lrck, lrck_ext); 874 if (ret) 875 goto err_dis_all; 876 877 ret = clk_set_parent(mclk, mclk_ext); 878 if (ret) 879 goto err_dis_all; 880 881 /* The i2sclk will be got and enabled repeatedly later and should be disabled now. */ 882 clk_disable_unprepare(bclk_mst); 883 clk_bulk_put(ARRAY_SIZE(clks), clks); 884 dev->is_jh7110 = true; 885 886 return 0; 887 888 err_dis_all: 889 clk_disable_unprepare(bclk_mst); 890 err_dis_pclk: 891 clk_disable_unprepare(pclk); 892 exit: 893 clk_bulk_put(ARRAY_SIZE(clks), clks); 894 return ret; 895 } 896 897 /* Special syscon initialization about RX channel with slave mode on JH7110 SoC */ 898 static int jh7110_i2srx_crg_init(struct dw_i2s_dev *dev) 899 { 900 struct regmap *regmap; 901 unsigned int args[2]; 902 903 regmap = syscon_regmap_lookup_by_phandle_args(dev->dev->of_node, 904 "starfive,syscon", 905 2, args); 906 if (IS_ERR(regmap)) 907 return dev_err_probe(dev->dev, PTR_ERR(regmap), "getting the regmap failed\n"); 908 909 /* Enable I2Srx with syscon register, args[0]: offset, args[1]: mask */ 910 regmap_update_bits(regmap, args[0], args[1], args[1]); 911 912 return jh7110_i2s_crg_slave_init(dev); 913 } 914 915 static int jh7110_i2stx0_clk_cfg(struct i2s_clk_config_data *config) 916 { 917 struct dw_i2s_dev *dev = container_of(config, struct dw_i2s_dev, config); 918 u32 bclk_rate = config->sample_rate * 64; 919 920 return clk_set_rate(dev->clk, bclk_rate); 921 } 922 #endif /* CONFIG_OF */ 923 924 static int dw_i2s_probe(struct platform_device *pdev) 925 { 926 const struct i2s_platform_data *pdata = device_get_match_data(&pdev->dev); 927 struct dw_i2s_dev *dev; 928 struct resource *res; 929 int ret, irq; 930 struct snd_soc_dai_driver *dw_i2s_dai; 931 const char *clk_id; 932 933 if (!pdata) 934 pdata = dev_get_platdata(&pdev->dev); 935 936 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 937 if (!dev) 938 return -ENOMEM; 939 940 dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL); 941 if (!dw_i2s_dai) 942 return -ENOMEM; 943 944 dw_i2s_dai->ops = &dw_i2s_dai_ops; 945 946 dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 947 if (IS_ERR(dev->i2s_base)) 948 return PTR_ERR(dev->i2s_base); 949 950 dev->dev = &pdev->dev; 951 dev->is_jh7110 = false; 952 if (pdata) { 953 if (pdata->i2s_pd_init) { 954 ret = pdata->i2s_pd_init(dev); 955 if (ret) 956 return ret; 957 } 958 } 959 960 if (!dev->is_jh7110) { 961 dev->reset = devm_reset_control_array_get_optional_shared(&pdev->dev); 962 if (IS_ERR(dev->reset)) 963 return PTR_ERR(dev->reset); 964 965 ret = reset_control_deassert(dev->reset); 966 if (ret) 967 return ret; 968 } 969 970 irq = platform_get_irq_optional(pdev, 0); 971 if (irq == -EPROBE_DEFER) 972 return irq; 973 if (irq > 0) { 974 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0, 975 pdev->name, dev); 976 if (ret < 0) { 977 dev_err(&pdev->dev, "failed to request irq\n"); 978 goto err_assert_reset; 979 } 980 } 981 982 dev->i2s_reg_comp1 = I2S_COMP_PARAM_1; 983 dev->i2s_reg_comp2 = I2S_COMP_PARAM_2; 984 if (pdata) { 985 dev->capability = pdata->cap; 986 clk_id = NULL; 987 dev->quirks = pdata->quirks; 988 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) { 989 dev->i2s_reg_comp1 = pdata->i2s_reg_comp1; 990 dev->i2s_reg_comp2 = pdata->i2s_reg_comp2; 991 } 992 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata); 993 } else { 994 clk_id = "i2sclk"; 995 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res); 996 } 997 if (ret < 0) 998 goto err_assert_reset; 999 1000 if (dev->capability & DW_I2S_MASTER) { 1001 if (pdata) { 1002 dev->i2s_clk_cfg = pdata->i2s_clk_cfg; 1003 if (!dev->i2s_clk_cfg) { 1004 dev_err(&pdev->dev, "no clock configure method\n"); 1005 ret = -ENODEV; 1006 goto err_assert_reset; 1007 } 1008 } 1009 dev->clk = devm_clk_get_enabled(&pdev->dev, clk_id); 1010 1011 if (IS_ERR(dev->clk)) { 1012 ret = PTR_ERR(dev->clk); 1013 goto err_assert_reset; 1014 } 1015 } 1016 1017 dev_set_drvdata(&pdev->dev, dev); 1018 ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component, 1019 dw_i2s_dai, 1); 1020 if (ret != 0) { 1021 dev_err(&pdev->dev, "not able to register dai\n"); 1022 goto err_assert_reset; 1023 } 1024 1025 if (!pdata || dev->is_jh7110) { 1026 if (irq >= 0) { 1027 ret = dw_pcm_register(pdev); 1028 dev->use_pio = true; 1029 dev->l_reg = LRBR_LTHR(0); 1030 dev->r_reg = RRBR_RTHR(0); 1031 } else { 1032 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 1033 0); 1034 dev->use_pio = false; 1035 } 1036 1037 if (ret) { 1038 dev_err(&pdev->dev, "could not register pcm: %d\n", 1039 ret); 1040 goto err_assert_reset; 1041 } 1042 } 1043 1044 pm_runtime_enable(&pdev->dev); 1045 return 0; 1046 1047 err_assert_reset: 1048 reset_control_assert(dev->reset); 1049 return ret; 1050 } 1051 1052 static void dw_i2s_remove(struct platform_device *pdev) 1053 { 1054 struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev); 1055 1056 reset_control_assert(dev->reset); 1057 pm_runtime_disable(&pdev->dev); 1058 } 1059 1060 #ifdef CONFIG_OF 1061 static const struct i2s_platform_data jh7110_i2stx0_data = { 1062 .cap = DWC_I2S_PLAY | DW_I2S_MASTER, 1063 .channel = TWO_CHANNEL_SUPPORT, 1064 .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1065 .snd_rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000, 1066 .i2s_clk_cfg = jh7110_i2stx0_clk_cfg, 1067 .i2s_pd_init = jh7110_i2s_crg_master_init, 1068 }; 1069 1070 static const struct i2s_platform_data jh7110_i2stx1_data = { 1071 .cap = DWC_I2S_PLAY | DW_I2S_SLAVE, 1072 .channel = TWO_CHANNEL_SUPPORT, 1073 .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1074 .snd_rates = SNDRV_PCM_RATE_8000_192000, 1075 .i2s_pd_init = jh7110_i2s_crg_slave_init, 1076 }; 1077 1078 static const struct i2s_platform_data jh7110_i2srx_data = { 1079 .cap = DWC_I2S_RECORD | DW_I2S_SLAVE, 1080 .channel = TWO_CHANNEL_SUPPORT, 1081 .snd_fmts = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 1082 .snd_rates = SNDRV_PCM_RATE_8000_192000, 1083 .i2s_pd_init = jh7110_i2srx_crg_init, 1084 }; 1085 1086 static const struct of_device_id dw_i2s_of_match[] = { 1087 { .compatible = "snps,designware-i2s", }, 1088 { .compatible = "starfive,jh7110-i2stx0", .data = &jh7110_i2stx0_data, }, 1089 { .compatible = "starfive,jh7110-i2stx1", .data = &jh7110_i2stx1_data,}, 1090 { .compatible = "starfive,jh7110-i2srx", .data = &jh7110_i2srx_data,}, 1091 {}, 1092 }; 1093 1094 MODULE_DEVICE_TABLE(of, dw_i2s_of_match); 1095 #endif 1096 1097 static const struct dev_pm_ops dwc_pm_ops = { 1098 RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL) 1099 }; 1100 1101 static struct platform_driver dw_i2s_driver = { 1102 .probe = dw_i2s_probe, 1103 .remove = dw_i2s_remove, 1104 .driver = { 1105 .name = "designware-i2s", 1106 .of_match_table = of_match_ptr(dw_i2s_of_match), 1107 .pm = pm_ptr(&dwc_pm_ops), 1108 }, 1109 }; 1110 1111 module_platform_driver(dw_i2s_driver); 1112 1113 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>"); 1114 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface"); 1115 MODULE_LICENSE("GPL"); 1116 MODULE_ALIAS("platform:designware_i2s"); 1117