1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver
4 //
5 // Copyright (C) 2021 Renesas Electronics Corp.
6 // Copyright (C) 2019 Chris Brandt.
7 //
8
9 #include <linux/clk.h>
10 #include <linux/dmaengine.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/module.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
16 #include <sound/soc.h>
17
18 /* REGISTER OFFSET */
19 #define SSICR 0x000
20 #define SSISR 0x004
21 #define SSIFCR 0x010
22 #define SSIFSR 0x014
23 #define SSIFTDR 0x018
24 #define SSIFRDR 0x01c
25 #define SSIOFR 0x020
26 #define SSISCR 0x024
27
28 /* SSI REGISTER BITS */
29 #define SSICR_DWL(x) (((x) & 0x7) << 19)
30 #define SSICR_SWL(x) (((x) & 0x7) << 16)
31
32 #define SSICR_CKS BIT(30)
33 #define SSICR_TUIEN BIT(29)
34 #define SSICR_TOIEN BIT(28)
35 #define SSICR_RUIEN BIT(27)
36 #define SSICR_ROIEN BIT(26)
37 #define SSICR_MST BIT(14)
38 #define SSICR_BCKP BIT(13)
39 #define SSICR_LRCKP BIT(12)
40 #define SSICR_CKDV(x) (((x) & 0xf) << 4)
41 #define SSICR_TEN BIT(1)
42 #define SSICR_REN BIT(0)
43
44 #define SSISR_TUIRQ BIT(29)
45 #define SSISR_TOIRQ BIT(28)
46 #define SSISR_RUIRQ BIT(27)
47 #define SSISR_ROIRQ BIT(26)
48 #define SSISR_IIRQ BIT(25)
49
50 #define SSIFCR_AUCKE BIT(31)
51 #define SSIFCR_SSIRST BIT(16)
52 #define SSIFCR_TIE BIT(3)
53 #define SSIFCR_RIE BIT(2)
54 #define SSIFCR_TFRST BIT(1)
55 #define SSIFCR_RFRST BIT(0)
56 #define SSIFCR_FIFO_RST (SSIFCR_TFRST | SSIFCR_RFRST)
57
58 #define SSIFSR_TDC_MASK 0x3f
59 #define SSIFSR_TDC_SHIFT 24
60 #define SSIFSR_RDC_MASK 0x3f
61 #define SSIFSR_RDC_SHIFT 8
62
63 #define SSIFSR_TDE BIT(16)
64 #define SSIFSR_RDF BIT(0)
65
66 #define SSIOFR_LRCONT BIT(8)
67
68 #define SSISCR_TDES(x) (((x) & 0x1f) << 8)
69 #define SSISCR_RDFS(x) (((x) & 0x1f) << 0)
70
71 /* Pre allocated buffers sizes */
72 #define PREALLOC_BUFFER (SZ_32K)
73 #define PREALLOC_BUFFER_MAX (SZ_32K)
74
75 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-48kHz */
76 #define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE
77 #define SSI_CHAN_MIN 2
78 #define SSI_CHAN_MAX 2
79 #define SSI_FIFO_DEPTH 32
80
81 struct rz_ssi_priv;
82
83 struct rz_ssi_stream {
84 struct rz_ssi_priv *priv;
85 struct snd_pcm_substream *substream;
86 int fifo_sample_size; /* sample capacity of SSI FIFO */
87 int dma_buffer_pos; /* The address for the next DMA descriptor */
88 int completed_dma_buf_pos; /* The address of the last completed DMA descriptor. */
89 int period_counter; /* for keeping track of periods transferred */
90 int sample_width;
91 int buffer_pos; /* current frame position in the buffer */
92 int running; /* 0=stopped, 1=running */
93
94 int uerr_num;
95 int oerr_num;
96
97 struct dma_chan *dma_ch;
98
99 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm);
100 };
101
102 struct rz_ssi_priv {
103 void __iomem *base;
104 struct reset_control *rstc;
105 struct device *dev;
106 struct clk *sfr_clk;
107 struct clk *clk;
108
109 phys_addr_t phys;
110 int irq_int;
111 int irq_tx;
112 int irq_rx;
113 int irq_rt;
114
115 spinlock_t lock;
116
117 /*
118 * The SSI supports full-duplex transmission and reception.
119 * However, if an error occurs, channel reset (both transmission
120 * and reception reset) is required.
121 * So it is better to use as half-duplex (playing and recording
122 * should be done on separate channels).
123 */
124 struct rz_ssi_stream playback;
125 struct rz_ssi_stream capture;
126
127 /* clock */
128 unsigned long audio_mck;
129 unsigned long audio_clk_1;
130 unsigned long audio_clk_2;
131
132 bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */
133 bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */
134 bool dma_rt;
135
136 /* Full duplex communication support */
137 struct {
138 unsigned int rate;
139 unsigned int channels;
140 unsigned int sample_width;
141 unsigned int sample_bits;
142 } hw_params_cache;
143 };
144
145 static void rz_ssi_dma_complete(void *data);
146
rz_ssi_reg_writel(struct rz_ssi_priv * priv,uint reg,u32 data)147 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data)
148 {
149 writel(data, (priv->base + reg));
150 }
151
rz_ssi_reg_readl(struct rz_ssi_priv * priv,uint reg)152 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg)
153 {
154 return readl(priv->base + reg);
155 }
156
rz_ssi_reg_mask_setl(struct rz_ssi_priv * priv,uint reg,u32 bclr,u32 bset)157 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg,
158 u32 bclr, u32 bset)
159 {
160 u32 val;
161
162 val = readl(priv->base + reg);
163 val = (val & ~bclr) | bset;
164 writel(val, (priv->base + reg));
165 }
166
rz_ssi_stream_is_play(struct snd_pcm_substream * substream)167 static inline bool rz_ssi_stream_is_play(struct snd_pcm_substream *substream)
168 {
169 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
170 }
171
172 static inline struct rz_ssi_stream *
rz_ssi_stream_get(struct rz_ssi_priv * ssi,struct snd_pcm_substream * substream)173 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream)
174 {
175 struct rz_ssi_stream *stream = &ssi->playback;
176
177 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
178 stream = &ssi->capture;
179
180 return stream;
181 }
182
rz_ssi_is_dma_enabled(struct rz_ssi_priv * ssi)183 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi)
184 {
185 return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch));
186 }
187
rz_ssi_set_substream(struct rz_ssi_stream * strm,struct snd_pcm_substream * substream)188 static void rz_ssi_set_substream(struct rz_ssi_stream *strm,
189 struct snd_pcm_substream *substream)
190 {
191 struct rz_ssi_priv *ssi = strm->priv;
192
193 guard(spinlock_irqsave)(&ssi->lock);
194
195 strm->substream = substream;
196 }
197
rz_ssi_stream_is_valid(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)198 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi,
199 struct rz_ssi_stream *strm)
200 {
201 guard(spinlock_irqsave)(&ssi->lock);
202
203 return strm->substream && strm->substream->runtime;
204 }
205
rz_ssi_is_stream_running(struct rz_ssi_stream * strm)206 static inline bool rz_ssi_is_stream_running(struct rz_ssi_stream *strm)
207 {
208 return strm->substream && strm->running;
209 }
210
rz_ssi_stream_init(struct rz_ssi_stream * strm,struct snd_pcm_substream * substream)211 static void rz_ssi_stream_init(struct rz_ssi_stream *strm,
212 struct snd_pcm_substream *substream)
213 {
214 struct snd_pcm_runtime *runtime = substream->runtime;
215
216 rz_ssi_set_substream(strm, substream);
217 strm->sample_width = samples_to_bytes(runtime, 1);
218 strm->dma_buffer_pos = 0;
219 strm->completed_dma_buf_pos = 0;
220 strm->period_counter = 0;
221 strm->buffer_pos = 0;
222
223 strm->oerr_num = 0;
224 strm->uerr_num = 0;
225 strm->running = 0;
226
227 /* fifo init */
228 strm->fifo_sample_size = SSI_FIFO_DEPTH;
229 }
230
rz_ssi_stream_quit(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)231 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi,
232 struct rz_ssi_stream *strm)
233 {
234 struct device *dev = ssi->dev;
235
236 rz_ssi_set_substream(strm, NULL);
237
238 if (strm->oerr_num > 0)
239 dev_info(dev, "overrun = %d\n", strm->oerr_num);
240
241 if (strm->uerr_num > 0)
242 dev_info(dev, "underrun = %d\n", strm->uerr_num);
243 }
244
rz_ssi_clk_setup(struct rz_ssi_priv * ssi,unsigned int rate,unsigned int channels)245 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate,
246 unsigned int channels)
247 {
248 static u8 ckdv[] = { 1, 2, 4, 8, 16, 32, 64, 128, 6, 12, 24, 48, 96 };
249 unsigned int channel_bits = 32; /* System Word Length */
250 unsigned long bclk_rate = rate * channels * channel_bits;
251 unsigned int div;
252 unsigned int i;
253 u32 ssicr = 0;
254 u32 clk_ckdv;
255
256 /* Clear AUCKE so we can set MST */
257 rz_ssi_reg_writel(ssi, SSIFCR, 0);
258
259 /* Continue to output LRCK pin even when idle */
260 rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT);
261 if (ssi->audio_clk_1 && ssi->audio_clk_2) {
262 if (ssi->audio_clk_1 % bclk_rate)
263 ssi->audio_mck = ssi->audio_clk_2;
264 else
265 ssi->audio_mck = ssi->audio_clk_1;
266 }
267
268 /* Clock setting */
269 ssicr |= SSICR_MST;
270 if (ssi->audio_mck == ssi->audio_clk_1)
271 ssicr |= SSICR_CKS;
272 if (ssi->bckp_rise)
273 ssicr |= SSICR_BCKP;
274 if (ssi->lrckp_fsync_fall)
275 ssicr |= SSICR_LRCKP;
276
277 /* Determine the clock divider */
278 clk_ckdv = 0;
279 div = ssi->audio_mck / bclk_rate;
280 /* try to find an match */
281 for (i = 0; i < ARRAY_SIZE(ckdv); i++) {
282 if (ckdv[i] == div) {
283 clk_ckdv = i;
284 break;
285 }
286 }
287
288 if (i == ARRAY_SIZE(ckdv)) {
289 dev_err(ssi->dev, "Rate not divisible by audio clock source\n");
290 return -EINVAL;
291 }
292
293 /*
294 * DWL: Data Word Length = 16 bits
295 * SWL: System Word Length = 32 bits
296 */
297 ssicr |= SSICR_CKDV(clk_ckdv);
298 ssicr |= SSICR_DWL(1) | SSICR_SWL(3);
299 rz_ssi_reg_writel(ssi, SSICR, ssicr);
300 rz_ssi_reg_writel(ssi, SSIFCR, SSIFCR_AUCKE | SSIFCR_FIFO_RST);
301
302 return 0;
303 }
304
rz_ssi_set_idle(struct rz_ssi_priv * ssi)305 static void rz_ssi_set_idle(struct rz_ssi_priv *ssi)
306 {
307 u32 tmp;
308 int ret;
309
310 /* Disable irqs */
311 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN |
312 SSICR_RUIEN | SSICR_ROIEN, 0);
313 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0);
314
315 /* Clear all error flags */
316 rz_ssi_reg_mask_setl(ssi, SSISR,
317 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
318 SSISR_RUIRQ), 0);
319
320 /* Wait for idle */
321 ret = readl_poll_timeout_atomic(ssi->base + SSISR, tmp, (tmp & SSISR_IIRQ), 1, 100);
322 if (ret)
323 dev_warn_ratelimited(ssi->dev, "timeout waiting for SSI idle\n");
324
325 /* Hold FIFOs in reset */
326 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_FIFO_RST);
327 }
328
rz_ssi_start(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)329 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
330 {
331 bool is_play = rz_ssi_stream_is_play(strm->substream);
332 bool is_full_duplex;
333 u32 ssicr, ssifcr;
334
335 is_full_duplex = rz_ssi_is_stream_running(&ssi->playback) ||
336 rz_ssi_is_stream_running(&ssi->capture);
337 ssicr = rz_ssi_reg_readl(ssi, SSICR);
338 ssifcr = rz_ssi_reg_readl(ssi, SSIFCR);
339 if (!is_full_duplex) {
340 ssifcr &= ~0xF;
341 } else {
342 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0);
343 rz_ssi_set_idle(ssi);
344 ssifcr &= ~SSIFCR_FIFO_RST;
345 }
346
347 /* FIFO interrupt thresholds */
348 if (rz_ssi_is_dma_enabled(ssi))
349 rz_ssi_reg_writel(ssi, SSISCR, 0);
350 else
351 rz_ssi_reg_writel(ssi, SSISCR,
352 SSISCR_TDES(strm->fifo_sample_size / 2 - 1) |
353 SSISCR_RDFS(0));
354
355 /* enable IRQ */
356 if (is_play) {
357 ssicr |= SSICR_TUIEN | SSICR_TOIEN;
358 ssifcr |= SSIFCR_TIE;
359 if (!is_full_duplex)
360 ssifcr |= SSIFCR_RFRST;
361 } else {
362 ssicr |= SSICR_RUIEN | SSICR_ROIEN;
363 ssifcr |= SSIFCR_RIE;
364 if (!is_full_duplex)
365 ssifcr |= SSIFCR_TFRST;
366 }
367
368 rz_ssi_reg_writel(ssi, SSICR, ssicr);
369 rz_ssi_reg_writel(ssi, SSIFCR, ssifcr);
370
371 /* Clear all error flags */
372 rz_ssi_reg_mask_setl(ssi, SSISR,
373 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ |
374 SSISR_RUIRQ), 0);
375
376 strm->running = 1;
377 if (is_full_duplex)
378 ssicr |= SSICR_TEN | SSICR_REN;
379 else
380 ssicr |= is_play ? SSICR_TEN : SSICR_REN;
381
382 rz_ssi_reg_writel(ssi, SSICR, ssicr);
383
384 return 0;
385 }
386
rz_ssi_swreset(struct rz_ssi_priv * ssi)387 static int rz_ssi_swreset(struct rz_ssi_priv *ssi)
388 {
389 u32 tmp;
390
391 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST);
392 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0);
393 return readl_poll_timeout_atomic(ssi->base + SSIFCR, tmp, !(tmp & SSIFCR_SSIRST), 1, 5);
394 }
395
rz_ssi_stop(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)396 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
397 {
398 strm->running = 0;
399
400 if (rz_ssi_is_stream_running(&ssi->playback) ||
401 rz_ssi_is_stream_running(&ssi->capture))
402 return 0;
403
404 /* Disable TX/RX */
405 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0);
406
407 /* Cancel all remaining DMA transactions */
408 if (rz_ssi_is_dma_enabled(ssi)) {
409 if (ssi->playback.dma_ch)
410 dmaengine_terminate_async(ssi->playback.dma_ch);
411 if (ssi->capture.dma_ch)
412 dmaengine_terminate_async(ssi->capture.dma_ch);
413 }
414
415 rz_ssi_set_idle(ssi);
416
417 return 0;
418 }
419
rz_ssi_pointer_update(struct rz_ssi_stream * strm,int frames)420 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames)
421 {
422 struct snd_pcm_substream *substream = strm->substream;
423 struct snd_pcm_runtime *runtime;
424 int current_period;
425
426 if (!strm->running || !substream || !substream->runtime)
427 return;
428
429 runtime = substream->runtime;
430 strm->buffer_pos += frames;
431 WARN_ON(strm->buffer_pos > runtime->buffer_size);
432
433 /* ring buffer */
434 if (strm->buffer_pos == runtime->buffer_size)
435 strm->buffer_pos = 0;
436
437 current_period = strm->buffer_pos / runtime->period_size;
438 if (strm->period_counter != current_period) {
439 snd_pcm_period_elapsed(strm->substream);
440 strm->period_counter = current_period;
441 }
442
443 strm->completed_dma_buf_pos += runtime->period_size;
444 if (strm->completed_dma_buf_pos >= runtime->buffer_size)
445 strm->completed_dma_buf_pos = 0;
446 }
447
rz_ssi_pio_recv(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)448 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
449 {
450 struct snd_pcm_substream *substream = strm->substream;
451 struct snd_pcm_runtime *runtime;
452 u16 *buf;
453 int fifo_samples;
454 int frames_left;
455 int samples;
456 int i;
457
458 if (!rz_ssi_stream_is_valid(ssi, strm))
459 return -EINVAL;
460
461 runtime = substream->runtime;
462
463 do {
464 /* frames left in this period */
465 frames_left = runtime->period_size -
466 (strm->buffer_pos % runtime->period_size);
467 if (!frames_left)
468 frames_left = runtime->period_size;
469
470 /* Samples in RX FIFO */
471 fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >>
472 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK;
473
474 /* Only read full frames at a time */
475 samples = 0;
476 while (frames_left && (fifo_samples >= runtime->channels)) {
477 samples += runtime->channels;
478 fifo_samples -= runtime->channels;
479 frames_left--;
480 }
481
482 /* not enough samples yet */
483 if (!samples)
484 break;
485
486 /* calculate new buffer index */
487 buf = (u16 *)runtime->dma_area;
488 buf += strm->buffer_pos * runtime->channels;
489
490 /* Note, only supports 16-bit samples */
491 for (i = 0; i < samples; i++)
492 *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16);
493
494 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
495 rz_ssi_pointer_update(strm, samples / runtime->channels);
496 } while (!frames_left && fifo_samples >= runtime->channels);
497
498 return 0;
499 }
500
rz_ssi_pio_send(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)501 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
502 {
503 struct snd_pcm_substream *substream = strm->substream;
504 struct snd_pcm_runtime *runtime = substream->runtime;
505 int sample_space;
506 int samples = 0;
507 int frames_left;
508 int i;
509 u32 ssifsr;
510 u16 *buf;
511
512 if (!rz_ssi_stream_is_valid(ssi, strm))
513 return -EINVAL;
514
515 /* frames left in this period */
516 frames_left = runtime->period_size - (strm->buffer_pos %
517 runtime->period_size);
518 if (frames_left == 0)
519 frames_left = runtime->period_size;
520
521 sample_space = strm->fifo_sample_size;
522 ssifsr = rz_ssi_reg_readl(ssi, SSIFSR);
523 sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK;
524 if (sample_space < 0)
525 return -EINVAL;
526
527 /* Only add full frames at a time */
528 while (frames_left && (sample_space >= runtime->channels)) {
529 samples += runtime->channels;
530 sample_space -= runtime->channels;
531 frames_left--;
532 }
533
534 /* no space to send anything right now */
535 if (samples == 0)
536 return 0;
537
538 /* calculate new buffer index */
539 buf = (u16 *)(runtime->dma_area);
540 buf += strm->buffer_pos * runtime->channels;
541
542 /* Note, only supports 16-bit samples */
543 for (i = 0; i < samples; i++)
544 rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16));
545
546 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0);
547 rz_ssi_pointer_update(strm, samples / runtime->channels);
548
549 return 0;
550 }
551
rz_ssi_interrupt(int irq,void * data)552 static irqreturn_t rz_ssi_interrupt(int irq, void *data)
553 {
554 struct rz_ssi_stream *strm_playback = NULL;
555 struct rz_ssi_stream *strm_capture = NULL;
556 struct rz_ssi_priv *ssi = data;
557 u32 ssisr = rz_ssi_reg_readl(ssi, SSISR);
558
559 if (ssi->playback.substream)
560 strm_playback = &ssi->playback;
561 if (ssi->capture.substream)
562 strm_capture = &ssi->capture;
563
564 if (!strm_playback && !strm_capture)
565 return IRQ_HANDLED; /* Left over TX/RX interrupt */
566
567 if (irq == ssi->irq_int) { /* error or idle */
568 bool is_stopped = false;
569 int i, count;
570
571 if (rz_ssi_is_dma_enabled(ssi))
572 count = 4;
573 else
574 count = 1;
575
576 if (ssisr & (SSISR_RUIRQ | SSISR_ROIRQ | SSISR_TUIRQ | SSISR_TOIRQ))
577 is_stopped = true;
578
579 if (ssi->capture.substream && is_stopped) {
580 if (ssisr & SSISR_RUIRQ)
581 strm_capture->uerr_num++;
582 if (ssisr & SSISR_ROIRQ)
583 strm_capture->oerr_num++;
584
585 rz_ssi_stop(ssi, strm_capture);
586 }
587
588 if (ssi->playback.substream && is_stopped) {
589 if (ssisr & SSISR_TUIRQ)
590 strm_playback->uerr_num++;
591 if (ssisr & SSISR_TOIRQ)
592 strm_playback->oerr_num++;
593
594 rz_ssi_stop(ssi, strm_playback);
595 }
596
597 /* Clear all flags */
598 rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ | SSISR_TUIRQ |
599 SSISR_ROIRQ | SSISR_RUIRQ, 0);
600
601 /* Add/remove more data */
602 if (ssi->capture.substream && is_stopped) {
603 for (i = 0; i < count; i++)
604 strm_capture->transfer(ssi, strm_capture);
605 }
606
607 if (ssi->playback.substream && is_stopped) {
608 for (i = 0; i < count; i++)
609 strm_playback->transfer(ssi, strm_playback);
610 }
611
612 /* Resume */
613 if (ssi->playback.substream && is_stopped)
614 rz_ssi_start(ssi, &ssi->playback);
615 if (ssi->capture.substream && is_stopped)
616 rz_ssi_start(ssi, &ssi->capture);
617 }
618
619 if (!rz_ssi_is_stream_running(&ssi->playback) &&
620 !rz_ssi_is_stream_running(&ssi->capture))
621 return IRQ_HANDLED;
622
623 /* tx data empty */
624 if (irq == ssi->irq_tx && rz_ssi_is_stream_running(&ssi->playback))
625 strm_playback->transfer(ssi, &ssi->playback);
626
627 /* rx data full */
628 if (irq == ssi->irq_rx && rz_ssi_is_stream_running(&ssi->capture)) {
629 strm_capture->transfer(ssi, &ssi->capture);
630 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
631 }
632
633 if (irq == ssi->irq_rt) {
634 if (ssi->playback.substream) {
635 strm_playback->transfer(ssi, &ssi->playback);
636 } else {
637 strm_capture->transfer(ssi, &ssi->capture);
638 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0);
639 }
640 }
641
642 return IRQ_HANDLED;
643 }
644
rz_ssi_dma_slave_config(struct rz_ssi_priv * ssi,struct dma_chan * dma_ch,bool is_play)645 static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi,
646 struct dma_chan *dma_ch, bool is_play)
647 {
648 struct dma_slave_config cfg;
649
650 memset(&cfg, 0, sizeof(cfg));
651
652 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
653 cfg.dst_addr = ssi->phys + SSIFTDR;
654 cfg.src_addr = ssi->phys + SSIFRDR;
655 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
656 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
657
658 return dmaengine_slave_config(dma_ch, &cfg);
659 }
660
rz_ssi_dma_transfer(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)661 static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi,
662 struct rz_ssi_stream *strm)
663 {
664 struct snd_pcm_substream *substream = strm->substream;
665 struct dma_async_tx_descriptor *desc;
666 struct snd_pcm_runtime *runtime;
667 enum dma_transfer_direction dir;
668 u32 dma_paddr, dma_size;
669 int amount;
670
671 if (!rz_ssi_stream_is_valid(ssi, strm))
672 return -EINVAL;
673
674 runtime = substream->runtime;
675 if (runtime->state == SNDRV_PCM_STATE_DRAINING)
676 /*
677 * Stream is ending, so do not queue up any more DMA
678 * transfers otherwise we play partial sound clips
679 * because we can't shut off the DMA quick enough.
680 */
681 return 0;
682
683 dir = rz_ssi_stream_is_play(substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
684
685 /* Always transfer 1 period */
686 amount = runtime->period_size;
687
688 /* DMA physical address and size */
689 dma_paddr = runtime->dma_addr + frames_to_bytes(runtime,
690 strm->dma_buffer_pos);
691 dma_size = frames_to_bytes(runtime, amount);
692 desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size,
693 dir,
694 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
695 if (!desc) {
696 dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n");
697 return -ENOMEM;
698 }
699
700 desc->callback = rz_ssi_dma_complete;
701 desc->callback_param = strm;
702
703 if (dmaengine_submit(desc) < 0) {
704 dev_err(ssi->dev, "dmaengine_submit() fail\n");
705 return -EIO;
706 }
707
708 /* Update DMA pointer */
709 strm->dma_buffer_pos += amount;
710 if (strm->dma_buffer_pos >= runtime->buffer_size)
711 strm->dma_buffer_pos = 0;
712
713 /* Start DMA */
714 dma_async_issue_pending(strm->dma_ch);
715
716 return 0;
717 }
718
rz_ssi_dma_complete(void * data)719 static void rz_ssi_dma_complete(void *data)
720 {
721 struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data;
722
723 if (!strm->running || !strm->substream || !strm->substream->runtime)
724 return;
725
726 /* Note that next DMA transaction has probably already started */
727 rz_ssi_pointer_update(strm, strm->substream->runtime->period_size);
728
729 /* Queue up another DMA transaction */
730 rz_ssi_dma_transfer(strm->priv, strm);
731 }
732
rz_ssi_release_dma_channels(struct rz_ssi_priv * ssi)733 static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi)
734 {
735 if (ssi->playback.dma_ch) {
736 dma_release_channel(ssi->playback.dma_ch);
737 ssi->playback.dma_ch = NULL;
738 if (ssi->dma_rt)
739 ssi->dma_rt = false;
740 }
741
742 if (ssi->capture.dma_ch) {
743 dma_release_channel(ssi->capture.dma_ch);
744 ssi->capture.dma_ch = NULL;
745 }
746 }
747
rz_ssi_dma_request(struct rz_ssi_priv * ssi,struct device * dev)748 static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev)
749 {
750 ssi->playback.dma_ch = dma_request_chan(dev, "tx");
751 if (IS_ERR(ssi->playback.dma_ch))
752 ssi->playback.dma_ch = NULL;
753
754 ssi->capture.dma_ch = dma_request_chan(dev, "rx");
755 if (IS_ERR(ssi->capture.dma_ch))
756 ssi->capture.dma_ch = NULL;
757
758 if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) {
759 ssi->playback.dma_ch = dma_request_chan(dev, "rt");
760 if (IS_ERR(ssi->playback.dma_ch)) {
761 ssi->playback.dma_ch = NULL;
762 goto no_dma;
763 }
764
765 ssi->dma_rt = true;
766 }
767
768 if (!rz_ssi_is_dma_enabled(ssi))
769 goto no_dma;
770
771 if (ssi->playback.dma_ch &&
772 (rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0))
773 goto no_dma;
774
775 if (ssi->capture.dma_ch &&
776 (rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0))
777 goto no_dma;
778
779 return 0;
780
781 no_dma:
782 rz_ssi_release_dma_channels(ssi);
783
784 return -ENODEV;
785 }
786
rz_ssi_trigger_resume(struct rz_ssi_priv * ssi,struct rz_ssi_stream * strm)787 static int rz_ssi_trigger_resume(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm)
788 {
789 struct snd_pcm_substream *substream = strm->substream;
790 struct snd_pcm_runtime *runtime = substream->runtime;
791 int ret;
792
793 strm->dma_buffer_pos = strm->completed_dma_buf_pos + runtime->period_size;
794
795 if (rz_ssi_is_stream_running(&ssi->playback) ||
796 rz_ssi_is_stream_running(&ssi->capture))
797 return 0;
798
799 ret = rz_ssi_swreset(ssi);
800 if (ret)
801 return ret;
802
803 return rz_ssi_clk_setup(ssi, ssi->hw_params_cache.rate,
804 ssi->hw_params_cache.channels);
805 }
806
rz_ssi_dai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)807 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
808 struct snd_soc_dai *dai)
809 {
810 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
811 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
812 int ret = 0, i, num_transfer = 1;
813
814 switch (cmd) {
815 case SNDRV_PCM_TRIGGER_RESUME:
816 ret = rz_ssi_trigger_resume(ssi, strm);
817 if (ret)
818 return ret;
819
820 fallthrough;
821
822 case SNDRV_PCM_TRIGGER_START:
823 if (cmd == SNDRV_PCM_TRIGGER_START)
824 rz_ssi_stream_init(strm, substream);
825
826 if (ssi->dma_rt) {
827 bool is_playback;
828
829 is_playback = rz_ssi_stream_is_play(substream);
830 ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch,
831 is_playback);
832 /* Fallback to pio */
833 if (ret < 0) {
834 ssi->playback.transfer = rz_ssi_pio_send;
835 ssi->capture.transfer = rz_ssi_pio_recv;
836 rz_ssi_release_dma_channels(ssi);
837 }
838 }
839
840 /* For DMA, queue up multiple DMA descriptors */
841 if (rz_ssi_is_dma_enabled(ssi))
842 num_transfer = 4;
843
844 for (i = 0; i < num_transfer; i++) {
845 ret = strm->transfer(ssi, strm);
846 if (ret)
847 goto done;
848 }
849
850 ret = rz_ssi_start(ssi, strm);
851 break;
852
853 case SNDRV_PCM_TRIGGER_SUSPEND:
854 rz_ssi_stop(ssi, strm);
855 break;
856
857 case SNDRV_PCM_TRIGGER_STOP:
858 rz_ssi_stop(ssi, strm);
859 rz_ssi_stream_quit(ssi, strm);
860 break;
861 }
862
863 done:
864 return ret;
865 }
866
rz_ssi_dai_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)867 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
868 {
869 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
870
871 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
872 case SND_SOC_DAIFMT_BP_FP:
873 break;
874 default:
875 dev_err(ssi->dev, "Codec should be clk and frame consumer\n");
876 return -EINVAL;
877 }
878
879 /*
880 * set clock polarity
881 *
882 * "normal" BCLK = Signal is available at rising edge of BCLK
883 * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge
884 */
885 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
886 case SND_SOC_DAIFMT_NB_NF:
887 ssi->bckp_rise = false;
888 ssi->lrckp_fsync_fall = false;
889 break;
890 case SND_SOC_DAIFMT_NB_IF:
891 ssi->bckp_rise = false;
892 ssi->lrckp_fsync_fall = true;
893 break;
894 case SND_SOC_DAIFMT_IB_NF:
895 ssi->bckp_rise = true;
896 ssi->lrckp_fsync_fall = false;
897 break;
898 case SND_SOC_DAIFMT_IB_IF:
899 ssi->bckp_rise = true;
900 ssi->lrckp_fsync_fall = true;
901 break;
902 default:
903 return -EINVAL;
904 }
905
906 /* only i2s support */
907 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
908 case SND_SOC_DAIFMT_I2S:
909 break;
910 default:
911 dev_err(ssi->dev, "Only I2S mode is supported.\n");
912 return -EINVAL;
913 }
914
915 return 0;
916 }
917
rz_ssi_is_valid_hw_params(struct rz_ssi_priv * ssi,unsigned int rate,unsigned int channels,unsigned int sample_width,unsigned int sample_bits)918 static bool rz_ssi_is_valid_hw_params(struct rz_ssi_priv *ssi, unsigned int rate,
919 unsigned int channels,
920 unsigned int sample_width,
921 unsigned int sample_bits)
922 {
923 if (ssi->hw_params_cache.rate != rate ||
924 ssi->hw_params_cache.channels != channels ||
925 ssi->hw_params_cache.sample_width != sample_width ||
926 ssi->hw_params_cache.sample_bits != sample_bits)
927 return false;
928
929 return true;
930 }
931
rz_ssi_cache_hw_params(struct rz_ssi_priv * ssi,unsigned int rate,unsigned int channels,unsigned int sample_width,unsigned int sample_bits)932 static void rz_ssi_cache_hw_params(struct rz_ssi_priv *ssi, unsigned int rate,
933 unsigned int channels,
934 unsigned int sample_width,
935 unsigned int sample_bits)
936 {
937 ssi->hw_params_cache.rate = rate;
938 ssi->hw_params_cache.channels = channels;
939 ssi->hw_params_cache.sample_width = sample_width;
940 ssi->hw_params_cache.sample_bits = sample_bits;
941 }
942
rz_ssi_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)943 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream,
944 struct snd_pcm_hw_params *params,
945 struct snd_soc_dai *dai)
946 {
947 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
948 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
949 unsigned int sample_bits = hw_param_interval(params,
950 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
951 unsigned int channels = params_channels(params);
952 unsigned int rate = params_rate(params);
953 int ret;
954
955 if (sample_bits != 16) {
956 dev_err(ssi->dev, "Unsupported sample width: %d\n",
957 sample_bits);
958 return -EINVAL;
959 }
960
961 if (channels != 2) {
962 dev_err(ssi->dev, "Number of channels not matched: %d\n",
963 channels);
964 return -EINVAL;
965 }
966
967 if (rz_ssi_is_stream_running(&ssi->playback) ||
968 rz_ssi_is_stream_running(&ssi->capture)) {
969 if (rz_ssi_is_valid_hw_params(ssi, rate, channels,
970 strm->sample_width, sample_bits))
971 return 0;
972
973 dev_err(ssi->dev, "Full duplex needs same HW params\n");
974 return -EINVAL;
975 }
976
977 rz_ssi_cache_hw_params(ssi, rate, channels, strm->sample_width,
978 sample_bits);
979
980 ret = rz_ssi_swreset(ssi);
981 if (ret)
982 return ret;
983
984 return rz_ssi_clk_setup(ssi, rate, channels);
985 }
986
987 static const struct snd_soc_dai_ops rz_ssi_dai_ops = {
988 .trigger = rz_ssi_dai_trigger,
989 .set_fmt = rz_ssi_dai_set_fmt,
990 .hw_params = rz_ssi_dai_hw_params,
991 };
992
993 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = {
994 .info = SNDRV_PCM_INFO_INTERLEAVED |
995 SNDRV_PCM_INFO_MMAP |
996 SNDRV_PCM_INFO_MMAP_VALID |
997 SNDRV_PCM_INFO_RESUME,
998 .buffer_bytes_max = PREALLOC_BUFFER,
999 .period_bytes_min = 32,
1000 .period_bytes_max = 8192,
1001 .channels_min = SSI_CHAN_MIN,
1002 .channels_max = SSI_CHAN_MAX,
1003 .periods_min = 1,
1004 .periods_max = 32,
1005 .fifo_size = 32 * 2,
1006 };
1007
rz_ssi_pcm_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)1008 static int rz_ssi_pcm_open(struct snd_soc_component *component,
1009 struct snd_pcm_substream *substream)
1010 {
1011 snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware);
1012
1013 return snd_pcm_hw_constraint_integer(substream->runtime,
1014 SNDRV_PCM_HW_PARAM_PERIODS);
1015 }
1016
rz_ssi_pcm_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)1017 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component,
1018 struct snd_pcm_substream *substream)
1019 {
1020 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1021 struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0);
1022 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai);
1023 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream);
1024
1025 return strm->buffer_pos;
1026 }
1027
rz_ssi_pcm_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)1028 static int rz_ssi_pcm_new(struct snd_soc_component *component,
1029 struct snd_soc_pcm_runtime *rtd)
1030 {
1031 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
1032 rtd->card->snd_card->dev,
1033 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1034 return 0;
1035 }
1036
1037 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = {
1038 {
1039 .name = "rz-ssi-dai",
1040 .playback = {
1041 .rates = SSI_RATES,
1042 .formats = SSI_FMTS,
1043 .channels_min = SSI_CHAN_MIN,
1044 .channels_max = SSI_CHAN_MAX,
1045 },
1046 .capture = {
1047 .rates = SSI_RATES,
1048 .formats = SSI_FMTS,
1049 .channels_min = SSI_CHAN_MIN,
1050 .channels_max = SSI_CHAN_MAX,
1051 },
1052 .ops = &rz_ssi_dai_ops,
1053 },
1054 };
1055
1056 static const struct snd_soc_component_driver rz_ssi_soc_component = {
1057 .name = "rz-ssi",
1058 .open = rz_ssi_pcm_open,
1059 .pointer = rz_ssi_pcm_pointer,
1060 .pcm_construct = rz_ssi_pcm_new,
1061 .legacy_dai_naming = 1,
1062 };
1063
rz_ssi_probe(struct platform_device * pdev)1064 static int rz_ssi_probe(struct platform_device *pdev)
1065 {
1066 struct device *dev = &pdev->dev;
1067 struct rz_ssi_priv *ssi;
1068 struct clk *audio_clk;
1069 struct resource *res;
1070 int ret;
1071
1072 ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL);
1073 if (!ssi)
1074 return -ENOMEM;
1075
1076 ssi->dev = dev;
1077 ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1078 if (IS_ERR(ssi->base))
1079 return PTR_ERR(ssi->base);
1080
1081 ssi->phys = res->start;
1082 ssi->clk = devm_clk_get(dev, "ssi");
1083 if (IS_ERR(ssi->clk))
1084 return PTR_ERR(ssi->clk);
1085
1086 ssi->sfr_clk = devm_clk_get(dev, "ssi_sfr");
1087 if (IS_ERR(ssi->sfr_clk))
1088 return PTR_ERR(ssi->sfr_clk);
1089
1090 audio_clk = devm_clk_get(dev, "audio_clk1");
1091 if (IS_ERR(audio_clk))
1092 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk),
1093 "no audio clk1");
1094
1095 ssi->audio_clk_1 = clk_get_rate(audio_clk);
1096 audio_clk = devm_clk_get(dev, "audio_clk2");
1097 if (IS_ERR(audio_clk))
1098 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk),
1099 "no audio clk2");
1100
1101 ssi->audio_clk_2 = clk_get_rate(audio_clk);
1102 if (!(ssi->audio_clk_1 || ssi->audio_clk_2))
1103 return dev_err_probe(&pdev->dev, -EINVAL,
1104 "no audio clk1 or audio clk2");
1105
1106 ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2;
1107
1108 /* Detect DMA support */
1109 ret = rz_ssi_dma_request(ssi, dev);
1110 if (ret < 0) {
1111 dev_warn(dev, "DMA not available, using PIO\n");
1112 ssi->playback.transfer = rz_ssi_pio_send;
1113 ssi->capture.transfer = rz_ssi_pio_recv;
1114 } else {
1115 dev_info(dev, "DMA enabled");
1116 ssi->playback.transfer = rz_ssi_dma_transfer;
1117 ssi->capture.transfer = rz_ssi_dma_transfer;
1118 }
1119
1120 ssi->playback.priv = ssi;
1121 ssi->capture.priv = ssi;
1122
1123 spin_lock_init(&ssi->lock);
1124 dev_set_drvdata(dev, ssi);
1125
1126 /* Error Interrupt */
1127 ssi->irq_int = platform_get_irq_byname(pdev, "int_req");
1128 if (ssi->irq_int < 0) {
1129 ret = ssi->irq_int;
1130 goto err_release_dma_chs;
1131 }
1132
1133 ret = devm_request_irq(dev, ssi->irq_int, &rz_ssi_interrupt,
1134 0, dev_name(dev), ssi);
1135 if (ret < 0) {
1136 dev_err_probe(dev, ret, "irq request error (int_req)\n");
1137 goto err_release_dma_chs;
1138 }
1139
1140 if (!rz_ssi_is_dma_enabled(ssi)) {
1141 /* Tx and Rx interrupts (pio only) */
1142 ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx");
1143 ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx");
1144 if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) {
1145 ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt");
1146 if (ssi->irq_rt < 0)
1147 return ssi->irq_rt;
1148
1149 ret = devm_request_irq(dev, ssi->irq_rt,
1150 &rz_ssi_interrupt, 0,
1151 dev_name(dev), ssi);
1152 if (ret < 0)
1153 return dev_err_probe(dev, ret,
1154 "irq request error (dma_rt)\n");
1155 } else {
1156 if (ssi->irq_tx < 0)
1157 return ssi->irq_tx;
1158
1159 if (ssi->irq_rx < 0)
1160 return ssi->irq_rx;
1161
1162 ret = devm_request_irq(dev, ssi->irq_tx,
1163 &rz_ssi_interrupt, 0,
1164 dev_name(dev), ssi);
1165 if (ret < 0)
1166 return dev_err_probe(dev, ret,
1167 "irq request error (dma_tx)\n");
1168
1169 ret = devm_request_irq(dev, ssi->irq_rx,
1170 &rz_ssi_interrupt, 0,
1171 dev_name(dev), ssi);
1172 if (ret < 0)
1173 return dev_err_probe(dev, ret,
1174 "irq request error (dma_rx)\n");
1175 }
1176 }
1177
1178 ssi->rstc = devm_reset_control_get_exclusive(dev, NULL);
1179 if (IS_ERR(ssi->rstc)) {
1180 ret = PTR_ERR(ssi->rstc);
1181 goto err_release_dma_chs;
1182 }
1183
1184 /* Default 0 for power saving. Can be overridden via sysfs. */
1185 pm_runtime_set_autosuspend_delay(dev, 0);
1186 pm_runtime_use_autosuspend(dev);
1187 ret = devm_pm_runtime_enable(dev);
1188 if (ret < 0) {
1189 dev_err(dev, "Failed to enable runtime PM!\n");
1190 goto err_release_dma_chs;
1191 }
1192
1193 ret = devm_snd_soc_register_component(dev, &rz_ssi_soc_component,
1194 rz_ssi_soc_dai,
1195 ARRAY_SIZE(rz_ssi_soc_dai));
1196 if (ret < 0) {
1197 dev_err(dev, "failed to register snd component\n");
1198 goto err_release_dma_chs;
1199 }
1200
1201 return 0;
1202
1203 err_release_dma_chs:
1204 rz_ssi_release_dma_channels(ssi);
1205
1206 return ret;
1207 }
1208
rz_ssi_remove(struct platform_device * pdev)1209 static void rz_ssi_remove(struct platform_device *pdev)
1210 {
1211 struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev);
1212
1213 rz_ssi_release_dma_channels(ssi);
1214
1215 reset_control_assert(ssi->rstc);
1216 }
1217
1218 static const struct of_device_id rz_ssi_of_match[] = {
1219 { .compatible = "renesas,rz-ssi", },
1220 {/* Sentinel */},
1221 };
1222 MODULE_DEVICE_TABLE(of, rz_ssi_of_match);
1223
rz_ssi_runtime_suspend(struct device * dev)1224 static int rz_ssi_runtime_suspend(struct device *dev)
1225 {
1226 struct rz_ssi_priv *ssi = dev_get_drvdata(dev);
1227
1228 return reset_control_assert(ssi->rstc);
1229 }
1230
rz_ssi_runtime_resume(struct device * dev)1231 static int rz_ssi_runtime_resume(struct device *dev)
1232 {
1233 struct rz_ssi_priv *ssi = dev_get_drvdata(dev);
1234
1235 return reset_control_deassert(ssi->rstc);
1236 }
1237
1238 static const struct dev_pm_ops rz_ssi_pm_ops = {
1239 RUNTIME_PM_OPS(rz_ssi_runtime_suspend, rz_ssi_runtime_resume, NULL)
1240 NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1241 };
1242
1243 static struct platform_driver rz_ssi_driver = {
1244 .driver = {
1245 .name = "rz-ssi-pcm-audio",
1246 .of_match_table = rz_ssi_of_match,
1247 .pm = pm_ptr(&rz_ssi_pm_ops),
1248 },
1249 .probe = rz_ssi_probe,
1250 .remove = rz_ssi_remove,
1251 };
1252
1253 module_platform_driver(rz_ssi_driver);
1254
1255 MODULE_LICENSE("GPL v2");
1256 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver");
1257 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
1258