1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
3 #include "main.h"
4
5 /**
6 * irdma_query_device - get device attributes
7 * @ibdev: device pointer from stack
8 * @props: returning device attributes
9 * @udata: user data
10 */
irdma_query_device(struct ib_device * ibdev,struct ib_device_attr * props,struct ib_udata * udata)11 static int irdma_query_device(struct ib_device *ibdev,
12 struct ib_device_attr *props,
13 struct ib_udata *udata)
14 {
15 struct irdma_device *iwdev = to_iwdev(ibdev);
16 struct irdma_pci_f *rf = iwdev->rf;
17 struct pci_dev *pcidev = iwdev->rf->pcidev;
18 struct irdma_hw_attrs *hw_attrs = &rf->sc_dev.hw_attrs;
19 int err;
20
21 err = ib_no_udata_io(udata);
22 if (err)
23 return err;
24
25 addrconf_addr_eui48((u8 *)&props->sys_image_guid,
26 iwdev->netdev->dev_addr);
27 props->fw_ver = (u64)irdma_fw_major_ver(&rf->sc_dev) << 32 |
28 irdma_fw_minor_ver(&rf->sc_dev);
29 props->device_cap_flags = IB_DEVICE_MEM_WINDOW |
30 IB_DEVICE_MEM_MGT_EXTENSIONS;
31 if (hw_attrs->uk_attrs.hw_rev < IRDMA_GEN_3)
32 props->kernel_cap_flags = IBK_LOCAL_DMA_LKEY;
33 props->vendor_id = pcidev->vendor;
34 props->vendor_part_id = pcidev->device;
35
36 props->hw_ver = rf->pcidev->revision;
37 props->page_size_cap = hw_attrs->page_size_cap;
38 props->max_mr_size = hw_attrs->max_mr_size;
39 props->max_qp = rf->max_qp - rf->used_qps;
40 props->max_qp_wr = hw_attrs->max_qp_wr;
41 props->max_send_sge = hw_attrs->uk_attrs.max_hw_wq_frags;
42 props->max_recv_sge = hw_attrs->uk_attrs.max_hw_wq_frags;
43 props->max_cq = rf->max_cq - rf->used_cqs;
44 props->max_cqe = rf->max_cqe - 1;
45 props->max_mr = rf->max_mr - rf->used_mrs;
46 if (hw_attrs->uk_attrs.hw_rev >= IRDMA_GEN_3)
47 props->max_mw = props->max_mr;
48 props->max_pd = rf->max_pd - rf->used_pds;
49 props->max_sge_rd = hw_attrs->uk_attrs.max_hw_read_sges;
50 props->max_qp_rd_atom = hw_attrs->max_hw_ird;
51 props->max_qp_init_rd_atom = hw_attrs->max_hw_ord;
52 if (rdma_protocol_roce(ibdev, 1)) {
53 props->device_cap_flags |= IB_DEVICE_RC_RNR_NAK_GEN;
54 props->max_pkeys = IRDMA_PKEY_TBL_SZ;
55 }
56
57 props->max_ah = rf->max_ah;
58 props->max_mcast_grp = rf->max_mcg;
59 props->max_mcast_qp_attach = IRDMA_MAX_MGS_PER_CTX;
60 props->max_total_mcast_qp_attach = rf->max_qp * IRDMA_MAX_MGS_PER_CTX;
61 props->max_fast_reg_page_list_len = IRDMA_MAX_PAGES_PER_FMR;
62 props->max_srq = rf->max_srq - rf->used_srqs;
63 props->max_srq_wr = IRDMA_MAX_SRQ_WRS;
64 props->max_srq_sge = hw_attrs->uk_attrs.max_hw_wq_frags;
65 if (hw_attrs->uk_attrs.feature_flags & IRDMA_FEATURE_ATOMIC_OPS)
66 props->atomic_cap = IB_ATOMIC_HCA;
67 else
68 props->atomic_cap = IB_ATOMIC_NONE;
69 props->masked_atomic_cap = props->atomic_cap;
70 if (hw_attrs->uk_attrs.hw_rev >= IRDMA_GEN_3) {
71 #define HCA_CORE_CLOCK_KHZ 1000000UL
72 props->timestamp_mask = GENMASK(31, 0);
73 props->hca_core_clock = HCA_CORE_CLOCK_KHZ;
74 }
75 if (hw_attrs->uk_attrs.hw_rev >= IRDMA_GEN_3)
76 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
77
78 return 0;
79 }
80
81 /**
82 * irdma_query_port - get port attributes
83 * @ibdev: device pointer from stack
84 * @port: port number for query
85 * @props: returning device attributes
86 */
irdma_query_port(struct ib_device * ibdev,u32 port,struct ib_port_attr * props)87 static int irdma_query_port(struct ib_device *ibdev, u32 port,
88 struct ib_port_attr *props)
89 {
90 struct irdma_device *iwdev = to_iwdev(ibdev);
91 struct net_device *netdev = iwdev->netdev;
92
93 /* no need to zero out pros here. done by caller */
94
95 props->max_mtu = IB_MTU_4096;
96 props->active_mtu = ib_mtu_int_to_enum(netdev->mtu);
97 props->lid = 1;
98 props->lmc = 0;
99 props->sm_lid = 0;
100 props->sm_sl = 0;
101 if (netif_carrier_ok(netdev) && netif_running(netdev)) {
102 props->state = IB_PORT_ACTIVE;
103 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
104 } else {
105 props->state = IB_PORT_DOWN;
106 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
107 }
108
109 ib_get_eth_speed(ibdev, port, &props->active_speed,
110 &props->active_width);
111
112 if (rdma_protocol_roce(ibdev, 1)) {
113 props->gid_tbl_len = 32;
114 props->ip_gids = true;
115 props->pkey_tbl_len = IRDMA_PKEY_TBL_SZ;
116 } else {
117 props->gid_tbl_len = 1;
118 }
119 props->qkey_viol_cntr = 0;
120 props->port_cap_flags |= IB_PORT_CM_SUP | IB_PORT_REINIT_SUP;
121 props->max_msg_sz = iwdev->rf->sc_dev.hw_attrs.max_hw_outbound_msg_size;
122
123 return 0;
124 }
125
126 /**
127 * irdma_disassociate_ucontext - Disassociate user context
128 * @context: ib user context
129 */
irdma_disassociate_ucontext(struct ib_ucontext * context)130 static void irdma_disassociate_ucontext(struct ib_ucontext *context)
131 {
132 }
133
irdma_mmap_legacy(struct irdma_ucontext * ucontext,struct vm_area_struct * vma)134 static int irdma_mmap_legacy(struct irdma_ucontext *ucontext,
135 struct vm_area_struct *vma)
136 {
137 u64 pfn;
138
139 if (vma->vm_pgoff || vma->vm_end - vma->vm_start != PAGE_SIZE)
140 return -EINVAL;
141
142 vma->vm_private_data = ucontext;
143 pfn = ((uintptr_t)ucontext->iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET] +
144 pci_resource_start(ucontext->iwdev->rf->pcidev, 0)) >> PAGE_SHIFT;
145
146 return rdma_user_mmap_io(&ucontext->ibucontext, vma, pfn, PAGE_SIZE,
147 pgprot_noncached(vma->vm_page_prot), NULL);
148 }
149
irdma_mmap_free(struct rdma_user_mmap_entry * rdma_entry)150 static void irdma_mmap_free(struct rdma_user_mmap_entry *rdma_entry)
151 {
152 struct irdma_user_mmap_entry *entry = to_irdma_mmap_entry(rdma_entry);
153
154 kfree(entry);
155 }
156
157 static struct rdma_user_mmap_entry*
irdma_user_mmap_entry_insert(struct irdma_ucontext * ucontext,u64 bar_offset,enum irdma_mmap_flag mmap_flag,u64 * mmap_offset)158 irdma_user_mmap_entry_insert(struct irdma_ucontext *ucontext, u64 bar_offset,
159 enum irdma_mmap_flag mmap_flag, u64 *mmap_offset)
160 {
161 struct irdma_user_mmap_entry *entry = kzalloc_obj(*entry);
162 int ret;
163
164 if (!entry)
165 return NULL;
166
167 entry->bar_offset = bar_offset;
168 entry->mmap_flag = mmap_flag;
169
170 ret = rdma_user_mmap_entry_insert(&ucontext->ibucontext,
171 &entry->rdma_entry, PAGE_SIZE);
172 if (ret) {
173 kfree(entry);
174 return NULL;
175 }
176 *mmap_offset = rdma_user_mmap_get_offset(&entry->rdma_entry);
177
178 return &entry->rdma_entry;
179 }
180
181 /**
182 * irdma_mmap - user memory map
183 * @context: context created during alloc
184 * @vma: kernel info for user memory map
185 */
irdma_mmap(struct ib_ucontext * context,struct vm_area_struct * vma)186 static int irdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
187 {
188 struct rdma_user_mmap_entry *rdma_entry;
189 struct irdma_user_mmap_entry *entry;
190 struct irdma_ucontext *ucontext;
191 u64 pfn;
192 int ret;
193
194 ucontext = to_ucontext(context);
195
196 /* Legacy support for libi40iw with hard-coded mmap key */
197 if (ucontext->legacy_mode)
198 return irdma_mmap_legacy(ucontext, vma);
199
200 rdma_entry = rdma_user_mmap_entry_get(&ucontext->ibucontext, vma);
201 if (!rdma_entry) {
202 ibdev_dbg(&ucontext->iwdev->ibdev,
203 "VERBS: pgoff[0x%lx] does not have valid entry\n",
204 vma->vm_pgoff);
205 return -EINVAL;
206 }
207
208 entry = to_irdma_mmap_entry(rdma_entry);
209 ibdev_dbg(&ucontext->iwdev->ibdev,
210 "VERBS: bar_offset [0x%llx] mmap_flag [%d]\n",
211 entry->bar_offset, entry->mmap_flag);
212
213 pfn = (entry->bar_offset +
214 pci_resource_start(ucontext->iwdev->rf->pcidev, 0)) >> PAGE_SHIFT;
215
216 switch (entry->mmap_flag) {
217 case IRDMA_MMAP_IO_NC:
218 ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE,
219 pgprot_noncached(vma->vm_page_prot),
220 rdma_entry);
221 break;
222 case IRDMA_MMAP_IO_WC:
223 ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE,
224 pgprot_writecombine(vma->vm_page_prot),
225 rdma_entry);
226 break;
227 default:
228 ret = -EINVAL;
229 }
230
231 if (ret)
232 ibdev_dbg(&ucontext->iwdev->ibdev,
233 "VERBS: bar_offset [0x%llx] mmap_flag[%d] err[%d]\n",
234 entry->bar_offset, entry->mmap_flag, ret);
235 rdma_user_mmap_entry_put(rdma_entry);
236
237 return ret;
238 }
239
240 /**
241 * irdma_alloc_push_page - allocate a push page for qp
242 * @iwqp: qp pointer
243 */
irdma_alloc_push_page(struct irdma_qp * iwqp)244 static void irdma_alloc_push_page(struct irdma_qp *iwqp)
245 {
246 struct irdma_cqp_request *cqp_request;
247 struct cqp_cmds_info *cqp_info;
248 struct irdma_device *iwdev = iwqp->iwdev;
249 struct irdma_sc_qp *qp = &iwqp->sc_qp;
250 int status;
251
252 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
253 if (!cqp_request)
254 return;
255
256 cqp_info = &cqp_request->info;
257 cqp_info->cqp_cmd = IRDMA_OP_MANAGE_PUSH_PAGE;
258 cqp_info->post_sq = 1;
259 cqp_info->in.u.manage_push_page.info.push_idx = 0;
260 cqp_info->in.u.manage_push_page.info.qs_handle =
261 qp->vsi->qos[qp->user_pri].qs_handle;
262 cqp_info->in.u.manage_push_page.info.free_page = 0;
263 cqp_info->in.u.manage_push_page.info.push_page_type = 0;
264 cqp_info->in.u.manage_push_page.cqp = &iwdev->rf->cqp.sc_cqp;
265 cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
266
267 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
268 if (!status && cqp_request->compl_info.op_ret_val <
269 iwdev->rf->sc_dev.hw_attrs.max_hw_device_pages) {
270 qp->push_idx = cqp_request->compl_info.op_ret_val;
271 qp->push_offset = 0;
272 }
273
274 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
275 }
276
277 /**
278 * irdma_alloc_ucontext - Allocate the user context data structure
279 * @uctx: uverbs context pointer
280 * @udata: user data
281 *
282 * This keeps track of all objects associated with a particular
283 * user-mode client.
284 */
irdma_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)285 static int irdma_alloc_ucontext(struct ib_ucontext *uctx,
286 struct ib_udata *udata)
287 {
288 #define IRDMA_ALLOC_UCTX_MIN_RESP_LEN offsetofend(struct irdma_alloc_ucontext_resp, rsvd)
289 struct ib_device *ibdev = uctx->device;
290 struct irdma_device *iwdev = to_iwdev(ibdev);
291 struct irdma_alloc_ucontext_req req = {};
292 struct irdma_alloc_ucontext_resp uresp = {};
293 struct irdma_ucontext *ucontext = to_ucontext(uctx);
294 struct irdma_uk_attrs *uk_attrs = &iwdev->rf->sc_dev.hw_attrs.uk_attrs;
295 int ret;
296
297 if (udata->outlen < IRDMA_ALLOC_UCTX_MIN_RESP_LEN)
298 return -EINVAL;
299
300 ret = ib_copy_validate_udata_in_cm(udata, req, rsvd8,
301 IRDMA_ALLOC_UCTX_USE_RAW_ATTR |
302 IRDMA_SUPPORT_WQE_FORMAT_V2);
303 if (ret)
304 return ret;
305
306 if (req.userspace_ver < 4 || req.userspace_ver > IRDMA_ABI_VER)
307 goto ver_error;
308
309 ucontext->iwdev = iwdev;
310 ucontext->abi_ver = req.userspace_ver;
311
312 if (!(req.comp_mask & IRDMA_SUPPORT_WQE_FORMAT_V2) &&
313 uk_attrs->hw_rev >= IRDMA_GEN_3)
314 return -EOPNOTSUPP;
315
316 if (req.comp_mask & IRDMA_ALLOC_UCTX_USE_RAW_ATTR)
317 ucontext->use_raw_attrs = true;
318
319 /* GEN_1 legacy support with libi40iw */
320 if (udata->outlen == IRDMA_ALLOC_UCTX_MIN_RESP_LEN) {
321 if (uk_attrs->hw_rev != IRDMA_GEN_1)
322 return -EOPNOTSUPP;
323
324 ucontext->legacy_mode = true;
325 uresp.max_qps = iwdev->rf->max_qp;
326 uresp.max_pds = iwdev->rf->sc_dev.hw_attrs.max_hw_pds;
327 uresp.wq_size = iwdev->rf->sc_dev.hw_attrs.max_qp_wr * 2;
328 uresp.kernel_ver = req.userspace_ver;
329 ret = ib_respond_udata(udata, uresp);
330 if (ret)
331 return ret;
332 } else {
333 u64 bar_off = (uintptr_t)iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET];
334
335 ucontext->db_mmap_entry =
336 irdma_user_mmap_entry_insert(ucontext, bar_off,
337 IRDMA_MMAP_IO_NC,
338 &uresp.db_mmap_key);
339 if (!ucontext->db_mmap_entry)
340 return -ENOMEM;
341
342 uresp.kernel_ver = IRDMA_ABI_VER;
343 uresp.feature_flags = uk_attrs->feature_flags;
344 uresp.max_hw_wq_frags = uk_attrs->max_hw_wq_frags;
345 uresp.max_hw_read_sges = uk_attrs->max_hw_read_sges;
346 uresp.max_hw_inline = uk_attrs->max_hw_inline;
347 uresp.max_hw_rq_quanta = uk_attrs->max_hw_rq_quanta;
348 uresp.max_hw_wq_quanta = uk_attrs->max_hw_wq_quanta;
349 uresp.max_hw_sq_chunk = uk_attrs->max_hw_sq_chunk;
350 uresp.max_hw_cq_size = uk_attrs->max_hw_cq_size;
351 uresp.min_hw_cq_size = uk_attrs->min_hw_cq_size;
352 uresp.hw_rev = uk_attrs->hw_rev;
353 uresp.comp_mask |= IRDMA_ALLOC_UCTX_USE_RAW_ATTR;
354 uresp.min_hw_wq_size = uk_attrs->min_hw_wq_size;
355 uresp.comp_mask |= IRDMA_ALLOC_UCTX_MIN_HW_WQ_SIZE;
356 uresp.max_hw_srq_quanta = uk_attrs->max_hw_srq_quanta;
357 uresp.comp_mask |= IRDMA_ALLOC_UCTX_MAX_HW_SRQ_QUANTA;
358 ret = ib_respond_udata(udata, uresp);
359 if (ret) {
360 rdma_user_mmap_entry_remove(ucontext->db_mmap_entry);
361 return ret;
362 }
363 }
364
365 INIT_LIST_HEAD(&ucontext->cq_reg_mem_list);
366 spin_lock_init(&ucontext->cq_reg_mem_list_lock);
367 INIT_LIST_HEAD(&ucontext->qp_reg_mem_list);
368 spin_lock_init(&ucontext->qp_reg_mem_list_lock);
369 INIT_LIST_HEAD(&ucontext->srq_reg_mem_list);
370 spin_lock_init(&ucontext->srq_reg_mem_list_lock);
371
372 return 0;
373
374 ver_error:
375 ibdev_err(&iwdev->ibdev,
376 "Invalid userspace driver version detected. Detected version %d, should be %d\n",
377 req.userspace_ver, IRDMA_ABI_VER);
378 return -EINVAL;
379 }
380
381 /**
382 * irdma_dealloc_ucontext - deallocate the user context data structure
383 * @context: user context created during alloc
384 */
irdma_dealloc_ucontext(struct ib_ucontext * context)385 static void irdma_dealloc_ucontext(struct ib_ucontext *context)
386 {
387 struct irdma_ucontext *ucontext = to_ucontext(context);
388
389 rdma_user_mmap_entry_remove(ucontext->db_mmap_entry);
390 }
391
392 /**
393 * irdma_alloc_pd - allocate protection domain
394 * @pd: PD pointer
395 * @udata: user data
396 */
irdma_alloc_pd(struct ib_pd * pd,struct ib_udata * udata)397 static int irdma_alloc_pd(struct ib_pd *pd, struct ib_udata *udata)
398 {
399 #define IRDMA_ALLOC_PD_MIN_RESP_LEN offsetofend(struct irdma_alloc_pd_resp, rsvd)
400 struct irdma_pd *iwpd = to_iwpd(pd);
401 struct irdma_device *iwdev = to_iwdev(pd->device);
402 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
403 struct irdma_pci_f *rf = iwdev->rf;
404 struct irdma_alloc_pd_resp uresp = {};
405 struct irdma_sc_pd *sc_pd;
406 u32 pd_id = 0;
407 int err;
408
409 err = ib_is_udata_in_empty(udata);
410 if (err)
411 return err;
412
413 if (udata && udata->outlen < IRDMA_ALLOC_PD_MIN_RESP_LEN)
414 return -EINVAL;
415
416 err = irdma_alloc_rsrc(rf, rf->allocated_pds, rf->max_pd, &pd_id,
417 &rf->next_pd);
418 if (err)
419 return err;
420
421 sc_pd = &iwpd->sc_pd;
422 if (udata) {
423 struct irdma_ucontext *ucontext =
424 rdma_udata_to_drv_context(udata, struct irdma_ucontext,
425 ibucontext);
426 irdma_sc_pd_init(dev, sc_pd, pd_id, ucontext->abi_ver);
427 uresp.pd_id = pd_id;
428 err = ib_respond_udata(udata, uresp);
429 if (err)
430 goto error;
431 } else {
432 irdma_sc_pd_init(dev, sc_pd, pd_id, IRDMA_ABI_VER);
433 }
434
435 return 0;
436 error:
437 irdma_free_rsrc(rf, rf->allocated_pds, pd_id);
438
439 return err;
440 }
441
442 /**
443 * irdma_dealloc_pd - deallocate pd
444 * @ibpd: ptr of pd to be deallocated
445 * @udata: user data
446 */
irdma_dealloc_pd(struct ib_pd * ibpd,struct ib_udata * udata)447 static int irdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
448 {
449 struct irdma_pd *iwpd = to_iwpd(ibpd);
450 struct irdma_device *iwdev = to_iwdev(ibpd->device);
451 int ret;
452
453 ret = ib_no_udata_io(udata);
454 if (ret)
455 return ret;
456
457 irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_pds, iwpd->sc_pd.pd_id);
458
459 return 0;
460 }
461
462 /**
463 * irdma_get_pbl - Retrieve pbl from a list given a virtual
464 * address
465 * @va: user virtual address
466 * @pbl_list: pbl list to search in (QP's or CQ's)
467 */
irdma_get_pbl(unsigned long va,struct list_head * pbl_list)468 static struct irdma_pbl *irdma_get_pbl(unsigned long va,
469 struct list_head *pbl_list)
470 {
471 struct irdma_pbl *iwpbl;
472
473 list_for_each_entry (iwpbl, pbl_list, list) {
474 if (iwpbl->user_base == va) {
475 struct irdma_mr *iwmr = iwpbl->iwmr;
476
477 refcount_inc(&iwmr->user_ring_refs);
478 list_del(&iwpbl->list);
479 iwpbl->on_list = false;
480 return iwpbl;
481 }
482 }
483
484 return NULL;
485 }
486
487 /**
488 * irdma_clean_cqes - clean cq entries for qp
489 * @iwqp: qp ptr (user or kernel)
490 * @iwcq: cq ptr
491 */
irdma_clean_cqes(struct irdma_qp * iwqp,struct irdma_cq * iwcq)492 static void irdma_clean_cqes(struct irdma_qp *iwqp, struct irdma_cq *iwcq)
493 {
494 struct irdma_cq_uk *ukcq = &iwcq->sc_cq.cq_uk;
495 unsigned long flags;
496
497 spin_lock_irqsave(&iwcq->lock, flags);
498 irdma_uk_clean_cq(&iwqp->sc_qp.qp_uk, ukcq);
499 spin_unlock_irqrestore(&iwcq->lock, flags);
500 }
501
irdma_remove_push_mmap_entries(struct irdma_qp * iwqp)502 static void irdma_remove_push_mmap_entries(struct irdma_qp *iwqp)
503 {
504 if (iwqp->push_db_mmap_entry) {
505 rdma_user_mmap_entry_remove(iwqp->push_db_mmap_entry);
506 iwqp->push_db_mmap_entry = NULL;
507 }
508 if (iwqp->push_wqe_mmap_entry) {
509 rdma_user_mmap_entry_remove(iwqp->push_wqe_mmap_entry);
510 iwqp->push_wqe_mmap_entry = NULL;
511 }
512 }
513
irdma_setup_push_mmap_entries(struct irdma_ucontext * ucontext,struct irdma_qp * iwqp,u64 * push_wqe_mmap_key,u64 * push_db_mmap_key)514 static int irdma_setup_push_mmap_entries(struct irdma_ucontext *ucontext,
515 struct irdma_qp *iwqp,
516 u64 *push_wqe_mmap_key,
517 u64 *push_db_mmap_key)
518 {
519 struct irdma_device *iwdev = ucontext->iwdev;
520 u64 rsvd, bar_off;
521
522 rsvd = IRDMA_PF_BAR_RSVD;
523 bar_off = (uintptr_t)iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET];
524 /* skip over db page */
525 bar_off += IRDMA_HW_PAGE_SIZE;
526 /* push wqe page */
527 bar_off += rsvd + iwqp->sc_qp.push_idx * IRDMA_HW_PAGE_SIZE;
528 iwqp->push_wqe_mmap_entry = irdma_user_mmap_entry_insert(ucontext,
529 bar_off, IRDMA_MMAP_IO_WC,
530 push_wqe_mmap_key);
531 if (!iwqp->push_wqe_mmap_entry)
532 return -ENOMEM;
533
534 /* push doorbell page */
535 bar_off += IRDMA_HW_PAGE_SIZE;
536 iwqp->push_db_mmap_entry = irdma_user_mmap_entry_insert(ucontext,
537 bar_off, IRDMA_MMAP_IO_NC,
538 push_db_mmap_key);
539 if (!iwqp->push_db_mmap_entry) {
540 rdma_user_mmap_entry_remove(iwqp->push_wqe_mmap_entry);
541 return -ENOMEM;
542 }
543
544 return 0;
545 }
546
547 /**
548 * _irdma_destroy_qp - destroy qp
549 * @ibqp: qp's ib pointer also to get to device's qp address
550 */
_irdma_destroy_qp(struct ib_qp * ibqp)551 static void _irdma_destroy_qp(struct ib_qp *ibqp)
552 {
553 struct irdma_qp *iwqp = to_iwqp(ibqp);
554 struct irdma_device *iwdev = iwqp->iwdev;
555
556 iwqp->sc_qp.qp_uk.destroy_pending = true;
557
558 if (iwqp->iwarp_state >= IRDMA_QP_STATE_IDLE)
559 irdma_modify_qp_to_err(&iwqp->sc_qp);
560
561 if (!iwqp->user_mode)
562 cancel_delayed_work_sync(&iwqp->dwork_flush);
563
564 if (!iwqp->user_mode) {
565 if (iwqp->iwscq) {
566 irdma_clean_cqes(iwqp, iwqp->iwscq);
567 if (iwqp->iwrcq != iwqp->iwscq)
568 irdma_clean_cqes(iwqp, iwqp->iwrcq);
569 }
570 }
571
572 irdma_qp_rem_ref(&iwqp->ibqp);
573 if (!iwdev->rf->reset)
574 wait_for_completion(&iwqp->free_qp);
575 irdma_free_lsmm_rsrc(iwqp);
576 irdma_cqp_qp_destroy_cmd(&iwdev->rf->sc_dev, &iwqp->sc_qp);
577
578 irdma_remove_push_mmap_entries(iwqp);
579
580 if (iwqp->sc_qp.qp_uk.qp_id == 1)
581 iwdev->rf->hwqp1_rsvd = false;
582 irdma_free_qp_rsrc(iwqp);
583 }
584
585 /**
586 * irdma_destroy_qp - destroy qp
587 * @ibqp: qp's ib pointer also to get to device's qp address
588 * @udata: user data
589 */
irdma_destroy_qp(struct ib_qp * ibqp,struct ib_udata * udata)590 static int irdma_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
591 {
592 int ret;
593
594 ret = ib_no_udata_io(udata);
595 if (ret)
596 return ret;
597
598 _irdma_destroy_qp(ibqp);
599
600 return 0;
601 }
602
603 /**
604 * irdma_setup_virt_qp - setup for allocation of virtual qp
605 * @iwdev: irdma device
606 * @iwqp: qp ptr
607 * @init_info: initialize info to return
608 */
irdma_setup_virt_qp(struct irdma_device * iwdev,struct irdma_qp * iwqp,struct irdma_qp_init_info * init_info)609 static void irdma_setup_virt_qp(struct irdma_device *iwdev,
610 struct irdma_qp *iwqp,
611 struct irdma_qp_init_info *init_info)
612 {
613 struct irdma_pbl *iwpbl = iwqp->iwpbl;
614 struct irdma_qp_mr *qpmr = &iwpbl->qp_mr;
615
616 iwqp->page = qpmr->sq_page;
617 init_info->shadow_area_pa = qpmr->shadow;
618 if (iwpbl->pbl_allocated) {
619 init_info->virtual_map = true;
620 init_info->sq_pa = qpmr->sq_pbl.idx;
621 /* Need to use contiguous buffer for RQ of QP
622 * in case it is associated with SRQ.
623 */
624 init_info->rq_pa = init_info->qp_uk_init_info.srq_uk ?
625 qpmr->rq_pa : qpmr->rq_pbl.idx;
626 } else {
627 init_info->sq_pa = qpmr->sq_pbl.addr;
628 init_info->rq_pa = qpmr->rq_pbl.addr;
629 }
630 }
631
632 /**
633 * irdma_setup_umode_qp - setup sq and rq size in user mode qp
634 * @ucontext: user context
635 * @req: user request pointer
636 * @iwdev: iwarp device
637 * @iwqp: qp ptr (user or kernel)
638 * @info: initialize info to return
639 * @init_attr: Initial QP create attributes
640 */
irdma_setup_umode_qp(struct irdma_ucontext * ucontext,struct irdma_create_qp_req * req,struct irdma_device * iwdev,struct irdma_qp * iwqp,struct irdma_qp_init_info * info,struct ib_qp_init_attr * init_attr)641 static int irdma_setup_umode_qp(struct irdma_ucontext *ucontext,
642 struct irdma_create_qp_req *req,
643 struct irdma_device *iwdev,
644 struct irdma_qp *iwqp,
645 struct irdma_qp_init_info *info,
646 struct ib_qp_init_attr *init_attr)
647 {
648 struct irdma_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
649 unsigned long flags;
650 int ret;
651
652 iwqp->ctx_info.qp_compl_ctx = req->user_compl_ctx;
653 iwqp->user_mode = 1;
654
655 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
656 iwqp->iwpbl = irdma_get_pbl((unsigned long)req->user_wqe_bufs,
657 &ucontext->qp_reg_mem_list);
658 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
659
660 if (!iwqp->iwpbl) {
661 ret = -ENODATA;
662 ibdev_dbg(&iwdev->ibdev, "VERBS: no pbl info\n");
663 return ret;
664 }
665
666 if (!ucontext->use_raw_attrs) {
667 /**
668 * Maintain backward compat with older ABI which passes sq and
669 * rq depth in quanta in cap.max_send_wr and cap.max_recv_wr.
670 * There is no way to compute the correct value of
671 * iwqp->max_send_wr/max_recv_wr in the kernel.
672 */
673 iwqp->max_send_wr = init_attr->cap.max_send_wr;
674 iwqp->max_recv_wr = init_attr->cap.max_recv_wr;
675 ukinfo->sq_size = init_attr->cap.max_send_wr;
676 ukinfo->rq_size = init_attr->cap.max_recv_wr;
677 irdma_uk_calc_shift_wq(ukinfo, &ukinfo->sq_shift,
678 &ukinfo->rq_shift);
679 } else {
680 ret = irdma_uk_calc_depth_shift_sq(ukinfo, &ukinfo->sq_depth,
681 &ukinfo->sq_shift);
682 if (ret)
683 return ret;
684
685 ret = irdma_uk_calc_depth_shift_rq(ukinfo, &ukinfo->rq_depth,
686 &ukinfo->rq_shift);
687 if (ret)
688 return ret;
689
690 iwqp->max_send_wr =
691 (ukinfo->sq_depth - IRDMA_SQ_RSVD) >> ukinfo->sq_shift;
692 iwqp->max_recv_wr =
693 (ukinfo->rq_depth - IRDMA_RQ_RSVD) >> ukinfo->rq_shift;
694 ukinfo->sq_size = ukinfo->sq_depth >> ukinfo->sq_shift;
695 ukinfo->rq_size = ukinfo->rq_depth >> ukinfo->rq_shift;
696 }
697
698 irdma_setup_virt_qp(iwdev, iwqp, info);
699
700 return 0;
701 }
702
703 /**
704 * irdma_setup_kmode_qp - setup initialization for kernel mode qp
705 * @iwdev: iwarp device
706 * @iwqp: qp ptr (user or kernel)
707 * @info: initialize info to return
708 * @init_attr: Initial QP create attributes
709 */
irdma_setup_kmode_qp(struct irdma_device * iwdev,struct irdma_qp * iwqp,struct irdma_qp_init_info * info,struct ib_qp_init_attr * init_attr)710 static int irdma_setup_kmode_qp(struct irdma_device *iwdev,
711 struct irdma_qp *iwqp,
712 struct irdma_qp_init_info *info,
713 struct ib_qp_init_attr *init_attr)
714 {
715 struct irdma_dma_mem *mem = &iwqp->kqp.dma_mem;
716 u32 size;
717 int status;
718 struct irdma_qp_uk_init_info *ukinfo = &info->qp_uk_init_info;
719
720 status = irdma_uk_calc_depth_shift_sq(ukinfo, &ukinfo->sq_depth,
721 &ukinfo->sq_shift);
722 if (status)
723 return status;
724
725 status = irdma_uk_calc_depth_shift_rq(ukinfo, &ukinfo->rq_depth,
726 &ukinfo->rq_shift);
727 if (status)
728 return status;
729
730 iwqp->kqp.sq_wrid_mem =
731 kzalloc_objs(*iwqp->kqp.sq_wrid_mem, ukinfo->sq_depth);
732 if (!iwqp->kqp.sq_wrid_mem)
733 return -ENOMEM;
734
735 iwqp->kqp.rq_wrid_mem =
736 kzalloc_objs(*iwqp->kqp.rq_wrid_mem, ukinfo->rq_depth);
737
738 if (!iwqp->kqp.rq_wrid_mem) {
739 kfree(iwqp->kqp.sq_wrid_mem);
740 iwqp->kqp.sq_wrid_mem = NULL;
741 return -ENOMEM;
742 }
743
744 ukinfo->sq_wrtrk_array = iwqp->kqp.sq_wrid_mem;
745 ukinfo->rq_wrid_array = iwqp->kqp.rq_wrid_mem;
746
747 size = (ukinfo->sq_depth + ukinfo->rq_depth) * IRDMA_QP_WQE_MIN_SIZE;
748 size += (IRDMA_SHADOW_AREA_SIZE << 3);
749
750 mem->size = ALIGN(size, 256);
751 mem->va = dma_alloc_coherent(iwdev->rf->hw.device, mem->size,
752 &mem->pa, GFP_KERNEL);
753 if (!mem->va) {
754 kfree(iwqp->kqp.sq_wrid_mem);
755 iwqp->kqp.sq_wrid_mem = NULL;
756 kfree(iwqp->kqp.rq_wrid_mem);
757 iwqp->kqp.rq_wrid_mem = NULL;
758 return -ENOMEM;
759 }
760
761 ukinfo->sq = mem->va;
762 info->sq_pa = mem->pa;
763 ukinfo->rq = &ukinfo->sq[ukinfo->sq_depth];
764 info->rq_pa = info->sq_pa + (ukinfo->sq_depth * IRDMA_QP_WQE_MIN_SIZE);
765 ukinfo->shadow_area = ukinfo->rq[ukinfo->rq_depth].elem;
766 info->shadow_area_pa =
767 info->rq_pa + (ukinfo->rq_depth * IRDMA_QP_WQE_MIN_SIZE);
768 ukinfo->sq_size = ukinfo->sq_depth >> ukinfo->sq_shift;
769 ukinfo->rq_size = ukinfo->rq_depth >> ukinfo->rq_shift;
770 ukinfo->qp_id = info->qp_uk_init_info.qp_id;
771
772 iwqp->max_send_wr = (ukinfo->sq_depth - IRDMA_SQ_RSVD) >> ukinfo->sq_shift;
773 iwqp->max_recv_wr = (ukinfo->rq_depth - IRDMA_RQ_RSVD) >> ukinfo->rq_shift;
774 init_attr->cap.max_send_wr = iwqp->max_send_wr;
775 init_attr->cap.max_recv_wr = iwqp->max_recv_wr;
776
777 return 0;
778 }
779
irdma_cqp_create_qp_cmd(struct irdma_qp * iwqp)780 static int irdma_cqp_create_qp_cmd(struct irdma_qp *iwqp)
781 {
782 struct irdma_pci_f *rf = iwqp->iwdev->rf;
783 struct irdma_cqp_request *cqp_request;
784 struct cqp_cmds_info *cqp_info;
785 struct irdma_create_qp_info *qp_info;
786 int status;
787
788 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
789 if (!cqp_request)
790 return -ENOMEM;
791
792 cqp_info = &cqp_request->info;
793 qp_info = &cqp_request->info.in.u.qp_create.info;
794 qp_info->mac_valid = true;
795 qp_info->cq_num_valid = true;
796 qp_info->next_iwarp_state = IRDMA_QP_STATE_IDLE;
797
798 cqp_info->cqp_cmd = IRDMA_OP_QP_CREATE;
799 cqp_info->post_sq = 1;
800 cqp_info->in.u.qp_create.qp = &iwqp->sc_qp;
801 cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
802 status = irdma_handle_cqp_op(rf, cqp_request);
803 irdma_put_cqp_request(&rf->cqp, cqp_request);
804
805 return status;
806 }
807
irdma_roce_fill_and_set_qpctx_info(struct irdma_qp * iwqp,struct irdma_qp_host_ctx_info * ctx_info)808 static void irdma_roce_fill_and_set_qpctx_info(struct irdma_qp *iwqp,
809 struct irdma_qp_host_ctx_info *ctx_info)
810 {
811 struct irdma_device *iwdev = iwqp->iwdev;
812 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
813 struct irdma_roce_offload_info *roce_info;
814 struct irdma_udp_offload_info *udp_info;
815
816 udp_info = &iwqp->udp_info;
817 udp_info->snd_mss = ib_mtu_enum_to_int(ib_mtu_int_to_enum(iwdev->vsi.mtu));
818 udp_info->cwnd = iwdev->roce_cwnd;
819 udp_info->rexmit_thresh = 2;
820 udp_info->rnr_nak_thresh = 2;
821 udp_info->src_port = 0xc000;
822 udp_info->dst_port = ROCE_V2_UDP_DPORT;
823 roce_info = &iwqp->roce_info;
824 ether_addr_copy(roce_info->mac_addr, iwdev->netdev->dev_addr);
825
826 if (iwqp->ibqp.qp_type == IB_QPT_GSI && iwqp->ibqp.qp_num != 1)
827 roce_info->is_qp1 = true;
828 roce_info->rd_en = true;
829 roce_info->wr_rdresp_en = true;
830 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3)
831 roce_info->bind_en = true;
832 roce_info->dcqcn_en = false;
833 roce_info->rtomin = 5;
834
835 roce_info->ack_credits = iwdev->roce_ackcreds;
836 roce_info->ird_size = dev->hw_attrs.max_hw_ird;
837 roce_info->ord_size = dev->hw_attrs.max_hw_ord;
838
839 if (!iwqp->user_mode) {
840 roce_info->priv_mode_en = true;
841 roce_info->fast_reg_en = true;
842 roce_info->udprivcq_en = true;
843 }
844 roce_info->roce_tver = 0;
845
846 ctx_info->roce_info = &iwqp->roce_info;
847 ctx_info->udp_info = &iwqp->udp_info;
848 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
849 }
850
irdma_iw_fill_and_set_qpctx_info(struct irdma_qp * iwqp,struct irdma_qp_host_ctx_info * ctx_info)851 static void irdma_iw_fill_and_set_qpctx_info(struct irdma_qp *iwqp,
852 struct irdma_qp_host_ctx_info *ctx_info)
853 {
854 struct irdma_device *iwdev = iwqp->iwdev;
855 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
856 struct irdma_iwarp_offload_info *iwarp_info;
857
858 iwarp_info = &iwqp->iwarp_info;
859 ether_addr_copy(iwarp_info->mac_addr, iwdev->netdev->dev_addr);
860 iwarp_info->rd_en = true;
861 iwarp_info->wr_rdresp_en = true;
862 iwarp_info->ecn_en = true;
863 iwarp_info->rtomin = 5;
864
865 if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
866 iwarp_info->ib_rd_en = true;
867 if (!iwqp->user_mode) {
868 iwarp_info->priv_mode_en = true;
869 iwarp_info->fast_reg_en = true;
870 }
871 iwarp_info->ddp_ver = 1;
872 iwarp_info->rdmap_ver = 1;
873
874 ctx_info->iwarp_info = &iwqp->iwarp_info;
875 ctx_info->iwarp_info_valid = true;
876 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
877 ctx_info->iwarp_info_valid = false;
878 }
879
irdma_validate_qp_attrs(struct ib_qp_init_attr * init_attr,struct irdma_device * iwdev)880 static int irdma_validate_qp_attrs(struct ib_qp_init_attr *init_attr,
881 struct irdma_device *iwdev)
882 {
883 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
884 struct irdma_uk_attrs *uk_attrs = &dev->hw_attrs.uk_attrs;
885
886 if (init_attr->create_flags)
887 return -EOPNOTSUPP;
888
889 if (init_attr->cap.max_inline_data > uk_attrs->max_hw_inline ||
890 init_attr->cap.max_send_sge > uk_attrs->max_hw_wq_frags ||
891 init_attr->cap.max_recv_sge > uk_attrs->max_hw_wq_frags ||
892 init_attr->cap.max_send_wr > uk_attrs->max_hw_wq_quanta ||
893 init_attr->cap.max_recv_wr > uk_attrs->max_hw_rq_quanta)
894 return -EINVAL;
895
896 if (rdma_protocol_roce(&iwdev->ibdev, 1)) {
897 if (init_attr->qp_type != IB_QPT_RC &&
898 init_attr->qp_type != IB_QPT_UD &&
899 init_attr->qp_type != IB_QPT_GSI)
900 return -EOPNOTSUPP;
901 } else {
902 if (init_attr->qp_type != IB_QPT_RC)
903 return -EOPNOTSUPP;
904 }
905
906 return 0;
907 }
908
irdma_flush_worker(struct work_struct * work)909 static void irdma_flush_worker(struct work_struct *work)
910 {
911 struct delayed_work *dwork = to_delayed_work(work);
912 struct irdma_qp *iwqp = container_of(dwork, struct irdma_qp, dwork_flush);
913
914 irdma_generate_flush_completions(iwqp);
915 }
916
irdma_setup_gsi_qp_rsrc(struct irdma_qp * iwqp,u32 * qp_num)917 static int irdma_setup_gsi_qp_rsrc(struct irdma_qp *iwqp, u32 *qp_num)
918 {
919 struct irdma_device *iwdev = iwqp->iwdev;
920 struct irdma_pci_f *rf = iwdev->rf;
921 unsigned long flags;
922 int ret;
923
924 if (rf->rdma_ver <= IRDMA_GEN_2) {
925 *qp_num = 1;
926 return 0;
927 }
928
929 spin_lock_irqsave(&rf->rsrc_lock, flags);
930 if (!rf->hwqp1_rsvd) {
931 *qp_num = 1;
932 rf->hwqp1_rsvd = true;
933 spin_unlock_irqrestore(&rf->rsrc_lock, flags);
934 } else {
935 spin_unlock_irqrestore(&rf->rsrc_lock, flags);
936 ret = irdma_alloc_rsrc(rf, rf->allocated_qps, rf->max_qp,
937 qp_num, &rf->next_qp);
938 if (ret)
939 return ret;
940 }
941
942 ret = irdma_vchnl_req_add_vport(&rf->sc_dev, iwdev->vport_id, *qp_num,
943 (&iwdev->vsi)->qos);
944 if (ret) {
945 if (*qp_num != 1) {
946 irdma_free_rsrc(rf, rf->allocated_qps, *qp_num);
947 } else {
948 spin_lock_irqsave(&rf->rsrc_lock, flags);
949 rf->hwqp1_rsvd = false;
950 spin_unlock_irqrestore(&rf->rsrc_lock, flags);
951 }
952 return ret;
953 }
954
955 return 0;
956 }
957
958 /**
959 * irdma_create_qp - create qp
960 * @ibqp: ptr of qp
961 * @init_attr: attributes for qp
962 * @udata: user data for create qp
963 */
irdma_create_qp(struct ib_qp * ibqp,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)964 static int irdma_create_qp(struct ib_qp *ibqp,
965 struct ib_qp_init_attr *init_attr,
966 struct ib_udata *udata)
967 {
968 #define IRDMA_CREATE_QP_MIN_REQ_LEN offsetofend(struct irdma_create_qp_req, user_compl_ctx)
969 #define IRDMA_CREATE_QP_MIN_RESP_LEN offsetofend(struct irdma_create_qp_resp, rsvd)
970 struct ib_pd *ibpd = ibqp->pd;
971 struct irdma_pd *iwpd = to_iwpd(ibpd);
972 struct irdma_device *iwdev = to_iwdev(ibpd->device);
973 struct irdma_pci_f *rf = iwdev->rf;
974 struct irdma_qp *iwqp = to_iwqp(ibqp);
975 struct irdma_create_qp_resp uresp = {};
976 u32 qp_num = 0;
977 int err_code;
978 struct irdma_sc_qp *qp;
979 struct irdma_sc_dev *dev = &rf->sc_dev;
980 struct irdma_uk_attrs *uk_attrs = &dev->hw_attrs.uk_attrs;
981 struct irdma_qp_init_info init_info = {};
982 struct irdma_qp_host_ctx_info *ctx_info;
983 struct irdma_create_qp_req ureq = {};
984 struct irdma_srq *iwsrq;
985 bool srq_valid = false;
986 u32 srq_id = 0;
987
988 if (init_attr->srq) {
989 iwsrq = to_iwsrq(init_attr->srq);
990 srq_valid = true;
991 srq_id = iwsrq->srq_num;
992 init_attr->cap.max_recv_sge = uk_attrs->max_hw_wq_frags;
993 init_attr->cap.max_recv_wr = 4;
994 init_info.qp_uk_init_info.srq_uk = &iwsrq->sc_srq.srq_uk;
995 }
996
997 err_code = irdma_validate_qp_attrs(init_attr, iwdev);
998 if (err_code)
999 return err_code;
1000
1001 if (udata) {
1002 if (udata->outlen < IRDMA_CREATE_QP_MIN_RESP_LEN)
1003 return -EINVAL;
1004
1005 err_code = ib_copy_validate_udata_in(udata, ureq, user_compl_ctx);
1006 if (err_code)
1007 return err_code;
1008 }
1009
1010 init_info.vsi = &iwdev->vsi;
1011 init_info.qp_uk_init_info.uk_attrs = uk_attrs;
1012 init_info.qp_uk_init_info.sq_size = init_attr->cap.max_send_wr;
1013 init_info.qp_uk_init_info.rq_size = init_attr->cap.max_recv_wr;
1014 init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge;
1015 init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge;
1016 init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data;
1017
1018 qp = &iwqp->sc_qp;
1019 qp->qp_uk.back_qp = iwqp;
1020 qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX;
1021
1022 iwqp->iwdev = iwdev;
1023 iwqp->q2_ctx_mem.size = ALIGN(IRDMA_Q2_BUF_SIZE + IRDMA_QP_CTX_SIZE,
1024 256);
1025 iwqp->q2_ctx_mem.va = dma_alloc_coherent(dev->hw->device,
1026 iwqp->q2_ctx_mem.size,
1027 &iwqp->q2_ctx_mem.pa,
1028 GFP_KERNEL);
1029 if (!iwqp->q2_ctx_mem.va)
1030 return -ENOMEM;
1031
1032 init_info.q2 = iwqp->q2_ctx_mem.va;
1033 init_info.q2_pa = iwqp->q2_ctx_mem.pa;
1034 init_info.host_ctx = (__le64 *)(init_info.q2 + IRDMA_Q2_BUF_SIZE);
1035 init_info.host_ctx_pa = init_info.q2_pa + IRDMA_Q2_BUF_SIZE;
1036
1037 if (init_attr->qp_type == IB_QPT_GSI) {
1038 err_code = irdma_setup_gsi_qp_rsrc(iwqp, &qp_num);
1039 if (err_code)
1040 goto error;
1041 iwqp->ibqp.qp_num = 1;
1042 } else {
1043 err_code = irdma_alloc_rsrc(rf, rf->allocated_qps, rf->max_qp,
1044 &qp_num, &rf->next_qp);
1045 if (err_code)
1046 goto error;
1047 iwqp->ibqp.qp_num = qp_num;
1048 }
1049
1050 iwqp->iwpd = iwpd;
1051 qp = &iwqp->sc_qp;
1052 iwqp->iwscq = to_iwcq(init_attr->send_cq);
1053 iwqp->iwrcq = to_iwcq(init_attr->recv_cq);
1054 iwqp->host_ctx.va = init_info.host_ctx;
1055 iwqp->host_ctx.pa = init_info.host_ctx_pa;
1056 iwqp->host_ctx.size = IRDMA_QP_CTX_SIZE;
1057
1058 init_info.pd = &iwpd->sc_pd;
1059 init_info.qp_uk_init_info.qp_id = qp_num;
1060 if (!rdma_protocol_roce(&iwdev->ibdev, 1))
1061 init_info.qp_uk_init_info.first_sq_wq = 1;
1062 iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp;
1063 init_waitqueue_head(&iwqp->waitq);
1064 init_waitqueue_head(&iwqp->mod_qp_waitq);
1065
1066 if (udata) {
1067 struct irdma_ucontext *ucontext =
1068 rdma_udata_to_drv_context(udata,
1069 struct irdma_ucontext,
1070 ibucontext);
1071
1072 init_info.qp_uk_init_info.abi_ver = iwpd->sc_pd.abi_ver;
1073 err_code = irdma_setup_umode_qp(ucontext, &ureq, iwdev, iwqp,
1074 &init_info, init_attr);
1075 } else {
1076 INIT_DELAYED_WORK(&iwqp->dwork_flush, irdma_flush_worker);
1077 init_info.qp_uk_init_info.abi_ver = IRDMA_ABI_VER;
1078 err_code = irdma_setup_kmode_qp(iwdev, iwqp, &init_info, init_attr);
1079 }
1080
1081 if (err_code) {
1082 ibdev_dbg(&iwdev->ibdev, "VERBS: setup qp failed\n");
1083 goto error;
1084 }
1085
1086 if (rdma_protocol_roce(&iwdev->ibdev, 1)) {
1087 if (init_attr->qp_type == IB_QPT_RC) {
1088 init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_ROCE_RC;
1089 init_info.qp_uk_init_info.qp_caps = IRDMA_SEND_WITH_IMM |
1090 IRDMA_WRITE_WITH_IMM |
1091 IRDMA_ROCE;
1092 } else {
1093 init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_ROCE_UD;
1094 init_info.qp_uk_init_info.qp_caps = IRDMA_SEND_WITH_IMM |
1095 IRDMA_ROCE;
1096 }
1097 } else {
1098 init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_IWARP;
1099 init_info.qp_uk_init_info.qp_caps = IRDMA_WRITE_WITH_IMM;
1100 }
1101
1102 if (dev->hw_attrs.uk_attrs.hw_rev > IRDMA_GEN_1)
1103 init_info.qp_uk_init_info.qp_caps |= IRDMA_PUSH_MODE;
1104
1105 err_code = irdma_sc_qp_init(qp, &init_info);
1106 if (err_code) {
1107 ibdev_dbg(&iwdev->ibdev, "VERBS: qp_init fail\n");
1108 goto error;
1109 }
1110
1111 ctx_info = &iwqp->ctx_info;
1112 ctx_info->srq_valid = srq_valid;
1113 ctx_info->srq_id = srq_id;
1114 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
1115 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
1116
1117 if (rdma_protocol_roce(&iwdev->ibdev, 1)) {
1118 if (dev->ws_add(&iwdev->vsi, 0)) {
1119 irdma_cqp_qp_destroy_cmd(&rf->sc_dev, &iwqp->sc_qp);
1120 err_code = -EINVAL;
1121 goto error;
1122 }
1123 irdma_qp_add_qos(&iwqp->sc_qp);
1124 irdma_roce_fill_and_set_qpctx_info(iwqp, ctx_info);
1125 } else {
1126 irdma_iw_fill_and_set_qpctx_info(iwqp, ctx_info);
1127 }
1128
1129 err_code = irdma_cqp_create_qp_cmd(iwqp);
1130 if (err_code)
1131 goto error;
1132
1133 refcount_set(&iwqp->refcnt, 1);
1134 spin_lock_init(&iwqp->lock);
1135 spin_lock_init(&iwqp->sc_qp.pfpdu.lock);
1136 iwqp->sig_all = init_attr->sq_sig_type == IB_SIGNAL_ALL_WR;
1137 rf->qp_table[qp_num] = iwqp;
1138 init_completion(&iwqp->free_qp);
1139
1140 if (udata) {
1141 /* GEN_1 legacy support with libi40iw does not have expanded
1142 * uresp struct. Check for the exact legacy size (20 bytes) to
1143 * ensure that newer expanded uresp structs don't accidentally
1144 * trigger the legacy fallback.
1145 */
1146 if (udata->outlen == IRDMA_CREATE_QP_MIN_RESP_LEN) {
1147 uresp.lsmm = 1;
1148 uresp.push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1;
1149 } else {
1150 if (rdma_protocol_iwarp(&iwdev->ibdev, 1))
1151 uresp.lsmm = 1;
1152 }
1153 uresp.actual_sq_size = init_info.qp_uk_init_info.sq_size;
1154 uresp.actual_rq_size = init_info.qp_uk_init_info.rq_size;
1155 uresp.qp_id = qp_num;
1156 uresp.qp_caps = qp->qp_uk.qp_caps;
1157
1158 err_code = ib_respond_udata(udata, uresp);
1159 if (err_code) {
1160 _irdma_destroy_qp(&iwqp->ibqp);
1161 return err_code;
1162 }
1163 }
1164
1165 return 0;
1166
1167 error:
1168 irdma_free_qp_rsrc(iwqp);
1169 return err_code;
1170 }
1171
irdma_get_ib_acc_flags(struct irdma_qp * iwqp)1172 static int irdma_get_ib_acc_flags(struct irdma_qp *iwqp)
1173 {
1174 int acc_flags = 0;
1175
1176 if (rdma_protocol_roce(iwqp->ibqp.device, 1)) {
1177 if (iwqp->roce_info.wr_rdresp_en) {
1178 acc_flags |= IB_ACCESS_LOCAL_WRITE;
1179 acc_flags |= IB_ACCESS_REMOTE_WRITE;
1180 }
1181 if (iwqp->roce_info.rd_en)
1182 acc_flags |= IB_ACCESS_REMOTE_READ;
1183 if (iwqp->roce_info.bind_en)
1184 acc_flags |= IB_ACCESS_MW_BIND;
1185 if (iwqp->ctx_info.remote_atomics_en)
1186 acc_flags |= IB_ACCESS_REMOTE_ATOMIC;
1187 } else {
1188 if (iwqp->iwarp_info.wr_rdresp_en) {
1189 acc_flags |= IB_ACCESS_LOCAL_WRITE;
1190 acc_flags |= IB_ACCESS_REMOTE_WRITE;
1191 }
1192 if (iwqp->iwarp_info.rd_en)
1193 acc_flags |= IB_ACCESS_REMOTE_READ;
1194 if (iwqp->ctx_info.remote_atomics_en)
1195 acc_flags |= IB_ACCESS_REMOTE_ATOMIC;
1196 }
1197 return acc_flags;
1198 }
1199
1200 /**
1201 * irdma_query_qp - query qp attributes
1202 * @ibqp: qp pointer
1203 * @attr: attributes pointer
1204 * @attr_mask: Not used
1205 * @init_attr: qp attributes to return
1206 */
irdma_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_qp_init_attr * init_attr)1207 static int irdma_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1208 int attr_mask, struct ib_qp_init_attr *init_attr)
1209 {
1210 struct irdma_qp *iwqp = to_iwqp(ibqp);
1211 struct irdma_sc_qp *qp = &iwqp->sc_qp;
1212
1213 memset(attr, 0, sizeof(*attr));
1214 memset(init_attr, 0, sizeof(*init_attr));
1215
1216 attr->qp_state = iwqp->ibqp_state;
1217 attr->cur_qp_state = iwqp->ibqp_state;
1218 attr->cap.max_send_wr = iwqp->max_send_wr;
1219 attr->cap.max_recv_wr = iwqp->max_recv_wr;
1220 attr->cap.max_inline_data = qp->qp_uk.max_inline_data;
1221 attr->cap.max_send_sge = qp->qp_uk.max_sq_frag_cnt;
1222 attr->cap.max_recv_sge = qp->qp_uk.max_rq_frag_cnt;
1223 attr->qp_access_flags = irdma_get_ib_acc_flags(iwqp);
1224 attr->port_num = 1;
1225 if (rdma_protocol_roce(ibqp->device, 1)) {
1226 attr->path_mtu = ib_mtu_int_to_enum(iwqp->udp_info.snd_mss);
1227 attr->qkey = iwqp->roce_info.qkey;
1228 attr->rq_psn = iwqp->udp_info.epsn;
1229 attr->sq_psn = iwqp->udp_info.psn_nxt;
1230 attr->dest_qp_num = iwqp->roce_info.dest_qp;
1231 attr->pkey_index = iwqp->roce_info.p_key;
1232 attr->retry_cnt = iwqp->udp_info.rexmit_thresh;
1233 attr->rnr_retry = iwqp->udp_info.rnr_nak_thresh;
1234 attr->min_rnr_timer = iwqp->udp_info.min_rnr_timer;
1235 attr->max_rd_atomic = iwqp->roce_info.ord_size;
1236 attr->max_dest_rd_atomic = iwqp->roce_info.ird_size;
1237 }
1238
1239 init_attr->event_handler = iwqp->ibqp.event_handler;
1240 init_attr->qp_context = iwqp->ibqp.qp_context;
1241 init_attr->send_cq = iwqp->ibqp.send_cq;
1242 init_attr->recv_cq = iwqp->ibqp.recv_cq;
1243 init_attr->srq = iwqp->ibqp.srq;
1244 init_attr->cap = attr->cap;
1245
1246 return 0;
1247 }
1248
1249 /**
1250 * irdma_query_pkey - Query partition key
1251 * @ibdev: device pointer from stack
1252 * @port: port number
1253 * @index: index of pkey
1254 * @pkey: pointer to store the pkey
1255 */
irdma_query_pkey(struct ib_device * ibdev,u32 port,u16 index,u16 * pkey)1256 static int irdma_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1257 u16 *pkey)
1258 {
1259 if (index >= IRDMA_PKEY_TBL_SZ)
1260 return -EINVAL;
1261
1262 *pkey = IRDMA_DEFAULT_PKEY;
1263 return 0;
1264 }
1265
irdma_roce_get_vlan_prio(const struct ib_gid_attr * attr,u8 prio)1266 static u8 irdma_roce_get_vlan_prio(const struct ib_gid_attr *attr, u8 prio)
1267 {
1268 struct net_device *ndev;
1269
1270 rcu_read_lock();
1271 ndev = rcu_dereference(attr->ndev);
1272 if (!ndev)
1273 goto exit;
1274 if (is_vlan_dev(ndev)) {
1275 u16 vlan_qos = vlan_dev_get_egress_qos_mask(ndev, prio);
1276
1277 prio = (vlan_qos & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1278 }
1279 exit:
1280 rcu_read_unlock();
1281 return prio;
1282 }
1283
irdma_wait_for_suspend(struct irdma_qp * iwqp)1284 static int irdma_wait_for_suspend(struct irdma_qp *iwqp)
1285 {
1286 if (!wait_event_timeout(iwqp->iwdev->suspend_wq,
1287 !iwqp->suspend_pending,
1288 msecs_to_jiffies(IRDMA_EVENT_TIMEOUT_MS))) {
1289 iwqp->suspend_pending = false;
1290 ibdev_warn(&iwqp->iwdev->ibdev,
1291 "modify_qp timed out waiting for suspend. qp_id = %d, last_ae = 0x%x\n",
1292 iwqp->ibqp.qp_num, iwqp->last_aeq);
1293 return -EBUSY;
1294 }
1295
1296 return 0;
1297 }
1298
1299 /**
1300 * irdma_modify_qp_roce - modify qp request
1301 * @ibqp: qp's pointer for modify
1302 * @attr: access attributes
1303 * @attr_mask: state mask
1304 * @udata: user data
1305 */
irdma_modify_qp_roce(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)1306 int irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1307 int attr_mask, struct ib_udata *udata)
1308 {
1309 #define IRDMA_MODIFY_QP_MIN_RESP_LEN offsetofend(struct irdma_modify_qp_resp, push_valid)
1310 struct irdma_pd *iwpd = to_iwpd(ibqp->pd);
1311 struct irdma_qp *iwqp = to_iwqp(ibqp);
1312 struct irdma_device *iwdev = iwqp->iwdev;
1313 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
1314 struct irdma_qp_host_ctx_info *ctx_info;
1315 struct irdma_roce_offload_info *roce_info;
1316 struct irdma_udp_offload_info *udp_info;
1317 struct irdma_modify_qp_info info = {};
1318 struct irdma_modify_qp_resp uresp = {};
1319 struct irdma_modify_qp_req ureq = {};
1320 unsigned long flags;
1321 u8 issue_modify_qp = 0;
1322 int ret = 0;
1323
1324 /* Clear the response buffer (if any). It may be updated again later. */
1325 ret = ib_respond_empty_udata(udata);
1326 if (ret)
1327 return ret;
1328
1329 ctx_info = &iwqp->ctx_info;
1330 roce_info = &iwqp->roce_info;
1331 udp_info = &iwqp->udp_info;
1332
1333 if (udata) {
1334 /* udata inlen/outlen can be 0 when supporting legacy libi40iw */
1335 if (udata->outlen && udata->outlen < IRDMA_MODIFY_QP_MIN_RESP_LEN)
1336 return -EINVAL;
1337
1338 /* For current irdma, validate against ABI def. */
1339 if (udata->inlen) {
1340 ret = ib_copy_validate_udata_in(udata, ureq, rsvd);
1341 if (ret)
1342 return ret;
1343 }
1344 }
1345
1346 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
1347 return -EOPNOTSUPP;
1348
1349 if (attr_mask & IB_QP_DEST_QPN)
1350 roce_info->dest_qp = attr->dest_qp_num;
1351
1352 if (attr_mask & IB_QP_PKEY_INDEX) {
1353 ret = irdma_query_pkey(ibqp->device, 0, attr->pkey_index,
1354 &roce_info->p_key);
1355 if (ret)
1356 return ret;
1357 }
1358
1359 if (attr_mask & IB_QP_QKEY)
1360 roce_info->qkey = attr->qkey;
1361
1362 if (attr_mask & IB_QP_PATH_MTU)
1363 udp_info->snd_mss = ib_mtu_enum_to_int(attr->path_mtu);
1364
1365 if (attr_mask & IB_QP_SQ_PSN) {
1366 udp_info->psn_nxt = attr->sq_psn;
1367 udp_info->lsn = 0xffff;
1368 udp_info->psn_una = attr->sq_psn;
1369 udp_info->psn_max = attr->sq_psn;
1370 }
1371
1372 if (attr_mask & IB_QP_RQ_PSN)
1373 udp_info->epsn = attr->rq_psn;
1374
1375 if (attr_mask & IB_QP_RNR_RETRY)
1376 udp_info->rnr_nak_thresh = attr->rnr_retry;
1377
1378 if (attr_mask & IB_QP_MIN_RNR_TIMER &&
1379 dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3)
1380 udp_info->min_rnr_timer = attr->min_rnr_timer;
1381
1382 if (attr_mask & IB_QP_RETRY_CNT)
1383 udp_info->rexmit_thresh = attr->retry_cnt;
1384
1385 ctx_info->roce_info->pd_id = iwpd->sc_pd.pd_id;
1386
1387 if (attr_mask & IB_QP_AV) {
1388 struct irdma_av *av = &iwqp->roce_ah.av;
1389 const struct ib_gid_attr *sgid_attr =
1390 attr->ah_attr.grh.sgid_attr;
1391 u16 vlan_id = VLAN_N_VID;
1392 u32 local_ip[4];
1393
1394 memset(&iwqp->roce_ah, 0, sizeof(iwqp->roce_ah));
1395 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
1396 udp_info->ttl = attr->ah_attr.grh.hop_limit;
1397 udp_info->flow_label = attr->ah_attr.grh.flow_label;
1398 udp_info->tos = attr->ah_attr.grh.traffic_class;
1399 udp_info->src_port =
1400 rdma_get_udp_sport(udp_info->flow_label,
1401 ibqp->qp_num,
1402 roce_info->dest_qp);
1403 irdma_qp_rem_qos(&iwqp->sc_qp);
1404 dev->ws_remove(iwqp->sc_qp.vsi, ctx_info->user_pri);
1405 if (iwqp->sc_qp.vsi->dscp_mode)
1406 ctx_info->user_pri =
1407 iwqp->sc_qp.vsi->dscp_map[irdma_tos2dscp(udp_info->tos)];
1408 else
1409 ctx_info->user_pri = rt_tos2priority(udp_info->tos);
1410 }
1411 ret = rdma_read_gid_l2_fields(sgid_attr, &vlan_id,
1412 ctx_info->roce_info->mac_addr);
1413 if (ret)
1414 return ret;
1415 ctx_info->user_pri = irdma_roce_get_vlan_prio(sgid_attr,
1416 ctx_info->user_pri);
1417 if (dev->ws_add(iwqp->sc_qp.vsi, ctx_info->user_pri))
1418 return -ENOMEM;
1419 iwqp->sc_qp.user_pri = ctx_info->user_pri;
1420 irdma_qp_add_qos(&iwqp->sc_qp);
1421
1422 if (vlan_id >= VLAN_N_VID && iwdev->dcb_vlan_mode)
1423 vlan_id = 0;
1424 if (vlan_id < VLAN_N_VID) {
1425 udp_info->insert_vlan_tag = true;
1426 udp_info->vlan_tag = vlan_id |
1427 ctx_info->user_pri << VLAN_PRIO_SHIFT;
1428 } else {
1429 udp_info->insert_vlan_tag = false;
1430 }
1431
1432 av->attrs = attr->ah_attr;
1433 rdma_gid2ip((struct sockaddr *)&av->sgid_addr, &sgid_attr->gid);
1434 rdma_gid2ip((struct sockaddr *)&av->dgid_addr, &attr->ah_attr.grh.dgid);
1435 av->net_type = rdma_gid_attr_network_type(sgid_attr);
1436 if (av->net_type == RDMA_NETWORK_IPV6) {
1437 __be32 *daddr =
1438 av->dgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32;
1439 __be32 *saddr =
1440 av->sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32;
1441
1442 irdma_copy_ip_ntohl(&udp_info->dest_ip_addr[0], daddr);
1443 irdma_copy_ip_ntohl(&udp_info->local_ipaddr[0], saddr);
1444
1445 udp_info->ipv4 = false;
1446 irdma_copy_ip_ntohl(local_ip, daddr);
1447
1448 } else if (av->net_type == RDMA_NETWORK_IPV4) {
1449 __be32 saddr = av->sgid_addr.saddr_in.sin_addr.s_addr;
1450 __be32 daddr = av->dgid_addr.saddr_in.sin_addr.s_addr;
1451
1452 local_ip[0] = ntohl(daddr);
1453
1454 udp_info->ipv4 = true;
1455 udp_info->dest_ip_addr[0] = 0;
1456 udp_info->dest_ip_addr[1] = 0;
1457 udp_info->dest_ip_addr[2] = 0;
1458 udp_info->dest_ip_addr[3] = local_ip[0];
1459
1460 udp_info->local_ipaddr[0] = 0;
1461 udp_info->local_ipaddr[1] = 0;
1462 udp_info->local_ipaddr[2] = 0;
1463 udp_info->local_ipaddr[3] = ntohl(saddr);
1464 }
1465 udp_info->arp_idx =
1466 irdma_add_arp(iwdev->rf, local_ip, udp_info->ipv4,
1467 attr->ah_attr.roce.dmac);
1468 }
1469
1470 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1471 if (attr->max_rd_atomic > dev->hw_attrs.max_hw_ord) {
1472 ibdev_err(&iwdev->ibdev,
1473 "rd_atomic = %d, above max_hw_ord=%d\n",
1474 attr->max_rd_atomic,
1475 dev->hw_attrs.max_hw_ord);
1476 return -EINVAL;
1477 }
1478 if (attr->max_rd_atomic)
1479 roce_info->ord_size = attr->max_rd_atomic;
1480 info.ord_valid = true;
1481 }
1482
1483 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1484 if (attr->max_dest_rd_atomic > dev->hw_attrs.max_hw_ird) {
1485 ibdev_err(&iwdev->ibdev,
1486 "rd_atomic = %d, above max_hw_ird=%d\n",
1487 attr->max_dest_rd_atomic,
1488 dev->hw_attrs.max_hw_ird);
1489 return -EINVAL;
1490 }
1491 if (attr->max_dest_rd_atomic)
1492 roce_info->ird_size = attr->max_dest_rd_atomic;
1493 }
1494
1495 if (attr_mask & IB_QP_ACCESS_FLAGS) {
1496 if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
1497 roce_info->wr_rdresp_en = true;
1498 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
1499 roce_info->wr_rdresp_en = true;
1500 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
1501 roce_info->rd_en = true;
1502 if (dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_ATOMIC_OPS)
1503 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
1504 ctx_info->remote_atomics_en = true;
1505 }
1506
1507 ibdev_dbg(&iwdev->ibdev,
1508 "VERBS: caller: %pS qp_id=%d to_ibqpstate=%d ibqpstate=%d irdma_qpstate=%d attr_mask=0x%x\n",
1509 __builtin_return_address(0), ibqp->qp_num, attr->qp_state,
1510 iwqp->ibqp_state, iwqp->iwarp_state, attr_mask);
1511
1512 spin_lock_irqsave(&iwqp->lock, flags);
1513 if (attr_mask & IB_QP_STATE) {
1514 if (!ib_modify_qp_is_ok(iwqp->ibqp_state, attr->qp_state,
1515 iwqp->ibqp.qp_type, attr_mask)) {
1516 ibdev_warn(&iwdev->ibdev, "modify_qp invalid for qp_id=%d, old_state=0x%x, new_state=0x%x\n",
1517 iwqp->ibqp.qp_num, iwqp->ibqp_state,
1518 attr->qp_state);
1519 ret = -EINVAL;
1520 goto exit;
1521 }
1522 info.curr_iwarp_state = iwqp->iwarp_state;
1523
1524 switch (attr->qp_state) {
1525 case IB_QPS_INIT:
1526 if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) {
1527 ret = -EINVAL;
1528 goto exit;
1529 }
1530
1531 if (iwqp->iwarp_state == IRDMA_QP_STATE_INVALID) {
1532 info.next_iwarp_state = IRDMA_QP_STATE_IDLE;
1533 issue_modify_qp = 1;
1534 }
1535 break;
1536 case IB_QPS_RTR:
1537 if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) {
1538 ret = -EINVAL;
1539 goto exit;
1540 }
1541 info.arp_cache_idx_valid = true;
1542 info.cq_num_valid = true;
1543 info.next_iwarp_state = IRDMA_QP_STATE_RTR;
1544 issue_modify_qp = 1;
1545 break;
1546 case IB_QPS_RTS:
1547 if (iwqp->ibqp_state < IB_QPS_RTR ||
1548 iwqp->ibqp_state == IB_QPS_ERR) {
1549 ret = -EINVAL;
1550 goto exit;
1551 }
1552
1553 info.arp_cache_idx_valid = true;
1554 info.cq_num_valid = true;
1555 info.ord_valid = true;
1556 info.next_iwarp_state = IRDMA_QP_STATE_RTS;
1557 issue_modify_qp = 1;
1558 if (iwdev->push_mode && udata &&
1559 iwqp->sc_qp.push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX &&
1560 dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
1561 spin_unlock_irqrestore(&iwqp->lock, flags);
1562 irdma_alloc_push_page(iwqp);
1563 spin_lock_irqsave(&iwqp->lock, flags);
1564 }
1565 break;
1566 case IB_QPS_SQD:
1567 if (iwqp->iwarp_state == IRDMA_QP_STATE_SQD)
1568 goto exit;
1569
1570 if (iwqp->iwarp_state != IRDMA_QP_STATE_RTS) {
1571 ret = -EINVAL;
1572 goto exit;
1573 }
1574
1575 info.next_iwarp_state = IRDMA_QP_STATE_SQD;
1576 issue_modify_qp = 1;
1577 iwqp->suspend_pending = true;
1578 break;
1579 case IB_QPS_SQE:
1580 case IB_QPS_ERR:
1581 case IB_QPS_RESET:
1582 if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) {
1583 iwqp->ibqp_state = attr->qp_state;
1584 spin_unlock_irqrestore(&iwqp->lock, flags);
1585 if (udata && udata->inlen) {
1586 irdma_flush_wqes(iwqp,
1587 (ureq.sq_flush ? IRDMA_FLUSH_SQ : 0) |
1588 (ureq.rq_flush ? IRDMA_FLUSH_RQ : 0) |
1589 IRDMA_REFLUSH);
1590 }
1591 return 0;
1592 }
1593
1594 info.next_iwarp_state = IRDMA_QP_STATE_ERROR;
1595 issue_modify_qp = 1;
1596 break;
1597 default:
1598 ret = -EINVAL;
1599 goto exit;
1600 }
1601
1602 iwqp->ibqp_state = attr->qp_state;
1603 }
1604
1605 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
1606 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
1607 irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
1608 spin_unlock_irqrestore(&iwqp->lock, flags);
1609
1610 if (attr_mask & IB_QP_STATE) {
1611 if (issue_modify_qp) {
1612 ctx_info->rem_endpoint_idx = udp_info->arp_idx;
1613 if (irdma_hw_modify_qp(iwdev, iwqp, &info, true))
1614 return -EINVAL;
1615 if (info.next_iwarp_state == IRDMA_QP_STATE_SQD) {
1616 ret = irdma_wait_for_suspend(iwqp);
1617 if (ret)
1618 return ret;
1619 }
1620 spin_lock_irqsave(&iwqp->lock, flags);
1621 if (iwqp->iwarp_state == info.curr_iwarp_state) {
1622 iwqp->iwarp_state = info.next_iwarp_state;
1623 iwqp->ibqp_state = attr->qp_state;
1624 }
1625 if (iwqp->ibqp_state > IB_QPS_RTS &&
1626 !iwqp->flush_issued) {
1627 spin_unlock_irqrestore(&iwqp->lock, flags);
1628 irdma_flush_wqes(iwqp, IRDMA_FLUSH_SQ |
1629 IRDMA_FLUSH_RQ |
1630 IRDMA_FLUSH_WAIT);
1631 iwqp->flush_issued = 1;
1632 } else {
1633 spin_unlock_irqrestore(&iwqp->lock, flags);
1634 }
1635 } else {
1636 iwqp->ibqp_state = attr->qp_state;
1637 }
1638 if (udata && udata->outlen && dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
1639 struct irdma_ucontext *ucontext;
1640
1641 ucontext = rdma_udata_to_drv_context(udata,
1642 struct irdma_ucontext, ibucontext);
1643 if (iwqp->sc_qp.push_idx != IRDMA_INVALID_PUSH_PAGE_INDEX &&
1644 !iwqp->push_wqe_mmap_entry &&
1645 !irdma_setup_push_mmap_entries(ucontext, iwqp,
1646 &uresp.push_wqe_mmap_key, &uresp.push_db_mmap_key)) {
1647 uresp.push_valid = 1;
1648 uresp.push_offset = iwqp->sc_qp.push_offset;
1649 }
1650 ret = ib_respond_udata(udata, uresp);
1651 if (ret) {
1652 irdma_remove_push_mmap_entries(iwqp);
1653 return ret;
1654 }
1655 }
1656 }
1657
1658 return 0;
1659 exit:
1660 spin_unlock_irqrestore(&iwqp->lock, flags);
1661
1662 return ret;
1663 }
1664
1665 /**
1666 * irdma_modify_qp - modify qp request
1667 * @ibqp: qp's pointer for modify
1668 * @attr: access attributes
1669 * @attr_mask: state mask
1670 * @udata: user data
1671 */
irdma_modify_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)1672 int irdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
1673 struct ib_udata *udata)
1674 {
1675 #define IRDMA_MODIFY_QP_MIN_RESP_LEN offsetofend(struct irdma_modify_qp_resp, push_valid)
1676 struct irdma_qp *iwqp = to_iwqp(ibqp);
1677 struct irdma_device *iwdev = iwqp->iwdev;
1678 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
1679 struct irdma_qp_host_ctx_info *ctx_info;
1680 struct irdma_tcp_offload_info *tcp_info;
1681 struct irdma_iwarp_offload_info *offload_info;
1682 struct irdma_modify_qp_info info = {};
1683 struct irdma_modify_qp_resp uresp = {};
1684 struct irdma_modify_qp_req ureq = {};
1685 u8 issue_modify_qp = 0;
1686 u8 dont_wait = 0;
1687 int err;
1688 unsigned long flags;
1689
1690 err = ib_respond_empty_udata(udata);
1691 if (err)
1692 return err;
1693
1694 if (udata) {
1695 /* udata inlen/outlen can be 0 when supporting legacy libi40iw */
1696 if (udata->outlen && udata->outlen < IRDMA_MODIFY_QP_MIN_RESP_LEN)
1697 return -EINVAL;
1698
1699 if (udata->inlen) {
1700 err = ib_copy_validate_udata_in(udata, ureq, rsvd);
1701 if (err)
1702 return err;
1703 }
1704 }
1705
1706 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
1707 return -EOPNOTSUPP;
1708
1709 ctx_info = &iwqp->ctx_info;
1710 offload_info = &iwqp->iwarp_info;
1711 tcp_info = &iwqp->tcp_info;
1712 wait_event(iwqp->mod_qp_waitq, !atomic_read(&iwqp->hw_mod_qp_pend));
1713 ibdev_dbg(&iwdev->ibdev,
1714 "VERBS: caller: %pS qp_id=%d to_ibqpstate=%d ibqpstate=%d irdma_qpstate=%d last_aeq=%d hw_tcp_state=%d hw_iwarp_state=%d attr_mask=0x%x\n",
1715 __builtin_return_address(0), ibqp->qp_num, attr->qp_state,
1716 iwqp->ibqp_state, iwqp->iwarp_state, iwqp->last_aeq,
1717 iwqp->hw_tcp_state, iwqp->hw_iwarp_state, attr_mask);
1718
1719 spin_lock_irqsave(&iwqp->lock, flags);
1720 if (attr_mask & IB_QP_STATE) {
1721 info.curr_iwarp_state = iwqp->iwarp_state;
1722 switch (attr->qp_state) {
1723 case IB_QPS_INIT:
1724 case IB_QPS_RTR:
1725 if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) {
1726 err = -EINVAL;
1727 goto exit;
1728 }
1729
1730 if (iwqp->iwarp_state == IRDMA_QP_STATE_INVALID) {
1731 info.next_iwarp_state = IRDMA_QP_STATE_IDLE;
1732 issue_modify_qp = 1;
1733 }
1734 if (iwdev->push_mode && udata &&
1735 iwqp->sc_qp.push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX &&
1736 dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
1737 spin_unlock_irqrestore(&iwqp->lock, flags);
1738 irdma_alloc_push_page(iwqp);
1739 spin_lock_irqsave(&iwqp->lock, flags);
1740 }
1741 break;
1742 case IB_QPS_RTS:
1743 if (iwqp->iwarp_state > IRDMA_QP_STATE_RTS ||
1744 !iwqp->cm_id) {
1745 err = -EINVAL;
1746 goto exit;
1747 }
1748
1749 issue_modify_qp = 1;
1750 iwqp->hw_tcp_state = IRDMA_TCP_STATE_ESTABLISHED;
1751 iwqp->hte_added = 1;
1752 info.next_iwarp_state = IRDMA_QP_STATE_RTS;
1753 info.tcp_ctx_valid = true;
1754 info.ord_valid = true;
1755 info.arp_cache_idx_valid = true;
1756 info.cq_num_valid = true;
1757 break;
1758 case IB_QPS_SQD:
1759 if (iwqp->hw_iwarp_state > IRDMA_QP_STATE_RTS) {
1760 err = 0;
1761 goto exit;
1762 }
1763
1764 if (iwqp->iwarp_state == IRDMA_QP_STATE_CLOSING ||
1765 iwqp->iwarp_state < IRDMA_QP_STATE_RTS) {
1766 err = 0;
1767 goto exit;
1768 }
1769
1770 if (iwqp->iwarp_state > IRDMA_QP_STATE_CLOSING) {
1771 err = -EINVAL;
1772 goto exit;
1773 }
1774
1775 info.next_iwarp_state = IRDMA_QP_STATE_CLOSING;
1776 issue_modify_qp = 1;
1777 break;
1778 case IB_QPS_SQE:
1779 if (iwqp->iwarp_state >= IRDMA_QP_STATE_TERMINATE) {
1780 err = -EINVAL;
1781 goto exit;
1782 }
1783
1784 info.next_iwarp_state = IRDMA_QP_STATE_TERMINATE;
1785 issue_modify_qp = 1;
1786 break;
1787 case IB_QPS_ERR:
1788 case IB_QPS_RESET:
1789 if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) {
1790 iwqp->ibqp_state = attr->qp_state;
1791 spin_unlock_irqrestore(&iwqp->lock, flags);
1792 if (udata && udata->inlen) {
1793 irdma_flush_wqes(iwqp,
1794 (ureq.sq_flush ? IRDMA_FLUSH_SQ : 0) |
1795 (ureq.rq_flush ? IRDMA_FLUSH_RQ : 0) |
1796 IRDMA_REFLUSH);
1797 }
1798 return 0;
1799 }
1800
1801 if (iwqp->sc_qp.term_flags) {
1802 spin_unlock_irqrestore(&iwqp->lock, flags);
1803 irdma_terminate_del_timer(&iwqp->sc_qp);
1804 spin_lock_irqsave(&iwqp->lock, flags);
1805 }
1806 info.next_iwarp_state = IRDMA_QP_STATE_ERROR;
1807 if (iwqp->hw_tcp_state > IRDMA_TCP_STATE_CLOSED &&
1808 iwdev->iw_status &&
1809 iwqp->hw_tcp_state != IRDMA_TCP_STATE_TIME_WAIT)
1810 info.reset_tcp_conn = true;
1811 else
1812 dont_wait = 1;
1813
1814 issue_modify_qp = 1;
1815 info.next_iwarp_state = IRDMA_QP_STATE_ERROR;
1816 break;
1817 default:
1818 err = -EINVAL;
1819 goto exit;
1820 }
1821
1822 iwqp->ibqp_state = attr->qp_state;
1823 }
1824 if (attr_mask & IB_QP_ACCESS_FLAGS) {
1825 ctx_info->iwarp_info_valid = true;
1826 if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE)
1827 offload_info->wr_rdresp_en = true;
1828 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
1829 offload_info->wr_rdresp_en = true;
1830 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
1831 offload_info->rd_en = true;
1832 }
1833
1834 if (ctx_info->iwarp_info_valid) {
1835 ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id;
1836 ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id;
1837 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info);
1838 }
1839 spin_unlock_irqrestore(&iwqp->lock, flags);
1840
1841 if (attr_mask & IB_QP_STATE) {
1842 if (issue_modify_qp) {
1843 ctx_info->rem_endpoint_idx = tcp_info->arp_idx;
1844 if (irdma_hw_modify_qp(iwdev, iwqp, &info, true))
1845 return -EINVAL;
1846 }
1847
1848 spin_lock_irqsave(&iwqp->lock, flags);
1849 if (iwqp->iwarp_state == info.curr_iwarp_state) {
1850 iwqp->iwarp_state = info.next_iwarp_state;
1851 iwqp->ibqp_state = attr->qp_state;
1852 }
1853 spin_unlock_irqrestore(&iwqp->lock, flags);
1854 }
1855
1856 if (issue_modify_qp && iwqp->ibqp_state > IB_QPS_RTS) {
1857 if (dont_wait) {
1858 if (iwqp->hw_tcp_state) {
1859 spin_lock_irqsave(&iwqp->lock, flags);
1860 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSED;
1861 iwqp->last_aeq = IRDMA_AE_RESET_SENT;
1862 spin_unlock_irqrestore(&iwqp->lock, flags);
1863 }
1864 irdma_cm_disconn(iwqp);
1865 } else {
1866 int close_timer_started;
1867
1868 spin_lock_irqsave(&iwdev->cm_core.ht_lock, flags);
1869
1870 if (iwqp->cm_node) {
1871 refcount_inc(&iwqp->cm_node->refcnt);
1872 spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags);
1873 close_timer_started = atomic_inc_return(&iwqp->close_timer_started);
1874 if (iwqp->cm_id && close_timer_started == 1)
1875 irdma_schedule_cm_timer(iwqp->cm_node,
1876 (struct irdma_puda_buf *)iwqp,
1877 IRDMA_TIMER_TYPE_CLOSE, 1, 0);
1878
1879 irdma_rem_ref_cm_node(iwqp->cm_node);
1880 } else {
1881 spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags);
1882 }
1883 }
1884 }
1885 if (attr_mask & IB_QP_STATE && udata && udata->outlen &&
1886 dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
1887 struct irdma_ucontext *ucontext;
1888
1889 ucontext = rdma_udata_to_drv_context(udata,
1890 struct irdma_ucontext, ibucontext);
1891 if (iwqp->sc_qp.push_idx != IRDMA_INVALID_PUSH_PAGE_INDEX &&
1892 !iwqp->push_wqe_mmap_entry &&
1893 !irdma_setup_push_mmap_entries(ucontext, iwqp,
1894 &uresp.push_wqe_mmap_key, &uresp.push_db_mmap_key)) {
1895 uresp.push_valid = 1;
1896 uresp.push_offset = iwqp->sc_qp.push_offset;
1897 }
1898
1899 err = ib_respond_udata(udata, uresp);
1900 if (err) {
1901 irdma_remove_push_mmap_entries(iwqp);
1902 return err;
1903 }
1904 }
1905
1906 return 0;
1907 exit:
1908 spin_unlock_irqrestore(&iwqp->lock, flags);
1909
1910 return err;
1911 }
1912
1913 /**
1914 * irdma_srq_free_rsrc - free up resources for srq
1915 * @rf: RDMA PCI function
1916 * @iwsrq: srq ptr
1917 */
irdma_srq_free_rsrc(struct irdma_pci_f * rf,struct irdma_srq * iwsrq)1918 static void irdma_srq_free_rsrc(struct irdma_pci_f *rf, struct irdma_srq *iwsrq)
1919 {
1920 struct irdma_sc_srq *srq = &iwsrq->sc_srq;
1921
1922 if (!iwsrq->user_mode) {
1923 dma_free_coherent(rf->sc_dev.hw->device, iwsrq->kmem.size,
1924 iwsrq->kmem.va, iwsrq->kmem.pa);
1925 iwsrq->kmem.va = NULL;
1926 } else {
1927 /* Not called in any failure path, so iwpbl is valid. */
1928 struct irdma_mr *iwmr = iwsrq->iwpbl->iwmr;
1929
1930 refcount_dec(&iwmr->user_ring_refs);
1931 }
1932
1933 irdma_free_rsrc(rf, rf->allocated_srqs, srq->srq_uk.srq_id);
1934 }
1935
1936 /**
1937 * irdma_cq_free_rsrc - free up resources for cq
1938 * @rf: RDMA PCI function
1939 * @iwcq: cq ptr
1940 */
irdma_cq_free_rsrc(struct irdma_pci_f * rf,struct irdma_cq * iwcq)1941 static void irdma_cq_free_rsrc(struct irdma_pci_f *rf, struct irdma_cq *iwcq)
1942 {
1943 struct irdma_sc_cq *cq = &iwcq->sc_cq;
1944
1945 if (!iwcq->user_mode) {
1946 dma_free_coherent(rf->sc_dev.hw->device, iwcq->kmem.size,
1947 iwcq->kmem.va, iwcq->kmem.pa);
1948 iwcq->kmem.va = NULL;
1949 dma_free_coherent(rf->sc_dev.hw->device,
1950 iwcq->kmem_shadow.size,
1951 iwcq->kmem_shadow.va, iwcq->kmem_shadow.pa);
1952 iwcq->kmem_shadow.va = NULL;
1953 } else {
1954 struct irdma_mr *iwmr;
1955
1956 /* May be called in a failure path before iwpbl is valid. */
1957 if (iwcq->iwpbl) {
1958 iwmr = iwcq->iwpbl->iwmr;
1959
1960 refcount_dec(&iwmr->user_ring_refs);
1961 }
1962
1963 if (iwcq->iwpbl_shadow) {
1964 iwmr = iwcq->iwpbl_shadow->iwmr;
1965
1966 refcount_dec(&iwmr->user_ring_refs);
1967 }
1968 }
1969
1970 irdma_free_rsrc(rf, rf->allocated_cqs, cq->cq_uk.cq_id);
1971 }
1972
1973 /**
1974 * irdma_free_cqbuf - worker to free a cq buffer
1975 * @work: provides access to the cq buffer to free
1976 */
irdma_free_cqbuf(struct work_struct * work)1977 static void irdma_free_cqbuf(struct work_struct *work)
1978 {
1979 struct irdma_cq_buf *cq_buf = container_of(work, struct irdma_cq_buf, work);
1980
1981 dma_free_coherent(cq_buf->hw->device, cq_buf->kmem_buf.size,
1982 cq_buf->kmem_buf.va, cq_buf->kmem_buf.pa);
1983 cq_buf->kmem_buf.va = NULL;
1984 kfree(cq_buf);
1985 }
1986
1987 /**
1988 * irdma_process_resize_list - remove resized cq buffers from the resize_list
1989 * @iwcq: cq which owns the resize_list
1990 * @iwdev: irdma device
1991 * @lcqe_buf: the buffer where the last cqe is received
1992 */
irdma_process_resize_list(struct irdma_cq * iwcq,struct irdma_device * iwdev,struct irdma_cq_buf * lcqe_buf)1993 static int irdma_process_resize_list(struct irdma_cq *iwcq,
1994 struct irdma_device *iwdev,
1995 struct irdma_cq_buf *lcqe_buf)
1996 {
1997 struct list_head *tmp_node, *list_node;
1998 struct irdma_cq_buf *cq_buf;
1999 int cnt = 0;
2000
2001 list_for_each_safe(list_node, tmp_node, &iwcq->resize_list) {
2002 cq_buf = list_entry(list_node, struct irdma_cq_buf, list);
2003 if (cq_buf == lcqe_buf)
2004 return cnt;
2005
2006 list_del(&cq_buf->list);
2007 queue_work(iwdev->cleanup_wq, &cq_buf->work);
2008 cnt++;
2009 }
2010
2011 return cnt;
2012 }
2013
2014 /**
2015 * irdma_destroy_srq - destroy srq
2016 * @ibsrq: srq pointer
2017 * @udata: user data
2018 */
irdma_destroy_srq(struct ib_srq * ibsrq,struct ib_udata * udata)2019 static int irdma_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata)
2020 {
2021 struct irdma_device *iwdev = to_iwdev(ibsrq->device);
2022 struct irdma_srq *iwsrq = to_iwsrq(ibsrq);
2023 struct irdma_sc_srq *srq = &iwsrq->sc_srq;
2024 int ret;
2025
2026 ret = ib_no_udata_io(udata);
2027 if (ret)
2028 return ret;
2029
2030 irdma_srq_wq_destroy(iwdev->rf, srq);
2031 irdma_srq_free_rsrc(iwdev->rf, iwsrq);
2032 return 0;
2033 }
2034
2035 /**
2036 * irdma_destroy_cq - destroy cq
2037 * @ib_cq: cq pointer
2038 * @udata: user data
2039 */
irdma_destroy_cq(struct ib_cq * ib_cq,struct ib_udata * udata)2040 static int irdma_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
2041 {
2042 struct irdma_device *iwdev = to_iwdev(ib_cq->device);
2043 struct irdma_cq *iwcq = to_iwcq(ib_cq);
2044 struct irdma_sc_cq *cq = &iwcq->sc_cq;
2045 struct irdma_sc_dev *dev = cq->dev;
2046 struct irdma_sc_ceq *ceq = dev->ceq[cq->ceq_id];
2047 struct irdma_ceq *iwceq = container_of(ceq, struct irdma_ceq, sc_ceq);
2048 unsigned long flags;
2049 int ret;
2050
2051 ret = ib_no_udata_io(udata);
2052 if (ret)
2053 return ret;
2054
2055 spin_lock_irqsave(&iwcq->lock, flags);
2056 if (!list_empty(&iwcq->cmpl_generated))
2057 irdma_remove_cmpls_list(iwcq);
2058 if (!list_empty(&iwcq->resize_list))
2059 irdma_process_resize_list(iwcq, iwdev, NULL);
2060 spin_unlock_irqrestore(&iwcq->lock, flags);
2061
2062 irdma_cq_rem_ref(ib_cq);
2063 wait_for_completion(&iwcq->free_cq);
2064
2065 irdma_cq_wq_destroy(iwdev->rf, cq);
2066
2067 spin_lock_irqsave(&iwceq->ce_lock, flags);
2068 irdma_sc_cleanup_ceqes(cq, ceq);
2069 spin_unlock_irqrestore(&iwceq->ce_lock, flags);
2070 irdma_cq_free_rsrc(iwdev->rf, iwcq);
2071
2072 return 0;
2073 }
2074
2075 /**
2076 * irdma_resize_cq - resize cq
2077 * @ibcq: cq to be resized
2078 * @entries: desired cq size
2079 * @udata: user data
2080 */
irdma_resize_cq(struct ib_cq * ibcq,unsigned int entries,struct ib_udata * udata)2081 static int irdma_resize_cq(struct ib_cq *ibcq, unsigned int entries,
2082 struct ib_udata *udata)
2083 {
2084 struct irdma_cq *iwcq = to_iwcq(ibcq);
2085 struct irdma_sc_dev *dev = iwcq->sc_cq.dev;
2086 struct irdma_cqp_request *cqp_request;
2087 struct cqp_cmds_info *cqp_info;
2088 struct irdma_modify_cq_info *m_info;
2089 struct irdma_modify_cq_info info = {};
2090 struct irdma_dma_mem kmem_buf;
2091 struct irdma_cq_mr *cqmr_buf;
2092 struct irdma_pbl *iwpbl_buf = NULL;
2093 struct irdma_device *iwdev;
2094 struct irdma_pci_f *rf;
2095 struct irdma_cq_buf *cq_buf = NULL;
2096 unsigned long flags;
2097 u8 cqe_size;
2098 int ret;
2099
2100 iwdev = to_iwdev(ibcq->device);
2101 rf = iwdev->rf;
2102
2103 if (!(rf->sc_dev.hw_attrs.uk_attrs.feature_flags &
2104 IRDMA_FEATURE_CQ_RESIZE))
2105 return -EOPNOTSUPP;
2106
2107 if (entries > rf->max_cqe)
2108 return -EINVAL;
2109
2110 ret = ib_respond_empty_udata(udata);
2111 if (ret)
2112 return ret;
2113
2114 if (!iwcq->user_mode) {
2115 entries += 2;
2116
2117 if (!iwcq->sc_cq.cq_uk.avoid_mem_cflct &&
2118 dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
2119 entries *= 2;
2120
2121 if (entries & 1)
2122 entries += 1; /* cq size must be an even number */
2123
2124 cqe_size = iwcq->sc_cq.cq_uk.avoid_mem_cflct ? 64 : 32;
2125 if (entries * cqe_size == IRDMA_HW_PAGE_SIZE)
2126 entries += 2;
2127 }
2128
2129 info.cq_size = max(entries, 4);
2130
2131 if (info.cq_size == iwcq->sc_cq.cq_uk.cq_size - 1)
2132 return 0;
2133
2134 if (udata) {
2135 struct irdma_resize_cq_req req = {};
2136 struct irdma_ucontext *ucontext =
2137 rdma_udata_to_drv_context(udata, struct irdma_ucontext,
2138 ibucontext);
2139
2140 ret = ib_copy_validate_udata_in(udata, req, user_cq_buffer);
2141 if (ret)
2142 return ret;
2143
2144 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
2145 iwpbl_buf = irdma_get_pbl((unsigned long)req.user_cq_buffer,
2146 &ucontext->cq_reg_mem_list);
2147 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
2148
2149 if (!iwpbl_buf)
2150 return -ENOMEM;
2151
2152 cqmr_buf = &iwpbl_buf->cq_mr;
2153 if (iwpbl_buf->pbl_allocated) {
2154 info.virtual_map = true;
2155 info.pbl_chunk_size = 1;
2156 info.first_pm_pbl_idx = cqmr_buf->cq_pbl.idx;
2157 } else {
2158 info.cq_pa = cqmr_buf->cq_pbl.addr;
2159 }
2160 } else {
2161 /* Kmode CQ resize */
2162 int rsize;
2163
2164 rsize = info.cq_size * sizeof(struct irdma_cqe);
2165 kmem_buf.size = ALIGN(round_up(rsize, 256), 256);
2166 kmem_buf.va = dma_alloc_coherent(dev->hw->device,
2167 kmem_buf.size, &kmem_buf.pa,
2168 GFP_KERNEL);
2169 if (!kmem_buf.va)
2170 return -ENOMEM;
2171
2172 info.cq_base = kmem_buf.va;
2173 info.cq_pa = kmem_buf.pa;
2174 cq_buf = kzalloc_obj(*cq_buf);
2175 if (!cq_buf) {
2176 ret = -ENOMEM;
2177 goto error;
2178 }
2179 }
2180
2181 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
2182 if (!cqp_request) {
2183 ret = -ENOMEM;
2184 goto error;
2185 }
2186
2187 info.shadow_read_threshold = iwcq->sc_cq.shadow_read_threshold;
2188 info.cq_resize = true;
2189
2190 cqp_info = &cqp_request->info;
2191 m_info = &cqp_info->in.u.cq_modify.info;
2192 memcpy(m_info, &info, sizeof(*m_info));
2193
2194 cqp_info->cqp_cmd = IRDMA_OP_CQ_MODIFY;
2195 cqp_info->in.u.cq_modify.cq = &iwcq->sc_cq;
2196 cqp_info->in.u.cq_modify.scratch = (uintptr_t)cqp_request;
2197 cqp_info->post_sq = 1;
2198 ret = irdma_handle_cqp_op(rf, cqp_request);
2199 irdma_put_cqp_request(&rf->cqp, cqp_request);
2200 if (ret)
2201 goto error;
2202
2203 spin_lock_irqsave(&iwcq->lock, flags);
2204 if (udata) {
2205 struct irdma_pbl *old_iwpbl = iwcq->iwpbl;
2206
2207 /* Only update if the resize was successful. Otherwise, HW is
2208 * still pointing to the old PBL.
2209 */
2210 iwcq->iwpbl = iwpbl_buf;
2211 if (old_iwpbl) {
2212 struct irdma_mr *old_iwmr = old_iwpbl->iwmr;
2213
2214 refcount_dec(&old_iwmr->user_ring_refs);
2215 }
2216 }
2217 if (cq_buf) {
2218 cq_buf->kmem_buf = iwcq->kmem;
2219 cq_buf->hw = dev->hw;
2220 memcpy(&cq_buf->cq_uk, &iwcq->sc_cq.cq_uk, sizeof(cq_buf->cq_uk));
2221 INIT_WORK(&cq_buf->work, irdma_free_cqbuf);
2222 list_add_tail(&cq_buf->list, &iwcq->resize_list);
2223 iwcq->kmem = kmem_buf;
2224 }
2225
2226 irdma_sc_cq_resize(&iwcq->sc_cq, &info);
2227 ibcq->cqe = info.cq_size - 1;
2228 spin_unlock_irqrestore(&iwcq->lock, flags);
2229
2230 return 0;
2231 error:
2232 if (iwpbl_buf) {
2233 struct irdma_mr *iwmr = iwpbl_buf->iwmr;
2234
2235 refcount_dec(&iwmr->user_ring_refs);
2236 }
2237 if (!udata) {
2238 dma_free_coherent(dev->hw->device, kmem_buf.size, kmem_buf.va,
2239 kmem_buf.pa);
2240 kmem_buf.va = NULL;
2241 }
2242 kfree(cq_buf);
2243
2244 return ret;
2245 }
2246
2247 /**
2248 * irdma_srq_event - event notification for srq limit
2249 * @srq: shared srq struct
2250 */
irdma_srq_event(struct irdma_sc_srq * srq)2251 void irdma_srq_event(struct irdma_sc_srq *srq)
2252 {
2253 struct irdma_srq *iwsrq = container_of(srq, struct irdma_srq, sc_srq);
2254 struct ib_srq *ibsrq = &iwsrq->ibsrq;
2255 struct ib_event event;
2256
2257 srq->srq_limit = 0;
2258
2259 if (!ibsrq->event_handler)
2260 return;
2261
2262 event.device = ibsrq->device;
2263 event.element.port_num = 1;
2264 event.element.srq = ibsrq;
2265 event.event = IB_EVENT_SRQ_LIMIT_REACHED;
2266 ibsrq->event_handler(&event, ibsrq->srq_context);
2267 }
2268
2269 /**
2270 * irdma_modify_srq - modify srq request
2271 * @ibsrq: srq's pointer for modify
2272 * @attr: access attributes
2273 * @attr_mask: state mask
2274 * @udata: user data
2275 */
irdma_modify_srq(struct ib_srq * ibsrq,struct ib_srq_attr * attr,enum ib_srq_attr_mask attr_mask,struct ib_udata * udata)2276 static int irdma_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
2277 enum ib_srq_attr_mask attr_mask,
2278 struct ib_udata *udata)
2279 {
2280 struct irdma_device *iwdev = to_iwdev(ibsrq->device);
2281 struct irdma_srq *iwsrq = to_iwsrq(ibsrq);
2282 struct irdma_cqp_request *cqp_request;
2283 struct irdma_pci_f *rf = iwdev->rf;
2284 struct irdma_modify_srq_info *info;
2285 struct cqp_cmds_info *cqp_info;
2286 int status;
2287
2288 status = ib_no_udata_io(udata);
2289 if (status)
2290 return status;
2291
2292 if (attr_mask & IB_SRQ_MAX_WR)
2293 return -EINVAL;
2294
2295 if (!(attr_mask & IB_SRQ_LIMIT))
2296 return 0;
2297
2298 if (attr->srq_limit > iwsrq->sc_srq.srq_uk.srq_size)
2299 return -EINVAL;
2300
2301 /* Execute this cqp op synchronously, so we can update srq_limit
2302 * upon successful completion.
2303 */
2304 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
2305 if (!cqp_request)
2306 return -ENOMEM;
2307
2308 cqp_info = &cqp_request->info;
2309 info = &cqp_info->in.u.srq_modify.info;
2310 info->srq_limit = attr->srq_limit;
2311 if (info->srq_limit > 0xFFF)
2312 info->srq_limit = 0xFFF;
2313 info->arm_limit_event = 1;
2314
2315 cqp_info->cqp_cmd = IRDMA_OP_SRQ_MODIFY;
2316 cqp_info->post_sq = 1;
2317 cqp_info->in.u.srq_modify.srq = &iwsrq->sc_srq;
2318 cqp_info->in.u.srq_modify.scratch = (uintptr_t)cqp_request;
2319 status = irdma_handle_cqp_op(rf, cqp_request);
2320 irdma_put_cqp_request(&rf->cqp, cqp_request);
2321 if (status)
2322 return status;
2323
2324 iwsrq->sc_srq.srq_limit = info->srq_limit;
2325
2326 return 0;
2327 }
2328
irdma_setup_umode_srq(struct irdma_device * iwdev,struct irdma_srq * iwsrq,struct irdma_srq_init_info * info,struct ib_udata * udata)2329 static int irdma_setup_umode_srq(struct irdma_device *iwdev,
2330 struct irdma_srq *iwsrq,
2331 struct irdma_srq_init_info *info,
2332 struct ib_udata *udata)
2333 {
2334 struct irdma_create_srq_req req = {};
2335 struct irdma_ucontext *ucontext;
2336 struct irdma_srq_mr *srqmr;
2337 struct irdma_pbl *iwpbl;
2338 unsigned long flags;
2339 int ret;
2340
2341 iwsrq->user_mode = true;
2342 ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext,
2343 ibucontext);
2344
2345 ret = ib_copy_validate_udata_in(udata, req, user_shadow_area);
2346 if (ret)
2347 return ret;
2348
2349 spin_lock_irqsave(&ucontext->srq_reg_mem_list_lock, flags);
2350 iwpbl = irdma_get_pbl((unsigned long)req.user_srq_buf,
2351 &ucontext->srq_reg_mem_list);
2352 spin_unlock_irqrestore(&ucontext->srq_reg_mem_list_lock, flags);
2353 if (!iwpbl)
2354 return -EPROTO;
2355
2356 iwsrq->iwpbl = iwpbl;
2357 srqmr = &iwpbl->srq_mr;
2358
2359 if (iwpbl->pbl_allocated) {
2360 info->virtual_map = true;
2361 info->pbl_chunk_size = 1;
2362 info->first_pm_pbl_idx = srqmr->srq_pbl.idx;
2363 info->leaf_pbl_size = 1;
2364 } else {
2365 info->srq_pa = srqmr->srq_pbl.addr;
2366 }
2367 info->shadow_area_pa = srqmr->shadow;
2368
2369 return 0;
2370 }
2371
irdma_setup_kmode_srq(struct irdma_device * iwdev,struct irdma_srq * iwsrq,struct irdma_srq_init_info * info,u32 depth,u8 shift)2372 static int irdma_setup_kmode_srq(struct irdma_device *iwdev,
2373 struct irdma_srq *iwsrq,
2374 struct irdma_srq_init_info *info, u32 depth,
2375 u8 shift)
2376 {
2377 struct irdma_srq_uk_init_info *ukinfo = &info->srq_uk_init_info;
2378 struct irdma_dma_mem *mem = &iwsrq->kmem;
2379 u32 size, ring_size;
2380
2381 ring_size = depth * IRDMA_QP_WQE_MIN_SIZE;
2382 size = ring_size + (IRDMA_SHADOW_AREA_SIZE << 3);
2383
2384 mem->size = ALIGN(size, 256);
2385 mem->va = dma_alloc_coherent(iwdev->rf->hw.device, mem->size,
2386 &mem->pa, GFP_KERNEL);
2387 if (!mem->va)
2388 return -ENOMEM;
2389
2390 ukinfo->srq = mem->va;
2391 ukinfo->srq_size = depth >> shift;
2392 ukinfo->shadow_area = mem->va + ring_size;
2393
2394 info->srq_pa = mem->pa;
2395 info->shadow_area_pa = info->srq_pa + ring_size;
2396
2397 return 0;
2398 }
2399
2400 /**
2401 * irdma_create_srq - create srq
2402 * @ibsrq: ib's srq pointer
2403 * @initattrs: attributes for srq
2404 * @udata: user data for create srq
2405 */
irdma_create_srq(struct ib_srq * ibsrq,struct ib_srq_init_attr * initattrs,struct ib_udata * udata)2406 static int irdma_create_srq(struct ib_srq *ibsrq,
2407 struct ib_srq_init_attr *initattrs,
2408 struct ib_udata *udata)
2409 {
2410 #define IRDMA_CREATE_SRQ_MIN_RESP_LEN offsetofend(struct irdma_create_srq_resp, srq_size)
2411 struct irdma_device *iwdev = to_iwdev(ibsrq->device);
2412 struct ib_srq_attr *attr = &initattrs->attr;
2413 struct irdma_pd *iwpd = to_iwpd(ibsrq->pd);
2414 struct irdma_srq *iwsrq = to_iwsrq(ibsrq);
2415 struct irdma_srq_uk_init_info *ukinfo;
2416 struct irdma_cqp_request *cqp_request;
2417 struct irdma_srq_init_info info = {};
2418 struct irdma_pci_f *rf = iwdev->rf;
2419 struct irdma_uk_attrs *uk_attrs;
2420 struct cqp_cmds_info *cqp_info;
2421 int err_code = 0;
2422 u32 depth;
2423 u8 shift;
2424
2425 uk_attrs = &rf->sc_dev.hw_attrs.uk_attrs;
2426 ukinfo = &info.srq_uk_init_info;
2427
2428 if (initattrs->srq_type != IB_SRQT_BASIC)
2429 return -EOPNOTSUPP;
2430
2431 if (udata && udata->outlen < IRDMA_CREATE_SRQ_MIN_RESP_LEN)
2432 return -EINVAL;
2433
2434 if (!(uk_attrs->feature_flags & IRDMA_FEATURE_SRQ) ||
2435 attr->max_sge > uk_attrs->max_hw_wq_frags)
2436 return -EINVAL;
2437
2438 refcount_set(&iwsrq->refcnt, 1);
2439 spin_lock_init(&iwsrq->lock);
2440 err_code = irdma_alloc_rsrc(rf, rf->allocated_srqs, rf->max_srq,
2441 &iwsrq->srq_num, &rf->next_srq);
2442 if (err_code)
2443 return err_code;
2444
2445 ukinfo->max_srq_frag_cnt = attr->max_sge;
2446 ukinfo->uk_attrs = uk_attrs;
2447 ukinfo->srq_id = iwsrq->srq_num;
2448
2449 irdma_get_wqe_shift(ukinfo->uk_attrs, ukinfo->max_srq_frag_cnt, 0,
2450 &shift);
2451
2452 err_code = irdma_get_srqdepth(ukinfo->uk_attrs, attr->max_wr,
2453 shift, &depth);
2454 if (err_code)
2455 return err_code;
2456
2457 /* Actual SRQ size in WRs for ring and HW */
2458 ukinfo->srq_size = depth >> shift;
2459
2460 /* Max postable WRs to SRQ */
2461 iwsrq->max_wr = (depth - IRDMA_RQ_RSVD) >> shift;
2462 attr->max_wr = iwsrq->max_wr;
2463
2464 if (udata)
2465 err_code = irdma_setup_umode_srq(iwdev, iwsrq, &info, udata);
2466 else
2467 err_code = irdma_setup_kmode_srq(iwdev, iwsrq, &info, depth,
2468 shift);
2469
2470 if (err_code)
2471 goto free_rsrc;
2472
2473 info.vsi = &iwdev->vsi;
2474 info.pd = &iwpd->sc_pd;
2475
2476 iwsrq->sc_srq.srq_uk.lock = &iwsrq->lock;
2477 err_code = irdma_sc_srq_init(&iwsrq->sc_srq, &info);
2478 if (err_code)
2479 goto free_dmem;
2480
2481 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
2482 if (!cqp_request) {
2483 err_code = -ENOMEM;
2484 goto free_dmem;
2485 }
2486
2487 cqp_info = &cqp_request->info;
2488 cqp_info->cqp_cmd = IRDMA_OP_SRQ_CREATE;
2489 cqp_info->post_sq = 1;
2490 cqp_info->in.u.srq_create.srq = &iwsrq->sc_srq;
2491 cqp_info->in.u.srq_create.scratch = (uintptr_t)cqp_request;
2492 err_code = irdma_handle_cqp_op(rf, cqp_request);
2493 irdma_put_cqp_request(&rf->cqp, cqp_request);
2494 if (err_code)
2495 goto free_dmem;
2496
2497 if (udata) {
2498 struct irdma_create_srq_resp resp = {};
2499
2500 resp.srq_id = iwsrq->srq_num;
2501 resp.srq_size = ukinfo->srq_size;
2502 err_code = ib_respond_udata(udata, resp);
2503 if (err_code)
2504 goto srq_destroy;
2505 }
2506
2507 return 0;
2508
2509 srq_destroy:
2510 irdma_srq_wq_destroy(rf, &iwsrq->sc_srq);
2511
2512 free_dmem:
2513 if (!iwsrq->user_mode)
2514 dma_free_coherent(rf->hw.device, iwsrq->kmem.size,
2515 iwsrq->kmem.va, iwsrq->kmem.pa);
2516 free_rsrc:
2517 if (iwsrq->user_mode && iwsrq->iwpbl) {
2518 struct irdma_mr *iwmr = iwsrq->iwpbl->iwmr;
2519
2520 refcount_dec(&iwmr->user_ring_refs);
2521 }
2522 irdma_free_rsrc(rf, rf->allocated_srqs, iwsrq->srq_num);
2523 return err_code;
2524 }
2525
2526 /**
2527 * irdma_query_srq - get SRQ attributes
2528 * @ibsrq: the SRQ to query
2529 * @attr: the attributes of the SRQ
2530 */
irdma_query_srq(struct ib_srq * ibsrq,struct ib_srq_attr * attr)2531 static int irdma_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr)
2532 {
2533 struct irdma_srq *iwsrq = to_iwsrq(ibsrq);
2534
2535 attr->max_wr = iwsrq->max_wr;
2536 attr->max_sge = iwsrq->sc_srq.srq_uk.max_srq_frag_cnt;
2537 attr->srq_limit = iwsrq->sc_srq.srq_limit;
2538
2539 return 0;
2540 }
2541
cq_validate_flags(u32 flags,u8 hw_rev)2542 static inline int cq_validate_flags(u32 flags, u8 hw_rev)
2543 {
2544 /* GEN1/2 does not support CQ create flags */
2545 if (hw_rev <= IRDMA_GEN_2)
2546 return flags ? -EOPNOTSUPP : 0;
2547
2548 return flags & ~IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION ? -EOPNOTSUPP : 0;
2549 }
2550
2551 /**
2552 * irdma_create_cq - create cq
2553 * @ibcq: CQ allocated
2554 * @attr: attributes for cq
2555 * @attrs: uverbs attribute bundle
2556 */
irdma_create_cq(struct ib_cq * ibcq,const struct ib_cq_init_attr * attr,struct uverbs_attr_bundle * attrs)2557 static int irdma_create_cq(struct ib_cq *ibcq,
2558 const struct ib_cq_init_attr *attr,
2559 struct uverbs_attr_bundle *attrs)
2560 {
2561 #define IRDMA_CREATE_CQ_MIN_RESP_LEN offsetofend(struct irdma_create_cq_resp, cq_size)
2562 struct ib_udata *udata = &attrs->driver_udata;
2563 struct ib_device *ibdev = ibcq->device;
2564 struct irdma_device *iwdev = to_iwdev(ibdev);
2565 struct irdma_pci_f *rf = iwdev->rf;
2566 struct irdma_cq *iwcq = to_iwcq(ibcq);
2567 u32 cq_num = 0;
2568 struct irdma_sc_cq *cq;
2569 struct irdma_sc_dev *dev = &rf->sc_dev;
2570 struct irdma_cq_init_info info = {};
2571 struct irdma_cqp_request *cqp_request;
2572 struct cqp_cmds_info *cqp_info;
2573 struct irdma_cq_uk_init_info *ukinfo = &info.cq_uk_init_info;
2574 unsigned long flags;
2575 int err_code;
2576 int entries = attr->cqe;
2577 bool cqe_64byte_ena;
2578 u8 cqe_size;
2579
2580 err_code = cq_validate_flags(attr->flags, dev->hw_attrs.uk_attrs.hw_rev);
2581 if (err_code)
2582 return err_code;
2583
2584 if (udata && udata->outlen < IRDMA_CREATE_CQ_MIN_RESP_LEN)
2585 return -EINVAL;
2586
2587 err_code = irdma_alloc_rsrc(rf, rf->allocated_cqs, rf->max_cq, &cq_num,
2588 &rf->next_cq);
2589 if (err_code)
2590 return err_code;
2591
2592 cq = &iwcq->sc_cq;
2593 cq->back_cq = iwcq;
2594 refcount_set(&iwcq->refcnt, 1);
2595 spin_lock_init(&iwcq->lock);
2596 INIT_LIST_HEAD(&iwcq->resize_list);
2597 INIT_LIST_HEAD(&iwcq->cmpl_generated);
2598 iwcq->cq_num = cq_num;
2599 iwcq->iwpbl = NULL;
2600 iwcq->iwpbl_shadow = NULL;
2601 info.dev = dev;
2602 ukinfo->cq_size = max(entries, 4);
2603 ukinfo->cq_id = cq_num;
2604 cqe_64byte_ena = dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_64_BYTE_CQE ?
2605 true : false;
2606 cqe_size = cqe_64byte_ena ? 64 : 32;
2607 ukinfo->avoid_mem_cflct = cqe_64byte_ena;
2608 iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size;
2609 if (attr->comp_vector < rf->ceqs_count)
2610 info.ceq_id = attr->comp_vector;
2611 info.ceq_id_valid = true;
2612 info.ceqe_mask = 1;
2613 info.type = IRDMA_CQ_TYPE_IWARP;
2614 info.vsi = &iwdev->vsi;
2615
2616 if (udata) {
2617 struct irdma_ucontext *ucontext;
2618 struct irdma_create_cq_req req = {};
2619 struct irdma_cq_mr *cqmr;
2620 struct irdma_cq_mr *cqmr_shadow;
2621
2622 iwcq->user_mode = true;
2623 ucontext =
2624 rdma_udata_to_drv_context(udata, struct irdma_ucontext,
2625 ibucontext);
2626 /* Even though the last member of struct irdma_create_cq_req
2627 * was always user_shadow_area, we need backwards compat with
2628 * the legacy i40iw struct i40iw_ucreate_cq which stopped
2629 * at user_cq_buffer.
2630 */
2631 err_code = ib_copy_validate_udata_in(udata, req, user_cq_buf);
2632 if (err_code)
2633 goto cq_free_rsrc;
2634
2635 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
2636 iwcq->iwpbl = irdma_get_pbl((unsigned long)req.user_cq_buf,
2637 &ucontext->cq_reg_mem_list);
2638 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
2639 if (!iwcq->iwpbl) {
2640 err_code = -EPROTO;
2641 goto cq_free_rsrc;
2642 }
2643
2644 cqmr = &iwcq->iwpbl->cq_mr;
2645
2646 if (rf->sc_dev.hw_attrs.uk_attrs.feature_flags &
2647 IRDMA_FEATURE_CQ_RESIZE) {
2648 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
2649 iwcq->iwpbl_shadow = irdma_get_pbl(
2650 (unsigned long)req.user_shadow_area,
2651 &ucontext->cq_reg_mem_list);
2652 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
2653
2654 if (!iwcq->iwpbl_shadow) {
2655 err_code = -EPROTO;
2656 goto cq_free_rsrc;
2657 }
2658 cqmr_shadow = &iwcq->iwpbl_shadow->cq_mr;
2659 info.shadow_area_pa = cqmr_shadow->cq_pbl.addr;
2660 } else {
2661 info.shadow_area_pa = cqmr->shadow;
2662 }
2663 if (iwcq->iwpbl->pbl_allocated) {
2664 info.virtual_map = true;
2665 info.pbl_chunk_size = 1;
2666 info.first_pm_pbl_idx = cqmr->cq_pbl.idx;
2667 } else {
2668 info.cq_base_pa = cqmr->cq_pbl.addr;
2669 }
2670 } else {
2671 /* Kmode allocations */
2672 int rsize;
2673
2674 if (entries < 1 || entries > rf->max_cqe) {
2675 err_code = -EINVAL;
2676 goto cq_free_rsrc;
2677 }
2678
2679 entries += 2;
2680 if (!cqe_64byte_ena && dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2)
2681 entries *= 2;
2682
2683 if (entries & 1)
2684 entries += 1; /* cq size must be an even number */
2685
2686 if (entries * cqe_size == IRDMA_HW_PAGE_SIZE)
2687 entries += 2;
2688
2689 ukinfo->cq_size = entries;
2690
2691 if (cqe_64byte_ena)
2692 rsize = info.cq_uk_init_info.cq_size * sizeof(struct irdma_extended_cqe);
2693 else
2694 rsize = info.cq_uk_init_info.cq_size * sizeof(struct irdma_cqe);
2695 iwcq->kmem.size = ALIGN(round_up(rsize, 256), 256);
2696 iwcq->kmem.va = dma_alloc_coherent(dev->hw->device,
2697 iwcq->kmem.size,
2698 &iwcq->kmem.pa, GFP_KERNEL);
2699 if (!iwcq->kmem.va) {
2700 err_code = -ENOMEM;
2701 goto cq_free_rsrc;
2702 }
2703
2704 iwcq->kmem_shadow.size = ALIGN(IRDMA_SHADOW_AREA_SIZE << 3,
2705 64);
2706 iwcq->kmem_shadow.va = dma_alloc_coherent(dev->hw->device,
2707 iwcq->kmem_shadow.size,
2708 &iwcq->kmem_shadow.pa,
2709 GFP_KERNEL);
2710 if (!iwcq->kmem_shadow.va) {
2711 err_code = -ENOMEM;
2712 goto cq_free_rsrc;
2713 }
2714 info.shadow_area_pa = iwcq->kmem_shadow.pa;
2715 ukinfo->shadow_area = iwcq->kmem_shadow.va;
2716 ukinfo->cq_base = iwcq->kmem.va;
2717 info.cq_base_pa = iwcq->kmem.pa;
2718 }
2719
2720 info.shadow_read_threshold = min(info.cq_uk_init_info.cq_size / 2,
2721 (u32)IRDMA_MAX_CQ_READ_THRESH);
2722
2723 if (irdma_sc_cq_init(cq, &info)) {
2724 ibdev_dbg(&iwdev->ibdev, "VERBS: init cq fail\n");
2725 err_code = -EPROTO;
2726 goto cq_free_rsrc;
2727 }
2728
2729 cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
2730 if (!cqp_request) {
2731 err_code = -ENOMEM;
2732 goto cq_free_rsrc;
2733 }
2734
2735 cqp_info = &cqp_request->info;
2736 cqp_info->cqp_cmd = IRDMA_OP_CQ_CREATE;
2737 cqp_info->post_sq = 1;
2738 cqp_info->in.u.cq_create.cq = cq;
2739 cqp_info->in.u.cq_create.check_overflow = true;
2740 cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
2741 err_code = irdma_handle_cqp_op(rf, cqp_request);
2742 irdma_put_cqp_request(&rf->cqp, cqp_request);
2743 if (err_code)
2744 goto cq_free_rsrc;
2745
2746 if (udata) {
2747 struct irdma_create_cq_resp resp = {};
2748
2749 resp.cq_id = info.cq_uk_init_info.cq_id;
2750 resp.cq_size = info.cq_uk_init_info.cq_size;
2751 err_code = ib_respond_udata(udata, resp);
2752 if (err_code)
2753 goto cq_destroy;
2754 }
2755
2756 init_completion(&iwcq->free_cq);
2757
2758 /* Populate table entry after CQ is fully created. */
2759 smp_store_release(&rf->cq_table[cq_num], iwcq);
2760
2761 return 0;
2762 cq_destroy:
2763 irdma_cq_wq_destroy(rf, cq);
2764 cq_free_rsrc:
2765 irdma_cq_free_rsrc(rf, iwcq);
2766
2767 return err_code;
2768 }
2769
2770 /**
2771 * irdma_get_mr_access - get hw MR access permissions from IB access flags
2772 * @access: IB access flags
2773 * @hw_rev: Hardware version
2774 */
irdma_get_mr_access(int access,u8 hw_rev)2775 static inline u16 irdma_get_mr_access(int access, u8 hw_rev)
2776 {
2777 u16 hw_access = 0;
2778
2779 hw_access |= (access & IB_ACCESS_LOCAL_WRITE) ?
2780 IRDMA_ACCESS_FLAGS_LOCALWRITE : 0;
2781 hw_access |= (access & IB_ACCESS_REMOTE_WRITE) ?
2782 IRDMA_ACCESS_FLAGS_REMOTEWRITE : 0;
2783 hw_access |= (access & IB_ACCESS_REMOTE_READ) ?
2784 IRDMA_ACCESS_FLAGS_REMOTEREAD : 0;
2785 if (hw_rev >= IRDMA_GEN_3) {
2786 hw_access |= (access & IB_ACCESS_MW_BIND) ?
2787 IRDMA_ACCESS_FLAGS_BIND_WINDOW : 0;
2788 }
2789 hw_access |= (access & IB_ZERO_BASED) ?
2790 IRDMA_ACCESS_FLAGS_ZERO_BASED : 0;
2791 hw_access |= IRDMA_ACCESS_FLAGS_LOCALREAD;
2792
2793 return hw_access;
2794 }
2795
2796 /**
2797 * irdma_free_stag - free stag resource
2798 * @iwdev: irdma device
2799 * @stag: stag to free
2800 */
irdma_free_stag(struct irdma_device * iwdev,u32 stag)2801 static void irdma_free_stag(struct irdma_device *iwdev, u32 stag)
2802 {
2803 u32 stag_idx;
2804
2805 stag_idx = (stag & iwdev->rf->mr_stagmask) >> IRDMA_CQPSQ_STAG_IDX_S;
2806 irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_mrs, stag_idx);
2807 }
2808
2809 /**
2810 * irdma_create_stag - create random stag
2811 * @iwdev: irdma device
2812 */
irdma_create_stag(struct irdma_device * iwdev)2813 static u32 irdma_create_stag(struct irdma_device *iwdev)
2814 {
2815 u32 stag = 0;
2816 u32 stag_index = 0;
2817 u32 next_stag_index;
2818 u32 driver_key;
2819 u32 random;
2820 u8 consumer_key;
2821 int ret;
2822
2823 get_random_bytes(&random, sizeof(random));
2824 consumer_key = (u8)random;
2825
2826 driver_key = random & ~iwdev->rf->mr_stagmask;
2827 next_stag_index = (random & iwdev->rf->mr_stagmask) >> 8;
2828 next_stag_index %= iwdev->rf->max_mr;
2829
2830 ret = irdma_alloc_rsrc(iwdev->rf, iwdev->rf->allocated_mrs,
2831 iwdev->rf->max_mr, &stag_index,
2832 &next_stag_index);
2833 if (ret)
2834 return stag;
2835 stag = stag_index << IRDMA_CQPSQ_STAG_IDX_S;
2836 stag |= driver_key;
2837 stag += (u32)consumer_key;
2838
2839 return stag;
2840 }
2841
2842 /**
2843 * irdma_next_pbl_addr - Get next pbl address
2844 * @pbl: pointer to a pble
2845 * @pinfo: info pointer
2846 * @idx: index
2847 */
irdma_next_pbl_addr(u64 * pbl,struct irdma_pble_info ** pinfo,u32 * idx)2848 static inline u64 *irdma_next_pbl_addr(u64 *pbl, struct irdma_pble_info **pinfo,
2849 u32 *idx)
2850 {
2851 *idx += 1;
2852 if (!(*pinfo) || *idx != (*pinfo)->cnt)
2853 return ++pbl;
2854 *idx = 0;
2855 (*pinfo)++;
2856
2857 return (*pinfo)->addr;
2858 }
2859
2860 /**
2861 * irdma_copy_user_pgaddrs - copy user page address to pble's os locally
2862 * @iwmr: iwmr for IB's user page addresses
2863 * @pbl: ple pointer to save 1 level or 0 level pble
2864 * @pbl_len: Max number of PBL entries to populate
2865 * @level: indicated level 0, 1 or 2
2866 */
irdma_copy_user_pgaddrs(struct irdma_mr * iwmr,u64 * pbl,u32 pbl_len,enum irdma_pble_level level)2867 static void irdma_copy_user_pgaddrs(struct irdma_mr *iwmr, u64 *pbl,
2868 u32 pbl_len, enum irdma_pble_level level)
2869 {
2870 struct ib_umem *region = iwmr->region;
2871 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
2872 struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
2873 struct irdma_pble_info *pinfo;
2874 struct ib_block_iter biter;
2875 u32 idx = 0;
2876
2877 if (!pbl_len)
2878 return;
2879
2880 pinfo = (level == PBLE_LEVEL_1) ? NULL : palloc->level2.leaf;
2881
2882 if (iwmr->type == IRDMA_MEMREG_TYPE_QP)
2883 iwpbl->qp_mr.sq_page = sg_page(region->sgt_append.sgt.sgl);
2884
2885 rdma_umem_for_each_dma_block(region, &biter, iwmr->page_size) {
2886 *pbl = rdma_block_iter_dma_address(&biter);
2887 if (!--pbl_len)
2888 break;
2889 pbl = irdma_next_pbl_addr(pbl, &pinfo, &idx);
2890 }
2891 }
2892
2893 /**
2894 * irdma_check_mem_contiguous - check if pbls stored in arr are contiguous
2895 * @arr: lvl1 pbl array
2896 * @npages: page count
2897 * @pg_size: page size
2898 *
2899 */
irdma_check_mem_contiguous(u64 * arr,u32 npages,u32 pg_size)2900 static bool irdma_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size)
2901 {
2902 u32 pg_idx;
2903
2904 for (pg_idx = 0; pg_idx < npages; pg_idx++) {
2905 if ((*arr + ((u64)pg_size * pg_idx)) != arr[pg_idx])
2906 return false;
2907 }
2908
2909 return true;
2910 }
2911
2912 /**
2913 * irdma_check_mr_contiguous - check if MR is physically contiguous
2914 * @palloc: pbl allocation struct
2915 * @pg_size: page size
2916 */
irdma_check_mr_contiguous(struct irdma_pble_alloc * palloc,u32 pg_size)2917 static bool irdma_check_mr_contiguous(struct irdma_pble_alloc *palloc,
2918 u32 pg_size)
2919 {
2920 struct irdma_pble_level2 *lvl2 = &palloc->level2;
2921 struct irdma_pble_info *leaf = lvl2->leaf;
2922 u64 *arr = NULL;
2923 u64 *start_addr = NULL;
2924 int i;
2925 bool ret;
2926
2927 if (palloc->level == PBLE_LEVEL_1) {
2928 arr = palloc->level1.addr;
2929 ret = irdma_check_mem_contiguous(arr, palloc->total_cnt,
2930 pg_size);
2931 return ret;
2932 }
2933
2934 start_addr = leaf->addr;
2935
2936 for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) {
2937 arr = leaf->addr;
2938 if ((*start_addr + ((u64)i * pg_size * PBLE_PER_PAGE)) != *arr)
2939 return false;
2940 ret = irdma_check_mem_contiguous(arr, leaf->cnt, pg_size);
2941 if (!ret)
2942 return false;
2943 }
2944
2945 return true;
2946 }
2947
2948 /**
2949 * irdma_setup_pbles - copy user pg address to pble's
2950 * @rf: RDMA PCI function
2951 * @iwmr: mr pointer for this memory registration
2952 * @lvl: requested pble levels
2953 */
irdma_setup_pbles(struct irdma_pci_f * rf,struct irdma_mr * iwmr,u8 lvl)2954 static int irdma_setup_pbles(struct irdma_pci_f *rf, struct irdma_mr *iwmr,
2955 u8 lvl)
2956 {
2957 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
2958 struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
2959 struct irdma_pble_info *pinfo;
2960 u64 *pbl;
2961 int status;
2962 enum irdma_pble_level level = PBLE_LEVEL_1;
2963 u32 pbl_len;
2964
2965 if (lvl) {
2966 status = irdma_get_pble(rf->pble_rsrc, palloc, iwmr->page_cnt,
2967 lvl);
2968 if (status)
2969 return status;
2970
2971 pbl_len = palloc->total_cnt;
2972 iwpbl->pbl_allocated = true;
2973 level = palloc->level;
2974 pinfo = (level == PBLE_LEVEL_1) ? &palloc->level1 :
2975 palloc->level2.leaf;
2976 pbl = pinfo->addr;
2977 } else {
2978 pbl_len = IRDMA_MAX_SAVED_PHY_PGADDR;
2979 pbl = iwmr->pgaddrmem;
2980 }
2981
2982 irdma_copy_user_pgaddrs(iwmr, pbl, pbl_len, level);
2983
2984 if (lvl)
2985 iwmr->pgaddrmem[0] = *pbl;
2986
2987 return 0;
2988 }
2989
2990 /**
2991 * irdma_handle_q_mem - handle memory for qp and cq
2992 * @iwdev: irdma device
2993 * @req: information for q memory management
2994 * @iwpbl: pble struct
2995 * @lvl: pble level mask
2996 */
irdma_handle_q_mem(struct irdma_device * iwdev,struct irdma_mem_reg_req * req,struct irdma_pbl * iwpbl,u8 lvl)2997 static int irdma_handle_q_mem(struct irdma_device *iwdev,
2998 struct irdma_mem_reg_req *req,
2999 struct irdma_pbl *iwpbl, u8 lvl)
3000 {
3001 struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
3002 struct irdma_mr *iwmr = iwpbl->iwmr;
3003 struct irdma_qp_mr *qpmr = &iwpbl->qp_mr;
3004 struct irdma_cq_mr *cqmr = &iwpbl->cq_mr;
3005 struct irdma_srq_mr *srqmr = &iwpbl->srq_mr;
3006 struct irdma_hmc_pble *hmc_p;
3007 u64 *arr = iwmr->pgaddrmem;
3008 u32 pg_size, total;
3009 int err = 0;
3010 bool ret = true;
3011
3012 pg_size = iwmr->page_size;
3013 err = irdma_setup_pbles(iwdev->rf, iwmr, lvl);
3014 if (err)
3015 return err;
3016
3017 if (lvl)
3018 arr = palloc->level1.addr;
3019
3020 switch (iwmr->type) {
3021 case IRDMA_MEMREG_TYPE_QP:
3022 total = req->sq_pages + req->rq_pages;
3023 hmc_p = &qpmr->sq_pbl;
3024 qpmr->shadow = (dma_addr_t)arr[total];
3025 /* Need to use physical address for RQ of QP
3026 * in case it is associated with SRQ.
3027 */
3028 qpmr->rq_pa = (dma_addr_t)arr[req->sq_pages];
3029 if (lvl) {
3030 ret = irdma_check_mem_contiguous(arr, req->sq_pages,
3031 pg_size);
3032 if (ret)
3033 ret = irdma_check_mem_contiguous(&arr[req->sq_pages],
3034 req->rq_pages,
3035 pg_size);
3036 }
3037
3038 if (!ret) {
3039 hmc_p->idx = palloc->level1.idx;
3040 hmc_p = &qpmr->rq_pbl;
3041 hmc_p->idx = palloc->level1.idx + req->sq_pages;
3042 } else {
3043 hmc_p->addr = arr[0];
3044 hmc_p = &qpmr->rq_pbl;
3045 hmc_p->addr = arr[req->sq_pages];
3046 }
3047 break;
3048 case IRDMA_MEMREG_TYPE_SRQ:
3049 hmc_p = &srqmr->srq_pbl;
3050 srqmr->shadow = (dma_addr_t)arr[req->rq_pages];
3051 if (lvl)
3052 ret = irdma_check_mem_contiguous(arr, req->rq_pages,
3053 pg_size);
3054
3055 if (!ret)
3056 hmc_p->idx = palloc->level1.idx;
3057 else
3058 hmc_p->addr = arr[0];
3059 break;
3060 case IRDMA_MEMREG_TYPE_CQ:
3061 hmc_p = &cqmr->cq_pbl;
3062
3063 if (!(iwdev->rf->sc_dev.hw_attrs.uk_attrs.feature_flags &
3064 IRDMA_FEATURE_CQ_RESIZE))
3065 cqmr->shadow = (dma_addr_t)arr[req->cq_pages];
3066
3067 if (lvl)
3068 ret = irdma_check_mem_contiguous(arr, req->cq_pages,
3069 pg_size);
3070
3071 if (!ret)
3072 hmc_p->idx = palloc->level1.idx;
3073 else
3074 hmc_p->addr = arr[0];
3075 break;
3076 default:
3077 ibdev_dbg(&iwdev->ibdev, "VERBS: MR type error\n");
3078 err = -EINVAL;
3079 }
3080
3081 if (lvl && ret) {
3082 irdma_free_pble(iwdev->rf->pble_rsrc, palloc);
3083 iwpbl->pbl_allocated = false;
3084 }
3085
3086 return err;
3087 }
3088
3089 /**
3090 * irdma_hw_alloc_mw - create the hw memory window
3091 * @iwdev: irdma device
3092 * @iwmr: pointer to memory window info
3093 */
irdma_hw_alloc_mw(struct irdma_device * iwdev,struct irdma_mr * iwmr)3094 static int irdma_hw_alloc_mw(struct irdma_device *iwdev, struct irdma_mr *iwmr)
3095 {
3096 struct irdma_mw_alloc_info *info;
3097 struct irdma_pd *iwpd = to_iwpd(iwmr->ibmr.pd);
3098 struct irdma_cqp_request *cqp_request;
3099 struct cqp_cmds_info *cqp_info;
3100 int status;
3101
3102 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
3103 if (!cqp_request)
3104 return -ENOMEM;
3105
3106 cqp_info = &cqp_request->info;
3107 info = &cqp_info->in.u.mw_alloc.info;
3108 memset(info, 0, sizeof(*info));
3109 if (iwmr->ibmw.type == IB_MW_TYPE_1)
3110 info->mw_wide = true;
3111
3112 info->page_size = PAGE_SIZE;
3113 info->mw_stag_index = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S;
3114 info->pd_id = iwpd->sc_pd.pd_id;
3115 info->remote_access = true;
3116 cqp_info->cqp_cmd = IRDMA_OP_MW_ALLOC;
3117 cqp_info->post_sq = 1;
3118 cqp_info->in.u.mw_alloc.dev = &iwdev->rf->sc_dev;
3119 cqp_info->in.u.mw_alloc.scratch = (uintptr_t)cqp_request;
3120 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
3121 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
3122
3123 return status;
3124 }
3125
3126 /**
3127 * irdma_alloc_mw - Allocate memory window
3128 * @ibmw: Memory Window
3129 * @udata: user data pointer
3130 */
irdma_alloc_mw(struct ib_mw * ibmw,struct ib_udata * udata)3131 static int irdma_alloc_mw(struct ib_mw *ibmw, struct ib_udata *udata)
3132 {
3133 struct irdma_device *iwdev = to_iwdev(ibmw->device);
3134 struct irdma_mr *iwmr = to_iwmw(ibmw);
3135 int err_code;
3136 u32 stag;
3137
3138 err_code = ib_no_udata_io(udata);
3139 if (err_code)
3140 return err_code;
3141
3142 stag = irdma_create_stag(iwdev);
3143 if (!stag)
3144 return -ENOMEM;
3145
3146 iwmr->stag = stag;
3147 ibmw->rkey = stag;
3148
3149 err_code = irdma_hw_alloc_mw(iwdev, iwmr);
3150 if (err_code) {
3151 irdma_free_stag(iwdev, stag);
3152 return err_code;
3153 }
3154
3155 return 0;
3156 }
3157
3158 /**
3159 * irdma_dealloc_mw - Dealloc memory window
3160 * @ibmw: memory window structure.
3161 */
irdma_dealloc_mw(struct ib_mw * ibmw)3162 static int irdma_dealloc_mw(struct ib_mw *ibmw)
3163 {
3164 struct ib_pd *ibpd = ibmw->pd;
3165 struct irdma_pd *iwpd = to_iwpd(ibpd);
3166 struct irdma_mr *iwmr = to_iwmr((struct ib_mr *)ibmw);
3167 struct irdma_device *iwdev = to_iwdev(ibmw->device);
3168 struct irdma_cqp_request *cqp_request;
3169 struct cqp_cmds_info *cqp_info;
3170 struct irdma_dealloc_stag_info *info;
3171
3172 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
3173 if (!cqp_request)
3174 return -ENOMEM;
3175
3176 cqp_info = &cqp_request->info;
3177 info = &cqp_info->in.u.dealloc_stag.info;
3178 memset(info, 0, sizeof(*info));
3179 info->pd_id = iwpd->sc_pd.pd_id;
3180 info->stag_idx = ibmw->rkey >> IRDMA_CQPSQ_STAG_IDX_S;
3181 info->mr = false;
3182 cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG;
3183 cqp_info->post_sq = 1;
3184 cqp_info->in.u.dealloc_stag.dev = &iwdev->rf->sc_dev;
3185 cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
3186 irdma_handle_cqp_op(iwdev->rf, cqp_request);
3187 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
3188 irdma_free_stag(iwdev, iwmr->stag);
3189
3190 return 0;
3191 }
3192
3193 /**
3194 * irdma_hw_alloc_stag - cqp command to allocate stag
3195 * @iwdev: irdma device
3196 * @iwmr: irdma mr pointer
3197 */
irdma_hw_alloc_stag(struct irdma_device * iwdev,struct irdma_mr * iwmr)3198 static int irdma_hw_alloc_stag(struct irdma_device *iwdev,
3199 struct irdma_mr *iwmr)
3200 {
3201 struct irdma_allocate_stag_info *info;
3202 struct ib_pd *pd = iwmr->ibmr.pd;
3203 struct irdma_pd *iwpd = to_iwpd(pd);
3204 int status;
3205 struct irdma_cqp_request *cqp_request;
3206 struct cqp_cmds_info *cqp_info;
3207
3208 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
3209 if (!cqp_request)
3210 return -ENOMEM;
3211
3212 cqp_info = &cqp_request->info;
3213 info = &cqp_info->in.u.alloc_stag.info;
3214 info->page_size = PAGE_SIZE;
3215 info->stag_idx = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S;
3216 info->pd_id = iwpd->sc_pd.pd_id;
3217 info->total_len = iwmr->len;
3218 info->remote_access = true;
3219 cqp_info->cqp_cmd = IRDMA_OP_ALLOC_STAG;
3220 cqp_info->post_sq = 1;
3221 cqp_info->in.u.alloc_stag.dev = &iwdev->rf->sc_dev;
3222 cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request;
3223 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
3224 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
3225 if (status)
3226 return status;
3227
3228 iwmr->is_hwreg = true;
3229 return 0;
3230 }
3231
3232 /**
3233 * irdma_alloc_mr - register stag for fast memory registration
3234 * @pd: ibpd pointer
3235 * @mr_type: memory for stag registrion
3236 * @max_num_sg: man number of pages
3237 */
irdma_alloc_mr(struct ib_pd * pd,enum ib_mr_type mr_type,u32 max_num_sg)3238 static struct ib_mr *irdma_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
3239 u32 max_num_sg)
3240 {
3241 struct irdma_device *iwdev = to_iwdev(pd->device);
3242 struct irdma_pble_alloc *palloc;
3243 struct irdma_pbl *iwpbl;
3244 struct irdma_mr *iwmr;
3245 u32 stag;
3246 int err_code;
3247
3248 iwmr = kzalloc_obj(*iwmr);
3249 if (!iwmr)
3250 return ERR_PTR(-ENOMEM);
3251
3252 stag = irdma_create_stag(iwdev);
3253 if (!stag) {
3254 err_code = -ENOMEM;
3255 goto err;
3256 }
3257
3258 iwmr->stag = stag;
3259 iwmr->ibmr.rkey = stag;
3260 iwmr->ibmr.lkey = stag;
3261 iwmr->ibmr.pd = pd;
3262 iwmr->ibmr.device = pd->device;
3263 iwpbl = &iwmr->iwpbl;
3264 iwpbl->iwmr = iwmr;
3265 iwmr->type = IRDMA_MEMREG_TYPE_MEM;
3266 palloc = &iwpbl->pble_alloc;
3267 iwmr->page_cnt = max_num_sg;
3268 /* Use system PAGE_SIZE as the sg page sizes are unknown at this point */
3269 iwmr->len = max_num_sg * PAGE_SIZE;
3270 err_code = irdma_get_pble(iwdev->rf->pble_rsrc, palloc, iwmr->page_cnt,
3271 false);
3272 if (err_code)
3273 goto err_get_pble;
3274
3275 err_code = irdma_hw_alloc_stag(iwdev, iwmr);
3276 if (err_code)
3277 goto err_alloc_stag;
3278
3279 iwpbl->pbl_allocated = true;
3280
3281 return &iwmr->ibmr;
3282 err_alloc_stag:
3283 irdma_free_pble(iwdev->rf->pble_rsrc, palloc);
3284 err_get_pble:
3285 irdma_free_stag(iwdev, stag);
3286 err:
3287 kfree(iwmr);
3288
3289 return ERR_PTR(err_code);
3290 }
3291
3292 /**
3293 * irdma_set_page - populate pbl list for fmr
3294 * @ibmr: ib mem to access iwarp mr pointer
3295 * @addr: page dma address fro pbl list
3296 */
irdma_set_page(struct ib_mr * ibmr,u64 addr)3297 static int irdma_set_page(struct ib_mr *ibmr, u64 addr)
3298 {
3299 struct irdma_mr *iwmr = to_iwmr(ibmr);
3300 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
3301 struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
3302 u64 *pbl;
3303
3304 if (unlikely(iwmr->npages == iwmr->page_cnt))
3305 return -ENOMEM;
3306
3307 if (palloc->level == PBLE_LEVEL_2) {
3308 struct irdma_pble_info *palloc_info =
3309 palloc->level2.leaf + (iwmr->npages >> PBLE_512_SHIFT);
3310
3311 palloc_info->addr[iwmr->npages & (PBLE_PER_PAGE - 1)] = addr;
3312 } else {
3313 pbl = palloc->level1.addr;
3314 pbl[iwmr->npages] = addr;
3315 }
3316 iwmr->npages++;
3317
3318 return 0;
3319 }
3320
3321 /**
3322 * irdma_map_mr_sg - map of sg list for fmr
3323 * @ibmr: ib mem to access iwarp mr pointer
3324 * @sg: scatter gather list
3325 * @sg_nents: number of sg pages
3326 * @sg_offset: scatter gather list for fmr
3327 */
irdma_map_mr_sg(struct ib_mr * ibmr,struct scatterlist * sg,int sg_nents,unsigned int * sg_offset)3328 static int irdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
3329 int sg_nents, unsigned int *sg_offset)
3330 {
3331 struct irdma_mr *iwmr = to_iwmr(ibmr);
3332
3333 iwmr->npages = 0;
3334
3335 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, irdma_set_page);
3336 }
3337
3338 /**
3339 * irdma_hwreg_mr - send cqp command for memory registration
3340 * @iwdev: irdma device
3341 * @iwmr: irdma mr pointer
3342 * @access: access for MR
3343 */
irdma_hwreg_mr(struct irdma_device * iwdev,struct irdma_mr * iwmr,u16 access)3344 static int irdma_hwreg_mr(struct irdma_device *iwdev, struct irdma_mr *iwmr,
3345 u16 access)
3346 {
3347 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
3348 struct irdma_reg_ns_stag_info *stag_info;
3349 struct ib_pd *pd = iwmr->ibmr.pd;
3350 struct irdma_pd *iwpd = to_iwpd(pd);
3351 struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc;
3352 struct irdma_cqp_request *cqp_request;
3353 struct cqp_cmds_info *cqp_info;
3354 int ret;
3355
3356 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
3357 if (!cqp_request)
3358 return -ENOMEM;
3359
3360 cqp_info = &cqp_request->info;
3361 stag_info = &cqp_info->in.u.mr_reg_non_shared.info;
3362 stag_info->va = iwpbl->user_base;
3363 stag_info->stag_idx = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S;
3364 stag_info->stag_key = (u8)iwmr->stag;
3365 stag_info->total_len = iwmr->len;
3366 stag_info->access_rights = irdma_get_mr_access(access,
3367 iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev);
3368 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_ATOMIC_OPS)
3369 stag_info->remote_atomics_en = (access & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
3370 stag_info->pd_id = iwpd->sc_pd.pd_id;
3371 stag_info->all_memory = iwmr->dma_mr;
3372 if (stag_info->access_rights & IRDMA_ACCESS_FLAGS_ZERO_BASED)
3373 stag_info->addr_type = IRDMA_ADDR_TYPE_ZERO_BASED;
3374 else
3375 stag_info->addr_type = IRDMA_ADDR_TYPE_VA_BASED;
3376 stag_info->page_size = iwmr->page_size;
3377
3378 if (iwpbl->pbl_allocated) {
3379 if (palloc->level == PBLE_LEVEL_1) {
3380 stag_info->first_pm_pbl_index = palloc->level1.idx;
3381 stag_info->chunk_size = 1;
3382 } else {
3383 stag_info->first_pm_pbl_index = palloc->level2.root.idx;
3384 stag_info->chunk_size = 3;
3385 }
3386 } else {
3387 stag_info->reg_addr_pa = iwmr->pgaddrmem[0];
3388 }
3389
3390 cqp_info->cqp_cmd = IRDMA_OP_MR_REG_NON_SHARED;
3391 cqp_info->post_sq = 1;
3392 cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->rf->sc_dev;
3393 cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request;
3394 ret = irdma_handle_cqp_op(iwdev->rf, cqp_request);
3395 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
3396
3397 if (!ret)
3398 iwmr->is_hwreg = true;
3399
3400 return ret;
3401 }
3402
irdma_reg_user_mr_type_mem(struct irdma_mr * iwmr,int access,bool create_stag)3403 static int irdma_reg_user_mr_type_mem(struct irdma_mr *iwmr, int access,
3404 bool create_stag)
3405 {
3406 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
3407 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
3408 u32 stag = 0;
3409 u8 lvl;
3410 int err;
3411
3412 lvl = iwmr->page_cnt != 1 ? PBLE_LEVEL_1 | PBLE_LEVEL_2 : PBLE_LEVEL_0;
3413 iwmr->access = access;
3414
3415 err = irdma_setup_pbles(iwdev->rf, iwmr, lvl);
3416 if (err)
3417 return err;
3418
3419 if (lvl) {
3420 err = irdma_check_mr_contiguous(&iwpbl->pble_alloc,
3421 iwmr->page_size);
3422 if (err) {
3423 irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc);
3424 iwpbl->pbl_allocated = false;
3425 }
3426 }
3427
3428 if (create_stag) {
3429 stag = irdma_create_stag(iwdev);
3430 if (!stag) {
3431 err = -ENOMEM;
3432 goto free_pble;
3433 }
3434
3435 iwmr->stag = stag;
3436 iwmr->ibmr.rkey = stag;
3437 iwmr->ibmr.lkey = stag;
3438 }
3439
3440 err = irdma_hwreg_mr(iwdev, iwmr, access);
3441 if (err)
3442 goto err_hwreg;
3443
3444 return 0;
3445
3446 err_hwreg:
3447 if (stag)
3448 irdma_free_stag(iwdev, stag);
3449
3450 free_pble:
3451 if (iwpbl->pble_alloc.level != PBLE_LEVEL_0 && iwpbl->pbl_allocated)
3452 irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc);
3453
3454 return err;
3455 }
3456
irdma_alloc_iwmr(struct ib_umem * region,struct ib_pd * pd,u64 virt,enum irdma_memreg_type reg_type)3457 static struct irdma_mr *irdma_alloc_iwmr(struct ib_umem *region,
3458 struct ib_pd *pd, u64 virt,
3459 enum irdma_memreg_type reg_type)
3460 {
3461 struct irdma_device *iwdev = to_iwdev(pd->device);
3462 struct irdma_pbl *iwpbl;
3463 struct irdma_mr *iwmr;
3464 unsigned long pgsz_bitmap;
3465
3466 iwmr = kzalloc_obj(*iwmr);
3467 if (!iwmr)
3468 return ERR_PTR(-ENOMEM);
3469
3470 refcount_set(&iwmr->user_ring_refs, 1);
3471 iwpbl = &iwmr->iwpbl;
3472 iwpbl->iwmr = iwmr;
3473 iwmr->region = region;
3474 iwmr->ibmr.pd = pd;
3475 iwmr->ibmr.device = pd->device;
3476 iwmr->ibmr.iova = virt;
3477 iwmr->type = reg_type;
3478
3479 pgsz_bitmap = (reg_type == IRDMA_MEMREG_TYPE_MEM) ?
3480 iwdev->rf->sc_dev.hw_attrs.page_size_cap : SZ_4K;
3481
3482 iwmr->page_size = ib_umem_find_best_pgsz(region, pgsz_bitmap, virt);
3483 if (unlikely(!iwmr->page_size)) {
3484 kfree(iwmr);
3485 return ERR_PTR(-EOPNOTSUPP);
3486 }
3487
3488 iwmr->len = region->length;
3489 iwpbl->user_base = virt;
3490 iwmr->page_cnt = ib_umem_num_dma_blocks(region, iwmr->page_size);
3491
3492 return iwmr;
3493 }
3494
irdma_free_iwmr(struct irdma_mr * iwmr)3495 static void irdma_free_iwmr(struct irdma_mr *iwmr)
3496 {
3497 kfree(iwmr);
3498 }
3499
irdma_reg_user_mr_type_qp(struct irdma_mem_reg_req req,struct ib_udata * udata,struct irdma_mr * iwmr)3500 static int irdma_reg_user_mr_type_qp(struct irdma_mem_reg_req req,
3501 struct ib_udata *udata,
3502 struct irdma_mr *iwmr)
3503 {
3504 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
3505 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
3506 struct irdma_ucontext *ucontext = NULL;
3507 unsigned long flags;
3508 u32 total;
3509 int err;
3510 u8 lvl;
3511
3512 /* iWarp: Catch page not starting on OS page boundary */
3513 if (!rdma_protocol_roce(&iwdev->ibdev, 1) &&
3514 ib_umem_offset(iwmr->region))
3515 return -EINVAL;
3516
3517 total = req.sq_pages + req.rq_pages + 1;
3518 if (total > iwmr->page_cnt)
3519 return -EINVAL;
3520
3521 total = req.sq_pages + req.rq_pages;
3522 lvl = total > 2 ? PBLE_LEVEL_1 : PBLE_LEVEL_0;
3523 err = irdma_handle_q_mem(iwdev, &req, iwpbl, lvl);
3524 if (err)
3525 return err;
3526
3527 ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext,
3528 ibucontext);
3529 spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags);
3530 list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list);
3531 iwpbl->on_list = true;
3532 spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags);
3533
3534 return 0;
3535 }
3536
irdma_reg_user_mr_type_srq(struct irdma_mem_reg_req req,struct ib_udata * udata,struct irdma_mr * iwmr)3537 static int irdma_reg_user_mr_type_srq(struct irdma_mem_reg_req req,
3538 struct ib_udata *udata,
3539 struct irdma_mr *iwmr)
3540 {
3541 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
3542 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
3543 struct irdma_ucontext *ucontext;
3544 unsigned long flags;
3545 u32 total;
3546 int err;
3547 u8 lvl;
3548
3549 total = req.rq_pages + IRDMA_SHADOW_PGCNT;
3550 if (total > iwmr->page_cnt)
3551 return -EINVAL;
3552
3553 lvl = req.rq_pages > 1 ? PBLE_LEVEL_1 : PBLE_LEVEL_0;
3554 err = irdma_handle_q_mem(iwdev, &req, iwpbl, lvl);
3555 if (err)
3556 return err;
3557
3558 ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext,
3559 ibucontext);
3560 spin_lock_irqsave(&ucontext->srq_reg_mem_list_lock, flags);
3561 list_add_tail(&iwpbl->list, &ucontext->srq_reg_mem_list);
3562 iwpbl->on_list = true;
3563 spin_unlock_irqrestore(&ucontext->srq_reg_mem_list_lock, flags);
3564
3565 return 0;
3566 }
3567
irdma_reg_user_mr_type_cq(struct irdma_mem_reg_req req,struct ib_udata * udata,struct irdma_mr * iwmr)3568 static int irdma_reg_user_mr_type_cq(struct irdma_mem_reg_req req,
3569 struct ib_udata *udata,
3570 struct irdma_mr *iwmr)
3571 {
3572 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
3573 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
3574 struct irdma_ucontext *ucontext = NULL;
3575 u8 shadow_pgcnt = 1;
3576 unsigned long flags;
3577 u32 total;
3578 int err;
3579 u8 lvl;
3580
3581 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_CQ_RESIZE)
3582 shadow_pgcnt = 0;
3583 total = req.cq_pages + shadow_pgcnt;
3584 if (total > iwmr->page_cnt)
3585 return -EINVAL;
3586
3587 lvl = req.cq_pages > 1 ? PBLE_LEVEL_1 : PBLE_LEVEL_0;
3588 err = irdma_handle_q_mem(iwdev, &req, iwpbl, lvl);
3589 if (err)
3590 return err;
3591
3592 ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext,
3593 ibucontext);
3594 spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags);
3595 list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list);
3596 iwpbl->on_list = true;
3597 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
3598
3599 return 0;
3600 }
3601
3602 /**
3603 * irdma_reg_user_mr - Register a user memory region
3604 * @pd: ptr of pd
3605 * @start: virtual start address
3606 * @len: length of mr
3607 * @virt: virtual address
3608 * @access: access of mr
3609 * @dmah: dma handle
3610 * @udata: user data
3611 */
irdma_reg_user_mr(struct ib_pd * pd,u64 start,u64 len,u64 virt,int access,struct ib_dmah * dmah,struct ib_udata * udata)3612 static struct ib_mr *irdma_reg_user_mr(struct ib_pd *pd, u64 start, u64 len,
3613 u64 virt, int access,
3614 struct ib_dmah *dmah,
3615 struct ib_udata *udata)
3616 {
3617 struct irdma_device *iwdev = to_iwdev(pd->device);
3618 struct irdma_mem_reg_req req = {};
3619 struct ib_umem *region = NULL;
3620 struct irdma_mr *iwmr = NULL;
3621 int err;
3622
3623 if (dmah)
3624 return ERR_PTR(-EOPNOTSUPP);
3625
3626 err = ib_copy_validate_udata_in(udata, req, sq_pages);
3627 if (err)
3628 return ERR_PTR(err);
3629
3630 err = ib_respond_empty_udata(udata);
3631 if (err)
3632 return ERR_PTR(err);
3633
3634 if (len > iwdev->rf->sc_dev.hw_attrs.max_mr_size)
3635 return ERR_PTR(-EINVAL);
3636
3637 region = ib_umem_get_va(pd->device, start, len, access);
3638
3639 if (IS_ERR(region)) {
3640 ibdev_dbg(&iwdev->ibdev,
3641 "VERBS: Failed to create ib_umem region\n");
3642 return (struct ib_mr *)region;
3643 }
3644
3645 iwmr = irdma_alloc_iwmr(region, pd, virt, req.reg_type);
3646 if (IS_ERR(iwmr)) {
3647 ib_umem_release(region);
3648 return (struct ib_mr *)iwmr;
3649 }
3650
3651 switch (req.reg_type) {
3652 case IRDMA_MEMREG_TYPE_QP:
3653 err = irdma_reg_user_mr_type_qp(req, udata, iwmr);
3654 if (err)
3655 goto error;
3656
3657 break;
3658 case IRDMA_MEMREG_TYPE_SRQ:
3659 err = irdma_reg_user_mr_type_srq(req, udata, iwmr);
3660 if (err)
3661 goto error;
3662
3663 break;
3664 case IRDMA_MEMREG_TYPE_CQ:
3665 err = irdma_reg_user_mr_type_cq(req, udata, iwmr);
3666 if (err)
3667 goto error;
3668 break;
3669 case IRDMA_MEMREG_TYPE_MEM:
3670 err = irdma_reg_user_mr_type_mem(iwmr, access, true);
3671 if (err)
3672 goto error;
3673
3674 break;
3675 default:
3676 err = -EINVAL;
3677 goto error;
3678 }
3679
3680 return &iwmr->ibmr;
3681 error:
3682 ib_umem_release(region);
3683 irdma_free_iwmr(iwmr);
3684
3685 return ERR_PTR(err);
3686 }
3687
3688 static int irdma_hwdereg_mr(struct ib_mr *ib_mr);
3689
irdma_umem_dmabuf_revoke(void * priv)3690 static void irdma_umem_dmabuf_revoke(void *priv)
3691 {
3692 /* priv is guaranteed to be valid any time this callback is invoked
3693 * because we do not set the callback until after successful iwmr
3694 * allocation and initialization.
3695 */
3696 struct irdma_mr *iwmr = priv;
3697 int err;
3698
3699 /* Invalidate the key in hardware. This does not actually release the
3700 * key for potential reuse - that only occurs when the region is fully
3701 * deregistered.
3702 *
3703 * The irdma_hwdereg_mr call is a no-op if the region is not currently
3704 * registered with hardware.
3705 */
3706 err = irdma_hwdereg_mr(&iwmr->ibmr);
3707 if (err) {
3708 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
3709
3710 ibdev_err(&iwdev->ibdev, "dmabuf mr revoke failed %d", err);
3711 if (!iwdev->rf->reset) {
3712 iwdev->rf->reset = true;
3713 iwdev->rf->gen_ops.request_reset(iwdev->rf);
3714 }
3715 }
3716 }
3717
irdma_reg_user_mr_dmabuf(struct ib_pd * pd,u64 start,u64 len,u64 virt,int fd,int access,struct ib_dmah * dmah,struct uverbs_attr_bundle * attrs)3718 static struct ib_mr *irdma_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start,
3719 u64 len, u64 virt,
3720 int fd, int access,
3721 struct ib_dmah *dmah,
3722 struct uverbs_attr_bundle *attrs)
3723 {
3724 struct irdma_device *iwdev = to_iwdev(pd->device);
3725 struct ib_umem_dmabuf *umem_dmabuf;
3726 struct irdma_mr *iwmr;
3727 int err;
3728
3729 if (dmah)
3730 return ERR_PTR(-EOPNOTSUPP);
3731
3732 if (len > iwdev->rf->sc_dev.hw_attrs.max_mr_size)
3733 return ERR_PTR(-EINVAL);
3734
3735 umem_dmabuf =
3736 ib_umem_dmabuf_get_pinned_revocable_and_lock(pd->device, start,
3737 len, fd, access);
3738 if (IS_ERR(umem_dmabuf)) {
3739 ibdev_dbg(&iwdev->ibdev, "Failed to get dmabuf umem[%pe]\n",
3740 umem_dmabuf);
3741 return ERR_CAST(umem_dmabuf);
3742 }
3743
3744 iwmr = irdma_alloc_iwmr(&umem_dmabuf->umem, pd, virt, IRDMA_MEMREG_TYPE_MEM);
3745 if (IS_ERR(iwmr)) {
3746 err = PTR_ERR(iwmr);
3747 goto err_release;
3748 }
3749
3750 err = irdma_reg_user_mr_type_mem(iwmr, access, true);
3751 if (err)
3752 goto err_iwmr;
3753
3754 ib_umem_dmabuf_set_revoke_locked(umem_dmabuf, irdma_umem_dmabuf_revoke,
3755 iwmr);
3756 ib_umem_dmabuf_revoke_unlock(umem_dmabuf);
3757 return &iwmr->ibmr;
3758
3759 err_iwmr:
3760 irdma_free_iwmr(iwmr);
3761
3762 err_release:
3763 ib_umem_dmabuf_revoke_unlock(umem_dmabuf);
3764
3765 /* Will result in a call to revoke, but driver callback is not set and
3766 * is therefore skipped.
3767 */
3768 ib_umem_release(&umem_dmabuf->umem);
3769
3770 return ERR_PTR(err);
3771 }
3772
irdma_hwdereg_mr(struct ib_mr * ib_mr)3773 static int irdma_hwdereg_mr(struct ib_mr *ib_mr)
3774 {
3775 struct irdma_device *iwdev = to_iwdev(ib_mr->device);
3776 struct irdma_mr *iwmr = to_iwmr(ib_mr);
3777 struct irdma_pd *iwpd = to_iwpd(ib_mr->pd);
3778 struct irdma_dealloc_stag_info *info;
3779 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
3780 struct irdma_cqp_request *cqp_request;
3781 struct cqp_cmds_info *cqp_info;
3782 int status;
3783
3784 /* Skip HW MR de-register when it is already de-registered
3785 * during an MR re-reregister and the re-registration fails
3786 */
3787 if (!iwmr->is_hwreg)
3788 return 0;
3789
3790 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
3791 if (!cqp_request)
3792 return -ENOMEM;
3793
3794 cqp_info = &cqp_request->info;
3795 info = &cqp_info->in.u.dealloc_stag.info;
3796 info->pd_id = iwpd->sc_pd.pd_id;
3797 info->stag_idx = ib_mr->rkey >> IRDMA_CQPSQ_STAG_IDX_S;
3798 info->mr = true;
3799 if (iwpbl->pbl_allocated)
3800 info->dealloc_pbl = true;
3801
3802 cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG;
3803 cqp_info->post_sq = 1;
3804 cqp_info->in.u.dealloc_stag.dev = &iwdev->rf->sc_dev;
3805 cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request;
3806 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
3807 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
3808 if (status)
3809 return status;
3810
3811 iwmr->is_hwreg = false;
3812 return 0;
3813 }
3814
3815 /*
3816 * irdma_rereg_mr_trans - Re-register a user MR for a change translation.
3817 * @iwmr: ptr of iwmr
3818 * @start: virtual start address
3819 * @len: length of mr
3820 * @virt: virtual address
3821 *
3822 * Re-register a user memory region when a change translation is requested.
3823 * Re-register a new region while reusing the stag from the original registration.
3824 */
irdma_rereg_mr_trans(struct irdma_mr * iwmr,u64 start,u64 len,u64 virt)3825 static int irdma_rereg_mr_trans(struct irdma_mr *iwmr, u64 start, u64 len,
3826 u64 virt)
3827 {
3828 struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device);
3829 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
3830 struct ib_pd *pd = iwmr->ibmr.pd;
3831 struct ib_umem *region;
3832 int err;
3833
3834 region = ib_umem_get_va(pd->device, start, len, iwmr->access);
3835 if (IS_ERR(region))
3836 return PTR_ERR(region);
3837
3838 iwmr->region = region;
3839 iwmr->ibmr.iova = virt;
3840 iwmr->ibmr.pd = pd;
3841 iwmr->page_size = ib_umem_find_best_pgsz(region,
3842 iwdev->rf->sc_dev.hw_attrs.page_size_cap,
3843 virt);
3844 if (unlikely(!iwmr->page_size)) {
3845 err = -EOPNOTSUPP;
3846 goto err;
3847 }
3848
3849 iwmr->len = region->length;
3850 iwpbl->user_base = virt;
3851 iwmr->page_cnt = ib_umem_num_dma_blocks(region, iwmr->page_size);
3852
3853 err = irdma_reg_user_mr_type_mem(iwmr, iwmr->access, false);
3854 if (err)
3855 goto err;
3856
3857 return 0;
3858
3859 err:
3860 ib_umem_release(region);
3861 iwmr->region = NULL;
3862 return err;
3863 }
3864
3865 /*
3866 * irdma_rereg_user_mr - Re-Register a user memory region(MR)
3867 * @ibmr: ib mem to access iwarp mr pointer
3868 * @flags: bit mask to indicate which of the attr's of MR modified
3869 * @start: virtual start address
3870 * @len: length of mr
3871 * @virt: virtual address
3872 * @new_access: bit mask of access flags
3873 * @new_pd: ptr of pd
3874 * @udata: user data
3875 *
3876 * Return:
3877 * NULL - Success, existing MR updated
3878 * ERR_PTR - error occurred
3879 */
irdma_rereg_user_mr(struct ib_mr * ib_mr,int flags,u64 start,u64 len,u64 virt,int new_access,struct ib_pd * new_pd,struct ib_udata * udata)3880 static struct ib_mr *irdma_rereg_user_mr(struct ib_mr *ib_mr, int flags,
3881 u64 start, u64 len, u64 virt,
3882 int new_access, struct ib_pd *new_pd,
3883 struct ib_udata *udata)
3884 {
3885 struct irdma_device *iwdev = to_iwdev(ib_mr->device);
3886 struct irdma_mr *iwmr = to_iwmr(ib_mr);
3887 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
3888 int ret;
3889
3890 ret = ib_no_udata_io(udata);
3891 if (ret)
3892 return ERR_PTR(ret);
3893
3894 if (len > iwdev->rf->sc_dev.hw_attrs.max_mr_size)
3895 return ERR_PTR(-EINVAL);
3896
3897 if (flags & ~(IB_MR_REREG_TRANS | IB_MR_REREG_PD | IB_MR_REREG_ACCESS))
3898 return ERR_PTR(-EOPNOTSUPP);
3899
3900 if (iwmr->type != IRDMA_MEMREG_TYPE_MEM)
3901 return ERR_PTR(-EINVAL);
3902
3903 ret = ib_umem_check_rereg(iwmr->region, flags, new_access);
3904 if (ret)
3905 return ERR_PTR(ret);
3906
3907 ret = irdma_hwdereg_mr(ib_mr);
3908 if (ret)
3909 return ERR_PTR(ret);
3910
3911 if (flags & IB_MR_REREG_ACCESS)
3912 iwmr->access = new_access;
3913
3914 if (flags & IB_MR_REREG_PD) {
3915 iwmr->ibmr.pd = new_pd;
3916 iwmr->ibmr.device = new_pd->device;
3917 }
3918
3919 if (flags & IB_MR_REREG_TRANS) {
3920 if (iwpbl->pbl_allocated) {
3921 irdma_free_pble(iwdev->rf->pble_rsrc,
3922 &iwpbl->pble_alloc);
3923 iwpbl->pbl_allocated = false;
3924 }
3925
3926 if (iwmr->region) {
3927 ib_umem_release(iwmr->region);
3928 iwmr->region = NULL;
3929 }
3930
3931 ret = irdma_rereg_mr_trans(iwmr, start, len, virt);
3932 } else {
3933 ret = irdma_hwreg_mr(iwdev, iwmr, iwmr->access);
3934 }
3935
3936 return ret ? ERR_PTR(ret) : NULL;
3937 }
3938
3939 /**
3940 * irdma_reg_phys_mr - register kernel physical memory
3941 * @pd: ibpd pointer
3942 * @addr: physical address of memory to register
3943 * @size: size of memory to register
3944 * @access: Access rights
3945 * @iova_start: start of virtual address for physical buffers
3946 * @dma_mr: Flag indicating whether this region is a PD DMA MR
3947 */
irdma_reg_phys_mr(struct ib_pd * pd,u64 addr,u64 size,int access,u64 * iova_start,bool dma_mr)3948 struct ib_mr *irdma_reg_phys_mr(struct ib_pd *pd, u64 addr, u64 size, int access,
3949 u64 *iova_start, bool dma_mr)
3950 {
3951 struct irdma_device *iwdev = to_iwdev(pd->device);
3952 struct irdma_pbl *iwpbl;
3953 struct irdma_mr *iwmr;
3954 u32 stag;
3955 int ret;
3956
3957 iwmr = kzalloc_obj(*iwmr);
3958 if (!iwmr)
3959 return ERR_PTR(-ENOMEM);
3960
3961 iwmr->ibmr.pd = pd;
3962 iwmr->ibmr.device = pd->device;
3963 iwpbl = &iwmr->iwpbl;
3964 iwpbl->iwmr = iwmr;
3965 iwmr->type = IRDMA_MEMREG_TYPE_MEM;
3966 iwmr->dma_mr = dma_mr;
3967 iwpbl->user_base = *iova_start;
3968 stag = irdma_create_stag(iwdev);
3969 if (!stag) {
3970 ret = -ENOMEM;
3971 goto err;
3972 }
3973
3974 iwmr->stag = stag;
3975 iwmr->ibmr.iova = *iova_start;
3976 iwmr->ibmr.rkey = stag;
3977 iwmr->ibmr.lkey = stag;
3978 iwmr->page_cnt = 1;
3979 iwmr->pgaddrmem[0] = addr;
3980 iwmr->len = size;
3981 iwmr->page_size = SZ_4K;
3982 ret = irdma_hwreg_mr(iwdev, iwmr, access);
3983 if (ret) {
3984 irdma_free_stag(iwdev, stag);
3985 goto err;
3986 }
3987
3988 return &iwmr->ibmr;
3989
3990 err:
3991 kfree(iwmr);
3992
3993 return ERR_PTR(ret);
3994 }
3995
3996 /**
3997 * irdma_get_dma_mr - register physical mem
3998 * @pd: ptr of pd
3999 * @acc: access for memory
4000 */
irdma_get_dma_mr(struct ib_pd * pd,int acc)4001 static struct ib_mr *irdma_get_dma_mr(struct ib_pd *pd, int acc)
4002 {
4003 u64 kva = 0;
4004
4005 return irdma_reg_phys_mr(pd, 0, 0, acc, &kva, true);
4006 }
4007
4008 /**
4009 * irdma_del_memlist - Deleting pbl list entries for CQ/QP
4010 * @iwmr: iwmr for IB's user page addresses
4011 * @ucontext: ptr to user context
4012 *
4013 * Return: True if the MR is currently in-use by a QP/CQ/SRQ ring.
4014 */
irdma_del_memlist(struct irdma_mr * iwmr,struct irdma_ucontext * ucontext)4015 static bool irdma_del_memlist(struct irdma_mr *iwmr,
4016 struct irdma_ucontext *ucontext)
4017 {
4018 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
4019 unsigned long flags;
4020 spinlock_t *lock;
4021 bool in_use = false;
4022
4023 switch (iwmr->type) {
4024 case IRDMA_MEMREG_TYPE_CQ:
4025 lock = &ucontext->cq_reg_mem_list_lock;
4026 break;
4027 case IRDMA_MEMREG_TYPE_QP:
4028 lock = &ucontext->qp_reg_mem_list_lock;
4029 break;
4030 case IRDMA_MEMREG_TYPE_SRQ:
4031 lock = &ucontext->srq_reg_mem_list_lock;
4032 break;
4033 default:
4034 return false;
4035 }
4036
4037 spin_lock_irqsave(lock, flags);
4038 if (!refcount_dec_if_one(&iwmr->user_ring_refs)) {
4039 in_use = true;
4040 } else if (iwpbl->on_list) {
4041 iwpbl->on_list = false;
4042 list_del(&iwpbl->list);
4043 }
4044 spin_unlock_irqrestore(lock, flags);
4045
4046 return in_use;
4047 }
4048
4049 /**
4050 * irdma_dereg_mr - deregister mr
4051 * @ib_mr: mr ptr for dereg
4052 * @udata: user data
4053 */
irdma_dereg_mr(struct ib_mr * ib_mr,struct ib_udata * udata)4054 static int irdma_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
4055 {
4056 struct irdma_mr *iwmr = to_iwmr(ib_mr);
4057 struct irdma_device *iwdev = to_iwdev(ib_mr->device);
4058 struct irdma_pbl *iwpbl = &iwmr->iwpbl;
4059 bool dmabuf_revocable = iwmr->region && iwmr->region->is_dmabuf;
4060 int ret;
4061
4062 ret = ib_no_udata_io(udata);
4063 if (ret)
4064 return ret;
4065
4066 if (iwmr->type != IRDMA_MEMREG_TYPE_MEM) {
4067 if (iwmr->region) {
4068 struct irdma_ucontext *ucontext;
4069
4070 ucontext = rdma_udata_to_drv_context(udata,
4071 struct irdma_ucontext,
4072 ibucontext);
4073
4074 /* Do not allow the MR to be unpinned if it is still
4075 * backing a user ring.
4076 */
4077 if (irdma_del_memlist(iwmr, ucontext))
4078 return -EBUSY;
4079 }
4080 goto done;
4081 }
4082
4083 if (!dmabuf_revocable) {
4084 ret = irdma_hwdereg_mr(ib_mr);
4085 if (ret)
4086 return ret;
4087
4088 irdma_free_stag(iwdev, iwmr->stag);
4089 }
4090 done:
4091 if (iwmr->region)
4092 /* For dmabuf MRs, ib_umem_release will trigger a synchronous
4093 * call to the revoke callback which will perform the actual HW
4094 * invalidation via irdma_hwdereg_mr. We rely on this for its
4095 * implicit serialization w.r.t. concurrent revocations. This
4096 * must be done before freeing the PBLEs.
4097 */
4098 ib_umem_release(iwmr->region);
4099
4100 if (iwpbl->pbl_allocated)
4101 irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc);
4102
4103 if (dmabuf_revocable)
4104 irdma_free_stag(iwdev, iwmr->stag);
4105
4106 kfree(iwmr);
4107
4108 return 0;
4109 }
4110
4111 /**
4112 * irdma_post_send - kernel application wr
4113 * @ibqp: qp ptr for wr
4114 * @ib_wr: work request ptr
4115 * @bad_wr: return of bad wr if err
4116 */
irdma_post_send(struct ib_qp * ibqp,const struct ib_send_wr * ib_wr,const struct ib_send_wr ** bad_wr)4117 static int irdma_post_send(struct ib_qp *ibqp,
4118 const struct ib_send_wr *ib_wr,
4119 const struct ib_send_wr **bad_wr)
4120 {
4121 struct irdma_qp *iwqp;
4122 struct irdma_qp_uk *ukqp;
4123 struct irdma_sc_dev *dev;
4124 struct irdma_post_sq_info info;
4125 int err = 0;
4126 unsigned long flags;
4127 bool inv_stag;
4128 struct irdma_ah *ah;
4129
4130 iwqp = to_iwqp(ibqp);
4131 ukqp = &iwqp->sc_qp.qp_uk;
4132 dev = &iwqp->iwdev->rf->sc_dev;
4133
4134 spin_lock_irqsave(&iwqp->lock, flags);
4135 while (ib_wr) {
4136 memset(&info, 0, sizeof(info));
4137 inv_stag = false;
4138 info.wr_id = (ib_wr->wr_id);
4139 if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all)
4140 info.signaled = true;
4141 if (ib_wr->send_flags & IB_SEND_FENCE)
4142 info.read_fence = true;
4143 switch (ib_wr->opcode) {
4144 case IB_WR_ATOMIC_CMP_AND_SWP:
4145 if (unlikely(!(dev->hw_attrs.uk_attrs.feature_flags &
4146 IRDMA_FEATURE_ATOMIC_OPS))) {
4147 err = -EINVAL;
4148 break;
4149 }
4150 info.op_type = IRDMA_OP_TYPE_ATOMIC_COMPARE_AND_SWAP;
4151 info.op.atomic_compare_swap.tagged_offset = ib_wr->sg_list[0].addr;
4152 info.op.atomic_compare_swap.remote_tagged_offset =
4153 atomic_wr(ib_wr)->remote_addr;
4154 info.op.atomic_compare_swap.swap_data_bytes = atomic_wr(ib_wr)->swap;
4155 info.op.atomic_compare_swap.compare_data_bytes =
4156 atomic_wr(ib_wr)->compare_add;
4157 info.op.atomic_compare_swap.stag = ib_wr->sg_list[0].lkey;
4158 info.op.atomic_compare_swap.remote_stag = atomic_wr(ib_wr)->rkey;
4159 err = irdma_uk_atomic_compare_swap(ukqp, &info, false);
4160 break;
4161 case IB_WR_ATOMIC_FETCH_AND_ADD:
4162 if (unlikely(!(dev->hw_attrs.uk_attrs.feature_flags &
4163 IRDMA_FEATURE_ATOMIC_OPS))) {
4164 err = -EINVAL;
4165 break;
4166 }
4167 info.op_type = IRDMA_OP_TYPE_ATOMIC_FETCH_AND_ADD;
4168 info.op.atomic_fetch_add.tagged_offset = ib_wr->sg_list[0].addr;
4169 info.op.atomic_fetch_add.remote_tagged_offset =
4170 atomic_wr(ib_wr)->remote_addr;
4171 info.op.atomic_fetch_add.fetch_add_data_bytes =
4172 atomic_wr(ib_wr)->compare_add;
4173 info.op.atomic_fetch_add.stag = ib_wr->sg_list[0].lkey;
4174 info.op.atomic_fetch_add.remote_stag =
4175 atomic_wr(ib_wr)->rkey;
4176 err = irdma_uk_atomic_fetch_add(ukqp, &info, false);
4177 break;
4178 case IB_WR_SEND_WITH_IMM:
4179 if (ukqp->qp_caps & IRDMA_SEND_WITH_IMM) {
4180 info.imm_data_valid = true;
4181 info.imm_data = ntohl(ib_wr->ex.imm_data);
4182 } else {
4183 err = -EINVAL;
4184 break;
4185 }
4186 fallthrough;
4187 case IB_WR_SEND:
4188 case IB_WR_SEND_WITH_INV:
4189 if (ib_wr->opcode == IB_WR_SEND ||
4190 ib_wr->opcode == IB_WR_SEND_WITH_IMM) {
4191 if (ib_wr->send_flags & IB_SEND_SOLICITED)
4192 info.op_type = IRDMA_OP_TYPE_SEND_SOL;
4193 else
4194 info.op_type = IRDMA_OP_TYPE_SEND;
4195 } else {
4196 if (ib_wr->send_flags & IB_SEND_SOLICITED)
4197 info.op_type = IRDMA_OP_TYPE_SEND_SOL_INV;
4198 else
4199 info.op_type = IRDMA_OP_TYPE_SEND_INV;
4200 info.stag_to_inv = ib_wr->ex.invalidate_rkey;
4201 }
4202
4203 info.op.send.num_sges = ib_wr->num_sge;
4204 info.op.send.sg_list = ib_wr->sg_list;
4205 if (iwqp->ibqp.qp_type == IB_QPT_UD ||
4206 iwqp->ibqp.qp_type == IB_QPT_GSI) {
4207 ah = to_iwah(ud_wr(ib_wr)->ah);
4208 info.op.send.ah_id = ah->sc_ah.ah_info.ah_idx;
4209 info.op.send.qkey = ud_wr(ib_wr)->remote_qkey;
4210 info.op.send.dest_qp = ud_wr(ib_wr)->remote_qpn;
4211 }
4212
4213 if (ib_wr->send_flags & IB_SEND_INLINE)
4214 err = irdma_uk_inline_send(ukqp, &info, false);
4215 else
4216 err = irdma_uk_send(ukqp, &info, false);
4217 break;
4218 case IB_WR_RDMA_WRITE_WITH_IMM:
4219 if (ukqp->qp_caps & IRDMA_WRITE_WITH_IMM) {
4220 info.imm_data_valid = true;
4221 info.imm_data = ntohl(ib_wr->ex.imm_data);
4222 } else {
4223 err = -EINVAL;
4224 break;
4225 }
4226 fallthrough;
4227 case IB_WR_RDMA_WRITE:
4228 if (ib_wr->send_flags & IB_SEND_SOLICITED)
4229 info.op_type = IRDMA_OP_TYPE_RDMA_WRITE_SOL;
4230 else
4231 info.op_type = IRDMA_OP_TYPE_RDMA_WRITE;
4232
4233 info.op.rdma_write.num_lo_sges = ib_wr->num_sge;
4234 info.op.rdma_write.lo_sg_list = ib_wr->sg_list;
4235 info.op.rdma_write.rem_addr.addr =
4236 rdma_wr(ib_wr)->remote_addr;
4237 info.op.rdma_write.rem_addr.lkey = rdma_wr(ib_wr)->rkey;
4238 if (ib_wr->send_flags & IB_SEND_INLINE)
4239 err = irdma_uk_inline_rdma_write(ukqp, &info, false);
4240 else
4241 err = irdma_uk_rdma_write(ukqp, &info, false);
4242 break;
4243 case IB_WR_RDMA_READ_WITH_INV:
4244 inv_stag = true;
4245 fallthrough;
4246 case IB_WR_RDMA_READ:
4247 if (ib_wr->num_sge >
4248 dev->hw_attrs.uk_attrs.max_hw_read_sges) {
4249 err = -EINVAL;
4250 break;
4251 }
4252 info.op_type = IRDMA_OP_TYPE_RDMA_READ;
4253 info.op.rdma_read.rem_addr.addr = rdma_wr(ib_wr)->remote_addr;
4254 info.op.rdma_read.rem_addr.lkey = rdma_wr(ib_wr)->rkey;
4255 info.op.rdma_read.lo_sg_list = (void *)ib_wr->sg_list;
4256 info.op.rdma_read.num_lo_sges = ib_wr->num_sge;
4257 err = irdma_uk_rdma_read(ukqp, &info, inv_stag, false);
4258 break;
4259 case IB_WR_LOCAL_INV:
4260 info.op_type = IRDMA_OP_TYPE_INV_STAG;
4261 info.local_fence = true;
4262 info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey;
4263 err = irdma_uk_stag_local_invalidate(ukqp, &info, true);
4264 break;
4265 case IB_WR_REG_MR: {
4266 struct irdma_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
4267 struct irdma_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc;
4268 struct irdma_fast_reg_stag_info stag_info = {};
4269
4270 stag_info.signaled = info.signaled;
4271 stag_info.read_fence = info.read_fence;
4272 stag_info.access_rights =
4273 irdma_get_mr_access(reg_wr(ib_wr)->access,
4274 dev->hw_attrs.uk_attrs.hw_rev);
4275 stag_info.stag_key = reg_wr(ib_wr)->key & 0xff;
4276 stag_info.stag_idx = reg_wr(ib_wr)->key >> 8;
4277 stag_info.page_size = reg_wr(ib_wr)->mr->page_size;
4278 stag_info.wr_id = ib_wr->wr_id;
4279 stag_info.addr_type = IRDMA_ADDR_TYPE_VA_BASED;
4280 stag_info.va = (void *)(uintptr_t)iwmr->ibmr.iova;
4281 stag_info.total_len = iwmr->ibmr.length;
4282 stag_info.reg_addr_pa = *palloc->level1.addr;
4283 stag_info.first_pm_pbl_index = palloc->level1.idx;
4284 stag_info.local_fence = true;
4285 if (iwmr->npages > IRDMA_MIN_PAGES_PER_FMR)
4286 stag_info.chunk_size = 1;
4287 err = irdma_sc_mr_fast_register(&iwqp->sc_qp, &stag_info,
4288 true);
4289 break;
4290 }
4291 default:
4292 err = -EINVAL;
4293 ibdev_dbg(&iwqp->iwdev->ibdev,
4294 "VERBS: upost_send bad opcode = 0x%x\n",
4295 ib_wr->opcode);
4296 break;
4297 }
4298
4299 if (err)
4300 break;
4301 ib_wr = ib_wr->next;
4302 }
4303
4304 if (!iwqp->flush_issued) {
4305 if (iwqp->hw_iwarp_state <= IRDMA_QP_STATE_RTS)
4306 irdma_uk_qp_post_wr(ukqp);
4307 spin_unlock_irqrestore(&iwqp->lock, flags);
4308 } else {
4309 spin_unlock_irqrestore(&iwqp->lock, flags);
4310 mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush,
4311 msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
4312 }
4313
4314 if (err)
4315 *bad_wr = ib_wr;
4316
4317 return err;
4318 }
4319
4320 /**
4321 * irdma_post_srq_recv - post receive wr for kernel application
4322 * @ibsrq: ib srq pointer
4323 * @ib_wr: work request for receive
4324 * @bad_wr: bad wr caused an error
4325 */
irdma_post_srq_recv(struct ib_srq * ibsrq,const struct ib_recv_wr * ib_wr,const struct ib_recv_wr ** bad_wr)4326 static int irdma_post_srq_recv(struct ib_srq *ibsrq,
4327 const struct ib_recv_wr *ib_wr,
4328 const struct ib_recv_wr **bad_wr)
4329 {
4330 struct irdma_srq *iwsrq = to_iwsrq(ibsrq);
4331 struct irdma_srq_uk *uksrq = &iwsrq->sc_srq.srq_uk;
4332 struct irdma_post_rq_info post_recv = {};
4333 unsigned long flags;
4334 int err = 0;
4335
4336 spin_lock_irqsave(&iwsrq->lock, flags);
4337 while (ib_wr) {
4338 if (ib_wr->num_sge > uksrq->max_srq_frag_cnt) {
4339 err = -EINVAL;
4340 goto out;
4341 }
4342 post_recv.num_sges = ib_wr->num_sge;
4343 post_recv.wr_id = ib_wr->wr_id;
4344 post_recv.sg_list = ib_wr->sg_list;
4345 err = irdma_uk_srq_post_receive(uksrq, &post_recv);
4346 if (err)
4347 goto out;
4348
4349 ib_wr = ib_wr->next;
4350 }
4351
4352 out:
4353 spin_unlock_irqrestore(&iwsrq->lock, flags);
4354
4355 if (err)
4356 *bad_wr = ib_wr;
4357
4358 return err;
4359 }
4360
4361 /**
4362 * irdma_post_recv - post receive wr for kernel application
4363 * @ibqp: ib qp pointer
4364 * @ib_wr: work request for receive
4365 * @bad_wr: bad wr caused an error
4366 */
irdma_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * ib_wr,const struct ib_recv_wr ** bad_wr)4367 static int irdma_post_recv(struct ib_qp *ibqp,
4368 const struct ib_recv_wr *ib_wr,
4369 const struct ib_recv_wr **bad_wr)
4370 {
4371 struct irdma_qp *iwqp;
4372 struct irdma_qp_uk *ukqp;
4373 struct irdma_post_rq_info post_recv = {};
4374 unsigned long flags;
4375 int err = 0;
4376
4377 iwqp = to_iwqp(ibqp);
4378 ukqp = &iwqp->sc_qp.qp_uk;
4379
4380 if (ukqp->srq_uk) {
4381 *bad_wr = ib_wr;
4382 return -EINVAL;
4383 }
4384
4385 spin_lock_irqsave(&iwqp->lock, flags);
4386 while (ib_wr) {
4387 post_recv.num_sges = ib_wr->num_sge;
4388 post_recv.wr_id = ib_wr->wr_id;
4389 post_recv.sg_list = ib_wr->sg_list;
4390 err = irdma_uk_post_receive(ukqp, &post_recv);
4391 if (err) {
4392 ibdev_dbg(&iwqp->iwdev->ibdev,
4393 "VERBS: post_recv err %d\n", err);
4394 goto out;
4395 }
4396
4397 ib_wr = ib_wr->next;
4398 }
4399
4400 out:
4401 spin_unlock_irqrestore(&iwqp->lock, flags);
4402 if (iwqp->flush_issued)
4403 mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush,
4404 msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
4405
4406 if (err)
4407 *bad_wr = ib_wr;
4408
4409 return err;
4410 }
4411
4412 /**
4413 * irdma_flush_err_to_ib_wc_status - return change flush error code to IB status
4414 * @opcode: iwarp flush code
4415 */
irdma_flush_err_to_ib_wc_status(enum irdma_flush_opcode opcode)4416 static enum ib_wc_status irdma_flush_err_to_ib_wc_status(enum irdma_flush_opcode opcode)
4417 {
4418 switch (opcode) {
4419 case FLUSH_PROT_ERR:
4420 return IB_WC_LOC_PROT_ERR;
4421 case FLUSH_REM_ACCESS_ERR:
4422 return IB_WC_REM_ACCESS_ERR;
4423 case FLUSH_LOC_QP_OP_ERR:
4424 return IB_WC_LOC_QP_OP_ERR;
4425 case FLUSH_REM_OP_ERR:
4426 return IB_WC_REM_OP_ERR;
4427 case FLUSH_LOC_LEN_ERR:
4428 return IB_WC_LOC_LEN_ERR;
4429 case FLUSH_GENERAL_ERR:
4430 return IB_WC_WR_FLUSH_ERR;
4431 case FLUSH_RETRY_EXC_ERR:
4432 return IB_WC_RETRY_EXC_ERR;
4433 case FLUSH_MW_BIND_ERR:
4434 return IB_WC_MW_BIND_ERR;
4435 case FLUSH_REM_INV_REQ_ERR:
4436 return IB_WC_REM_INV_REQ_ERR;
4437 case FLUSH_RNR_RETRY_EXC_ERR:
4438 return IB_WC_RNR_RETRY_EXC_ERR;
4439 case FLUSH_FATAL_ERR:
4440 default:
4441 return IB_WC_FATAL_ERR;
4442 }
4443 }
4444
4445 /**
4446 * irdma_process_cqe - process cqe info
4447 * @entry: processed cqe
4448 * @cq_poll_info: cqe info
4449 */
irdma_process_cqe(struct ib_wc * entry,struct irdma_cq_poll_info * cq_poll_info)4450 static void irdma_process_cqe(struct ib_wc *entry,
4451 struct irdma_cq_poll_info *cq_poll_info)
4452 {
4453 struct irdma_sc_qp *qp;
4454
4455 entry->wc_flags = 0;
4456 entry->pkey_index = 0;
4457 entry->wr_id = cq_poll_info->wr_id;
4458
4459 qp = cq_poll_info->qp_handle;
4460 entry->qp = qp->qp_uk.back_qp;
4461
4462 if (cq_poll_info->error) {
4463 entry->status = (cq_poll_info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) ?
4464 irdma_flush_err_to_ib_wc_status(cq_poll_info->minor_err) : IB_WC_GENERAL_ERR;
4465
4466 entry->vendor_err = cq_poll_info->major_err << 16 |
4467 cq_poll_info->minor_err;
4468 } else {
4469 entry->status = IB_WC_SUCCESS;
4470 if (cq_poll_info->imm_valid) {
4471 entry->ex.imm_data = htonl(cq_poll_info->imm_data);
4472 entry->wc_flags |= IB_WC_WITH_IMM;
4473 }
4474 if (cq_poll_info->ud_smac_valid) {
4475 ether_addr_copy(entry->smac, cq_poll_info->ud_smac);
4476 entry->wc_flags |= IB_WC_WITH_SMAC;
4477 }
4478
4479 if (cq_poll_info->ud_vlan_valid) {
4480 u16 vlan = cq_poll_info->ud_vlan & VLAN_VID_MASK;
4481
4482 entry->sl = cq_poll_info->ud_vlan >> VLAN_PRIO_SHIFT;
4483 if (vlan) {
4484 entry->vlan_id = vlan;
4485 entry->wc_flags |= IB_WC_WITH_VLAN;
4486 }
4487 } else {
4488 entry->sl = 0;
4489 }
4490 }
4491
4492 if (cq_poll_info->q_type == IRDMA_CQE_QTYPE_SQ) {
4493 set_ib_wc_op_sq(cq_poll_info, entry);
4494 } else {
4495 if (qp->dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2)
4496 set_ib_wc_op_rq(cq_poll_info, entry,
4497 qp->qp_uk.qp_caps & IRDMA_SEND_WITH_IMM ?
4498 true : false);
4499 else
4500 set_ib_wc_op_rq_gen_3(cq_poll_info, entry);
4501 if (qp->qp_uk.qp_type != IRDMA_QP_TYPE_ROCE_UD &&
4502 cq_poll_info->stag_invalid_set) {
4503 entry->ex.invalidate_rkey = cq_poll_info->inv_stag;
4504 entry->wc_flags |= IB_WC_WITH_INVALIDATE;
4505 }
4506 }
4507
4508 if (qp->qp_uk.qp_type == IRDMA_QP_TYPE_ROCE_UD) {
4509 entry->src_qp = cq_poll_info->ud_src_qpn;
4510 entry->slid = 0;
4511 entry->wc_flags |=
4512 (IB_WC_GRH | IB_WC_WITH_NETWORK_HDR_TYPE);
4513 entry->network_hdr_type = cq_poll_info->ipv4 ?
4514 RDMA_NETWORK_IPV4 :
4515 RDMA_NETWORK_IPV6;
4516 } else {
4517 entry->src_qp = cq_poll_info->qp_id;
4518 }
4519
4520 entry->byte_len = cq_poll_info->bytes_xfered;
4521 }
4522
4523 /**
4524 * irdma_poll_one - poll one entry of the CQ
4525 * @ukcq: ukcq to poll
4526 * @cur_cqe: current CQE info to be filled in
4527 * @entry: ibv_wc object to be filled for non-extended CQ or NULL for extended CQ
4528 *
4529 * Returns the internal irdma device error code or 0 on success
4530 */
irdma_poll_one(struct irdma_cq_uk * ukcq,struct irdma_cq_poll_info * cur_cqe,struct ib_wc * entry)4531 static inline int irdma_poll_one(struct irdma_cq_uk *ukcq,
4532 struct irdma_cq_poll_info *cur_cqe,
4533 struct ib_wc *entry)
4534 {
4535 int ret = irdma_uk_cq_poll_cmpl(ukcq, cur_cqe);
4536
4537 if (ret)
4538 return ret;
4539
4540 irdma_process_cqe(entry, cur_cqe);
4541
4542 return 0;
4543 }
4544
4545 /**
4546 * __irdma_poll_cq - poll cq for completion (kernel apps)
4547 * @iwcq: cq to poll
4548 * @num_entries: number of entries to poll
4549 * @entry: wr of a completed entry
4550 */
__irdma_poll_cq(struct irdma_cq * iwcq,int num_entries,struct ib_wc * entry)4551 static int __irdma_poll_cq(struct irdma_cq *iwcq, int num_entries, struct ib_wc *entry)
4552 {
4553 struct list_head *tmp_node, *list_node;
4554 struct irdma_cq_buf *last_buf = NULL;
4555 struct irdma_cq_poll_info *cur_cqe = &iwcq->cur_cqe;
4556 struct irdma_cq_buf *cq_buf;
4557 int ret;
4558 struct irdma_device *iwdev;
4559 struct irdma_cq_uk *ukcq;
4560 bool cq_new_cqe = false;
4561 int resized_bufs = 0;
4562 int npolled = 0;
4563
4564 iwdev = to_iwdev(iwcq->ibcq.device);
4565 ukcq = &iwcq->sc_cq.cq_uk;
4566
4567 /* go through the list of previously resized CQ buffers */
4568 list_for_each_safe(list_node, tmp_node, &iwcq->resize_list) {
4569 cq_buf = container_of(list_node, struct irdma_cq_buf, list);
4570 while (npolled < num_entries) {
4571 ret = irdma_poll_one(&cq_buf->cq_uk, cur_cqe, entry + npolled);
4572 if (!ret) {
4573 ++npolled;
4574 cq_new_cqe = true;
4575 continue;
4576 }
4577 if (ret == -ENOENT)
4578 break;
4579 /* QP using the CQ is destroyed. Skip reporting this CQE */
4580 if (ret == -EFAULT) {
4581 cq_new_cqe = true;
4582 continue;
4583 }
4584 goto error;
4585 }
4586
4587 /* save the resized CQ buffer which received the last cqe */
4588 if (cq_new_cqe)
4589 last_buf = cq_buf;
4590 cq_new_cqe = false;
4591 }
4592
4593 /* check the current CQ for new cqes */
4594 while (npolled < num_entries) {
4595 ret = irdma_poll_one(ukcq, cur_cqe, entry + npolled);
4596 if (ret == -ENOENT) {
4597 ret = irdma_generated_cmpls(iwcq, cur_cqe);
4598 if (!ret)
4599 irdma_process_cqe(entry + npolled, cur_cqe);
4600 }
4601 if (!ret) {
4602 ++npolled;
4603 cq_new_cqe = true;
4604 continue;
4605 }
4606
4607 if (ret == -ENOENT)
4608 break;
4609 /* QP using the CQ is destroyed. Skip reporting this CQE */
4610 if (ret == -EFAULT) {
4611 cq_new_cqe = true;
4612 continue;
4613 }
4614 goto error;
4615 }
4616
4617 if (cq_new_cqe)
4618 /* all previous CQ resizes are complete */
4619 resized_bufs = irdma_process_resize_list(iwcq, iwdev, NULL);
4620 else if (last_buf)
4621 /* only CQ resizes up to the last_buf are complete */
4622 resized_bufs = irdma_process_resize_list(iwcq, iwdev, last_buf);
4623 if (resized_bufs)
4624 /* report to the HW the number of complete CQ resizes */
4625 irdma_uk_cq_set_resized_cnt(ukcq, resized_bufs);
4626
4627 return npolled;
4628 error:
4629 ibdev_dbg(&iwdev->ibdev, "%s: Error polling CQ, irdma_err: %d\n",
4630 __func__, ret);
4631
4632 return ret;
4633 }
4634
4635 /**
4636 * irdma_poll_cq - poll cq for completion (kernel apps)
4637 * @ibcq: cq to poll
4638 * @num_entries: number of entries to poll
4639 * @entry: wr of a completed entry
4640 */
irdma_poll_cq(struct ib_cq * ibcq,int num_entries,struct ib_wc * entry)4641 static int irdma_poll_cq(struct ib_cq *ibcq, int num_entries,
4642 struct ib_wc *entry)
4643 {
4644 struct irdma_cq *iwcq;
4645 unsigned long flags;
4646 int ret;
4647
4648 iwcq = to_iwcq(ibcq);
4649
4650 spin_lock_irqsave(&iwcq->lock, flags);
4651 ret = __irdma_poll_cq(iwcq, num_entries, entry);
4652 spin_unlock_irqrestore(&iwcq->lock, flags);
4653
4654 return ret;
4655 }
4656
4657 /**
4658 * irdma_req_notify_cq - arm cq kernel application
4659 * @ibcq: cq to arm
4660 * @notify_flags: notofication flags
4661 */
irdma_req_notify_cq(struct ib_cq * ibcq,enum ib_cq_notify_flags notify_flags)4662 static int irdma_req_notify_cq(struct ib_cq *ibcq,
4663 enum ib_cq_notify_flags notify_flags)
4664 {
4665 struct irdma_cq *iwcq;
4666 struct irdma_cq_uk *ukcq;
4667 unsigned long flags;
4668 enum irdma_cmpl_notify cq_notify;
4669 bool promo_event = false;
4670 int ret = 0;
4671
4672 cq_notify = notify_flags == IB_CQ_SOLICITED ?
4673 IRDMA_CQ_COMPL_SOLICITED : IRDMA_CQ_COMPL_EVENT;
4674 iwcq = to_iwcq(ibcq);
4675 ukcq = &iwcq->sc_cq.cq_uk;
4676
4677 spin_lock_irqsave(&iwcq->lock, flags);
4678 /* Only promote to arm the CQ for any event if the last arm event was solicited. */
4679 if (iwcq->last_notify == IRDMA_CQ_COMPL_SOLICITED && notify_flags != IB_CQ_SOLICITED)
4680 promo_event = true;
4681
4682 if (!atomic_cmpxchg(&iwcq->armed, 0, 1) || promo_event) {
4683 iwcq->last_notify = cq_notify;
4684 irdma_uk_cq_request_notification(ukcq, cq_notify);
4685 }
4686
4687 if ((notify_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
4688 (!irdma_uk_cq_empty(ukcq) || !list_empty(&iwcq->cmpl_generated)))
4689 ret = 1;
4690 spin_unlock_irqrestore(&iwcq->lock, flags);
4691
4692 return ret;
4693 }
4694
4695 static const struct rdma_stat_desc irdma_hw_stat_descs[] = {
4696 /* gen1 - 32-bit */
4697 [IRDMA_HW_STAT_INDEX_IP4RXDISCARD].name = "ip4InDiscards",
4698 [IRDMA_HW_STAT_INDEX_IP4RXTRUNC].name = "ip4InTruncatedPkts",
4699 [IRDMA_HW_STAT_INDEX_IP4TXNOROUTE].name = "ip4OutNoRoutes",
4700 [IRDMA_HW_STAT_INDEX_IP6RXDISCARD].name = "ip6InDiscards",
4701 [IRDMA_HW_STAT_INDEX_IP6RXTRUNC].name = "ip6InTruncatedPkts",
4702 [IRDMA_HW_STAT_INDEX_IP6TXNOROUTE].name = "ip6OutNoRoutes",
4703 [IRDMA_HW_STAT_INDEX_RXVLANERR].name = "rxVlanErrors",
4704 /* gen1 - 64-bit */
4705 [IRDMA_HW_STAT_INDEX_IP4RXOCTS].name = "ip4InOctets",
4706 [IRDMA_HW_STAT_INDEX_IP4RXPKTS].name = "ip4InPkts",
4707 [IRDMA_HW_STAT_INDEX_IP4RXFRAGS].name = "ip4InReasmRqd",
4708 [IRDMA_HW_STAT_INDEX_IP4RXMCPKTS].name = "ip4InMcastPkts",
4709 [IRDMA_HW_STAT_INDEX_IP4TXOCTS].name = "ip4OutOctets",
4710 [IRDMA_HW_STAT_INDEX_IP4TXPKTS].name = "ip4OutPkts",
4711 [IRDMA_HW_STAT_INDEX_IP4TXFRAGS].name = "ip4OutSegRqd",
4712 [IRDMA_HW_STAT_INDEX_IP4TXMCPKTS].name = "ip4OutMcastPkts",
4713 [IRDMA_HW_STAT_INDEX_IP6RXOCTS].name = "ip6InOctets",
4714 [IRDMA_HW_STAT_INDEX_IP6RXPKTS].name = "ip6InPkts",
4715 [IRDMA_HW_STAT_INDEX_IP6RXFRAGS].name = "ip6InReasmRqd",
4716 [IRDMA_HW_STAT_INDEX_IP6RXMCPKTS].name = "ip6InMcastPkts",
4717 [IRDMA_HW_STAT_INDEX_IP6TXOCTS].name = "ip6OutOctets",
4718 [IRDMA_HW_STAT_INDEX_IP6TXPKTS].name = "ip6OutPkts",
4719 [IRDMA_HW_STAT_INDEX_IP6TXFRAGS].name = "ip6OutSegRqd",
4720 [IRDMA_HW_STAT_INDEX_IP6TXMCPKTS].name = "ip6OutMcastPkts",
4721 [IRDMA_HW_STAT_INDEX_RDMARXRDS].name = "InRdmaReads",
4722 [IRDMA_HW_STAT_INDEX_RDMARXSNDS].name = "InRdmaSends",
4723 [IRDMA_HW_STAT_INDEX_RDMARXWRS].name = "InRdmaWrites",
4724 [IRDMA_HW_STAT_INDEX_RDMATXRDS].name = "OutRdmaReads",
4725 [IRDMA_HW_STAT_INDEX_RDMATXSNDS].name = "OutRdmaSends",
4726 [IRDMA_HW_STAT_INDEX_RDMATXWRS].name = "OutRdmaWrites",
4727 [IRDMA_HW_STAT_INDEX_RDMAVBND].name = "RdmaBnd",
4728 [IRDMA_HW_STAT_INDEX_RDMAVINV].name = "RdmaInv",
4729
4730 /* gen2 - 32-bit */
4731 [IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED].name = "cnpHandled",
4732 [IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED].name = "cnpIgnored",
4733 [IRDMA_HW_STAT_INDEX_TXNPCNPSENT].name = "cnpSent",
4734 /* gen2 - 64-bit */
4735 [IRDMA_HW_STAT_INDEX_IP4RXMCOCTS].name = "ip4InMcastOctets",
4736 [IRDMA_HW_STAT_INDEX_IP4TXMCOCTS].name = "ip4OutMcastOctets",
4737 [IRDMA_HW_STAT_INDEX_IP6RXMCOCTS].name = "ip6InMcastOctets",
4738 [IRDMA_HW_STAT_INDEX_IP6TXMCOCTS].name = "ip6OutMcastOctets",
4739 [IRDMA_HW_STAT_INDEX_UDPRXPKTS].name = "RxUDP",
4740 [IRDMA_HW_STAT_INDEX_UDPTXPKTS].name = "TxUDP",
4741 [IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS].name = "RxECNMrkd",
4742 [IRDMA_HW_STAT_INDEX_TCPRTXSEG].name = "RetransSegs",
4743 [IRDMA_HW_STAT_INDEX_TCPRXOPTERR].name = "InOptErrors",
4744 [IRDMA_HW_STAT_INDEX_TCPRXPROTOERR].name = "InProtoErrors",
4745 [IRDMA_HW_STAT_INDEX_TCPRXSEGS].name = "InSegs",
4746 [IRDMA_HW_STAT_INDEX_TCPTXSEG].name = "OutSegs",
4747
4748 /* gen3 */
4749 [IRDMA_HW_STAT_INDEX_RNR_SENT].name = "RNR sent",
4750 [IRDMA_HW_STAT_INDEX_RNR_RCVD].name = "RNR received",
4751 [IRDMA_HW_STAT_INDEX_RDMAORDLMTCNT].name = "ord limit count",
4752 [IRDMA_HW_STAT_INDEX_RDMAIRDLMTCNT].name = "ird limit count",
4753 [IRDMA_HW_STAT_INDEX_RDMARXATS].name = "Rx atomics",
4754 [IRDMA_HW_STAT_INDEX_RDMATXATS].name = "Tx atomics",
4755 [IRDMA_HW_STAT_INDEX_NAKSEQERR].name = "Nak Sequence Error",
4756 [IRDMA_HW_STAT_INDEX_NAKSEQERR_IMPLIED].name = "Nak Sequence Error Implied",
4757 [IRDMA_HW_STAT_INDEX_RTO].name = "RTO",
4758 [IRDMA_HW_STAT_INDEX_RXOOOPKTS].name = "Rcvd Out of order packets",
4759 [IRDMA_HW_STAT_INDEX_ICRCERR].name = "CRC errors",
4760 };
4761
irdma_roce_port_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)4762 static int irdma_roce_port_immutable(struct ib_device *ibdev, u32 port_num,
4763 struct ib_port_immutable *immutable)
4764 {
4765 struct ib_port_attr attr;
4766 int err;
4767
4768 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4769 err = ib_query_port(ibdev, port_num, &attr);
4770 if (err)
4771 return err;
4772
4773 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4774 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4775 immutable->gid_tbl_len = attr.gid_tbl_len;
4776
4777 return 0;
4778 }
4779
irdma_iw_port_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)4780 static int irdma_iw_port_immutable(struct ib_device *ibdev, u32 port_num,
4781 struct ib_port_immutable *immutable)
4782 {
4783 struct ib_port_attr attr;
4784 int err;
4785
4786 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
4787 err = ib_query_port(ibdev, port_num, &attr);
4788 if (err)
4789 return err;
4790 immutable->gid_tbl_len = attr.gid_tbl_len;
4791
4792 return 0;
4793 }
4794
irdma_get_dev_fw_str(struct ib_device * dev,char * str)4795 static void irdma_get_dev_fw_str(struct ib_device *dev, char *str)
4796 {
4797 struct irdma_device *iwdev = to_iwdev(dev);
4798
4799 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u",
4800 irdma_fw_major_ver(&iwdev->rf->sc_dev),
4801 irdma_fw_minor_ver(&iwdev->rf->sc_dev));
4802 }
4803
4804 /**
4805 * irdma_alloc_hw_port_stats - Allocate a hw stats structure
4806 * @ibdev: device pointer from stack
4807 * @port_num: port number
4808 */
irdma_alloc_hw_port_stats(struct ib_device * ibdev,u32 port_num)4809 static struct rdma_hw_stats *irdma_alloc_hw_port_stats(struct ib_device *ibdev,
4810 u32 port_num)
4811 {
4812 struct irdma_device *iwdev = to_iwdev(ibdev);
4813 struct irdma_sc_dev *dev = &iwdev->rf->sc_dev;
4814
4815 int num_counters = dev->hw_attrs.max_stat_idx;
4816 unsigned long lifespan = RDMA_HW_STATS_DEFAULT_LIFESPAN;
4817
4818 return rdma_alloc_hw_stats_struct(irdma_hw_stat_descs, num_counters,
4819 lifespan);
4820 }
4821
4822 /**
4823 * irdma_get_hw_stats - Populates the rdma_hw_stats structure
4824 * @ibdev: device pointer from stack
4825 * @stats: stats pointer from stack
4826 * @port_num: port number
4827 * @index: which hw counter the stack is requesting we update
4828 */
irdma_get_hw_stats(struct ib_device * ibdev,struct rdma_hw_stats * stats,u32 port_num,int index)4829 static int irdma_get_hw_stats(struct ib_device *ibdev,
4830 struct rdma_hw_stats *stats, u32 port_num,
4831 int index)
4832 {
4833 struct irdma_device *iwdev = to_iwdev(ibdev);
4834 struct irdma_dev_hw_stats *hw_stats = &iwdev->vsi.pestat->hw_stats;
4835
4836 if (iwdev->rf->rdma_ver >= IRDMA_GEN_2)
4837 irdma_cqp_gather_stats_cmd(&iwdev->rf->sc_dev, iwdev->vsi.pestat, true);
4838 else
4839 irdma_cqp_gather_stats_gen1(&iwdev->rf->sc_dev, iwdev->vsi.pestat);
4840
4841 memcpy(&stats->value[0], hw_stats, sizeof(u64) * stats->num_counters);
4842
4843 return stats->num_counters;
4844 }
4845
4846 /**
4847 * irdma_query_gid - Query port GID
4848 * @ibdev: device pointer from stack
4849 * @port: port number
4850 * @index: Entry index
4851 * @gid: Global ID
4852 */
irdma_query_gid(struct ib_device * ibdev,u32 port,int index,union ib_gid * gid)4853 static int irdma_query_gid(struct ib_device *ibdev, u32 port, int index,
4854 union ib_gid *gid)
4855 {
4856 struct irdma_device *iwdev = to_iwdev(ibdev);
4857
4858 memset(gid->raw, 0, sizeof(gid->raw));
4859 ether_addr_copy(gid->raw, iwdev->netdev->dev_addr);
4860
4861 return 0;
4862 }
4863
4864 /**
4865 * mcast_list_add - Add a new mcast item to list
4866 * @rf: RDMA PCI function
4867 * @new_elem: pointer to element to add
4868 */
mcast_list_add(struct irdma_pci_f * rf,struct mc_table_list * new_elem)4869 static void mcast_list_add(struct irdma_pci_f *rf,
4870 struct mc_table_list *new_elem)
4871 {
4872 list_add(&new_elem->list, &rf->mc_qht_list.list);
4873 }
4874
4875 /**
4876 * mcast_list_del - Remove an mcast item from list
4877 * @mc_qht_elem: pointer to mcast table list element
4878 */
mcast_list_del(struct mc_table_list * mc_qht_elem)4879 static void mcast_list_del(struct mc_table_list *mc_qht_elem)
4880 {
4881 if (mc_qht_elem)
4882 list_del(&mc_qht_elem->list);
4883 }
4884
4885 /**
4886 * mcast_list_lookup_ip - Search mcast list for address
4887 * @rf: RDMA PCI function
4888 * @ip_mcast: pointer to mcast IP address
4889 */
mcast_list_lookup_ip(struct irdma_pci_f * rf,u32 * ip_mcast)4890 static struct mc_table_list *mcast_list_lookup_ip(struct irdma_pci_f *rf,
4891 u32 *ip_mcast)
4892 {
4893 struct mc_table_list *mc_qht_el;
4894 struct list_head *pos, *q;
4895
4896 list_for_each_safe (pos, q, &rf->mc_qht_list.list) {
4897 mc_qht_el = list_entry(pos, struct mc_table_list, list);
4898 if (!memcmp(mc_qht_el->mc_info.dest_ip, ip_mcast,
4899 sizeof(mc_qht_el->mc_info.dest_ip)))
4900 return mc_qht_el;
4901 }
4902
4903 return NULL;
4904 }
4905
4906 /**
4907 * irdma_mcast_cqp_op - perform a mcast cqp operation
4908 * @iwdev: irdma device
4909 * @mc_grp_ctx: mcast group info
4910 * @op: operation
4911 *
4912 * returns error status
4913 */
irdma_mcast_cqp_op(struct irdma_device * iwdev,struct irdma_mcast_grp_info * mc_grp_ctx,u8 op)4914 static int irdma_mcast_cqp_op(struct irdma_device *iwdev,
4915 struct irdma_mcast_grp_info *mc_grp_ctx, u8 op)
4916 {
4917 struct cqp_cmds_info *cqp_info;
4918 struct irdma_cqp_request *cqp_request;
4919 int status;
4920
4921 cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true);
4922 if (!cqp_request)
4923 return -ENOMEM;
4924
4925 cqp_request->info.in.u.mc_create.info = *mc_grp_ctx;
4926 cqp_info = &cqp_request->info;
4927 cqp_info->cqp_cmd = op;
4928 cqp_info->post_sq = 1;
4929 cqp_info->in.u.mc_create.scratch = (uintptr_t)cqp_request;
4930 cqp_info->in.u.mc_create.cqp = &iwdev->rf->cqp.sc_cqp;
4931 status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
4932 irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
4933
4934 return status;
4935 }
4936
4937 /**
4938 * irdma_mcast_mac - Get the multicast MAC for an IP address
4939 * @ip_addr: IPv4 or IPv6 address
4940 * @mac: pointer to result MAC address
4941 * @ipv4: flag indicating IPv4 or IPv6
4942 *
4943 */
irdma_mcast_mac(u32 * ip_addr,u8 * mac,bool ipv4)4944 void irdma_mcast_mac(u32 *ip_addr, u8 *mac, bool ipv4)
4945 {
4946 u8 *ip = (u8 *)ip_addr;
4947
4948 if (ipv4) {
4949 unsigned char mac4[ETH_ALEN] = {0x01, 0x00, 0x5E, 0x00,
4950 0x00, 0x00};
4951
4952 mac4[3] = ip[2] & 0x7F;
4953 mac4[4] = ip[1];
4954 mac4[5] = ip[0];
4955 ether_addr_copy(mac, mac4);
4956 } else {
4957 unsigned char mac6[ETH_ALEN] = {0x33, 0x33, 0x00, 0x00,
4958 0x00, 0x00};
4959
4960 mac6[2] = ip[3];
4961 mac6[3] = ip[2];
4962 mac6[4] = ip[1];
4963 mac6[5] = ip[0];
4964 ether_addr_copy(mac, mac6);
4965 }
4966 }
4967
4968 /**
4969 * irdma_attach_mcast - attach a qp to a multicast group
4970 * @ibqp: ptr to qp
4971 * @ibgid: pointer to global ID
4972 * @lid: local ID
4973 *
4974 * returns error status
4975 */
irdma_attach_mcast(struct ib_qp * ibqp,union ib_gid * ibgid,u16 lid)4976 static int irdma_attach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid)
4977 {
4978 struct irdma_qp *iwqp = to_iwqp(ibqp);
4979 struct irdma_device *iwdev = iwqp->iwdev;
4980 struct irdma_pci_f *rf = iwdev->rf;
4981 struct mc_table_list *mc_qht_elem;
4982 struct irdma_mcast_grp_ctx_entry_info mcg_info = {};
4983 unsigned long flags;
4984 u32 ip_addr[4] = {};
4985 u32 mgn;
4986 u32 no_mgs;
4987 int ret = 0;
4988 bool ipv4;
4989 u16 vlan_id;
4990 union irdma_sockaddr sgid_addr;
4991 unsigned char dmac[ETH_ALEN];
4992
4993 rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);
4994
4995 if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid)) {
4996 irdma_copy_ip_ntohl(ip_addr,
4997 sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32);
4998 irdma_get_vlan_mac_ipv6(ip_addr, &vlan_id, NULL);
4999 ipv4 = false;
5000 ibdev_dbg(&iwdev->ibdev,
5001 "VERBS: qp_id=%d, IP6address=%pI6\n", ibqp->qp_num,
5002 ip_addr);
5003 irdma_mcast_mac(ip_addr, dmac, false);
5004 } else {
5005 ip_addr[0] = ntohl(sgid_addr.saddr_in.sin_addr.s_addr);
5006 ipv4 = true;
5007 vlan_id = irdma_get_vlan_ipv4(ip_addr);
5008 irdma_mcast_mac(ip_addr, dmac, true);
5009 ibdev_dbg(&iwdev->ibdev,
5010 "VERBS: qp_id=%d, IP4address=%pI4, MAC=%pM\n",
5011 ibqp->qp_num, ip_addr, dmac);
5012 }
5013
5014 spin_lock_irqsave(&rf->qh_list_lock, flags);
5015 mc_qht_elem = mcast_list_lookup_ip(rf, ip_addr);
5016 if (!mc_qht_elem) {
5017 struct irdma_dma_mem *dma_mem_mc;
5018
5019 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
5020 mc_qht_elem = kzalloc_obj(*mc_qht_elem);
5021 if (!mc_qht_elem)
5022 return -ENOMEM;
5023
5024 mc_qht_elem->mc_info.ipv4_valid = ipv4;
5025 memcpy(mc_qht_elem->mc_info.dest_ip, ip_addr,
5026 sizeof(mc_qht_elem->mc_info.dest_ip));
5027 ret = irdma_alloc_rsrc(rf, rf->allocated_mcgs, rf->max_mcg,
5028 &mgn, &rf->next_mcg);
5029 if (ret) {
5030 kfree(mc_qht_elem);
5031 return -ENOMEM;
5032 }
5033
5034 mc_qht_elem->mc_info.mgn = mgn;
5035 dma_mem_mc = &mc_qht_elem->mc_grp_ctx.dma_mem_mc;
5036 dma_mem_mc->size = ALIGN(sizeof(u64) * IRDMA_MAX_MGS_PER_CTX,
5037 IRDMA_HW_PAGE_SIZE);
5038 dma_mem_mc->va = dma_alloc_coherent(rf->hw.device,
5039 dma_mem_mc->size,
5040 &dma_mem_mc->pa,
5041 GFP_KERNEL);
5042 if (!dma_mem_mc->va) {
5043 irdma_free_rsrc(rf, rf->allocated_mcgs, mgn);
5044 kfree(mc_qht_elem);
5045 return -ENOMEM;
5046 }
5047
5048 mc_qht_elem->mc_grp_ctx.mg_id = (u16)mgn;
5049 memcpy(mc_qht_elem->mc_grp_ctx.dest_ip_addr, ip_addr,
5050 sizeof(mc_qht_elem->mc_grp_ctx.dest_ip_addr));
5051 mc_qht_elem->mc_grp_ctx.ipv4_valid = ipv4;
5052 mc_qht_elem->mc_grp_ctx.vlan_id = vlan_id;
5053 if (vlan_id < VLAN_N_VID)
5054 mc_qht_elem->mc_grp_ctx.vlan_valid = true;
5055 mc_qht_elem->mc_grp_ctx.hmc_fcn_id = iwdev->rf->sc_dev.hmc_fn_id;
5056 mc_qht_elem->mc_grp_ctx.qs_handle =
5057 iwqp->sc_qp.vsi->qos[iwqp->sc_qp.user_pri].qs_handle;
5058 ether_addr_copy(mc_qht_elem->mc_grp_ctx.dest_mac_addr, dmac);
5059
5060 spin_lock_irqsave(&rf->qh_list_lock, flags);
5061 mcast_list_add(rf, mc_qht_elem);
5062 } else {
5063 if (mc_qht_elem->mc_grp_ctx.no_of_mgs ==
5064 IRDMA_MAX_MGS_PER_CTX) {
5065 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
5066 return -ENOMEM;
5067 }
5068 }
5069
5070 mcg_info.qp_id = iwqp->ibqp.qp_num;
5071 no_mgs = mc_qht_elem->mc_grp_ctx.no_of_mgs;
5072 irdma_sc_add_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info);
5073 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
5074
5075 /* Only if there is a change do we need to modify or create */
5076 if (!no_mgs) {
5077 ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
5078 IRDMA_OP_MC_CREATE);
5079 } else if (no_mgs != mc_qht_elem->mc_grp_ctx.no_of_mgs) {
5080 ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
5081 IRDMA_OP_MC_MODIFY);
5082 } else {
5083 return 0;
5084 }
5085
5086 if (ret)
5087 goto error;
5088
5089 return 0;
5090
5091 error:
5092 irdma_sc_del_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info);
5093 if (!mc_qht_elem->mc_grp_ctx.no_of_mgs) {
5094 mcast_list_del(mc_qht_elem);
5095 dma_free_coherent(rf->hw.device,
5096 mc_qht_elem->mc_grp_ctx.dma_mem_mc.size,
5097 mc_qht_elem->mc_grp_ctx.dma_mem_mc.va,
5098 mc_qht_elem->mc_grp_ctx.dma_mem_mc.pa);
5099 mc_qht_elem->mc_grp_ctx.dma_mem_mc.va = NULL;
5100 irdma_free_rsrc(rf, rf->allocated_mcgs,
5101 mc_qht_elem->mc_grp_ctx.mg_id);
5102 kfree(mc_qht_elem);
5103 }
5104
5105 return ret;
5106 }
5107
5108 /**
5109 * irdma_detach_mcast - detach a qp from a multicast group
5110 * @ibqp: ptr to qp
5111 * @ibgid: pointer to global ID
5112 * @lid: local ID
5113 *
5114 * returns error status
5115 */
irdma_detach_mcast(struct ib_qp * ibqp,union ib_gid * ibgid,u16 lid)5116 static int irdma_detach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid)
5117 {
5118 struct irdma_qp *iwqp = to_iwqp(ibqp);
5119 struct irdma_device *iwdev = iwqp->iwdev;
5120 struct irdma_pci_f *rf = iwdev->rf;
5121 u32 ip_addr[4] = {};
5122 struct mc_table_list *mc_qht_elem;
5123 struct irdma_mcast_grp_ctx_entry_info mcg_info = {};
5124 int ret;
5125 unsigned long flags;
5126 union irdma_sockaddr sgid_addr;
5127
5128 rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid);
5129 if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid))
5130 irdma_copy_ip_ntohl(ip_addr,
5131 sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32);
5132 else
5133 ip_addr[0] = ntohl(sgid_addr.saddr_in.sin_addr.s_addr);
5134
5135 spin_lock_irqsave(&rf->qh_list_lock, flags);
5136 mc_qht_elem = mcast_list_lookup_ip(rf, ip_addr);
5137 if (!mc_qht_elem) {
5138 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
5139 ibdev_dbg(&iwdev->ibdev,
5140 "VERBS: address not found MCG\n");
5141 return 0;
5142 }
5143
5144 mcg_info.qp_id = iwqp->ibqp.qp_num;
5145 irdma_sc_del_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info);
5146 if (!mc_qht_elem->mc_grp_ctx.no_of_mgs) {
5147 mcast_list_del(mc_qht_elem);
5148 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
5149 ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
5150 IRDMA_OP_MC_DESTROY);
5151 if (ret) {
5152 ibdev_dbg(&iwdev->ibdev,
5153 "VERBS: failed MC_DESTROY MCG\n");
5154 spin_lock_irqsave(&rf->qh_list_lock, flags);
5155 mcast_list_add(rf, mc_qht_elem);
5156 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
5157 return -EAGAIN;
5158 }
5159
5160 dma_free_coherent(rf->hw.device,
5161 mc_qht_elem->mc_grp_ctx.dma_mem_mc.size,
5162 mc_qht_elem->mc_grp_ctx.dma_mem_mc.va,
5163 mc_qht_elem->mc_grp_ctx.dma_mem_mc.pa);
5164 mc_qht_elem->mc_grp_ctx.dma_mem_mc.va = NULL;
5165 irdma_free_rsrc(rf, rf->allocated_mcgs,
5166 mc_qht_elem->mc_grp_ctx.mg_id);
5167 kfree(mc_qht_elem);
5168 } else {
5169 spin_unlock_irqrestore(&rf->qh_list_lock, flags);
5170 ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx,
5171 IRDMA_OP_MC_MODIFY);
5172 if (ret) {
5173 ibdev_dbg(&iwdev->ibdev,
5174 "VERBS: failed Modify MCG\n");
5175 return ret;
5176 }
5177 }
5178
5179 return 0;
5180 }
5181
irdma_create_hw_ah(struct irdma_device * iwdev,struct irdma_ah * ah,bool sleep)5182 static int irdma_create_hw_ah(struct irdma_device *iwdev, struct irdma_ah *ah, bool sleep)
5183 {
5184 struct irdma_pci_f *rf = iwdev->rf;
5185 int err;
5186
5187 err = irdma_alloc_rsrc(rf, rf->allocated_ahs, rf->max_ah, &ah->sc_ah.ah_info.ah_idx,
5188 &rf->next_ah);
5189 if (err)
5190 return err;
5191
5192 err = irdma_ah_cqp_op(rf, &ah->sc_ah, IRDMA_OP_AH_CREATE, sleep,
5193 irdma_gsi_ud_qp_ah_cb, &ah->sc_ah);
5194
5195 if (err) {
5196 ibdev_dbg(&iwdev->ibdev, "VERBS: CQP-OP Create AH fail");
5197 goto err_ah_create;
5198 }
5199
5200 if (!sleep) {
5201 const u64 tmout_ms = irdma_get_timeout_threshold(&rf->sc_dev) *
5202 CQP_COMPL_WAIT_TIME_MS;
5203
5204 if (poll_timeout_us_atomic(irdma_cqp_ce_handler(rf,
5205 &rf->ccq.sc_cq),
5206 ah->sc_ah.ah_info.ah_valid, 1,
5207 tmout_ms * USEC_PER_MSEC, false)) {
5208 ibdev_dbg(&iwdev->ibdev,
5209 "VERBS: CQP create AH timed out");
5210 err = -ETIMEDOUT;
5211 goto err_ah_create;
5212 }
5213 }
5214 return 0;
5215
5216 err_ah_create:
5217 irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, ah->sc_ah.ah_info.ah_idx);
5218
5219 return err;
5220 }
5221
irdma_setup_ah(struct ib_ah * ibah,struct rdma_ah_init_attr * attr)5222 static int irdma_setup_ah(struct ib_ah *ibah, struct rdma_ah_init_attr *attr)
5223 {
5224 struct irdma_pd *pd = to_iwpd(ibah->pd);
5225 struct irdma_ah *ah = container_of(ibah, struct irdma_ah, ibah);
5226 struct rdma_ah_attr *ah_attr = attr->ah_attr;
5227 const struct ib_gid_attr *sgid_attr;
5228 struct irdma_device *iwdev = to_iwdev(ibah->pd->device);
5229 struct irdma_pci_f *rf = iwdev->rf;
5230 struct irdma_sc_ah *sc_ah;
5231 struct irdma_ah_info *ah_info;
5232 union irdma_sockaddr sgid_addr, dgid_addr;
5233 int err;
5234 u8 dmac[ETH_ALEN];
5235
5236 ah->pd = pd;
5237 sc_ah = &ah->sc_ah;
5238 sc_ah->ah_info.vsi = &iwdev->vsi;
5239 irdma_sc_init_ah(&rf->sc_dev, sc_ah);
5240 ah->sgid_index = ah_attr->grh.sgid_index;
5241 sgid_attr = ah_attr->grh.sgid_attr;
5242 memcpy(&ah->dgid, &ah_attr->grh.dgid, sizeof(ah->dgid));
5243 rdma_gid2ip((struct sockaddr *)&sgid_addr, &sgid_attr->gid);
5244 rdma_gid2ip((struct sockaddr *)&dgid_addr, &ah_attr->grh.dgid);
5245 ah->av.attrs = *ah_attr;
5246 ah->av.net_type = rdma_gid_attr_network_type(sgid_attr);
5247 ah_info = &sc_ah->ah_info;
5248 ah_info->pd_idx = pd->sc_pd.pd_id;
5249 if (ah_attr->ah_flags & IB_AH_GRH) {
5250 ah_info->flow_label = ah_attr->grh.flow_label;
5251 ah_info->hop_ttl = ah_attr->grh.hop_limit;
5252 ah_info->tc_tos = ah_attr->grh.traffic_class;
5253 }
5254
5255 ether_addr_copy(dmac, ah_attr->roce.dmac);
5256 if (ah->av.net_type == RDMA_NETWORK_IPV4) {
5257 ah_info->ipv4_valid = true;
5258 ah_info->dest_ip_addr[0] =
5259 ntohl(dgid_addr.saddr_in.sin_addr.s_addr);
5260 ah_info->src_ip_addr[0] =
5261 ntohl(sgid_addr.saddr_in.sin_addr.s_addr);
5262 ah_info->do_lpbk = irdma_ipv4_is_lpb(ah_info->src_ip_addr[0],
5263 ah_info->dest_ip_addr[0]);
5264 if (ipv4_is_multicast(dgid_addr.saddr_in.sin_addr.s_addr)) {
5265 ah_info->do_lpbk = true;
5266 irdma_mcast_mac(ah_info->dest_ip_addr, dmac, true);
5267 }
5268 } else {
5269 irdma_copy_ip_ntohl(ah_info->dest_ip_addr,
5270 dgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32);
5271 irdma_copy_ip_ntohl(ah_info->src_ip_addr,
5272 sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32);
5273 ah_info->do_lpbk = irdma_ipv6_is_lpb(ah_info->src_ip_addr,
5274 ah_info->dest_ip_addr);
5275 if (rdma_is_multicast_addr(&dgid_addr.saddr_in6.sin6_addr)) {
5276 ah_info->do_lpbk = true;
5277 irdma_mcast_mac(ah_info->dest_ip_addr, dmac, false);
5278 }
5279 }
5280
5281 err = rdma_read_gid_l2_fields(sgid_attr, &ah_info->vlan_tag,
5282 ah_info->mac_addr);
5283 if (err)
5284 return err;
5285
5286 ah_info->dst_arpindex = irdma_add_arp(iwdev->rf, ah_info->dest_ip_addr,
5287 ah_info->ipv4_valid, dmac);
5288
5289 if (ah_info->dst_arpindex == -1)
5290 return -EINVAL;
5291
5292 if (ah_info->vlan_tag >= VLAN_N_VID && iwdev->dcb_vlan_mode)
5293 ah_info->vlan_tag = 0;
5294
5295 if (ah_info->vlan_tag < VLAN_N_VID) {
5296 u8 prio = rt_tos2priority(ah_info->tc_tos);
5297
5298 prio = irdma_roce_get_vlan_prio(sgid_attr, prio);
5299
5300 ah_info->vlan_tag |= (u16)prio << VLAN_PRIO_SHIFT;
5301 ah_info->insert_vlan_tag = true;
5302 }
5303
5304 return 0;
5305 }
5306
5307 /**
5308 * irdma_ah_exists - Check for existing identical AH
5309 * @iwdev: irdma device
5310 * @new_ah: AH to check for
5311 *
5312 * returns true if AH is found, false if not found.
5313 */
irdma_ah_exists(struct irdma_device * iwdev,struct irdma_ah * new_ah)5314 static bool irdma_ah_exists(struct irdma_device *iwdev,
5315 struct irdma_ah *new_ah)
5316 {
5317 struct irdma_ah *ah;
5318 u32 key = new_ah->sc_ah.ah_info.dest_ip_addr[0] ^
5319 new_ah->sc_ah.ah_info.dest_ip_addr[1] ^
5320 new_ah->sc_ah.ah_info.dest_ip_addr[2] ^
5321 new_ah->sc_ah.ah_info.dest_ip_addr[3];
5322
5323 hash_for_each_possible(iwdev->rf->ah_hash_tbl, ah, list, key) {
5324 /* Set ah_valid and ah_id the same so memcmp can work */
5325 new_ah->sc_ah.ah_info.ah_idx = ah->sc_ah.ah_info.ah_idx;
5326 new_ah->sc_ah.ah_info.ah_valid = ah->sc_ah.ah_info.ah_valid;
5327 if (!memcmp(&ah->sc_ah.ah_info, &new_ah->sc_ah.ah_info,
5328 sizeof(ah->sc_ah.ah_info))) {
5329 refcount_inc(&ah->refcnt);
5330 new_ah->parent_ah = ah;
5331 return true;
5332 }
5333 }
5334
5335 return false;
5336 }
5337
5338 /**
5339 * irdma_destroy_ah - Destroy address handle
5340 * @ibah: pointer to address handle
5341 * @ah_flags: flags for sleepable
5342 */
irdma_destroy_ah(struct ib_ah * ibah,u32 ah_flags)5343 static int irdma_destroy_ah(struct ib_ah *ibah, u32 ah_flags)
5344 {
5345 struct irdma_device *iwdev = to_iwdev(ibah->device);
5346 struct irdma_ah *ah = to_iwah(ibah);
5347
5348 if ((ah_flags & RDMA_DESTROY_AH_SLEEPABLE) && ah->parent_ah) {
5349 mutex_lock(&iwdev->rf->ah_tbl_lock);
5350 if (!refcount_dec_and_test(&ah->parent_ah->refcnt)) {
5351 mutex_unlock(&iwdev->rf->ah_tbl_lock);
5352 return 0;
5353 }
5354 hash_del(&ah->parent_ah->list);
5355 kfree(ah->parent_ah);
5356 mutex_unlock(&iwdev->rf->ah_tbl_lock);
5357 }
5358
5359 irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, IRDMA_OP_AH_DESTROY,
5360 false, NULL, ah);
5361
5362 irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs,
5363 ah->sc_ah.ah_info.ah_idx);
5364
5365 return 0;
5366 }
5367
5368 /**
5369 * irdma_create_user_ah - create user address handle
5370 * @ibah: address handle
5371 * @attr: address handle attributes
5372 * @udata: User data
5373 *
5374 * returns 0 on success, error otherwise
5375 */
irdma_create_user_ah(struct ib_ah * ibah,struct rdma_ah_init_attr * attr,struct ib_udata * udata)5376 static int irdma_create_user_ah(struct ib_ah *ibah,
5377 struct rdma_ah_init_attr *attr,
5378 struct ib_udata *udata)
5379 {
5380 #define IRDMA_CREATE_AH_MIN_RESP_LEN offsetofend(struct irdma_create_ah_resp, rsvd)
5381 struct irdma_ah *ah = container_of(ibah, struct irdma_ah, ibah);
5382 struct irdma_device *iwdev = to_iwdev(ibah->pd->device);
5383 struct irdma_create_ah_resp uresp = {};
5384 struct irdma_ah *parent_ah;
5385 int err;
5386
5387 err = ib_is_udata_in_empty(udata);
5388 if (err)
5389 return err;
5390
5391 if (udata->outlen < IRDMA_CREATE_AH_MIN_RESP_LEN)
5392 return -EINVAL;
5393
5394 err = irdma_setup_ah(ibah, attr);
5395 if (err)
5396 return err;
5397 mutex_lock(&iwdev->rf->ah_tbl_lock);
5398 if (!irdma_ah_exists(iwdev, ah)) {
5399 err = irdma_create_hw_ah(iwdev, ah, true);
5400 if (err) {
5401 mutex_unlock(&iwdev->rf->ah_tbl_lock);
5402 return err;
5403 }
5404 /* Add new AH to list */
5405 parent_ah = kmemdup(ah, sizeof(*ah), GFP_KERNEL);
5406 if (parent_ah) {
5407 u32 key = parent_ah->sc_ah.ah_info.dest_ip_addr[0] ^
5408 parent_ah->sc_ah.ah_info.dest_ip_addr[1] ^
5409 parent_ah->sc_ah.ah_info.dest_ip_addr[2] ^
5410 parent_ah->sc_ah.ah_info.dest_ip_addr[3];
5411
5412 ah->parent_ah = parent_ah;
5413 hash_add(iwdev->rf->ah_hash_tbl, &parent_ah->list, key);
5414 refcount_set(&parent_ah->refcnt, 1);
5415 }
5416 }
5417 mutex_unlock(&iwdev->rf->ah_tbl_lock);
5418
5419 uresp.ah_id = ah->sc_ah.ah_info.ah_idx;
5420 err = ib_respond_udata(udata, uresp);
5421 if (err)
5422 irdma_destroy_ah(ibah, attr->flags);
5423
5424 return err;
5425 }
5426
5427 /**
5428 * irdma_create_ah - create address handle
5429 * @ibah: address handle
5430 * @attr: address handle attributes
5431 * @udata: NULL
5432 *
5433 * returns 0 on success, error otherwise
5434 */
irdma_create_ah(struct ib_ah * ibah,struct rdma_ah_init_attr * attr,struct ib_udata * udata)5435 static int irdma_create_ah(struct ib_ah *ibah, struct rdma_ah_init_attr *attr,
5436 struct ib_udata *udata)
5437 {
5438 struct irdma_ah *ah = container_of(ibah, struct irdma_ah, ibah);
5439 struct irdma_device *iwdev = to_iwdev(ibah->pd->device);
5440 int err;
5441
5442 err = ib_no_udata_io(udata);
5443 if (err)
5444 return err;
5445
5446 err = irdma_setup_ah(ibah, attr);
5447 if (err)
5448 return err;
5449 err = irdma_create_hw_ah(iwdev, ah, attr->flags & RDMA_CREATE_AH_SLEEPABLE);
5450
5451 return err;
5452 }
5453
5454 /**
5455 * irdma_query_ah - Query address handle
5456 * @ibah: pointer to address handle
5457 * @ah_attr: address handle attributes
5458 */
irdma_query_ah(struct ib_ah * ibah,struct rdma_ah_attr * ah_attr)5459 static int irdma_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr)
5460 {
5461 struct irdma_ah *ah = to_iwah(ibah);
5462
5463 memset(ah_attr, 0, sizeof(*ah_attr));
5464 if (ah->av.attrs.ah_flags & IB_AH_GRH) {
5465 ah_attr->ah_flags = IB_AH_GRH;
5466 ah_attr->grh.flow_label = ah->sc_ah.ah_info.flow_label;
5467 ah_attr->grh.traffic_class = ah->sc_ah.ah_info.tc_tos;
5468 ah_attr->grh.hop_limit = ah->sc_ah.ah_info.hop_ttl;
5469 ah_attr->grh.sgid_index = ah->sgid_index;
5470 memcpy(&ah_attr->grh.dgid, &ah->dgid,
5471 sizeof(ah_attr->grh.dgid));
5472 }
5473
5474 return 0;
5475 }
5476
irdma_get_link_layer(struct ib_device * ibdev,u32 port_num)5477 static enum rdma_link_layer irdma_get_link_layer(struct ib_device *ibdev,
5478 u32 port_num)
5479 {
5480 return IB_LINK_LAYER_ETHERNET;
5481 }
5482
5483 static const struct ib_device_ops irdma_gen1_dev_ops = {
5484 .dealloc_driver = irdma_ib_dealloc_device,
5485 };
5486
5487 static const struct ib_device_ops irdma_gen3_dev_ops = {
5488 .alloc_mw = irdma_alloc_mw,
5489 .create_srq = irdma_create_srq,
5490 .dealloc_mw = irdma_dealloc_mw,
5491 .destroy_srq = irdma_destroy_srq,
5492 .modify_srq = irdma_modify_srq,
5493 .post_srq_recv = irdma_post_srq_recv,
5494 .query_srq = irdma_query_srq,
5495 };
5496
5497 static const struct ib_device_ops irdma_roce_dev_ops = {
5498 .attach_mcast = irdma_attach_mcast,
5499 .create_ah = irdma_create_ah,
5500 .create_user_ah = irdma_create_user_ah,
5501 .destroy_ah = irdma_destroy_ah,
5502 .detach_mcast = irdma_detach_mcast,
5503 .get_link_layer = irdma_get_link_layer,
5504 .get_port_immutable = irdma_roce_port_immutable,
5505 .modify_qp = irdma_modify_qp_roce,
5506 .query_ah = irdma_query_ah,
5507 .query_pkey = irdma_query_pkey,
5508 };
5509
5510 static const struct ib_device_ops irdma_iw_dev_ops = {
5511 .get_port_immutable = irdma_iw_port_immutable,
5512 .iw_accept = irdma_accept,
5513 .iw_add_ref = irdma_qp_add_ref,
5514 .iw_connect = irdma_connect,
5515 .iw_create_listen = irdma_create_listen,
5516 .iw_destroy_listen = irdma_destroy_listen,
5517 .iw_get_qp = irdma_get_qp,
5518 .iw_reject = irdma_reject,
5519 .iw_rem_ref = irdma_qp_rem_ref,
5520 .modify_qp = irdma_modify_qp,
5521 .query_gid = irdma_query_gid,
5522 };
5523
5524 static const struct ib_device_ops irdma_dev_ops = {
5525 .owner = THIS_MODULE,
5526 .driver_id = RDMA_DRIVER_IRDMA,
5527 .uverbs_abi_ver = IRDMA_ABI_VER,
5528 .uverbs_robust_udata = true,
5529
5530 .alloc_hw_port_stats = irdma_alloc_hw_port_stats,
5531 .alloc_mr = irdma_alloc_mr,
5532 .alloc_pd = irdma_alloc_pd,
5533 .alloc_ucontext = irdma_alloc_ucontext,
5534 .create_cq = irdma_create_cq,
5535 .create_qp = irdma_create_qp,
5536 .dealloc_driver = irdma_ib_dealloc_device,
5537 .dealloc_mw = irdma_dealloc_mw,
5538 .dealloc_pd = irdma_dealloc_pd,
5539 .dealloc_ucontext = irdma_dealloc_ucontext,
5540 .dereg_mr = irdma_dereg_mr,
5541 .destroy_cq = irdma_destroy_cq,
5542 .destroy_qp = irdma_destroy_qp,
5543 .disassociate_ucontext = irdma_disassociate_ucontext,
5544 .get_dev_fw_str = irdma_get_dev_fw_str,
5545 .get_dma_mr = irdma_get_dma_mr,
5546 .get_hw_stats = irdma_get_hw_stats,
5547 .map_mr_sg = irdma_map_mr_sg,
5548 .mmap = irdma_mmap,
5549 .mmap_free = irdma_mmap_free,
5550 .poll_cq = irdma_poll_cq,
5551 .post_recv = irdma_post_recv,
5552 .post_send = irdma_post_send,
5553 .query_device = irdma_query_device,
5554 .query_port = irdma_query_port,
5555 .query_qp = irdma_query_qp,
5556 .reg_user_mr = irdma_reg_user_mr,
5557 .reg_user_mr_dmabuf = irdma_reg_user_mr_dmabuf,
5558 .rereg_user_mr = irdma_rereg_user_mr,
5559 .req_notify_cq = irdma_req_notify_cq,
5560 .resize_user_cq = irdma_resize_cq,
5561 INIT_RDMA_OBJ_SIZE(ib_pd, irdma_pd, ibpd),
5562 INIT_RDMA_OBJ_SIZE(ib_ucontext, irdma_ucontext, ibucontext),
5563 INIT_RDMA_OBJ_SIZE(ib_ah, irdma_ah, ibah),
5564 INIT_RDMA_OBJ_SIZE(ib_cq, irdma_cq, ibcq),
5565 INIT_RDMA_OBJ_SIZE(ib_mw, irdma_mr, ibmw),
5566 INIT_RDMA_OBJ_SIZE(ib_qp, irdma_qp, ibqp),
5567 INIT_RDMA_OBJ_SIZE(ib_srq, irdma_srq, ibsrq),
5568 };
5569
5570 /**
5571 * irdma_init_roce_device - initialization of roce rdma device
5572 * @iwdev: irdma device
5573 */
irdma_init_roce_device(struct irdma_device * iwdev)5574 static void irdma_init_roce_device(struct irdma_device *iwdev)
5575 {
5576 iwdev->ibdev.node_type = RDMA_NODE_IB_CA;
5577 addrconf_addr_eui48((u8 *)&iwdev->ibdev.node_guid,
5578 iwdev->netdev->dev_addr);
5579 ib_set_device_ops(&iwdev->ibdev, &irdma_roce_dev_ops);
5580 }
5581
5582 /**
5583 * irdma_init_iw_device - initialization of iwarp rdma device
5584 * @iwdev: irdma device
5585 */
irdma_init_iw_device(struct irdma_device * iwdev)5586 static void irdma_init_iw_device(struct irdma_device *iwdev)
5587 {
5588 struct net_device *netdev = iwdev->netdev;
5589
5590 iwdev->ibdev.node_type = RDMA_NODE_RNIC;
5591 addrconf_addr_eui48((u8 *)&iwdev->ibdev.node_guid,
5592 netdev->dev_addr);
5593 memcpy(iwdev->ibdev.iw_ifname, netdev->name,
5594 sizeof(iwdev->ibdev.iw_ifname));
5595 ib_set_device_ops(&iwdev->ibdev, &irdma_iw_dev_ops);
5596 }
5597
5598 /**
5599 * irdma_init_rdma_device - initialization of rdma device
5600 * @iwdev: irdma device
5601 */
irdma_init_rdma_device(struct irdma_device * iwdev)5602 static void irdma_init_rdma_device(struct irdma_device *iwdev)
5603 {
5604 struct pci_dev *pcidev = iwdev->rf->pcidev;
5605
5606 if (iwdev->roce_mode)
5607 irdma_init_roce_device(iwdev);
5608 else
5609 irdma_init_iw_device(iwdev);
5610
5611 iwdev->ibdev.phys_port_cnt = 1;
5612 iwdev->ibdev.num_comp_vectors = iwdev->rf->ceqs_count;
5613 iwdev->ibdev.dev.parent = &pcidev->dev;
5614 ib_set_device_ops(&iwdev->ibdev, &irdma_dev_ops);
5615 if (iwdev->rf->rdma_ver == IRDMA_GEN_1)
5616 ib_set_device_ops(&iwdev->ibdev, &irdma_gen1_dev_ops);
5617 if (iwdev->rf->rdma_ver >= IRDMA_GEN_3)
5618 ib_set_device_ops(&iwdev->ibdev, &irdma_gen3_dev_ops);
5619 }
5620
5621 /**
5622 * irdma_port_ibevent - indicate port event
5623 * @iwdev: irdma device
5624 */
irdma_port_ibevent(struct irdma_device * iwdev)5625 void irdma_port_ibevent(struct irdma_device *iwdev)
5626 {
5627 struct ib_event event;
5628
5629 event.device = &iwdev->ibdev;
5630 event.element.port_num = 1;
5631 event.event =
5632 iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
5633 ib_dispatch_event(&event);
5634 }
5635
5636 /**
5637 * irdma_ib_unregister_device - unregister rdma device from IB
5638 * core
5639 * @iwdev: irdma device
5640 */
irdma_ib_unregister_device(struct irdma_device * iwdev)5641 void irdma_ib_unregister_device(struct irdma_device *iwdev)
5642 {
5643 iwdev->iw_status = 0;
5644 irdma_port_ibevent(iwdev);
5645 ib_unregister_device(&iwdev->ibdev);
5646 }
5647
5648 /**
5649 * irdma_ib_register_device - register irdma device to IB core
5650 * @iwdev: irdma device
5651 */
irdma_ib_register_device(struct irdma_device * iwdev)5652 int irdma_ib_register_device(struct irdma_device *iwdev)
5653 {
5654 int ret;
5655
5656 irdma_init_rdma_device(iwdev);
5657
5658 ret = ib_device_set_netdev(&iwdev->ibdev, iwdev->netdev, 1);
5659 if (ret)
5660 goto error;
5661 dma_set_max_seg_size(iwdev->rf->hw.device, UINT_MAX);
5662 ret = ib_register_device(&iwdev->ibdev, "irdma%d", iwdev->rf->hw.device);
5663 if (ret)
5664 goto error;
5665
5666 iwdev->iw_status = 1;
5667 irdma_port_ibevent(iwdev);
5668
5669 return 0;
5670
5671 error:
5672 if (ret)
5673 ibdev_dbg(&iwdev->ibdev, "VERBS: Register RDMA device fail\n");
5674
5675 return ret;
5676 }
5677
5678 /**
5679 * irdma_ib_dealloc_device
5680 * @ibdev: ib device
5681 *
5682 * callback from ibdev dealloc_driver to deallocate resources
5683 * unber irdma device
5684 */
irdma_ib_dealloc_device(struct ib_device * ibdev)5685 void irdma_ib_dealloc_device(struct ib_device *ibdev)
5686 {
5687 struct irdma_device *iwdev = to_iwdev(ibdev);
5688
5689 irdma_rt_deinit_hw(iwdev);
5690 if (!iwdev->is_vport) {
5691 irdma_ctrl_deinit_hw(iwdev->rf);
5692 if (iwdev->rf->vchnl_wq) {
5693 destroy_workqueue(iwdev->rf->vchnl_wq);
5694 mutex_destroy(&iwdev->rf->sc_dev.vchnl_mutex);
5695 }
5696 }
5697 }
5698