1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2010-2017 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
4 *
5 * membarrier system call
6 */
7 #include <uapi/linux/membarrier.h>
8 #include "sched.h"
9
10 /*
11 * For documentation purposes, here are some membarrier ordering
12 * scenarios to keep in mind:
13 *
14 * A) Userspace thread execution after IPI vs membarrier's memory
15 * barrier before sending the IPI
16 *
17 * Userspace variables:
18 *
19 * int x = 0, y = 0;
20 *
21 * The memory barrier at the start of membarrier() on CPU0 is necessary in
22 * order to enforce the guarantee that any writes occurring on CPU0 before
23 * the membarrier() is executed will be visible to any code executing on
24 * CPU1 after the IPI-induced memory barrier:
25 *
26 * CPU0 CPU1
27 *
28 * x = 1
29 * membarrier():
30 * a: smp_mb()
31 * b: send IPI IPI-induced mb
32 * c: smp_mb()
33 * r2 = y
34 * y = 1
35 * barrier()
36 * r1 = x
37 *
38 * BUG_ON(r1 == 0 && r2 == 0)
39 *
40 * The write to y and load from x by CPU1 are unordered by the hardware,
41 * so it's possible to have "r1 = x" reordered before "y = 1" at any
42 * point after (b). If the memory barrier at (a) is omitted, then "x = 1"
43 * can be reordered after (a) (although not after (c)), so we get r1 == 0
44 * and r2 == 0. This violates the guarantee that membarrier() is
45 * supposed by provide.
46 *
47 * The timing of the memory barrier at (a) has to ensure that it executes
48 * before the IPI-induced memory barrier on CPU1.
49 *
50 * B) Userspace thread execution before IPI vs membarrier's memory
51 * barrier after completing the IPI
52 *
53 * Userspace variables:
54 *
55 * int x = 0, y = 0;
56 *
57 * The memory barrier at the end of membarrier() on CPU0 is necessary in
58 * order to enforce the guarantee that any writes occurring on CPU1 before
59 * the membarrier() is executed will be visible to any code executing on
60 * CPU0 after the membarrier():
61 *
62 * CPU0 CPU1
63 *
64 * x = 1
65 * barrier()
66 * y = 1
67 * r2 = y
68 * membarrier():
69 * a: smp_mb()
70 * b: send IPI IPI-induced mb
71 * c: smp_mb()
72 * r1 = x
73 * BUG_ON(r1 == 0 && r2 == 1)
74 *
75 * The writes to x and y are unordered by the hardware, so it's possible to
76 * have "r2 = 1" even though the write to x doesn't execute until (b). If
77 * the memory barrier at (c) is omitted then "r1 = x" can be reordered
78 * before (b) (although not before (a)), so we get "r1 = 0". This violates
79 * the guarantee that membarrier() is supposed to provide.
80 *
81 * The timing of the memory barrier at (c) has to ensure that it executes
82 * after the IPI-induced memory barrier on CPU1.
83 *
84 * C) Scheduling userspace thread -> kthread -> userspace thread vs membarrier
85 *
86 * CPU0 CPU1
87 *
88 * membarrier():
89 * a: smp_mb()
90 * d: switch to kthread (includes mb)
91 * b: read rq->curr->mm == NULL
92 * e: switch to user (includes mb)
93 * c: smp_mb()
94 *
95 * Using the scenario from (A), we can show that (a) needs to be paired
96 * with (e). Using the scenario from (B), we can show that (c) needs to
97 * be paired with (d).
98 *
99 * D) exit_mm vs membarrier
100 *
101 * Two thread groups are created, A and B. Thread group B is created by
102 * issuing clone from group A with flag CLONE_VM set, but not CLONE_THREAD.
103 * Let's assume we have a single thread within each thread group (Thread A
104 * and Thread B). Thread A runs on CPU0, Thread B runs on CPU1.
105 *
106 * CPU0 CPU1
107 *
108 * membarrier():
109 * a: smp_mb()
110 * exit_mm():
111 * d: smp_mb()
112 * e: current->mm = NULL
113 * b: read rq->curr->mm == NULL
114 * c: smp_mb()
115 *
116 * Using scenario (B), we can show that (c) needs to be paired with (d).
117 *
118 * E) kthread_{use,unuse}_mm vs membarrier
119 *
120 * CPU0 CPU1
121 *
122 * membarrier():
123 * a: smp_mb()
124 * kthread_unuse_mm()
125 * d: smp_mb()
126 * e: current->mm = NULL
127 * b: read rq->curr->mm == NULL
128 * kthread_use_mm()
129 * f: current->mm = mm
130 * g: smp_mb()
131 * c: smp_mb()
132 *
133 * Using the scenario from (A), we can show that (a) needs to be paired
134 * with (g). Using the scenario from (B), we can show that (c) needs to
135 * be paired with (d).
136 */
137
138 /*
139 * Bitmask made from a "or" of all commands within enum membarrier_cmd,
140 * except MEMBARRIER_CMD_QUERY.
141 */
142 #ifdef CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE
143 #define MEMBARRIER_PRIVATE_EXPEDITED_SYNC_CORE_BITMASK \
144 (MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE \
145 | MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE)
146 #else
147 #define MEMBARRIER_PRIVATE_EXPEDITED_SYNC_CORE_BITMASK 0
148 #endif
149
150 #ifdef CONFIG_RSEQ
151 #define MEMBARRIER_PRIVATE_EXPEDITED_RSEQ_BITMASK \
152 (MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ \
153 | MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ)
154 #else
155 #define MEMBARRIER_PRIVATE_EXPEDITED_RSEQ_BITMASK 0
156 #endif
157
158 #define MEMBARRIER_CMD_BITMASK \
159 (MEMBARRIER_CMD_GLOBAL | MEMBARRIER_CMD_GLOBAL_EXPEDITED \
160 | MEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED \
161 | MEMBARRIER_CMD_PRIVATE_EXPEDITED \
162 | MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED \
163 | MEMBARRIER_PRIVATE_EXPEDITED_SYNC_CORE_BITMASK \
164 | MEMBARRIER_PRIVATE_EXPEDITED_RSEQ_BITMASK \
165 | MEMBARRIER_CMD_GET_REGISTRATIONS)
166
167 static DEFINE_MUTEX(membarrier_ipi_mutex);
168 #define SERIALIZE_IPI() guard(mutex)(&membarrier_ipi_mutex)
169
ipi_mb(void * info)170 static void ipi_mb(void *info)
171 {
172 smp_mb(); /* IPIs should be serializing but paranoid. */
173 }
174
ipi_sync_core(void * info)175 static void ipi_sync_core(void *info)
176 {
177 /*
178 * The smp_mb() in membarrier after all the IPIs is supposed to
179 * ensure that memory on remote CPUs that occur before the IPI
180 * become visible to membarrier()'s caller -- see scenario B in
181 * the big comment at the top of this file.
182 *
183 * A sync_core() would provide this guarantee, but
184 * sync_core_before_usermode() might end up being deferred until
185 * after membarrier()'s smp_mb().
186 */
187 smp_mb(); /* IPIs should be serializing but paranoid. */
188
189 sync_core_before_usermode();
190 }
191
ipi_rseq(void * info)192 static void ipi_rseq(void *info)
193 {
194 /*
195 * Ensure that all stores done by the calling thread are visible
196 * to the current task before the current task resumes. We could
197 * probably optimize this away on most architectures, but by the
198 * time we've already sent an IPI, the cost of the extra smp_mb()
199 * is negligible.
200 */
201 smp_mb();
202 /*
203 * Legacy mode requires that IDs are written and the critical section is
204 * evaluated. V2 optimized mode handles the critical section and IDs are
205 * only updated if they change as a consequence of preemption after
206 * return from this IPI.
207 */
208 if (rseq_v2(current))
209 rseq_sched_switch_event(current);
210 else
211 rseq_force_update();
212 }
213
ipi_sync_rq_state(void * info)214 static void ipi_sync_rq_state(void *info)
215 {
216 struct mm_struct *mm = (struct mm_struct *) info;
217
218 if (current->mm != mm)
219 return;
220 this_cpu_write(runqueues.membarrier_state,
221 atomic_read(&mm->membarrier_state));
222 /*
223 * Issue a memory barrier after setting
224 * MEMBARRIER_STATE_GLOBAL_EXPEDITED in the current runqueue to
225 * guarantee that no memory access following registration is reordered
226 * before registration.
227 */
228 smp_mb();
229 }
230
membarrier_exec_mmap(struct mm_struct * mm)231 void membarrier_exec_mmap(struct mm_struct *mm)
232 {
233 /*
234 * Issue a memory barrier before clearing membarrier_state to
235 * guarantee that no memory access prior to exec is reordered after
236 * clearing this state.
237 */
238 smp_mb();
239 atomic_set(&mm->membarrier_state, 0);
240 /*
241 * Keep the runqueue membarrier_state in sync with this mm
242 * membarrier_state.
243 */
244 this_cpu_write(runqueues.membarrier_state, 0);
245 }
246
membarrier_update_current_mm(struct mm_struct * next_mm)247 void membarrier_update_current_mm(struct mm_struct *next_mm)
248 {
249 struct rq *rq = this_rq();
250 int membarrier_state = 0;
251
252 if (next_mm)
253 membarrier_state = atomic_read(&next_mm->membarrier_state);
254 if (READ_ONCE(rq->membarrier_state) == membarrier_state)
255 return;
256 WRITE_ONCE(rq->membarrier_state, membarrier_state);
257 }
258
membarrier_global_expedited(void)259 static int membarrier_global_expedited(void)
260 {
261 int cpu;
262 cpumask_var_t tmpmask;
263
264 if (num_online_cpus() == 1)
265 return 0;
266
267 /*
268 * Matches memory barriers after rq->curr modification in
269 * scheduler.
270 */
271 smp_mb(); /* system call entry is not a mb. */
272
273 if (!zalloc_cpumask_var(&tmpmask, GFP_KERNEL))
274 return -ENOMEM;
275
276 SERIALIZE_IPI();
277 cpus_read_lock();
278 rcu_read_lock();
279 for_each_online_cpu(cpu) {
280 struct task_struct *p;
281
282 /*
283 * Skipping the current CPU is OK even through we can be
284 * migrated at any point. The current CPU, at the point
285 * where we read raw_smp_processor_id(), is ensured to
286 * be in program order with respect to the caller
287 * thread. Therefore, we can skip this CPU from the
288 * iteration.
289 */
290 if (cpu == raw_smp_processor_id())
291 continue;
292
293 if (!(READ_ONCE(cpu_rq(cpu)->membarrier_state) &
294 MEMBARRIER_STATE_GLOBAL_EXPEDITED))
295 continue;
296
297 /*
298 * Skip the CPU if it runs a kernel thread which is not using
299 * a task mm.
300 */
301 p = rcu_dereference(cpu_rq(cpu)->curr);
302 if (!p->mm)
303 continue;
304
305 __cpumask_set_cpu(cpu, tmpmask);
306 }
307 rcu_read_unlock();
308
309 preempt_disable();
310 smp_call_function_many(tmpmask, ipi_mb, NULL, 1);
311 preempt_enable();
312
313 free_cpumask_var(tmpmask);
314 cpus_read_unlock();
315
316 /*
317 * Memory barrier on the caller thread _after_ we finished
318 * waiting for the last IPI. Matches memory barriers before
319 * rq->curr modification in scheduler.
320 */
321 smp_mb(); /* exit from system call is not a mb */
322 return 0;
323 }
324
membarrier_private_expedited(int flags,int cpu_id)325 static int membarrier_private_expedited(int flags, int cpu_id)
326 {
327 cpumask_var_t tmpmask;
328 struct mm_struct *mm = current->mm;
329 smp_call_func_t ipi_func = ipi_mb;
330
331 if (flags == MEMBARRIER_FLAG_SYNC_CORE) {
332 if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE))
333 return -EINVAL;
334 if (!(atomic_read(&mm->membarrier_state) &
335 MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY))
336 return -EPERM;
337 ipi_func = ipi_sync_core;
338 prepare_sync_core_cmd(mm);
339 } else if (flags == MEMBARRIER_FLAG_RSEQ) {
340 if (!IS_ENABLED(CONFIG_RSEQ))
341 return -EINVAL;
342 if (!(atomic_read(&mm->membarrier_state) &
343 MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY))
344 return -EPERM;
345 ipi_func = ipi_rseq;
346 } else {
347 WARN_ON_ONCE(flags);
348 if (!(atomic_read(&mm->membarrier_state) &
349 MEMBARRIER_STATE_PRIVATE_EXPEDITED_READY))
350 return -EPERM;
351 }
352
353 if (flags != MEMBARRIER_FLAG_SYNC_CORE &&
354 (atomic_read(&mm->mm_users) == 1 || num_online_cpus() == 1))
355 return 0;
356
357 /*
358 * Matches memory barriers after rq->curr modification in
359 * scheduler.
360 *
361 * On RISC-V, this barrier pairing is also needed for the
362 * SYNC_CORE command when switching between processes, cf.
363 * the inline comments in membarrier_arch_switch_mm().
364 */
365 smp_mb(); /* system call entry is not a mb. */
366
367 if (cpu_id < 0 && !zalloc_cpumask_var(&tmpmask, GFP_KERNEL))
368 return -ENOMEM;
369
370 SERIALIZE_IPI();
371 cpus_read_lock();
372
373 if (cpu_id >= 0) {
374 struct task_struct *p;
375
376 if (cpu_id >= nr_cpu_ids || !cpu_online(cpu_id))
377 goto out;
378 rcu_read_lock();
379 p = rcu_dereference(cpu_rq(cpu_id)->curr);
380 if (!p || p->mm != mm) {
381 rcu_read_unlock();
382 goto out;
383 }
384 rcu_read_unlock();
385 } else {
386 int cpu;
387
388 rcu_read_lock();
389 for_each_online_cpu(cpu) {
390 struct task_struct *p;
391
392 p = rcu_dereference(cpu_rq(cpu)->curr);
393 if (p && p->mm == mm)
394 __cpumask_set_cpu(cpu, tmpmask);
395 }
396 rcu_read_unlock();
397 }
398
399 if (cpu_id >= 0) {
400 /*
401 * smp_call_function_single() will call ipi_func() if cpu_id
402 * is the calling CPU.
403 */
404 smp_call_function_single(cpu_id, ipi_func, NULL, 1);
405 } else {
406 /*
407 * For regular membarrier, we can save a few cycles by
408 * skipping the current cpu -- we're about to do smp_mb()
409 * below, and if we migrate to a different cpu, this cpu
410 * and the new cpu will execute a full barrier in the
411 * scheduler.
412 *
413 * For SYNC_CORE, we do need a barrier on the current cpu --
414 * otherwise, if we are migrated and replaced by a different
415 * task in the same mm just before, during, or after
416 * membarrier, we will end up with some thread in the mm
417 * running without a core sync.
418 *
419 * For RSEQ, don't invoke rseq_sched_switch_event() on the
420 * caller. User code is not supposed to issue syscalls at
421 * all from inside an rseq critical section.
422 */
423 if (flags != MEMBARRIER_FLAG_SYNC_CORE) {
424 preempt_disable();
425 smp_call_function_many(tmpmask, ipi_func, NULL, true);
426 preempt_enable();
427 } else {
428 on_each_cpu_mask(tmpmask, ipi_func, NULL, true);
429 }
430 }
431
432 out:
433 if (cpu_id < 0)
434 free_cpumask_var(tmpmask);
435 cpus_read_unlock();
436
437 /*
438 * Memory barrier on the caller thread _after_ we finished
439 * waiting for the last IPI. Matches memory barriers before
440 * rq->curr modification in scheduler.
441 */
442 smp_mb(); /* exit from system call is not a mb */
443
444 return 0;
445 }
446
sync_runqueues_membarrier_state(struct mm_struct * mm)447 static int sync_runqueues_membarrier_state(struct mm_struct *mm)
448 {
449 int membarrier_state = atomic_read(&mm->membarrier_state);
450 cpumask_var_t tmpmask;
451 int cpu;
452
453 if (atomic_read(&mm->mm_users) == 1 || num_online_cpus() == 1) {
454 this_cpu_write(runqueues.membarrier_state, membarrier_state);
455
456 /*
457 * For single mm user, we can simply issue a memory barrier
458 * after setting MEMBARRIER_STATE_GLOBAL_EXPEDITED in the
459 * mm and in the current runqueue to guarantee that no memory
460 * access following registration is reordered before
461 * registration.
462 */
463 smp_mb();
464 return 0;
465 }
466
467 if (!zalloc_cpumask_var(&tmpmask, GFP_KERNEL))
468 return -ENOMEM;
469
470 /*
471 * For mm with multiple users, we need to ensure all future
472 * scheduler executions will observe @mm's new membarrier
473 * state.
474 */
475 synchronize_rcu();
476
477 /*
478 * For each cpu runqueue, if the task's mm match @mm, ensure that all
479 * @mm's membarrier state set bits are also set in the runqueue's
480 * membarrier state. This ensures that a runqueue scheduling
481 * between threads which are users of @mm has its membarrier state
482 * updated.
483 */
484 SERIALIZE_IPI();
485 cpus_read_lock();
486 rcu_read_lock();
487 for_each_online_cpu(cpu) {
488 struct rq *rq = cpu_rq(cpu);
489 struct task_struct *p;
490
491 p = rcu_dereference(rq->curr);
492 if (p && p->mm == mm)
493 __cpumask_set_cpu(cpu, tmpmask);
494 }
495 rcu_read_unlock();
496
497 on_each_cpu_mask(tmpmask, ipi_sync_rq_state, mm, true);
498
499 free_cpumask_var(tmpmask);
500 cpus_read_unlock();
501
502 return 0;
503 }
504
membarrier_register_global_expedited(void)505 static int membarrier_register_global_expedited(void)
506 {
507 struct task_struct *p = current;
508 struct mm_struct *mm = p->mm;
509 int ret;
510
511 if (atomic_read(&mm->membarrier_state) &
512 MEMBARRIER_STATE_GLOBAL_EXPEDITED_READY)
513 return 0;
514 atomic_or(MEMBARRIER_STATE_GLOBAL_EXPEDITED, &mm->membarrier_state);
515 ret = sync_runqueues_membarrier_state(mm);
516 if (ret)
517 return ret;
518 atomic_or(MEMBARRIER_STATE_GLOBAL_EXPEDITED_READY,
519 &mm->membarrier_state);
520
521 return 0;
522 }
523
membarrier_register_private_expedited(int flags)524 static int membarrier_register_private_expedited(int flags)
525 {
526 struct task_struct *p = current;
527 struct mm_struct *mm = p->mm;
528 int ready_state = MEMBARRIER_STATE_PRIVATE_EXPEDITED_READY,
529 set_state = MEMBARRIER_STATE_PRIVATE_EXPEDITED,
530 ret;
531
532 if (flags == MEMBARRIER_FLAG_SYNC_CORE) {
533 if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE))
534 return -EINVAL;
535 ready_state =
536 MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY;
537 } else if (flags == MEMBARRIER_FLAG_RSEQ) {
538 if (!IS_ENABLED(CONFIG_RSEQ))
539 return -EINVAL;
540 ready_state =
541 MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY;
542 } else {
543 WARN_ON_ONCE(flags);
544 }
545
546 /*
547 * We need to consider threads belonging to different thread
548 * groups, which use the same mm. (CLONE_VM but not
549 * CLONE_THREAD).
550 */
551 if ((atomic_read(&mm->membarrier_state) & ready_state) == ready_state)
552 return 0;
553 if (flags & MEMBARRIER_FLAG_SYNC_CORE)
554 set_state |= MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE;
555 if (flags & MEMBARRIER_FLAG_RSEQ)
556 set_state |= MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ;
557 atomic_or(set_state, &mm->membarrier_state);
558 ret = sync_runqueues_membarrier_state(mm);
559 if (ret)
560 return ret;
561 atomic_or(ready_state, &mm->membarrier_state);
562
563 return 0;
564 }
565
membarrier_get_registrations(void)566 static int membarrier_get_registrations(void)
567 {
568 struct task_struct *p = current;
569 struct mm_struct *mm = p->mm;
570 int registrations_mask = 0, membarrier_state, i;
571 static const int states[] = {
572 MEMBARRIER_STATE_GLOBAL_EXPEDITED |
573 MEMBARRIER_STATE_GLOBAL_EXPEDITED_READY,
574 MEMBARRIER_STATE_PRIVATE_EXPEDITED |
575 MEMBARRIER_STATE_PRIVATE_EXPEDITED_READY,
576 MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE |
577 MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY,
578 MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ |
579 MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY
580 };
581 static const int registration_cmds[] = {
582 MEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED,
583 MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED,
584 MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE,
585 MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ
586 };
587 BUILD_BUG_ON(ARRAY_SIZE(states) != ARRAY_SIZE(registration_cmds));
588
589 membarrier_state = atomic_read(&mm->membarrier_state);
590 for (i = 0; i < ARRAY_SIZE(states); ++i) {
591 if (membarrier_state & states[i]) {
592 registrations_mask |= registration_cmds[i];
593 membarrier_state &= ~states[i];
594 }
595 }
596 WARN_ON_ONCE(membarrier_state != 0);
597 return registrations_mask;
598 }
599
600 /**
601 * sys_membarrier - issue memory barriers on a set of threads
602 * @cmd: Takes command values defined in enum membarrier_cmd.
603 * @flags: Currently needs to be 0 for all commands other than
604 * MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ: in the latter
605 * case it can be MEMBARRIER_CMD_FLAG_CPU, indicating that @cpu_id
606 * contains the CPU on which to interrupt (= restart)
607 * the RSEQ critical section.
608 * @cpu_id: if @flags == MEMBARRIER_CMD_FLAG_CPU, indicates the cpu on which
609 * RSEQ CS should be interrupted (@cmd must be
610 * MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ).
611 *
612 * If this system call is not implemented, -ENOSYS is returned. If the
613 * command specified does not exist, not available on the running
614 * kernel, or if the command argument is invalid, this system call
615 * returns -EINVAL. For a given command, with flags argument set to 0,
616 * if this system call returns -ENOSYS or -EINVAL, it is guaranteed to
617 * always return the same value until reboot. In addition, it can return
618 * -ENOMEM if there is not enough memory available to perform the system
619 * call.
620 *
621 * All memory accesses performed in program order from each targeted thread
622 * is guaranteed to be ordered with respect to sys_membarrier(). If we use
623 * the semantic "barrier()" to represent a compiler barrier forcing memory
624 * accesses to be performed in program order across the barrier, and
625 * smp_mb() to represent explicit memory barriers forcing full memory
626 * ordering across the barrier, we have the following ordering table for
627 * each pair of barrier(), sys_membarrier() and smp_mb():
628 *
629 * The pair ordering is detailed as (O: ordered, X: not ordered):
630 *
631 * barrier() smp_mb() sys_membarrier()
632 * barrier() X X O
633 * smp_mb() X O O
634 * sys_membarrier() O O O
635 */
SYSCALL_DEFINE3(membarrier,int,cmd,unsigned int,flags,int,cpu_id)636 SYSCALL_DEFINE3(membarrier, int, cmd, unsigned int, flags, int, cpu_id)
637 {
638 switch (cmd) {
639 case MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ:
640 if (unlikely(flags && flags != MEMBARRIER_CMD_FLAG_CPU))
641 return -EINVAL;
642 break;
643 default:
644 if (unlikely(flags))
645 return -EINVAL;
646 }
647
648 if (!(flags & MEMBARRIER_CMD_FLAG_CPU))
649 cpu_id = -1;
650
651 switch (cmd) {
652 case MEMBARRIER_CMD_QUERY:
653 {
654 int cmd_mask = MEMBARRIER_CMD_BITMASK;
655
656 if (tick_nohz_full_enabled())
657 cmd_mask &= ~MEMBARRIER_CMD_GLOBAL;
658 return cmd_mask;
659 }
660 case MEMBARRIER_CMD_GLOBAL:
661 /* MEMBARRIER_CMD_GLOBAL is not compatible with nohz_full. */
662 if (tick_nohz_full_enabled())
663 return -EINVAL;
664 if (num_online_cpus() > 1)
665 synchronize_rcu();
666 return 0;
667 case MEMBARRIER_CMD_GLOBAL_EXPEDITED:
668 return membarrier_global_expedited();
669 case MEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED:
670 return membarrier_register_global_expedited();
671 case MEMBARRIER_CMD_PRIVATE_EXPEDITED:
672 return membarrier_private_expedited(0, cpu_id);
673 case MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED:
674 return membarrier_register_private_expedited(0);
675 case MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE:
676 return membarrier_private_expedited(MEMBARRIER_FLAG_SYNC_CORE, cpu_id);
677 case MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE:
678 return membarrier_register_private_expedited(MEMBARRIER_FLAG_SYNC_CORE);
679 case MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ:
680 return membarrier_private_expedited(MEMBARRIER_FLAG_RSEQ, cpu_id);
681 case MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ:
682 return membarrier_register_private_expedited(MEMBARRIER_FLAG_RSEQ);
683 case MEMBARRIER_CMD_GET_REGISTRATIONS:
684 return membarrier_get_registrations();
685 default:
686 return -EINVAL;
687 }
688 }
689