1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2023 Realtek Corporation
3 */
4
5 #include <linux/pci.h>
6
7 #include "mac.h"
8 #include "pci.h"
9 #include "reg.h"
10
11 enum pcie_rxbd_mode {
12 PCIE_RXBD_NORM = 0,
13 PCIE_RXBD_SEP,
14 PCIE_RXBD_EXT,
15 };
16
17 #define PL0_TMR_SCALE_ASIC 1
18 #define PL0_TMR_ANA_172US 0x800
19 #define PL0_TMR_MAC_1MS 0x27100
20 #define PL0_TMR_AUX_1MS 0x1E848
21
rtw89_pci_aspm_set_be(struct rtw89_dev * rtwdev,bool enable)22 static void rtw89_pci_aspm_set_be(struct rtw89_dev *rtwdev, bool enable)
23 {
24 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
25 struct pci_dev *pdev = rtwpci->pdev;
26 u8 value = 0;
27 int ret;
28
29 ret = pci_read_config_byte(pdev, RTW89_PCIE_ASPM_CTRL, &value);
30 if (ret)
31 rtw89_warn(rtwdev, "failed to read ASPM Delay\n");
32
33 u8p_replace_bits(&value, PCIE_L1DLY_16US, RTW89_L1DLY_MASK);
34
35 ret = pci_write_config_byte(pdev, RTW89_PCIE_ASPM_CTRL, value);
36 if (ret)
37 rtw89_warn(rtwdev, "failed to write ASPM Delay\n");
38
39 if (enable)
40 rtw89_write32_set(rtwdev, R_AX_PCIE_MIX_CFG_V1,
41 B_BE_ASPM_CTRL_L1);
42 else
43 rtw89_write32_clr(rtwdev, R_AX_PCIE_MIX_CFG_V1,
44 B_BE_ASPM_CTRL_L1);
45 }
46
rtw89_pci_l1ss_set_be(struct rtw89_dev * rtwdev,bool enable)47 static void rtw89_pci_l1ss_set_be(struct rtw89_dev *rtwdev, bool enable)
48 {
49 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
50 struct rtw89_hal *hal = &rtwdev->hal;
51
52 if (enable && chip_id == RTL8922D && hal->cid == RTL8922D_CID7090)
53 rtw89_write32_set(rtwdev, R_BE_PCIE_PS_CTRL,
54 B_BE_ASPM_L11_EN | B_BE_ASPM_L12_EN |
55 B_BE_PCIPM_L11_EN | B_BE_PCIPM_L12_EN);
56
57 if (enable)
58 rtw89_write32_set(rtwdev, R_BE_PCIE_MIX_CFG,
59 B_BE_L1SUB_ENABLE);
60 else
61 rtw89_write32_clr(rtwdev, R_BE_PCIE_MIX_CFG,
62 B_BE_L1SUB_ENABLE);
63 }
64
rtw89_pci_clkreq_set_be(struct rtw89_dev * rtwdev,bool enable)65 static void rtw89_pci_clkreq_set_be(struct rtw89_dev *rtwdev, bool enable)
66 {
67 rtw89_write32_mask(rtwdev, R_BE_PCIE_LAT_CTRL, B_BE_CLK_REQ_LAT_MASK,
68 PCIE_CLKDLY_HW_V1_0);
69
70 if (enable)
71 rtw89_write32_set(rtwdev, R_BE_L1_CLK_CTRL,
72 B_BE_CLK_PM_EN);
73 else
74 rtw89_write32_clr(rtwdev, R_AX_L1_CLK_CTRL,
75 B_BE_CLK_PM_EN);
76 }
77
_patch_pcie_power_wake_be(struct rtw89_dev * rtwdev,bool power_up)78 static void _patch_pcie_power_wake_be(struct rtw89_dev *rtwdev, bool power_up)
79 {
80 if (power_up)
81 rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, BIT_WAKE_CTRL_V1);
82 else
83 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, BIT_WAKE_CTRL_V1);
84 }
85
_patch_pre_init_be(struct rtw89_dev * rtwdev)86 static void _patch_pre_init_be(struct rtw89_dev *rtwdev)
87 {
88 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
89 struct rtw89_hal *hal = &rtwdev->hal;
90 struct pci_dev *pdev = rtwpci->pdev;
91
92 if (rtwdev->chip->chip_id != RTL8922D)
93 return;
94
95 if (hal->cid != RTL8922D_CID7090)
96 goto set_ts1;
97
98 rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G2 +
99 RAC_ANA14 * RAC_MULT, EIEOS_L1SS_WAIT_CLKRDY);
100
101 set_ts1:
102 pci_clear_and_set_config_dword(pdev, RTW89_PCIE_L1_STS_V1,
103 0, RTW89_PCIE_EXTENDED_SYNCH);
104 }
105
rtw89_pci_set_io_rcy_be(struct rtw89_dev * rtwdev)106 static void rtw89_pci_set_io_rcy_be(struct rtw89_dev *rtwdev)
107 {
108 const struct rtw89_pci_info *info = rtwdev->pci_info;
109 u32 scale = PL0_TMR_SCALE_ASIC;
110 u32 val32;
111
112 if (info->io_rcy_en == MAC_AX_PCIE_ENABLE) {
113 val32 = info->io_rcy_tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ?
114 PL0_TMR_ANA_172US : info->io_rcy_tmr;
115 val32 /= scale;
116
117 rtw89_write32(rtwdev, R_BE_AON_WDT_TMR, val32);
118 rtw89_write32(rtwdev, R_BE_MDIO_WDT_TMR, val32);
119 rtw89_write32(rtwdev, R_BE_LA_MODE_WDT_TMR, val32);
120 rtw89_write32(rtwdev, R_BE_WDT_AR_TMR, val32);
121 rtw89_write32(rtwdev, R_BE_WDT_AW_TMR, val32);
122 rtw89_write32(rtwdev, R_BE_WDT_W_TMR, val32);
123 rtw89_write32(rtwdev, R_BE_WDT_B_TMR, val32);
124 rtw89_write32(rtwdev, R_BE_WDT_R_TMR, val32);
125
126 val32 = info->io_rcy_tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ?
127 PL0_TMR_MAC_1MS : info->io_rcy_tmr;
128 val32 /= scale;
129 rtw89_write32(rtwdev, R_BE_WLAN_WDT_TMR, val32);
130 rtw89_write32(rtwdev, R_BE_AXIDMA_WDT_TMR, val32);
131
132 val32 = info->io_rcy_tmr == MAC_AX_IO_RCY_ANA_TMR_DEF ?
133 PL0_TMR_AUX_1MS : info->io_rcy_tmr;
134 val32 /= scale;
135 rtw89_write32(rtwdev, R_BE_LOCAL_WDT_TMR, val32);
136 } else {
137 rtw89_write32_clr(rtwdev, R_BE_WLAN_WDT, B_BE_WLAN_WDT_ENABLE);
138 rtw89_write32_clr(rtwdev, R_BE_AXIDMA_WDT, B_BE_AXIDMA_WDT_ENABLE);
139 rtw89_write32_clr(rtwdev, R_BE_AON_WDT, B_BE_AON_WDT_ENABLE);
140 rtw89_write32_clr(rtwdev, R_BE_LOCAL_WDT, B_BE_LOCAL_WDT_ENABLE);
141 rtw89_write32_clr(rtwdev, R_BE_MDIO_WDT, B_BE_MDIO_WDT_ENABLE);
142 rtw89_write32_clr(rtwdev, R_BE_LA_MODE_WDT, B_BE_LA_MODE_WDT_ENABLE);
143 rtw89_write32_clr(rtwdev, R_BE_WDT_AR, B_BE_WDT_AR_ENABLE);
144 rtw89_write32_clr(rtwdev, R_BE_WDT_AW, B_BE_WDT_AW_ENABLE);
145 rtw89_write32_clr(rtwdev, R_BE_WDT_W, B_BE_WDT_W_ENABLE);
146 rtw89_write32_clr(rtwdev, R_BE_WDT_B, B_BE_WDT_B_ENABLE);
147 rtw89_write32_clr(rtwdev, R_BE_WDT_R, B_BE_WDT_R_ENABLE);
148 }
149 }
150
rtw89_pci_ctrl_wpdma_pcie_be(struct rtw89_dev * rtwdev,bool en)151 static void rtw89_pci_ctrl_wpdma_pcie_be(struct rtw89_dev *rtwdev, bool en)
152 {
153 if (en)
154 rtw89_write32_clr(rtwdev, R_BE_HAXI_DMA_STOP1, B_BE_STOP_WPDMA);
155 else
156 rtw89_write32_set(rtwdev, R_BE_HAXI_DMA_STOP1, B_BE_STOP_WPDMA);
157 }
158
rtw89_pci_ctrl_trxdma_pcie_be(struct rtw89_dev * rtwdev,enum mac_ax_pcie_func_ctrl tx_en,enum mac_ax_pcie_func_ctrl rx_en,enum mac_ax_pcie_func_ctrl io_en)159 static void rtw89_pci_ctrl_trxdma_pcie_be(struct rtw89_dev *rtwdev,
160 enum mac_ax_pcie_func_ctrl tx_en,
161 enum mac_ax_pcie_func_ctrl rx_en,
162 enum mac_ax_pcie_func_ctrl io_en)
163 {
164 u32 val;
165
166 val = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1);
167
168 if (tx_en == MAC_AX_PCIE_ENABLE)
169 val |= B_BE_TXDMA_EN;
170 else if (tx_en == MAC_AX_PCIE_DISABLE)
171 val &= ~B_BE_TXDMA_EN;
172
173 if (rx_en == MAC_AX_PCIE_ENABLE)
174 val |= B_BE_RXDMA_EN;
175 else if (rx_en == MAC_AX_PCIE_DISABLE)
176 val &= ~B_BE_RXDMA_EN;
177
178 if (io_en == MAC_AX_PCIE_ENABLE)
179 val &= ~B_BE_STOP_AXI_MST;
180 else if (io_en == MAC_AX_PCIE_DISABLE)
181 val |= B_BE_STOP_AXI_MST;
182
183 rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val);
184
185 if (io_en == MAC_AX_PCIE_ENABLE && rtwdev->chip->chip_id == RTL8922A)
186 rtw89_write32_mask(rtwdev, R_BE_HAXI_MST_WDT_TIMEOUT_SEL_V1,
187 B_BE_HAXI_MST_WDT_TIMEOUT_SEL_MASK, 4);
188 }
189
rtw89_pci_clr_idx_all_be(struct rtw89_dev * rtwdev)190 static void rtw89_pci_clr_idx_all_be(struct rtw89_dev *rtwdev)
191 {
192 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
193 const struct rtw89_chip_info *chip = rtwdev->chip;
194 struct rtw89_pci_rx_ring *rx_ring;
195 u32 val;
196
197 if (chip->chip_id == RTL8922A)
198 val = B_BE_CLR_ALL_IDX_MASK;
199 else
200 val = B_BE_CLR_ALL_IDX_MASK_V1;
201
202 rtw89_write32(rtwdev, R_BE_TXBD_RWPTR_CLR1, val);
203
204 rtw89_write32(rtwdev, R_BE_RXBD_RWPTR_CLR1_V1,
205 B_BE_CLR_RXQ0_IDX | B_BE_CLR_RPQ0_IDX);
206
207 rx_ring = &rtwpci->rx.rings[RTW89_RXCH_RXQ];
208 rtw89_write16(rtwdev, R_BE_RXQ0_RXBD_IDX_V1, rx_ring->bd_ring.len - 1);
209
210 rx_ring = &rtwpci->rx.rings[RTW89_RXCH_RPQ];
211 rtw89_write16(rtwdev, R_BE_RPQ0_RXBD_IDX_V1, rx_ring->bd_ring.len - 1);
212 }
213
rtw89_pci_poll_txdma_ch_idle_be(struct rtw89_dev * rtwdev)214 static int rtw89_pci_poll_txdma_ch_idle_be(struct rtw89_dev *rtwdev)
215 {
216 const struct rtw89_pci_info *info = rtwdev->pci_info;
217 u32 dma_busy1 = info->dma_busy1.addr;
218 u32 check = info->dma_busy1.mask;
219 u32 val;
220
221 return read_poll_timeout(rtw89_read32, val, (val & check) == 0,
222 10, 1000, false, rtwdev, dma_busy1);
223 }
224
rtw89_pci_poll_rxdma_ch_idle_be(struct rtw89_dev * rtwdev)225 static int rtw89_pci_poll_rxdma_ch_idle_be(struct rtw89_dev *rtwdev)
226 {
227 u32 check;
228 u32 val;
229
230 check = B_BE_RXQ0_BUSY_V1 | B_BE_RPQ0_BUSY_V1;
231
232 return read_poll_timeout(rtw89_read32, val, (val & check) == 0,
233 10, 1000, false, rtwdev, R_BE_HAXI_DMA_BUSY1);
234 }
235
rtw89_pci_poll_dma_all_idle_be(struct rtw89_dev * rtwdev)236 static int rtw89_pci_poll_dma_all_idle_be(struct rtw89_dev *rtwdev)
237 {
238 int ret;
239
240 ret = rtw89_pci_poll_txdma_ch_idle_be(rtwdev);
241 if (ret) {
242 rtw89_err(rtwdev, "txdma ch busy\n");
243 return ret;
244 }
245
246 ret = rtw89_pci_poll_rxdma_ch_idle_be(rtwdev);
247 if (ret) {
248 rtw89_err(rtwdev, "rxdma ch busy\n");
249 return ret;
250 }
251
252 return 0;
253 }
254
rtw89_pci_mode_op_be(struct rtw89_dev * rtwdev)255 static void rtw89_pci_mode_op_be(struct rtw89_dev *rtwdev)
256 {
257 const struct rtw89_pci_info *info = rtwdev->pci_info;
258 const struct rtw89_chip_info *chip = rtwdev->chip;
259 u32 val32_init1, val32_rxapp, val32_exp;
260
261 val32_init1 = rtw89_read32(rtwdev, R_BE_HAXI_INIT_CFG1);
262 if (chip->chip_id == RTL8922A)
263 val32_rxapp = rtw89_read32(rtwdev, R_BE_RX_APPEND_MODE);
264 val32_exp = rtw89_read32(rtwdev, R_BE_HAXI_EXP_CTRL_V1);
265
266 if (chip->chip_id == RTL8922A) {
267 if (info->rxbd_mode == MAC_AX_RXBD_PKT) {
268 val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_NORM,
269 B_BE_RXQ_RXBD_MODE_MASK);
270 } else if (info->rxbd_mode == MAC_AX_RXBD_SEP) {
271 val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_SEP,
272 B_BE_RXQ_RXBD_MODE_MASK);
273 val32_rxapp = u32_replace_bits(val32_rxapp, 0,
274 B_BE_APPEND_LEN_MASK);
275 }
276 }
277
278 val32_init1 = u32_replace_bits(val32_init1, info->tx_burst,
279 B_BE_MAX_TXDMA_MASK);
280 val32_init1 = u32_replace_bits(val32_init1, info->rx_burst,
281 B_BE_MAX_RXDMA_MASK);
282 val32_exp = u32_replace_bits(val32_exp, info->multi_tag_num,
283 B_BE_MAX_TAG_NUM_MASK);
284 val32_init1 = u32_replace_bits(val32_init1, info->wd_dma_idle_intvl,
285 B_BE_CFG_WD_PERIOD_IDLE_MASK);
286 val32_init1 = u32_replace_bits(val32_init1, info->wd_dma_act_intvl,
287 B_BE_CFG_WD_PERIOD_ACTIVE_MASK);
288
289 rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val32_init1);
290 if (chip->chip_id == RTL8922A)
291 rtw89_write32(rtwdev, R_BE_RX_APPEND_MODE, val32_rxapp);
292 rtw89_write32(rtwdev, R_BE_HAXI_EXP_CTRL_V1, val32_exp);
293 }
294
rtw89_pci_rst_bdram_be(struct rtw89_dev * rtwdev)295 static int rtw89_pci_rst_bdram_be(struct rtw89_dev *rtwdev)
296 {
297 u32 val;
298
299 rtw89_write32_set(rtwdev, R_BE_HAXI_INIT_CFG1, B_BE_SET_BDRAM_BOUND);
300
301 return read_poll_timeout(rtw89_read32, val, !(val & B_BE_SET_BDRAM_BOUND),
302 50, 500000, false, rtwdev, R_BE_HAXI_INIT_CFG1);
303 }
304
rtw89_pci_debounce_be(struct rtw89_dev * rtwdev)305 static void rtw89_pci_debounce_be(struct rtw89_dev *rtwdev)
306 {
307 u32 val32;
308
309 val32 = rtw89_read32(rtwdev, R_BE_SYS_PAGE_CLK_GATED);
310 val32 = u32_replace_bits(val32, 0, B_BE_PCIE_PRST_DEBUNC_PERIOD_MASK);
311 val32 |= B_BE_SYM_PRST_DEBUNC_SEL;
312 rtw89_write32(rtwdev, R_BE_SYS_PAGE_CLK_GATED, val32);
313 }
314
rtw89_pci_ldo_low_pwr_be(struct rtw89_dev * rtwdev)315 static void rtw89_pci_ldo_low_pwr_be(struct rtw89_dev *rtwdev)
316 {
317 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
318 struct rtw89_hal *hal = &rtwdev->hal;
319 u32 clr;
320
321 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_PSUS_OFF_CAPC_EN);
322 rtw89_write32_set(rtwdev, R_BE_SYS_PAGE_CLK_GATED,
323 B_BE_SOP_OFFPOOBS_PC | B_BE_CPHY_AUXCLK_OP |
324 B_BE_CPHY_POWER_READY_CHK);
325 rtw89_write32_clr(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_PCIE_FORCE_IBX_EN |
326 B_BE_PCIE_DIS_L2_RTK_PERST |
327 B_BE_PCIE_DIS_L2__CTRL_LDO_HCI);
328
329 if (chip_id == RTL8922D && hal->cid == RTL8922D_CID7090)
330 clr = B_BE_PCIE_DIS_L1_2_CTRL_HCILDO |
331 B_BE_PCIE_DIS_L1_2_CTRL_APHY_SUSB |
332 B_BE_PCIE_DIS_RTK_PRST_N_L1_2 |
333 B_BE_PCIE_DIS_L2_CTRL_APHY_SUSB;
334 else
335 clr = B_BE_PCIE_DIS_L1_2_CTRL_HCILDO;
336
337 rtw89_write32_clr(rtwdev, R_BE_L1_2_CTRL_HCILDO, clr);
338 }
339
rtw89_pci_pcie_setting_be(struct rtw89_dev * rtwdev)340 static void rtw89_pci_pcie_setting_be(struct rtw89_dev *rtwdev)
341 {
342 const struct rtw89_chip_info *chip = rtwdev->chip;
343 struct rtw89_hal *hal = &rtwdev->hal;
344
345 rtw89_write32_set(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_EN_AUX_CLK);
346 rtw89_write32_clr(rtwdev, R_BE_PCIE_PS_CTRL, B_BE_CMAC_EXIT_L1_EN);
347
348 if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV)
349 return;
350
351 rtw89_write32_set(rtwdev, R_BE_EFUSE_CTRL_2_V1, B_BE_R_SYM_AUTOLOAD_WITH_PMC_SEL);
352 rtw89_write32_set(rtwdev, R_BE_PCIE_LAT_CTRL, B_BE_SYM_AUX_CLK_SEL);
353
354 if (chip->chip_id != RTL8922D)
355 return;
356
357 rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_R_SYM_PRST_CPHY_RST);
358 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_USUS_OFFCAPC_EN);
359 rtw89_write32(rtwdev, R_BE_PCIE_HCI2FW_ISR, 0xFFFFFFFF);
360 }
361
rtw89_pci_ser_setting_be(struct rtw89_dev * rtwdev)362 static void rtw89_pci_ser_setting_be(struct rtw89_dev *rtwdev)
363 {
364 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
365 struct rtw89_hal *hal = &rtwdev->hal;
366 u32 val32;
367 int ret;
368
369 if (chip_id == RTL8922D)
370 goto be2_chips;
371 else if (chip_id != RTL8922A)
372 return;
373
374 rtw89_write32(rtwdev, R_BE_PL1_DBG_INFO, 0x0);
375
376 switch (hal->cv) {
377 case CHIP_CAV:
378 case CHIP_CBV:
379 rtw89_write32_clr(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
380 rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL,
381 B_BE_PL1_TIMER_UNIT_MASK, PCIE_SER_TIMER_UNIT);
382
383 val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK);
384 val32 &= ~(B_BE_SER_PMU_IMR | B_BE_SER_L1SUB_IMR |
385 B_BE_SER_PM_MASTER_IMR | B_BE_SER_LTSSM_IMR |
386 B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK);
387 rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
388 break;
389 case CHIP_CCV:
390 default:
391 rtw89_write32_clr(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
392
393 ret = read_poll_timeout_atomic(rtw89_read32, val32, !val32,
394 1, 1000, false, rtwdev, R_BE_REG_PL1_ISR);
395 if (ret)
396 rtw89_warn(rtwdev, "[ERR] PCIE SER clear poll fail\n");
397
398 rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL,
399 B_BE_PL1_TIMER_UNIT_MASK, PCIE_SER_TIMER_UNIT);
400 rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
401
402 val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK);
403 val32 |= (B_BE_SER_PMU_IMR | B_BE_SER_PM_MASTER_IMR |
404 B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK |
405 B_BE_SER_PCLKREQ_ACK_MASK);
406 val32 &= ~B_BE_SER_L1SUB_IMR;
407 rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
408 break;
409 }
410
411 return;
412
413 be2_chips:
414 rtw89_write32_clr(rtwdev, R_BE_PCIE_SER_DBG, B_BE_PCIE_SER_FLUSH_RSTB);
415 rtw89_write32_set(rtwdev, R_BE_PCIE_SER_DBG, B_BE_PCIE_SER_FLUSH_RSTB);
416
417 rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
418 RAC_ANA40 * RAC_MULT, PHY_ERR_IMR_DIS);
419 rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
420 RAC_ANA40 * RAC_MULT, PHY_ERR_IMR_DIS);
421
422 rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
423 RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
424 rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
425 RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
426 rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
427 RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
428 rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
429 RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
430
431 val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
432 val32 &= ~B_BE_PL1_SER_PL1_EN;
433 rtw89_write32(rtwdev, R_BE_SER_PL1_CTRL, val32);
434 rtw89_write32(rtwdev, R_BE_REG_PL1_ISR, B_PCIE_SER_ALL_ISR);
435
436 ret = read_poll_timeout_atomic(rtw89_read32, val32, !val32,
437 1, 1000, false, rtwdev, R_BE_REG_PL1_ISR);
438 if (ret)
439 rtw89_warn(rtwdev, "[ERR] PCIE SER clear poll fail\n");
440
441 val32 = rtw89_read32(rtwdev, R_BE_REG_PL1_MASK);
442 val32 |= B_BE_SER_PMU_IMR | B_BE_SER_PM_MASTER_IMR |
443 B_BE_SER_LTSSM_IMR | B_BE_SER_PM_CLK_MASK | B_BE_SER_PCLKREQ_ACK_MASK |
444 B_BE_SER_LTSSM_UNSTABLE_MASK;
445 val32 &= ~B_BE_SER_L1SUB_IMR;
446 rtw89_write32(rtwdev, R_BE_REG_PL1_MASK, val32);
447
448 rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_TIMER_UNIT_MASK,
449 PCIE_SER_TIMER_UNIT);
450 rtw89_write32_set(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
451
452 if (hal->cid == RTL8922D_CID7090)
453 rtw89_write32_set(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_SER_DETECT_EN);
454 }
455
rtw89_pci_ctrl_txdma_ch_be(struct rtw89_dev * rtwdev,bool enable)456 static void rtw89_pci_ctrl_txdma_ch_be(struct rtw89_dev *rtwdev, bool enable)
457 {
458 const struct rtw89_pci_info *info = rtwdev->pci_info;
459 u32 mask_all;
460 u32 val;
461
462 mask_all = B_BE_STOP_CH0 | B_BE_STOP_CH1 | B_BE_STOP_CH2 |
463 B_BE_STOP_CH3 | B_BE_STOP_CH4 | B_BE_STOP_CH5 |
464 B_BE_STOP_CH6 | B_BE_STOP_CH7 | B_BE_STOP_CH8 |
465 B_BE_STOP_CH9 | B_BE_STOP_CH10 | B_BE_STOP_CH11;
466
467 /* mask out unsupported channels for certains chips */
468 mask_all &= info->dma_stop1.mask;
469
470 val = rtw89_read32(rtwdev, R_BE_HAXI_DMA_STOP1);
471 val |= B_BE_STOP_CH13 | B_BE_STOP_CH14;
472
473 if (enable)
474 val &= ~mask_all;
475 else
476 val |= mask_all;
477
478 rtw89_write32(rtwdev, R_BE_HAXI_DMA_STOP1, val);
479 }
480
rtw89_pci_ctrl_txdma_fw_ch_be(struct rtw89_dev * rtwdev,bool enable)481 static void rtw89_pci_ctrl_txdma_fw_ch_be(struct rtw89_dev *rtwdev, bool enable)
482 {
483 u32 val = rtw89_read32(rtwdev, R_BE_HAXI_DMA_STOP1);
484
485 if (enable)
486 val &= ~B_BE_STOP_CH12;
487 else
488 val |= B_BE_STOP_CH12;
489
490 rtw89_write32(rtwdev, R_BE_HAXI_DMA_STOP1, val);
491 }
492
rtw89_pci_ops_mac_pre_init_be(struct rtw89_dev * rtwdev)493 static int rtw89_pci_ops_mac_pre_init_be(struct rtw89_dev *rtwdev)
494 {
495 int ret;
496
497 rtw89_pci_set_io_rcy_be(rtwdev);
498 _patch_pcie_power_wake_be(rtwdev, true);
499 _patch_pre_init_be(rtwdev);
500 rtw89_pci_ctrl_wpdma_pcie_be(rtwdev, false);
501 rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_DISABLE,
502 MAC_AX_PCIE_DISABLE, MAC_AX_PCIE_DISABLE);
503 rtw89_pci_clr_idx_all_be(rtwdev);
504
505 ret = rtw89_pci_poll_dma_all_idle_be(rtwdev);
506 if (ret) {
507 rtw89_err(rtwdev, "[ERR] poll pcie dma all idle\n");
508 return ret;
509 }
510
511 rtw89_pci_mode_op_be(rtwdev);
512 rtw89_pci_ops_reset(rtwdev);
513
514 ret = rtw89_pci_rst_bdram_be(rtwdev);
515 if (ret) {
516 rtw89_err(rtwdev, "[ERR]pcie rst bdram\n");
517 return ret;
518 }
519
520 rtw89_pci_debounce_be(rtwdev);
521 rtw89_pci_ldo_low_pwr_be(rtwdev);
522 rtw89_pci_pcie_setting_be(rtwdev);
523 rtw89_pci_ser_setting_be(rtwdev);
524
525 rtw89_pci_ctrl_txdma_ch_be(rtwdev, false);
526 rtw89_pci_ctrl_txdma_fw_ch_be(rtwdev, true);
527 rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_ENABLE,
528 MAC_AX_PCIE_ENABLE, MAC_AX_PCIE_ENABLE);
529
530 return 0;
531 }
532
rtw89_pci_ops_mac_pre_deinit_be(struct rtw89_dev * rtwdev)533 static int rtw89_pci_ops_mac_pre_deinit_be(struct rtw89_dev *rtwdev)
534 {
535 u32 val;
536
537 _patch_pcie_power_wake_be(rtwdev, false);
538
539 val = rtw89_read32_mask(rtwdev, R_BE_IC_PWR_STATE, B_BE_WLMAC_PWR_STE_MASK);
540 if (val == 0)
541 return 0;
542
543 rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_DISABLE,
544 MAC_AX_PCIE_DISABLE, MAC_AX_PCIE_DISABLE);
545 rtw89_pci_clr_idx_all_be(rtwdev);
546
547 return 0;
548 }
549
rtw89_pci_ltr_set_v2(struct rtw89_dev * rtwdev,bool en)550 int rtw89_pci_ltr_set_v2(struct rtw89_dev *rtwdev, bool en)
551 {
552 u32 ctrl0, cfg0, cfg1, dec_ctrl, idle_ltcy, act_ltcy, dis_ltcy;
553 u32 ltr_idle_lat_ctrl, ltr_act_lat_ctrl;
554
555 ctrl0 = rtw89_read32(rtwdev, R_BE_LTR_CTRL_0);
556 if (rtw89_pci_ltr_is_err_reg_val(ctrl0))
557 return -EINVAL;
558 cfg0 = rtw89_read32(rtwdev, R_BE_LTR_CFG_0);
559 if (rtw89_pci_ltr_is_err_reg_val(cfg0))
560 return -EINVAL;
561 cfg1 = rtw89_read32(rtwdev, R_BE_LTR_CFG_1);
562 if (rtw89_pci_ltr_is_err_reg_val(cfg1))
563 return -EINVAL;
564 dec_ctrl = rtw89_read32(rtwdev, R_BE_LTR_DECISION_CTRL_V1);
565 if (rtw89_pci_ltr_is_err_reg_val(dec_ctrl))
566 return -EINVAL;
567 idle_ltcy = rtw89_read32(rtwdev, R_BE_LTR_LATENCY_IDX3_V1);
568 if (rtw89_pci_ltr_is_err_reg_val(idle_ltcy))
569 return -EINVAL;
570 act_ltcy = rtw89_read32(rtwdev, R_BE_LTR_LATENCY_IDX1_V1);
571 if (rtw89_pci_ltr_is_err_reg_val(act_ltcy))
572 return -EINVAL;
573 dis_ltcy = rtw89_read32(rtwdev, R_BE_LTR_LATENCY_IDX0_V1);
574 if (rtw89_pci_ltr_is_err_reg_val(dis_ltcy))
575 return -EINVAL;
576
577 if (en) {
578 dec_ctrl |= B_BE_ENABLE_LTR_CTL_DECISION | B_BE_LTR_HW_DEC_EN_V1;
579 ctrl0 |= B_BE_LTR_HW_EN;
580 } else {
581 dec_ctrl &= ~(B_BE_ENABLE_LTR_CTL_DECISION | B_BE_LTR_HW_DEC_EN_V1 |
582 B_BE_LTR_EN_PORT_V1_MASK);
583 ctrl0 &= ~B_BE_LTR_HW_EN;
584 }
585
586 dec_ctrl = u32_replace_bits(dec_ctrl, PCI_LTR_SPC_500US,
587 B_BE_LTR_SPACE_IDX_MASK);
588 cfg0 = u32_replace_bits(cfg0, PCI_LTR_IDLE_TIMER_3_2MS,
589 B_BE_LTR_IDLE_TIMER_IDX_MASK);
590 cfg1 = u32_replace_bits(cfg1, 0xC0, B_BE_LTR_CMAC0_RX_USE_PG_TH_MASK);
591 cfg1 = u32_replace_bits(cfg1, 0xC0, B_BE_LTR_CMAC1_RX_USE_PG_TH_MASK);
592 cfg0 = u32_replace_bits(cfg0, 1, B_BE_LTR_IDX_ACTIVE_MASK);
593 cfg0 = u32_replace_bits(cfg0, 3, B_BE_LTR_IDX_IDLE_MASK);
594 dec_ctrl = u32_replace_bits(dec_ctrl, 0, B_BE_LTR_IDX_DISABLE_V1_MASK);
595
596 if (rtwdev->chip->chip_id == RTL8922A) {
597 ltr_idle_lat_ctrl = 0x90039003;
598 ltr_act_lat_ctrl = 0x880b880b;
599 } else {
600 ltr_idle_lat_ctrl = 0x90019001;
601 ltr_act_lat_ctrl = 0x88018801;
602 }
603
604 rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX3_V1, ltr_idle_lat_ctrl);
605 rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX1_V1, ltr_act_lat_ctrl);
606 rtw89_write32(rtwdev, R_BE_LTR_LATENCY_IDX0_V1, 0);
607 rtw89_write32(rtwdev, R_BE_LTR_DECISION_CTRL_V1, dec_ctrl);
608 rtw89_write32(rtwdev, R_BE_LTR_CFG_0, cfg0);
609 rtw89_write32(rtwdev, R_BE_LTR_CFG_1, cfg1);
610 rtw89_write32(rtwdev, R_BE_LTR_CTRL_0, ctrl0);
611
612 return 0;
613 }
614 EXPORT_SYMBOL(rtw89_pci_ltr_set_v2);
615
rtw89_pci_configure_mit_be(struct rtw89_dev * rtwdev)616 static void rtw89_pci_configure_mit_be(struct rtw89_dev *rtwdev)
617 {
618 u32 cnt;
619 u32 val;
620
621 rtw89_write32_mask(rtwdev, R_BE_PCIE_MIT0_TMR,
622 B_BE_PCIE_MIT0_RX_TMR_MASK, BE_MIT0_TMR_UNIT_1MS);
623
624 val = rtw89_read32(rtwdev, R_BE_PCIE_MIT0_CNT);
625 cnt = min_t(u32, U8_MAX, RTW89_PCI_RXBD_NUM_MAX / 2);
626 val = u32_replace_bits(val, cnt, B_BE_PCIE_RX_MIT0_CNT_MASK);
627 val = u32_replace_bits(val, 2, B_BE_PCIE_RX_MIT0_TMR_CNT_MASK);
628 rtw89_write32(rtwdev, R_BE_PCIE_MIT0_CNT, val);
629 }
630
rtw89_pci_ops_mac_post_init_be(struct rtw89_dev * rtwdev)631 static int rtw89_pci_ops_mac_post_init_be(struct rtw89_dev *rtwdev)
632 {
633 const struct rtw89_pci_info *info = rtwdev->pci_info;
634 int ret;
635
636 ret = info->ltr_set(rtwdev, true);
637 if (ret) {
638 rtw89_err(rtwdev, "pci ltr set fail\n");
639 return ret;
640 }
641
642 rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_IGNORE,
643 MAC_AX_PCIE_IGNORE, MAC_AX_PCIE_ENABLE);
644 rtw89_pci_ctrl_wpdma_pcie_be(rtwdev, true);
645 rtw89_pci_ctrl_txdma_ch_be(rtwdev, true);
646 rtw89_pci_ctrl_txdma_fw_ch_be(rtwdev, true);
647 rtw89_pci_configure_mit_be(rtwdev);
648
649 return 0;
650 }
651
rtw89_pci_poll_io_idle_be(struct rtw89_dev * rtwdev)652 static int rtw89_pci_poll_io_idle_be(struct rtw89_dev *rtwdev)
653 {
654 u32 sts;
655 int ret;
656
657 ret = read_poll_timeout_atomic(rtw89_read32, sts,
658 !(sts & B_BE_HAXI_MST_BUSY),
659 10, 1000, false, rtwdev,
660 R_BE_HAXI_DMA_BUSY1);
661 if (ret) {
662 rtw89_err(rtwdev, "pci dmach busy1 0x%X\n", sts);
663 return ret;
664 }
665
666 return 0;
667 }
668
rtw89_pci_lv1rst_stop_dma_be(struct rtw89_dev * rtwdev)669 static int rtw89_pci_lv1rst_stop_dma_be(struct rtw89_dev *rtwdev)
670 {
671 int ret;
672
673 rtw89_pci_ctrl_dma_all(rtwdev, false);
674 ret = rtw89_pci_poll_io_idle_be(rtwdev);
675 if (!ret)
676 return 0;
677
678 rtw89_debug(rtwdev, RTW89_DBG_HCI,
679 "[PCIe] poll_io_idle fail; reset hci dma trx\n");
680
681 rtw89_mac_ctrl_hci_dma_trx(rtwdev, false);
682 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true);
683
684 return rtw89_pci_poll_io_idle_be(rtwdev);
685 }
686
rtw89_pci_lv1rst_start_dma_be(struct rtw89_dev * rtwdev)687 static int rtw89_pci_lv1rst_start_dma_be(struct rtw89_dev *rtwdev)
688 {
689 int ret;
690
691 rtw89_mac_ctrl_hci_dma_trx(rtwdev, false);
692 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true);
693 rtw89_pci_clr_idx_all(rtwdev);
694
695 ret = rtw89_pci_rst_bdram_be(rtwdev);
696 if (ret)
697 return ret;
698
699 rtw89_pci_ctrl_dma_all(rtwdev, true);
700 return 0;
701 }
702
rtw89_pci_disable_eq_be(struct rtw89_dev * rtwdev)703 static void rtw89_pci_disable_eq_be(struct rtw89_dev *rtwdev)
704 {
705 u32 backup_aspm, phy_offset;
706 u16 oobs_val, offset_cal;
707 u16 g1_oobs, g2_oobs;
708 u8 gen;
709
710 if (rtwdev->chip->chip_id != RTL8922A)
711 return;
712
713 g1_oobs = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G1 +
714 RAC_ANA09 * RAC_MULT, BAC_OOBS_SEL);
715 g2_oobs = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G2 +
716 RAC_ANA09 * RAC_MULT, BAC_OOBS_SEL);
717 if (g1_oobs && g2_oobs)
718 return;
719
720 backup_aspm = rtw89_read32(rtwdev, R_BE_PCIE_MIX_CFG);
721 rtw89_write32_clr(rtwdev, R_BE_PCIE_MIX_CFG, B_BE_RTK_ASPM_CTRL_MASK);
722
723 /* offset K */
724 for (gen = 1; gen <= 2; gen++) {
725 phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 :
726 R_RAC_DIRECT_OFFSET_BE_LANE0_G2;
727
728 rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT,
729 B_PCIE_BIT_RD_SEL);
730 }
731
732 offset_cal = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G1 +
733 RAC_ANA1F * RAC_MULT, OFFSET_CAL_MASK);
734
735 for (gen = 1; gen <= 2; gen++) {
736 phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 :
737 R_RAC_DIRECT_OFFSET_BE_LANE0_G2;
738
739 rtw89_write16_mask(rtwdev, phy_offset + RAC_ANA0B * RAC_MULT,
740 MANUAL_LVL_MASK, offset_cal);
741 rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT,
742 OFFSET_CAL_MODE);
743 }
744
745 /* OOBS */
746 for (gen = 1; gen <= 2; gen++) {
747 phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 :
748 R_RAC_DIRECT_OFFSET_BE_LANE0_G2;
749
750 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA0D * RAC_MULT,
751 BAC_RX_TEST_EN);
752 rtw89_write16_mask(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT,
753 ADDR_SEL_MASK, ADDR_SEL_VAL);
754 rtw89_write16_clr(rtwdev, phy_offset + RAC_ANA10 * RAC_MULT,
755 B_PCIE_BIT_PINOUT_DIS);
756 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA19 * RAC_MULT,
757 B_PCIE_BIT_RD_SEL);
758 }
759
760 oobs_val = rtw89_read16_mask(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G1 +
761 RAC_ANA1F * RAC_MULT, OOBS_LEVEL_MASK);
762
763 for (gen = 1; gen <= 2; gen++) {
764 phy_offset = gen == 1 ? R_RAC_DIRECT_OFFSET_BE_LANE0_G1 :
765 R_RAC_DIRECT_OFFSET_BE_LANE0_G2;
766
767 rtw89_write16_mask(rtwdev, phy_offset + RAC_ANA03 * RAC_MULT,
768 OOBS_SEN_MASK, oobs_val);
769 rtw89_write16_set(rtwdev, phy_offset + RAC_ANA09 * RAC_MULT,
770 BAC_OOBS_SEL);
771 }
772
773 rtw89_write32(rtwdev, R_BE_PCIE_MIX_CFG, backup_aspm);
774 }
775
rtw89_pci_suspend_be(struct device * dev)776 static int __maybe_unused rtw89_pci_suspend_be(struct device *dev)
777 {
778 struct ieee80211_hw *hw = dev_get_drvdata(dev);
779 struct rtw89_dev *rtwdev = hw->priv;
780 u32 val32;
781
782 rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6);
783 rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_R_DIS_PRST);
784 rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6);
785 rtw89_write32_set(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_FRZ_REG_RST);
786
787 val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
788 if (val32 & B_BE_PL1_SER_PL1_EN) {
789 val32 = u32_replace_bits(val32, PCIE_SER_WOW_TIMER_UNIT,
790 B_BE_PL1_TIMER_UNIT_MASK);
791 rtw89_write32(rtwdev, R_BE_SER_PL1_CTRL, val32);
792
793 if (rtwdev->chip->chip_id == RTL8922A)
794 rtw89_write32_clr(rtwdev, R_BE_REG_PL1_MASK,
795 B_BE_SER_PM_MASTER_IMR);
796 }
797
798 return 0;
799 }
800
rtw89_pci_resume_be(struct device * dev)801 static int __maybe_unused rtw89_pci_resume_be(struct device *dev)
802 {
803 struct ieee80211_hw *hw = dev_get_drvdata(dev);
804 struct rtw89_dev *rtwdev = hw->priv;
805 u32 polling;
806 u32 val32;
807 u16 val16;
808 int ret;
809
810 rtw89_write32_set(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6);
811 rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_R_DIS_PRST);
812 rtw89_write32_clr(rtwdev, R_BE_RSV_CTRL, B_BE_WLOCK_1C_BIT6);
813 rtw89_write32_clr(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_FRZ_REG_RST);
814
815 val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
816 if (!(val32 & B_BE_PL1_SER_PL1_EN))
817 goto clear_phy_isr;
818
819 rtw89_write32_clr(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_SER_PL1_EN);
820 if (rtwdev->chip->chip_id == RTL8922D)
821 rtw89_write32(rtwdev, R_BE_REG_PL1_ISR, B_PCIE_SER_ALL_ISR);
822
823 ret = read_poll_timeout_atomic(rtw89_read32, polling, !polling, 1, 1000,
824 false, rtwdev, R_BE_REG_PL1_ISR);
825 if (ret)
826 rtw89_warn(rtwdev, "[ERR] PCIE SER clear polling fail\n");
827
828 if (rtwdev->chip->chip_id == RTL8922A)
829 rtw89_write32_set(rtwdev, R_BE_REG_PL1_MASK,
830 B_BE_SER_PM_MASTER_IMR | B_BE_SER_PCLKREQ_ACK_MASK);
831
832 val32 = rtw89_read32(rtwdev, R_BE_SER_PL1_CTRL);
833 val32 = u32_replace_bits(val32, PCIE_SER_TIMER_UNIT, B_BE_PL1_TIMER_UNIT_MASK);
834 val32 |= B_BE_PL1_SER_PL1_EN;
835 rtw89_write32(rtwdev, R_BE_SER_PL1_CTRL, val32);
836
837 clear_phy_isr:
838 if (rtwdev->chip->chip_id == RTL8922D) {
839 val16 = rtw89_read16(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
840 RAC_ANA41 * RAC_MULT);
841 if (val16 & PHY_ERR_FLAG_EN) {
842 rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
843 RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
844 rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G2 +
845 RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
846 }
847
848 val16 = rtw89_read16(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
849 RAC_ANA41 * RAC_MULT);
850 if (val16 & PHY_ERR_FLAG_EN) {
851 rtw89_write16_clr(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
852 RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
853 rtw89_write16_set(rtwdev, RAC_DIRECT_OFFESET_L0_G1 +
854 RAC_ANA41 * RAC_MULT, PHY_ERR_FLAG_EN);
855 }
856
857 rtw89_write32(rtwdev, R_BE_PCIE_HCI2FW_ISR, 0xFFFFFFFF);
858 }
859
860 rtw89_pci_basic_cfg(rtwdev, true);
861
862 return 0;
863 }
864
865 SIMPLE_DEV_PM_OPS(rtw89_pm_ops_be, rtw89_pci_suspend_be, rtw89_pci_resume_be);
866 EXPORT_SYMBOL(rtw89_pm_ops_be);
867
868 const struct rtw89_pci_isr_def rtw89_pci_isr_be = {
869 .isr_rdu = B_BE_RDU_CH1_INT_V1 | B_BE_RDU_CH0_INT_V1,
870 .isr_halt_c2h = B_BE_HALT_C2H_INT,
871 .isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT,
872 .isr_sps_ocp = 0,
873 .isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1},
874 .isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1},
875 };
876 EXPORT_SYMBOL(rtw89_pci_isr_be);
877
878 const struct rtw89_pci_isr_def rtw89_pci_isr_be_v1 = {
879 .isr_rdu = B_BE_PCIE_RDU_CH1_INT | B_BE_PCIE_RDU_CH0_INT,
880 .isr_halt_c2h = B_BE_HALT_C2H_INT,
881 .isr_wdt_timeout = B_BE_WDT_TIMEOUT_INT,
882 .isr_sps_ocp = B_BE_SPS_OCP_INT | B_BE_SPSANA_OCP_INT,
883 .isr_clear_rpq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RPQ0_ISR_V1},
884 .isr_clear_rxq = {R_BE_PCIE_DMA_ISR, B_BE_PCIE_RX_RX0P2_ISR_V1},
885 };
886 EXPORT_SYMBOL(rtw89_pci_isr_be_v1);
887
888 const struct rtw89_pci_gen_def rtw89_pci_gen_be = {
889 .mac_pre_init = rtw89_pci_ops_mac_pre_init_be,
890 .mac_pre_deinit = rtw89_pci_ops_mac_pre_deinit_be,
891 .mac_post_init = rtw89_pci_ops_mac_post_init_be,
892
893 .clr_idx_all = rtw89_pci_clr_idx_all_be,
894 .rst_bdram = rtw89_pci_rst_bdram_be,
895
896 .lv1rst_stop_dma = rtw89_pci_lv1rst_stop_dma_be,
897 .lv1rst_start_dma = rtw89_pci_lv1rst_start_dma_be,
898
899 .ctrl_txdma_ch = rtw89_pci_ctrl_txdma_ch_be,
900 .ctrl_txdma_fw_ch = rtw89_pci_ctrl_txdma_fw_ch_be,
901 .poll_txdma_ch_idle = rtw89_pci_poll_txdma_ch_idle_be,
902
903 .aspm_set = rtw89_pci_aspm_set_be,
904 .clkreq_set = rtw89_pci_clkreq_set_be,
905 .l1ss_set = rtw89_pci_l1ss_set_be,
906
907 .disable_eq = rtw89_pci_disable_eq_be,
908 .power_wake = _patch_pcie_power_wake_be,
909 };
910 EXPORT_SYMBOL(rtw89_pci_gen_be);
911