1 // SPDX-License-Identifier: GPL-2.0-only
2 /**
3 * ADE9000 driver
4 *
5 * Copyright 2025 Analog Devices Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/completion.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/iio/iio.h>
15 #include <linux/iio/buffer.h>
16 #include <linux/iio/kfifo_buf.h>
17 #include <linux/iio/events.h>
18 #include <linux/interrupt.h>
19 #include <linux/minmax.h>
20 #include <linux/module.h>
21 #include <linux/property.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/spi/spi.h>
25 #include <linux/unaligned.h>
26
27 /* Address of ADE9000 registers */
28 #define ADE9000_REG_AIGAIN 0x000
29 #define ADE9000_REG_AVGAIN 0x00B
30 #define ADE9000_REG_AIRMSOS 0x00C
31 #define ADE9000_REG_AVRMSOS 0x00D
32 #define ADE9000_REG_APGAIN 0x00E
33 #define ADE9000_REG_AWATTOS 0x00F
34 #define ADE9000_REG_AVAROS 0x010
35 #define ADE9000_REG_AFVAROS 0x012
36 #define ADE9000_REG_CONFIG0 0x060
37 #define ADE9000_REG_DICOEFF 0x072
38 #define ADE9000_REG_AI_PCF 0x20A
39 #define ADE9000_REG_AV_PCF 0x20B
40 #define ADE9000_REG_AIRMS 0x20C
41 #define ADE9000_REG_AVRMS 0x20D
42 #define ADE9000_REG_AWATT 0x210
43 #define ADE9000_REG_AVAR 0x211
44 #define ADE9000_REG_AVA 0x212
45 #define ADE9000_REG_AFVAR 0x214
46 #define ADE9000_REG_APF 0x216
47 #define ADE9000_REG_BI_PCF 0x22A
48 #define ADE9000_REG_BV_PCF 0x22B
49 #define ADE9000_REG_BIRMS 0x22C
50 #define ADE9000_REG_BVRMS 0x22D
51 #define ADE9000_REG_CI_PCF 0x24A
52 #define ADE9000_REG_CV_PCF 0x24B
53 #define ADE9000_REG_CIRMS 0x24C
54 #define ADE9000_REG_CVRMS 0x24D
55 #define ADE9000_REG_AWATT_ACC 0x2E5
56 #define ADE9000_REG_AWATTHR_LO 0x2E6
57 #define ADE9000_REG_AVAHR_LO 0x2FA
58 #define ADE9000_REG_AFVARHR_LO 0x30E
59 #define ADE9000_REG_BWATTHR_LO 0x322
60 #define ADE9000_REG_BVAHR_LO 0x336
61 #define ADE9000_REG_BFVARHR_LO 0x34A
62 #define ADE9000_REG_CWATTHR_LO 0x35E
63 #define ADE9000_REG_CVAHR_LO 0x372
64 #define ADE9000_REG_CFVARHR_LO 0x386
65 #define ADE9000_REG_STATUS0 0x402
66 #define ADE9000_REG_STATUS1 0x403
67 #define ADE9000_REG_MASK0 0x405
68 #define ADE9000_REG_MASK1 0x406
69 #define ADE9000_REG_EVENT_MASK 0x407
70 #define ADE9000_REG_VLEVEL 0x40F
71 #define ADE9000_REG_DIP_LVL 0x410
72 #define ADE9000_REG_DIPA 0x411
73 #define ADE9000_REG_DIPB 0x412
74 #define ADE9000_REG_DIPC 0x413
75 #define ADE9000_REG_SWELL_LVL 0x414
76 #define ADE9000_REG_SWELLA 0x415
77 #define ADE9000_REG_SWELLB 0x416
78 #define ADE9000_REG_SWELLC 0x417
79 #define ADE9000_REG_APERIOD 0x418
80 #define ADE9000_REG_BPERIOD 0x419
81 #define ADE9000_REG_CPERIOD 0x41A
82 #define ADE9000_REG_RUN 0x480
83 #define ADE9000_REG_CONFIG1 0x481
84 #define ADE9000_REG_ACCMODE 0x492
85 #define ADE9000_REG_CONFIG3 0x493
86 #define ADE9000_REG_ZXTOUT 0x498
87 #define ADE9000_REG_ZX_LP_SEL 0x49A
88 #define ADE9000_REG_WFB_CFG 0x4A0
89 #define ADE9000_REG_WFB_PG_IRQEN 0x4A1
90 #define ADE9000_REG_WFB_TRG_CFG 0x4A2
91 #define ADE9000_REG_WFB_TRG_STAT 0x4A3
92 #define ADE9000_REG_CONFIG2 0x4AF
93 #define ADE9000_REG_EP_CFG 0x4B0
94 #define ADE9000_REG_EGY_TIME 0x4B2
95 #define ADE9000_REG_PGA_GAIN 0x4B9
96 #define ADE9000_REG_VERSION 0x4FE
97 #define ADE9000_REG_WF_BUFF 0x800
98 #define ADE9000_REG_WF_HALF_BUFF 0xC00
99
100 #define ADE9000_REG_ADDR_MASK GENMASK(15, 4)
101 #define ADE9000_REG_READ_BIT_MASK BIT(3)
102
103 #define ADE9000_WF_CAP_EN_MASK BIT(4)
104 #define ADE9000_WF_CAP_SEL_MASK BIT(5)
105 #define ADE9000_WF_MODE_MASK GENMASK(7, 6)
106 #define ADE9000_WF_SRC_MASK GENMASK(9, 8)
107 #define ADE9000_WF_IN_EN_MASK BIT(12)
108
109 /* External reference selection bit in CONFIG1 */
110 #define ADE9000_EXT_REF_MASK BIT(15)
111
112 /*
113 * Configuration registers
114 */
115 #define ADE9000_PGA_GAIN 0x0000
116
117 /* Default configuration */
118
119 #define ADE9000_CONFIG0 0x00000000
120
121 /* CF3/ZX pin outputs Zero crossing, CF4 = DREADY */
122 #define ADE9000_CONFIG1 0x000E
123
124 /* Default High pass corner frequency of 1.25Hz */
125 #define ADE9000_CONFIG2 0x0A00
126
127 /* Peak and overcurrent detection disabled */
128 #define ADE9000_CONFIG3 0x0000
129
130 /*
131 * 50Hz operation, 3P4W Wye configuration, signed accumulation
132 * 3P4W Wye = 3-Phase 4-Wire star configuration (3 phases + neutral wire)
133 * Clear bit 8 i.e. ACCMODE=0x00xx for 50Hz operation
134 * ACCMODE=0x0x9x for 3Wire delta when phase B is used as reference
135 * 3Wire delta = 3-Phase 3-Wire triangle configuration (3 phases, no neutral)
136 */
137 #define ADE9000_ACCMODE 0x0000
138 #define ADE9000_ACCMODE_60HZ 0x0100
139
140 /*Line period and zero crossing obtained from VA */
141 #define ADE9000_ZX_LP_SEL 0x0000
142
143 /* Interrupt mask values for initialization */
144 #define ADE9000_MASK0_ALL_INT_DIS 0
145 #define ADE9000_MASK1_ALL_INT_DIS 0x00000000
146
147 /* Events disabled */
148 #define ADE9000_EVENT_DISABLE 0x00000000
149
150 /*
151 * Assuming Vnom=1/2 of full scale.
152 * Refer to Technical reference manual for detailed calculations.
153 */
154 #define ADE9000_VLEVEL 0x0022EA28
155
156 /* Set DICOEFF= 0xFFFFE000 when integrator is enabled */
157 #define ADE9000_DICOEFF 0x00000000
158
159 /* DSP ON */
160 #define ADE9000_RUN_ON 0xFFFFFFFF
161
162 /*
163 * Energy Accumulation Settings
164 * Enable energy accumulation, accumulate samples at 8ksps
165 * latch energy accumulation after EGYRDY
166 * If accumulation is changed to half line cycle mode, change EGY_TIME
167 */
168 #define ADE9000_EP_CFG 0x0011
169
170 /* Accumulate 4000 samples */
171 #define ADE9000_EGY_TIME 7999
172
173 /*
174 * Constant Definitions
175 * ADE9000 FDSP: 8000sps, ADE9000 FDSP: 4000sps
176 */
177 #define ADE9000_FDSP 4000
178 #define ADE9000_DEFAULT_CLK_FREQ_HZ 24576000
179 #define ADE9000_WFB_CFG 0x03E9
180 #define ADE9000_WFB_PAGE_SIZE 128
181 #define ADE9000_WFB_NR_OF_PAGES 16
182 #define ADE9000_WFB_MAX_CHANNELS 8
183 #define ADE9000_WFB_BYTES_IN_SAMPLE 4
184 #define ADE9000_WFB_SAMPLES_IN_PAGE \
185 (ADE9000_WFB_PAGE_SIZE / ADE9000_WFB_MAX_CHANNELS)
186 #define ADE9000_WFB_MAX_SAMPLES_CHAN \
187 (ADE9000_WFB_SAMPLES_IN_PAGE * ADE9000_WFB_NR_OF_PAGES)
188 #define ADE9000_WFB_FULL_BUFF_NR_SAMPLES \
189 (ADE9000_WFB_PAGE_SIZE * ADE9000_WFB_NR_OF_PAGES)
190 #define ADE9000_WFB_FULL_BUFF_SIZE \
191 (ADE9000_WFB_FULL_BUFF_NR_SAMPLES * ADE9000_WFB_BYTES_IN_SAMPLE)
192
193 #define ADE9000_SWRST_BIT BIT(0)
194
195 /* Status and Mask register bits*/
196 #define ADE9000_ST0_WFB_TRIG_BIT BIT(16)
197 #define ADE9000_ST0_PAGE_FULL_BIT BIT(17)
198 #define ADE9000_ST0_EGYRDY BIT(0)
199
200 #define ADE9000_ST1_ZXTOVA_BIT BIT(6)
201 #define ADE9000_ST1_ZXTOVB_BIT BIT(7)
202 #define ADE9000_ST1_ZXTOVC_BIT BIT(8)
203 #define ADE9000_ST1_ZXVA_BIT BIT(9)
204 #define ADE9000_ST1_ZXVB_BIT BIT(10)
205 #define ADE9000_ST1_ZXVC_BIT BIT(11)
206 #define ADE9000_ST1_ZXIA_BIT BIT(13)
207 #define ADE9000_ST1_ZXIB_BIT BIT(14)
208 #define ADE9000_ST1_ZXIC_BIT BIT(15)
209 #define ADE9000_ST1_RSTDONE_BIT BIT(16)
210 #define ADE9000_ST1_SEQERR_BIT BIT(18)
211 #define ADE9000_ST1_SWELLA_BIT BIT(20)
212 #define ADE9000_ST1_SWELLB_BIT BIT(21)
213 #define ADE9000_ST1_SWELLC_BIT BIT(22)
214 #define ADE9000_ST1_DIPA_BIT BIT(23)
215 #define ADE9000_ST1_DIPB_BIT BIT(24)
216 #define ADE9000_ST1_DIPC_BIT BIT(25)
217 #define ADE9000_ST1_ERROR0_BIT BIT(28)
218 #define ADE9000_ST1_ERROR1_BIT BIT(29)
219 #define ADE9000_ST1_ERROR2_BIT BIT(30)
220 #define ADE9000_ST1_ERROR3_BIT BIT(31)
221 #define ADE9000_ST1_CROSSING_FIRST 6
222 #define ADE9000_ST1_CROSSING_DEPTH 25
223
224 #define ADE9000_WFB_TRG_DIP_BIT BIT(0)
225 #define ADE9000_WFB_TRG_SWELL_BIT BIT(1)
226 #define ADE9000_WFB_TRG_ZXIA_BIT BIT(3)
227 #define ADE9000_WFB_TRG_ZXIB_BIT BIT(4)
228 #define ADE9000_WFB_TRG_ZXIC_BIT BIT(5)
229 #define ADE9000_WFB_TRG_ZXVA_BIT BIT(6)
230 #define ADE9000_WFB_TRG_ZXVB_BIT BIT(7)
231 #define ADE9000_WFB_TRG_ZXVC_BIT BIT(8)
232
233 /* Stop when waveform buffer is full */
234 #define ADE9000_WFB_FULL_MODE 0x0
235 /* Continuous fill—stop only on enabled trigger events */
236 #define ADE9000_WFB_EN_TRIG_MODE 0x1
237 /* Continuous filling—center capture around enabled trigger events */
238 #define ADE9000_WFB_C_EN_TRIG_MODE 0x2
239 /* Continuous fill—used as streaming mode for continuous data output */
240 #define ADE9000_WFB_STREAMING_MODE 0x3
241
242 #define ADE9000_LAST_PAGE_BIT BIT(15)
243 #define ADE9000_MIDDLE_PAGE_BIT BIT(7)
244
245 /*
246 * Full scale Codes referred from Datasheet. Respective digital codes are
247 * produced when ADC inputs are at full scale.
248 */
249 #define ADE9000_RMS_FULL_SCALE_CODES 52866837
250 #define ADE9000_WATT_FULL_SCALE_CODES 20694066
251 #define ADE9000_PCF_FULL_SCALE_CODES 74770000
252
253 /* Phase and channel definitions */
254 #define ADE9000_PHASE_A_NR 0
255 #define ADE9000_PHASE_B_NR 1
256 #define ADE9000_PHASE_C_NR 2
257
258 #define ADE9000_SCAN_POS_IA BIT(0)
259 #define ADE9000_SCAN_POS_VA BIT(1)
260 #define ADE9000_SCAN_POS_IB BIT(2)
261 #define ADE9000_SCAN_POS_VB BIT(3)
262 #define ADE9000_SCAN_POS_IC BIT(4)
263 #define ADE9000_SCAN_POS_VC BIT(5)
264
265 /* Waveform buffer configuration values */
266 enum ade9000_wfb_cfg {
267 ADE9000_WFB_CFG_ALL_CHAN = 0x0,
268 ADE9000_WFB_CFG_IA_VA = 0x1,
269 ADE9000_WFB_CFG_IB_VB = 0x2,
270 ADE9000_WFB_CFG_IC_VC = 0x3,
271 ADE9000_WFB_CFG_IA = 0x8,
272 ADE9000_WFB_CFG_VA = 0x9,
273 ADE9000_WFB_CFG_IB = 0xA,
274 ADE9000_WFB_CFG_VB = 0xB,
275 ADE9000_WFB_CFG_IC = 0xC,
276 ADE9000_WFB_CFG_VC = 0xD,
277 };
278
279 #define ADE9000_PHASE_B_POS_BIT BIT(5)
280 #define ADE9000_PHASE_C_POS_BIT BIT(6)
281
282 #define ADE9000_MAX_PHASE_NR 3
283
284 /*
285 * Calculate register address for multi-phase device.
286 * Phase A (chan 0): base address + 0x00
287 * Phase B (chan 1): base address + 0x20
288 * Phase C (chan 2): base address + 0x40
289 */
290 #define ADE9000_ADDR_ADJUST(addr, chan) \
291 (((chan) == 0 ? 0 : (chan) == 1 ? 2 : 4) << 4 | (addr))
292
293 struct ade9000_state {
294 struct completion reset_completion;
295 struct mutex lock; /* Protects SPI transactions */
296 u8 wf_src;
297 u32 wfb_trg;
298 u8 wfb_nr_activ_chan;
299 u32 wfb_nr_samples;
300 struct spi_device *spi;
301 struct clk *clkin;
302 struct spi_transfer xfer[2];
303 struct spi_message spi_msg;
304 struct regmap *regmap;
305 union{
306 u8 byte[ADE9000_WFB_FULL_BUFF_SIZE];
307 __be32 word[ADE9000_WFB_FULL_BUFF_NR_SAMPLES];
308 } rx_buff __aligned(IIO_DMA_MINALIGN);
309 u8 tx_buff[2] __aligned(IIO_DMA_MINALIGN);
310 unsigned int bulk_read_buf[2];
311 };
312
313 struct ade9000_irq1_event {
314 u32 bit_mask;
315 enum iio_chan_type chan_type;
316 u32 channel;
317 enum iio_event_type event_type;
318 enum iio_event_direction event_dir;
319 };
320
321 static const struct ade9000_irq1_event ade9000_irq1_events[] = {
322 { ADE9000_ST1_ZXVA_BIT, IIO_VOLTAGE, ADE9000_PHASE_A_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER },
323 { ADE9000_ST1_ZXIA_BIT, IIO_CURRENT, ADE9000_PHASE_A_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER },
324 { ADE9000_ST1_ZXVB_BIT, IIO_VOLTAGE, ADE9000_PHASE_B_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER },
325 { ADE9000_ST1_ZXIB_BIT, IIO_CURRENT, ADE9000_PHASE_B_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER },
326 { ADE9000_ST1_ZXVC_BIT, IIO_VOLTAGE, ADE9000_PHASE_C_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER },
327 { ADE9000_ST1_ZXIC_BIT, IIO_CURRENT, ADE9000_PHASE_C_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER },
328 { ADE9000_ST1_SWELLA_BIT, IIO_ALTVOLTAGE, ADE9000_PHASE_A_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING },
329 { ADE9000_ST1_SWELLB_BIT, IIO_ALTVOLTAGE, ADE9000_PHASE_B_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING },
330 { ADE9000_ST1_SWELLC_BIT, IIO_ALTVOLTAGE, ADE9000_PHASE_C_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING },
331 { ADE9000_ST1_DIPA_BIT, IIO_ALTVOLTAGE, ADE9000_PHASE_A_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING },
332 { ADE9000_ST1_DIPB_BIT, IIO_ALTVOLTAGE, ADE9000_PHASE_B_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING },
333 { ADE9000_ST1_DIPC_BIT, IIO_ALTVOLTAGE, ADE9000_PHASE_C_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING },
334 };
335
336 /* Voltage events (zero crossing on instantaneous voltage) */
337 static const struct iio_event_spec ade9000_voltage_events[] = {
338 {
339 /* Zero crossing detection - datasheet: ZXV interrupts */
340 .type = IIO_EV_TYPE_THRESH,
341 .dir = IIO_EV_DIR_EITHER,
342 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
343 },
344 };
345
346 /* Current events (zero crossing on instantaneous current) */
347 static const struct iio_event_spec ade9000_current_events[] = {
348 {
349 /* Zero crossing detection - datasheet: ZXI interrupts */
350 .type = IIO_EV_TYPE_THRESH,
351 .dir = IIO_EV_DIR_EITHER,
352 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
353 },
354 };
355
356 /* RMS voltage events (swell/sag detection on RMS values) */
357 static const struct iio_event_spec ade9000_rms_voltage_events[] = {
358 {
359 .type = IIO_EV_TYPE_THRESH,
360 .dir = IIO_EV_DIR_RISING, /* RMS swell detection */
361 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE),
362 },
363 {
364 .type = IIO_EV_TYPE_THRESH,
365 .dir = IIO_EV_DIR_FALLING, /* RMS sag/dip detection */
366 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE),
367 },
368 };
369
370 static const char * const ade9000_filter_type_items[] = {
371 "sinc4", "sinc4+lp",
372 };
373
374 static const int ade9000_filter_type_values[] = {
375 0, 2,
376 };
377
ade9000_filter_type_get(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)378 static int ade9000_filter_type_get(struct iio_dev *indio_dev,
379 const struct iio_chan_spec *chan)
380 {
381 struct ade9000_state *st = iio_priv(indio_dev);
382 u32 val;
383 int ret;
384 unsigned int i;
385
386 ret = regmap_read(st->regmap, ADE9000_REG_WFB_CFG, &val);
387 if (ret)
388 return ret;
389
390 val = FIELD_GET(ADE9000_WF_SRC_MASK, val);
391
392 for (i = 0; i < ARRAY_SIZE(ade9000_filter_type_values); i++) {
393 if (ade9000_filter_type_values[i] == val)
394 return i;
395 }
396
397 return -EINVAL;
398 }
399
ade9000_filter_type_set(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int index)400 static int ade9000_filter_type_set(struct iio_dev *indio_dev,
401 const struct iio_chan_spec *chan,
402 unsigned int index)
403 {
404 struct ade9000_state *st = iio_priv(indio_dev);
405 int ret, val;
406
407 if (index >= ARRAY_SIZE(ade9000_filter_type_values))
408 return -EINVAL;
409
410 val = ade9000_filter_type_values[index];
411
412 /* Update the WFB_CFG register with the new filter type */
413 ret = regmap_update_bits(st->regmap, ADE9000_REG_WFB_CFG,
414 ADE9000_WF_SRC_MASK,
415 FIELD_PREP(ADE9000_WF_SRC_MASK, val));
416 if (ret)
417 return ret;
418
419 /* Update cached value */
420 st->wf_src = val;
421
422 return 0;
423 }
424
425 static const struct iio_enum ade9000_filter_type_enum = {
426 .items = ade9000_filter_type_items,
427 .num_items = ARRAY_SIZE(ade9000_filter_type_items),
428 .get = ade9000_filter_type_get,
429 .set = ade9000_filter_type_set,
430 };
431
432 static const struct iio_chan_spec_ext_info ade9000_ext_info[] = {
433 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ade9000_filter_type_enum),
434 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, &ade9000_filter_type_enum),
435 { }
436 };
437
438 #define ADE9000_CURRENT_CHANNEL(num) { \
439 .type = IIO_CURRENT, \
440 .channel = num, \
441 .address = ADE9000_ADDR_ADJUST(ADE9000_REG_AI_PCF, num), \
442 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
443 BIT(IIO_CHAN_INFO_SCALE) | \
444 BIT(IIO_CHAN_INFO_CALIBSCALE), \
445 .event_spec = ade9000_current_events, \
446 .num_event_specs = ARRAY_SIZE(ade9000_current_events), \
447 .scan_index = num, \
448 .indexed = 1, \
449 .scan_type = { \
450 .sign = 's', \
451 .realbits = 32, \
452 .storagebits = 32, \
453 .endianness = IIO_BE, \
454 }, \
455 }
456
457 #define ADE9000_VOLTAGE_CHANNEL(num) { \
458 .type = IIO_VOLTAGE, \
459 .channel = num, \
460 .address = ADE9000_ADDR_ADJUST(ADE9000_REG_AV_PCF, num), \
461 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
462 BIT(IIO_CHAN_INFO_SCALE) | \
463 BIT(IIO_CHAN_INFO_CALIBSCALE) | \
464 BIT(IIO_CHAN_INFO_FREQUENCY), \
465 .event_spec = ade9000_voltage_events, \
466 .num_event_specs = ARRAY_SIZE(ade9000_voltage_events), \
467 .scan_index = num + 1, /* interleave with current channels */ \
468 .indexed = 1, \
469 .scan_type = { \
470 .sign = 's', \
471 .realbits = 32, \
472 .storagebits = 32, \
473 .endianness = IIO_BE, \
474 }, \
475 .ext_info = ade9000_ext_info, \
476 }
477
478 #define ADE9000_ALTCURRENT_RMS_CHANNEL(num) { \
479 .type = IIO_ALTCURRENT, \
480 .channel = num, \
481 .address = ADE9000_ADDR_ADJUST(ADE9000_REG_AIRMS, num), \
482 .channel2 = IIO_MOD_RMS, \
483 .modified = 1, \
484 .indexed = 1, \
485 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
486 BIT(IIO_CHAN_INFO_SCALE) | \
487 BIT(IIO_CHAN_INFO_CALIBBIAS), \
488 .scan_index = -1 \
489 }
490
491 #define ADE9000_ALTVOLTAGE_RMS_CHANNEL(num) { \
492 .type = IIO_ALTVOLTAGE, \
493 .channel = num, \
494 .address = ADE9000_ADDR_ADJUST(ADE9000_REG_AVRMS, num), \
495 .channel2 = IIO_MOD_RMS, \
496 .modified = 1, \
497 .indexed = 1, \
498 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
499 BIT(IIO_CHAN_INFO_SCALE) | \
500 BIT(IIO_CHAN_INFO_CALIBBIAS), \
501 .event_spec = ade9000_rms_voltage_events, \
502 .num_event_specs = ARRAY_SIZE(ade9000_rms_voltage_events), \
503 .scan_index = -1 \
504 }
505
506 #define ADE9000_POWER_ACTIVE_CHANNEL(num) { \
507 .type = IIO_POWER, \
508 .channel = num, \
509 .address = ADE9000_ADDR_ADJUST(ADE9000_REG_AWATT, num), \
510 .channel2 = IIO_MOD_ACTIVE, \
511 .modified = 1, \
512 .indexed = 1, \
513 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
514 BIT(IIO_CHAN_INFO_SCALE) | \
515 BIT(IIO_CHAN_INFO_CALIBBIAS) | \
516 BIT(IIO_CHAN_INFO_CALIBSCALE), \
517 .scan_index = -1 \
518 }
519
520 #define ADE9000_POWER_REACTIVE_CHANNEL(num) { \
521 .type = IIO_POWER, \
522 .channel = num, \
523 .address = ADE9000_ADDR_ADJUST(ADE9000_REG_AVAR, num), \
524 .channel2 = IIO_MOD_REACTIVE, \
525 .modified = 1, \
526 .indexed = 1, \
527 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
528 BIT(IIO_CHAN_INFO_SCALE) | \
529 BIT(IIO_CHAN_INFO_CALIBBIAS), \
530 .scan_index = -1 \
531 }
532
533 #define ADE9000_POWER_APPARENT_CHANNEL(num) { \
534 .type = IIO_POWER, \
535 .channel = num, \
536 .address = ADE9000_ADDR_ADJUST(ADE9000_REG_AVA, num), \
537 .channel2 = IIO_MOD_APPARENT, \
538 .modified = 1, \
539 .indexed = 1, \
540 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
541 BIT(IIO_CHAN_INFO_SCALE), \
542 .scan_index = -1 \
543 }
544
545 #define ADE9000_ENERGY_ACTIVE_CHANNEL(num, addr) { \
546 .type = IIO_ENERGY, \
547 .channel = num, \
548 .address = addr, \
549 .channel2 = IIO_MOD_ACTIVE, \
550 .modified = 1, \
551 .indexed = 1, \
552 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
553 .scan_index = -1 \
554 }
555
556 #define ADE9000_ENERGY_APPARENT_CHANNEL(num, addr) { \
557 .type = IIO_ENERGY, \
558 .channel = num, \
559 .address = addr, \
560 .channel2 = IIO_MOD_APPARENT, \
561 .modified = 1, \
562 .indexed = 1, \
563 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
564 .scan_index = -1 \
565 }
566
567 #define ADE9000_ENERGY_REACTIVE_CHANNEL(num, addr) { \
568 .type = IIO_ENERGY, \
569 .channel = num, \
570 .address = addr, \
571 .channel2 = IIO_MOD_REACTIVE, \
572 .modified = 1, \
573 .indexed = 1, \
574 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
575 .scan_index = -1 \
576 }
577
578 #define ADE9000_POWER_FACTOR_CHANNEL(num) { \
579 .type = IIO_POWER, \
580 .channel = num, \
581 .address = ADE9000_ADDR_ADJUST(ADE9000_REG_APF, num), \
582 .indexed = 1, \
583 .info_mask_separate = BIT(IIO_CHAN_INFO_POWERFACTOR), \
584 .scan_index = -1 \
585 }
586
587 static const struct iio_chan_spec ade9000_channels[] = {
588 /* Phase A channels */
589 ADE9000_CURRENT_CHANNEL(ADE9000_PHASE_A_NR),
590 ADE9000_VOLTAGE_CHANNEL(ADE9000_PHASE_A_NR),
591 ADE9000_ALTCURRENT_RMS_CHANNEL(ADE9000_PHASE_A_NR),
592 ADE9000_ALTVOLTAGE_RMS_CHANNEL(ADE9000_PHASE_A_NR),
593 ADE9000_POWER_ACTIVE_CHANNEL(ADE9000_PHASE_A_NR),
594 ADE9000_POWER_REACTIVE_CHANNEL(ADE9000_PHASE_A_NR),
595 ADE9000_POWER_APPARENT_CHANNEL(ADE9000_PHASE_A_NR),
596 ADE9000_ENERGY_ACTIVE_CHANNEL(ADE9000_PHASE_A_NR, ADE9000_REG_AWATTHR_LO),
597 ADE9000_ENERGY_APPARENT_CHANNEL(ADE9000_PHASE_A_NR, ADE9000_REG_AVAHR_LO),
598 ADE9000_ENERGY_REACTIVE_CHANNEL(ADE9000_PHASE_A_NR, ADE9000_REG_AFVARHR_LO),
599 ADE9000_POWER_FACTOR_CHANNEL(ADE9000_PHASE_A_NR),
600 /* Phase B channels */
601 ADE9000_CURRENT_CHANNEL(ADE9000_PHASE_B_NR),
602 ADE9000_VOLTAGE_CHANNEL(ADE9000_PHASE_B_NR),
603 ADE9000_ALTCURRENT_RMS_CHANNEL(ADE9000_PHASE_B_NR),
604 ADE9000_ALTVOLTAGE_RMS_CHANNEL(ADE9000_PHASE_B_NR),
605 ADE9000_POWER_ACTIVE_CHANNEL(ADE9000_PHASE_B_NR),
606 ADE9000_POWER_REACTIVE_CHANNEL(ADE9000_PHASE_B_NR),
607 ADE9000_POWER_APPARENT_CHANNEL(ADE9000_PHASE_B_NR),
608 ADE9000_ENERGY_ACTIVE_CHANNEL(ADE9000_PHASE_B_NR, ADE9000_REG_BWATTHR_LO),
609 ADE9000_ENERGY_APPARENT_CHANNEL(ADE9000_PHASE_B_NR, ADE9000_REG_BVAHR_LO),
610 ADE9000_ENERGY_REACTIVE_CHANNEL(ADE9000_PHASE_B_NR, ADE9000_REG_BFVARHR_LO),
611 ADE9000_POWER_FACTOR_CHANNEL(ADE9000_PHASE_B_NR),
612 /* Phase C channels */
613 ADE9000_CURRENT_CHANNEL(ADE9000_PHASE_C_NR),
614 ADE9000_VOLTAGE_CHANNEL(ADE9000_PHASE_C_NR),
615 ADE9000_ALTCURRENT_RMS_CHANNEL(ADE9000_PHASE_C_NR),
616 ADE9000_ALTVOLTAGE_RMS_CHANNEL(ADE9000_PHASE_C_NR),
617 ADE9000_POWER_ACTIVE_CHANNEL(ADE9000_PHASE_C_NR),
618 ADE9000_POWER_REACTIVE_CHANNEL(ADE9000_PHASE_C_NR),
619 ADE9000_POWER_APPARENT_CHANNEL(ADE9000_PHASE_C_NR),
620 ADE9000_ENERGY_ACTIVE_CHANNEL(ADE9000_PHASE_C_NR, ADE9000_REG_CWATTHR_LO),
621 ADE9000_ENERGY_APPARENT_CHANNEL(ADE9000_PHASE_C_NR, ADE9000_REG_CVAHR_LO),
622 ADE9000_ENERGY_REACTIVE_CHANNEL(ADE9000_PHASE_C_NR, ADE9000_REG_CFVARHR_LO),
623 ADE9000_POWER_FACTOR_CHANNEL(ADE9000_PHASE_C_NR),
624 };
625
626 static const struct reg_sequence ade9000_initialization_sequence[] = {
627 { ADE9000_REG_PGA_GAIN, ADE9000_PGA_GAIN },
628 { ADE9000_REG_CONFIG0, ADE9000_CONFIG0 },
629 { ADE9000_REG_CONFIG1, ADE9000_CONFIG1 },
630 { ADE9000_REG_CONFIG2, ADE9000_CONFIG2 },
631 { ADE9000_REG_CONFIG3, ADE9000_CONFIG3 },
632 { ADE9000_REG_ACCMODE, ADE9000_ACCMODE },
633 { ADE9000_REG_ZX_LP_SEL, ADE9000_ZX_LP_SEL },
634 { ADE9000_REG_MASK0, ADE9000_MASK0_ALL_INT_DIS },
635 { ADE9000_REG_MASK1, ADE9000_MASK1_ALL_INT_DIS },
636 { ADE9000_REG_EVENT_MASK, ADE9000_EVENT_DISABLE },
637 { ADE9000_REG_WFB_CFG, ADE9000_WFB_CFG },
638 { ADE9000_REG_VLEVEL, ADE9000_VLEVEL },
639 { ADE9000_REG_DICOEFF, ADE9000_DICOEFF },
640 { ADE9000_REG_EGY_TIME, ADE9000_EGY_TIME },
641 { ADE9000_REG_EP_CFG, ADE9000_EP_CFG },
642 /* Clear all pending status bits by writing 1s */
643 { ADE9000_REG_STATUS0, GENMASK(31, 0) },
644 { ADE9000_REG_STATUS1, GENMASK(31, 0) },
645 { ADE9000_REG_RUN, ADE9000_RUN_ON }
646 };
647
ade9000_spi_write_reg(void * context,unsigned int reg,unsigned int val)648 static int ade9000_spi_write_reg(void *context, unsigned int reg,
649 unsigned int val)
650 {
651 struct ade9000_state *st = context;
652 u8 tx_buf[6];
653 u16 addr;
654 int ret, len;
655
656 guard(mutex)(&st->lock);
657
658 addr = FIELD_PREP(ADE9000_REG_ADDR_MASK, reg);
659 put_unaligned_be16(addr, tx_buf);
660
661 if (reg > ADE9000_REG_RUN && reg < ADE9000_REG_VERSION) {
662 put_unaligned_be16(val, &tx_buf[2]);
663 len = 4;
664 } else {
665 put_unaligned_be32(val, &tx_buf[2]);
666 len = 6;
667 }
668
669 ret = spi_write_then_read(st->spi, tx_buf, len, NULL, 0);
670 if (ret)
671 dev_err(&st->spi->dev, "problem when writing register 0x%x\n", reg);
672
673 return ret;
674 }
675
ade9000_spi_read_reg(void * context,unsigned int reg,unsigned int * val)676 static int ade9000_spi_read_reg(void *context, unsigned int reg,
677 unsigned int *val)
678 {
679 struct ade9000_state *st = context;
680 u8 tx_buf[2];
681 u8 rx_buf[4];
682 u16 addr;
683 int ret, rx_len;
684
685 guard(mutex)(&st->lock);
686
687 addr = FIELD_PREP(ADE9000_REG_ADDR_MASK, reg) |
688 ADE9000_REG_READ_BIT_MASK;
689
690 put_unaligned_be16(addr, tx_buf);
691
692 /* Skip CRC bytes - only read actual data */
693 if (reg > ADE9000_REG_RUN && reg < ADE9000_REG_VERSION)
694 rx_len = 2;
695 else
696 rx_len = 4;
697
698 ret = spi_write_then_read(st->spi, tx_buf, 2, rx_buf, rx_len);
699 if (ret) {
700 dev_err(&st->spi->dev, "error reading register 0x%x\n", reg);
701 return ret;
702 }
703
704 if (reg > ADE9000_REG_RUN && reg < ADE9000_REG_VERSION)
705 *val = get_unaligned_be16(rx_buf);
706 else
707 *val = get_unaligned_be32(rx_buf);
708
709 return 0;
710 }
711
ade9000_is_volatile_reg(struct device * dev,unsigned int reg)712 static bool ade9000_is_volatile_reg(struct device *dev, unsigned int reg)
713 {
714 switch (reg) {
715 /* Interrupt/error status registers - volatile */
716 case ADE9000_REG_STATUS0:
717 case ADE9000_REG_STATUS1:
718 return true;
719 default:
720 /* All other registers are non-volatile */
721 return false;
722 }
723 }
724
ade9000_configure_scan(struct iio_dev * indio_dev,u32 wfb_addr)725 static void ade9000_configure_scan(struct iio_dev *indio_dev, u32 wfb_addr)
726 {
727 struct ade9000_state *st = iio_priv(indio_dev);
728 u16 addr;
729
730 addr = FIELD_PREP(ADE9000_REG_ADDR_MASK, wfb_addr) |
731 ADE9000_REG_READ_BIT_MASK;
732
733 put_unaligned_be16(addr, st->tx_buff);
734
735 st->xfer[0].tx_buf = &st->tx_buff[0];
736 st->xfer[0].len = 2;
737
738 st->xfer[1].rx_buf = st->rx_buff.byte;
739
740 /* Always use streaming mode */
741 st->xfer[1].len = (st->wfb_nr_samples / 2) * 4;
742
743 spi_message_init_with_transfers(&st->spi_msg, st->xfer, ARRAY_SIZE(st->xfer));
744 }
745
ade9000_iio_push_streaming(struct iio_dev * indio_dev)746 static int ade9000_iio_push_streaming(struct iio_dev *indio_dev)
747 {
748 struct ade9000_state *st = iio_priv(indio_dev);
749 struct device *dev = &st->spi->dev;
750 u32 current_page, i;
751 int ret;
752
753 guard(mutex)(&st->lock);
754
755 ret = spi_sync(st->spi, &st->spi_msg);
756 if (ret) {
757 dev_err_ratelimited(dev, "SPI fail in trigger handler\n");
758 return ret;
759 }
760
761 /* In streaming mode, only half the buffer is filled per interrupt */
762 for (i = 0; i < st->wfb_nr_samples / 2; i += st->wfb_nr_activ_chan)
763 iio_push_to_buffers(indio_dev, &st->rx_buff.word[i]);
764
765 ret = regmap_read(st->regmap, ADE9000_REG_WFB_PG_IRQEN, ¤t_page);
766 if (ret) {
767 dev_err_ratelimited(dev, "IRQ0 WFB read fail\n");
768 return ret;
769 }
770
771 if (current_page & ADE9000_MIDDLE_PAGE_BIT) {
772 ret = regmap_write(st->regmap, ADE9000_REG_WFB_PG_IRQEN,
773 ADE9000_LAST_PAGE_BIT);
774 if (ret) {
775 dev_err_ratelimited(dev, "IRQ0 WFB write fail\n");
776 return ret;
777 }
778
779 ade9000_configure_scan(indio_dev,
780 ADE9000_REG_WF_HALF_BUFF);
781 } else {
782 ret = regmap_write(st->regmap, ADE9000_REG_WFB_PG_IRQEN,
783 ADE9000_MIDDLE_PAGE_BIT);
784 if (ret) {
785 dev_err_ratelimited(dev, "IRQ0 WFB write fail");
786 return ret;
787 }
788
789 ade9000_configure_scan(indio_dev, ADE9000_REG_WF_BUFF);
790 }
791
792 return 0;
793 }
794
ade9000_iio_push_buffer(struct iio_dev * indio_dev)795 static int ade9000_iio_push_buffer(struct iio_dev *indio_dev)
796 {
797 struct ade9000_state *st = iio_priv(indio_dev);
798 int ret;
799 u32 i;
800
801 guard(mutex)(&st->lock);
802
803 ret = spi_sync(st->spi, &st->spi_msg);
804 if (ret) {
805 dev_err_ratelimited(&st->spi->dev,
806 "SPI fail in trigger handler\n");
807 return ret;
808 }
809
810 for (i = 0; i < st->wfb_nr_samples; i += st->wfb_nr_activ_chan)
811 iio_push_to_buffers(indio_dev, &st->rx_buff.word[i]);
812
813 return 0;
814 }
815
ade9000_irq0_thread(int irq,void * data)816 static irqreturn_t ade9000_irq0_thread(int irq, void *data)
817 {
818 struct iio_dev *indio_dev = data;
819 struct ade9000_state *st = iio_priv(indio_dev);
820 struct device *dev = &st->spi->dev;
821 u32 handled_irq = 0;
822 u32 interrupts, status;
823 int ret;
824
825 ret = regmap_read(st->regmap, ADE9000_REG_STATUS0, &status);
826 if (ret) {
827 dev_err_ratelimited(dev, "IRQ0 read status fail\n");
828 return IRQ_HANDLED;
829 }
830
831 ret = regmap_read(st->regmap, ADE9000_REG_MASK0, &interrupts);
832 if (ret) {
833 dev_err_ratelimited(dev, "IRQ0 read mask fail\n");
834 return IRQ_HANDLED;
835 }
836
837 if ((status & ADE9000_ST0_PAGE_FULL_BIT) &&
838 (interrupts & ADE9000_ST0_PAGE_FULL_BIT)) {
839 /* Always use streaming mode */
840 ret = ade9000_iio_push_streaming(indio_dev);
841 if (ret) {
842 dev_err_ratelimited(dev, "IRQ0 IIO push fail\n");
843 return IRQ_HANDLED;
844 }
845
846 handled_irq |= ADE9000_ST0_PAGE_FULL_BIT;
847 }
848
849 if ((status & ADE9000_ST0_WFB_TRIG_BIT) &&
850 (interrupts & ADE9000_ST0_WFB_TRIG_BIT)) {
851 ret = regmap_update_bits(st->regmap, ADE9000_REG_WFB_CFG,
852 ADE9000_WF_CAP_EN_MASK, 0);
853 if (ret) {
854 dev_err_ratelimited(dev, "IRQ0 WFB fail\n");
855 return IRQ_HANDLED;
856 }
857
858 if (iio_buffer_enabled(indio_dev)) {
859 ret = ade9000_iio_push_buffer(indio_dev);
860 if (ret) {
861 dev_err_ratelimited(dev,
862 "IRQ0 IIO push fail @ WFB TRIG\n");
863 return IRQ_HANDLED;
864 }
865 }
866
867 handled_irq |= ADE9000_ST0_WFB_TRIG_BIT;
868 }
869
870 ret = regmap_write(st->regmap, ADE9000_REG_STATUS0, handled_irq);
871 if (ret)
872 dev_err_ratelimited(dev, "IRQ0 write status fail\n");
873
874 return IRQ_HANDLED;
875 }
876
ade9000_irq1_thread(int irq,void * data)877 static irqreturn_t ade9000_irq1_thread(int irq, void *data)
878 {
879 struct iio_dev *indio_dev = data;
880 struct ade9000_state *st = iio_priv(indio_dev);
881 unsigned int bit = ADE9000_ST1_CROSSING_FIRST;
882 s64 timestamp = iio_get_time_ns(indio_dev);
883 u32 handled_irq = 0;
884 u32 interrupts, result, status, tmp;
885 DECLARE_BITMAP(interrupt_bits, ADE9000_ST1_CROSSING_DEPTH);
886 const struct ade9000_irq1_event *event;
887 int ret, i;
888
889 if (!completion_done(&st->reset_completion)) {
890 ret = regmap_read(st->regmap, ADE9000_REG_STATUS1, &result);
891 if (ret) {
892 dev_err_ratelimited(&st->spi->dev, "IRQ1 read status fail\n");
893 return IRQ_HANDLED;
894 }
895
896 if (result & ADE9000_ST1_RSTDONE_BIT) {
897 complete(&st->reset_completion);
898 /* Clear the reset done status bit */
899 ret = regmap_write(st->regmap, ADE9000_REG_STATUS1, ADE9000_ST1_RSTDONE_BIT);
900 if (ret)
901 dev_err_ratelimited(&st->spi->dev,
902 "IRQ1 clear reset status fail\n");
903 } else {
904 dev_err_ratelimited(&st->spi->dev,
905 "Error testing reset done\n");
906 }
907
908 return IRQ_HANDLED;
909 }
910
911 ret = regmap_read(st->regmap, ADE9000_REG_STATUS1, &status);
912 if (ret) {
913 dev_err_ratelimited(&st->spi->dev, "IRQ1 read status fail\n");
914 return IRQ_HANDLED;
915 }
916
917 ret = regmap_read(st->regmap, ADE9000_REG_MASK1, &interrupts);
918 if (ret) {
919 dev_err_ratelimited(&st->spi->dev, "IRQ1 read mask fail\n");
920 return IRQ_HANDLED;
921 }
922
923 bitmap_from_arr32(interrupt_bits, &interrupts, ADE9000_ST1_CROSSING_DEPTH);
924 for_each_set_bit_from(bit, interrupt_bits,
925 ADE9000_ST1_CROSSING_DEPTH) {
926 tmp = status & BIT(bit);
927 if (!tmp)
928 continue;
929
930 event = NULL;
931
932 /* Find corresponding event in lookup table */
933 for (i = 0; i < ARRAY_SIZE(ade9000_irq1_events); i++) {
934 if (ade9000_irq1_events[i].bit_mask == tmp) {
935 event = &ade9000_irq1_events[i];
936 break;
937 }
938 }
939
940 if (event) {
941 iio_push_event(indio_dev,
942 IIO_UNMOD_EVENT_CODE(event->chan_type,
943 event->channel,
944 event->event_type,
945 event->event_dir),
946 timestamp);
947 }
948 handled_irq |= tmp;
949 }
950
951 ret = regmap_write(st->regmap, ADE9000_REG_STATUS1, handled_irq);
952 if (ret)
953 dev_err_ratelimited(&st->spi->dev, "IRQ1 write status fail\n");
954
955 return IRQ_HANDLED;
956 }
957
ade9000_dready_thread(int irq,void * data)958 static irqreturn_t ade9000_dready_thread(int irq, void *data)
959 {
960 struct iio_dev *indio_dev = data;
961
962 /* Handle data ready interrupt from C4/EVENT/DREADY pin */
963 if (iio_device_try_claim_buffer_mode(indio_dev)) {
964 ade9000_iio_push_buffer(indio_dev);
965 iio_device_release_buffer_mode(indio_dev);
966 }
967
968 return IRQ_HANDLED;
969 }
970
ade9000_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)971 static int ade9000_read_raw(struct iio_dev *indio_dev,
972 struct iio_chan_spec const *chan,
973 int *val,
974 int *val2,
975 long mask)
976 {
977 struct ade9000_state *st = iio_priv(indio_dev);
978 unsigned int measured;
979 int ret;
980
981 switch (mask) {
982 case IIO_CHAN_INFO_FREQUENCY:
983 if (chan->type == IIO_VOLTAGE) {
984 int period_reg;
985 int period;
986
987 switch (chan->channel) {
988 case ADE9000_PHASE_A_NR:
989 period_reg = ADE9000_REG_APERIOD;
990 break;
991 case ADE9000_PHASE_B_NR:
992 period_reg = ADE9000_REG_BPERIOD;
993 break;
994 case ADE9000_PHASE_C_NR:
995 period_reg = ADE9000_REG_CPERIOD;
996 break;
997 default:
998 return -EINVAL;
999 }
1000 ret = regmap_read(st->regmap, period_reg, &period);
1001 if (ret)
1002 return ret;
1003 /*
1004 * Frequency = (4MHz * 65536) / (PERIOD + 1)
1005 * 4MHz = ADC sample rate, 65536 = 2^16 period register scaling
1006 * See ADE9000 datasheet section on period measurement
1007 */
1008 *val = 4000 * 65536;
1009 *val2 = period + 1;
1010 return IIO_VAL_FRACTIONAL;
1011 }
1012
1013 return -EINVAL;
1014 case IIO_CHAN_INFO_RAW:
1015 if (chan->type == IIO_ENERGY) {
1016 u16 lo_reg = chan->address;
1017
1018 ret = regmap_bulk_read(st->regmap, lo_reg,
1019 st->bulk_read_buf, 2);
1020 if (ret)
1021 return ret;
1022
1023 *val = st->bulk_read_buf[0]; /* Lower 32 bits */
1024 *val2 = st->bulk_read_buf[1]; /* Upper 32 bits */
1025 return IIO_VAL_INT_64;
1026 }
1027
1028 if (!iio_device_claim_direct(indio_dev))
1029 return -EBUSY;
1030
1031 ret = regmap_read(st->regmap, chan->address, &measured);
1032 iio_device_release_direct(indio_dev);
1033 if (ret)
1034 return ret;
1035
1036 *val = measured;
1037
1038 return IIO_VAL_INT;
1039
1040 case IIO_CHAN_INFO_POWERFACTOR:
1041 if (!iio_device_claim_direct(indio_dev))
1042 return -EBUSY;
1043
1044 ret = regmap_read(st->regmap, chan->address, &measured);
1045 iio_device_release_direct(indio_dev);
1046 if (ret)
1047 return ret;
1048
1049 *val = measured;
1050
1051 return IIO_VAL_INT;
1052
1053 case IIO_CHAN_INFO_SCALE:
1054 switch (chan->type) {
1055 case IIO_CURRENT:
1056 case IIO_VOLTAGE:
1057 case IIO_ALTVOLTAGE:
1058 case IIO_ALTCURRENT:
1059 switch (chan->address) {
1060 case ADE9000_REG_AI_PCF:
1061 case ADE9000_REG_AV_PCF:
1062 case ADE9000_REG_BI_PCF:
1063 case ADE9000_REG_BV_PCF:
1064 case ADE9000_REG_CI_PCF:
1065 case ADE9000_REG_CV_PCF:
1066 *val = 1;
1067 *val2 = ADE9000_PCF_FULL_SCALE_CODES;
1068 return IIO_VAL_FRACTIONAL;
1069 case ADE9000_REG_AIRMS:
1070 case ADE9000_REG_AVRMS:
1071 case ADE9000_REG_BIRMS:
1072 case ADE9000_REG_BVRMS:
1073 case ADE9000_REG_CIRMS:
1074 case ADE9000_REG_CVRMS:
1075 *val = 1;
1076 *val2 = ADE9000_RMS_FULL_SCALE_CODES;
1077 return IIO_VAL_FRACTIONAL;
1078 default:
1079 return -EINVAL;
1080 }
1081 case IIO_POWER:
1082 *val = 1;
1083 *val2 = ADE9000_WATT_FULL_SCALE_CODES;
1084 return IIO_VAL_FRACTIONAL;
1085 default:
1086 break;
1087 }
1088
1089 return -EINVAL;
1090 default:
1091 return -EINVAL;
1092 }
1093 }
1094
ade9000_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)1095 static int ade9000_write_raw(struct iio_dev *indio_dev,
1096 struct iio_chan_spec const *chan,
1097 int val,
1098 int val2,
1099 long mask)
1100 {
1101 struct ade9000_state *st = iio_priv(indio_dev);
1102 u32 tmp;
1103
1104 switch (mask) {
1105 case IIO_CHAN_INFO_CALIBBIAS:
1106 switch (chan->type) {
1107 case IIO_CURRENT:
1108 return regmap_write(st->regmap,
1109 ADE9000_ADDR_ADJUST(ADE9000_REG_AIRMSOS,
1110 chan->channel), val);
1111 case IIO_VOLTAGE:
1112 case IIO_ALTVOLTAGE:
1113 return regmap_write(st->regmap,
1114 ADE9000_ADDR_ADJUST(ADE9000_REG_AVRMSOS,
1115 chan->channel), val);
1116 case IIO_POWER:
1117 tmp = chan->address;
1118 tmp &= ~ADE9000_PHASE_B_POS_BIT;
1119 tmp &= ~ADE9000_PHASE_C_POS_BIT;
1120
1121 switch (tmp) {
1122 case ADE9000_REG_AWATT:
1123 return regmap_write(st->regmap,
1124 ADE9000_ADDR_ADJUST(ADE9000_REG_AWATTOS,
1125 chan->channel), val);
1126 case ADE9000_REG_AVAR:
1127 return regmap_write(st->regmap,
1128 ADE9000_ADDR_ADJUST(ADE9000_REG_AVAROS,
1129 chan->channel), val);
1130 case ADE9000_REG_AFVAR:
1131 return regmap_write(st->regmap,
1132 ADE9000_ADDR_ADJUST(ADE9000_REG_AFVAROS,
1133 chan->channel), val);
1134 default:
1135 return -EINVAL;
1136 }
1137 default:
1138 return -EINVAL;
1139 }
1140 case IIO_CHAN_INFO_CALIBSCALE:
1141 /*
1142 * Calibration gain registers for fine-tuning measurements.
1143 * These are separate from PGA gain and applied in the digital domain.
1144 */
1145 switch (chan->type) {
1146 case IIO_CURRENT:
1147 return regmap_write(st->regmap,
1148 ADE9000_ADDR_ADJUST(ADE9000_REG_AIGAIN,
1149 chan->channel), val);
1150 case IIO_VOLTAGE:
1151 return regmap_write(st->regmap,
1152 ADE9000_ADDR_ADJUST(ADE9000_REG_AVGAIN,
1153 chan->channel), val);
1154 case IIO_POWER:
1155 return regmap_write(st->regmap,
1156 ADE9000_ADDR_ADJUST(ADE9000_REG_APGAIN,
1157 chan->channel), val);
1158 default:
1159 return -EINVAL;
1160 }
1161 case IIO_CHAN_INFO_SCALE:
1162 /* Per-channel scales are read-only */
1163 return -EINVAL;
1164 default:
1165 return -EINVAL;
1166 }
1167 }
1168
ade9000_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int tx_val,unsigned int * rx_val)1169 static int ade9000_reg_access(struct iio_dev *indio_dev,
1170 unsigned int reg,
1171 unsigned int tx_val,
1172 unsigned int *rx_val)
1173 {
1174 struct ade9000_state *st = iio_priv(indio_dev);
1175
1176 if (rx_val)
1177 return regmap_read(st->regmap, reg, rx_val);
1178
1179 return regmap_write(st->regmap, reg, tx_val);
1180 }
1181
ade9000_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1182 static int ade9000_read_event_config(struct iio_dev *indio_dev,
1183 const struct iio_chan_spec *chan,
1184 enum iio_event_type type,
1185 enum iio_event_direction dir)
1186 {
1187 struct ade9000_state *st = iio_priv(indio_dev);
1188 u32 interrupts1;
1189 int ret;
1190
1191 /* All events use MASK1 register */
1192 ret = regmap_read(st->regmap, ADE9000_REG_MASK1, &interrupts1);
1193 if (ret)
1194 return ret;
1195
1196 switch (chan->channel) {
1197 case ADE9000_PHASE_A_NR:
1198 if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER)
1199 return !!(interrupts1 & ADE9000_ST1_ZXVA_BIT);
1200 else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER)
1201 return !!(interrupts1 & ADE9000_ST1_ZXIA_BIT);
1202 else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING)
1203 return !!(interrupts1 & ADE9000_ST1_SWELLA_BIT);
1204 else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING)
1205 return !!(interrupts1 & ADE9000_ST1_DIPA_BIT);
1206 dev_err_ratelimited(&indio_dev->dev,
1207 "Invalid channel type %d or direction %d for phase A\n", chan->type, dir);
1208 return -EINVAL;
1209 case ADE9000_PHASE_B_NR:
1210 if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER)
1211 return !!(interrupts1 & ADE9000_ST1_ZXVB_BIT);
1212 else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER)
1213 return !!(interrupts1 & ADE9000_ST1_ZXIB_BIT);
1214 else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING)
1215 return !!(interrupts1 & ADE9000_ST1_SWELLB_BIT);
1216 else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING)
1217 return !!(interrupts1 & ADE9000_ST1_DIPB_BIT);
1218 dev_err_ratelimited(&indio_dev->dev,
1219 "Invalid channel type %d or direction %d for phase B\n", chan->type, dir);
1220 return -EINVAL;
1221 case ADE9000_PHASE_C_NR:
1222 if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER)
1223 return !!(interrupts1 & ADE9000_ST1_ZXVC_BIT);
1224 else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER)
1225 return !!(interrupts1 & ADE9000_ST1_ZXIC_BIT);
1226 else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING)
1227 return !!(interrupts1 & ADE9000_ST1_SWELLC_BIT);
1228 else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING)
1229 return !!(interrupts1 & ADE9000_ST1_DIPC_BIT);
1230 dev_err_ratelimited(&indio_dev->dev,
1231 "Invalid channel type %d or direction %d for phase C\n", chan->type, dir);
1232 return -EINVAL;
1233 default:
1234 return -EINVAL;
1235 }
1236 }
1237
ade9000_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,bool state)1238 static int ade9000_write_event_config(struct iio_dev *indio_dev,
1239 const struct iio_chan_spec *chan,
1240 enum iio_event_type type,
1241 enum iio_event_direction dir,
1242 bool state)
1243 {
1244 struct ade9000_state *st = iio_priv(indio_dev);
1245 u32 bit_mask;
1246 int ret;
1247
1248 /* Clear all pending events in STATUS1 register (write 1 to clear) */
1249 ret = regmap_write(st->regmap, ADE9000_REG_STATUS1, GENMASK(31, 0));
1250 if (ret)
1251 return ret;
1252
1253 /* Determine which interrupt bit to enable/disable */
1254 switch (chan->channel) {
1255 case ADE9000_PHASE_A_NR:
1256 if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER) {
1257 bit_mask = ADE9000_ST1_ZXVA_BIT;
1258 if (state)
1259 st->wfb_trg |= ADE9000_WFB_TRG_ZXVA_BIT;
1260 else
1261 st->wfb_trg &= ~ADE9000_WFB_TRG_ZXVA_BIT;
1262 } else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER) {
1263 bit_mask = ADE9000_ST1_ZXIA_BIT;
1264 if (state)
1265 st->wfb_trg |= ADE9000_WFB_TRG_ZXIA_BIT;
1266 else
1267 st->wfb_trg &= ~ADE9000_WFB_TRG_ZXIA_BIT;
1268 } else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING) {
1269 bit_mask = ADE9000_ST1_SWELLA_BIT;
1270 if (state)
1271 st->wfb_trg |= ADE9000_WFB_TRG_SWELL_BIT;
1272 else
1273 st->wfb_trg &= ~ADE9000_WFB_TRG_SWELL_BIT;
1274 } else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING) {
1275 bit_mask = ADE9000_ST1_DIPA_BIT;
1276 if (state)
1277 st->wfb_trg |= ADE9000_WFB_TRG_DIP_BIT;
1278 else
1279 st->wfb_trg &= ~ADE9000_WFB_TRG_DIP_BIT;
1280 } else {
1281 dev_err_ratelimited(&indio_dev->dev, "Invalid channel type %d or direction %d for phase A\n",
1282 chan->type, dir);
1283 return -EINVAL;
1284 }
1285 break;
1286 case ADE9000_PHASE_B_NR:
1287 if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER) {
1288 bit_mask = ADE9000_ST1_ZXVB_BIT;
1289 if (state)
1290 st->wfb_trg |= ADE9000_WFB_TRG_ZXVB_BIT;
1291 else
1292 st->wfb_trg &= ~ADE9000_WFB_TRG_ZXVB_BIT;
1293 } else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER) {
1294 bit_mask = ADE9000_ST1_ZXIB_BIT;
1295 if (state)
1296 st->wfb_trg |= ADE9000_WFB_TRG_ZXIB_BIT;
1297 else
1298 st->wfb_trg &= ~ADE9000_WFB_TRG_ZXIB_BIT;
1299 } else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING) {
1300 bit_mask = ADE9000_ST1_SWELLB_BIT;
1301 if (state)
1302 st->wfb_trg |= ADE9000_WFB_TRG_SWELL_BIT;
1303 else
1304 st->wfb_trg &= ~ADE9000_WFB_TRG_SWELL_BIT;
1305 } else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING) {
1306 bit_mask = ADE9000_ST1_DIPB_BIT;
1307 if (state)
1308 st->wfb_trg |= ADE9000_WFB_TRG_DIP_BIT;
1309 else
1310 st->wfb_trg &= ~ADE9000_WFB_TRG_DIP_BIT;
1311 } else {
1312 dev_err_ratelimited(&indio_dev->dev,
1313 "Invalid channel type %d or direction %d for phase B\n",
1314 chan->type, dir);
1315 return -EINVAL;
1316 }
1317 break;
1318 case ADE9000_PHASE_C_NR:
1319 if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER) {
1320 bit_mask = ADE9000_ST1_ZXVC_BIT;
1321 if (state)
1322 st->wfb_trg |= ADE9000_WFB_TRG_ZXVC_BIT;
1323 else
1324 st->wfb_trg &= ~ADE9000_WFB_TRG_ZXVC_BIT;
1325 } else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER) {
1326 bit_mask = ADE9000_ST1_ZXIC_BIT;
1327 if (state)
1328 st->wfb_trg |= ADE9000_WFB_TRG_ZXIC_BIT;
1329 else
1330 st->wfb_trg &= ~ADE9000_WFB_TRG_ZXIC_BIT;
1331 } else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING) {
1332 bit_mask = ADE9000_ST1_SWELLC_BIT;
1333 if (state)
1334 st->wfb_trg |= ADE9000_WFB_TRG_SWELL_BIT;
1335 else
1336 st->wfb_trg &= ~ADE9000_WFB_TRG_SWELL_BIT;
1337 } else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING) {
1338 bit_mask = ADE9000_ST1_DIPC_BIT;
1339 if (state)
1340 st->wfb_trg |= ADE9000_WFB_TRG_DIP_BIT;
1341 else
1342 st->wfb_trg &= ~ADE9000_WFB_TRG_DIP_BIT;
1343 } else {
1344 dev_err_ratelimited(&indio_dev->dev,
1345 "Invalid channel type %d or direction %d for phase C\n",
1346 chan->type, dir);
1347 return -EINVAL;
1348 }
1349 break;
1350 default:
1351 return -EINVAL;
1352 }
1353
1354 /* Set bits if enabling event, clear bits if disabling */
1355 return regmap_assign_bits(st->regmap, ADE9000_REG_MASK1, bit_mask, state ? bit_mask : 0);
1356 }
1357
ade9000_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1358 static int ade9000_write_event_value(struct iio_dev *indio_dev,
1359 const struct iio_chan_spec *chan,
1360 enum iio_event_type type,
1361 enum iio_event_direction dir,
1362 enum iio_event_info info,
1363 int val, int val2)
1364 {
1365 struct ade9000_state *st = iio_priv(indio_dev);
1366
1367 switch (info) {
1368 case IIO_EV_INFO_VALUE:
1369 switch (dir) {
1370 case IIO_EV_DIR_FALLING:
1371 return regmap_write(st->regmap, ADE9000_REG_DIP_LVL, val);
1372 case IIO_EV_DIR_RISING:
1373 return regmap_write(st->regmap, ADE9000_REG_SWELL_LVL, val);
1374 default:
1375 return -EINVAL;
1376 }
1377 default:
1378 return -EINVAL;
1379 }
1380 }
1381
ade9000_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)1382 static int ade9000_read_event_value(struct iio_dev *indio_dev,
1383 const struct iio_chan_spec *chan,
1384 enum iio_event_type type,
1385 enum iio_event_direction dir,
1386 enum iio_event_info info,
1387 int *val, int *val2)
1388 {
1389 struct ade9000_state *st = iio_priv(indio_dev);
1390 unsigned int data;
1391 int ret;
1392
1393 switch (info) {
1394 case IIO_EV_INFO_VALUE:
1395 switch (dir) {
1396 case IIO_EV_DIR_FALLING:
1397 ret = regmap_read(st->regmap, ADE9000_REG_DIP_LVL, &data);
1398 if (ret)
1399 return ret;
1400 *val = data;
1401 return IIO_VAL_INT;
1402 case IIO_EV_DIR_RISING:
1403 ret = regmap_read(st->regmap, ADE9000_REG_SWELL_LVL, &data);
1404 if (ret)
1405 return ret;
1406 *val = data;
1407 return IIO_VAL_INT;
1408 default:
1409 return -EINVAL;
1410 }
1411 default:
1412 return -EINVAL;
1413 }
1414 }
1415
ade9000_waveform_buffer_config(struct iio_dev * indio_dev)1416 static int ade9000_waveform_buffer_config(struct iio_dev *indio_dev)
1417 {
1418 struct ade9000_state *st = iio_priv(indio_dev);
1419 u32 wfb_cfg_val;
1420 u32 active_scans;
1421
1422 bitmap_to_arr32(&active_scans, indio_dev->active_scan_mask,
1423 iio_get_masklength(indio_dev));
1424
1425 switch (active_scans) {
1426 case ADE9000_SCAN_POS_IA | ADE9000_SCAN_POS_VA:
1427 wfb_cfg_val = ADE9000_WFB_CFG_IA_VA;
1428 st->wfb_nr_activ_chan = 2;
1429 break;
1430 case ADE9000_SCAN_POS_IB | ADE9000_SCAN_POS_VB:
1431 wfb_cfg_val = ADE9000_WFB_CFG_IB_VB;
1432 st->wfb_nr_activ_chan = 2;
1433 break;
1434 case ADE9000_SCAN_POS_IC | ADE9000_SCAN_POS_VC:
1435 wfb_cfg_val = ADE9000_WFB_CFG_IC_VC;
1436 st->wfb_nr_activ_chan = 2;
1437 break;
1438 case ADE9000_SCAN_POS_IA:
1439 wfb_cfg_val = ADE9000_WFB_CFG_IA;
1440 st->wfb_nr_activ_chan = 1;
1441 break;
1442 case ADE9000_SCAN_POS_VA:
1443 wfb_cfg_val = ADE9000_WFB_CFG_VA;
1444 st->wfb_nr_activ_chan = 1;
1445 break;
1446 case ADE9000_SCAN_POS_IB:
1447 wfb_cfg_val = ADE9000_WFB_CFG_IB;
1448 st->wfb_nr_activ_chan = 1;
1449 break;
1450 case ADE9000_SCAN_POS_VB:
1451 wfb_cfg_val = ADE9000_WFB_CFG_VB;
1452 st->wfb_nr_activ_chan = 1;
1453 break;
1454 case ADE9000_SCAN_POS_IC:
1455 wfb_cfg_val = ADE9000_WFB_CFG_IC;
1456 st->wfb_nr_activ_chan = 1;
1457 break;
1458 case ADE9000_SCAN_POS_VC:
1459 wfb_cfg_val = ADE9000_WFB_CFG_VC;
1460 st->wfb_nr_activ_chan = 1;
1461 break;
1462 case (ADE9000_SCAN_POS_IA | ADE9000_SCAN_POS_VA | ADE9000_SCAN_POS_IB |
1463 ADE9000_SCAN_POS_VB | ADE9000_SCAN_POS_IC | ADE9000_SCAN_POS_VC):
1464 wfb_cfg_val = ADE9000_WFB_CFG_ALL_CHAN;
1465 st->wfb_nr_activ_chan = 6;
1466 break;
1467 default:
1468 dev_err(&st->spi->dev, "Unsupported combination of scans\n");
1469 return -EINVAL;
1470 }
1471
1472 wfb_cfg_val |= FIELD_PREP(ADE9000_WF_SRC_MASK, st->wf_src);
1473
1474 return regmap_write(st->regmap, ADE9000_REG_WFB_CFG, wfb_cfg_val);
1475 }
1476
ade9000_waveform_buffer_interrupt_setup(struct ade9000_state * st)1477 static int ade9000_waveform_buffer_interrupt_setup(struct ade9000_state *st)
1478 {
1479 int ret;
1480
1481 ret = regmap_write(st->regmap, ADE9000_REG_WFB_TRG_CFG, 0x0);
1482 if (ret)
1483 return ret;
1484
1485 /* Always use streaming mode setup */
1486 ret = regmap_write(st->regmap, ADE9000_REG_WFB_PG_IRQEN,
1487 ADE9000_MIDDLE_PAGE_BIT);
1488 if (ret)
1489 return ret;
1490
1491 ret = regmap_write(st->regmap, ADE9000_REG_STATUS0, GENMASK(31, 0));
1492 if (ret)
1493 return ret;
1494
1495 return regmap_set_bits(st->regmap, ADE9000_REG_MASK0,
1496 ADE9000_ST0_PAGE_FULL_BIT);
1497 }
1498
ade9000_buffer_preenable(struct iio_dev * indio_dev)1499 static int ade9000_buffer_preenable(struct iio_dev *indio_dev)
1500 {
1501 struct ade9000_state *st = iio_priv(indio_dev);
1502 int ret;
1503
1504 ret = ade9000_waveform_buffer_config(indio_dev);
1505 if (ret)
1506 return ret;
1507
1508 st->wfb_nr_samples = ADE9000_WFB_MAX_SAMPLES_CHAN * st->wfb_nr_activ_chan;
1509
1510 ade9000_configure_scan(indio_dev, ADE9000_REG_WF_BUFF);
1511
1512 ret = ade9000_waveform_buffer_interrupt_setup(st);
1513 if (ret)
1514 return ret;
1515
1516 ret = regmap_set_bits(st->regmap, ADE9000_REG_WFB_CFG,
1517 ADE9000_WF_CAP_EN_MASK);
1518 if (ret) {
1519 dev_err(&st->spi->dev, "Post-enable waveform buffer enable fail\n");
1520 return ret;
1521 }
1522
1523 return 0;
1524 }
1525
ade9000_buffer_postdisable(struct iio_dev * indio_dev)1526 static int ade9000_buffer_postdisable(struct iio_dev *indio_dev)
1527 {
1528 struct ade9000_state *st = iio_priv(indio_dev);
1529 struct device *dev = &st->spi->dev;
1530 u32 interrupts;
1531 int ret;
1532
1533 ret = regmap_clear_bits(st->regmap, ADE9000_REG_WFB_CFG,
1534 ADE9000_WF_CAP_EN_MASK);
1535 if (ret) {
1536 dev_err(dev, "Post-disable waveform buffer disable fail\n");
1537 return ret;
1538 }
1539
1540 ret = regmap_write(st->regmap, ADE9000_REG_WFB_TRG_CFG, 0x0);
1541 if (ret)
1542 return ret;
1543
1544 interrupts = ADE9000_ST0_WFB_TRIG_BIT | ADE9000_ST0_PAGE_FULL_BIT;
1545
1546 ret = regmap_clear_bits(st->regmap, ADE9000_REG_MASK0, interrupts);
1547 if (ret) {
1548 dev_err(dev, "Post-disable update mask0 fail\n");
1549 return ret;
1550 }
1551
1552 return regmap_write(st->regmap, ADE9000_REG_STATUS0, GENMASK(31, 0));
1553 }
1554
1555 static const struct iio_buffer_setup_ops ade9000_buffer_ops = {
1556 .preenable = &ade9000_buffer_preenable,
1557 .postdisable = &ade9000_buffer_postdisable,
1558 };
1559
ade9000_reset(struct ade9000_state * st)1560 static int ade9000_reset(struct ade9000_state *st)
1561 {
1562 struct device *dev = &st->spi->dev;
1563 struct gpio_desc *gpio_reset;
1564 int ret;
1565
1566 gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1567 if (IS_ERR(gpio_reset))
1568 return PTR_ERR(gpio_reset);
1569
1570 /* Software reset via register if no GPIO available */
1571 if (!gpio_reset) {
1572 ret = regmap_set_bits(st->regmap, ADE9000_REG_CONFIG1,
1573 ADE9000_SWRST_BIT);
1574 if (ret)
1575 return ret;
1576 fsleep(90);
1577 return 0;
1578 }
1579
1580 /* Hardware reset via GPIO */
1581 fsleep(10);
1582 gpiod_set_value_cansleep(gpio_reset, 0);
1583 fsleep(50000);
1584
1585 /* Only wait for completion if IRQ1 is available to signal reset done */
1586 if (fwnode_irq_get_byname(dev_fwnode(dev), "irq1") >= 0) {
1587 if (!wait_for_completion_timeout(&st->reset_completion,
1588 msecs_to_jiffies(1000)))
1589 return dev_err_probe(dev, -ETIMEDOUT,
1590 "Reset timeout after 1s\n");
1591 }
1592 /* If no IRQ available, reset is already complete after the 50ms delay above */
1593
1594 return 0;
1595 }
1596
ade9000_setup(struct ade9000_state * st)1597 static int ade9000_setup(struct ade9000_state *st)
1598 {
1599 struct device *dev = &st->spi->dev;
1600 int ret;
1601
1602 ret = regmap_multi_reg_write(st->regmap, ade9000_initialization_sequence,
1603 ARRAY_SIZE(ade9000_initialization_sequence));
1604 if (ret)
1605 return dev_err_probe(dev, ret, "Failed to write register sequence");
1606
1607 fsleep(2000);
1608
1609 return 0;
1610 }
1611
1612 static const struct iio_info ade9000_info = {
1613 .read_raw = ade9000_read_raw,
1614 .write_raw = ade9000_write_raw,
1615 .debugfs_reg_access = ade9000_reg_access,
1616 .write_event_config = ade9000_write_event_config,
1617 .read_event_config = ade9000_read_event_config,
1618 .write_event_value = ade9000_write_event_value,
1619 .read_event_value = ade9000_read_event_value,
1620 };
1621
1622 static const struct regmap_config ade9000_regmap_config = {
1623 .reg_bits = 16,
1624 .val_bits = 32,
1625 .max_register = 0x6bc,
1626 .zero_flag_mask = true,
1627 .cache_type = REGCACHE_MAPLE,
1628 .reg_read = ade9000_spi_read_reg,
1629 .reg_write = ade9000_spi_write_reg,
1630 .volatile_reg = ade9000_is_volatile_reg,
1631 };
1632
ade9000_setup_clkout(struct device * dev,struct ade9000_state * st)1633 static int ade9000_setup_clkout(struct device *dev, struct ade9000_state *st)
1634 {
1635 struct clk_hw *clkout_hw;
1636 int ret;
1637
1638 if (!IS_ENABLED(CONFIG_COMMON_CLK))
1639 return 0;
1640
1641 /*
1642 * Only provide clock output when using external CMOS clock.
1643 * When using crystal, CLKOUT is connected to crystal and shouldn't
1644 * be used as clock provider for other devices.
1645 */
1646 if (!device_property_present(dev, "#clock-cells") || !st->clkin)
1647 return 0;
1648
1649 /* CLKOUT passes through CLKIN with divider of 1 */
1650 clkout_hw = devm_clk_hw_register_divider(dev, "clkout", __clk_get_name(st->clkin),
1651 CLK_SET_RATE_PARENT, NULL, 0, 1, 0, NULL);
1652 if (IS_ERR(clkout_hw))
1653 return dev_err_probe(dev, PTR_ERR(clkout_hw), "Failed to register clkout");
1654
1655 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, clkout_hw);
1656 if (ret)
1657 return dev_err_probe(dev, ret, "Failed to add clock provider");
1658
1659 return 0;
1660 }
1661
ade9000_request_irq(struct device * dev,const char * name,irq_handler_t handler,void * dev_id)1662 static int ade9000_request_irq(struct device *dev, const char *name,
1663 irq_handler_t handler, void *dev_id)
1664 {
1665 int irq, ret;
1666
1667 irq = fwnode_irq_get_byname(dev_fwnode(dev), name);
1668 if (irq == -EINVAL)
1669 return 0; /* interrupts are optional */
1670 if (irq < 0)
1671 return dev_err_probe(dev, irq, "Failed to get %s irq", name);
1672
1673 ret = devm_request_threaded_irq(dev, irq, NULL, handler,
1674 IRQF_ONESHOT, KBUILD_MODNAME, dev_id);
1675 if (ret)
1676 return dev_err_probe(dev, ret, "Failed to request %s irq", name);
1677
1678 return 0;
1679 }
1680
ade9000_probe(struct spi_device * spi)1681 static int ade9000_probe(struct spi_device *spi)
1682 {
1683 struct device *dev = &spi->dev;
1684 struct iio_dev *indio_dev;
1685 struct ade9000_state *st;
1686 struct regmap *regmap;
1687 int ret;
1688
1689 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1690 if (!indio_dev)
1691 return -ENOMEM;
1692
1693 st = iio_priv(indio_dev);
1694
1695 regmap = devm_regmap_init(dev, NULL, st, &ade9000_regmap_config);
1696 if (IS_ERR(regmap))
1697 return dev_err_probe(dev, PTR_ERR(regmap), "Unable to allocate ADE9000 regmap");
1698
1699 st->regmap = regmap;
1700 st->spi = spi;
1701
1702 init_completion(&st->reset_completion);
1703
1704 ret = devm_mutex_init(dev, &st->lock);
1705 if (ret)
1706 return ret;
1707
1708 ret = ade9000_request_irq(dev, "irq0", ade9000_irq0_thread, indio_dev);
1709 if (ret)
1710 return ret;
1711
1712 ret = ade9000_request_irq(dev, "irq1", ade9000_irq1_thread, indio_dev);
1713 if (ret)
1714 return ret;
1715
1716 ret = ade9000_request_irq(dev, "dready", ade9000_dready_thread, indio_dev);
1717 if (ret)
1718 return ret;
1719
1720 /* External CMOS clock input (optional - crystal can be used instead) */
1721 st->clkin = devm_clk_get_optional_enabled(dev, NULL);
1722 if (IS_ERR(st->clkin))
1723 return dev_err_probe(dev, PTR_ERR(st->clkin), "Failed to get and enable clkin");
1724
1725 ret = ade9000_setup_clkout(dev, st);
1726 if (ret)
1727 return ret;
1728
1729 indio_dev->name = "ade9000";
1730 indio_dev->info = &ade9000_info;
1731 indio_dev->modes = INDIO_DIRECT_MODE;
1732 indio_dev->setup_ops = &ade9000_buffer_ops;
1733
1734 ret = devm_regulator_get_enable(&spi->dev, "vdd");
1735 if (ret)
1736 return dev_err_probe(&spi->dev, ret,
1737 "Failed to get and enable vdd regulator\n");
1738
1739 indio_dev->channels = ade9000_channels;
1740 indio_dev->num_channels = ARRAY_SIZE(ade9000_channels);
1741
1742 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev,
1743 &ade9000_buffer_ops);
1744 if (ret)
1745 return dev_err_probe(dev, ret, "Failed to setup IIO buffer");
1746
1747 ret = ade9000_reset(st);
1748 if (ret)
1749 return ret;
1750
1751 /* Configure reference selection if vref regulator is available */
1752 ret = devm_regulator_get_enable_optional(dev, "vref");
1753 if (ret != -ENODEV && ret >= 0) {
1754 ret = regmap_set_bits(st->regmap, ADE9000_REG_CONFIG1,
1755 ADE9000_EXT_REF_MASK);
1756 if (ret)
1757 return ret;
1758 } else if (ret < 0 && ret != -ENODEV) {
1759 return dev_err_probe(dev, ret,
1760 "Failed to get and enable vref regulator\n");
1761 }
1762
1763 ret = ade9000_setup(st);
1764 if (ret)
1765 return ret;
1766
1767 return devm_iio_device_register(dev, indio_dev);
1768 };
1769
1770 static const struct spi_device_id ade9000_id[] = {
1771 { "ade9000", 0 },
1772 { }
1773 };
1774 MODULE_DEVICE_TABLE(spi, ade9000_id);
1775
1776 static const struct of_device_id ade9000_of_match[] = {
1777 { .compatible = "adi,ade9000" },
1778 { }
1779 };
1780 MODULE_DEVICE_TABLE(of, ade9000_of_match);
1781
1782 static struct spi_driver ade9000_driver = {
1783 .driver = {
1784 .name = "ade9000",
1785 .of_match_table = ade9000_of_match,
1786 },
1787 .probe = ade9000_probe,
1788 .id_table = ade9000_id,
1789 };
1790 module_spi_driver(ade9000_driver);
1791
1792 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>");
1793 MODULE_DESCRIPTION("Analog Devices ADE9000");
1794 MODULE_LICENSE("GPL");
1795