1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Universal Flash Storage Host controller PCI glue driver
4 *
5 * Copyright (C) 2011-2013 Samsung India Software Operations
6 *
7 * Authors:
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
10 */
11
12 #include <ufs/ufshcd.h>
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/pm_qos.h>
18 #include <linux/suspend.h>
19 #include <linux/debugfs.h>
20 #include <linux/uuid.h>
21 #include <linux/acpi.h>
22 #include <linux/gpio/consumer.h>
23
24 #define MAX_SUPP_MAC 64
25
26 enum intel_ufs_dsm_func_id {
27 INTEL_DSM_FNS = 0,
28 INTEL_DSM_RESET = 1,
29 };
30
31 struct intel_host {
32 u32 dsm_fns;
33 u32 active_ltr;
34 u32 idle_ltr;
35 int saved_spm_lvl;
36 struct dentry *debugfs_root;
37 struct gpio_desc *reset_gpio;
38 };
39
40 static const guid_t intel_dsm_guid =
41 GUID_INIT(0x1A4832A0, 0x7D03, 0x43CA,
42 0xB0, 0x20, 0xF6, 0xDC, 0xD1, 0x2A, 0x19, 0x50);
43
__intel_dsm_supported(struct intel_host * host,enum intel_ufs_dsm_func_id fn)44 static bool __intel_dsm_supported(struct intel_host *host,
45 enum intel_ufs_dsm_func_id fn)
46 {
47 return fn < 32 && fn >= 0 && (host->dsm_fns & (1u << fn));
48 }
49
50 #define INTEL_DSM_SUPPORTED(host, name) \
51 __intel_dsm_supported(host, INTEL_DSM_##name)
52
__intel_dsm(struct intel_host * intel_host,struct device * dev,unsigned int fn,u32 * result)53 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
54 unsigned int fn, u32 *result)
55 {
56 union acpi_object *obj;
57 int err = 0;
58 size_t len;
59
60 obj = acpi_evaluate_dsm_typed(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL,
61 ACPI_TYPE_BUFFER);
62 if (!obj)
63 return -EOPNOTSUPP;
64
65 if (obj->buffer.length < 1) {
66 err = -EINVAL;
67 goto out;
68 }
69
70 len = min_t(size_t, obj->buffer.length, 4);
71
72 *result = 0;
73 memcpy(result, obj->buffer.pointer, len);
74 out:
75 ACPI_FREE(obj);
76
77 return err;
78 }
79
intel_dsm(struct intel_host * intel_host,struct device * dev,unsigned int fn,u32 * result)80 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
81 unsigned int fn, u32 *result)
82 {
83 if (!__intel_dsm_supported(intel_host, fn))
84 return -EOPNOTSUPP;
85
86 return __intel_dsm(intel_host, dev, fn, result);
87 }
88
intel_dsm_init(struct intel_host * intel_host,struct device * dev)89 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev)
90 {
91 int err;
92
93 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
94 dev_dbg(dev, "DSM fns %#x, error %d\n", intel_host->dsm_fns, err);
95 }
96
ufs_intel_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)97 static int ufs_intel_hce_enable_notify(struct ufs_hba *hba,
98 enum ufs_notify_change_status status)
99 {
100 /* Cannot enable ICE until after HC enable */
101 if (status == POST_CHANGE && hba->caps & UFSHCD_CAP_CRYPTO) {
102 u32 hce = ufshcd_readl(hba, REG_CONTROLLER_ENABLE);
103
104 hce |= CRYPTO_GENERAL_ENABLE;
105 ufshcd_writel(hba, hce, REG_CONTROLLER_ENABLE);
106 }
107
108 return 0;
109 }
110
ufs_intel_disable_lcc(struct ufs_hba * hba)111 static int ufs_intel_disable_lcc(struct ufs_hba *hba)
112 {
113 u32 attr = UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE);
114 u32 lcc_enable = 0;
115
116 ufshcd_dme_get(hba, attr, &lcc_enable);
117 if (lcc_enable)
118 ufshcd_disable_host_tx_lcc(hba);
119
120 return 0;
121 }
122
ufs_intel_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)123 static int ufs_intel_link_startup_notify(struct ufs_hba *hba,
124 enum ufs_notify_change_status status)
125 {
126 int err = 0;
127
128 switch (status) {
129 case PRE_CHANGE:
130 err = ufs_intel_disable_lcc(hba);
131 break;
132 case POST_CHANGE:
133 break;
134 default:
135 break;
136 }
137
138 return err;
139 }
140
ufs_intel_set_lanes(struct ufs_hba * hba,u32 lanes)141 static int ufs_intel_set_lanes(struct ufs_hba *hba, u32 lanes)
142 {
143 struct ufs_pa_layer_attr pwr_info = hba->pwr_info;
144 int ret;
145
146 pwr_info.lane_rx = lanes;
147 pwr_info.lane_tx = lanes;
148 ret = ufshcd_change_power_mode(hba, &pwr_info,
149 UFSHCD_PMC_POLICY_DONT_FORCE);
150 if (ret)
151 dev_err(hba->dev, "%s: Setting %u lanes, err = %d\n",
152 __func__, lanes, ret);
153 return ret;
154 }
155
ufs_intel_lkf_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_req_params)156 static int ufs_intel_lkf_pwr_change_notify(struct ufs_hba *hba,
157 enum ufs_notify_change_status status,
158 struct ufs_pa_layer_attr *dev_req_params)
159 {
160 int err = 0;
161
162 switch (status) {
163 case PRE_CHANGE:
164 if (ufshcd_is_hs_mode(dev_req_params) &&
165 (hba->pwr_info.lane_rx != 2 || hba->pwr_info.lane_tx != 2))
166 ufs_intel_set_lanes(hba, 2);
167 break;
168 case POST_CHANGE:
169 if (ufshcd_is_hs_mode(dev_req_params)) {
170 u32 peer_granularity;
171
172 usleep_range(1000, 1250);
173 err = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
174 &peer_granularity);
175 }
176 break;
177 default:
178 break;
179 }
180
181 return err;
182 }
183
ufs_intel_nvl_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status stage,struct ufs_pa_layer_attr * dev_req_params)184 static int ufs_intel_nvl_pwr_change_notify(struct ufs_hba *hba,
185 enum ufs_notify_change_status stage,
186 struct ufs_pa_layer_attr *dev_req_params)
187 {
188 int adapt_val;
189
190 if (stage != PRE_CHANGE || hba->ufs_version < ufshci_version(4, 0))
191 return 0;
192
193 if (dev_req_params->pwr_tx == FAST_MODE || dev_req_params->pwr_tx == FASTAUTO_MODE)
194 adapt_val = PA_INITIAL_ADAPT;
195 else
196 adapt_val = PA_NO_ADAPT;
197
198 ufshcd_dme_configure_adapt(hba, dev_req_params->gear_tx, adapt_val);
199
200 return 0;
201 }
202
ufs_intel_lkf_apply_dev_quirks(struct ufs_hba * hba)203 static int ufs_intel_lkf_apply_dev_quirks(struct ufs_hba *hba)
204 {
205 u32 granularity, peer_granularity;
206 u32 pa_tactivate, peer_pa_tactivate;
207 int ret;
208
209 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), &granularity);
210 if (ret)
211 goto out;
212
213 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), &peer_granularity);
214 if (ret)
215 goto out;
216
217 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
218 if (ret)
219 goto out;
220
221 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &peer_pa_tactivate);
222 if (ret)
223 goto out;
224
225 if (granularity == peer_granularity) {
226 u32 new_peer_pa_tactivate = pa_tactivate + 2;
227
228 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), new_peer_pa_tactivate);
229 }
230 out:
231 return ret;
232 }
233
234 #define INTEL_ACTIVELTR 0x804
235 #define INTEL_IDLELTR 0x808
236
237 #define INTEL_LTR_REQ BIT(15)
238 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10)
239 #define INTEL_LTR_SCALE_1US (2 << 10)
240 #define INTEL_LTR_SCALE_32US (3 << 10)
241 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0)
242
intel_cache_ltr(struct ufs_hba * hba)243 static void intel_cache_ltr(struct ufs_hba *hba)
244 {
245 struct intel_host *host = ufshcd_get_variant(hba);
246
247 host->active_ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
248 host->idle_ltr = readl(hba->mmio_base + INTEL_IDLELTR);
249 }
250
intel_ltr_set(struct device * dev,s32 val)251 static void intel_ltr_set(struct device *dev, s32 val)
252 {
253 struct ufs_hba *hba = dev_get_drvdata(dev);
254 struct intel_host *host = ufshcd_get_variant(hba);
255 u32 ltr;
256
257 pm_runtime_get_sync(dev);
258
259 /*
260 * Program latency tolerance (LTR) accordingly what has been asked
261 * by the PM QoS layer or disable it in case we were passed
262 * negative value or PM_QOS_LATENCY_ANY.
263 */
264 ltr = readl(hba->mmio_base + INTEL_ACTIVELTR);
265
266 if (val == PM_QOS_LATENCY_ANY || val < 0) {
267 ltr &= ~INTEL_LTR_REQ;
268 } else {
269 ltr |= INTEL_LTR_REQ;
270 ltr &= ~INTEL_LTR_SCALE_MASK;
271 ltr &= ~INTEL_LTR_VALUE_MASK;
272
273 if (val > INTEL_LTR_VALUE_MASK) {
274 val >>= 5;
275 if (val > INTEL_LTR_VALUE_MASK)
276 val = INTEL_LTR_VALUE_MASK;
277 ltr |= INTEL_LTR_SCALE_32US | val;
278 } else {
279 ltr |= INTEL_LTR_SCALE_1US | val;
280 }
281 }
282
283 if (ltr == host->active_ltr)
284 goto out;
285
286 writel(ltr, hba->mmio_base + INTEL_ACTIVELTR);
287 writel(ltr, hba->mmio_base + INTEL_IDLELTR);
288
289 /* Cache the values into intel_host structure */
290 intel_cache_ltr(hba);
291 out:
292 pm_runtime_put(dev);
293 }
294
intel_ltr_expose(struct device * dev)295 static void intel_ltr_expose(struct device *dev)
296 {
297 dev->power.set_latency_tolerance = intel_ltr_set;
298 dev_pm_qos_expose_latency_tolerance(dev);
299 }
300
intel_ltr_hide(struct device * dev)301 static void intel_ltr_hide(struct device *dev)
302 {
303 dev_pm_qos_hide_latency_tolerance(dev);
304 dev->power.set_latency_tolerance = NULL;
305 }
306
intel_add_debugfs(struct ufs_hba * hba)307 static void intel_add_debugfs(struct ufs_hba *hba)
308 {
309 struct dentry *dir = debugfs_create_dir(dev_name(hba->dev), NULL);
310 struct intel_host *host = ufshcd_get_variant(hba);
311
312 intel_cache_ltr(hba);
313
314 host->debugfs_root = dir;
315 debugfs_create_x32("active_ltr", 0444, dir, &host->active_ltr);
316 debugfs_create_x32("idle_ltr", 0444, dir, &host->idle_ltr);
317 }
318
intel_remove_debugfs(struct ufs_hba * hba)319 static void intel_remove_debugfs(struct ufs_hba *hba)
320 {
321 struct intel_host *host = ufshcd_get_variant(hba);
322
323 debugfs_remove_recursive(host->debugfs_root);
324 }
325
ufs_intel_device_reset(struct ufs_hba * hba)326 static int ufs_intel_device_reset(struct ufs_hba *hba)
327 {
328 struct intel_host *host = ufshcd_get_variant(hba);
329
330 if (INTEL_DSM_SUPPORTED(host, RESET)) {
331 u32 result = 0;
332 int err;
333
334 err = intel_dsm(host, hba->dev, INTEL_DSM_RESET, &result);
335 if (!err && !result)
336 err = -EIO;
337 if (err)
338 dev_err(hba->dev, "%s: DSM error %d result %u\n",
339 __func__, err, result);
340 return err;
341 }
342
343 if (!host->reset_gpio)
344 return -EOPNOTSUPP;
345
346 gpiod_set_value_cansleep(host->reset_gpio, 1);
347 usleep_range(10, 15);
348
349 gpiod_set_value_cansleep(host->reset_gpio, 0);
350 usleep_range(10, 15);
351
352 return 0;
353 }
354
ufs_intel_get_reset_gpio(struct device * dev)355 static struct gpio_desc *ufs_intel_get_reset_gpio(struct device *dev)
356 {
357 /* GPIO in _DSD has active low setting */
358 return devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
359 }
360
ufs_intel_common_init(struct ufs_hba * hba)361 static int ufs_intel_common_init(struct ufs_hba *hba)
362 {
363 struct intel_host *host;
364
365 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
366
367 host = devm_kzalloc(hba->dev, sizeof(*host), GFP_KERNEL);
368 if (!host)
369 return -ENOMEM;
370 host->saved_spm_lvl = -1;
371 ufshcd_set_variant(hba, host);
372 intel_dsm_init(host, hba->dev);
373 if (INTEL_DSM_SUPPORTED(host, RESET)) {
374 if (hba->vops->device_reset)
375 hba->caps |= UFSHCD_CAP_DEEPSLEEP;
376 } else {
377 if (hba->vops->device_reset)
378 host->reset_gpio = ufs_intel_get_reset_gpio(hba->dev);
379 if (IS_ERR(host->reset_gpio)) {
380 dev_err(hba->dev, "%s: failed to get reset GPIO, error %ld\n",
381 __func__, PTR_ERR(host->reset_gpio));
382 host->reset_gpio = NULL;
383 }
384 if (host->reset_gpio) {
385 gpiod_set_value_cansleep(host->reset_gpio, 0);
386 hba->caps |= UFSHCD_CAP_DEEPSLEEP;
387 }
388 }
389 intel_ltr_expose(hba->dev);
390 intel_add_debugfs(hba);
391 return 0;
392 }
393
ufs_intel_common_exit(struct ufs_hba * hba)394 static void ufs_intel_common_exit(struct ufs_hba *hba)
395 {
396 intel_remove_debugfs(hba);
397 intel_ltr_hide(hba->dev);
398 }
399
ufs_intel_resume(struct ufs_hba * hba,enum ufs_pm_op op)400 static int ufs_intel_resume(struct ufs_hba *hba, enum ufs_pm_op op)
401 {
402 if (ufshcd_is_link_hibern8(hba)) {
403 int ret = ufshcd_uic_hibern8_exit(hba);
404
405 if (!ret) {
406 ufshcd_set_link_active(hba);
407 } else {
408 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
409 __func__, ret);
410 /*
411 * Force reset and restore. Any other actions can lead
412 * to an unrecoverable state.
413 */
414 ufshcd_set_link_off(hba);
415 }
416 }
417
418 return 0;
419 }
420
ufs_intel_ehl_init(struct ufs_hba * hba)421 static int ufs_intel_ehl_init(struct ufs_hba *hba)
422 {
423 hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
424 return ufs_intel_common_init(hba);
425 }
426
ufs_intel_lkf_init(struct ufs_hba * hba)427 static int ufs_intel_lkf_init(struct ufs_hba *hba)
428 {
429 int err;
430
431 hba->nop_out_timeout = 200;
432 hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
433 hba->caps |= UFSHCD_CAP_CRYPTO;
434 err = ufs_intel_common_init(hba);
435 /* LKF always needs a full reset, so set PM accordingly */
436 if (hba->caps & UFSHCD_CAP_DEEPSLEEP) {
437 hba->spm_lvl = UFS_PM_LVL_6;
438 hba->rpm_lvl = UFS_PM_LVL_6;
439 } else {
440 hba->spm_lvl = UFS_PM_LVL_5;
441 hba->rpm_lvl = UFS_PM_LVL_5;
442 }
443 return err;
444 }
445
ufs_intel_adl_init(struct ufs_hba * hba)446 static int ufs_intel_adl_init(struct ufs_hba *hba)
447 {
448 hba->nop_out_timeout = 200;
449 hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 |
450 UFSHCD_QUIRK_PERFORM_LINK_STARTUP_ONCE;
451 hba->caps |= UFSHCD_CAP_WB_EN;
452 return ufs_intel_common_init(hba);
453 }
454
ufs_intel_mtl_init(struct ufs_hba * hba)455 static int ufs_intel_mtl_init(struct ufs_hba *hba)
456 {
457 hba->rpm_lvl = UFS_PM_LVL_2;
458 hba->spm_lvl = UFS_PM_LVL_2;
459 hba->caps |= UFSHCD_CAP_CRYPTO | UFSHCD_CAP_WB_EN;
460 return ufs_intel_common_init(hba);
461 }
462
ufs_intel_mcq_config_resource(struct ufs_hba * hba)463 static int ufs_intel_mcq_config_resource(struct ufs_hba *hba)
464 {
465 hba->mcq_base = hba->mmio_base + ufshcd_mcq_queue_cfg_addr(hba);
466
467 return 0;
468 }
469
470 /*
471 * This Intel UFS4.0 controller maps MCQ doorbell and interrupt-status
472 * registers into the same PCI BAR as the legacy HCI space, at this
473 * fixed offset/stride.
474 */
475 #define UFS_INTEL_SQDAO0 0x2800
476 #define UFS_INTEL_SQISAO0 0x2814
477 #define UFS_INTEL_CQDAO0 0x281C
478 #define UFS_INTEL_CQISAO0 0x2824
479 #define UFS_INTEL_MCQ_STRIDE 0x30
480
ufs_intel_op_runtime_config(struct ufs_hba * hba)481 static int ufs_intel_op_runtime_config(struct ufs_hba *hba)
482 {
483 struct ufshcd_mcq_opr_info_t *opr;
484 int i;
485
486 hba->mcq_opr[OPR_SQD].offset = UFS_INTEL_SQDAO0;
487 hba->mcq_opr[OPR_SQIS].offset = UFS_INTEL_SQISAO0;
488 hba->mcq_opr[OPR_CQD].offset = UFS_INTEL_CQDAO0;
489 hba->mcq_opr[OPR_CQIS].offset = UFS_INTEL_CQISAO0;
490
491 for (i = 0; i < OPR_MAX; i++) {
492 opr = &hba->mcq_opr[i];
493 opr->stride = UFS_INTEL_MCQ_STRIDE;
494 opr->base = hba->mmio_base + opr->offset;
495 }
496
497 return 0;
498 }
499
ufs_qemu_get_hba_mac(struct ufs_hba * hba)500 static int ufs_qemu_get_hba_mac(struct ufs_hba *hba)
501 {
502 return MAX_SUPP_MAC;
503 }
504
ufs_qemu_mcq_config_resource(struct ufs_hba * hba)505 static int ufs_qemu_mcq_config_resource(struct ufs_hba *hba)
506 {
507 hba->mcq_base = hba->mmio_base + ufshcd_mcq_queue_cfg_addr(hba);
508
509 return 0;
510 }
511
ufs_qemu_op_runtime_config(struct ufs_hba * hba)512 static int ufs_qemu_op_runtime_config(struct ufs_hba *hba)
513 {
514 struct ufshcd_mcq_opr_info_t *opr;
515 int i;
516
517 u32 sqdao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_SQDAO, 0));
518 u32 sqisao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_SQISAO, 0));
519 u32 cqdao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_CQDAO, 0));
520 u32 cqisao = ufsmcq_readl(hba, ufshcd_mcq_cfg_offset(REG_CQISAO, 0));
521
522 hba->mcq_opr[OPR_SQD].offset = sqdao;
523 hba->mcq_opr[OPR_SQIS].offset = sqisao;
524 hba->mcq_opr[OPR_CQD].offset = cqdao;
525 hba->mcq_opr[OPR_CQIS].offset = cqisao;
526
527 for (i = 0; i < OPR_MAX; i++) {
528 opr = &hba->mcq_opr[i];
529 opr->stride = 48;
530 opr->base = hba->mmio_base + opr->offset;
531 }
532
533 return 0;
534 }
535
536 static struct ufs_hba_variant_ops ufs_qemu_hba_vops = {
537 .name = "qemu-pci",
538 .get_hba_mac = ufs_qemu_get_hba_mac,
539 .mcq_config_resource = ufs_qemu_mcq_config_resource,
540 .op_runtime_config = ufs_qemu_op_runtime_config,
541 };
542
543 static struct ufs_hba_variant_ops ufs_intel_cnl_hba_vops = {
544 .name = "intel-pci",
545 .init = ufs_intel_common_init,
546 .exit = ufs_intel_common_exit,
547 .link_startup_notify = ufs_intel_link_startup_notify,
548 .resume = ufs_intel_resume,
549 };
550
551 static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops = {
552 .name = "intel-pci",
553 .init = ufs_intel_ehl_init,
554 .exit = ufs_intel_common_exit,
555 .link_startup_notify = ufs_intel_link_startup_notify,
556 .resume = ufs_intel_resume,
557 };
558
559 static struct ufs_hba_variant_ops ufs_intel_lkf_hba_vops = {
560 .name = "intel-pci",
561 .init = ufs_intel_lkf_init,
562 .exit = ufs_intel_common_exit,
563 .hce_enable_notify = ufs_intel_hce_enable_notify,
564 .link_startup_notify = ufs_intel_link_startup_notify,
565 .pwr_change_notify = ufs_intel_lkf_pwr_change_notify,
566 .apply_dev_quirks = ufs_intel_lkf_apply_dev_quirks,
567 .resume = ufs_intel_resume,
568 .device_reset = ufs_intel_device_reset,
569 };
570
571 static struct ufs_hba_variant_ops ufs_intel_adl_hba_vops = {
572 .name = "intel-pci",
573 .init = ufs_intel_adl_init,
574 .exit = ufs_intel_common_exit,
575 .link_startup_notify = ufs_intel_link_startup_notify,
576 .resume = ufs_intel_resume,
577 .device_reset = ufs_intel_device_reset,
578 };
579
580 static struct ufs_hba_variant_ops ufs_intel_mtl_hba_vops = {
581 .name = "intel-pci",
582 .init = ufs_intel_mtl_init,
583 .exit = ufs_intel_common_exit,
584 .hce_enable_notify = ufs_intel_hce_enable_notify,
585 .link_startup_notify = ufs_intel_link_startup_notify,
586 .pwr_change_notify = ufs_intel_nvl_pwr_change_notify,
587 .mcq_config_resource = ufs_intel_mcq_config_resource,
588 .op_runtime_config = ufs_intel_op_runtime_config,
589 .resume = ufs_intel_resume,
590 .device_reset = ufs_intel_device_reset,
591 };
592
593 #ifdef CONFIG_PM_SLEEP
ufshcd_pci_restore(struct device * dev)594 static int ufshcd_pci_restore(struct device *dev)
595 {
596 struct ufs_hba *hba = dev_get_drvdata(dev);
597
598 /* Force a full reset and restore */
599 ufshcd_set_link_off(hba);
600
601 return ufshcd_system_resume(dev);
602 }
603
ufs_intel_suspend_prepare(struct device * dev)604 static int ufs_intel_suspend_prepare(struct device *dev)
605 {
606 struct ufs_hba *hba = dev_get_drvdata(dev);
607 struct intel_host *host = ufshcd_get_variant(hba);
608 int err;
609
610 /*
611 * Only s2idle (S0ix) retains link state. Force power-off
612 * (UFS_PM_LVL_5) for any other case.
613 */
614 if (pm_suspend_target_state != PM_SUSPEND_TO_IDLE && hba->spm_lvl < UFS_PM_LVL_5) {
615 host->saved_spm_lvl = hba->spm_lvl;
616 hba->spm_lvl = UFS_PM_LVL_5;
617 }
618
619 err = ufshcd_suspend_prepare(dev);
620
621 if (err < 0 && host->saved_spm_lvl != -1) {
622 hba->spm_lvl = host->saved_spm_lvl;
623 host->saved_spm_lvl = -1;
624 }
625
626 return err;
627 }
628
ufs_intel_resume_complete(struct device * dev)629 static void ufs_intel_resume_complete(struct device *dev)
630 {
631 struct ufs_hba *hba = dev_get_drvdata(dev);
632 struct intel_host *host = ufshcd_get_variant(hba);
633
634 ufshcd_resume_complete(dev);
635
636 if (host->saved_spm_lvl != -1) {
637 hba->spm_lvl = host->saved_spm_lvl;
638 host->saved_spm_lvl = -1;
639 }
640 }
641
ufshcd_pci_suspend_prepare(struct device * dev)642 static int ufshcd_pci_suspend_prepare(struct device *dev)
643 {
644 struct ufs_hba *hba = dev_get_drvdata(dev);
645
646 if (!strcmp(hba->vops->name, "intel-pci"))
647 return ufs_intel_suspend_prepare(dev);
648
649 return ufshcd_suspend_prepare(dev);
650 }
651
ufshcd_pci_resume_complete(struct device * dev)652 static void ufshcd_pci_resume_complete(struct device *dev)
653 {
654 struct ufs_hba *hba = dev_get_drvdata(dev);
655
656 if (!strcmp(hba->vops->name, "intel-pci")) {
657 ufs_intel_resume_complete(dev);
658 return;
659 }
660
661 ufshcd_resume_complete(dev);
662 }
663 #endif
664
665 /**
666 * ufshcd_pci_remove - de-allocate PCI/SCSI host and host memory space
667 * data structure memory
668 * @pdev: pointer to PCI handle
669 */
ufshcd_pci_remove(struct pci_dev * pdev)670 static void ufshcd_pci_remove(struct pci_dev *pdev)
671 {
672 struct ufs_hba *hba = pci_get_drvdata(pdev);
673
674 pm_runtime_forbid(&pdev->dev);
675 pm_runtime_get_noresume(&pdev->dev);
676 ufshcd_remove(hba);
677 }
678
679 /**
680 * ufshcd_pci_probe - probe routine of the driver
681 * @pdev: pointer to PCI device handle
682 * @id: PCI device id
683 *
684 * Return: 0 on success, non-zero value on failure.
685 */
686 static int
ufshcd_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)687 ufshcd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
688 {
689 struct ufs_hba *hba;
690 void __iomem *mmio_base;
691 int err;
692
693 err = pcim_enable_device(pdev);
694 if (err) {
695 dev_err(&pdev->dev, "pcim_enable_device failed\n");
696 return err;
697 }
698
699 pci_set_master(pdev);
700
701 mmio_base = pcim_iomap_region(pdev, 0, UFSHCD);
702 if (IS_ERR(mmio_base)) {
703 dev_err(&pdev->dev, "request and iomap failed\n");
704 return PTR_ERR(mmio_base);
705 }
706
707 err = ufshcd_alloc_host(&pdev->dev, &hba);
708 if (err) {
709 dev_err(&pdev->dev, "Allocation failed\n");
710 return err;
711 }
712
713 hba->vops = (struct ufs_hba_variant_ops *)id->driver_data;
714
715 err = ufshcd_init(hba, mmio_base, pdev->irq);
716 if (err) {
717 dev_err(&pdev->dev, "Initialization failed\n");
718 return err;
719 }
720
721 pm_runtime_put_noidle(&pdev->dev);
722 pm_runtime_allow(&pdev->dev);
723
724 return 0;
725 }
726
727 static const struct dev_pm_ops ufshcd_pci_pm_ops = {
728 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
729 #ifdef CONFIG_PM_SLEEP
730 .suspend = ufshcd_system_suspend,
731 .resume = ufshcd_system_resume,
732 .freeze = ufshcd_system_suspend,
733 .thaw = ufshcd_system_resume,
734 .poweroff = ufshcd_system_suspend,
735 .restore = ufshcd_pci_restore,
736 .prepare = ufshcd_pci_suspend_prepare,
737 .complete = ufshcd_pci_resume_complete,
738 #endif
739 };
740
741 static const struct pci_device_id ufshcd_pci_tbl[] = {
742 { PCI_VDEVICE(REDHAT, 0x0013), .driver_data = (kernel_ulong_t)&ufs_qemu_hba_vops },
743 { PCI_VDEVICE(SAMSUNG, 0xC00C), .driver_data = 0 },
744 { PCI_VDEVICE(INTEL, 0x9DFA), .driver_data = (kernel_ulong_t)&ufs_intel_cnl_hba_vops },
745 { PCI_VDEVICE(INTEL, 0x4B41), .driver_data = (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
746 { PCI_VDEVICE(INTEL, 0x4B43), .driver_data = (kernel_ulong_t)&ufs_intel_ehl_hba_vops },
747 { PCI_VDEVICE(INTEL, 0x98FA), .driver_data = (kernel_ulong_t)&ufs_intel_lkf_hba_vops },
748 { PCI_VDEVICE(INTEL, 0x51FF), .driver_data = (kernel_ulong_t)&ufs_intel_adl_hba_vops },
749 { PCI_VDEVICE(INTEL, 0x54FF), .driver_data = (kernel_ulong_t)&ufs_intel_adl_hba_vops },
750 { PCI_VDEVICE(INTEL, 0x7E47), .driver_data = (kernel_ulong_t)&ufs_intel_mtl_hba_vops },
751 { PCI_VDEVICE(INTEL, 0xA847), .driver_data = (kernel_ulong_t)&ufs_intel_mtl_hba_vops },
752 { PCI_VDEVICE(INTEL, 0x7747), .driver_data = (kernel_ulong_t)&ufs_intel_mtl_hba_vops },
753 { PCI_VDEVICE(INTEL, 0xE447), .driver_data = (kernel_ulong_t)&ufs_intel_mtl_hba_vops },
754 { PCI_VDEVICE(INTEL, 0x4D47), .driver_data = (kernel_ulong_t)&ufs_intel_mtl_hba_vops },
755 { PCI_VDEVICE(INTEL, 0xD335), .driver_data = (kernel_ulong_t)&ufs_intel_mtl_hba_vops },
756 { PCI_VDEVICE(AMD, 0x1B29), .driver_data = 0 },
757 { } /* terminate list */
758 };
759
760 MODULE_DEVICE_TABLE(pci, ufshcd_pci_tbl);
761
762 static struct pci_driver ufshcd_pci_driver = {
763 .name = UFSHCD,
764 .id_table = ufshcd_pci_tbl,
765 .probe = ufshcd_pci_probe,
766 .remove = ufshcd_pci_remove,
767 .driver = {
768 .pm = &ufshcd_pci_pm_ops
769 },
770 };
771
772 module_pci_driver(ufshcd_pci_driver);
773
774 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
775 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
776 MODULE_DESCRIPTION("UFS host controller PCI glue driver");
777 MODULE_LICENSE("GPL");
778