1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6 */ 7 8 #include <linux/string_helpers.h> 9 10 #include <drm/drm_print.h> 11 12 #include "g4x_dp.h" 13 #include "intel_audio.h" 14 #include "intel_backlight.h" 15 #include "intel_connector.h" 16 #include "intel_crtc.h" 17 #include "intel_de.h" 18 #include "intel_display_power.h" 19 #include "intel_display_regs.h" 20 #include "intel_display_types.h" 21 #include "intel_display_utils.h" 22 #include "intel_dp.h" 23 #include "intel_dp_aux.h" 24 #include "intel_dp_link_training.h" 25 #include "intel_dp_test.h" 26 #include "intel_dpio_phy.h" 27 #include "intel_encoder.h" 28 #include "intel_fifo_underrun.h" 29 #include "intel_hdmi.h" 30 #include "intel_hotplug.h" 31 #include "intel_pch_display.h" 32 #include "intel_pps.h" 33 34 static const struct dpll g4x_dpll[] = { 35 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, }, 36 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, }, 37 }; 38 39 static const struct dpll pch_dpll[] = { 40 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, }, 41 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, }, 42 }; 43 44 static const struct dpll vlv_dpll[] = { 45 { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, }, 46 { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, }, 47 }; 48 49 static const struct dpll chv_dpll[] = { 50 /* m2 is .22 binary fixed point */ 51 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ }, 52 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ }, 53 }; 54 55 const struct dpll *vlv_get_dpll(struct intel_display *display) 56 { 57 return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0]; 58 } 59 60 static void g4x_dp_set_clock(struct intel_encoder *encoder, 61 struct intel_crtc_state *pipe_config) 62 { 63 struct intel_display *display = to_intel_display(encoder); 64 const struct dpll *divisor = NULL; 65 int i, count = 0; 66 67 if (display->platform.g4x) { 68 divisor = g4x_dpll; 69 count = ARRAY_SIZE(g4x_dpll); 70 } else if (HAS_PCH_SPLIT(display)) { 71 divisor = pch_dpll; 72 count = ARRAY_SIZE(pch_dpll); 73 } else if (display->platform.cherryview) { 74 divisor = chv_dpll; 75 count = ARRAY_SIZE(chv_dpll); 76 } else if (display->platform.valleyview) { 77 divisor = vlv_dpll; 78 count = ARRAY_SIZE(vlv_dpll); 79 } 80 81 if (divisor && count) { 82 for (i = 0; i < count; i++) { 83 if (pipe_config->port_clock == divisor[i].dot) { 84 pipe_config->dpll = divisor[i]; 85 pipe_config->clock_set = true; 86 break; 87 } 88 } 89 } 90 } 91 92 static void intel_dp_prepare(struct intel_encoder *encoder, 93 const struct intel_crtc_state *pipe_config) 94 { 95 struct intel_display *display = to_intel_display(encoder); 96 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 97 enum port port = encoder->port; 98 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 99 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 100 101 intel_dp_set_link_params(intel_dp, 102 pipe_config->port_clock, 103 pipe_config->lane_count); 104 105 /* 106 * There are four kinds of DP registers: 107 * IBX PCH 108 * SNB CPU 109 * IVB CPU 110 * CPT PCH 111 * 112 * IBX PCH and CPU are the same for almost everything, 113 * except that the CPU DP PLL is configured in this 114 * register 115 * 116 * CPT PCH is quite different, having many bits moved 117 * to the TRANS_DP_CTL register instead. That 118 * configuration happens (oddly) in ilk_pch_enable 119 */ 120 121 /* Preserve the BIOS-computed detected bit. This is 122 * supposed to be read-only. 123 */ 124 intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED; 125 126 /* Handle DP bits in common between all three register formats */ 127 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 128 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); 129 130 /* Split out the IBX/CPU vs CPT settings */ 131 132 if (display->platform.ivybridge && port == PORT_A) { 133 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 134 intel_dp->DP |= DP_SYNC_HS_HIGH; 135 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 136 intel_dp->DP |= DP_SYNC_VS_HIGH; 137 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 138 139 if (pipe_config->enhanced_framing) 140 intel_dp->DP |= DP_ENHANCED_FRAMING; 141 142 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); 143 } else if (HAS_PCH_CPT(display) && port != PORT_A) { 144 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 145 146 intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe), 147 TRANS_DP_ENH_FRAMING, 148 pipe_config->enhanced_framing ? 149 TRANS_DP_ENH_FRAMING : 0); 150 } else { 151 if (display->platform.g4x && pipe_config->limited_color_range) 152 intel_dp->DP |= DP_COLOR_RANGE_16_235; 153 154 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 155 intel_dp->DP |= DP_SYNC_HS_HIGH; 156 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 157 intel_dp->DP |= DP_SYNC_VS_HIGH; 158 intel_dp->DP |= DP_LINK_TRAIN_OFF; 159 160 if (pipe_config->enhanced_framing) 161 intel_dp->DP |= DP_ENHANCED_FRAMING; 162 163 if (display->platform.cherryview) 164 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe); 165 else 166 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); 167 } 168 } 169 170 static void assert_dp_port(struct intel_dp *intel_dp, bool state) 171 { 172 struct intel_display *display = to_intel_display(intel_dp); 173 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 174 bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN; 175 176 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 177 "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n", 178 dig_port->base.base.base.id, dig_port->base.base.name, 179 str_on_off(state), str_on_off(cur_state)); 180 } 181 #define assert_dp_port_disabled(d) assert_dp_port((d), false) 182 183 static void assert_edp_pll(struct intel_display *display, bool state) 184 { 185 bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE; 186 187 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 188 "eDP PLL state assertion failure (expected %s, current %s)\n", 189 str_on_off(state), str_on_off(cur_state)); 190 } 191 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) 192 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) 193 194 static void ilk_edp_pll_on(struct intel_dp *intel_dp, 195 const struct intel_crtc_state *pipe_config) 196 { 197 struct intel_display *display = to_intel_display(intel_dp); 198 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 199 200 assert_transcoder_disabled(display, pipe_config->cpu_transcoder); 201 assert_dp_port_disabled(intel_dp); 202 assert_edp_pll_disabled(display); 203 204 drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n", 205 pipe_config->port_clock); 206 207 intel_dp->DP &= ~EDP_PLL_FREQ_MASK; 208 209 if (pipe_config->port_clock == 162000) 210 intel_dp->DP |= EDP_PLL_FREQ_162MHZ; 211 else 212 intel_dp->DP |= EDP_PLL_FREQ_270MHZ; 213 214 intel_de_write(display, DP_A, intel_dp->DP); 215 intel_de_posting_read(display, DP_A); 216 udelay(500); 217 218 /* 219 * [DevILK] Work around required when enabling DP PLL 220 * while a pipe is enabled going to FDI: 221 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI 222 * 2. Program DP PLL enable 223 */ 224 if (display->platform.ironlake) 225 intel_wait_for_vblank_if_active(display, !crtc->pipe); 226 227 intel_dp->DP |= EDP_PLL_ENABLE; 228 229 intel_de_write(display, DP_A, intel_dp->DP); 230 intel_de_posting_read(display, DP_A); 231 udelay(200); 232 } 233 234 static void ilk_edp_pll_off(struct intel_dp *intel_dp, 235 const struct intel_crtc_state *old_crtc_state) 236 { 237 struct intel_display *display = to_intel_display(intel_dp); 238 239 assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder); 240 assert_dp_port_disabled(intel_dp); 241 assert_edp_pll_enabled(display); 242 243 drm_dbg_kms(display->drm, "disabling eDP PLL\n"); 244 245 intel_dp->DP &= ~EDP_PLL_ENABLE; 246 247 intel_de_write(display, DP_A, intel_dp->DP); 248 intel_de_posting_read(display, DP_A); 249 udelay(200); 250 } 251 252 static bool cpt_dp_port_selected(struct intel_display *display, 253 enum port port, enum pipe *pipe) 254 { 255 enum pipe p; 256 257 for_each_pipe(display, p) { 258 u32 val = intel_de_read(display, TRANS_DP_CTL(p)); 259 260 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) { 261 *pipe = p; 262 return true; 263 } 264 } 265 266 drm_dbg_kms(display->drm, "No pipe for DP port %c found\n", 267 port_name(port)); 268 269 /* must initialize pipe to something for the asserts */ 270 *pipe = PIPE_A; 271 272 return false; 273 } 274 275 bool g4x_dp_port_enabled(struct intel_display *display, 276 i915_reg_t dp_reg, enum port port, 277 enum pipe *pipe) 278 { 279 bool ret; 280 u32 val; 281 282 val = intel_de_read(display, dp_reg); 283 284 ret = val & DP_PORT_EN; 285 286 /* asserts want to know the pipe even if the port is disabled */ 287 if (display->platform.ivybridge && port == PORT_A) 288 *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_IVB, val); 289 else if (HAS_PCH_CPT(display) && port != PORT_A) 290 ret &= cpt_dp_port_selected(display, port, pipe); 291 else if (display->platform.cherryview) 292 *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK_CHV, val); 293 else 294 *pipe = REG_FIELD_GET(DP_PIPE_SEL_MASK, val); 295 296 return ret; 297 } 298 299 static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 300 enum pipe *pipe) 301 { 302 struct intel_display *display = to_intel_display(encoder); 303 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 304 struct ref_tracker *wakeref; 305 bool ret; 306 307 wakeref = intel_display_power_get_if_enabled(display, 308 encoder->power_domain); 309 if (!wakeref) 310 return false; 311 312 ret = g4x_dp_port_enabled(display, intel_dp->output_reg, 313 encoder->port, pipe); 314 315 intel_display_power_put(display, encoder->power_domain, wakeref); 316 317 return ret; 318 } 319 320 static void g4x_dp_get_m_n(struct intel_crtc_state *crtc_state) 321 { 322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 323 324 if (crtc_state->has_pch_encoder) { 325 intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n); 326 intel_pch_transcoder_get_m2_n2(crtc, &crtc_state->dp_m2_n2); 327 } else { 328 intel_cpu_transcoder_get_m1_n1(crtc, crtc_state->cpu_transcoder, 329 &crtc_state->dp_m_n); 330 intel_cpu_transcoder_get_m2_n2(crtc, crtc_state->cpu_transcoder, 331 &crtc_state->dp_m2_n2); 332 } 333 } 334 335 static void intel_dp_get_config(struct intel_encoder *encoder, 336 struct intel_crtc_state *pipe_config) 337 { 338 struct intel_display *display = to_intel_display(encoder); 339 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 340 u32 tmp, flags = 0; 341 enum port port = encoder->port; 342 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 343 344 if (encoder->type == INTEL_OUTPUT_EDP) 345 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 346 else 347 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 348 349 tmp = intel_de_read(display, intel_dp->output_reg); 350 351 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; 352 353 if (HAS_PCH_CPT(display) && port != PORT_A) { 354 u32 trans_dp = intel_de_read(display, 355 TRANS_DP_CTL(crtc->pipe)); 356 357 if (trans_dp & TRANS_DP_ENH_FRAMING) 358 pipe_config->enhanced_framing = true; 359 360 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) 361 flags |= DRM_MODE_FLAG_PHSYNC; 362 else 363 flags |= DRM_MODE_FLAG_NHSYNC; 364 365 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) 366 flags |= DRM_MODE_FLAG_PVSYNC; 367 else 368 flags |= DRM_MODE_FLAG_NVSYNC; 369 } else { 370 if (tmp & DP_ENHANCED_FRAMING) 371 pipe_config->enhanced_framing = true; 372 373 if (tmp & DP_SYNC_HS_HIGH) 374 flags |= DRM_MODE_FLAG_PHSYNC; 375 else 376 flags |= DRM_MODE_FLAG_NHSYNC; 377 378 if (tmp & DP_SYNC_VS_HIGH) 379 flags |= DRM_MODE_FLAG_PVSYNC; 380 else 381 flags |= DRM_MODE_FLAG_NVSYNC; 382 } 383 384 pipe_config->hw.adjusted_mode.flags |= flags; 385 386 if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235) 387 pipe_config->limited_color_range = true; 388 389 pipe_config->lane_count = REG_FIELD_GET(DP_PORT_WIDTH_MASK, tmp) + 1; 390 391 g4x_dp_get_m_n(pipe_config); 392 393 if (port == PORT_A) { 394 if ((intel_de_read(display, DP_A) & EDP_PLL_FREQ_MASK) == EDP_PLL_FREQ_162MHZ) 395 pipe_config->port_clock = 162000; 396 else 397 pipe_config->port_clock = 270000; 398 } 399 400 pipe_config->hw.adjusted_mode.crtc_clock = 401 intel_dotclock_calculate(pipe_config->port_clock, 402 &pipe_config->dp_m_n); 403 404 if (intel_dp_is_edp(intel_dp)) 405 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 406 407 intel_audio_codec_get_config(encoder, pipe_config); 408 } 409 410 static void 411 intel_dp_link_down(struct intel_encoder *encoder, 412 const struct intel_crtc_state *old_crtc_state) 413 { 414 struct intel_display *display = to_intel_display(encoder); 415 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 416 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 417 enum port port = encoder->port; 418 419 if (drm_WARN_ON(display->drm, 420 (intel_de_read(display, intel_dp->output_reg) & 421 DP_PORT_EN) == 0)) 422 return; 423 424 drm_dbg_kms(display->drm, "\n"); 425 426 intel_dp->DP &= ~DP_PORT_EN; 427 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 428 intel_de_posting_read(display, intel_dp->output_reg); 429 430 /* 431 * HW workaround for IBX, we need to move the port 432 * to transcoder A after disabling it to allow the 433 * matching HDMI port to be enabled on transcoder A. 434 */ 435 if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B && port != PORT_A) { 436 /* 437 * We get CPU/PCH FIFO underruns on the other pipe when 438 * doing the workaround. Sweep them under the rug. 439 */ 440 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); 441 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 442 443 /* always enable with pattern 1 (as per spec) */ 444 intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK); 445 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | 446 DP_LINK_TRAIN_PAT_1; 447 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 448 intel_de_posting_read(display, intel_dp->output_reg); 449 450 intel_dp->DP &= ~DP_PORT_EN; 451 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 452 intel_de_posting_read(display, intel_dp->output_reg); 453 454 intel_wait_for_vblank_if_active(display, PIPE_A); 455 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); 456 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 457 } 458 459 msleep(intel_dp->pps.panel_power_down_delay); 460 461 if (display->platform.valleyview || display->platform.cherryview) 462 vlv_pps_port_disable(encoder, old_crtc_state); 463 } 464 465 static void g4x_dp_audio_enable(struct intel_encoder *encoder, 466 const struct intel_crtc_state *crtc_state, 467 const struct drm_connector_state *conn_state) 468 { 469 struct intel_display *display = to_intel_display(encoder); 470 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 471 472 if (!crtc_state->has_audio) 473 return; 474 475 /* Enable audio presence detect */ 476 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 477 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 478 479 intel_audio_codec_enable(encoder, crtc_state, conn_state); 480 } 481 482 static void g4x_dp_audio_disable(struct intel_encoder *encoder, 483 const struct intel_crtc_state *old_crtc_state, 484 const struct drm_connector_state *old_conn_state) 485 { 486 struct intel_display *display = to_intel_display(encoder); 487 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 488 489 if (!old_crtc_state->has_audio) 490 return; 491 492 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 493 494 /* Disable audio presence detect */ 495 intel_dp->DP &= ~DP_AUDIO_OUTPUT_ENABLE; 496 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 497 } 498 499 static void intel_disable_dp(struct intel_atomic_state *state, 500 struct intel_encoder *encoder, 501 const struct intel_crtc_state *old_crtc_state, 502 const struct drm_connector_state *old_conn_state) 503 { 504 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 505 506 intel_dp->link.active = false; 507 508 /* 509 * Make sure the panel is off before trying to change the mode. 510 * But also ensure that we have vdd while we switch off the panel. 511 */ 512 intel_pps_vdd_on(intel_dp); 513 intel_edp_backlight_off(old_conn_state); 514 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 515 intel_pps_off(intel_dp); 516 } 517 518 static void g4x_disable_dp(struct intel_atomic_state *state, 519 struct intel_encoder *encoder, 520 const struct intel_crtc_state *old_crtc_state, 521 const struct drm_connector_state *old_conn_state) 522 { 523 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 524 } 525 526 static void vlv_disable_dp(struct intel_atomic_state *state, 527 struct intel_encoder *encoder, 528 const struct intel_crtc_state *old_crtc_state, 529 const struct drm_connector_state *old_conn_state) 530 { 531 intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); 532 } 533 534 static void g4x_post_disable_dp(struct intel_atomic_state *state, 535 struct intel_encoder *encoder, 536 const struct intel_crtc_state *old_crtc_state, 537 const struct drm_connector_state *old_conn_state) 538 { 539 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 540 enum port port = encoder->port; 541 542 /* 543 * Bspec does not list a specific disable sequence for g4x DP. 544 * Follow the ilk+ sequence (disable pipe before the port) for 545 * g4x DP as it does not suffer from underruns like the normal 546 * g4x modeset sequence (disable pipe after the port). 547 */ 548 intel_dp_link_down(encoder, old_crtc_state); 549 550 /* Only ilk+ has port A */ 551 if (port == PORT_A) 552 ilk_edp_pll_off(intel_dp, old_crtc_state); 553 } 554 555 static void vlv_post_disable_dp(struct intel_atomic_state *state, 556 struct intel_encoder *encoder, 557 const struct intel_crtc_state *old_crtc_state, 558 const struct drm_connector_state *old_conn_state) 559 { 560 intel_dp_link_down(encoder, old_crtc_state); 561 } 562 563 static void chv_post_disable_dp(struct intel_atomic_state *state, 564 struct intel_encoder *encoder, 565 const struct intel_crtc_state *old_crtc_state, 566 const struct drm_connector_state *old_conn_state) 567 { 568 intel_dp_link_down(encoder, old_crtc_state); 569 570 /* Assert data lane reset */ 571 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 572 } 573 574 static void 575 cpt_set_link_train(struct intel_dp *intel_dp, 576 const struct intel_crtc_state *crtc_state, 577 u8 dp_train_pat) 578 { 579 struct intel_display *display = to_intel_display(intel_dp); 580 581 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT; 582 583 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 584 case DP_TRAINING_PATTERN_DISABLE: 585 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 586 break; 587 case DP_TRAINING_PATTERN_1: 588 intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT; 589 break; 590 case DP_TRAINING_PATTERN_2: 591 intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT; 592 break; 593 default: 594 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat)); 595 return; 596 } 597 598 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 599 intel_de_posting_read(display, intel_dp->output_reg); 600 } 601 602 static void 603 cpt_set_idle_link_train(struct intel_dp *intel_dp, 604 const struct intel_crtc_state *crtc_state) 605 { 606 struct intel_display *display = to_intel_display(intel_dp); 607 608 intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT; 609 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; 610 611 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 612 intel_de_posting_read(display, intel_dp->output_reg); 613 } 614 615 static void 616 g4x_set_link_train(struct intel_dp *intel_dp, 617 const struct intel_crtc_state *crtc_state, 618 u8 dp_train_pat) 619 { 620 struct intel_display *display = to_intel_display(intel_dp); 621 622 intel_dp->DP &= ~DP_LINK_TRAIN_MASK; 623 624 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 625 case DP_TRAINING_PATTERN_DISABLE: 626 intel_dp->DP |= DP_LINK_TRAIN_OFF; 627 break; 628 case DP_TRAINING_PATTERN_1: 629 intel_dp->DP |= DP_LINK_TRAIN_PAT_1; 630 break; 631 case DP_TRAINING_PATTERN_2: 632 intel_dp->DP |= DP_LINK_TRAIN_PAT_2; 633 break; 634 default: 635 MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat)); 636 return; 637 } 638 639 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 640 intel_de_posting_read(display, intel_dp->output_reg); 641 } 642 643 static void 644 g4x_set_idle_link_train(struct intel_dp *intel_dp, 645 const struct intel_crtc_state *crtc_state) 646 { 647 struct intel_display *display = to_intel_display(intel_dp); 648 649 intel_dp->DP &= ~DP_LINK_TRAIN_MASK; 650 intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE; 651 652 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 653 intel_de_posting_read(display, intel_dp->output_reg); 654 } 655 656 static void intel_dp_enable_port(struct intel_dp *intel_dp, 657 const struct intel_crtc_state *crtc_state) 658 { 659 struct intel_display *display = to_intel_display(intel_dp); 660 661 /* enable with pattern 1 (as per spec) */ 662 663 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 664 DP_PHY_DPRX, DP_TRAINING_PATTERN_1); 665 666 /* 667 * Magic for VLV/CHV. We _must_ first set up the register 668 * without actually enabling the port, and then do another 669 * write to enable the port. Otherwise link training will 670 * fail when the power sequencer is freshly used for this port. 671 */ 672 intel_dp->DP |= DP_PORT_EN; 673 674 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 675 intel_de_posting_read(display, intel_dp->output_reg); 676 } 677 678 static void intel_enable_dp(struct intel_atomic_state *state, 679 struct intel_encoder *encoder, 680 const struct intel_crtc_state *pipe_config, 681 const struct drm_connector_state *conn_state) 682 { 683 struct intel_display *display = to_intel_display(state); 684 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 685 u32 dp_reg = intel_de_read(display, intel_dp->output_reg); 686 687 if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN)) 688 return; 689 690 with_intel_pps_lock(intel_dp) { 691 if (display->platform.valleyview || display->platform.cherryview) 692 vlv_pps_port_enable_unlocked(encoder, pipe_config); 693 694 intel_dp_enable_port(intel_dp, pipe_config); 695 696 intel_pps_vdd_on_unlocked(intel_dp); 697 intel_pps_on_unlocked(intel_dp); 698 intel_pps_vdd_off_unlocked(intel_dp, true); 699 } 700 701 if (display->platform.valleyview || display->platform.cherryview) { 702 unsigned int lane_mask = 0x0; 703 704 if (display->platform.cherryview) 705 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); 706 707 vlv_wait_port_ready(encoder, lane_mask); 708 } 709 710 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 711 intel_dp_configure_protocol_converter(intel_dp, pipe_config); 712 intel_dp_check_frl_training(intel_dp); 713 intel_dp_pcon_dsc_configure(intel_dp, pipe_config); 714 intel_dp_start_link_train(state, intel_dp, pipe_config); 715 intel_dp_stop_link_train(intel_dp, pipe_config); 716 } 717 718 static void g4x_enable_dp(struct intel_atomic_state *state, 719 struct intel_encoder *encoder, 720 const struct intel_crtc_state *pipe_config, 721 const struct drm_connector_state *conn_state) 722 { 723 intel_enable_dp(state, encoder, pipe_config, conn_state); 724 intel_edp_backlight_on(pipe_config, conn_state); 725 } 726 727 static void vlv_enable_dp(struct intel_atomic_state *state, 728 struct intel_encoder *encoder, 729 const struct intel_crtc_state *pipe_config, 730 const struct drm_connector_state *conn_state) 731 { 732 intel_edp_backlight_on(pipe_config, conn_state); 733 } 734 735 static void g4x_pre_enable_dp(struct intel_atomic_state *state, 736 struct intel_encoder *encoder, 737 const struct intel_crtc_state *pipe_config, 738 const struct drm_connector_state *conn_state) 739 { 740 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 741 enum port port = encoder->port; 742 743 intel_dp_prepare(encoder, pipe_config); 744 745 /* Only ilk+ has port A */ 746 if (port == PORT_A) 747 ilk_edp_pll_on(intel_dp, pipe_config); 748 } 749 750 static void vlv_pre_enable_dp(struct intel_atomic_state *state, 751 struct intel_encoder *encoder, 752 const struct intel_crtc_state *pipe_config, 753 const struct drm_connector_state *conn_state) 754 { 755 vlv_phy_pre_encoder_enable(encoder, pipe_config); 756 757 intel_enable_dp(state, encoder, pipe_config, conn_state); 758 } 759 760 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state, 761 struct intel_encoder *encoder, 762 const struct intel_crtc_state *pipe_config, 763 const struct drm_connector_state *conn_state) 764 { 765 intel_dp_prepare(encoder, pipe_config); 766 767 vlv_phy_pre_pll_enable(encoder, pipe_config); 768 } 769 770 static void chv_pre_enable_dp(struct intel_atomic_state *state, 771 struct intel_encoder *encoder, 772 const struct intel_crtc_state *pipe_config, 773 const struct drm_connector_state *conn_state) 774 { 775 chv_phy_pre_encoder_enable(encoder, pipe_config); 776 777 intel_enable_dp(state, encoder, pipe_config, conn_state); 778 779 /* Second common lane will stay alive on its own now */ 780 chv_phy_release_cl2_override(encoder); 781 } 782 783 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state, 784 struct intel_encoder *encoder, 785 const struct intel_crtc_state *pipe_config, 786 const struct drm_connector_state *conn_state) 787 { 788 intel_dp_prepare(encoder, pipe_config); 789 790 chv_phy_pre_pll_enable(encoder, pipe_config); 791 } 792 793 static void chv_dp_post_pll_disable(struct intel_atomic_state *state, 794 struct intel_encoder *encoder, 795 const struct intel_crtc_state *old_crtc_state, 796 const struct drm_connector_state *old_conn_state) 797 { 798 chv_phy_post_pll_disable(encoder, old_crtc_state); 799 } 800 801 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp, 802 const struct intel_crtc_state *crtc_state) 803 { 804 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 805 } 806 807 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp, 808 const struct intel_crtc_state *crtc_state) 809 { 810 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 811 } 812 813 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp) 814 { 815 return DP_TRAIN_PRE_EMPH_LEVEL_2; 816 } 817 818 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp) 819 { 820 return DP_TRAIN_PRE_EMPH_LEVEL_3; 821 } 822 823 static void vlv_set_signal_levels(struct intel_encoder *encoder, 824 const struct intel_crtc_state *crtc_state) 825 { 826 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 827 unsigned long demph_reg_value, preemph_reg_value, 828 uniqtranscale_reg_value; 829 u8 train_set = intel_dp->train_set[0]; 830 831 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 832 case DP_TRAIN_PRE_EMPH_LEVEL_0: 833 preemph_reg_value = 0x0004000; 834 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 835 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 836 demph_reg_value = 0x2B405555; 837 uniqtranscale_reg_value = 0x552AB83A; 838 break; 839 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 840 demph_reg_value = 0x2B404040; 841 uniqtranscale_reg_value = 0x5548B83A; 842 break; 843 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 844 demph_reg_value = 0x2B245555; 845 uniqtranscale_reg_value = 0x5560B83A; 846 break; 847 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 848 demph_reg_value = 0x2B405555; 849 uniqtranscale_reg_value = 0x5598DA3A; 850 break; 851 default: 852 return; 853 } 854 break; 855 case DP_TRAIN_PRE_EMPH_LEVEL_1: 856 preemph_reg_value = 0x0002000; 857 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 858 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 859 demph_reg_value = 0x2B404040; 860 uniqtranscale_reg_value = 0x5552B83A; 861 break; 862 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 863 demph_reg_value = 0x2B404848; 864 uniqtranscale_reg_value = 0x5580B83A; 865 break; 866 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 867 demph_reg_value = 0x2B404040; 868 uniqtranscale_reg_value = 0x55ADDA3A; 869 break; 870 default: 871 return; 872 } 873 break; 874 case DP_TRAIN_PRE_EMPH_LEVEL_2: 875 preemph_reg_value = 0x0000000; 876 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 877 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 878 demph_reg_value = 0x2B305555; 879 uniqtranscale_reg_value = 0x5570B83A; 880 break; 881 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 882 demph_reg_value = 0x2B2B4040; 883 uniqtranscale_reg_value = 0x55ADDA3A; 884 break; 885 default: 886 return; 887 } 888 break; 889 case DP_TRAIN_PRE_EMPH_LEVEL_3: 890 preemph_reg_value = 0x0006000; 891 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 892 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 893 demph_reg_value = 0x1B405555; 894 uniqtranscale_reg_value = 0x55ADDA3A; 895 break; 896 default: 897 return; 898 } 899 break; 900 default: 901 return; 902 } 903 904 vlv_set_phy_signal_level(encoder, crtc_state, 905 demph_reg_value, preemph_reg_value, 906 uniqtranscale_reg_value, 0); 907 } 908 909 static void chv_set_signal_levels(struct intel_encoder *encoder, 910 const struct intel_crtc_state *crtc_state) 911 { 912 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 913 u32 deemph_reg_value, margin_reg_value; 914 bool uniq_trans_scale = false; 915 u8 train_set = intel_dp->train_set[0]; 916 917 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 918 case DP_TRAIN_PRE_EMPH_LEVEL_0: 919 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 920 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 921 deemph_reg_value = 128; 922 margin_reg_value = 52; 923 break; 924 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 925 deemph_reg_value = 128; 926 margin_reg_value = 77; 927 break; 928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 929 deemph_reg_value = 128; 930 margin_reg_value = 102; 931 break; 932 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 933 deemph_reg_value = 128; 934 margin_reg_value = 154; 935 uniq_trans_scale = true; 936 break; 937 default: 938 return; 939 } 940 break; 941 case DP_TRAIN_PRE_EMPH_LEVEL_1: 942 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 944 deemph_reg_value = 85; 945 margin_reg_value = 78; 946 break; 947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 948 deemph_reg_value = 85; 949 margin_reg_value = 116; 950 break; 951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 952 deemph_reg_value = 85; 953 margin_reg_value = 154; 954 break; 955 default: 956 return; 957 } 958 break; 959 case DP_TRAIN_PRE_EMPH_LEVEL_2: 960 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 962 deemph_reg_value = 64; 963 margin_reg_value = 104; 964 break; 965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 966 deemph_reg_value = 64; 967 margin_reg_value = 154; 968 break; 969 default: 970 return; 971 } 972 break; 973 case DP_TRAIN_PRE_EMPH_LEVEL_3: 974 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 975 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 976 deemph_reg_value = 43; 977 margin_reg_value = 154; 978 break; 979 default: 980 return; 981 } 982 break; 983 default: 984 return; 985 } 986 987 chv_set_phy_signal_level(encoder, crtc_state, 988 deemph_reg_value, margin_reg_value, 989 uniq_trans_scale); 990 } 991 992 static u32 g4x_signal_levels(u8 train_set) 993 { 994 u32 signal_levels = 0; 995 996 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 998 default: 999 signal_levels |= DP_VOLTAGE_0_4; 1000 break; 1001 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 1002 signal_levels |= DP_VOLTAGE_0_6; 1003 break; 1004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 1005 signal_levels |= DP_VOLTAGE_0_8; 1006 break; 1007 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 1008 signal_levels |= DP_VOLTAGE_1_2; 1009 break; 1010 } 1011 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 1012 case DP_TRAIN_PRE_EMPH_LEVEL_0: 1013 default: 1014 signal_levels |= DP_PRE_EMPHASIS_0; 1015 break; 1016 case DP_TRAIN_PRE_EMPH_LEVEL_1: 1017 signal_levels |= DP_PRE_EMPHASIS_3_5; 1018 break; 1019 case DP_TRAIN_PRE_EMPH_LEVEL_2: 1020 signal_levels |= DP_PRE_EMPHASIS_6; 1021 break; 1022 case DP_TRAIN_PRE_EMPH_LEVEL_3: 1023 signal_levels |= DP_PRE_EMPHASIS_9_5; 1024 break; 1025 } 1026 return signal_levels; 1027 } 1028 1029 static void 1030 g4x_set_signal_levels(struct intel_encoder *encoder, 1031 const struct intel_crtc_state *crtc_state) 1032 { 1033 struct intel_display *display = to_intel_display(encoder); 1034 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1035 u8 train_set = intel_dp->train_set[0]; 1036 u32 signal_levels; 1037 1038 signal_levels = g4x_signal_levels(train_set); 1039 1040 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1041 signal_levels); 1042 1043 intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK); 1044 intel_dp->DP |= signal_levels; 1045 1046 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 1047 intel_de_posting_read(display, intel_dp->output_reg); 1048 } 1049 1050 /* SNB CPU eDP voltage swing and pre-emphasis control */ 1051 static u32 snb_cpu_edp_signal_levels(u8 train_set) 1052 { 1053 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1054 DP_TRAIN_PRE_EMPHASIS_MASK); 1055 1056 switch (signal_levels) { 1057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1059 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1061 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1062 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1064 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1065 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1066 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1067 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1069 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1070 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1071 default: 1072 MISSING_CASE(signal_levels); 1073 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1074 } 1075 } 1076 1077 static void 1078 snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder, 1079 const struct intel_crtc_state *crtc_state) 1080 { 1081 struct intel_display *display = to_intel_display(encoder); 1082 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1083 u8 train_set = intel_dp->train_set[0]; 1084 u32 signal_levels; 1085 1086 signal_levels = snb_cpu_edp_signal_levels(train_set); 1087 1088 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1089 signal_levels); 1090 1091 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 1092 intel_dp->DP |= signal_levels; 1093 1094 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 1095 intel_de_posting_read(display, intel_dp->output_reg); 1096 } 1097 1098 /* IVB CPU eDP voltage swing and pre-emphasis control */ 1099 static u32 ivb_cpu_edp_signal_levels(u8 train_set) 1100 { 1101 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1102 DP_TRAIN_PRE_EMPHASIS_MASK); 1103 1104 switch (signal_levels) { 1105 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1106 return EDP_LINK_TRAIN_400MV_0DB_IVB; 1107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1108 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 1109 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 1111 return EDP_LINK_TRAIN_400MV_6DB_IVB; 1112 1113 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1114 return EDP_LINK_TRAIN_600MV_0DB_IVB; 1115 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1116 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 1117 1118 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 1119 return EDP_LINK_TRAIN_800MV_0DB_IVB; 1120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 1121 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 1122 1123 default: 1124 MISSING_CASE(signal_levels); 1125 return EDP_LINK_TRAIN_500MV_0DB_IVB; 1126 } 1127 } 1128 1129 static void 1130 ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder, 1131 const struct intel_crtc_state *crtc_state) 1132 { 1133 struct intel_display *display = to_intel_display(encoder); 1134 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1135 u8 train_set = intel_dp->train_set[0]; 1136 u32 signal_levels; 1137 1138 signal_levels = ivb_cpu_edp_signal_levels(train_set); 1139 1140 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1141 signal_levels); 1142 1143 intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 1144 intel_dp->DP |= signal_levels; 1145 1146 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); 1147 intel_de_posting_read(display, intel_dp->output_reg); 1148 } 1149 1150 /* 1151 * If display is now connected check links status, 1152 * there has been known issues of link loss triggering 1153 * long pulse. 1154 * 1155 * Some sinks (eg. ASUS PB287Q) seem to perform some 1156 * weird HPD ping pong during modesets. So we can apparently 1157 * end up with HPD going low during a modeset, and then 1158 * going back up soon after. And once that happens we must 1159 * retrain the link to get a picture. That's in case no 1160 * userspace component reacted to intermittent HPD dip. 1161 */ 1162 static enum intel_hotplug_state 1163 intel_dp_hotplug(struct intel_encoder *encoder, 1164 struct intel_connector *connector) 1165 { 1166 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1167 enum intel_hotplug_state state; 1168 1169 if (intel_dp_test_phy(intel_dp)) 1170 return INTEL_HOTPLUG_UNCHANGED; 1171 1172 state = intel_encoder_hotplug(encoder, connector); 1173 1174 intel_dp_check_link_state(intel_dp); 1175 1176 /* 1177 * Keeping it consistent with intel_ddi_hotplug() and 1178 * intel_hdmi_hotplug(). 1179 */ 1180 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 1181 state = INTEL_HOTPLUG_RETRY; 1182 1183 return state; 1184 } 1185 1186 static bool ibx_digital_port_connected(struct intel_encoder *encoder) 1187 { 1188 struct intel_display *display = to_intel_display(encoder); 1189 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 1190 1191 return intel_de_read(display, SDEISR) & bit; 1192 } 1193 1194 static bool g4x_digital_port_connected(struct intel_encoder *encoder) 1195 { 1196 struct intel_display *display = to_intel_display(encoder); 1197 u32 bit; 1198 1199 switch (encoder->hpd_pin) { 1200 case HPD_PORT_B: 1201 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 1202 break; 1203 case HPD_PORT_C: 1204 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 1205 break; 1206 case HPD_PORT_D: 1207 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 1208 break; 1209 default: 1210 MISSING_CASE(encoder->hpd_pin); 1211 return false; 1212 } 1213 1214 return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit; 1215 } 1216 1217 static bool ilk_digital_port_connected(struct intel_encoder *encoder) 1218 { 1219 struct intel_display *display = to_intel_display(encoder); 1220 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 1221 1222 return intel_de_read(display, DEISR) & bit; 1223 } 1224 1225 static int g4x_dp_compute_config(struct intel_encoder *encoder, 1226 struct intel_crtc_state *crtc_state, 1227 struct drm_connector_state *conn_state) 1228 { 1229 struct intel_display *display = to_intel_display(encoder); 1230 int ret; 1231 1232 if (HAS_PCH_SPLIT(display) && encoder->port != PORT_A) 1233 crtc_state->has_pch_encoder = true; 1234 1235 ret = intel_dp_compute_config(encoder, crtc_state, conn_state); 1236 if (ret) 1237 return ret; 1238 1239 g4x_dp_set_clock(encoder, crtc_state); 1240 1241 return 0; 1242 } 1243 1244 static void g4x_dp_suspend_complete(struct intel_encoder *encoder) 1245 { 1246 /* 1247 * TODO: Move this to intel_dp_encoder_suspend(), 1248 * once modeset locking around that is removed. 1249 */ 1250 intel_encoder_link_check_flush_work(encoder); 1251 } 1252 1253 static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 1254 { 1255 intel_dp_encoder_flush_work(encoder); 1256 1257 drm_encoder_cleanup(encoder); 1258 kfree(enc_to_dig_port(to_intel_encoder(encoder))); 1259 } 1260 1261 static void intel_dp_encoder_reset(struct drm_encoder *encoder) 1262 { 1263 struct intel_display *display = to_intel_display(encoder->dev); 1264 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 1265 1266 intel_dp->DP = intel_de_read(display, intel_dp->output_reg); 1267 1268 intel_dp->reset_link_params = true; 1269 intel_dp_invalidate_source_oui(intel_dp); 1270 1271 if (display->platform.valleyview || display->platform.cherryview) 1272 vlv_pps_pipe_reset(intel_dp); 1273 1274 intel_pps_encoder_reset(intel_dp); 1275 } 1276 1277 static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1278 .reset = intel_dp_encoder_reset, 1279 .destroy = intel_dp_encoder_destroy, 1280 }; 1281 1282 bool g4x_dp_init(struct intel_display *display, 1283 i915_reg_t output_reg, enum port port) 1284 { 1285 const struct intel_bios_encoder_data *devdata; 1286 struct intel_digital_port *dig_port; 1287 struct intel_encoder *intel_encoder; 1288 struct drm_encoder *encoder; 1289 struct intel_connector *intel_connector; 1290 1291 if (!assert_port_valid(display, port)) 1292 return false; 1293 1294 devdata = intel_bios_encoder_data_lookup(display, port); 1295 1296 /* FIXME bail? */ 1297 if (!devdata) 1298 drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n", 1299 port_name(port)); 1300 1301 dig_port = intel_dig_port_alloc(); 1302 if (!dig_port) 1303 return false; 1304 1305 intel_connector = intel_connector_alloc(); 1306 if (!intel_connector) 1307 goto err_connector_alloc; 1308 1309 intel_encoder = &dig_port->base; 1310 encoder = &intel_encoder->base; 1311 1312 intel_encoder->devdata = devdata; 1313 1314 if (drm_encoder_init(display->drm, &intel_encoder->base, 1315 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, 1316 "DP %c", port_name(port))) 1317 goto err_encoder_init; 1318 1319 intel_encoder_link_check_init(intel_encoder, intel_dp_link_check); 1320 1321 intel_encoder->hotplug = intel_dp_hotplug; 1322 intel_encoder->compute_config = g4x_dp_compute_config; 1323 intel_encoder->get_hw_state = intel_dp_get_hw_state; 1324 intel_encoder->get_config = intel_dp_get_config; 1325 intel_encoder->sync_state = intel_dp_sync_state; 1326 intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check; 1327 intel_encoder->update_pipe = intel_backlight_update; 1328 intel_encoder->suspend = intel_dp_encoder_suspend; 1329 intel_encoder->suspend_complete = g4x_dp_suspend_complete; 1330 intel_encoder->shutdown = intel_dp_encoder_shutdown; 1331 if (display->platform.cherryview) { 1332 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 1333 intel_encoder->pre_enable = chv_pre_enable_dp; 1334 intel_encoder->enable = vlv_enable_dp; 1335 intel_encoder->disable = vlv_disable_dp; 1336 intel_encoder->post_disable = chv_post_disable_dp; 1337 intel_encoder->post_pll_disable = chv_dp_post_pll_disable; 1338 } else if (display->platform.valleyview) { 1339 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 1340 intel_encoder->pre_enable = vlv_pre_enable_dp; 1341 intel_encoder->enable = vlv_enable_dp; 1342 intel_encoder->disable = vlv_disable_dp; 1343 intel_encoder->post_disable = vlv_post_disable_dp; 1344 } else { 1345 intel_encoder->pre_enable = g4x_pre_enable_dp; 1346 intel_encoder->enable = g4x_enable_dp; 1347 intel_encoder->disable = g4x_disable_dp; 1348 intel_encoder->post_disable = g4x_post_disable_dp; 1349 } 1350 intel_encoder->audio_enable = g4x_dp_audio_enable; 1351 intel_encoder->audio_disable = g4x_dp_audio_disable; 1352 1353 if ((display->platform.ivybridge && port == PORT_A) || 1354 (HAS_PCH_CPT(display) && port != PORT_A)) { 1355 dig_port->dp.set_link_train = cpt_set_link_train; 1356 dig_port->dp.set_idle_link_train = cpt_set_idle_link_train; 1357 } else { 1358 dig_port->dp.set_link_train = g4x_set_link_train; 1359 dig_port->dp.set_idle_link_train = g4x_set_idle_link_train; 1360 } 1361 1362 if (display->platform.cherryview) 1363 intel_encoder->set_signal_levels = chv_set_signal_levels; 1364 else if (display->platform.valleyview) 1365 intel_encoder->set_signal_levels = vlv_set_signal_levels; 1366 else if (display->platform.ivybridge && port == PORT_A) 1367 intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels; 1368 else if (display->platform.sandybridge && port == PORT_A) 1369 intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels; 1370 else 1371 intel_encoder->set_signal_levels = g4x_set_signal_levels; 1372 1373 if (display->platform.valleyview || display->platform.cherryview || 1374 (HAS_PCH_SPLIT(display) && port != PORT_A)) { 1375 dig_port->dp.preemph_max = intel_dp_preemph_max_3; 1376 dig_port->dp.voltage_max = intel_dp_voltage_max_3; 1377 } else { 1378 dig_port->dp.preemph_max = intel_dp_preemph_max_2; 1379 dig_port->dp.voltage_max = intel_dp_voltage_max_2; 1380 } 1381 1382 dig_port->dp.output_reg = output_reg; 1383 1384 intel_encoder->type = INTEL_OUTPUT_DP; 1385 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 1386 if (display->platform.cherryview) { 1387 if (port == PORT_D) 1388 intel_encoder->pipe_mask = BIT(PIPE_C); 1389 else 1390 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 1391 } else { 1392 intel_encoder->pipe_mask = ~0; 1393 } 1394 intel_encoder->cloneable = 0; 1395 intel_encoder->port = port; 1396 intel_encoder->hpd_pin = intel_hpd_pin_default(port); 1397 1398 dig_port->hpd_pulse = intel_dp_hpd_pulse; 1399 1400 if (HAS_GMCH(display)) { 1401 dig_port->connected = g4x_digital_port_connected; 1402 } else { 1403 if (port == PORT_A) 1404 dig_port->connected = ilk_digital_port_connected; 1405 else 1406 dig_port->connected = ibx_digital_port_connected; 1407 } 1408 1409 if (port != PORT_A) 1410 intel_infoframe_init(dig_port); 1411 1412 dig_port->aux_ch = intel_dp_aux_ch(intel_encoder); 1413 if (dig_port->aux_ch == AUX_CH_NONE) 1414 goto err_init_connector; 1415 1416 if (!intel_dp_init_connector(dig_port, intel_connector)) 1417 goto err_init_connector; 1418 1419 return true; 1420 1421 err_init_connector: 1422 drm_encoder_cleanup(encoder); 1423 err_encoder_init: 1424 kfree(intel_connector); 1425 err_connector_alloc: 1426 kfree(dig_port); 1427 return false; 1428 } 1429