1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #ifndef __INTEL_DE_H__
7 #define __INTEL_DE_H__
8
9 #include "intel_display_conversion.h"
10 #include "intel_display_core.h"
11 #include "intel_dmc_wl.h"
12 #include "intel_dsb.h"
13 #include "intel_uncore.h"
14 #include "intel_uncore_trace.h"
15
__to_uncore(struct intel_display * display)16 static inline struct intel_uncore *__to_uncore(struct intel_display *display)
17 {
18 return to_intel_uncore(display->drm);
19 }
20
21 static inline u32
__intel_de_read(struct intel_display * display,i915_reg_t reg)22 __intel_de_read(struct intel_display *display, i915_reg_t reg)
23 {
24 u32 val;
25
26 intel_dmc_wl_get(display, reg);
27
28 val = intel_uncore_read(__to_uncore(display), reg);
29
30 intel_dmc_wl_put(display, reg);
31
32 return val;
33 }
34 #define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), __VA_ARGS__)
35
36 static inline u8
intel_de_read8(struct intel_display * display,i915_reg_t reg)37 intel_de_read8(struct intel_display *display, i915_reg_t reg)
38 {
39 u8 val;
40
41 intel_dmc_wl_get(display, reg);
42
43 val = intel_uncore_read8(__to_uncore(display), reg);
44
45 intel_dmc_wl_put(display, reg);
46
47 return val;
48 }
49
50 static inline u64
intel_de_read64_2x32(struct intel_display * display,i915_reg_t lower_reg,i915_reg_t upper_reg)51 intel_de_read64_2x32(struct intel_display *display,
52 i915_reg_t lower_reg, i915_reg_t upper_reg)
53 {
54 u64 val;
55
56 intel_dmc_wl_get(display, lower_reg);
57 intel_dmc_wl_get(display, upper_reg);
58
59 val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg,
60 upper_reg);
61
62 intel_dmc_wl_put(display, upper_reg);
63 intel_dmc_wl_put(display, lower_reg);
64
65 return val;
66 }
67
68 static inline void
__intel_de_posting_read(struct intel_display * display,i915_reg_t reg)69 __intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
70 {
71 intel_dmc_wl_get(display, reg);
72
73 intel_uncore_posting_read(__to_uncore(display), reg);
74
75 intel_dmc_wl_put(display, reg);
76 }
77 #define intel_de_posting_read(p,...) __intel_de_posting_read(__to_intel_display(p), __VA_ARGS__)
78
79 static inline void
__intel_de_write(struct intel_display * display,i915_reg_t reg,u32 val)80 __intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
81 {
82 intel_dmc_wl_get(display, reg);
83
84 intel_uncore_write(__to_uncore(display), reg, val);
85
86 intel_dmc_wl_put(display, reg);
87 }
88 #define intel_de_write(p,...) __intel_de_write(__to_intel_display(p), __VA_ARGS__)
89
90 static inline u32
__intel_de_rmw_nowl(struct intel_display * display,i915_reg_t reg,u32 clear,u32 set)91 __intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
92 u32 clear, u32 set)
93 {
94 return intel_uncore_rmw(__to_uncore(display), reg, clear, set);
95 }
96
97 static inline u32
__intel_de_rmw(struct intel_display * display,i915_reg_t reg,u32 clear,u32 set)98 __intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear,
99 u32 set)
100 {
101 u32 val;
102
103 intel_dmc_wl_get(display, reg);
104
105 val = __intel_de_rmw_nowl(display, reg, clear, set);
106
107 intel_dmc_wl_put(display, reg);
108
109 return val;
110 }
111 #define intel_de_rmw(p,...) __intel_de_rmw(__to_intel_display(p), __VA_ARGS__)
112
113 static inline int
__intel_de_wait_for_register_nowl(struct intel_display * display,i915_reg_t reg,u32 mask,u32 value,unsigned int timeout)114 __intel_de_wait_for_register_nowl(struct intel_display *display,
115 i915_reg_t reg,
116 u32 mask, u32 value, unsigned int timeout)
117 {
118 return intel_wait_for_register(__to_uncore(display), reg, mask,
119 value, timeout);
120 }
121
122 static inline int
__intel_de_wait_for_register_atomic_nowl(struct intel_display * display,i915_reg_t reg,u32 mask,u32 value,unsigned int fast_timeout_us)123 __intel_de_wait_for_register_atomic_nowl(struct intel_display *display,
124 i915_reg_t reg,
125 u32 mask, u32 value,
126 unsigned int fast_timeout_us)
127 {
128 return __intel_wait_for_register(__to_uncore(display), reg, mask,
129 value, fast_timeout_us, 0, NULL);
130 }
131
132 static inline int
intel_de_wait(struct intel_display * display,i915_reg_t reg,u32 mask,u32 value,unsigned int timeout)133 intel_de_wait(struct intel_display *display, i915_reg_t reg,
134 u32 mask, u32 value, unsigned int timeout)
135 {
136 int ret;
137
138 intel_dmc_wl_get(display, reg);
139
140 ret = __intel_de_wait_for_register_nowl(display, reg, mask, value,
141 timeout);
142
143 intel_dmc_wl_put(display, reg);
144
145 return ret;
146 }
147
148 static inline int
intel_de_wait_fw(struct intel_display * display,i915_reg_t reg,u32 mask,u32 value,unsigned int timeout)149 intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
150 u32 mask, u32 value, unsigned int timeout)
151 {
152 int ret;
153
154 intel_dmc_wl_get(display, reg);
155
156 ret = intel_wait_for_register_fw(__to_uncore(display), reg, mask,
157 value, timeout);
158
159 intel_dmc_wl_put(display, reg);
160
161 return ret;
162 }
163
164 static inline int
intel_de_wait_custom(struct intel_display * display,i915_reg_t reg,u32 mask,u32 value,unsigned int fast_timeout_us,unsigned int slow_timeout_ms,u32 * out_value)165 intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
166 u32 mask, u32 value,
167 unsigned int fast_timeout_us,
168 unsigned int slow_timeout_ms, u32 *out_value)
169 {
170 int ret;
171
172 intel_dmc_wl_get(display, reg);
173
174 ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
175 value,
176 fast_timeout_us, slow_timeout_ms, out_value);
177
178 intel_dmc_wl_put(display, reg);
179
180 return ret;
181 }
182
183 static inline int
__intel_de_wait_for_set(struct intel_display * display,i915_reg_t reg,u32 mask,unsigned int timeout)184 __intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
185 u32 mask, unsigned int timeout)
186 {
187 return intel_de_wait(display, reg, mask, mask, timeout);
188 }
189 #define intel_de_wait_for_set(p,...) __intel_de_wait_for_set(__to_intel_display(p), __VA_ARGS__)
190
191 static inline int
__intel_de_wait_for_clear(struct intel_display * display,i915_reg_t reg,u32 mask,unsigned int timeout)192 __intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg,
193 u32 mask, unsigned int timeout)
194 {
195 return intel_de_wait(display, reg, mask, 0, timeout);
196 }
197 #define intel_de_wait_for_clear(p,...) __intel_de_wait_for_clear(__to_intel_display(p), __VA_ARGS__)
198
199 /*
200 * Unlocked mmio-accessors, think carefully before using these.
201 *
202 * Certain architectures will die if the same cacheline is concurrently accessed
203 * by different clients (e.g. on Ivybridge). Access to registers should
204 * therefore generally be serialised, by either the dev_priv->uncore.lock or
205 * a more localised lock guarding all access to that bank of registers.
206 */
207 static inline u32
__intel_de_read_fw(struct intel_display * display,i915_reg_t reg)208 __intel_de_read_fw(struct intel_display *display, i915_reg_t reg)
209 {
210 u32 val;
211
212 val = intel_uncore_read_fw(__to_uncore(display), reg);
213 trace_i915_reg_rw(false, reg, val, sizeof(val), true);
214
215 return val;
216 }
217 #define intel_de_read_fw(p,...) __intel_de_read_fw(__to_intel_display(p), __VA_ARGS__)
218
219 static inline void
__intel_de_write_fw(struct intel_display * display,i915_reg_t reg,u32 val)220 __intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
221 {
222 trace_i915_reg_rw(true, reg, val, sizeof(val), true);
223 intel_uncore_write_fw(__to_uncore(display), reg, val);
224 }
225 #define intel_de_write_fw(p,...) __intel_de_write_fw(__to_intel_display(p), __VA_ARGS__)
226
227 static inline u32
intel_de_read_notrace(struct intel_display * display,i915_reg_t reg)228 intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
229 {
230 return intel_uncore_read_notrace(__to_uncore(display), reg);
231 }
232
233 static inline void
intel_de_write_notrace(struct intel_display * display,i915_reg_t reg,u32 val)234 intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)
235 {
236 intel_uncore_write_notrace(__to_uncore(display), reg, val);
237 }
238
239 static __always_inline void
intel_de_write_dsb(struct intel_display * display,struct intel_dsb * dsb,i915_reg_t reg,u32 val)240 intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
241 i915_reg_t reg, u32 val)
242 {
243 if (dsb)
244 intel_dsb_reg_write(dsb, reg, val);
245 else
246 intel_de_write_fw(display, reg, val);
247 }
248
249 #endif /* __INTEL_DE_H__ */
250