1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2023 Cai Huoqing 4 * Synopsys DesignWare HDMA v0 reg 5 * 6 * Author: Cai Huoqing <cai.huoqing@linux.dev> 7 */ 8 9 #ifndef _DW_HDMA_V0_REGS_H 10 #define _DW_HDMA_V0_REGS_H 11 12 #include <linux/dmaengine.h> 13 14 #define HDMA_V0_MAX_NR_CH 64 15 #define HDMA_V0_CH_EN BIT(0) 16 #define HDMA_V0_LOCAL_ABORT_INT_EN BIT(6) 17 #define HDMA_V0_REMOTE_ABORT_INT_EN BIT(5) 18 #define HDMA_V0_LOCAL_STOP_INT_EN BIT(4) 19 #define HDMA_V0_REMOTE_STOP_INT_EN BIT(3) 20 #define HDMA_V0_ABORT_INT_MASK BIT(2) 21 #define HDMA_V0_STOP_INT_MASK BIT(0) 22 #define HDMA_V0_LINKLIST_EN BIT(0) 23 #define HDMA_V0_CONSUMER_CYCLE_STAT BIT(1) 24 #define HDMA_V0_CONSUMER_CYCLE_BIT BIT(0) 25 #define HDMA_V0_DOORBELL_START BIT(0) 26 #define HDMA_V0_CH_STATUS_MASK GENMASK(1, 0) 27 #define HDMA_V0_FUNC_NUM_PF_MASK GENMASK(7, 0) 28 29 struct dw_hdma_v0_ch_regs { 30 u32 ch_en; /* 0x0000 */ 31 u32 doorbell; /* 0x0004 */ 32 u32 prefetch; /* 0x0008 */ 33 u32 handshake; /* 0x000c */ 34 union { 35 u64 reg; /* 0x0010..0x0014 */ 36 struct { 37 u32 lsb; /* 0x0010 */ 38 u32 msb; /* 0x0014 */ 39 }; 40 } llp; 41 u32 cycle_sync; /* 0x0018 */ 42 u32 transfer_size; /* 0x001c */ 43 union { 44 u64 reg; /* 0x0020..0x0024 */ 45 struct { 46 u32 lsb; /* 0x0020 */ 47 u32 msb; /* 0x0024 */ 48 }; 49 } sar; 50 union { 51 u64 reg; /* 0x0028..0x002c */ 52 struct { 53 u32 lsb; /* 0x0028 */ 54 u32 msb; /* 0x002c */ 55 }; 56 } dar; 57 u32 watermark_en; /* 0x0030 */ 58 u32 control1; /* 0x0034 */ 59 u32 func_num; /* 0x0038 */ 60 u32 qos; /* 0x003c */ 61 u32 padding_1[16]; /* 0x0040..0x007c */ 62 u32 ch_stat; /* 0x0080 */ 63 u32 int_stat; /* 0x0084 */ 64 u32 int_setup; /* 0x0088 */ 65 u32 int_clear; /* 0x008c */ 66 union { 67 u64 reg; /* 0x0090..0x0094 */ 68 struct { 69 u32 lsb; /* 0x0090 */ 70 u32 msb; /* 0x0094 */ 71 }; 72 } msi_stop; 73 union { 74 u64 reg; /* 0x0098..0x009c */ 75 struct { 76 u32 lsb; /* 0x0098 */ 77 u32 msb; /* 0x009c */ 78 }; 79 } msi_watermark; 80 union { 81 u64 reg; /* 0x00a0..0x00a4 */ 82 struct { 83 u32 lsb; /* 0x00a0 */ 84 u32 msb; /* 0x00a4 */ 85 }; 86 } msi_abort; 87 u32 msi_msgdata; /* 0x00a8 */ 88 u32 padding_2[21]; /* 0x00ac..0x00fc */ 89 } __packed; 90 91 struct dw_hdma_v0_ch { 92 struct dw_hdma_v0_ch_regs wr; /* 0x0000 */ 93 struct dw_hdma_v0_ch_regs rd; /* 0x0100 */ 94 } __packed; 95 96 struct dw_hdma_v0_regs { 97 struct dw_hdma_v0_ch ch[HDMA_V0_MAX_NR_CH]; /* 0x0000..0x0fa8 */ 98 } __packed; 99 100 struct dw_hdma_v0_lli { 101 u32 control; 102 u32 transfer_size; 103 union { 104 u64 reg; 105 struct { 106 u32 lsb; 107 u32 msb; 108 }; 109 } sar; 110 union { 111 u64 reg; 112 struct { 113 u32 lsb; 114 u32 msb; 115 }; 116 } dar; 117 } __packed; 118 119 struct dw_hdma_v0_llp { 120 u32 control; 121 u32 reserved; 122 union { 123 u64 reg; 124 struct { 125 u32 lsb; 126 u32 msb; 127 }; 128 } llp; 129 } __packed; 130 131 #endif /* _DW_HDMA_V0_REGS_H */ 132