1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface framework 4 * 5 * Author: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/iopoll.h> 10 #include <linux/interrupt.h> 11 #include <linux/mdio.h> 12 #include <linux/phy.h> 13 #include <linux/oa_tc6.h> 14 15 /* OPEN Alliance TC6 registers */ 16 /* Standard Capabilities Register */ 17 #define OA_TC6_REG_STDCAP 0x0002 18 #define STDCAP_DIRECT_PHY_REG_ACCESS BIT(8) 19 20 /* Reset Control and Status Register */ 21 #define OA_TC6_REG_RESET 0x0003 22 #define RESET_SWRESET BIT(0) /* Software Reset */ 23 24 /* Configuration Register #0 */ 25 #define OA_TC6_REG_CONFIG0 0x0004 26 #define CONFIG0_SYNC BIT(15) 27 #define CONFIG0_ZARFE_ENABLE BIT(12) 28 29 /* Status Register #0 */ 30 #define OA_TC6_REG_STATUS0 0x0008 31 #define STATUS0_RESETC BIT(6) /* Reset Complete */ 32 #define STATUS0_HEADER_ERROR BIT(5) 33 #define STATUS0_LOSS_OF_FRAME_ERROR BIT(4) 34 #define STATUS0_RX_BUFFER_OVERFLOW_ERROR BIT(3) 35 #define STATUS0_TX_PROTOCOL_ERROR BIT(0) 36 37 /* Buffer Status Register */ 38 #define OA_TC6_REG_BUFFER_STATUS 0x000B 39 #define BUFFER_STATUS_TX_CREDITS_AVAILABLE GENMASK(15, 8) 40 #define BUFFER_STATUS_RX_CHUNKS_AVAILABLE GENMASK(7, 0) 41 42 /* Interrupt Mask Register #0 */ 43 #define OA_TC6_REG_INT_MASK0 0x000C 44 #define INT_MASK0_HEADER_ERR_MASK BIT(5) 45 #define INT_MASK0_LOSS_OF_FRAME_ERR_MASK BIT(4) 46 #define INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK BIT(3) 47 #define INT_MASK0_TX_PROTOCOL_ERR_MASK BIT(0) 48 #define INT_MASK0_ALL_INTERRUPTS (GENMASK(5, 0) | \ 49 GENMASK(12, 7)) 50 51 /* PHY Clause 22 registers base address and mask */ 52 #define OA_TC6_PHY_STD_REG_ADDR_BASE 0xFF00 53 #define OA_TC6_PHY_STD_REG_ADDR_MASK 0x1F 54 55 /* Control command header */ 56 #define OA_TC6_CTRL_HEADER_DATA_NOT_CTRL BIT(31) 57 #define OA_TC6_CTRL_HEADER_WRITE_NOT_READ BIT(29) 58 #define OA_TC6_CTRL_HEADER_MEM_MAP_SELECTOR GENMASK(27, 24) 59 #define OA_TC6_CTRL_HEADER_ADDR GENMASK(23, 8) 60 #define OA_TC6_CTRL_HEADER_LENGTH GENMASK(7, 1) 61 #define OA_TC6_CTRL_HEADER_PARITY BIT(0) 62 63 /* Data header */ 64 #define OA_TC6_DATA_HEADER_DATA_NOT_CTRL BIT(31) 65 #define OA_TC6_DATA_HEADER_DATA_VALID BIT(21) 66 #define OA_TC6_DATA_HEADER_START_VALID BIT(20) 67 #define OA_TC6_DATA_HEADER_START_WORD_OFFSET GENMASK(19, 16) 68 #define OA_TC6_DATA_HEADER_END_VALID BIT(14) 69 #define OA_TC6_DATA_HEADER_END_BYTE_OFFSET GENMASK(13, 8) 70 #define OA_TC6_DATA_HEADER_PARITY BIT(0) 71 72 /* Data footer */ 73 #define OA_TC6_DATA_FOOTER_EXTENDED_STS BIT(31) 74 #define OA_TC6_DATA_FOOTER_RXD_HEADER_BAD BIT(30) 75 #define OA_TC6_DATA_FOOTER_CONFIG_SYNC BIT(29) 76 #define OA_TC6_DATA_FOOTER_RX_CHUNKS GENMASK(28, 24) 77 #define OA_TC6_DATA_FOOTER_DATA_VALID BIT(21) 78 #define OA_TC6_DATA_FOOTER_START_VALID BIT(20) 79 #define OA_TC6_DATA_FOOTER_START_WORD_OFFSET GENMASK(19, 16) 80 #define OA_TC6_DATA_FOOTER_END_VALID BIT(14) 81 #define OA_TC6_DATA_FOOTER_END_BYTE_OFFSET GENMASK(13, 8) 82 #define OA_TC6_DATA_FOOTER_TX_CREDITS GENMASK(5, 1) 83 84 /* PHY – Clause 45 registers memory map selector (MMS) as per table 6 in the 85 * OPEN Alliance specification. 86 */ 87 #define OA_TC6_PHY_C45_PCS_MMS2 2 /* MMD 3 */ 88 #define OA_TC6_PHY_C45_PMA_PMD_MMS3 3 /* MMD 1 */ 89 #define OA_TC6_PHY_C45_VS_PLCA_MMS4 4 /* MMD 31 */ 90 #define OA_TC6_PHY_C45_AUTO_NEG_MMS5 5 /* MMD 7 */ 91 #define OA_TC6_PHY_C45_POWER_UNIT_MMS6 6 /* MMD 13 */ 92 93 #define OA_TC6_CTRL_HEADER_SIZE 4 94 #define OA_TC6_CTRL_REG_VALUE_SIZE 4 95 #define OA_TC6_CTRL_IGNORED_SIZE 4 96 #define OA_TC6_CTRL_MAX_REGISTERS 128 97 #define OA_TC6_CTRL_SPI_BUF_SIZE (OA_TC6_CTRL_HEADER_SIZE +\ 98 (OA_TC6_CTRL_MAX_REGISTERS *\ 99 OA_TC6_CTRL_REG_VALUE_SIZE) +\ 100 OA_TC6_CTRL_IGNORED_SIZE) 101 #define OA_TC6_CHUNK_PAYLOAD_SIZE 64 102 #define OA_TC6_DATA_HEADER_SIZE 4 103 #define OA_TC6_CHUNK_SIZE (OA_TC6_DATA_HEADER_SIZE +\ 104 OA_TC6_CHUNK_PAYLOAD_SIZE) 105 #define OA_TC6_MAX_TX_CHUNKS 48 106 #define OA_TC6_SPI_DATA_BUF_SIZE (OA_TC6_MAX_TX_CHUNKS *\ 107 OA_TC6_CHUNK_SIZE) 108 #define STATUS0_RESETC_POLL_DELAY 1000 109 #define STATUS0_RESETC_POLL_TIMEOUT 1000000 110 111 /* Internal structure for MAC-PHY drivers */ 112 struct oa_tc6 { 113 struct net_device *netdev; 114 struct phy_device *phydev; 115 struct mii_bus *mdiobus; 116 struct spi_device *spi; 117 struct mutex spi_ctrl_lock; /* Protects spi control transfer */ 118 spinlock_t tx_skb_lock; /* Protects tx skb handling */ 119 void *spi_ctrl_tx_buf; 120 void *spi_ctrl_rx_buf; 121 void *spi_data_tx_buf; 122 void *spi_data_rx_buf; 123 struct sk_buff *ongoing_tx_skb; 124 struct sk_buff *waiting_tx_skb; 125 struct sk_buff *rx_skb; 126 u16 tx_skb_offset; 127 u16 spi_data_tx_buf_offset; 128 u16 tx_credits; 129 u8 rx_chunks_available; 130 bool rx_buf_overflow; 131 bool int_flag; 132 bool disable_traffic; 133 }; 134 135 enum oa_tc6_header_type { 136 OA_TC6_CTRL_HEADER, 137 OA_TC6_DATA_HEADER, 138 }; 139 140 enum oa_tc6_register_op { 141 OA_TC6_CTRL_REG_READ = 0, 142 OA_TC6_CTRL_REG_WRITE = 1, 143 }; 144 145 enum oa_tc6_data_valid_info { 146 OA_TC6_DATA_INVALID, 147 OA_TC6_DATA_VALID, 148 }; 149 150 enum oa_tc6_data_start_valid_info { 151 OA_TC6_DATA_START_INVALID, 152 OA_TC6_DATA_START_VALID, 153 }; 154 155 enum oa_tc6_data_end_valid_info { 156 OA_TC6_DATA_END_INVALID, 157 OA_TC6_DATA_END_VALID, 158 }; 159 160 static int oa_tc6_spi_transfer(struct oa_tc6 *tc6, 161 enum oa_tc6_header_type header_type, u16 length) 162 { 163 struct spi_transfer xfer = { 0 }; 164 struct spi_message msg; 165 166 if (header_type == OA_TC6_DATA_HEADER) { 167 xfer.tx_buf = tc6->spi_data_tx_buf; 168 xfer.rx_buf = tc6->spi_data_rx_buf; 169 } else { 170 xfer.tx_buf = tc6->spi_ctrl_tx_buf; 171 xfer.rx_buf = tc6->spi_ctrl_rx_buf; 172 } 173 xfer.len = length; 174 175 spi_message_init(&msg); 176 spi_message_add_tail(&xfer, &msg); 177 178 return spi_sync(tc6->spi, &msg); 179 } 180 181 static int oa_tc6_get_parity(u32 p) 182 { 183 /* Public domain code snippet, lifted from 184 * http://www-graphics.stanford.edu/~seander/bithacks.html 185 */ 186 p ^= p >> 1; 187 p ^= p >> 2; 188 p = (p & 0x11111111U) * 0x11111111U; 189 190 /* Odd parity is used here */ 191 return !((p >> 28) & 1); 192 } 193 194 static __be32 oa_tc6_prepare_ctrl_header(u32 addr, u8 length, 195 enum oa_tc6_register_op reg_op) 196 { 197 u32 header; 198 199 header = FIELD_PREP(OA_TC6_CTRL_HEADER_DATA_NOT_CTRL, 200 OA_TC6_CTRL_HEADER) | 201 FIELD_PREP(OA_TC6_CTRL_HEADER_WRITE_NOT_READ, reg_op) | 202 FIELD_PREP(OA_TC6_CTRL_HEADER_MEM_MAP_SELECTOR, addr >> 16) | 203 FIELD_PREP(OA_TC6_CTRL_HEADER_ADDR, addr) | 204 FIELD_PREP(OA_TC6_CTRL_HEADER_LENGTH, length - 1); 205 header |= FIELD_PREP(OA_TC6_CTRL_HEADER_PARITY, 206 oa_tc6_get_parity(header)); 207 208 return cpu_to_be32(header); 209 } 210 211 static void oa_tc6_update_ctrl_write_data(struct oa_tc6 *tc6, u32 value[], 212 u8 length) 213 { 214 __be32 *tx_buf = tc6->spi_ctrl_tx_buf + OA_TC6_CTRL_HEADER_SIZE; 215 216 for (int i = 0; i < length; i++) 217 *tx_buf++ = cpu_to_be32(value[i]); 218 } 219 220 static u16 oa_tc6_calculate_ctrl_buf_size(u8 length) 221 { 222 /* Control command consists 4 bytes header + 4 bytes register value for 223 * each register + 4 bytes ignored value. 224 */ 225 return OA_TC6_CTRL_HEADER_SIZE + OA_TC6_CTRL_REG_VALUE_SIZE * length + 226 OA_TC6_CTRL_IGNORED_SIZE; 227 } 228 229 static void oa_tc6_prepare_ctrl_spi_buf(struct oa_tc6 *tc6, u32 address, 230 u32 value[], u8 length, 231 enum oa_tc6_register_op reg_op) 232 { 233 __be32 *tx_buf = tc6->spi_ctrl_tx_buf; 234 235 *tx_buf = oa_tc6_prepare_ctrl_header(address, length, reg_op); 236 237 if (reg_op == OA_TC6_CTRL_REG_WRITE) 238 oa_tc6_update_ctrl_write_data(tc6, value, length); 239 } 240 241 static int oa_tc6_check_ctrl_write_reply(struct oa_tc6 *tc6, u8 size) 242 { 243 u8 *tx_buf = tc6->spi_ctrl_tx_buf; 244 u8 *rx_buf = tc6->spi_ctrl_rx_buf; 245 246 rx_buf += OA_TC6_CTRL_IGNORED_SIZE; 247 248 /* The echoed control write must match with the one that was 249 * transmitted. 250 */ 251 if (memcmp(tx_buf, rx_buf, size - OA_TC6_CTRL_IGNORED_SIZE)) 252 return -EPROTO; 253 254 return 0; 255 } 256 257 static int oa_tc6_check_ctrl_read_reply(struct oa_tc6 *tc6, u8 size) 258 { 259 u32 *rx_buf = tc6->spi_ctrl_rx_buf + OA_TC6_CTRL_IGNORED_SIZE; 260 u32 *tx_buf = tc6->spi_ctrl_tx_buf; 261 262 /* The echoed control read header must match with the one that was 263 * transmitted. 264 */ 265 if (*tx_buf != *rx_buf) 266 return -EPROTO; 267 268 return 0; 269 } 270 271 static void oa_tc6_copy_ctrl_read_data(struct oa_tc6 *tc6, u32 value[], 272 u8 length) 273 { 274 __be32 *rx_buf = tc6->spi_ctrl_rx_buf + OA_TC6_CTRL_IGNORED_SIZE + 275 OA_TC6_CTRL_HEADER_SIZE; 276 277 for (int i = 0; i < length; i++) 278 value[i] = be32_to_cpu(*rx_buf++); 279 } 280 281 static int oa_tc6_perform_ctrl(struct oa_tc6 *tc6, u32 address, u32 value[], 282 u8 length, enum oa_tc6_register_op reg_op) 283 { 284 u16 size; 285 int ret; 286 287 /* Prepare control command and copy to SPI control buffer */ 288 oa_tc6_prepare_ctrl_spi_buf(tc6, address, value, length, reg_op); 289 290 size = oa_tc6_calculate_ctrl_buf_size(length); 291 292 /* Perform SPI transfer */ 293 ret = oa_tc6_spi_transfer(tc6, OA_TC6_CTRL_HEADER, size); 294 if (ret) { 295 dev_err(&tc6->spi->dev, "SPI transfer failed for control: %d\n", 296 ret); 297 return ret; 298 } 299 300 /* Check echoed/received control write command reply for errors */ 301 if (reg_op == OA_TC6_CTRL_REG_WRITE) 302 return oa_tc6_check_ctrl_write_reply(tc6, size); 303 304 /* Check echoed/received control read command reply for errors */ 305 ret = oa_tc6_check_ctrl_read_reply(tc6, size); 306 if (ret) 307 return ret; 308 309 oa_tc6_copy_ctrl_read_data(tc6, value, length); 310 311 return 0; 312 } 313 314 /** 315 * oa_tc6_read_registers - function for reading multiple consecutive registers. 316 * @tc6: oa_tc6 struct. 317 * @address: address of the first register to be read in the MAC-PHY. 318 * @value: values to be read from the starting register address @address. 319 * @length: number of consecutive registers to be read from @address. 320 * 321 * Maximum of 128 consecutive registers can be read starting at @address. 322 * 323 * Return: 0 on success otherwise failed. 324 */ 325 int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address, u32 value[], 326 u8 length) 327 { 328 int ret; 329 330 if (!length || length > OA_TC6_CTRL_MAX_REGISTERS) { 331 dev_err(&tc6->spi->dev, "Invalid register length parameter\n"); 332 return -EINVAL; 333 } 334 335 mutex_lock(&tc6->spi_ctrl_lock); 336 ret = oa_tc6_perform_ctrl(tc6, address, value, length, 337 OA_TC6_CTRL_REG_READ); 338 mutex_unlock(&tc6->spi_ctrl_lock); 339 340 return ret; 341 } 342 EXPORT_SYMBOL_GPL(oa_tc6_read_registers); 343 344 /** 345 * oa_tc6_read_register - function for reading a MAC-PHY register. 346 * @tc6: oa_tc6 struct. 347 * @address: register address of the MAC-PHY to be read. 348 * @value: value read from the @address register address of the MAC-PHY. 349 * 350 * Return: 0 on success otherwise failed. 351 */ 352 int oa_tc6_read_register(struct oa_tc6 *tc6, u32 address, u32 *value) 353 { 354 return oa_tc6_read_registers(tc6, address, value, 1); 355 } 356 EXPORT_SYMBOL_GPL(oa_tc6_read_register); 357 358 /** 359 * oa_tc6_write_registers - function for writing multiple consecutive registers. 360 * @tc6: oa_tc6 struct. 361 * @address: address of the first register to be written in the MAC-PHY. 362 * @value: values to be written from the starting register address @address. 363 * @length: number of consecutive registers to be written from @address. 364 * 365 * Maximum of 128 consecutive registers can be written starting at @address. 366 * 367 * Return: 0 on success otherwise failed. 368 */ 369 int oa_tc6_write_registers(struct oa_tc6 *tc6, u32 address, u32 value[], 370 u8 length) 371 { 372 int ret; 373 374 if (!length || length > OA_TC6_CTRL_MAX_REGISTERS) { 375 dev_err(&tc6->spi->dev, "Invalid register length parameter\n"); 376 return -EINVAL; 377 } 378 379 mutex_lock(&tc6->spi_ctrl_lock); 380 ret = oa_tc6_perform_ctrl(tc6, address, value, length, 381 OA_TC6_CTRL_REG_WRITE); 382 mutex_unlock(&tc6->spi_ctrl_lock); 383 384 return ret; 385 } 386 EXPORT_SYMBOL_GPL(oa_tc6_write_registers); 387 388 /** 389 * oa_tc6_write_register - function for writing a MAC-PHY register. 390 * @tc6: oa_tc6 struct. 391 * @address: register address of the MAC-PHY to be written. 392 * @value: value to be written in the @address register address of the MAC-PHY. 393 * 394 * Return: 0 on success otherwise failed. 395 */ 396 int oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, u32 value) 397 { 398 return oa_tc6_write_registers(tc6, address, &value, 1); 399 } 400 EXPORT_SYMBOL_GPL(oa_tc6_write_register); 401 402 static int oa_tc6_check_phy_reg_direct_access_capability(struct oa_tc6 *tc6) 403 { 404 u32 regval; 405 int ret; 406 407 ret = oa_tc6_read_register(tc6, OA_TC6_REG_STDCAP, ®val); 408 if (ret) 409 return ret; 410 411 if (!(regval & STDCAP_DIRECT_PHY_REG_ACCESS)) 412 return -ENODEV; 413 414 return 0; 415 } 416 417 static void oa_tc6_handle_link_change(struct net_device *netdev) 418 { 419 phy_print_status(netdev->phydev); 420 } 421 422 static int oa_tc6_mdiobus_read(struct mii_bus *bus, int addr, int regnum) 423 { 424 struct oa_tc6 *tc6 = bus->priv; 425 u32 regval; 426 bool ret; 427 428 ret = oa_tc6_read_register(tc6, OA_TC6_PHY_STD_REG_ADDR_BASE | 429 (regnum & OA_TC6_PHY_STD_REG_ADDR_MASK), 430 ®val); 431 if (ret) 432 return ret; 433 434 return regval; 435 } 436 437 static int oa_tc6_mdiobus_write(struct mii_bus *bus, int addr, int regnum, 438 u16 val) 439 { 440 struct oa_tc6 *tc6 = bus->priv; 441 442 return oa_tc6_write_register(tc6, OA_TC6_PHY_STD_REG_ADDR_BASE | 443 (regnum & OA_TC6_PHY_STD_REG_ADDR_MASK), 444 val); 445 } 446 447 static int oa_tc6_get_phy_c45_mms(int devnum) 448 { 449 switch (devnum) { 450 case MDIO_MMD_PCS: 451 return OA_TC6_PHY_C45_PCS_MMS2; 452 case MDIO_MMD_PMAPMD: 453 return OA_TC6_PHY_C45_PMA_PMD_MMS3; 454 case MDIO_MMD_VEND2: 455 return OA_TC6_PHY_C45_VS_PLCA_MMS4; 456 case MDIO_MMD_AN: 457 return OA_TC6_PHY_C45_AUTO_NEG_MMS5; 458 case MDIO_MMD_POWER_UNIT: 459 return OA_TC6_PHY_C45_POWER_UNIT_MMS6; 460 default: 461 return -EOPNOTSUPP; 462 } 463 } 464 465 static int oa_tc6_mdiobus_read_c45(struct mii_bus *bus, int addr, int devnum, 466 int regnum) 467 { 468 struct oa_tc6 *tc6 = bus->priv; 469 u32 regval; 470 int ret; 471 472 ret = oa_tc6_get_phy_c45_mms(devnum); 473 if (ret < 0) 474 return ret; 475 476 ret = oa_tc6_read_register(tc6, (ret << 16) | regnum, ®val); 477 if (ret) 478 return ret; 479 480 return regval; 481 } 482 483 static int oa_tc6_mdiobus_write_c45(struct mii_bus *bus, int addr, int devnum, 484 int regnum, u16 val) 485 { 486 struct oa_tc6 *tc6 = bus->priv; 487 int ret; 488 489 ret = oa_tc6_get_phy_c45_mms(devnum); 490 if (ret < 0) 491 return ret; 492 493 return oa_tc6_write_register(tc6, (ret << 16) | regnum, val); 494 } 495 496 static int oa_tc6_mdiobus_register(struct oa_tc6 *tc6) 497 { 498 int ret; 499 500 tc6->mdiobus = mdiobus_alloc(); 501 if (!tc6->mdiobus) { 502 netdev_err(tc6->netdev, "MDIO bus alloc failed\n"); 503 return -ENOMEM; 504 } 505 506 tc6->mdiobus->priv = tc6; 507 tc6->mdiobus->read = oa_tc6_mdiobus_read; 508 tc6->mdiobus->write = oa_tc6_mdiobus_write; 509 /* OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and 510 * C45 registers space. If the PHY is discovered via C22 bus protocol it 511 * assumes it uses C22 protocol and always uses C22 registers indirect 512 * access to access C45 registers. This is because, we don't have a 513 * clean separation between C22/C45 register space and C22/C45 MDIO bus 514 * protocols. Resulting, PHY C45 registers direct access can't be used 515 * which can save multiple SPI bus access. To support this feature, PHY 516 * drivers can set .read_mmd/.write_mmd in the PHY driver to call 517 * .read_c45/.write_c45. Ex: drivers/net/phy/microchip_t1s.c 518 */ 519 tc6->mdiobus->read_c45 = oa_tc6_mdiobus_read_c45; 520 tc6->mdiobus->write_c45 = oa_tc6_mdiobus_write_c45; 521 tc6->mdiobus->name = "oa-tc6-mdiobus"; 522 tc6->mdiobus->parent = &tc6->spi->dev; 523 524 snprintf(tc6->mdiobus->id, ARRAY_SIZE(tc6->mdiobus->id), "%s", 525 dev_name(&tc6->spi->dev)); 526 527 ret = mdiobus_register(tc6->mdiobus); 528 if (ret) { 529 netdev_err(tc6->netdev, "Could not register MDIO bus\n"); 530 mdiobus_free(tc6->mdiobus); 531 return ret; 532 } 533 534 return 0; 535 } 536 537 static void oa_tc6_mdiobus_unregister(struct oa_tc6 *tc6) 538 { 539 mdiobus_unregister(tc6->mdiobus); 540 mdiobus_free(tc6->mdiobus); 541 } 542 543 static int oa_tc6_phy_init(struct oa_tc6 *tc6) 544 { 545 int ret; 546 547 ret = oa_tc6_check_phy_reg_direct_access_capability(tc6); 548 if (ret) { 549 netdev_err(tc6->netdev, 550 "Direct PHY register access is not supported by the MAC-PHY\n"); 551 return ret; 552 } 553 554 ret = oa_tc6_mdiobus_register(tc6); 555 if (ret) 556 return ret; 557 558 tc6->phydev = phy_find_first(tc6->mdiobus); 559 if (!tc6->phydev) { 560 netdev_err(tc6->netdev, "No PHY found\n"); 561 oa_tc6_mdiobus_unregister(tc6); 562 return -ENODEV; 563 } 564 565 tc6->phydev->is_internal = true; 566 ret = phy_connect_direct(tc6->netdev, tc6->phydev, 567 &oa_tc6_handle_link_change, 568 PHY_INTERFACE_MODE_INTERNAL); 569 if (ret) { 570 netdev_err(tc6->netdev, "Can't attach PHY to %s\n", 571 tc6->mdiobus->id); 572 oa_tc6_mdiobus_unregister(tc6); 573 return ret; 574 } 575 576 phy_attached_info(tc6->netdev->phydev); 577 578 return 0; 579 } 580 581 static void oa_tc6_phy_exit(struct oa_tc6 *tc6) 582 { 583 phy_disconnect(tc6->phydev); 584 oa_tc6_mdiobus_unregister(tc6); 585 } 586 587 static int oa_tc6_read_status0(struct oa_tc6 *tc6) 588 { 589 u32 regval; 590 int ret; 591 592 ret = oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, ®val); 593 if (ret) { 594 dev_err(&tc6->spi->dev, "STATUS0 register read failed: %d\n", 595 ret); 596 return 0; 597 } 598 599 return regval; 600 } 601 602 static int oa_tc6_sw_reset_macphy(struct oa_tc6 *tc6) 603 { 604 u32 regval = RESET_SWRESET; 605 int ret; 606 607 ret = oa_tc6_write_register(tc6, OA_TC6_REG_RESET, regval); 608 if (ret) 609 return ret; 610 611 /* Poll for soft reset complete for every 1ms until 1s timeout */ 612 ret = readx_poll_timeout(oa_tc6_read_status0, tc6, regval, 613 regval & STATUS0_RESETC, 614 STATUS0_RESETC_POLL_DELAY, 615 STATUS0_RESETC_POLL_TIMEOUT); 616 if (ret) 617 return -ENODEV; 618 619 /* Clear the reset complete status */ 620 return oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval); 621 } 622 623 static int oa_tc6_unmask_macphy_error_interrupts(struct oa_tc6 *tc6) 624 { 625 u32 regval; 626 int ret; 627 628 ret = oa_tc6_read_register(tc6, OA_TC6_REG_INT_MASK0, ®val); 629 if (ret) 630 return ret; 631 632 regval &= ~(INT_MASK0_TX_PROTOCOL_ERR_MASK | 633 INT_MASK0_RX_BUFFER_OVERFLOW_ERR_MASK | 634 INT_MASK0_LOSS_OF_FRAME_ERR_MASK | 635 INT_MASK0_HEADER_ERR_MASK); 636 637 return oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval); 638 } 639 640 static int oa_tc6_enable_data_transfer(struct oa_tc6 *tc6) 641 { 642 u32 value; 643 int ret; 644 645 ret = oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, &value); 646 if (ret) 647 return ret; 648 649 /* Enable configuration synchronization for data transfer */ 650 value |= CONFIG0_SYNC; 651 652 return oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, value); 653 } 654 655 static void oa_tc6_cleanup_ongoing_rx_skb(struct oa_tc6 *tc6) 656 { 657 if (tc6->rx_skb) { 658 tc6->netdev->stats.rx_dropped++; 659 kfree_skb(tc6->rx_skb); 660 tc6->rx_skb = NULL; 661 } 662 } 663 664 static void oa_tc6_cleanup_ongoing_tx_skb(struct oa_tc6 *tc6) 665 { 666 if (tc6->ongoing_tx_skb) { 667 tc6->netdev->stats.tx_dropped++; 668 kfree_skb(tc6->ongoing_tx_skb); 669 tc6->ongoing_tx_skb = NULL; 670 } 671 } 672 673 static void oa_tc6_cleanup_waiting_tx_skb(struct oa_tc6 *tc6) 674 { 675 if (tc6->waiting_tx_skb) { 676 tc6->netdev->stats.tx_dropped++; 677 kfree_skb(tc6->waiting_tx_skb); 678 tc6->waiting_tx_skb = NULL; 679 } 680 } 681 682 static void oa_tc6_free_pending_skbs(struct oa_tc6 *tc6) 683 { 684 oa_tc6_cleanup_ongoing_tx_skb(tc6); 685 oa_tc6_cleanup_ongoing_rx_skb(tc6); 686 oa_tc6_cleanup_waiting_tx_skb(tc6); 687 } 688 689 /* If the failure is at SPI interface level, masking and clearing 690 * the interrupt of the device won't work. Since SPI interrupt is 691 * disabled, it should stop the repeated interrupts. 692 */ 693 static void oa_tc6_disable_traffic(struct oa_tc6 *tc6) 694 { 695 u32 regval = INT_MASK0_ALL_INTERRUPTS; 696 697 tc6->disable_traffic = true; 698 oa_tc6_free_pending_skbs(tc6); 699 oa_tc6_write_register(tc6, OA_TC6_REG_INT_MASK0, regval); 700 oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, ®val); 701 oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, regval); 702 dev_err(&tc6->spi->dev, "Device interrupt disabled to avoid interrupt storm"); 703 } 704 705 static int oa_tc6_process_extended_status(struct oa_tc6 *tc6) 706 { 707 u32 value; 708 int ret; 709 710 ret = oa_tc6_read_register(tc6, OA_TC6_REG_STATUS0, &value); 711 if (ret) { 712 netdev_err(tc6->netdev, "STATUS0 register read failed: %d\n", 713 ret); 714 return ret; 715 } 716 717 /* Clear the error interrupts status */ 718 ret = oa_tc6_write_register(tc6, OA_TC6_REG_STATUS0, value); 719 if (ret) { 720 netdev_err(tc6->netdev, "STATUS0 register write failed: %d\n", 721 ret); 722 return ret; 723 } 724 725 if (FIELD_GET(STATUS0_RX_BUFFER_OVERFLOW_ERROR, value)) { 726 tc6->rx_buf_overflow = true; 727 oa_tc6_cleanup_ongoing_rx_skb(tc6); 728 net_err_ratelimited("%s: Receive buffer overflow error\n", 729 tc6->netdev->name); 730 return -EAGAIN; 731 } 732 if (FIELD_GET(STATUS0_TX_PROTOCOL_ERROR, value)) { 733 netdev_err(tc6->netdev, "Transmit protocol error\n"); 734 return -ENODEV; 735 } 736 /* TODO: Currently loss of frame and header errors are treated as 737 * non-recoverable errors. They will be handled in the next version. 738 */ 739 if (FIELD_GET(STATUS0_LOSS_OF_FRAME_ERROR, value)) { 740 netdev_err(tc6->netdev, "Loss of frame error\n"); 741 return -ENODEV; 742 } 743 if (FIELD_GET(STATUS0_HEADER_ERROR, value)) { 744 netdev_err(tc6->netdev, "Header error\n"); 745 return -ENODEV; 746 } 747 748 return 0; 749 } 750 751 static int oa_tc6_process_rx_chunk_footer(struct oa_tc6 *tc6, u32 footer) 752 { 753 /* Process rx chunk footer for the following, 754 * 1. tx credits 755 * 2. errors if any from MAC-PHY 756 * 3. receive chunks available 757 */ 758 tc6->tx_credits = FIELD_GET(OA_TC6_DATA_FOOTER_TX_CREDITS, footer); 759 tc6->rx_chunks_available = FIELD_GET(OA_TC6_DATA_FOOTER_RX_CHUNKS, 760 footer); 761 762 if (FIELD_GET(OA_TC6_DATA_FOOTER_EXTENDED_STS, footer)) { 763 int ret = oa_tc6_process_extended_status(tc6); 764 765 if (ret) 766 return ret; 767 } 768 769 /* TODO: Currently received header bad and configuration unsync errors 770 * are treated as non-recoverable errors. They will be handled in the 771 * next version. 772 */ 773 if (FIELD_GET(OA_TC6_DATA_FOOTER_RXD_HEADER_BAD, footer)) { 774 netdev_err(tc6->netdev, "Rxd header bad error\n"); 775 return -ENODEV; 776 } 777 778 if (!FIELD_GET(OA_TC6_DATA_FOOTER_CONFIG_SYNC, footer)) { 779 netdev_err(tc6->netdev, "Config unsync error\n"); 780 return -ENODEV; 781 } 782 783 return 0; 784 } 785 786 static void oa_tc6_submit_rx_skb(struct oa_tc6 *tc6) 787 { 788 /* MAC-PHY delivers each frame with its Ethernet FCS attached. 789 * Strip it before handing over to the stack, unless the user 790 * has asked to keep it via NETIF_F_RXFCS. Keeping the FCS 791 * in the frame is harmless for IP traffic, but is parsed as 792 * a (malformed) suffix TLV by PTP, which makes ptp4l reject 793 * every message with "bad message" error. 794 */ 795 if (!(tc6->netdev->features & NETIF_F_RXFCS) && 796 tc6->rx_skb->len > ETH_FCS_LEN) 797 skb_trim(tc6->rx_skb, tc6->rx_skb->len - ETH_FCS_LEN); 798 799 tc6->rx_skb->protocol = eth_type_trans(tc6->rx_skb, tc6->netdev); 800 tc6->netdev->stats.rx_packets++; 801 tc6->netdev->stats.rx_bytes += tc6->rx_skb->len; 802 803 netif_rx(tc6->rx_skb); 804 805 tc6->rx_skb = NULL; 806 } 807 808 static void oa_tc6_update_rx_skb(struct oa_tc6 *tc6, u8 *payload, u8 length) 809 { 810 memcpy(skb_put(tc6->rx_skb, length), payload, length); 811 } 812 813 static int oa_tc6_allocate_rx_skb(struct oa_tc6 *tc6) 814 { 815 tc6->rx_skb = netdev_alloc_skb_ip_align(tc6->netdev, tc6->netdev->mtu + 816 ETH_HLEN + ETH_FCS_LEN); 817 if (!tc6->rx_skb) { 818 tc6->netdev->stats.rx_dropped++; 819 return -ENOMEM; 820 } 821 822 return 0; 823 } 824 825 static int oa_tc6_prcs_complete_rx_frame(struct oa_tc6 *tc6, u8 *payload, 826 u16 size) 827 { 828 int ret; 829 830 ret = oa_tc6_allocate_rx_skb(tc6); 831 if (ret) 832 return ret; 833 834 oa_tc6_update_rx_skb(tc6, payload, size); 835 836 oa_tc6_submit_rx_skb(tc6); 837 838 return 0; 839 } 840 841 static int oa_tc6_prcs_rx_frame_start(struct oa_tc6 *tc6, u8 *payload, u16 size) 842 { 843 int ret; 844 845 ret = oa_tc6_allocate_rx_skb(tc6); 846 if (ret) 847 return ret; 848 849 oa_tc6_update_rx_skb(tc6, payload, size); 850 851 return 0; 852 } 853 854 static void oa_tc6_prcs_rx_frame_end(struct oa_tc6 *tc6, u8 *payload, u16 size) 855 { 856 oa_tc6_update_rx_skb(tc6, payload, size); 857 858 oa_tc6_submit_rx_skb(tc6); 859 } 860 861 static void oa_tc6_prcs_ongoing_rx_frame(struct oa_tc6 *tc6, u8 *payload, 862 u32 footer) 863 { 864 oa_tc6_update_rx_skb(tc6, payload, OA_TC6_CHUNK_PAYLOAD_SIZE); 865 } 866 867 static int oa_tc6_prcs_rx_chunk_payload(struct oa_tc6 *tc6, u8 *data, 868 u32 footer) 869 { 870 u8 start_byte_offset = FIELD_GET(OA_TC6_DATA_FOOTER_START_WORD_OFFSET, 871 footer) * sizeof(u32); 872 u8 end_byte_offset = FIELD_GET(OA_TC6_DATA_FOOTER_END_BYTE_OFFSET, 873 footer); 874 bool start_valid = FIELD_GET(OA_TC6_DATA_FOOTER_START_VALID, footer); 875 bool end_valid = FIELD_GET(OA_TC6_DATA_FOOTER_END_VALID, footer); 876 u16 size; 877 878 /* Restart the new rx frame after receiving rx buffer overflow error */ 879 if (start_valid && tc6->rx_buf_overflow) 880 tc6->rx_buf_overflow = false; 881 882 if (tc6->rx_buf_overflow) 883 return 0; 884 885 /* Process the chunk with complete rx frame */ 886 if (start_valid && end_valid && start_byte_offset < end_byte_offset) { 887 size = end_byte_offset + 1 - start_byte_offset; 888 return oa_tc6_prcs_complete_rx_frame(tc6, 889 &data[start_byte_offset], 890 size); 891 } 892 893 /* Process the chunk with only rx frame start */ 894 if (start_valid && !end_valid) { 895 size = OA_TC6_CHUNK_PAYLOAD_SIZE - start_byte_offset; 896 return oa_tc6_prcs_rx_frame_start(tc6, 897 &data[start_byte_offset], 898 size); 899 } 900 901 /* Process the chunk with only rx frame end */ 902 if (end_valid && !start_valid) { 903 size = end_byte_offset + 1; 904 oa_tc6_prcs_rx_frame_end(tc6, data, size); 905 return 0; 906 } 907 908 /* Process the chunk with previous rx frame end and next rx frame 909 * start. 910 */ 911 if (start_valid && end_valid && start_byte_offset > end_byte_offset) { 912 /* After rx buffer overflow error received, there might be a 913 * possibility of getting an end valid of a previously 914 * incomplete rx frame along with the new rx frame start valid. 915 */ 916 if (tc6->rx_skb) { 917 size = end_byte_offset + 1; 918 oa_tc6_prcs_rx_frame_end(tc6, data, size); 919 } 920 size = OA_TC6_CHUNK_PAYLOAD_SIZE - start_byte_offset; 921 return oa_tc6_prcs_rx_frame_start(tc6, 922 &data[start_byte_offset], 923 size); 924 } 925 926 /* Process the chunk with ongoing rx frame data */ 927 oa_tc6_prcs_ongoing_rx_frame(tc6, data, footer); 928 929 return 0; 930 } 931 932 static u32 oa_tc6_get_rx_chunk_footer(struct oa_tc6 *tc6, u16 footer_offset) 933 { 934 u8 *rx_buf = tc6->spi_data_rx_buf; 935 __be32 footer; 936 937 footer = *((__be32 *)&rx_buf[footer_offset]); 938 939 return be32_to_cpu(footer); 940 } 941 942 static int oa_tc6_process_spi_data_rx_buf(struct oa_tc6 *tc6, u16 length) 943 { 944 u16 no_of_rx_chunks = length / OA_TC6_CHUNK_SIZE; 945 u32 footer; 946 int ret; 947 948 /* All the rx chunks in the receive SPI data buffer are examined here */ 949 for (int i = 0; i < no_of_rx_chunks; i++) { 950 /* Last 4 bytes in each received chunk consist footer info */ 951 footer = oa_tc6_get_rx_chunk_footer(tc6, i * OA_TC6_CHUNK_SIZE + 952 OA_TC6_CHUNK_PAYLOAD_SIZE); 953 954 ret = oa_tc6_process_rx_chunk_footer(tc6, footer); 955 if (ret) 956 return ret; 957 958 /* If there is a data valid chunks then process it for the 959 * information needed to determine the validity and the location 960 * of the receive frame data. 961 */ 962 if (FIELD_GET(OA_TC6_DATA_FOOTER_DATA_VALID, footer)) { 963 u8 *payload = tc6->spi_data_rx_buf + i * 964 OA_TC6_CHUNK_SIZE; 965 966 ret = oa_tc6_prcs_rx_chunk_payload(tc6, payload, 967 footer); 968 if (ret) 969 return ret; 970 } 971 } 972 973 return 0; 974 } 975 976 static __be32 oa_tc6_prepare_data_header(bool data_valid, bool start_valid, 977 bool end_valid, u8 end_byte_offset) 978 { 979 u32 header = FIELD_PREP(OA_TC6_DATA_HEADER_DATA_NOT_CTRL, 980 OA_TC6_DATA_HEADER) | 981 FIELD_PREP(OA_TC6_DATA_HEADER_DATA_VALID, data_valid) | 982 FIELD_PREP(OA_TC6_DATA_HEADER_START_VALID, start_valid) | 983 FIELD_PREP(OA_TC6_DATA_HEADER_END_VALID, end_valid) | 984 FIELD_PREP(OA_TC6_DATA_HEADER_END_BYTE_OFFSET, 985 end_byte_offset); 986 987 header |= FIELD_PREP(OA_TC6_DATA_HEADER_PARITY, 988 oa_tc6_get_parity(header)); 989 990 return cpu_to_be32(header); 991 } 992 993 static void oa_tc6_add_tx_skb_to_spi_buf(struct oa_tc6 *tc6) 994 { 995 enum oa_tc6_data_end_valid_info end_valid = OA_TC6_DATA_END_INVALID; 996 __be32 *tx_buf = tc6->spi_data_tx_buf + tc6->spi_data_tx_buf_offset; 997 u16 remaining_len = tc6->ongoing_tx_skb->len - tc6->tx_skb_offset; 998 u8 *tx_skb_data = tc6->ongoing_tx_skb->data + tc6->tx_skb_offset; 999 enum oa_tc6_data_start_valid_info start_valid; 1000 u8 end_byte_offset = 0; 1001 u16 length_to_copy; 1002 1003 /* Initial value is assigned here to avoid more than 80 characters in 1004 * the declaration place. 1005 */ 1006 start_valid = OA_TC6_DATA_START_INVALID; 1007 1008 /* Set start valid if the current tx chunk contains the start of the tx 1009 * ethernet frame. 1010 */ 1011 if (!tc6->tx_skb_offset) 1012 start_valid = OA_TC6_DATA_START_VALID; 1013 1014 /* If the remaining tx skb length is more than the chunk payload size of 1015 * 64 bytes then copy only 64 bytes and leave the ongoing tx skb for 1016 * next tx chunk. 1017 */ 1018 length_to_copy = min_t(u16, remaining_len, OA_TC6_CHUNK_PAYLOAD_SIZE); 1019 1020 /* Copy the tx skb data to the tx chunk payload buffer */ 1021 memcpy(tx_buf + 1, tx_skb_data, length_to_copy); 1022 tc6->tx_skb_offset += length_to_copy; 1023 1024 /* Set end valid if the current tx chunk contains the end of the tx 1025 * ethernet frame. 1026 */ 1027 if (tc6->ongoing_tx_skb->len == tc6->tx_skb_offset) { 1028 end_valid = OA_TC6_DATA_END_VALID; 1029 end_byte_offset = length_to_copy - 1; 1030 tc6->tx_skb_offset = 0; 1031 tc6->netdev->stats.tx_bytes += tc6->ongoing_tx_skb->len; 1032 tc6->netdev->stats.tx_packets++; 1033 kfree_skb(tc6->ongoing_tx_skb); 1034 tc6->ongoing_tx_skb = NULL; 1035 } 1036 1037 *tx_buf = oa_tc6_prepare_data_header(OA_TC6_DATA_VALID, start_valid, 1038 end_valid, end_byte_offset); 1039 tc6->spi_data_tx_buf_offset += OA_TC6_CHUNK_SIZE; 1040 } 1041 1042 static u16 oa_tc6_prepare_spi_tx_buf_for_tx_skbs(struct oa_tc6 *tc6) 1043 { 1044 u16 used_tx_credits; 1045 1046 /* Get tx skbs and convert them into tx chunks based on the tx credits 1047 * available. 1048 */ 1049 for (used_tx_credits = 0; used_tx_credits < tc6->tx_credits; 1050 used_tx_credits++) { 1051 if (!tc6->ongoing_tx_skb) { 1052 spin_lock_bh(&tc6->tx_skb_lock); 1053 tc6->ongoing_tx_skb = tc6->waiting_tx_skb; 1054 tc6->waiting_tx_skb = NULL; 1055 spin_unlock_bh(&tc6->tx_skb_lock); 1056 } 1057 if (!tc6->ongoing_tx_skb) 1058 break; 1059 oa_tc6_add_tx_skb_to_spi_buf(tc6); 1060 } 1061 1062 return used_tx_credits * OA_TC6_CHUNK_SIZE; 1063 } 1064 1065 static void oa_tc6_add_empty_chunks_to_spi_buf(struct oa_tc6 *tc6, 1066 u16 needed_empty_chunks) 1067 { 1068 __be32 header; 1069 1070 header = oa_tc6_prepare_data_header(OA_TC6_DATA_INVALID, 1071 OA_TC6_DATA_START_INVALID, 1072 OA_TC6_DATA_END_INVALID, 0); 1073 1074 while (needed_empty_chunks--) { 1075 __be32 *tx_buf = tc6->spi_data_tx_buf + 1076 tc6->spi_data_tx_buf_offset; 1077 1078 *tx_buf = header; 1079 tc6->spi_data_tx_buf_offset += OA_TC6_CHUNK_SIZE; 1080 } 1081 } 1082 1083 static u16 oa_tc6_prepare_spi_tx_buf_for_rx_chunks(struct oa_tc6 *tc6, u16 len) 1084 { 1085 u16 tx_chunks = len / OA_TC6_CHUNK_SIZE; 1086 u16 needed_empty_chunks; 1087 1088 /* If there are more chunks to receive than to transmit, we need to add 1089 * enough empty tx chunks to allow the reception of the excess rx 1090 * chunks. 1091 */ 1092 if (tx_chunks >= tc6->rx_chunks_available) 1093 return len; 1094 1095 needed_empty_chunks = tc6->rx_chunks_available - tx_chunks; 1096 1097 oa_tc6_add_empty_chunks_to_spi_buf(tc6, needed_empty_chunks); 1098 1099 return needed_empty_chunks * OA_TC6_CHUNK_SIZE + len; 1100 } 1101 1102 static int oa_tc6_try_spi_transfer(struct oa_tc6 *tc6) 1103 { 1104 int ret; 1105 1106 while (true) { 1107 u16 spi_len = 0; 1108 1109 tc6->spi_data_tx_buf_offset = 0; 1110 1111 if (tc6->ongoing_tx_skb || tc6->waiting_tx_skb) 1112 spi_len = oa_tc6_prepare_spi_tx_buf_for_tx_skbs(tc6); 1113 1114 spi_len = oa_tc6_prepare_spi_tx_buf_for_rx_chunks(tc6, spi_len); 1115 1116 if (tc6->int_flag) { 1117 tc6->int_flag = false; 1118 if (spi_len == 0) { 1119 oa_tc6_add_empty_chunks_to_spi_buf(tc6, 1); 1120 spi_len = OA_TC6_CHUNK_SIZE; 1121 } 1122 } 1123 1124 if (spi_len == 0) 1125 break; 1126 1127 ret = oa_tc6_spi_transfer(tc6, OA_TC6_DATA_HEADER, spi_len); 1128 if (ret) { 1129 netdev_err(tc6->netdev, "SPI data transfer failed: %d\n", 1130 ret); 1131 return ret; 1132 } 1133 1134 ret = oa_tc6_process_spi_data_rx_buf(tc6, spi_len); 1135 if (ret) { 1136 if (ret == -EAGAIN) 1137 continue; 1138 1139 oa_tc6_cleanup_ongoing_tx_skb(tc6); 1140 oa_tc6_cleanup_ongoing_rx_skb(tc6); 1141 netdev_err(tc6->netdev, "Device error: %d\n", ret); 1142 return ret; 1143 } 1144 1145 if (!tc6->waiting_tx_skb && netif_queue_stopped(tc6->netdev)) 1146 netif_wake_queue(tc6->netdev); 1147 } 1148 1149 return 0; 1150 } 1151 1152 static irqreturn_t oa_tc6_macphy_threaded_irq(int irq, void *data) 1153 { 1154 struct oa_tc6 *tc6 = data; 1155 int ret = 0; 1156 1157 /* It is possible that interrupt woke the thread before it is 1158 * disabled. Until we come up with good recovery mechanism, 1159 * no need to attempt spi transfer, once it fails. Pending skbs 1160 * are already freed. 1161 */ 1162 if (!tc6->disable_traffic) { 1163 while (tc6->int_flag || 1164 (tc6->waiting_tx_skb && tc6->tx_credits)) { 1165 ret = oa_tc6_try_spi_transfer(tc6); 1166 if (ret) { 1167 disable_irq_nosync(tc6->spi->irq); 1168 oa_tc6_disable_traffic(tc6); 1169 break; 1170 } 1171 } 1172 } 1173 1174 return IRQ_HANDLED; 1175 } 1176 1177 static int oa_tc6_update_buffer_status_from_register(struct oa_tc6 *tc6) 1178 { 1179 u32 value; 1180 int ret; 1181 1182 /* Initially tx credits and rx chunks available to be updated from the 1183 * register as there is no data transfer performed yet. Later they will 1184 * be updated from the rx footer. 1185 */ 1186 ret = oa_tc6_read_register(tc6, OA_TC6_REG_BUFFER_STATUS, &value); 1187 if (ret) 1188 return ret; 1189 1190 tc6->tx_credits = FIELD_GET(BUFFER_STATUS_TX_CREDITS_AVAILABLE, value); 1191 tc6->rx_chunks_available = FIELD_GET(BUFFER_STATUS_RX_CHUNKS_AVAILABLE, 1192 value); 1193 1194 return 0; 1195 } 1196 1197 static irqreturn_t oa_tc6_macphy_isr(int irq, void *data) 1198 { 1199 struct oa_tc6 *tc6 = data; 1200 1201 /* MAC-PHY interrupt can occur for the following reasons. 1202 * - availability of tx credits if it was 0 before and not reported in 1203 * the previous rx footer. 1204 * - availability of rx chunks if it was 0 before and not reported in 1205 * the previous rx footer. 1206 * - extended status event not reported in the previous rx footer. 1207 */ 1208 if (tc6->disable_traffic) 1209 disable_irq_nosync(tc6->spi->irq); 1210 else 1211 tc6->int_flag = true; 1212 /* Wake IRQ thread to perform spi transfer . In case 1213 * disable_traffic is set, threaded irq may run again 1214 * one more time. 1215 */ 1216 return IRQ_WAKE_THREAD; 1217 } 1218 1219 /** 1220 * oa_tc6_zero_align_receive_frame_enable - function to enable zero align 1221 * receive frame feature. 1222 * @tc6: oa_tc6 struct. 1223 * 1224 * Return: 0 on success otherwise failed. 1225 */ 1226 int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6) 1227 { 1228 u32 regval; 1229 int ret; 1230 1231 ret = oa_tc6_read_register(tc6, OA_TC6_REG_CONFIG0, ®val); 1232 if (ret) 1233 return ret; 1234 1235 /* Set Zero-Align Receive Frame Enable */ 1236 regval |= CONFIG0_ZARFE_ENABLE; 1237 1238 return oa_tc6_write_register(tc6, OA_TC6_REG_CONFIG0, regval); 1239 } 1240 EXPORT_SYMBOL_GPL(oa_tc6_zero_align_receive_frame_enable); 1241 1242 /** 1243 * oa_tc6_start_xmit - function for sending the tx skb which consists ethernet 1244 * frame. 1245 * @tc6: oa_tc6 struct. 1246 * @skb: socket buffer in which the ethernet frame is stored. 1247 * 1248 * Return: NETDEV_TX_OK if the transmit ethernet frame skb added in the tx_skb_q 1249 * otherwise returns NETDEV_TX_BUSY. 1250 */ 1251 netdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, struct sk_buff *skb) 1252 { 1253 if (tc6->disable_traffic || tc6->waiting_tx_skb) { 1254 netif_stop_queue(tc6->netdev); 1255 return NETDEV_TX_BUSY; 1256 } 1257 1258 if (skb_linearize(skb)) { 1259 dev_kfree_skb_any(skb); 1260 tc6->netdev->stats.tx_dropped++; 1261 return NETDEV_TX_OK; 1262 } 1263 1264 spin_lock_bh(&tc6->tx_skb_lock); 1265 tc6->waiting_tx_skb = skb; 1266 spin_unlock_bh(&tc6->tx_skb_lock); 1267 1268 /* Wake the threaded IRQ to perform spi transfer. */ 1269 irq_wake_thread(tc6->spi->irq, tc6); 1270 1271 return NETDEV_TX_OK; 1272 } 1273 EXPORT_SYMBOL_GPL(oa_tc6_start_xmit); 1274 1275 /** 1276 * oa_tc6_init - allocates and initializes oa_tc6 structure. 1277 * @spi: device with which data will be exchanged. 1278 * @netdev: network device interface structure. 1279 * 1280 * Return: pointer reference to the oa_tc6 structure if the MAC-PHY 1281 * initialization is successful otherwise NULL. 1282 */ 1283 struct oa_tc6 *oa_tc6_init(struct spi_device *spi, struct net_device *netdev) 1284 { 1285 struct oa_tc6 *tc6; 1286 int ret; 1287 1288 tc6 = devm_kzalloc(&spi->dev, sizeof(*tc6), GFP_KERNEL); 1289 if (!tc6) 1290 return NULL; 1291 1292 tc6->spi = spi; 1293 tc6->netdev = netdev; 1294 SET_NETDEV_DEV(netdev, &spi->dev); 1295 mutex_init(&tc6->spi_ctrl_lock); 1296 spin_lock_init(&tc6->tx_skb_lock); 1297 1298 /* Set the SPI controller to pump at realtime priority */ 1299 tc6->spi->rt = true; 1300 if (spi_setup(tc6->spi) < 0) 1301 return NULL; 1302 1303 tc6->spi_ctrl_tx_buf = devm_kzalloc(&tc6->spi->dev, 1304 OA_TC6_CTRL_SPI_BUF_SIZE, 1305 GFP_KERNEL); 1306 if (!tc6->spi_ctrl_tx_buf) 1307 return NULL; 1308 1309 tc6->spi_ctrl_rx_buf = devm_kzalloc(&tc6->spi->dev, 1310 OA_TC6_CTRL_SPI_BUF_SIZE, 1311 GFP_KERNEL); 1312 if (!tc6->spi_ctrl_rx_buf) 1313 return NULL; 1314 1315 tc6->spi_data_tx_buf = devm_kzalloc(&tc6->spi->dev, 1316 OA_TC6_SPI_DATA_BUF_SIZE, 1317 GFP_KERNEL); 1318 if (!tc6->spi_data_tx_buf) 1319 return NULL; 1320 1321 tc6->spi_data_rx_buf = devm_kzalloc(&tc6->spi->dev, 1322 OA_TC6_SPI_DATA_BUF_SIZE, 1323 GFP_KERNEL); 1324 if (!tc6->spi_data_rx_buf) 1325 return NULL; 1326 1327 ret = oa_tc6_sw_reset_macphy(tc6); 1328 if (ret) { 1329 dev_err(&tc6->spi->dev, 1330 "MAC-PHY software reset failed: %d\n", ret); 1331 return NULL; 1332 } 1333 1334 ret = oa_tc6_unmask_macphy_error_interrupts(tc6); 1335 if (ret) { 1336 dev_err(&tc6->spi->dev, 1337 "MAC-PHY error interrupts unmask failed: %d\n", ret); 1338 return NULL; 1339 } 1340 1341 ret = oa_tc6_phy_init(tc6); 1342 if (ret) { 1343 dev_err(&tc6->spi->dev, 1344 "MAC internal PHY initialization failed: %d\n", ret); 1345 return NULL; 1346 } 1347 1348 ret = oa_tc6_enable_data_transfer(tc6); 1349 if (ret) { 1350 dev_err(&tc6->spi->dev, "Failed to enable data transfer: %d\n", 1351 ret); 1352 goto phy_exit; 1353 } 1354 1355 ret = oa_tc6_update_buffer_status_from_register(tc6); 1356 if (ret) { 1357 dev_err(&tc6->spi->dev, 1358 "Failed to update buffer status: %d\n", ret); 1359 goto phy_exit; 1360 } 1361 1362 ret = devm_request_threaded_irq(&tc6->spi->dev, tc6->spi->irq, 1363 oa_tc6_macphy_isr, 1364 oa_tc6_macphy_threaded_irq, 1365 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1366 dev_name(&tc6->spi->dev), tc6); 1367 if (ret) { 1368 dev_err(&tc6->spi->dev, "Failed to request macphy isr %d\n", 1369 ret); 1370 goto phy_exit; 1371 } 1372 1373 /* oa_tc6_sw_reset_macphy() function resets and clears the MAC-PHY reset 1374 * complete status. IRQ is also asserted on reset completion and it is 1375 * remain asserted until MAC-PHY receives a data chunk. So performing an 1376 * empty data chunk transmission will deassert the IRQ. Refer section 1377 * 7.7 and 9.2.8.8 in the OPEN Alliance specification for more details. 1378 */ 1379 tc6->int_flag = true; 1380 irq_wake_thread(tc6->spi->irq, tc6); 1381 1382 return tc6; 1383 1384 phy_exit: 1385 oa_tc6_phy_exit(tc6); 1386 return NULL; 1387 } 1388 EXPORT_SYMBOL_GPL(oa_tc6_init); 1389 1390 /** 1391 * oa_tc6_exit - exit function. 1392 * @tc6: oa_tc6 struct. 1393 */ 1394 void oa_tc6_exit(struct oa_tc6 *tc6) 1395 { 1396 tc6->disable_traffic = true; 1397 disable_irq(tc6->spi->irq); 1398 oa_tc6_phy_exit(tc6); 1399 oa_tc6_free_pending_skbs(tc6); 1400 } 1401 EXPORT_SYMBOL_GPL(oa_tc6_exit); 1402 1403 MODULE_DESCRIPTION("OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface Lib"); 1404 MODULE_AUTHOR("Parthiban Veerasooran <parthiban.veerasooran@microchip.com>"); 1405 MODULE_LICENSE("GPL"); 1406