1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2011 Jamie Iles
4 *
5 * All enquiries to support@picochip.com
6 */
7 #include <linux/acpi.h>
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/gpio/generic.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/ioport.h>
16 #include <linux/irq.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23
24 #include "gpiolib-acpi.h"
25
26 #define GPIO_SWPORTA_DR 0x00
27 #define GPIO_SWPORTA_DDR 0x04
28 #define GPIO_SWPORTB_DR 0x0c
29 #define GPIO_SWPORTB_DDR 0x10
30 #define GPIO_SWPORTC_DR 0x18
31 #define GPIO_SWPORTC_DDR 0x1c
32 #define GPIO_SWPORTD_DR 0x24
33 #define GPIO_SWPORTD_DDR 0x28
34 #define GPIO_INTEN 0x30
35 #define GPIO_INTMASK 0x34
36 #define GPIO_INTTYPE_LEVEL 0x38
37 #define GPIO_INT_POLARITY 0x3c
38 #define GPIO_INTSTATUS 0x40
39 #define GPIO_PORTA_DEBOUNCE 0x48
40 #define GPIO_PORTA_EOI 0x4c
41 #define GPIO_EXT_PORTA 0x50
42 #define GPIO_EXT_PORTB 0x54
43 #define GPIO_EXT_PORTC 0x58
44 #define GPIO_EXT_PORTD 0x5c
45
46 #define DWAPB_DRIVER_NAME "gpio-dwapb"
47 #define DWAPB_MAX_PORTS 4
48 #define DWAPB_MAX_GPIOS 32
49
50 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
51 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
52 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
53
54 #define GPIO_REG_OFFSET_V1 0
55 #define GPIO_REG_OFFSET_V2 1
56 #define GPIO_REG_OFFSET_MASK BIT(0)
57
58 #define GPIO_INTMASK_V2 0x44
59 #define GPIO_INTTYPE_LEVEL_V2 0x34
60 #define GPIO_INT_POLARITY_V2 0x38
61 #define GPIO_INTSTATUS_V2 0x3c
62 #define GPIO_PORTA_EOI_V2 0x40
63
64 #define DWAPB_NR_CLOCKS 2
65
66 struct dwapb_gpio;
67
68 struct dwapb_port_property {
69 struct fwnode_handle *fwnode;
70 unsigned int idx;
71 unsigned int ngpio;
72 unsigned int gpio_base;
73 int irq[DWAPB_MAX_GPIOS];
74 };
75
76 struct dwapb_platform_data {
77 unsigned int nports;
78 struct dwapb_port_property properties[] __counted_by(nports);
79 };
80
81 /* Store GPIO context across system-wide suspend/resume transitions */
82 struct dwapb_context {
83 u32 data;
84 u32 dir;
85 u32 ext;
86 u32 int_en;
87 u32 int_mask;
88 u32 int_type;
89 u32 int_pol;
90 u32 int_deb;
91 u32 wake_en;
92 };
93
94 struct dwapb_gpio_port_irqchip {
95 unsigned int nr_irqs;
96 unsigned int irq[DWAPB_MAX_GPIOS];
97 };
98
99 struct dwapb_gpio_port {
100 struct gpio_generic_chip chip;
101 struct dwapb_gpio_port_irqchip *pirq;
102 struct dwapb_gpio *gpio;
103 struct dwapb_context *ctx;
104 unsigned int idx;
105 };
106
to_dwapb_gpio(struct gpio_chip * gc)107 static inline struct dwapb_gpio *to_dwapb_gpio(struct gpio_chip *gc)
108 {
109 return container_of(to_gpio_generic_chip(gc),
110 struct dwapb_gpio_port, chip)->gpio;
111 }
112
113 struct dwapb_gpio {
114 struct device *dev;
115 void __iomem *regs;
116 unsigned int nr_ports;
117 unsigned int flags;
118 struct reset_control *rst;
119 struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
120 struct dwapb_gpio_port ports[] __counted_by(nr_ports);
121 };
122
gpio_reg_v2_convert(unsigned int offset)123 static inline u32 gpio_reg_v2_convert(unsigned int offset)
124 {
125 switch (offset) {
126 case GPIO_INTMASK:
127 return GPIO_INTMASK_V2;
128 case GPIO_INTTYPE_LEVEL:
129 return GPIO_INTTYPE_LEVEL_V2;
130 case GPIO_INT_POLARITY:
131 return GPIO_INT_POLARITY_V2;
132 case GPIO_INTSTATUS:
133 return GPIO_INTSTATUS_V2;
134 case GPIO_PORTA_EOI:
135 return GPIO_PORTA_EOI_V2;
136 }
137
138 return offset;
139 }
140
gpio_reg_convert(struct dwapb_gpio * gpio,unsigned int offset)141 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
142 {
143 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)
144 return gpio_reg_v2_convert(offset);
145
146 return offset;
147 }
148
dwapb_read(struct dwapb_gpio * gpio,unsigned int offset)149 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
150 {
151 struct gpio_generic_chip *chip = &gpio->ports[0].chip;
152 void __iomem *reg_base = gpio->regs;
153
154 return gpio_generic_read_reg(chip, reg_base + gpio_reg_convert(gpio, offset));
155 }
156
dwapb_write(struct dwapb_gpio * gpio,unsigned int offset,u32 val)157 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
158 u32 val)
159 {
160 struct gpio_generic_chip *chip = &gpio->ports[0].chip;
161 void __iomem *reg_base = gpio->regs;
162
163 gpio_generic_write_reg(chip, reg_base + gpio_reg_convert(gpio, offset), val);
164 }
165
dwapb_offs_to_port(struct dwapb_gpio * gpio,unsigned int offs)166 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
167 {
168 struct dwapb_gpio_port *port;
169 int i;
170
171 for (i = 0; i < gpio->nr_ports; i++) {
172 port = &gpio->ports[i];
173 if (port->idx == offs / DWAPB_MAX_GPIOS)
174 return port;
175 }
176
177 return NULL;
178 }
179
dwapb_toggle_trigger(struct dwapb_gpio * gpio,unsigned int offs)180 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
181 {
182 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
183 struct gpio_chip *gc;
184 u32 pol;
185 int val;
186
187 if (!port)
188 return;
189 gc = &port->chip.gc;
190
191 pol = dwapb_read(gpio, GPIO_INT_POLARITY);
192 /* Just read the current value right out of the data register */
193 val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
194 if (val)
195 pol &= ~BIT(offs);
196 else
197 pol |= BIT(offs);
198
199 dwapb_write(gpio, GPIO_INT_POLARITY, pol);
200 }
201
dwapb_do_irq(struct dwapb_gpio * gpio)202 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
203 {
204 struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip;
205 unsigned long irq_status;
206 irq_hw_number_t hwirq;
207
208 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
209 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
210 int gpio_irq = irq_find_mapping(gen_gc->gc.irq.domain, hwirq);
211 u32 irq_type = irq_get_trigger_type(gpio_irq);
212
213 generic_handle_irq(gpio_irq);
214
215 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
216 dwapb_toggle_trigger(gpio, hwirq);
217 }
218
219 return irq_status;
220 }
221
dwapb_irq_handler(struct irq_desc * desc)222 static void dwapb_irq_handler(struct irq_desc *desc)
223 {
224 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
225 struct irq_chip *chip = irq_desc_get_chip(desc);
226
227 chained_irq_enter(chip, desc);
228 dwapb_do_irq(gpio);
229 chained_irq_exit(chip, desc);
230 }
231
dwapb_irq_handler_mfd(int irq,void * dev_id)232 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
233 {
234 return IRQ_RETVAL(dwapb_do_irq(dev_id));
235 }
236
dwapb_irq_ack(struct irq_data * d)237 static void dwapb_irq_ack(struct irq_data *d)
238 {
239 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
240 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
241 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
242 u32 val = BIT(irqd_to_hwirq(d));
243
244 guard(gpio_generic_lock_irqsave)(gen_gc);
245
246 dwapb_write(gpio, GPIO_PORTA_EOI, val);
247 }
248
dwapb_irq_mask(struct irq_data * d)249 static void dwapb_irq_mask(struct irq_data *d)
250 {
251 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
252 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
253 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
254 irq_hw_number_t hwirq = irqd_to_hwirq(d);
255 u32 val;
256
257 scoped_guard(gpio_generic_lock_irqsave, gen_gc) {
258 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
259 dwapb_write(gpio, GPIO_INTMASK, val);
260 }
261
262 gpiochip_disable_irq(gc, hwirq);
263 }
264
dwapb_irq_unmask(struct irq_data * d)265 static void dwapb_irq_unmask(struct irq_data *d)
266 {
267 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
268 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
269 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
270 irq_hw_number_t hwirq = irqd_to_hwirq(d);
271 u32 val;
272
273 gpiochip_enable_irq(gc, hwirq);
274
275 guard(gpio_generic_lock_irqsave)(gen_gc);
276
277 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
278 dwapb_write(gpio, GPIO_INTMASK, val);
279 }
280
dwapb_irq_enable(struct irq_data * d)281 static void dwapb_irq_enable(struct irq_data *d)
282 {
283 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
284 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
285 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
286 irq_hw_number_t hwirq = irqd_to_hwirq(d);
287 u32 val;
288
289 guard(gpio_generic_lock_irqsave)(gen_gc);
290
291 val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq);
292 dwapb_write(gpio, GPIO_INTEN, val);
293 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
294 dwapb_write(gpio, GPIO_INTMASK, val);
295 }
296
dwapb_irq_disable(struct irq_data * d)297 static void dwapb_irq_disable(struct irq_data *d)
298 {
299 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
300 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
301 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
302 irq_hw_number_t hwirq = irqd_to_hwirq(d);
303 u32 val;
304
305 guard(gpio_generic_lock_irqsave)(gen_gc);
306
307 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
308 dwapb_write(gpio, GPIO_INTMASK, val);
309 val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq);
310 dwapb_write(gpio, GPIO_INTEN, val);
311 }
312
dwapb_irq_set_type(struct irq_data * d,u32 type)313 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
314 {
315 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
316 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
317 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
318 irq_hw_number_t bit = irqd_to_hwirq(d);
319 unsigned long level, polarity;
320
321 guard(gpio_generic_lock_irqsave)(gen_gc);
322
323 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
324 polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
325
326 switch (type) {
327 case IRQ_TYPE_EDGE_BOTH:
328 level |= BIT(bit);
329 dwapb_toggle_trigger(gpio, bit);
330 break;
331 case IRQ_TYPE_EDGE_RISING:
332 level |= BIT(bit);
333 polarity |= BIT(bit);
334 break;
335 case IRQ_TYPE_EDGE_FALLING:
336 level |= BIT(bit);
337 polarity &= ~BIT(bit);
338 break;
339 case IRQ_TYPE_LEVEL_HIGH:
340 level &= ~BIT(bit);
341 polarity |= BIT(bit);
342 break;
343 case IRQ_TYPE_LEVEL_LOW:
344 level &= ~BIT(bit);
345 polarity &= ~BIT(bit);
346 break;
347 }
348
349 if (type & IRQ_TYPE_LEVEL_MASK)
350 irq_set_handler_locked(d, handle_level_irq);
351 else if (type & IRQ_TYPE_EDGE_BOTH)
352 irq_set_handler_locked(d, handle_edge_irq);
353
354 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
355 if (type != IRQ_TYPE_EDGE_BOTH)
356 dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
357
358 return 0;
359 }
360
dwapb_irq_set_wake(struct irq_data * d,unsigned int enable)361 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
362 {
363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
364 struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
365 struct dwapb_context *ctx = gpio->ports[0].ctx;
366 irq_hw_number_t bit = irqd_to_hwirq(d);
367
368 if (enable)
369 ctx->wake_en |= BIT(bit);
370 else
371 ctx->wake_en &= ~BIT(bit);
372
373 return 0;
374 }
375
376 static const struct irq_chip dwapb_irq_chip = {
377 .name = DWAPB_DRIVER_NAME,
378 .irq_ack = dwapb_irq_ack,
379 .irq_mask = dwapb_irq_mask,
380 .irq_unmask = dwapb_irq_unmask,
381 .irq_set_type = dwapb_irq_set_type,
382 .irq_enable = dwapb_irq_enable,
383 .irq_disable = dwapb_irq_disable,
384 .irq_set_wake = pm_sleep_ptr(dwapb_irq_set_wake),
385 .flags = IRQCHIP_IMMUTABLE,
386 GPIOCHIP_IRQ_RESOURCE_HELPERS,
387 };
388
dwapb_gpio_set_debounce(struct gpio_chip * gc,unsigned offset,unsigned debounce)389 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
390 unsigned offset, unsigned debounce)
391 {
392 struct dwapb_gpio_port *port = gpiochip_get_data(gc);
393 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
394 struct dwapb_gpio *gpio = port->gpio;
395 unsigned long val_deb;
396 unsigned long mask = BIT(offset);
397
398 guard(gpio_generic_lock_irqsave)(gen_gc);
399
400 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
401 if (debounce)
402 val_deb |= mask;
403 else
404 val_deb &= ~mask;
405 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
406
407 return 0;
408 }
409
dwapb_gpio_set_config(struct gpio_chip * gc,unsigned offset,unsigned long config)410 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
411 unsigned long config)
412 {
413 u32 debounce;
414
415 if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {
416 debounce = pinconf_to_config_argument(config);
417 return dwapb_gpio_set_debounce(gc, offset, debounce);
418 }
419
420 return gpiochip_generic_config(gc, offset, config);
421 }
422
dwapb_convert_irqs(struct dwapb_gpio_port_irqchip * pirq,struct dwapb_port_property * pp)423 static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
424 struct dwapb_port_property *pp)
425 {
426 int i;
427
428 /* Group all available IRQs into an array of parental IRQs. */
429 for (i = 0; i < pp->ngpio; ++i) {
430 if (!pp->irq[i])
431 continue;
432
433 pirq->irq[pirq->nr_irqs++] = pp->irq[i];
434 }
435
436 return pirq->nr_irqs ? 0 : -ENOENT;
437 }
438
dwapb_configure_irqs(struct dwapb_gpio * gpio,struct dwapb_gpio_port * port,struct dwapb_port_property * pp)439 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
440 struct dwapb_gpio_port *port,
441 struct dwapb_port_property *pp)
442 {
443 struct dwapb_gpio_port_irqchip *pirq;
444 struct gpio_chip *gc = &port->chip.gc;
445 struct gpio_irq_chip *girq;
446 int err;
447
448 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
449 if (!pirq)
450 return;
451
452 if (dwapb_convert_irqs(pirq, pp)) {
453 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
454 goto err_kfree_pirq;
455 }
456
457 girq = &gc->irq;
458 girq->handler = handle_bad_irq;
459 girq->default_type = IRQ_TYPE_NONE;
460
461 port->pirq = pirq;
462
463 /*
464 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO
465 * IRQ lane shared between several devices. In that case the parental
466 * IRQ has to be handled in the shared way so to be properly delivered
467 * to all the connected devices.
468 */
469 if (has_acpi_companion(gpio->dev)) {
470 girq->num_parents = 0;
471 girq->parents = NULL;
472 girq->parent_handler = NULL;
473
474 err = devm_request_irq(gpio->dev, pp->irq[0],
475 dwapb_irq_handler_mfd,
476 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
477 if (err) {
478 dev_err(gpio->dev, "error requesting IRQ\n");
479 goto err_kfree_pirq;
480 }
481 } else {
482 girq->num_parents = pirq->nr_irqs;
483 girq->parents = pirq->irq;
484 girq->parent_handler_data = gpio;
485 girq->parent_handler = dwapb_irq_handler;
486 }
487
488 gpio_irq_chip_set_chip(girq, &dwapb_irq_chip);
489
490 return;
491
492 err_kfree_pirq:
493 devm_kfree(gpio->dev, pirq);
494 }
495
dwapb_gpio_add_port(struct dwapb_gpio * gpio,struct dwapb_port_property * pp,unsigned int offs)496 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
497 struct dwapb_port_property *pp,
498 unsigned int offs)
499 {
500 struct gpio_generic_chip_config config;
501 struct dwapb_gpio_port *port;
502 void __iomem *dat, *set, *dirout;
503 int err;
504
505 port = &gpio->ports[offs];
506 port->gpio = gpio;
507 port->idx = pp->idx;
508
509 #ifdef CONFIG_PM_SLEEP
510 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
511 if (!port->ctx)
512 return -ENOMEM;
513 #endif
514
515 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
516 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
517 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
518
519 config = (struct gpio_generic_chip_config) {
520 .dev = gpio->dev,
521 .sz = 4,
522 .dat = dat,
523 .set = set,
524 .dirout = dirout,
525 };
526
527 /* This registers 32 GPIO lines per port */
528 err = gpio_generic_chip_init(&port->chip, &config);
529 if (err) {
530 dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
531 port->idx);
532 return err;
533 }
534
535 port->chip.gc.fwnode = pp->fwnode;
536 port->chip.gc.ngpio = pp->ngpio;
537 port->chip.gc.base = pp->gpio_base;
538 port->chip.gc.request = gpiochip_generic_request;
539 port->chip.gc.free = gpiochip_generic_free;
540
541 /* Only port A support debounce */
542 if (pp->idx == 0)
543 port->chip.gc.set_config = dwapb_gpio_set_config;
544 else
545 port->chip.gc.set_config = gpiochip_generic_config;
546
547 /* Only port A can provide interrupts in all configurations of the IP */
548 if (pp->idx == 0)
549 dwapb_configure_irqs(gpio, port, pp);
550
551 err = devm_gpiochip_add_data(gpio->dev, &port->chip.gc, port);
552 if (err) {
553 dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
554 port->idx);
555 return err;
556 }
557
558 return 0;
559 }
560
dwapb_get_irq(struct device * dev,struct fwnode_handle * fwnode,struct dwapb_port_property * pp)561 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
562 struct dwapb_port_property *pp)
563 {
564 int irq, j;
565
566 for (j = 0; j < pp->ngpio; j++) {
567 if (has_acpi_companion(dev))
568 irq = platform_get_irq_optional(to_platform_device(dev), j);
569 else
570 irq = fwnode_irq_get(fwnode, j);
571 if (irq > 0)
572 pp->irq[j] = irq;
573 }
574 }
575
dwapb_gpio_get_pdata(struct device * dev)576 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
577 {
578 struct dwapb_platform_data *pdata;
579 struct dwapb_port_property *pp;
580 int nports;
581 int i;
582
583 nports = device_get_child_node_count(dev);
584 if (nports == 0)
585 return ERR_PTR(-ENODEV);
586
587 pdata = devm_kzalloc(dev, struct_size(pdata, properties, nports), GFP_KERNEL);
588 if (!pdata)
589 return ERR_PTR(-ENOMEM);
590
591 pdata->nports = nports;
592
593 i = 0;
594 device_for_each_child_node_scoped(dev, fwnode) {
595 pp = &pdata->properties[i++];
596 pp->fwnode = fwnode;
597
598 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
599 pp->idx >= DWAPB_MAX_PORTS) {
600 dev_err(dev,
601 "missing/invalid port index for port%d\n", i);
602 return ERR_PTR(-EINVAL);
603 }
604
605 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
606 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
607 dev_info(dev,
608 "failed to get number of gpios for port%d\n",
609 i);
610 pp->ngpio = DWAPB_MAX_GPIOS;
611 }
612
613 pp->gpio_base = -1;
614
615 /* For internal use only, new platforms mustn't exercise this */
616 if (is_software_node(fwnode))
617 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);
618
619 /*
620 * Only port A can provide interrupts in all configurations of
621 * the IP.
622 */
623 if (pp->idx == 0)
624 dwapb_get_irq(dev, fwnode, pp);
625 }
626
627 return pdata;
628 }
629
dwapb_assert_reset(void * data)630 static void dwapb_assert_reset(void *data)
631 {
632 struct dwapb_gpio *gpio = data;
633
634 reset_control_assert(gpio->rst);
635 }
636
dwapb_get_reset(struct dwapb_gpio * gpio)637 static int dwapb_get_reset(struct dwapb_gpio *gpio)
638 {
639 int err;
640
641 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
642 if (IS_ERR(gpio->rst))
643 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
644 "Cannot get reset descriptor\n");
645
646 err = reset_control_deassert(gpio->rst);
647 if (err) {
648 dev_err(gpio->dev, "Cannot deassert reset lane\n");
649 return err;
650 }
651
652 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
653 }
654
dwapb_disable_clks(void * data)655 static void dwapb_disable_clks(void *data)
656 {
657 struct dwapb_gpio *gpio = data;
658
659 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
660 }
661
dwapb_get_clks(struct dwapb_gpio * gpio)662 static int dwapb_get_clks(struct dwapb_gpio *gpio)
663 {
664 int err;
665
666 /* Optional bus and debounce clocks */
667 gpio->clks[0].id = "bus";
668 gpio->clks[1].id = "db";
669 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
670 gpio->clks);
671 if (err)
672 return dev_err_probe(gpio->dev, err,
673 "Cannot get APB/Debounce clocks\n");
674
675 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
676 if (err) {
677 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
678 return err;
679 }
680
681 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
682 }
683
684 static const struct of_device_id dwapb_of_match[] = {
685 { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
686 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
687 { /* Sentinel */ }
688 };
689 MODULE_DEVICE_TABLE(of, dwapb_of_match);
690
691 static const struct acpi_device_id dwapb_acpi_match[] = {
692 {"HISI0181", GPIO_REG_OFFSET_V1},
693 {"APMC0D07", GPIO_REG_OFFSET_V1},
694 {"APMC0D81", GPIO_REG_OFFSET_V2},
695 {"FUJI200A", GPIO_REG_OFFSET_V1},
696 {"LECA0001", GPIO_REG_OFFSET_V1},
697 { }
698 };
699 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
700
dwapb_gpio_probe(struct platform_device * pdev)701 static int dwapb_gpio_probe(struct platform_device *pdev)
702 {
703 unsigned int i;
704 struct dwapb_gpio *gpio;
705 int err;
706 struct dwapb_platform_data *pdata;
707 struct device *dev = &pdev->dev;
708
709 pdata = dwapb_gpio_get_pdata(dev);
710 if (IS_ERR(pdata))
711 return PTR_ERR(pdata);
712
713 gpio = devm_kzalloc(&pdev->dev, struct_size(gpio, ports, pdata->nports), GFP_KERNEL);
714 if (!gpio)
715 return -ENOMEM;
716
717 gpio->nr_ports = pdata->nports;
718 gpio->dev = &pdev->dev;
719
720 err = dwapb_get_reset(gpio);
721 if (err)
722 return err;
723
724 gpio->regs = devm_platform_ioremap_resource(pdev, 0);
725 if (IS_ERR(gpio->regs))
726 return PTR_ERR(gpio->regs);
727
728 err = dwapb_get_clks(gpio);
729 if (err)
730 return err;
731
732 gpio->flags = (uintptr_t)device_get_match_data(dev);
733
734 for (i = 0; i < gpio->nr_ports; i++) {
735 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
736 if (err)
737 return err;
738 }
739
740 platform_set_drvdata(pdev, gpio);
741
742 return 0;
743 }
744
dwapb_gpio_suspend(struct device * dev)745 static int dwapb_gpio_suspend(struct device *dev)
746 {
747 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
748 struct gpio_generic_chip *gen_gc = &gpio->ports[0].chip;
749 int i;
750
751 scoped_guard(gpio_generic_lock_irqsave, gen_gc) {
752 for (i = 0; i < gpio->nr_ports; i++) {
753 unsigned int offset;
754 unsigned int idx = gpio->ports[i].idx;
755 struct dwapb_context *ctx = gpio->ports[i].ctx;
756
757 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
758 ctx->dir = dwapb_read(gpio, offset);
759
760 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
761 ctx->data = dwapb_read(gpio, offset);
762
763 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
764 ctx->ext = dwapb_read(gpio, offset);
765
766 /* Only port A can provide interrupts */
767 if (idx == 0) {
768 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
769 ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
770 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
771 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
772 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
773
774 /* Mask out interrupts */
775 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
776 }
777 }
778 }
779
780 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
781
782 return 0;
783 }
784
dwapb_gpio_resume(struct device * dev)785 static int dwapb_gpio_resume(struct device *dev)
786 {
787 struct dwapb_gpio *gpio = dev_get_drvdata(dev);
788 struct gpio_chip *gc = &gpio->ports[0].chip.gc;
789 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(gc);
790 int i, err;
791
792 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
793 if (err) {
794 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
795 return err;
796 }
797
798 guard(gpio_generic_lock_irqsave)(gen_gc);
799
800 for (i = 0; i < gpio->nr_ports; i++) {
801 unsigned int offset;
802 unsigned int idx = gpio->ports[i].idx;
803 struct dwapb_context *ctx = gpio->ports[i].ctx;
804
805 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
806 dwapb_write(gpio, offset, ctx->data);
807
808 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
809 dwapb_write(gpio, offset, ctx->dir);
810
811 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
812 dwapb_write(gpio, offset, ctx->ext);
813
814 /* Only port A can provide interrupts */
815 if (idx == 0) {
816 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
817 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
818 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
819 dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
820 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
821
822 /* Clear out spurious interrupts */
823 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
824 }
825 }
826
827 return 0;
828 }
829
830 static DEFINE_SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops,
831 dwapb_gpio_suspend, dwapb_gpio_resume);
832
833 static struct platform_driver dwapb_gpio_driver = {
834 .driver = {
835 .name = DWAPB_DRIVER_NAME,
836 .pm = pm_sleep_ptr(&dwapb_gpio_pm_ops),
837 .of_match_table = dwapb_of_match,
838 .acpi_match_table = dwapb_acpi_match,
839 },
840 .probe = dwapb_gpio_probe,
841 };
842
843 module_platform_driver(dwapb_gpio_driver);
844
845 MODULE_LICENSE("GPL");
846 MODULE_AUTHOR("Jamie Iles");
847 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
848 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);
849