1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* ppc-opc.c -- PowerPC opcode list
3 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 */
9
10 #include <linux/stddef.h>
11 #include <linux/kernel.h>
12 #include <linux/bug.h>
13 #include "nonstdio.h"
14 #include "ppc.h"
15
16 #define ATTRIBUTE_UNUSED
17 #define _(x) x
18
19 /* This file holds the PowerPC opcode table. The opcode table
20 includes almost all of the extended instruction mnemonics. This
21 permits the disassembler to use them, and simplifies the assembler
22 logic, at the cost of increasing the table size. The table is
23 strictly constant data, so the compiler should be able to put it in
24 the .text section.
25
26 This file also holds the operand table. All knowledge about
27 inserting operands into instructions and vice-versa is kept in this
28 file. */
29
30 /* Local insertion and extraction functions. */
31
32 static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
33 static long extract_arx (unsigned long, ppc_cpu_t, int *);
34 static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
35 static long extract_ary (unsigned long, ppc_cpu_t, int *);
36 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
37 static long extract_bat (unsigned long, ppc_cpu_t, int *);
38 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
39 static long extract_bba (unsigned long, ppc_cpu_t, int *);
40 static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **);
41 static long extract_bdm (unsigned long, ppc_cpu_t, int *);
42 static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **);
43 static long extract_bdp (unsigned long, ppc_cpu_t, int *);
44 static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **);
45 static long extract_bo (unsigned long, ppc_cpu_t, int *);
46 static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **);
47 static long extract_boe (unsigned long, ppc_cpu_t, int *);
48 static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **);
49 static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **);
50 static long extract_dcmxs (unsigned long, ppc_cpu_t, int *);
51 static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **);
52 static long extract_dxd (unsigned long, ppc_cpu_t, int *);
53 static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **);
54 static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
55 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
56 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
57 static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
58 static long extract_li20 (unsigned long, ppc_cpu_t, int *);
59 static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
60 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
61 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
62 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
63 static long extract_mb6 (unsigned long, ppc_cpu_t, int *);
64 static long extract_nb (unsigned long, ppc_cpu_t, int *);
65 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
66 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
67 static long extract_nsi (unsigned long, ppc_cpu_t, int *);
68 static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
69 static long extract_oimm (unsigned long, ppc_cpu_t, int *);
70 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
71 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
72 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
73 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
74 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
75 static long extract_rbs (unsigned long, ppc_cpu_t, int *);
76 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
77 static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
78 static long extract_rx (unsigned long, ppc_cpu_t, int *);
79 static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
80 static long extract_ry (unsigned long, ppc_cpu_t, int *);
81 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
82 static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
83 static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
84 static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
85 static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
86 static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
87 static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
88 static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
89 static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
90 static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
91 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
92 static long extract_spr (unsigned long, ppc_cpu_t, int *);
93 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
94 static long extract_sprg (unsigned long, ppc_cpu_t, int *);
95 static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
96 static long extract_tbr (unsigned long, ppc_cpu_t, int *);
97 static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
98 static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
99 static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **);
100 static long extract_xtq6 (unsigned long, ppc_cpu_t, int *);
101 static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
102 static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
103 static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
104 static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
105 static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
106 static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
107 static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **);
108 static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
109 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
110 static long extract_dm (unsigned long, ppc_cpu_t, int *);
111 static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
112 static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
113 static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
114 static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
115 static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
116 static long extract_vleui (unsigned long, ppc_cpu_t, int *);
117 static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
118 static long extract_vleil (unsigned long, ppc_cpu_t, int *);
119
120 /* The operands table.
121
122 The fields are bitm, shift, insert, extract, flags.
123
124 We used to put parens around the various additions, like the one
125 for BA just below. However, that caused trouble with feeble
126 compilers with a limit on depth of a parenthesized expression, like
127 (reportedly) the compiler in Microsoft Developer Studio 5. So we
128 omit the parens, since the macros are never used in a context where
129 the addition will be ambiguous. */
130
131 const struct powerpc_operand powerpc_operands[] =
132 {
133 /* The zero index is used to indicate the end of the list of
134 operands. */
135 #define UNUSED 0
136 { 0, 0, NULL, NULL, 0 },
137
138 /* The BA field in an XL form instruction. */
139 #define BA UNUSED + 1
140 /* The BI field in a B form or XL form instruction. */
141 #define BI BA
142 #define BI_MASK (0x1f << 16)
143 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
144
145 /* The BA field in an XL form instruction when it must be the same
146 as the BT field in the same instruction. */
147 #define BAT BA + 1
148 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
149
150 /* The BB field in an XL form instruction. */
151 #define BB BAT + 1
152 #define BB_MASK (0x1f << 11)
153 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
154
155 /* The BB field in an XL form instruction when it must be the same
156 as the BA field in the same instruction. */
157 #define BBA BB + 1
158 /* The VB field in a VX form instruction when it must be the same
159 as the VA field in the same instruction. */
160 #define VBA BBA
161 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
162
163 /* The BD field in a B form instruction. The lower two bits are
164 forced to zero. */
165 #define BD BBA + 1
166 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
167
168 /* The BD field in a B form instruction when absolute addressing is
169 used. */
170 #define BDA BD + 1
171 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
172
173 /* The BD field in a B form instruction when the - modifier is used.
174 This sets the y bit of the BO field appropriately. */
175 #define BDM BDA + 1
176 { 0xfffc, 0, insert_bdm, extract_bdm,
177 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
178
179 /* The BD field in a B form instruction when the - modifier is used
180 and absolute address is used. */
181 #define BDMA BDM + 1
182 { 0xfffc, 0, insert_bdm, extract_bdm,
183 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
184
185 /* The BD field in a B form instruction when the + modifier is used.
186 This sets the y bit of the BO field appropriately. */
187 #define BDP BDMA + 1
188 { 0xfffc, 0, insert_bdp, extract_bdp,
189 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
190
191 /* The BD field in a B form instruction when the + modifier is used
192 and absolute addressing is used. */
193 #define BDPA BDP + 1
194 { 0xfffc, 0, insert_bdp, extract_bdp,
195 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
196
197 /* The BF field in an X or XL form instruction. */
198 #define BF BDPA + 1
199 /* The CRFD field in an X form instruction. */
200 #define CRFD BF
201 /* The CRD field in an XL form instruction. */
202 #define CRD BF
203 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
204
205 /* The BF field in an X or XL form instruction. */
206 #define BFF BF + 1
207 { 0x7, 23, NULL, NULL, 0 },
208
209 /* An optional BF field. This is used for comparison instructions,
210 in which an omitted BF field is taken as zero. */
211 #define OBF BFF + 1
212 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
213
214 /* The BFA field in an X or XL form instruction. */
215 #define BFA OBF + 1
216 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
217
218 /* The BO field in a B form instruction. Certain values are
219 illegal. */
220 #define BO BFA + 1
221 #define BO_MASK (0x1f << 21)
222 { 0x1f, 21, insert_bo, extract_bo, 0 },
223
224 /* The BO field in a B form instruction when the + or - modifier is
225 used. This is like the BO field, but it must be even. */
226 #define BOE BO + 1
227 { 0x1e, 21, insert_boe, extract_boe, 0 },
228
229 /* The RM field in an X form instruction. */
230 #define RM BOE + 1
231 { 0x3, 11, NULL, NULL, 0 },
232
233 #define BH RM + 1
234 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
235
236 /* The BT field in an X or XL form instruction. */
237 #define BT BH + 1
238 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
239
240 /* The BI16 field in a BD8 form instruction. */
241 #define BI16 BT + 1
242 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
243
244 /* The BI32 field in a BD15 form instruction. */
245 #define BI32 BI16 + 1
246 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
247
248 /* The BO32 field in a BD15 form instruction. */
249 #define BO32 BI32 + 1
250 { 0x3, 20, NULL, NULL, 0 },
251
252 /* The B8 field in a BD8 form instruction. */
253 #define B8 BO32 + 1
254 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
255
256 /* The B15 field in a BD15 form instruction. The lowest bit is
257 forced to zero. */
258 #define B15 B8 + 1
259 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
260
261 /* The B24 field in a BD24 form instruction. The lowest bit is
262 forced to zero. */
263 #define B24 B15 + 1
264 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
265
266 /* The condition register number portion of the BI field in a B form
267 or XL form instruction. This is used for the extended
268 conditional branch mnemonics, which set the lower two bits of the
269 BI field. This field is optional. */
270 #define CR B24 + 1
271 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
272
273 /* The CRB field in an X form instruction. */
274 #define CRB CR + 1
275 /* The MB field in an M form instruction. */
276 #define MB CRB
277 #define MB_MASK (0x1f << 6)
278 { 0x1f, 6, NULL, NULL, 0 },
279
280 /* The CRD32 field in an XL form instruction. */
281 #define CRD32 CRB + 1
282 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
283
284 /* The CRFS field in an X form instruction. */
285 #define CRFS CRD32 + 1
286 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
287
288 #define CRS CRFS + 1
289 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
290
291 /* The CT field in an X form instruction. */
292 #define CT CRS + 1
293 /* The MO field in an mbar instruction. */
294 #define MO CT
295 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
296
297 /* The D field in a D form instruction. This is a displacement off
298 a register, and implies that the next operand is a register in
299 parentheses. */
300 #define D CT + 1
301 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
302
303 /* The D8 field in a D form instruction. This is a displacement off
304 a register, and implies that the next operand is a register in
305 parentheses. */
306 #define D8 D + 1
307 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
308
309 /* The DCMX field in an X form instruction. */
310 #define DCMX D8 + 1
311 { 0x7f, 16, NULL, NULL, 0 },
312
313 /* The split DCMX field in an X form instruction. */
314 #define DCMXS DCMX + 1
315 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 },
316
317 /* The DQ field in a DQ form instruction. This is like D, but the
318 lower four bits are forced to zero. */
319 #define DQ DCMXS + 1
320 { 0xfff0, 0, NULL, NULL,
321 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
322
323 /* The DS field in a DS form instruction. This is like D, but the
324 lower two bits are forced to zero. */
325 #define DS DQ + 1
326 { 0xfffc, 0, NULL, NULL,
327 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
328
329 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits
330 unsigned imediate */
331 #define DUIS DS + 1
332 #define BHRBE DUIS
333 { 0x3ff, 11, NULL, NULL, 0 },
334
335 /* The split D field in a DX form instruction. */
336 #define DXD DUIS + 1
337 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd,
338 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
339
340 /* The split ND field in a DX form instruction.
341 This is the same as the DX field, only negated. */
342 #define NDXD DXD + 1
343 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn,
344 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT},
345
346 /* The E field in a wrteei instruction. */
347 /* And the W bit in the pair singles instructions. */
348 /* And the ST field in a VX form instruction. */
349 #define E NDXD + 1
350 #define PSW E
351 #define ST E
352 { 0x1, 15, NULL, NULL, 0 },
353
354 /* The FL1 field in a POWER SC form instruction. */
355 #define FL1 E + 1
356 /* The U field in an X form instruction. */
357 #define U FL1
358 { 0xf, 12, NULL, NULL, 0 },
359
360 /* The FL2 field in a POWER SC form instruction. */
361 #define FL2 FL1 + 1
362 { 0x7, 2, NULL, NULL, 0 },
363
364 /* The FLM field in an XFL form instruction. */
365 #define FLM FL2 + 1
366 { 0xff, 17, NULL, NULL, 0 },
367
368 /* The FRA field in an X or A form instruction. */
369 #define FRA FLM + 1
370 #define FRA_MASK (0x1f << 16)
371 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
372
373 /* The FRAp field of DFP instructions. */
374 #define FRAp FRA + 1
375 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR },
376
377 /* The FRB field in an X or A form instruction. */
378 #define FRB FRAp + 1
379 #define FRB_MASK (0x1f << 11)
380 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
381
382 /* The FRBp field of DFP instructions. */
383 #define FRBp FRB + 1
384 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR },
385
386 /* The FRC field in an A form instruction. */
387 #define FRC FRBp + 1
388 #define FRC_MASK (0x1f << 6)
389 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
390
391 /* The FRS field in an X form instruction or the FRT field in a D, X
392 or A form instruction. */
393 #define FRS FRC + 1
394 #define FRT FRS
395 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
396
397 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP
398 instructions. */
399 #define FRSp FRS + 1
400 #define FRTp FRSp
401 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR },
402
403 /* The FXM field in an XFX instruction. */
404 #define FXM FRSp + 1
405 { 0xff, 12, insert_fxm, extract_fxm, 0 },
406
407 /* Power4 version for mfcr. */
408 #define FXM4 FXM + 1
409 { 0xff, 12, insert_fxm, extract_fxm,
410 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
411 /* If the FXM4 operand is omitted, use the sentinel value -1. */
412 { -1, -1, NULL, NULL, 0},
413
414 /* The IMM20 field in an LI instruction. */
415 #define IMM20 FXM4 + 2
416 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
417
418 /* The L field in a D or X form instruction. */
419 #define L IMM20 + 1
420 { 0x1, 21, NULL, NULL, 0 },
421
422 /* The optional L field in tlbie and tlbiel instructions. */
423 #define LOPT L + 1
424 /* The R field in a HTM X form instruction. */
425 #define HTM_R LOPT
426 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
427
428 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
429 #define L32OPT LOPT + 1
430 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
431
432 /* The L field in dcbf instruction. */
433 #define L2OPT L32OPT + 1
434 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
435
436 /* The LEV field in a POWER SVC form instruction. */
437 #define SVC_LEV L2OPT + 1
438 { 0x7f, 5, NULL, NULL, 0 },
439
440 /* The LEV field in an SC form instruction. */
441 #define LEV SVC_LEV + 1
442 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
443
444 /* The LI field in an I form instruction. The lower two bits are
445 forced to zero. */
446 #define LI LEV + 1
447 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
448
449 /* The LI field in an I form instruction when used as an absolute
450 address. */
451 #define LIA LI + 1
452 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
453
454 /* The LS or WC field in an X (sync or wait) form instruction. */
455 #define LS LIA + 1
456 #define WC LS
457 { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL },
458
459 /* The ME field in an M form instruction. */
460 #define ME LS + 1
461 #define ME_MASK (0x1f << 1)
462 { 0x1f, 1, NULL, NULL, 0 },
463
464 /* The MB and ME fields in an M form instruction expressed a single
465 operand which is a bitmask indicating which bits to select. This
466 is a two operand form using PPC_OPERAND_NEXT. See the
467 description in opcode/ppc.h for what this means. */
468 #define MBE ME + 1
469 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
470 { -1, 0, insert_mbe, extract_mbe, 0 },
471
472 /* The MB or ME field in an MD or MDS form instruction. The high
473 bit is wrapped to the low end. */
474 #define MB6 MBE + 2
475 #define ME6 MB6
476 #define MB6_MASK (0x3f << 5)
477 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
478
479 /* The NB field in an X form instruction. The value 32 is stored as
480 0. */
481 #define NB MB6 + 1
482 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
483
484 /* The NBI field in an lswi instruction, which has special value
485 restrictions. The value 32 is stored as 0. */
486 #define NBI NB + 1
487 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 },
488
489 /* The NSI field in a D form instruction. This is the same as the
490 SI field, only negated. */
491 #define NSI NBI + 1
492 { 0xffff, 0, insert_nsi, extract_nsi,
493 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
494
495 /* The NSI field in a D form instruction when we accept a wide range
496 of positive values. */
497 #define NSISIGNOPT NSI + 1
498 { 0xffff, 0, insert_nsi, extract_nsi,
499 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
500
501 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
502 #define RA NSISIGNOPT + 1
503 #define RA_MASK (0x1f << 16)
504 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
505
506 /* As above, but 0 in the RA field means zero, not r0. */
507 #define RA0 RA + 1
508 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
509
510 /* The RA field in the DQ form lq or an lswx instruction, which have special
511 value restrictions. */
512 #define RAQ RA0 + 1
513 #define RAX RAQ
514 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
515
516 /* The RA field in a D or X form instruction which is an updating
517 load, which means that the RA field may not be zero and may not
518 equal the RT field. */
519 #define RAL RAQ + 1
520 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
521
522 /* The RA field in an lmw instruction, which has special value
523 restrictions. */
524 #define RAM RAL + 1
525 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
526
527 /* The RA field in a D or X form instruction which is an updating
528 store or an updating floating point load, which means that the RA
529 field may not be zero. */
530 #define RAS RAM + 1
531 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
532
533 /* The RA field of the tlbwe, dccci and iccci instructions,
534 which are optional. */
535 #define RAOPT RAS + 1
536 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
537
538 /* The RB field in an X, XO, M, or MDS form instruction. */
539 #define RB RAOPT + 1
540 #define RB_MASK (0x1f << 11)
541 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
542
543 /* The RB field in an X form instruction when it must be the same as
544 the RS field in the instruction. This is used for extended
545 mnemonics like mr. */
546 #define RBS RB + 1
547 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
548
549 /* The RB field in an lswx instruction, which has special value
550 restrictions. */
551 #define RBX RBS + 1
552 { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR },
553
554 /* The RB field of the dccci and iccci instructions, which are optional. */
555 #define RBOPT RBX + 1
556 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
557
558 /* The RC register field in an maddld, maddhd or maddhdu instruction. */
559 #define RC RBOPT + 1
560 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR },
561
562 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
563 instruction or the RT field in a D, DS, X, XFX or XO form
564 instruction. */
565 #define RS RC + 1
566 #define RT RS
567 #define RT_MASK (0x1f << 21)
568 #define RD RS
569 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
570
571 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
572 which have special value restrictions. */
573 #define RSQ RS + 1
574 #define RTQ RSQ
575 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
576
577 /* The RS field of the tlbwe instruction, which is optional. */
578 #define RSO RSQ + 1
579 #define RTO RSO
580 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
581
582 /* The RX field of the SE_RR form instruction. */
583 #define RX RSO + 1
584 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
585
586 /* The ARX field of the SE_RR form instruction. */
587 #define ARX RX + 1
588 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
589
590 /* The RY field of the SE_RR form instruction. */
591 #define RY ARX + 1
592 #define RZ RY
593 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
594
595 /* The ARY field of the SE_RR form instruction. */
596 #define ARY RY + 1
597 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
598
599 /* The SCLSCI8 field in a D form instruction. */
600 #define SCLSCI8 ARY + 1
601 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
602
603 /* The SCLSCI8N field in a D form instruction. This is the same as the
604 SCLSCI8 field, only negated. */
605 #define SCLSCI8N SCLSCI8 + 1
606 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
607 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
608
609 /* The SD field of the SD4 form instruction. */
610 #define SE_SD SCLSCI8N + 1
611 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
612
613 /* The SD field of the SD4 form instruction, for halfword. */
614 #define SE_SDH SE_SD + 1
615 { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
616
617 /* The SD field of the SD4 form instruction, for word. */
618 #define SE_SDW SE_SDH + 1
619 { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
620
621 /* The SH field in an X or M form instruction. */
622 #define SH SE_SDW + 1
623 #define SH_MASK (0x1f << 11)
624 /* The other UIMM field in a EVX form instruction. */
625 #define EVUIMM SH
626 /* The FC field in an atomic X form instruction. */
627 #define FC SH
628 { 0x1f, 11, NULL, NULL, 0 },
629
630 /* The SI field in a HTM X form instruction. */
631 #define HTM_SI SH + 1
632 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
633
634 /* The SH field in an MD form instruction. This is split. */
635 #define SH6 HTM_SI + 1
636 #define SH6_MASK ((0x1f << 11) | (1 << 1))
637 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
638
639 /* The SH field of the tlbwe instruction, which is optional. */
640 #define SHO SH6 + 1
641 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
642
643 /* The SI field in a D form instruction. */
644 #define SI SHO + 1
645 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
646
647 /* The SI field in a D form instruction when we accept a wide range
648 of positive values. */
649 #define SISIGNOPT SI + 1
650 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
651
652 /* The SI8 field in a D form instruction. */
653 #define SI8 SISIGNOPT + 1
654 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
655
656 /* The SPR field in an XFX form instruction. This is flipped--the
657 lower 5 bits are stored in the upper 5 and vice- versa. */
658 #define SPR SI8 + 1
659 #define PMR SPR
660 #define TMR SPR
661 #define SPR_MASK (0x3ff << 11)
662 { 0x3ff, 11, insert_spr, extract_spr, 0 },
663
664 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
665 #define SPRBAT SPR + 1
666 #define SPRBAT_MASK (0x3 << 17)
667 { 0x3, 17, NULL, NULL, 0 },
668
669 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
670 #define SPRG SPRBAT + 1
671 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
672
673 /* The SR field in an X form instruction. */
674 #define SR SPRG + 1
675 /* The 4-bit UIMM field in a VX form instruction. */
676 #define UIMM4 SR
677 { 0xf, 16, NULL, NULL, 0 },
678
679 /* The STRM field in an X AltiVec form instruction. */
680 #define STRM SR + 1
681 /* The T field in a tlbilx form instruction. */
682 #define T STRM
683 /* The L field in wclr instructions. */
684 #define L2 STRM
685 { 0x3, 21, NULL, NULL, 0 },
686
687 /* The ESYNC field in an X (sync) form instruction. */
688 #define ESYNC STRM + 1
689 { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL },
690
691 /* The SV field in a POWER SC form instruction. */
692 #define SV ESYNC + 1
693 { 0x3fff, 2, NULL, NULL, 0 },
694
695 /* The TBR field in an XFX form instruction. This is like the SPR
696 field, but it is optional. */
697 #define TBR SV + 1
698 { 0x3ff, 11, insert_tbr, extract_tbr,
699 PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
700 /* If the TBR operand is ommitted, use the value 268. */
701 { -1, 268, NULL, NULL, 0},
702
703 /* The TO field in a D or X form instruction. */
704 #define TO TBR + 2
705 #define DUI TO
706 #define TO_MASK (0x1f << 21)
707 { 0x1f, 21, NULL, NULL, 0 },
708
709 /* The UI field in a D form instruction. */
710 #define UI TO + 1
711 { 0xffff, 0, NULL, NULL, 0 },
712
713 #define UISIGNOPT UI + 1
714 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT },
715
716 /* The IMM field in an SE_IM5 instruction. */
717 #define UI5 UISIGNOPT + 1
718 { 0x1f, 4, NULL, NULL, 0 },
719
720 /* The OIMM field in an SE_OIM5 instruction. */
721 #define OIMM5 UI5 + 1
722 { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
723
724 /* The UI7 field in an SE_LI instruction. */
725 #define UI7 OIMM5 + 1
726 { 0x7f, 4, NULL, NULL, 0 },
727
728 /* The VA field in a VA, VX or VXR form instruction. */
729 #define VA UI7 + 1
730 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
731
732 /* The VB field in a VA, VX or VXR form instruction. */
733 #define VB VA + 1
734 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
735
736 /* The VC field in a VA form instruction. */
737 #define VC VB + 1
738 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
739
740 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
741 #define VD VC + 1
742 #define VS VD
743 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
744
745 /* The SIMM field in a VX form instruction, and TE in Z form. */
746 #define SIMM VD + 1
747 #define TE SIMM
748 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
749
750 /* The UIMM field in a VX form instruction. */
751 #define UIMM SIMM + 1
752 #define DCTL UIMM
753 { 0x1f, 16, NULL, NULL, 0 },
754
755 /* The 3-bit UIMM field in a VX form instruction. */
756 #define UIMM3 UIMM + 1
757 { 0x7, 16, NULL, NULL, 0 },
758
759 /* The 6-bit UIM field in a X form instruction. */
760 #define UIM6 UIMM3 + 1
761 { 0x3f, 16, NULL, NULL, 0 },
762
763 /* The SIX field in a VX form instruction. */
764 #define SIX UIM6 + 1
765 { 0xf, 11, NULL, NULL, 0 },
766
767 /* The PS field in a VX form instruction. */
768 #define PS SIX + 1
769 { 0x1, 9, NULL, NULL, 0 },
770
771 /* The SHB field in a VA form instruction. */
772 #define SHB PS + 1
773 { 0xf, 6, NULL, NULL, 0 },
774
775 /* The other UIMM field in a half word EVX form instruction. */
776 #define EVUIMM_2 SHB + 1
777 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
778
779 /* The other UIMM field in a word EVX form instruction. */
780 #define EVUIMM_4 EVUIMM_2 + 1
781 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
782
783 /* The other UIMM field in a double EVX form instruction. */
784 #define EVUIMM_8 EVUIMM_4 + 1
785 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
786
787 /* The WS or DRM field in an X form instruction. */
788 #define WS EVUIMM_8 + 1
789 #define DRM WS
790 { 0x7, 11, NULL, NULL, 0 },
791
792 /* PowerPC paired singles extensions. */
793 /* W bit in the pair singles instructions for x type instructions. */
794 #define PSWM WS + 1
795 /* The BO16 field in a BD8 form instruction. */
796 #define BO16 PSWM
797 { 0x1, 10, 0, 0, 0 },
798
799 /* IDX bits for quantization in the pair singles instructions. */
800 #define PSQ PSWM + 1
801 { 0x7, 12, 0, 0, 0 },
802
803 /* IDX bits for quantization in the pair singles x-type instructions. */
804 #define PSQM PSQ + 1
805 { 0x7, 7, 0, 0, 0 },
806
807 /* Smaller D field for quantization in the pair singles instructions. */
808 #define PSD PSQM + 1
809 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
810
811 /* The L field in an mtmsrd or A form instruction or R or W in an X form. */
812 #define A_L PSD + 1
813 #define W A_L
814 #define X_R A_L
815 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
816
817 /* The RMC or CY field in a Z23 form instruction. */
818 #define RMC A_L + 1
819 #define CY RMC
820 { 0x3, 9, NULL, NULL, 0 },
821
822 #define R RMC + 1
823 { 0x1, 16, NULL, NULL, 0 },
824
825 #define RIC R + 1
826 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL },
827
828 #define PRS RIC + 1
829 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
830
831 #define SP PRS + 1
832 { 0x3, 19, NULL, NULL, 0 },
833
834 #define S SP + 1
835 { 0x1, 20, NULL, NULL, 0 },
836
837 /* The S field in a XL form instruction. */
838 #define SXL S + 1
839 { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE},
840 /* If the SXL operand is ommitted, use the value 1. */
841 { -1, 1, NULL, NULL, 0},
842
843 /* SH field starting at bit position 16. */
844 #define SH16 SXL + 2
845 /* The DCM and DGM fields in a Z form instruction. */
846 #define DCM SH16
847 #define DGM DCM
848 { 0x3f, 10, NULL, NULL, 0 },
849
850 /* The EH field in larx instruction. */
851 #define EH SH16 + 1
852 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
853
854 /* The L field in an mtfsf or XFL form instruction. */
855 /* The A field in a HTM X form instruction. */
856 #define XFL_L EH + 1
857 #define HTM_A XFL_L
858 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
859
860 /* Xilinx APU related masks and macros */
861 #define FCRT XFL_L + 1
862 #define FCRT_MASK (0x1f << 21)
863 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
864
865 /* Xilinx FSL related masks and macros */
866 #define FSL FCRT + 1
867 #define FSL_MASK (0x1f << 11)
868 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
869
870 /* Xilinx UDI related masks and macros */
871 #define URT FSL + 1
872 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
873
874 #define URA URT + 1
875 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
876
877 #define URB URA + 1
878 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
879
880 #define URC URB + 1
881 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
882
883 /* The VLESIMM field in a D form instruction. */
884 #define VLESIMM URC + 1
885 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
886 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
887
888 /* The VLENSIMM field in a D form instruction. */
889 #define VLENSIMM VLESIMM + 1
890 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
891 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
892
893 /* The VLEUIMM field in a D form instruction. */
894 #define VLEUIMM VLENSIMM + 1
895 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
896
897 /* The VLEUIMML field in a D form instruction. */
898 #define VLEUIMML VLEUIMM + 1
899 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
900
901 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
902 #define XS6 VLEUIMML + 1
903 #define XT6 XS6
904 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
905
906 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
907 #define XSQ6 XT6 + 1
908 #define XTQ6 XSQ6
909 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR },
910
911 /* The XA field in an XX3 form instruction. This is split. */
912 #define XA6 XTQ6 + 1
913 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
914
915 /* The XB field in an XX2 or XX3 form instruction. This is split. */
916 #define XB6 XA6 + 1
917 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
918
919 /* The XB field in an XX3 form instruction when it must be the same as
920 the XA field in the instruction. This is used in extended mnemonics
921 like xvmovdp. This is split. */
922 #define XB6S XB6 + 1
923 { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
924
925 /* The XC field in an XX4 form instruction. This is split. */
926 #define XC6 XB6S + 1
927 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
928
929 /* The DM or SHW field in an XX3 form instruction. */
930 #define DM XC6 + 1
931 #define SHW DM
932 { 0x3, 8, NULL, NULL, 0 },
933
934 /* The DM field in an extended mnemonic XX3 form instruction. */
935 #define DMEX DM + 1
936 { 0x3, 8, insert_dm, extract_dm, 0 },
937
938 /* The UIM field in an XX2 form instruction. */
939 #define UIM DMEX + 1
940 /* The 2-bit UIMM field in a VX form instruction. */
941 #define UIMM2 UIM
942 /* The 2-bit L field in a darn instruction. */
943 #define LRAND UIM
944 { 0x3, 16, NULL, NULL, 0 },
945
946 #define ERAT_T UIM + 1
947 { 0x7, 21, NULL, NULL, 0 },
948
949 #define IH ERAT_T + 1
950 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
951
952 /* The 8-bit IMM8 field in a XX1 form instruction. */
953 #define IMM8 IH + 1
954 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
955 };
956
957 const unsigned int num_powerpc_operands = ARRAY_SIZE(powerpc_operands);
958
959 /* The functions used to insert and extract complicated operands. */
960
961 /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */
962
963 static unsigned long
insert_arx(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)964 insert_arx (unsigned long insn,
965 long value,
966 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
967 const char **errmsg ATTRIBUTE_UNUSED)
968 {
969 if (value >= 8 && value < 24)
970 return insn | ((value - 8) & 0xf);
971 else
972 {
973 *errmsg = _("invalid register");
974 return 0;
975 }
976 }
977
978 static long
extract_arx(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)979 extract_arx (unsigned long insn,
980 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
981 int *invalid ATTRIBUTE_UNUSED)
982 {
983 return (insn & 0xf) + 8;
984 }
985
986 static unsigned long
insert_ary(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)987 insert_ary (unsigned long insn,
988 long value,
989 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
990 const char **errmsg ATTRIBUTE_UNUSED)
991 {
992 if (value >= 8 && value < 24)
993 return insn | (((value - 8) & 0xf) << 4);
994 else
995 {
996 *errmsg = _("invalid register");
997 return 0;
998 }
999 }
1000
1001 static long
extract_ary(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1002 extract_ary (unsigned long insn,
1003 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1004 int *invalid ATTRIBUTE_UNUSED)
1005 {
1006 return ((insn >> 4) & 0xf) + 8;
1007 }
1008
1009 static unsigned long
insert_rx(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1010 insert_rx (unsigned long insn,
1011 long value,
1012 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1013 const char **errmsg)
1014 {
1015 if (value >= 0 && value < 8)
1016 return insn | value;
1017 else if (value >= 24 && value <= 31)
1018 return insn | (value - 16);
1019 else
1020 {
1021 *errmsg = _("invalid register");
1022 return 0;
1023 }
1024 }
1025
1026 static long
extract_rx(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1027 extract_rx (unsigned long insn,
1028 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1029 int *invalid ATTRIBUTE_UNUSED)
1030 {
1031 int value = insn & 0xf;
1032 if (value >= 0 && value < 8)
1033 return value;
1034 else
1035 return value + 16;
1036 }
1037
1038 static unsigned long
insert_ry(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1039 insert_ry (unsigned long insn,
1040 long value,
1041 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1042 const char **errmsg)
1043 {
1044 if (value >= 0 && value < 8)
1045 return insn | (value << 4);
1046 else if (value >= 24 && value <= 31)
1047 return insn | ((value - 16) << 4);
1048 else
1049 {
1050 *errmsg = _("invalid register");
1051 return 0;
1052 }
1053 }
1054
1055 static long
extract_ry(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1056 extract_ry (unsigned long insn,
1057 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1058 int *invalid ATTRIBUTE_UNUSED)
1059 {
1060 int value = (insn >> 4) & 0xf;
1061 if (value >= 0 && value < 8)
1062 return value;
1063 else
1064 return value + 16;
1065 }
1066
1067 /* The BA field in an XL form instruction when it must be the same as
1068 the BT field in the same instruction. This operand is marked FAKE.
1069 The insertion function just copies the BT field into the BA field,
1070 and the extraction function just checks that the fields are the
1071 same. */
1072
1073 static unsigned long
insert_bat(unsigned long insn,long value ATTRIBUTE_UNUSED,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1074 insert_bat (unsigned long insn,
1075 long value ATTRIBUTE_UNUSED,
1076 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1077 const char **errmsg ATTRIBUTE_UNUSED)
1078 {
1079 return insn | (((insn >> 21) & 0x1f) << 16);
1080 }
1081
1082 static long
extract_bat(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1083 extract_bat (unsigned long insn,
1084 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1085 int *invalid)
1086 {
1087 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
1088 *invalid = 1;
1089 return 0;
1090 }
1091
1092 /* The BB field in an XL form instruction when it must be the same as
1093 the BA field in the same instruction. This operand is marked FAKE.
1094 The insertion function just copies the BA field into the BB field,
1095 and the extraction function just checks that the fields are the
1096 same. */
1097
1098 static unsigned long
insert_bba(unsigned long insn,long value ATTRIBUTE_UNUSED,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1099 insert_bba (unsigned long insn,
1100 long value ATTRIBUTE_UNUSED,
1101 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1102 const char **errmsg ATTRIBUTE_UNUSED)
1103 {
1104 return insn | (((insn >> 16) & 0x1f) << 11);
1105 }
1106
1107 static long
extract_bba(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1108 extract_bba (unsigned long insn,
1109 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1110 int *invalid)
1111 {
1112 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
1113 *invalid = 1;
1114 return 0;
1115 }
1116
1117 /* The BD field in a B form instruction when the - modifier is used.
1118 This modifier means that the branch is not expected to be taken.
1119 For chips built to versions of the architecture prior to version 2
1120 (ie. not Power4 compatible), we set the y bit of the BO field to 1
1121 if the offset is negative. When extracting, we require that the y
1122 bit be 1 and that the offset be positive, since if the y bit is 0
1123 we just want to print the normal form of the instruction.
1124 Power4 compatible targets use two bits, "a", and "t", instead of
1125 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
1126 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
1127 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
1128 for branch on CTR. We only handle the taken/not-taken hint here.
1129 Note that we don't relax the conditions tested here when
1130 disassembling with -Many because insns using extract_bdm and
1131 extract_bdp always occur in pairs. One or the other will always
1132 be valid. */
1133
1134 #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
1135
1136 static unsigned long
insert_bdm(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg ATTRIBUTE_UNUSED)1137 insert_bdm (unsigned long insn,
1138 long value,
1139 ppc_cpu_t dialect,
1140 const char **errmsg ATTRIBUTE_UNUSED)
1141 {
1142 if ((dialect & ISA_V2) == 0)
1143 {
1144 if ((value & 0x8000) != 0)
1145 insn |= 1 << 21;
1146 }
1147 else
1148 {
1149 if ((insn & (0x14 << 21)) == (0x04 << 21))
1150 insn |= 0x02 << 21;
1151 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1152 insn |= 0x08 << 21;
1153 }
1154 return insn | (value & 0xfffc);
1155 }
1156
1157 static long
extract_bdm(unsigned long insn,ppc_cpu_t dialect,int * invalid)1158 extract_bdm (unsigned long insn,
1159 ppc_cpu_t dialect,
1160 int *invalid)
1161 {
1162 if ((dialect & ISA_V2) == 0)
1163 {
1164 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
1165 *invalid = 1;
1166 }
1167 else
1168 {
1169 if ((insn & (0x17 << 21)) != (0x06 << 21)
1170 && (insn & (0x1d << 21)) != (0x18 << 21))
1171 *invalid = 1;
1172 }
1173
1174 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1175 }
1176
1177 /* The BD field in a B form instruction when the + modifier is used.
1178 This is like BDM, above, except that the branch is expected to be
1179 taken. */
1180
1181 static unsigned long
insert_bdp(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg ATTRIBUTE_UNUSED)1182 insert_bdp (unsigned long insn,
1183 long value,
1184 ppc_cpu_t dialect,
1185 const char **errmsg ATTRIBUTE_UNUSED)
1186 {
1187 if ((dialect & ISA_V2) == 0)
1188 {
1189 if ((value & 0x8000) == 0)
1190 insn |= 1 << 21;
1191 }
1192 else
1193 {
1194 if ((insn & (0x14 << 21)) == (0x04 << 21))
1195 insn |= 0x03 << 21;
1196 else if ((insn & (0x14 << 21)) == (0x10 << 21))
1197 insn |= 0x09 << 21;
1198 }
1199 return insn | (value & 0xfffc);
1200 }
1201
1202 static long
extract_bdp(unsigned long insn,ppc_cpu_t dialect,int * invalid)1203 extract_bdp (unsigned long insn,
1204 ppc_cpu_t dialect,
1205 int *invalid)
1206 {
1207 if ((dialect & ISA_V2) == 0)
1208 {
1209 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1210 *invalid = 1;
1211 }
1212 else
1213 {
1214 if ((insn & (0x17 << 21)) != (0x07 << 21)
1215 && (insn & (0x1d << 21)) != (0x19 << 21))
1216 *invalid = 1;
1217 }
1218
1219 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1220 }
1221
1222 static inline int
valid_bo_pre_v2(long value)1223 valid_bo_pre_v2 (long value)
1224 {
1225 /* Certain encodings have bits that are required to be zero.
1226 These are (z must be zero, y may be anything):
1227 0000y
1228 0001y
1229 001zy
1230 0100y
1231 0101y
1232 011zy
1233 1z00y
1234 1z01y
1235 1z1zz
1236 */
1237 if ((value & 0x14) == 0)
1238 return 1;
1239 else if ((value & 0x14) == 0x4)
1240 return (value & 0x2) == 0;
1241 else if ((value & 0x14) == 0x10)
1242 return (value & 0x8) == 0;
1243 else
1244 return value == 0x14;
1245 }
1246
1247 static inline int
valid_bo_post_v2(long value)1248 valid_bo_post_v2 (long value)
1249 {
1250 /* Certain encodings have bits that are required to be zero.
1251 These are (z must be zero, a & t may be anything):
1252 0000z
1253 0001z
1254 001at
1255 0100z
1256 0101z
1257 011at
1258 1a00t
1259 1a01t
1260 1z1zz
1261 */
1262 if ((value & 0x14) == 0)
1263 return (value & 0x1) == 0;
1264 else if ((value & 0x14) == 0x14)
1265 return value == 0x14;
1266 else
1267 return 1;
1268 }
1269
1270 /* Check for legal values of a BO field. */
1271
1272 static int
valid_bo(long value,ppc_cpu_t dialect,int extract)1273 valid_bo (long value, ppc_cpu_t dialect, int extract)
1274 {
1275 int valid_y = valid_bo_pre_v2 (value);
1276 int valid_at = valid_bo_post_v2 (value);
1277
1278 /* When disassembling with -Many, accept either encoding on the
1279 second pass through opcodes. */
1280 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY)
1281 return valid_y || valid_at;
1282 if ((dialect & ISA_V2) == 0)
1283 return valid_y;
1284 else
1285 return valid_at;
1286 }
1287
1288 /* The BO field in a B form instruction. Warn about attempts to set
1289 the field to an illegal value. */
1290
1291 static unsigned long
insert_bo(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)1292 insert_bo (unsigned long insn,
1293 long value,
1294 ppc_cpu_t dialect,
1295 const char **errmsg)
1296 {
1297 if (!valid_bo (value, dialect, 0))
1298 *errmsg = _("invalid conditional option");
1299 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1300 *errmsg = _("invalid counter access");
1301 return insn | ((value & 0x1f) << 21);
1302 }
1303
1304 static long
extract_bo(unsigned long insn,ppc_cpu_t dialect,int * invalid)1305 extract_bo (unsigned long insn,
1306 ppc_cpu_t dialect,
1307 int *invalid)
1308 {
1309 long value;
1310
1311 value = (insn >> 21) & 0x1f;
1312 if (!valid_bo (value, dialect, 1))
1313 *invalid = 1;
1314 return value;
1315 }
1316
1317 /* The BO field in a B form instruction when the + or - modifier is
1318 used. This is like the BO field, but it must be even. When
1319 extracting it, we force it to be even. */
1320
1321 static unsigned long
insert_boe(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)1322 insert_boe (unsigned long insn,
1323 long value,
1324 ppc_cpu_t dialect,
1325 const char **errmsg)
1326 {
1327 if (!valid_bo (value, dialect, 0))
1328 *errmsg = _("invalid conditional option");
1329 else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
1330 *errmsg = _("invalid counter access");
1331 else if ((value & 1) != 0)
1332 *errmsg = _("attempt to set y bit when using + or - modifier");
1333
1334 return insn | ((value & 0x1f) << 21);
1335 }
1336
1337 static long
extract_boe(unsigned long insn,ppc_cpu_t dialect,int * invalid)1338 extract_boe (unsigned long insn,
1339 ppc_cpu_t dialect,
1340 int *invalid)
1341 {
1342 long value;
1343
1344 value = (insn >> 21) & 0x1f;
1345 if (!valid_bo (value, dialect, 1))
1346 *invalid = 1;
1347 return value & 0x1e;
1348 }
1349
1350 /* The DCMX field in a X form instruction when the field is split
1351 into separate DC, DM and DX fields. */
1352
1353 static unsigned long
insert_dcmxs(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1354 insert_dcmxs (unsigned long insn,
1355 long value,
1356 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1357 const char **errmsg ATTRIBUTE_UNUSED)
1358 {
1359 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40);
1360 }
1361
1362 static long
extract_dcmxs(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1363 extract_dcmxs (unsigned long insn,
1364 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1365 int *invalid ATTRIBUTE_UNUSED)
1366 {
1367 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
1368 }
1369
1370 /* The D field in a DX form instruction when the field is split
1371 into separate D0, D1 and D2 fields. */
1372
1373 static unsigned long
insert_dxd(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1374 insert_dxd (unsigned long insn,
1375 long value,
1376 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1377 const char **errmsg ATTRIBUTE_UNUSED)
1378 {
1379 return insn | (value & 0xffc1) | ((value & 0x3e) << 15);
1380 }
1381
1382 static long
extract_dxd(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1383 extract_dxd (unsigned long insn,
1384 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1385 int *invalid ATTRIBUTE_UNUSED)
1386 {
1387 unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e);
1388 return (dxd ^ 0x8000) - 0x8000;
1389 }
1390
1391 static unsigned long
insert_dxdn(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1392 insert_dxdn (unsigned long insn,
1393 long value,
1394 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1395 const char **errmsg ATTRIBUTE_UNUSED)
1396 {
1397 return insert_dxd (insn, -value, dialect, errmsg);
1398 }
1399
1400 static long
extract_dxdn(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1401 extract_dxdn (unsigned long insn,
1402 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1403 int *invalid ATTRIBUTE_UNUSED)
1404 {
1405 return -extract_dxd (insn, dialect, invalid);
1406 }
1407
1408 /* FXM mask in mfcr and mtcrf instructions. */
1409
1410 static unsigned long
insert_fxm(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)1411 insert_fxm (unsigned long insn,
1412 long value,
1413 ppc_cpu_t dialect,
1414 const char **errmsg)
1415 {
1416 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1417 one bit of the mask field is set. */
1418 if ((insn & (1 << 20)) != 0)
1419 {
1420 if (value == 0 || (value & -value) != value)
1421 {
1422 *errmsg = _("invalid mask field");
1423 value = 0;
1424 }
1425 }
1426
1427 /* If only one bit of the FXM field is set, we can use the new form
1428 of the instruction, which is faster. Unlike the Power4 branch hint
1429 encoding, this is not backward compatible. Do not generate the
1430 new form unless -mpower4 has been given, or -many and the two
1431 operand form of mfcr was used. */
1432 else if (value > 0
1433 && (value & -value) == value
1434 && ((dialect & PPC_OPCODE_POWER4) != 0
1435 || ((dialect & PPC_OPCODE_ANY) != 0
1436 && (insn & (0x3ff << 1)) == 19 << 1)))
1437 insn |= 1 << 20;
1438
1439 /* Any other value on mfcr is an error. */
1440 else if ((insn & (0x3ff << 1)) == 19 << 1)
1441 {
1442 /* A value of -1 means we used the one operand form of
1443 mfcr which is valid. */
1444 if (value != -1)
1445 *errmsg = _("invalid mfcr mask");
1446 value = 0;
1447 }
1448
1449 return insn | ((value & 0xff) << 12);
1450 }
1451
1452 static long
extract_fxm(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1453 extract_fxm (unsigned long insn,
1454 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1455 int *invalid)
1456 {
1457 long mask = (insn >> 12) & 0xff;
1458
1459 /* Is this a Power4 insn? */
1460 if ((insn & (1 << 20)) != 0)
1461 {
1462 /* Exactly one bit of MASK should be set. */
1463 if (mask == 0 || (mask & -mask) != mask)
1464 *invalid = 1;
1465 }
1466
1467 /* Check that non-power4 form of mfcr has a zero MASK. */
1468 else if ((insn & (0x3ff << 1)) == 19 << 1)
1469 {
1470 if (mask != 0)
1471 *invalid = 1;
1472 else
1473 mask = -1;
1474 }
1475
1476 return mask;
1477 }
1478
1479 static unsigned long
insert_li20(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1480 insert_li20 (unsigned long insn,
1481 long value,
1482 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1483 const char **errmsg ATTRIBUTE_UNUSED)
1484 {
1485 return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff);
1486 }
1487
1488 static long
extract_li20(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1489 extract_li20 (unsigned long insn,
1490 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1491 int *invalid ATTRIBUTE_UNUSED)
1492 {
1493 long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
1494
1495 return ext
1496 | (((insn >> 11) & 0xf) << 16)
1497 | (((insn >> 17) & 0xf) << 12)
1498 | (((insn >> 16) & 0x1) << 11)
1499 | (insn & 0x7ff);
1500 }
1501
1502 /* The 2-bit L field in a SYNC or WC field in a WAIT instruction.
1503 For SYNC, some L values are reserved:
1504 * Value 3 is reserved on newer server cpus.
1505 * Values 2 and 3 are reserved on all other cpus. */
1506
1507 static unsigned long
insert_ls(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)1508 insert_ls (unsigned long insn,
1509 long value,
1510 ppc_cpu_t dialect,
1511 const char **errmsg)
1512 {
1513 /* For SYNC, some L values are illegal. */
1514 if (((insn >> 1) & 0x3ff) == 598)
1515 {
1516 long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1;
1517 if (value > max_lvalue)
1518 {
1519 *errmsg = _("illegal L operand value");
1520 return insn;
1521 }
1522 }
1523
1524 return insn | ((value & 0x3) << 21);
1525 }
1526
1527 /* The 4-bit E field in a sync instruction that accepts 2 operands.
1528 If ESYNC is non-zero, then the L field must be either 0 or 1 and
1529 the complement of ESYNC-bit2. */
1530
1531 static unsigned long
insert_esync(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)1532 insert_esync (unsigned long insn,
1533 long value,
1534 ppc_cpu_t dialect,
1535 const char **errmsg)
1536 {
1537 unsigned long ls = (insn >> 21) & 0x03;
1538
1539 if (value == 0)
1540 {
1541 if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1)
1542 || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2))
1543 *errmsg = _("illegal L operand value");
1544 return insn;
1545 }
1546
1547 if ((ls & ~0x1)
1548 || (((value >> 1) & 0x1) ^ ls) == 0)
1549 *errmsg = _("incompatible L operand value");
1550
1551 return insn | ((value & 0xf) << 16);
1552 }
1553
1554 /* The MB and ME fields in an M form instruction expressed as a single
1555 operand which is itself a bitmask. The extraction function always
1556 marks it as invalid, since we never want to recognize an
1557 instruction which uses a field of this type. */
1558
1559 static unsigned long
insert_mbe(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1560 insert_mbe (unsigned long insn,
1561 long value,
1562 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1563 const char **errmsg)
1564 {
1565 unsigned long uval, mask;
1566 int mb, me, mx, count, last;
1567
1568 uval = value;
1569
1570 if (uval == 0)
1571 {
1572 *errmsg = _("illegal bitmask");
1573 return insn;
1574 }
1575
1576 mb = 0;
1577 me = 32;
1578 if ((uval & 1) != 0)
1579 last = 1;
1580 else
1581 last = 0;
1582 count = 0;
1583
1584 /* mb: location of last 0->1 transition */
1585 /* me: location of last 1->0 transition */
1586 /* count: # transitions */
1587
1588 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1589 {
1590 if ((uval & mask) && !last)
1591 {
1592 ++count;
1593 mb = mx;
1594 last = 1;
1595 }
1596 else if (!(uval & mask) && last)
1597 {
1598 ++count;
1599 me = mx;
1600 last = 0;
1601 }
1602 }
1603 if (me == 0)
1604 me = 32;
1605
1606 if (count != 2 && (count != 0 || ! last))
1607 *errmsg = _("illegal bitmask");
1608
1609 return insn | (mb << 6) | ((me - 1) << 1);
1610 }
1611
1612 static long
extract_mbe(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1613 extract_mbe (unsigned long insn,
1614 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1615 int *invalid)
1616 {
1617 long ret;
1618 int mb, me;
1619 int i;
1620
1621 *invalid = 1;
1622
1623 mb = (insn >> 6) & 0x1f;
1624 me = (insn >> 1) & 0x1f;
1625 if (mb < me + 1)
1626 {
1627 ret = 0;
1628 for (i = mb; i <= me; i++)
1629 ret |= 1L << (31 - i);
1630 }
1631 else if (mb == me + 1)
1632 ret = ~0;
1633 else /* (mb > me + 1) */
1634 {
1635 ret = ~0;
1636 for (i = me + 1; i < mb; i++)
1637 ret &= ~(1L << (31 - i));
1638 }
1639 return ret;
1640 }
1641
1642 /* The MB or ME field in an MD or MDS form instruction. The high bit
1643 is wrapped to the low end. */
1644
1645 static unsigned long
insert_mb6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1646 insert_mb6 (unsigned long insn,
1647 long value,
1648 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1649 const char **errmsg ATTRIBUTE_UNUSED)
1650 {
1651 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1652 }
1653
1654 static long
extract_mb6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1655 extract_mb6 (unsigned long insn,
1656 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1657 int *invalid ATTRIBUTE_UNUSED)
1658 {
1659 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1660 }
1661
1662 /* The NB field in an X form instruction. The value 32 is stored as
1663 0. */
1664
1665 static long
extract_nb(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1666 extract_nb (unsigned long insn,
1667 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1668 int *invalid ATTRIBUTE_UNUSED)
1669 {
1670 long ret;
1671
1672 ret = (insn >> 11) & 0x1f;
1673 if (ret == 0)
1674 ret = 32;
1675 return ret;
1676 }
1677
1678 /* The NB field in an lswi instruction, which has special value
1679 restrictions. The value 32 is stored as 0. */
1680
1681 static unsigned long
insert_nbi(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1682 insert_nbi (unsigned long insn,
1683 long value,
1684 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1685 const char **errmsg ATTRIBUTE_UNUSED)
1686 {
1687 long rtvalue = (insn & RT_MASK) >> 21;
1688 long ravalue = (insn & RA_MASK) >> 16;
1689
1690 if (value == 0)
1691 value = 32;
1692 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32
1693 : ravalue))
1694 *errmsg = _("address register in load range");
1695 return insn | ((value & 0x1f) << 11);
1696 }
1697
1698 /* The NSI field in a D form instruction. This is the same as the SI
1699 field, only negated. The extraction function always marks it as
1700 invalid, since we never want to recognize an instruction which uses
1701 a field of this type. */
1702
1703 static unsigned long
insert_nsi(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1704 insert_nsi (unsigned long insn,
1705 long value,
1706 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1707 const char **errmsg ATTRIBUTE_UNUSED)
1708 {
1709 return insn | (-value & 0xffff);
1710 }
1711
1712 static long
extract_nsi(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1713 extract_nsi (unsigned long insn,
1714 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1715 int *invalid)
1716 {
1717 *invalid = 1;
1718 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1719 }
1720
1721 /* The RA field in a D or X form instruction which is an updating
1722 load, which means that the RA field may not be zero and may not
1723 equal the RT field. */
1724
1725 static unsigned long
insert_ral(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1726 insert_ral (unsigned long insn,
1727 long value,
1728 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1729 const char **errmsg)
1730 {
1731 if (value == 0
1732 || (unsigned long) value == ((insn >> 21) & 0x1f))
1733 *errmsg = "invalid register operand when updating";
1734 return insn | ((value & 0x1f) << 16);
1735 }
1736
1737 /* The RA field in an lmw instruction, which has special value
1738 restrictions. */
1739
1740 static unsigned long
insert_ram(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1741 insert_ram (unsigned long insn,
1742 long value,
1743 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1744 const char **errmsg)
1745 {
1746 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1747 *errmsg = _("index register in load range");
1748 return insn | ((value & 0x1f) << 16);
1749 }
1750
1751 /* The RA field in the DQ form lq or an lswx instruction, which have special
1752 value restrictions. */
1753
1754 static unsigned long
insert_raq(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1755 insert_raq (unsigned long insn,
1756 long value,
1757 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1758 const char **errmsg)
1759 {
1760 long rtvalue = (insn & RT_MASK) >> 21;
1761
1762 if (value == rtvalue)
1763 *errmsg = _("source and target register operands must be different");
1764 return insn | ((value & 0x1f) << 16);
1765 }
1766
1767 /* The RA field in a D or X form instruction which is an updating
1768 store or an updating floating point load, which means that the RA
1769 field may not be zero. */
1770
1771 static unsigned long
insert_ras(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1772 insert_ras (unsigned long insn,
1773 long value,
1774 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1775 const char **errmsg)
1776 {
1777 if (value == 0)
1778 *errmsg = _("invalid register operand when updating");
1779 return insn | ((value & 0x1f) << 16);
1780 }
1781
1782 /* The RB field in an X form instruction when it must be the same as
1783 the RS field in the instruction. This is used for extended
1784 mnemonics like mr. This operand is marked FAKE. The insertion
1785 function just copies the BT field into the BA field, and the
1786 extraction function just checks that the fields are the same. */
1787
1788 static unsigned long
insert_rbs(unsigned long insn,long value ATTRIBUTE_UNUSED,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1789 insert_rbs (unsigned long insn,
1790 long value ATTRIBUTE_UNUSED,
1791 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1792 const char **errmsg ATTRIBUTE_UNUSED)
1793 {
1794 return insn | (((insn >> 21) & 0x1f) << 11);
1795 }
1796
1797 static long
extract_rbs(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)1798 extract_rbs (unsigned long insn,
1799 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1800 int *invalid)
1801 {
1802 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1803 *invalid = 1;
1804 return 0;
1805 }
1806
1807 /* The RB field in an lswx instruction, which has special value
1808 restrictions. */
1809
1810 static unsigned long
insert_rbx(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1811 insert_rbx (unsigned long insn,
1812 long value,
1813 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1814 const char **errmsg)
1815 {
1816 long rtvalue = (insn & RT_MASK) >> 21;
1817
1818 if (value == rtvalue)
1819 *errmsg = _("source and target register operands must be different");
1820 return insn | ((value & 0x1f) << 11);
1821 }
1822
1823 /* The SCI8 field is made up of SCL and {U,N}I8 fields. */
1824 static unsigned long
insert_sci8(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)1825 insert_sci8 (unsigned long insn,
1826 long value,
1827 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1828 const char **errmsg)
1829 {
1830 unsigned int fill_scale = 0;
1831 unsigned long ui8 = value;
1832
1833 if ((ui8 & 0xffffff00) == 0)
1834 ;
1835 else if ((ui8 & 0xffffff00) == 0xffffff00)
1836 fill_scale = 0x400;
1837 else if ((ui8 & 0xffff00ff) == 0)
1838 {
1839 fill_scale = 1 << 8;
1840 ui8 >>= 8;
1841 }
1842 else if ((ui8 & 0xffff00ff) == 0xffff00ff)
1843 {
1844 fill_scale = 0x400 | (1 << 8);
1845 ui8 >>= 8;
1846 }
1847 else if ((ui8 & 0xff00ffff) == 0)
1848 {
1849 fill_scale = 2 << 8;
1850 ui8 >>= 16;
1851 }
1852 else if ((ui8 & 0xff00ffff) == 0xff00ffff)
1853 {
1854 fill_scale = 0x400 | (2 << 8);
1855 ui8 >>= 16;
1856 }
1857 else if ((ui8 & 0x00ffffff) == 0)
1858 {
1859 fill_scale = 3 << 8;
1860 ui8 >>= 24;
1861 }
1862 else if ((ui8 & 0x00ffffff) == 0x00ffffff)
1863 {
1864 fill_scale = 0x400 | (3 << 8);
1865 ui8 >>= 24;
1866 }
1867 else
1868 {
1869 *errmsg = _("illegal immediate value");
1870 ui8 = 0;
1871 }
1872
1873 return insn | fill_scale | (ui8 & 0xff);
1874 }
1875
1876 static long
extract_sci8(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1877 extract_sci8 (unsigned long insn,
1878 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1879 int *invalid ATTRIBUTE_UNUSED)
1880 {
1881 int fill = insn & 0x400;
1882 int scale_factor = (insn & 0x300) >> 5;
1883 long value = (insn & 0xff) << scale_factor;
1884
1885 if (fill != 0)
1886 value |= ~((long) 0xff << scale_factor);
1887 return value;
1888 }
1889
1890 static unsigned long
insert_sci8n(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)1891 insert_sci8n (unsigned long insn,
1892 long value,
1893 ppc_cpu_t dialect,
1894 const char **errmsg)
1895 {
1896 return insert_sci8 (insn, -value, dialect, errmsg);
1897 }
1898
1899 static long
extract_sci8n(unsigned long insn,ppc_cpu_t dialect,int * invalid)1900 extract_sci8n (unsigned long insn,
1901 ppc_cpu_t dialect,
1902 int *invalid)
1903 {
1904 return -extract_sci8 (insn, dialect, invalid);
1905 }
1906
1907 static unsigned long
insert_sd4h(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1908 insert_sd4h (unsigned long insn,
1909 long value,
1910 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1911 const char **errmsg ATTRIBUTE_UNUSED)
1912 {
1913 return insn | ((value & 0x1e) << 7);
1914 }
1915
1916 static long
extract_sd4h(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1917 extract_sd4h (unsigned long insn,
1918 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1919 int *invalid ATTRIBUTE_UNUSED)
1920 {
1921 return ((insn >> 8) & 0xf) << 1;
1922 }
1923
1924 static unsigned long
insert_sd4w(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1925 insert_sd4w (unsigned long insn,
1926 long value,
1927 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1928 const char **errmsg ATTRIBUTE_UNUSED)
1929 {
1930 return insn | ((value & 0x3c) << 6);
1931 }
1932
1933 static long
extract_sd4w(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1934 extract_sd4w (unsigned long insn,
1935 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1936 int *invalid ATTRIBUTE_UNUSED)
1937 {
1938 return ((insn >> 8) & 0xf) << 2;
1939 }
1940
1941 static unsigned long
insert_oimm(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1942 insert_oimm (unsigned long insn,
1943 long value,
1944 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1945 const char **errmsg ATTRIBUTE_UNUSED)
1946 {
1947 return insn | (((value - 1) & 0x1f) << 4);
1948 }
1949
1950 static long
extract_oimm(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1951 extract_oimm (unsigned long insn,
1952 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1953 int *invalid ATTRIBUTE_UNUSED)
1954 {
1955 return ((insn >> 4) & 0x1f) + 1;
1956 }
1957
1958 /* The SH field in an MD form instruction. This is split. */
1959
1960 static unsigned long
insert_sh6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1961 insert_sh6 (unsigned long insn,
1962 long value,
1963 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1964 const char **errmsg ATTRIBUTE_UNUSED)
1965 {
1966 /* SH6 operand in the rldixor instructions. */
1967 if (PPC_OP (insn) == 4)
1968 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5);
1969 else
1970 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1971 }
1972
1973 static long
extract_sh6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1974 extract_sh6 (unsigned long insn,
1975 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1976 int *invalid ATTRIBUTE_UNUSED)
1977 {
1978 /* SH6 operand in the rldixor instructions. */
1979 if (PPC_OP (insn) == 4)
1980 return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20);
1981 else
1982 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1983 }
1984
1985 /* The SPR field in an XFX form instruction. This is flipped--the
1986 lower 5 bits are stored in the upper 5 and vice- versa. */
1987
1988 static unsigned long
insert_spr(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1989 insert_spr (unsigned long insn,
1990 long value,
1991 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
1992 const char **errmsg ATTRIBUTE_UNUSED)
1993 {
1994 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1995 }
1996
1997 static long
extract_spr(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1998 extract_spr (unsigned long insn,
1999 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2000 int *invalid ATTRIBUTE_UNUSED)
2001 {
2002 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2003 }
2004
2005 /* Some dialects have 8 SPRG registers instead of the standard 4. */
2006 #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405)
2007
2008 static unsigned long
insert_sprg(unsigned long insn,long value,ppc_cpu_t dialect,const char ** errmsg)2009 insert_sprg (unsigned long insn,
2010 long value,
2011 ppc_cpu_t dialect,
2012 const char **errmsg)
2013 {
2014 if (value > 7
2015 || (value > 3 && (dialect & ALLOW8_SPRG) == 0))
2016 *errmsg = _("invalid sprg number");
2017
2018 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
2019 user mode. Anything else must use spr 272..279. */
2020 if (value <= 3 || (insn & 0x100) != 0)
2021 value |= 0x10;
2022
2023 return insn | ((value & 0x17) << 16);
2024 }
2025
2026 static long
extract_sprg(unsigned long insn,ppc_cpu_t dialect,int * invalid)2027 extract_sprg (unsigned long insn,
2028 ppc_cpu_t dialect,
2029 int *invalid)
2030 {
2031 unsigned long val = (insn >> 16) & 0x1f;
2032
2033 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
2034 If not BOOKE, 405 or VLE, then both use only 272..275. */
2035 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
2036 || (val - 0x10 > 7 && (insn & 0x100) != 0)
2037 || val <= 3
2038 || (val & 8) != 0)
2039 *invalid = 1;
2040 return val & 7;
2041 }
2042
2043 /* The TBR field in an XFX instruction. This is just like SPR, but it
2044 is optional. */
2045
2046 static unsigned long
insert_tbr(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)2047 insert_tbr (unsigned long insn,
2048 long value,
2049 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2050 const char **errmsg)
2051 {
2052 if (value != 268 && value != 269)
2053 *errmsg = _("invalid tbr number");
2054 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
2055 }
2056
2057 static long
extract_tbr(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)2058 extract_tbr (unsigned long insn,
2059 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2060 int *invalid)
2061 {
2062 long ret;
2063
2064 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
2065 if (ret != 268 && ret != 269)
2066 *invalid = 1;
2067 return ret;
2068 }
2069
2070 /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
2071
2072 static unsigned long
insert_xt6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2073 insert_xt6 (unsigned long insn,
2074 long value,
2075 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2076 const char **errmsg ATTRIBUTE_UNUSED)
2077 {
2078 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
2079 }
2080
2081 static long
extract_xt6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2082 extract_xt6 (unsigned long insn,
2083 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2084 int *invalid ATTRIBUTE_UNUSED)
2085 {
2086 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
2087 }
2088
2089 /* The XT and XS fields in an DQ form VSX instruction. This is split. */
2090 static unsigned long
insert_xtq6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2091 insert_xtq6 (unsigned long insn,
2092 long value,
2093 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2094 const char **errmsg ATTRIBUTE_UNUSED)
2095 {
2096 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2);
2097 }
2098
2099 static long
extract_xtq6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2100 extract_xtq6 (unsigned long insn,
2101 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2102 int *invalid ATTRIBUTE_UNUSED)
2103 {
2104 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
2105 }
2106
2107 /* The XA field in an XX3 form instruction. This is split. */
2108
2109 static unsigned long
insert_xa6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2110 insert_xa6 (unsigned long insn,
2111 long value,
2112 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2113 const char **errmsg ATTRIBUTE_UNUSED)
2114 {
2115 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
2116 }
2117
2118 static long
extract_xa6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2119 extract_xa6 (unsigned long insn,
2120 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2121 int *invalid ATTRIBUTE_UNUSED)
2122 {
2123 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
2124 }
2125
2126 /* The XB field in an XX3 form instruction. This is split. */
2127
2128 static unsigned long
insert_xb6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2129 insert_xb6 (unsigned long insn,
2130 long value,
2131 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2132 const char **errmsg ATTRIBUTE_UNUSED)
2133 {
2134 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
2135 }
2136
2137 static long
extract_xb6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2138 extract_xb6 (unsigned long insn,
2139 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2140 int *invalid ATTRIBUTE_UNUSED)
2141 {
2142 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
2143 }
2144
2145 /* The XB field in an XX3 form instruction when it must be the same as
2146 the XA field in the instruction. This is used for extended
2147 mnemonics like xvmovdp. This operand is marked FAKE. The insertion
2148 function just copies the XA field into the XB field, and the
2149 extraction function just checks that the fields are the same. */
2150
2151 static unsigned long
insert_xb6s(unsigned long insn,long value ATTRIBUTE_UNUSED,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2152 insert_xb6s (unsigned long insn,
2153 long value ATTRIBUTE_UNUSED,
2154 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2155 const char **errmsg ATTRIBUTE_UNUSED)
2156 {
2157 return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
2158 }
2159
2160 static long
extract_xb6s(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)2161 extract_xb6s (unsigned long insn,
2162 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2163 int *invalid)
2164 {
2165 if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
2166 || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
2167 *invalid = 1;
2168 return 0;
2169 }
2170
2171 /* The XC field in an XX4 form instruction. This is split. */
2172
2173 static unsigned long
insert_xc6(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2174 insert_xc6 (unsigned long insn,
2175 long value,
2176 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2177 const char **errmsg ATTRIBUTE_UNUSED)
2178 {
2179 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2);
2180 }
2181
2182 static long
extract_xc6(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2183 extract_xc6 (unsigned long insn,
2184 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2185 int *invalid ATTRIBUTE_UNUSED)
2186 {
2187 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f);
2188 }
2189
2190 static unsigned long
insert_dm(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg)2191 insert_dm (unsigned long insn,
2192 long value,
2193 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2194 const char **errmsg)
2195 {
2196 if (value != 0 && value != 1)
2197 *errmsg = _("invalid constant");
2198 return insn | (((value) ? 3 : 0) << 8);
2199 }
2200
2201 static long
extract_dm(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid)2202 extract_dm (unsigned long insn,
2203 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2204 int *invalid)
2205 {
2206 long value;
2207
2208 value = (insn >> 8) & 3;
2209 if (value != 0 && value != 3)
2210 *invalid = 1;
2211 return (value) ? 1 : 0;
2212 }
2213
2214 /* The VLESIMM field in an I16A form instruction. This is split. */
2215
2216 static unsigned long
insert_vlesi(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2217 insert_vlesi (unsigned long insn,
2218 long value,
2219 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2220 const char **errmsg ATTRIBUTE_UNUSED)
2221 {
2222 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2223 }
2224
2225 static long
extract_vlesi(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2226 extract_vlesi (unsigned long insn,
2227 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2228 int *invalid ATTRIBUTE_UNUSED)
2229 {
2230 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2231 value = (value ^ 0x8000) - 0x8000;
2232 return value;
2233 }
2234
2235 static unsigned long
insert_vlensi(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2236 insert_vlensi (unsigned long insn,
2237 long value,
2238 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2239 const char **errmsg ATTRIBUTE_UNUSED)
2240 {
2241 value = -value;
2242 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2243 }
2244 static long
extract_vlensi(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2245 extract_vlensi (unsigned long insn,
2246 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2247 int *invalid ATTRIBUTE_UNUSED)
2248 {
2249 long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2250 value = (value ^ 0x8000) - 0x8000;
2251 /* Don't use for disassembly. */
2252 *invalid = 1;
2253 return -value;
2254 }
2255
2256 /* The VLEUIMM field in an I16A form instruction. This is split. */
2257
2258 static unsigned long
insert_vleui(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2259 insert_vleui (unsigned long insn,
2260 long value,
2261 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2262 const char **errmsg ATTRIBUTE_UNUSED)
2263 {
2264 return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
2265 }
2266
2267 static long
extract_vleui(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2268 extract_vleui (unsigned long insn,
2269 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2270 int *invalid ATTRIBUTE_UNUSED)
2271 {
2272 return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
2273 }
2274
2275 /* The VLEUIMML field in an I16L form instruction. This is split. */
2276
2277 static unsigned long
insert_vleil(unsigned long insn,long value,ppc_cpu_t dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)2278 insert_vleil (unsigned long insn,
2279 long value,
2280 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2281 const char **errmsg ATTRIBUTE_UNUSED)
2282 {
2283 return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
2284 }
2285
2286 static long
extract_vleil(unsigned long insn,ppc_cpu_t dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)2287 extract_vleil (unsigned long insn,
2288 ppc_cpu_t dialect ATTRIBUTE_UNUSED,
2289 int *invalid ATTRIBUTE_UNUSED)
2290 {
2291 return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
2292 }
2293
2294
2295 /* Macros used to form opcodes. */
2296
2297 /* The main opcode. */
2298 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
2299 #define OP_MASK OP (0x3f)
2300
2301 /* The main opcode combined with a trap code in the TO field of a D
2302 form instruction. Used for extended mnemonics for the trap
2303 instructions. */
2304 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
2305 #define OPTO_MASK (OP_MASK | TO_MASK)
2306
2307 /* The main opcode combined with a comparison size bit in the L field
2308 of a D form or X form instruction. Used for extended mnemonics for
2309 the comparison instructions. */
2310 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
2311 #define OPL_MASK OPL (0x3f,1)
2312
2313 /* The main opcode combined with an update code in D form instruction.
2314 Used for extended mnemonics for VLE memory instructions. */
2315 #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
2316 #define OPVUP_MASK OPVUP (0x3f, 0xff)
2317
2318 /* The main opcode combined with an update code and the RT fields specified in
2319 D form instruction. Used for VLE volatile context save/restore
2320 instructions. */
2321 #define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
2322 #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
2323
2324 /* An A form instruction. */
2325 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
2326 #define A_MASK A (0x3f, 0x1f, 1)
2327
2328 /* An A_MASK with the FRB field fixed. */
2329 #define AFRB_MASK (A_MASK | FRB_MASK)
2330
2331 /* An A_MASK with the FRC field fixed. */
2332 #define AFRC_MASK (A_MASK | FRC_MASK)
2333
2334 /* An A_MASK with the FRA and FRC fields fixed. */
2335 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
2336
2337 /* An AFRAFRC_MASK, but with L bit clear. */
2338 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
2339
2340 /* A B form instruction. */
2341 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
2342 #define B_MASK B (0x3f, 1, 1)
2343
2344 /* A BD8 form instruction. This is a 16-bit instruction. */
2345 #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
2346 #define BD8_MASK BD8 (0x3f, 1, 1)
2347
2348 /* Another BD8 form instruction. This is a 16-bit instruction. */
2349 #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
2350 #define BD8IO_MASK BD8IO (0x1f)
2351
2352 /* A BD8 form instruction for simplified mnemonics. */
2353 #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
2354 /* A mask that excludes BO32 and BI32. */
2355 #define EBD8IO1_MASK 0xf800
2356 /* A mask that includes BO32 and excludes BI32. */
2357 #define EBD8IO2_MASK 0xfc00
2358 /* A mask that include BO32 AND BI32. */
2359 #define EBD8IO3_MASK 0xff00
2360
2361 /* A BD15 form instruction. */
2362 #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
2363 #define BD15_MASK BD15 (0x3f, 0xf, 1)
2364
2365 /* A BD15 form instruction for extended conditional branch mnemonics. */
2366 #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
2367 #define EBD15_MASK 0xfff00001
2368
2369 /* A BD15 form instruction for extended conditional branch mnemonics with BI. */
2370 #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
2371 | (((aa) & 0xf) << 22) \
2372 | (((bo) & 0x3) << 20) \
2373 | (((bi) & 0x3) << 16) \
2374 | ((lk) & 1)
2375 #define EBD15BI_MASK 0xfff30001
2376
2377 /* A BD24 form instruction. */
2378 #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
2379 #define BD24_MASK BD24 (0x3f, 1, 1)
2380
2381 /* A B form instruction setting the BO field. */
2382 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2383 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
2384
2385 /* A BBO_MASK with the y bit of the BO field removed. This permits
2386 matching a conditional branch regardless of the setting of the y
2387 bit. Similarly for the 'at' bits used for power4 branch hints. */
2388 #define Y_MASK (((unsigned long) 1) << 21)
2389 #define AT1_MASK (((unsigned long) 3) << 21)
2390 #define AT2_MASK (((unsigned long) 9) << 21)
2391 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
2392 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
2393
2394 /* A B form instruction setting the BO field and the condition bits of
2395 the BI field. */
2396 #define BBOCB(op, bo, cb, aa, lk) \
2397 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
2398 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
2399
2400 /* A BBOCB_MASK with the y bit of the BO field removed. */
2401 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
2402 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
2403 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
2404
2405 /* A BBOYCB_MASK in which the BI field is fixed. */
2406 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
2407 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
2408
2409 /* A VLE C form instruction. */
2410 #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
2411 #define C_LK_MASK C_LK(0x7fff, 1)
2412 #define C(x) ((((unsigned long)(x)) & 0xffff))
2413 #define C_MASK C(0xffff)
2414
2415 /* An Context form instruction. */
2416 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
2417 #define CTX_MASK CTX(0x3f, 0x7)
2418
2419 /* A User Context form instruction. */
2420 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2421 #define UCTX_MASK UCTX(0x3f, 0x1f)
2422
2423 /* The main opcode mask with the RA field clear. */
2424 #define DRA_MASK (OP_MASK | RA_MASK)
2425
2426 /* A DQ form VSX instruction. */
2427 #define DQX(op, xop) (OP (op) | ((xop) & 0x7))
2428 #define DQX_MASK DQX (0x3f, 7)
2429
2430 /* A DS form instruction. */
2431 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
2432 #define DS_MASK DSO (0x3f, 3)
2433
2434 /* An DX form instruction. */
2435 #define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2436 #define DX_MASK DX (0x3f, 0x1f)
2437
2438 /* An EVSEL form instruction. */
2439 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
2440 #define EVSEL_MASK EVSEL(0x3f, 0xff)
2441
2442 /* An IA16 form instruction. */
2443 #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2444 #define IA16_MASK IA16(0x3f, 0x1f)
2445
2446 /* An I16A form instruction. */
2447 #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2448 #define I16A_MASK I16A(0x3f, 0x1f)
2449
2450 /* An I16L form instruction. */
2451 #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
2452 #define I16L_MASK I16L(0x3f, 0x1f)
2453
2454 /* An IM7 form instruction. */
2455 #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
2456 #define IM7_MASK IM7(0x1f)
2457
2458 /* An M form instruction. */
2459 #define M(op, rc) (OP (op) | ((rc) & 1))
2460 #define M_MASK M (0x3f, 1)
2461
2462 /* An LI20 form instruction. */
2463 #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
2464 #define LI20_MASK LI20(0x3f, 0x1)
2465
2466 /* An M form instruction with the ME field specified. */
2467 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
2468
2469 /* An M_MASK with the MB and ME fields fixed. */
2470 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2471
2472 /* An M_MASK with the SH and ME fields fixed. */
2473 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
2474
2475 /* An MD form instruction. */
2476 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
2477 #define MD_MASK MD (0x3f, 0x7, 1)
2478
2479 /* An MD_MASK with the MB field fixed. */
2480 #define MDMB_MASK (MD_MASK | MB6_MASK)
2481
2482 /* An MD_MASK with the SH field fixed. */
2483 #define MDSH_MASK (MD_MASK | SH6_MASK)
2484
2485 /* An MDS form instruction. */
2486 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
2487 #define MDS_MASK MDS (0x3f, 0xf, 1)
2488
2489 /* An MDS_MASK with the MB field fixed. */
2490 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
2491
2492 /* An SC form instruction. */
2493 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
2494 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
2495
2496 /* An SCI8 form instruction. */
2497 #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
2498 #define SCI8_MASK SCI8(0x3f, 0x1f)
2499
2500 /* An SCI8 form instruction. */
2501 #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
2502 #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
2503
2504 /* An SD4 form instruction. This is a 16-bit instruction. */
2505 #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12)
2506 #define SD4_MASK SD4(0xf)
2507
2508 /* An SE_IM5 form instruction. This is a 16-bit instruction. */
2509 #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
2510 #define SE_IM5_MASK SE_IM5(0x3f, 1)
2511
2512 /* An SE_R form instruction. This is a 16-bit instruction. */
2513 #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
2514 #define SE_R_MASK SE_R(0x3f, 0x3f)
2515
2516 /* An SE_RR form instruction. This is a 16-bit instruction. */
2517 #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
2518 #define SE_RR_MASK SE_RR(0x3f, 3)
2519
2520 /* A VX form instruction. */
2521 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2522
2523 /* The mask for an VX form instruction. */
2524 #define VX_MASK VX(0x3f, 0x7ff)
2525
2526 /* A VX_MASK with the VA field fixed. */
2527 #define VXVA_MASK (VX_MASK | (0x1f << 16))
2528
2529 /* A VX_MASK with the VB field fixed. */
2530 #define VXVB_MASK (VX_MASK | (0x1f << 11))
2531
2532 /* A VX_MASK with the VA and VB fields fixed. */
2533 #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
2534
2535 /* A VX_MASK with the VD and VA fields fixed. */
2536 #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
2537
2538 /* A VX_MASK with a UIMM4 field. */
2539 #define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
2540
2541 /* A VX_MASK with a UIMM3 field. */
2542 #define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
2543
2544 /* A VX_MASK with a UIMM2 field. */
2545 #define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
2546
2547 /* A VX_MASK with a PS field. */
2548 #define VXPS_MASK (VX_MASK & ~(0x1 << 9))
2549
2550 /* A VX_MASK with the VA field fixed with a PS field. */
2551 #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9))
2552
2553 /* A VA form instruction. */
2554 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
2555
2556 /* The mask for an VA form instruction. */
2557 #define VXA_MASK VXA(0x3f, 0x3f)
2558
2559 /* A VXA_MASK with a SHB field. */
2560 #define VXASHB_MASK (VXA_MASK | (1 << 10))
2561
2562 /* A VXR form instruction. */
2563 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
2564
2565 /* The mask for a VXR form instruction. */
2566 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
2567
2568 /* A VX form instruction with a VA tertiary opcode. */
2569 #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16))
2570
2571 #define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2572 #define VXASH_MASK VXASH (0x3f, 0x1f)
2573
2574 /* An X form instruction. */
2575 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2576
2577 /* A X form instruction for Quad-Precision FP Instructions. */
2578 #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
2579
2580 /* An EX form instruction. */
2581 #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
2582
2583 /* The mask for an EX form instruction. */
2584 #define EX_MASK EX (0x3f, 0x7ff)
2585
2586 /* An XX2 form instruction. */
2587 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
2588
2589 /* A XX2 form instruction with the VA bits specified. */
2590 #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
2591
2592 /* An XX3 form instruction. */
2593 #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
2594
2595 /* An XX3 form instruction with the RC bit specified. */
2596 #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3))
2597
2598 /* An XX4 form instruction. */
2599 #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4))
2600
2601 /* A Z form instruction. */
2602 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
2603
2604 /* An X form instruction with the RC bit specified. */
2605 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
2606
2607 /* A X form instruction for Quad-Precision FP Instructions with RC bit. */
2608 #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1))
2609
2610 /* An X form instruction with the RA bits specified as two ops. */
2611 #define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16)
2612
2613 /* A Z form instruction with the RC bit specified. */
2614 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
2615
2616 /* The mask for an X form instruction. */
2617 #define X_MASK XRC (0x3f, 0x3ff, 1)
2618
2619 /* The mask for an X form instruction with the BF bits specified. */
2620 #define XBF_MASK (X_MASK | (3 << 21))
2621
2622 /* An X form wait instruction with everything filled in except the WC field. */
2623 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2624
2625 /* The mask for an XX1 form instruction. */
2626 #define XX1_MASK X (0x3f, 0x3ff)
2627
2628 /* An XX1_MASK with the RB field fixed. */
2629 #define XX1RB_MASK (XX1_MASK | RB_MASK)
2630
2631 /* The mask for an XX2 form instruction. */
2632 #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16))
2633
2634 /* The mask for an XX2 form instruction with the UIM bits specified. */
2635 #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18))
2636
2637 /* The mask for an XX2 form instruction with the 4 UIM bits specified. */
2638 #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20))
2639
2640 /* The mask for an XX2 form instruction with the BF bits specified. */
2641 #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1))
2642
2643 /* The mask for an XX2 form instruction with the BF and DCMX bits specified. */
2644 #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1)
2645
2646 /* The mask for an XX2 form instruction with a split DCMX bits specified. */
2647 #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee)
2648
2649 /* The mask for an XX3 form instruction. */
2650 #define XX3_MASK XX3 (0x3f, 0xff)
2651
2652 /* The mask for an XX3 form instruction with the BF bits specified. */
2653 #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
2654
2655 /* The mask for an XX3 form instruction with the DM or SHW bits specified. */
2656 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
2657 #define XX3SHW_MASK XX3DM_MASK
2658
2659 /* The mask for an XX4 form instruction. */
2660 #define XX4_MASK XX4 (0x3f, 0x3)
2661
2662 /* An X form wait instruction with everything filled in except the WC field. */
2663 #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK)
2664
2665 /* The mask for an XMMF form instruction. */
2666 #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1))
2667
2668 /* The mask for a Z form instruction. */
2669 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
2670 #define Z2_MASK ZRC (0x3f, 0xff, 1)
2671
2672 /* An X_MASK with the RA/VA field fixed. */
2673 #define XRA_MASK (X_MASK | RA_MASK)
2674 #define XVA_MASK XRA_MASK
2675
2676 /* An XRA_MASK with the A_L/W field clear. */
2677 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
2678 #define XRLA_MASK XWRA_MASK
2679
2680 /* An X_MASK with the RB field fixed. */
2681 #define XRB_MASK (X_MASK | RB_MASK)
2682
2683 /* An X_MASK with the RT field fixed. */
2684 #define XRT_MASK (X_MASK | RT_MASK)
2685
2686 /* An XRT_MASK mask with the L bits clear. */
2687 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
2688
2689 /* An X_MASK with the RA and RB fields fixed. */
2690 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
2691
2692 /* An XBF_MASK with the RA and RB fields fixed. */
2693 #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK)
2694
2695 /* An XRARB_MASK, but with the L bit clear. */
2696 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
2697
2698 /* An XRARB_MASK, but with the L bits in a darn instruction clear. */
2699 #define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16))
2700
2701 /* An X_MASK with the RT and RA fields fixed. */
2702 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
2703
2704 /* An X_MASK with the RT and RB fields fixed. */
2705 #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
2706
2707 /* An XRTRA_MASK, but with L bit clear. */
2708 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
2709
2710 /* An X_MASK with the RT, RA and RB fields fixed. */
2711 #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
2712
2713 /* An XRTRARB_MASK, but with L bit clear. */
2714 #define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
2715
2716 /* An XRTRARB_MASK, but with A bit clear. */
2717 #define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
2718
2719 /* An XRTRARB_MASK, but with BF bits clear. */
2720 #define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
2721
2722 /* An X form instruction with the L bit specified. */
2723 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
2724
2725 /* An X form instruction with the L bits specified. */
2726 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2727
2728 /* An X form instruction with the L bit and RC bit specified. */
2729 #define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
2730
2731 /* An X form instruction with RT fields specified */
2732 #define XRT(op, xop, rt) (X ((op), (xop)) \
2733 | ((((unsigned long)(rt)) & 0x1f) << 21))
2734
2735 /* An X form instruction with RT and RA fields specified */
2736 #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \
2737 | ((((unsigned long)(rt)) & 0x1f) << 21) \
2738 | ((((unsigned long)(ra)) & 0x1f) << 16))
2739
2740 /* The mask for an X form comparison instruction. */
2741 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
2742
2743 /* The mask for an X form comparison instruction with the L field
2744 fixed. */
2745 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
2746
2747 /* An X form trap instruction with the TO field specified. */
2748 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
2749 #define XTO_MASK (X_MASK | TO_MASK)
2750
2751 /* An X form tlb instruction with the SH field specified. */
2752 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
2753 #define XTLB_MASK (X_MASK | SH_MASK)
2754
2755 /* An X form sync instruction. */
2756 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
2757
2758 /* An X form sync instruction with everything filled in except the LS field. */
2759 #define XSYNC_MASK (0xff9fffff)
2760
2761 /* An X form sync instruction with everything filled in except the L and E fields. */
2762 #define XSYNCLE_MASK (0xff90ffff)
2763
2764 /* An X_MASK, but with the EH bit clear. */
2765 #define XEH_MASK (X_MASK & ~((unsigned long )1))
2766
2767 /* An X form AltiVec dss instruction. */
2768 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
2769 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
2770
2771 /* An XFL form instruction. */
2772 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2773 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
2774
2775 /* An X form isel instruction. */
2776 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
2777 #define XISEL_MASK XISEL(0x3f, 0x1f)
2778
2779 /* An XL form instruction with the LK field set to 0. */
2780 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
2781
2782 /* An XL form instruction which uses the LK field. */
2783 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
2784
2785 /* The mask for an XL form instruction. */
2786 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
2787
2788 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
2789 #define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11))
2790
2791 /* An XL form instruction which explicitly sets the BO field. */
2792 #define XLO(op, bo, xop, lk) \
2793 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
2794 #define XLO_MASK (XL_MASK | BO_MASK)
2795
2796 /* An XL form instruction which explicitly sets the y bit of the BO
2797 field. */
2798 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
2799 #define XLYLK_MASK (XL_MASK | Y_MASK)
2800
2801 /* An XL form instruction which sets the BO field and the condition
2802 bits of the BI field. */
2803 #define XLOCB(op, bo, cb, xop, lk) \
2804 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
2805 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
2806
2807 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
2808 #define XLBB_MASK (XL_MASK | BB_MASK)
2809 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
2810 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
2811
2812 /* A mask for branch instructions using the BH field. */
2813 #define XLBH_MASK (XL_MASK | (0x1c << 11))
2814
2815 /* An XL_MASK with the BO and BB fields fixed. */
2816 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
2817
2818 /* An XL_MASK with the BO, BI and BB fields fixed. */
2819 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
2820
2821 /* An X form mbar instruction with MO field. */
2822 #define XMBAR(op, xop, mo) (X ((op), (xop)) | ((((unsigned long)(mo)) & 1) << 21))
2823
2824 /* An XO form instruction. */
2825 #define XO(op, xop, oe, rc) \
2826 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
2827 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
2828
2829 /* An XO_MASK with the RB field fixed. */
2830 #define XORB_MASK (XO_MASK | RB_MASK)
2831
2832 /* An XOPS form instruction for paired singles. */
2833 #define XOPS(op, xop, rc) \
2834 (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
2835 #define XOPS_MASK XOPS (0x3f, 0x3ff, 1)
2836
2837
2838 /* An XS form instruction. */
2839 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
2840 #define XS_MASK XS (0x3f, 0x1ff, 1)
2841
2842 /* A mask for the FXM version of an XFX form instruction. */
2843 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
2844
2845 /* An XFX form instruction with the FXM field filled in. */
2846 #define XFXM(op, xop, fxm, p4) \
2847 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
2848 | ((unsigned long)(p4) << 20))
2849
2850 /* An XFX form instruction with the SPR field filled in. */
2851 #define XSPR(op, xop, spr) \
2852 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
2853 #define XSPR_MASK (X_MASK | SPR_MASK)
2854
2855 /* An XFX form instruction with the SPR field filled in except for the
2856 SPRBAT field. */
2857 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
2858
2859 /* An XFX form instruction with the SPR field filled in except for the
2860 SPRG field. */
2861 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
2862
2863 /* An X form instruction with everything filled in except the E field. */
2864 #define XE_MASK (0xffff7fff)
2865
2866 /* An X form user context instruction. */
2867 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
2868 #define XUC_MASK XUC(0x3f, 0x1f)
2869
2870 /* An XW form instruction. */
2871 #define XW(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3f) << 1) | ((rc) & 1))
2872 /* The mask for a G form instruction. rc not supported at present. */
2873 #define XW_MASK XW (0x3f, 0x3f, 0)
2874
2875 /* An APU form instruction. */
2876 #define APU(op, xop, rc) (OP (op) | (((unsigned long)(xop)) & 0x3ff) << 1 | ((rc) & 1))
2877
2878 /* The mask for an APU form instruction. */
2879 #define APU_MASK APU (0x3f, 0x3ff, 1)
2880 #define APU_RT_MASK (APU_MASK | RT_MASK)
2881 #define APU_RA_MASK (APU_MASK | RA_MASK)
2882
2883 /* The BO encodings used in extended conditional branch mnemonics. */
2884 #define BODNZF (0x0)
2885 #define BODNZFP (0x1)
2886 #define BODZF (0x2)
2887 #define BODZFP (0x3)
2888 #define BODNZT (0x8)
2889 #define BODNZTP (0x9)
2890 #define BODZT (0xa)
2891 #define BODZTP (0xb)
2892
2893 #define BOF (0x4)
2894 #define BOFP (0x5)
2895 #define BOFM4 (0x6)
2896 #define BOFP4 (0x7)
2897 #define BOT (0xc)
2898 #define BOTP (0xd)
2899 #define BOTM4 (0xe)
2900 #define BOTP4 (0xf)
2901
2902 #define BODNZ (0x10)
2903 #define BODNZP (0x11)
2904 #define BODZ (0x12)
2905 #define BODZP (0x13)
2906 #define BODNZM4 (0x18)
2907 #define BODNZP4 (0x19)
2908 #define BODZM4 (0x1a)
2909 #define BODZP4 (0x1b)
2910
2911 #define BOU (0x14)
2912
2913 /* The BO16 encodings used in extended VLE conditional branch mnemonics. */
2914 #define BO16F (0x0)
2915 #define BO16T (0x1)
2916
2917 /* The BO32 encodings used in extended VLE conditional branch mnemonics. */
2918 #define BO32F (0x0)
2919 #define BO32T (0x1)
2920 #define BO32DNZ (0x2)
2921 #define BO32DZ (0x3)
2922
2923 /* The BI condition bit encodings used in extended conditional branch
2924 mnemonics. */
2925 #define CBLT (0)
2926 #define CBGT (1)
2927 #define CBEQ (2)
2928 #define CBSO (3)
2929
2930 /* The TO encodings used in extended trap mnemonics. */
2931 #define TOLGT (0x1)
2932 #define TOLLT (0x2)
2933 #define TOEQ (0x4)
2934 #define TOLGE (0x5)
2935 #define TOLNL (0x5)
2936 #define TOLLE (0x6)
2937 #define TOLNG (0x6)
2938 #define TOGT (0x8)
2939 #define TOGE (0xc)
2940 #define TONL (0xc)
2941 #define TOLT (0x10)
2942 #define TOLE (0x14)
2943 #define TONG (0x14)
2944 #define TONE (0x18)
2945 #define TOU (0x1f)
2946
2947 /* Smaller names for the flags so each entry in the opcodes table will
2948 fit on a single line. */
2949 #undef PPC
2950 #define PPC PPC_OPCODE_PPC
2951 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2952 #define POWER4 PPC_OPCODE_POWER4
2953 #define POWER5 PPC_OPCODE_POWER5
2954 #define POWER6 PPC_OPCODE_POWER6
2955 #define POWER7 PPC_OPCODE_POWER7
2956 #define POWER8 PPC_OPCODE_POWER8
2957 #define POWER9 PPC_OPCODE_POWER9
2958 #define CELL PPC_OPCODE_CELL
2959 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
2960 #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \
2961 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
2962 #define PPC403 PPC_OPCODE_403
2963 #define PPC405 PPC_OPCODE_405
2964 #define PPC440 PPC_OPCODE_440
2965 #define PPC464 PPC440
2966 #define PPC476 PPC_OPCODE_476
2967 #define PPC750 PPC_OPCODE_750
2968 #define PPC7450 PPC_OPCODE_7450
2969 #define PPC860 PPC_OPCODE_860
2970 #define PPCPS PPC_OPCODE_PPCPS
2971 #define PPCVEC PPC_OPCODE_ALTIVEC
2972 #define PPCVEC2 PPC_OPCODE_ALTIVEC2
2973 #define PPCVEC3 PPC_OPCODE_ALTIVEC2
2974 #define PPCVSX PPC_OPCODE_VSX
2975 #define PPCVSX2 PPC_OPCODE_VSX
2976 #define PPCVSX3 PPC_OPCODE_VSX3
2977 #define POWER PPC_OPCODE_POWER
2978 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
2979 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2980 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
2981 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
2982 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
2983 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
2984 #define MFDEC1 PPC_OPCODE_POWER
2985 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
2986 #define BOOKE PPC_OPCODE_BOOKE
2987 #define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
2988 #define PPCE300 PPC_OPCODE_E300
2989 #define PPCSPE PPC_OPCODE_SPE
2990 #define PPCISEL PPC_OPCODE_ISEL
2991 #define PPCEFS PPC_OPCODE_EFS
2992 #define PPCBRLK PPC_OPCODE_BRLOCK
2993 #define PPCPMR PPC_OPCODE_PMR
2994 #define PPCTMR PPC_OPCODE_TMR
2995 #define PPCCHLK PPC_OPCODE_CACHELCK
2996 #define PPCRFMCI PPC_OPCODE_RFMCI
2997 #define E500MC PPC_OPCODE_E500MC
2998 #define PPCA2 PPC_OPCODE_A2
2999 #define TITAN PPC_OPCODE_TITAN
3000 #define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
3001 #define E500 PPC_OPCODE_E500
3002 #define E6500 PPC_OPCODE_E6500
3003 #define PPCVLE PPC_OPCODE_VLE
3004 #define PPCHTM PPC_OPCODE_HTM
3005 #define E200Z4 PPC_OPCODE_E200Z4
3006 /* The list of embedded processors that use the embedded operand ordering
3007 for the 3 operand dcbt and dcbtst instructions. */
3008 #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
3009 | PPC_OPCODE_A2)
3010
3011
3012
3013 /* The opcode table.
3014
3015 The format of the opcode table is:
3016
3017 NAME OPCODE MASK FLAGS ANTI {OPERANDS}
3018
3019 NAME is the name of the instruction.
3020 OPCODE is the instruction opcode.
3021 MASK is the opcode mask; this is used to tell the disassembler
3022 which bits in the actual opcode must match OPCODE.
3023 FLAGS are flags indicating which processors support the instruction.
3024 ANTI indicates which processors don't support the instruction.
3025 OPERANDS is the list of operands.
3026
3027 The disassembler reads the table in order and prints the first
3028 instruction which matches, so this table is sorted to put more
3029 specific instructions before more general instructions.
3030
3031 This table must be sorted by major opcode. Please try to keep it
3032 vaguely sorted within major opcode too, except of course where
3033 constrained otherwise by disassembler operation. */
3034
3035 const struct powerpc_opcode powerpc_opcodes[] = {
3036 {"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}},
3037 {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3038 {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3039 {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3040 {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3041 {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3042 {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3043 {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3044 {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3045 {"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3046 {"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3047 {"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3048 {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3049 {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3050 {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3051 {"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE, {RA, SI}},
3052 {"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}},
3053
3054 {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3055 {"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3056 {"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3057 {"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3058 {"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3059 {"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3060 {"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3061 {"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3062 {"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3063 {"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3064 {"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3065 {"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3066 {"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3067 {"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3068 {"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3069 {"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3070 {"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3071 {"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3072 {"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3073 {"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3074 {"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3075 {"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3076 {"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3077 {"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3078 {"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3079 {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3080 {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3081 {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3082 {"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE, {RA, SI}},
3083 {"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE, {RA, SI}},
3084 {"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}},
3085 {"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}},
3086
3087 {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3088 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3089 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3090 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3091 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3092 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3093 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3094 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3095 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3096 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3097 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3098 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3099 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3100 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3101 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3102 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3103 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3104 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3105 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3106 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3107 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3108 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3109 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3110 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3111 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3112 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3113 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3114 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3115 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3116 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3117 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3118 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3119 {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3120 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3121 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3122 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3123 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3124 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3125 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3126 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3127 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3128 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3129 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3130 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3131 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3132 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3133 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
3134 {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
3135 {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3136 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3137 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3138 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3139 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
3140 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3141 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3142 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3143 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3144 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3145 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
3146 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3147 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3148 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
3149 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3150 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3151 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3152 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3153 {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
3154 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3155 {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3156 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3157 {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3158 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3159 {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3160 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
3161 {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
3162 {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3163 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3164 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3165 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3166 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3167 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3168 {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3169 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3170 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3171 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
3172 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3173 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
3174 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3175 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3176 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3177 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3178 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3179 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3180 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3181 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3182 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3183 {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3184 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3185 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3186 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3187 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3188 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3189 {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3190 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3191 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3192 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3193 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3194 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3195 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3196 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3197 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3198 {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
3199 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3200 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3201 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3202 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3203 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3204 {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3205 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3206 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3207 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3208 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3209 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3210 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3211 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3212 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3213 {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3214 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3215 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3216 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3217 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3218 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3219 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3220 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3221 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3222 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3223 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3224 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3225 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3226 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3227 {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3228 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3229 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3230 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3231 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3232 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3233 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3234 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3235 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3236 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3237 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3238 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3239 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3240 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3241 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3242 {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3243 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3244 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3245 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3246 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3247 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3248 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3249 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3250 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3251 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3252 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3253 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3254 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3255 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3256 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3257 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3258 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3259 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3260 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3261 {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
3262 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3263 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3264 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3265 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
3266 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3267 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
3268 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3269 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3270 {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
3271 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3272 {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
3273 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
3274 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3275 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
3276 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
3277 {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
3278 {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3279 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
3280 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
3281 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3282 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3283 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3284 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
3285 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3286 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3287 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3288 {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3289 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3290 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3291 {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
3292 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3293 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3294 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3295 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3296 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3297 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3298 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3299 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3300 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3301 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3302 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3303 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3304 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
3305 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
3306 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3307 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3308 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3309 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3310 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3311 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3312 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3313 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3314 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3315 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3316 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3317 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3318 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3319 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3320 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3321 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3322 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3323 {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
3324 {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3325 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3326 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3327 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
3328 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3329 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3330 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3331 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3332 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3333 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
3334 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3335 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
3336 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
3337 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3338 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3339 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3340 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3341 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3342 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3343 {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
3344 {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3345 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3346 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3347 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3348 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
3349 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
3350 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
3351 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
3352 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
3353 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
3354 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
3355 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
3356 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
3357 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3358 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
3359 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3360 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3361 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
3362 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3363 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3364 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3365 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3366 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
3367 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3368 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
3369 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
3370 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3371 {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3372 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3373 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3374 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3375 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3376 {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3377 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3378 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3379 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3380 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
3381 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
3382 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
3383 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
3384 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
3385 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
3386 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
3387 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
3388 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
3389 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
3390 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3391 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
3392 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3393 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3394 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3395 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3396 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3397 {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
3398 {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
3399 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
3400 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
3401 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
3402 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3403 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
3404 {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
3405 {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
3406 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3407 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3408 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3409 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
3410 {"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
3411 {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
3412 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
3413 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
3414 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
3415 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
3416 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
3417 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
3418 {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
3419 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
3420 {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
3421 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3422 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3423 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
3424 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3425 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3426 {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3427 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3428 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3429 {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3430 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3431 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3432 {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3433 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3434 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3435 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3436 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3437 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3438 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3439 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3440 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3441 {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3442 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3443 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3444 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3445 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
3446 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3447 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3448 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3449 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3450 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3451 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3452 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3453 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3454 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3455 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3456 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3457 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3458 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3459 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3460 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3461 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3462 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3463 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3464 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3465 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
3466 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3467 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3468 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3469 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3470 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3471 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3472 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3473 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
3474 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3475 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3476 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3477 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3478 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3479 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3480 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3481 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3482 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3483 {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3484 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3485 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3486 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3487 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3488 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3489 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3490 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3491 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3492 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3493 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3494 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3495 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3496 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3497 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3498 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
3499 {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3500 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3501 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3502 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3503 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3504 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3505 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3506 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3507 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
3508 {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
3509 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
3510 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3511 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3512 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3513 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3514 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3515 {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3516 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3517 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3518 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3519 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3520 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3521 {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3522 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3523 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3524 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3525 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3526 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3527 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3528 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3529 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3530 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3531 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3532 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3533 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3534 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3535 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3536 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3537 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3538 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3539 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3540 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3541 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3542 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3543 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3544 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3545 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3546 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3547 {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
3548 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3549 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3550 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3551 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3552 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3553 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3554 {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3555 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3556 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3557 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3558 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3559 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3560 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3561 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3562 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3563 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3564 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3565 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3566 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3567 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3568 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3569 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3570 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3571 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3572 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3573 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3574 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3575 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3576 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3577 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3578 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3579 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3580 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3581 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3582 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3583 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3584 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3585 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3586 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3587 {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3588 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3589 {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3590 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3591 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3592 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3593 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3594 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3595 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3596 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3597 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3598 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3599 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
3600 {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3601 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
3602 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
3603 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
3604 {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
3605 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3606 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3607 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3608 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3609 {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3610 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3611 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3612 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3613 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
3614 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
3615 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
3616 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
3617 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3618 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3619 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3620 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3621 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3622 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3623 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
3624 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3625 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3626 {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3627 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3628 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3629 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3630 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3631 {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
3632 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3633 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3634 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3635 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3636 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3637 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3638 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3639 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3640 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3641 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3642 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3643 {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3644 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3645 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3646 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3647 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3648 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3649 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3650 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3651 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3652 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3653 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3654 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3655 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3656 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3657 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3658 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3659 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3660 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3661 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3662 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3663 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3664 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3665 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3666 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3667 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3668 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3669 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3670 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3671 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3672 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3673 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3674 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3675 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3676 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3677 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3678 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3679 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3680 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3681 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3682 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3683 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3684 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3685 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3686 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3687 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
3688 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3689 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3690 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3691 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3692 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3693 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3694 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3695 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
3696 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3697 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3698 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3699 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3700 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3701 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3702 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3703 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3704 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3705 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3706 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3707 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3708 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3709 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3710 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3711 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3712 {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
3713 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3714 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3715 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3716 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3717 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
3718 {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
3719 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3720 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3721 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3722 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3723 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3724 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3725 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3726 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3727 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3728 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3729 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3730 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3731 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3732 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3733 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3734 {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3735 {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3736 {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3737 {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3738 {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3739 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3740 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3741 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3742 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3743 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3744 {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3745 {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3746 {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3747 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
3748 {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
3749 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3750 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3751 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3752 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3753 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3754 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3755 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
3756 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3757 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3758 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3759 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3760 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3761 {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3762 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3763 {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3764 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3765 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3766 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3767 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3768 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3769 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3770 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3771 {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
3772 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3773 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3774 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3775 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3776 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3777 {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3778 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3779 {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3780 {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3781 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3782 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3783 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3784 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3785 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3786 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3787 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3788 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3789 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3790 {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3791 {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3792 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
3793 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3794 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3795 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3796 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3797 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3798 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3799 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3800 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3801 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3802 {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3803 {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3804 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3805 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3806 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3807 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
3808 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
3809 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3810 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3811 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3812 {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3813 {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
3814 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
3815 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3816 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
3817 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
3818 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3819 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3820 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3821 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3822 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
3823
3824 {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3825 {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3826
3827 {"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3828 {"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3829
3830 {"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
3831
3832 {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
3833 {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
3834 {"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
3835 {"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
3836
3837 {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
3838 {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
3839 {"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
3840 {"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
3841
3842 {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3843 {"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3844 {"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3845
3846 {"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3847 {"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3848 {"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3849
3850 {"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
3851 {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
3852 {"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
3853 {"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
3854 {"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
3855 {"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
3856
3857 {"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
3858 {"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
3859 {"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3860 {"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3861 {"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
3862
3863 {"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3864 {"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3865 {"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3866 {"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3867 {"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3868 {"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3869 {"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BD}},
3870 {"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BD}},
3871 {"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3872 {"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3873 {"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3874 {"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3875 {"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3876 {"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3877 {"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDA}},
3878 {"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE, {BDA}},
3879 {"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3880 {"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3881 {"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE, {BD}},
3882 {"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDM}},
3883 {"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDP}},
3884 {"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE, {BD}},
3885 {"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3886 {"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3887 {"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE, {BDA}},
3888 {"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDMA}},
3889 {"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE, {BDPA}},
3890 {"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE, {BDA}},
3891
3892 {"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3893 {"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3894 {"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3895 {"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3896 {"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3897 {"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3898 {"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3899 {"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3900 {"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3901 {"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3902 {"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3903 {"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3904 {"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3905 {"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3906 {"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3907 {"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3908 {"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3909 {"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3910 {"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3911 {"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3912 {"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3913 {"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3914 {"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3915 {"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3916 {"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3917 {"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3918 {"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3919 {"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3920 {"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3921 {"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3922 {"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3923 {"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3924 {"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3925 {"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3926 {"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3927 {"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3928 {"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3929 {"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3930 {"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3931 {"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3932 {"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3933 {"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3934 {"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3935 {"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3936 {"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3937 {"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3938 {"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3939 {"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3940 {"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3941 {"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3942 {"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3943 {"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3944 {"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3945 {"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3946 {"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3947 {"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3948 {"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3949 {"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3950 {"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3951 {"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3952 {"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3953 {"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3954 {"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3955 {"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3956 {"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3957 {"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
3958 {"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3959 {"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3960 {"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3961 {"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3962 {"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3963 {"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
3964 {"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3965 {"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3966 {"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3967 {"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3968 {"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3969 {"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
3970 {"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3971 {"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3972 {"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3973 {"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3974 {"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3975 {"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
3976
3977 {"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3978 {"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3979 {"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3980 {"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3981 {"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3982 {"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3983 {"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3984 {"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3985 {"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3986 {"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3987 {"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3988 {"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3989 {"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3990 {"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3991 {"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3992 {"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
3993 {"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
3994 {"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
3995 {"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3996 {"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
3997 {"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
3998 {"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
3999 {"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4000 {"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4001 {"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4002 {"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4003 {"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4004 {"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4005 {"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4006 {"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4007 {"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4008 {"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4009 {"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4010 {"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4011 {"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4012 {"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4013 {"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4014 {"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4015 {"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4016 {"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4017 {"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4018 {"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4019 {"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4020 {"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4021 {"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE, {CR, BD}},
4022 {"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDM}},
4023 {"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDP}},
4024 {"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BD}},
4025 {"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4026 {"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4027 {"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4028 {"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4029 {"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4030 {"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4031 {"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4032 {"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4033 {"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE, {CR, BDA}},
4034 {"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDMA}},
4035 {"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDPA}},
4036 {"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE, {CR, BDA}},
4037
4038 {"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4039 {"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4040 {"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4041 {"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4042 {"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4043 {"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4044 {"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4045 {"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4046 {"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4047 {"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4048 {"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4049 {"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4050 {"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4051 {"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4052 {"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4053 {"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4054 {"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4055 {"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4056 {"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4057 {"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4058 {"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4059 {"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4060 {"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4061 {"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4062
4063 {"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4064 {"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4065 {"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4066 {"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4067 {"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4068 {"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4069 {"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4070 {"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4071 {"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4072 {"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4073 {"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4074 {"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4075 {"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4076 {"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4077 {"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4078 {"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4079
4080 {"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4081 {"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4082 {"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4083 {"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4084 {"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4085 {"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4086 {"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4087 {"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4088 {"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4089 {"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4090 {"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4091 {"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4092 {"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4093 {"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4094 {"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4095 {"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDM}},
4096 {"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDP}},
4097 {"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BD}},
4098 {"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4099 {"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4100 {"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4101 {"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDMA}},
4102 {"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE, {BI, BDPA}},
4103 {"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4104
4105 {"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4106 {"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4107 {"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4108 {"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4109 {"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDM}},
4110 {"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDP}},
4111 {"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BD}},
4112 {"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BD}},
4113 {"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4114 {"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4115 {"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4116 {"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4117 {"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDMA}},
4118 {"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDPA}},
4119 {"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE, {BI, BDA}},
4120 {"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE, {BI, BDA}},
4121
4122 {"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4123 {"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4124 {"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4125 {"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDM}},
4126 {"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDP}},
4127 {"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}},
4128 {"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4129 {"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4130 {"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4131 {"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDMA}},
4132 {"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE, {BOE, BI, BDPA}},
4133 {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
4134
4135 {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4136 {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
4137 {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
4138 {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
4139 {"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}},
4140
4141 {"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}},
4142 {"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}},
4143 {"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}},
4144 {"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}},
4145
4146 {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
4147
4148 {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
4149 {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
4150
4151 {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4152 {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4153 {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4154 {"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4155 {"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4156 {"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4157 {"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4158 {"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4159 {"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4160 {"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4161 {"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4162 {"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE, {0}},
4163 {"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4164 {"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4165 {"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE, {0}},
4166 {"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE, {0}},
4167 {"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4168 {"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4169 {"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4170 {"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4171 {"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4172 {"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4173 {"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4174 {"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE, {0}},
4175
4176 {"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4177 {"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4178 {"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4179 {"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4180 {"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4181 {"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4182 {"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4183 {"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4184 {"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4185 {"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4186 {"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4187 {"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4188 {"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4189 {"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4190 {"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4191 {"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4192 {"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4193 {"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4194 {"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4195 {"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4196 {"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4197 {"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4198 {"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4199 {"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4200 {"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4201 {"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4202 {"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4203 {"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4204 {"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4205 {"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4206 {"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4207 {"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4208 {"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4209 {"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4210 {"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4211 {"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4212 {"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4213 {"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4214 {"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4215 {"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4216 {"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4217 {"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4218 {"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4219 {"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4220 {"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4221 {"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4222 {"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4223 {"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4224 {"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4225 {"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4226 {"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4227 {"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4228 {"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4229 {"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4230 {"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4231 {"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4232 {"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4233 {"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4234 {"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4235 {"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4236 {"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4237 {"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4238 {"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4239 {"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4240 {"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4241 {"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4242 {"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4243 {"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4244 {"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4245 {"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4246 {"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4247 {"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4248 {"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4249 {"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4250 {"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4251 {"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4252 {"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4253 {"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4254 {"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4255 {"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4256 {"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4257 {"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4258 {"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4259 {"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4260 {"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4261 {"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4262 {"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4263 {"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4264 {"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4265 {"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4266 {"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4267 {"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4268 {"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4269 {"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4270 {"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4271 {"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4272 {"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4273 {"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4274 {"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4275 {"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4276 {"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4277 {"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4278 {"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4279 {"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4280 {"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4281 {"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4282 {"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4283 {"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE, {CR}},
4284 {"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4285 {"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4286 {"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4287 {"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4288 {"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4289 {"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4290 {"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4291 {"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4292 {"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4293 {"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4294 {"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4295 {"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4296 {"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4297 {"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4298 {"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4299 {"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4300 {"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4301 {"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4302 {"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4303 {"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4304 {"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4305 {"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4306 {"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4307 {"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4308 {"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4309 {"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4310 {"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4311 {"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4312 {"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4313 {"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4314 {"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4315 {"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4316
4317 {"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4318 {"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4319 {"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4320 {"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4321 {"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4322 {"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4323 {"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4324 {"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4325 {"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4326 {"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4327 {"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4328 {"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4329 {"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4330 {"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4331 {"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4332 {"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4333 {"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4334 {"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4335 {"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4336 {"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4337 {"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4338 {"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4339 {"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4340 {"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4341 {"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4342 {"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4343 {"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4344 {"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4345 {"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4346 {"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4347 {"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4348 {"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4349 {"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4350 {"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4351 {"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4352 {"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4353 {"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4354 {"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4355 {"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4356 {"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4357 {"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4358 {"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE, {BI}},
4359 {"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4360 {"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4361 {"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4362 {"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4363 {"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4364 {"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4365
4366 {"bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4367 {"bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4368 {"bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4369 {"bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4370 {"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4371 {"bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4372 {"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4373 {"bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4374
4375 {"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}},
4376
4377 {"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4378 {"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4379 {"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}},
4380
4381 {"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}},
4382 {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
4383 {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
4384
4385 {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
4386
4387 {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
4388
4389 {"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4390
4391 {"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}},
4392
4393 {"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}},
4394 {"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}},
4395
4396 {"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4397 {"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4398
4399 {"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}},
4400
4401 {"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4402
4403 {"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4404
4405 {"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}},
4406
4407 {"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE, {BT, BAT, BBA}},
4408 {"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4409
4410 {"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}},
4411 {"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}},
4412
4413 {"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4414
4415 {"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4416
4417 {"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4418
4419 {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE, {BT, BA, BBA}},
4420 {"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}},
4421
4422 {"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4423 {"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}},
4424
4425 {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4426 {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE, {0}},
4427
4428 {"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4429 {"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4430 {"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4431 {"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4432 {"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4433 {"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4434 {"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4435 {"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4436 {"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4437 {"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4438 {"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4439 {"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4440 {"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4441 {"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4442 {"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4443 {"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4444 {"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4445 {"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4446 {"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4447 {"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4448 {"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4449 {"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4450 {"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4451 {"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4452 {"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4453 {"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4454 {"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4455 {"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4456 {"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4457 {"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4458 {"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4459 {"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4460 {"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4461 {"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4462 {"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4463 {"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4464 {"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4465 {"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4466 {"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4467 {"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4468 {"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4469 {"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4470 {"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4471 {"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4472 {"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4473 {"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4474 {"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4475 {"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4476 {"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4477 {"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4478 {"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4479 {"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4480 {"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4481 {"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4482 {"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4483 {"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4484 {"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4485 {"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4486 {"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4487 {"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4488 {"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4489 {"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4490 {"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4491 {"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4492 {"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4493 {"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4494 {"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4495 {"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4496 {"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4497 {"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4498 {"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4499 {"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4500 {"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4501 {"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4502 {"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4503 {"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4504 {"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4505 {"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4506 {"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4507 {"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4508 {"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4509 {"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4510 {"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4511 {"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4512 {"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4513 {"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4514 {"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4515 {"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4516 {"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE, {CR}},
4517 {"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4518 {"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4519 {"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4520 {"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4521 {"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4522 {"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4523 {"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4524 {"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4525 {"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4526 {"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4527 {"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE, {CR}},
4528 {"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4529 {"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4530 {"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4531 {"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4532 {"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4533 {"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4534 {"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4535 {"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4536 {"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4537 {"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4538 {"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4539 {"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4540 {"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4541 {"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4542 {"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4543 {"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4544 {"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4545 {"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4546 {"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4547 {"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE, {CR}},
4548
4549 {"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4550 {"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4551 {"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4552 {"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4553 {"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4554 {"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4555 {"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4556 {"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4557 {"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4558 {"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4559 {"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4560 {"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4561 {"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE, {BI}},
4562 {"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4563 {"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4564 {"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE, {BI}},
4565 {"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4566 {"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4567 {"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4568 {"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE, {BI}},
4569
4570 {"bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4571 {"bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4572 {"bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4573 {"bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, PPCVLE, {BOE, BI}},
4574 {"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4575 {"bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4576 {"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}},
4577 {"bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, PPCVLE, {BO, BI}},
4578
4579 {"bctar-", XLYLK(19,560,0,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4580 {"bctarl-", XLYLK(19,560,0,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4581 {"bctar+", XLYLK(19,560,1,0), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4582 {"bctarl+", XLYLK(19,560,1,1), XLYBB_MASK, POWER8, PPCVLE, {BOE, BI}},
4583 {"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4584 {"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}},
4585
4586 {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4587 {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4588
4589 {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4590 {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4591
4592 {"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4593 {"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4594 {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4595 {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4596 {"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, SH}},
4597 {"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE, {RA, RS, MB}},
4598 {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4599 {"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4600
4601 {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4602 {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}},
4603
4604 {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4605 {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4606 {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4607 {"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE, {RA, RS, RB}},
4608 {"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4609 {"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
4610
4611 {"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
4612 {"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4613 {"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4614
4615 {"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4616 {"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4617
4618 {"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE, {0}},
4619 {"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4620 {"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4621
4622 {"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4623 {"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4624
4625 {"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4626 {"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4627
4628 {"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
4629 {"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
4630
4631 {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4632 {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4633 {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4634 {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE, {RA, RS, SH6}},
4635 {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE, {RA, RS, MB6}},
4636 {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4637
4638 {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4639 {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}},
4640
4641 {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4642 {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4643
4644 {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4645 {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}},
4646
4647 {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4648 {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4649 {"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE, {RA, RS, RB}},
4650 {"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}},
4651
4652 {"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4653 {"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}},
4654
4655 {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4656 {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4657 {"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
4658 {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4659
4660 {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4661 {"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4662 {"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4663 {"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4664 {"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, 0, {RA, RB}},
4665 {"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, 0, {RA, RB}},
4666 {"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4667 {"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4668 {"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4669 {"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4670 {"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4671 {"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4672 {"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4673 {"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4674 {"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4675 {"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4676 {"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4677 {"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4678 {"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, 0, {RA, RB}},
4679 {"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, 0, {RA, RB}},
4680 {"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, 0, {RA, RB}},
4681 {"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, 0, {RA, RB}},
4682 {"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4683 {"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4684 {"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, 0, {RA, RB}},
4685 {"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, 0, {RA, RB}},
4686 {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, 0, {RA, RB}},
4687 {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, 0, {RA, RB}},
4688 {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, 0, {0}},
4689 {"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, 0, {RA, RB}},
4690 {"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, 0, {RA, RB}},
4691 {"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}},
4692 {"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}},
4693
4694 {"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4695 {"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4696 {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4697
4698 {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4699 {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4700 {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4701 {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4702 {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4703 {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4704
4705 {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4706 {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4707
4708 {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4709 {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4710 {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4711 {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4712
4713 {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4714 {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4715
4716 {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4717
4718 {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4719
4720 {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}},
4721 {"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}},
4722 {"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4723 {"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}},
4724
4725 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
4726 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
4727
4728 {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
4729
4730 {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
4731
4732 {"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
4733
4734 {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4735 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4736
4737 {"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4738 {"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4739 {"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
4740 {"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
4741
4742 {"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
4743 {"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
4744 {"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
4745 {"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
4746
4747 {"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}},
4748 {"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}},
4749
4750 {"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}},
4751 {"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}},
4752
4753 {"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}},
4754 {"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}},
4755
4756 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4757
4758 {"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}},
4759 {"wait", X(31,30), XWC_MASK, POWER9, 0, {WC}},
4760
4761 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4762
4763 {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
4764 {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
4765 {"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
4766 {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
4767
4768 {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4769 {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4770 {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4771
4772 {"mviwsplt", X(31,46), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4773
4774 {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4775
4776 {"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4777
4778 {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
4779
4780 {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
4781
4782 {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4783
4784 {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
4785
4786 {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4787 {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
4788 {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4789 {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
4790
4791 {"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4792 {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4793 {"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4794 {"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}},
4795
4796 {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4797
4798 {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
4799
4800 {"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}},
4801
4802 {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
4803 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4804
4805 {"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}},
4806 {"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}},
4807
4808 {"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}},
4809 {"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}},
4810
4811 {"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4812 {"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, 0, {0}},
4813 {"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}},
4814
4815 {"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4816
4817 {"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, 0, {RA, RB}},
4818 {"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, 0, {RA, RB}},
4819 {"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, 0, {RA, RB}},
4820 {"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, 0, {RA, RB}},
4821 {"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, 0, {RA, RB}},
4822 {"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, 0, {RA, RB}},
4823 {"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, 0, {RA, RB}},
4824 {"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, 0, {RA, RB}},
4825 {"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, 0, {RA, RB}},
4826 {"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, 0, {RA, RB}},
4827 {"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, 0, {RA, RB}},
4828 {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, 0, {RA, RB}},
4829 {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, 0, {RA, RB}},
4830 {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, 0, {RA, RB}},
4831 {"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, 0, {RA, RB}},
4832 {"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}},
4833
4834 {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4835 {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4836 {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4837
4838 {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4839 {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4840
4841 {"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4842 {"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, 0, {RA, RS, RB}},
4843
4844 {"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}},
4845
4846 {"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
4847
4848 {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
4849
4850 {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
4851 {"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
4852
4853 {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
4854
4855 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4856
4857 {"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}},
4858
4859 {"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
4860 {"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4861
4862 {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
4863 {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
4864
4865 {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
4866 {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
4867
4868 {"mvidsplt", X(31,110), X_MASK, PPCVEC2, 0, {VD, RA, RB}},
4869
4870 {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
4871
4872 {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, 0, {RA, FRS}},
4873 {"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, 0, {RA, VS}},
4874 {"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}},
4875
4876 {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4877
4878 {"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}},
4879
4880 {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
4881
4882 {"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}},
4883
4884 {"not", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RBS}},
4885 {"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}},
4886 {"not.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RBS}},
4887 {"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}},
4888
4889 {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
4890
4891 {"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
4892
4893 {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
4894
4895 {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
4896
4897 {"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4898 {"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4899
4900 {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4901 {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4902 {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4903 {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4904
4905 {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4906 {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4907 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4908 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4909
4910 {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
4911
4912 {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4913 {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
4914
4915 {"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, 0, {RS}},
4916 {"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}},
4917 {"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}},
4918
4919 {"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}},
4920
4921 {"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}},
4922
4923 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4924 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4925
4926 {"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}},
4927
4928 {"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}},
4929
4930 {"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
4931 {"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}},
4932
4933 {"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}},
4934 {"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}},
4935
4936 {"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}},
4937 {"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}},
4938
4939 {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
4940
4941 {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
4942
4943 {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
4944
4945 {"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}},
4946
4947 {"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
4948
4949 {"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4950 {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4951
4952 {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
4953
4954 {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
4955 {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
4956
4957 {"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
4958
4959 {"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
4960 {"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
4961 {"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
4962 {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
4963
4964 {"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}},
4965
4966 {"stqcx.", XRC(31,182,1), X_MASK, POWER8, 0, {RSQ, RA0, RB}},
4967 {"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}},
4968
4969 {"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}},
4970 {"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
4971
4972 {"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}},
4973 {"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}},
4974
4975 {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
4976
4977 {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
4978
4979 {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
4980
4981 {"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
4982 {"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
4983
4984 {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4985 {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
4986 {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
4987 {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
4988
4989 {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4990 {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
4991 {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
4992 {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
4993
4994 {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
4995
4996 {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}},
4997
4998 {"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
4999 {"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5000 {"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5001 {"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}},
5002
5003 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
5004
5005 {"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}},
5006
5007 {"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}},
5008
5009 {"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}},
5010 {"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}},
5011
5012 {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
5013 {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
5014
5015 {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5016
5017 {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
5018
5019 {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5020
5021 {"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5022 {"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5023
5024 {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5025 {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5026 {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5027 {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5028
5029 {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5030 {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5031
5032 {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5033 {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5034 {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5035 {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5036
5037 {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5038 {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5039 {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5040 {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5041
5042 {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}},
5043 {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}},
5044 {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}},
5045 {"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}},
5046
5047 {"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, 0, {FRT, RA}},
5048 {"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, 0, {VD, RA}},
5049 {"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}},
5050
5051 {"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5052 {"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5053 {"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5054 {"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
5055
5056 {"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}},
5057
5058 {"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}},
5059 {"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}},
5060
5061 {"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}},
5062
5063 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5064
5065 {"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}},
5066 {"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}},
5067
5068 {"lvexbx", X(31,261), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5069
5070 {"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}},
5071
5072 {"lvepxl", X(31,263), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5073
5074 {"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5075 {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5076 {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5077
5078 {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
5079
5080 {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5081 {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5082 {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5083 {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5084
5085 {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
5086
5087 {"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}},
5088 {"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5089
5090 {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
5091
5092 {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
5093 {"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
5094
5095 {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
5096
5097 {"lqarx", X(31,276), XEH_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}},
5098
5099 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5100 {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
5101
5102 {"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, 0, {RA0, RB}},
5103 {"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}},
5104 {"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}},
5105 {"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}},
5106
5107 {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
5108
5109 {"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}},
5110
5111 {"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}},
5112 {"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}},
5113
5114 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5115
5116 {"mfdcrux", X(31,291), X_MASK, PPC464, 0, {RS, RA}},
5117
5118 {"lvexhx", X(31,293), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5119 {"lvepx", X(31,295), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5120
5121 {"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5122
5123 {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
5124
5125 {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
5126 {"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
5127 {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
5128 {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
5129
5130 {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
5131
5132 {"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
5133
5134 {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5135
5136 {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
5137
5138 {"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}},
5139
5140 {"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}},
5141 {"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}},
5142
5143 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5144
5145 {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5146 {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5147 {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5148 {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5149 {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5150 {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5151 {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5152 {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5153 {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5154 {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5155 {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5156 {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5157 {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5158 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5159 {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5160 {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5161 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5162 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5163 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5164 {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5165 {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5166 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5167 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5168 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5169 {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5170 {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5171 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5172 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5173 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5174 {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5175 {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5176 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5177 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5178 {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5179 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5180 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
5181
5182 {"lvexwx", X(31,325), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5183
5184 {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
5185
5186 {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5187 {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5188
5189 {"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5190
5191 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5192 {"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}},
5193
5194 {"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}},
5195
5196 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5197 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5198 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5199 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5200 {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5201 {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5202 {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5203 {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5204 {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5205 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5206 {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
5207 {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
5208 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5209 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5210 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5211 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5212 {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5213 {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5214 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5215 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5216 {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5217 {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5218 {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5219 {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5220 {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5221 {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5222 {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5223 {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5224 {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5225 {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5226 {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5227 {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5228 {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5229 {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5230 {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5231 {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5232 {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5233 {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5234 {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5235 {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5236 {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5237 {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5238 {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5239 {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5240 {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5241 {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5242 {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5243 {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5244 {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5245 {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5246 {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5247 {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5248 {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5249 {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5250 {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5251 {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5252 {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5253 {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5254 {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5255 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5256 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5257 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5258 {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5259 {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5260 {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5261 {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5262 {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5263 {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5264 {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5265 {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5266 {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5267 {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5268 {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5269 {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5270 {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5271 {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5272 {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5273 {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5274 {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5275 {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5276 {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5277 {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5278 {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5279 {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5280 {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5281 {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5282 {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5283 {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5284 {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5285 {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5286 {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
5287 {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
5288 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5289 {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
5290 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5291 {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5292 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5293 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5294 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5295 {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5296 {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5297 {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5298 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5299 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5300 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5301 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5302 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5303 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5304 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5305 {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5306 {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5307 {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5308 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5309 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5310 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5311 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5312 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5313 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5314 {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5315 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5316 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5317 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5318 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5319 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5320 {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5321 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5322 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5323 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5324 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5325 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5326 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5327 {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5328 {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5329 {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5330 {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5331 {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5332 {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5333 {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5334 {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5335 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5336 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5337 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5338 {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5339 {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5340 {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5341 {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5342 {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5343 {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5344 {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5345 {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5346 {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5347 {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5348 {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5349 {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5350 {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5351 {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5352 {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5353 {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5354 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5355 {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5356 {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5357 {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5358 {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5359 {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5360 {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5361 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5362 {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5363 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5364 {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5365 {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5366 {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5367 {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5368 {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5369 {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5370 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5371 {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5372 {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5373 {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5374 {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5375 {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5376 {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5377 {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5378 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5379 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5380 {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}},
5381 {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5382 {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5383 {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5384 {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5385 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5386 {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5387 {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5388 {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5389 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5390 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5391 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5392 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5393 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5394 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5395 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5396 {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5397
5398 {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5399
5400 {"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5401
5402 {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5403
5404 {"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
5405
5406 {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5407 {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5408
5409 {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5410 {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5411
5412 {"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5413
5414 {"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}},
5415
5416 {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5417 {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
5418 {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5419
5420 {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
5421
5422 {"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
5423
5424 {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
5425
5426 {"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5427
5428 {"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}},
5429 {"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}},
5430
5431 {"stvexbx", X(31,389), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5432
5433 {"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5434 {"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5435
5436 {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5437 {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5438 {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5439 {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5440
5441 {"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5442 {"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5443
5444 {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5445
5446 {"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}},
5447
5448 {"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}},
5449
5450 {"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}},
5451
5452 {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5453 {"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}},
5454
5455 {"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}},
5456
5457 {"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}},
5458 {"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}},
5459
5460 {"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
5461
5462 {"mtdcrux", X(31,419), X_MASK, PPC464, 0, {RA, RS}},
5463
5464 {"stvexhx", X(31,421), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5465
5466 {"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}},
5467
5468 {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5469 {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5470 {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5471 {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5472
5473 {"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
5474
5475 {"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}},
5476
5477 {"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}},
5478
5479 {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
5480
5481 {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5482
5483 {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
5484
5485 {"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
5486
5487 {"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
5488
5489 /* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
5490 "or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
5491 {"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
5492 {"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
5493 {"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
5494 {"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RBS}},
5495 {"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},
5496 {"mr.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RBS}},
5497 {"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}},
5498
5499 {"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}},
5500 {"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}},
5501 {"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}},
5502 {"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}},
5503 {"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}},
5504 {"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}},
5505 {"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}},
5506 {"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}},
5507 {"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}},
5508 {"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}},
5509 {"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}},
5510 {"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}},
5511 {"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}},
5512 {"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}},
5513 {"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}},
5514 {"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}},
5515 {"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}},
5516 {"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}},
5517 {"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}},
5518 {"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}},
5519 {"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}},
5520 {"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}},
5521 {"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}},
5522 {"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}},
5523 {"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}},
5524 {"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}},
5525 {"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}},
5526 {"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}},
5527 {"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}},
5528 {"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}},
5529 {"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}},
5530 {"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}},
5531 {"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}},
5532 {"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}},
5533 {"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}},
5534 {"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}},
5535
5536 {"stvexwx", X(31,453), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5537
5538 {"dccci", X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
5539 {"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
5540
5541 {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5542 {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5543
5544 {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5545 {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5546
5547 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}},
5548 {"mttmr", X(31,494), X_MASK, PPCTMR|E6500, 0, {TMR, RS}},
5549
5550 {"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}},
5551
5552 {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}},
5553 {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}},
5554 {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}},
5555 {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}},
5556 {"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}},
5557 {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}},
5558 {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}},
5559 {"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN, {RS}},
5560 {"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN, {RS}},
5561 {"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN, {RS}},
5562 {"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, 0, {RS}},
5563 {"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, 0, {RS}},
5564 {"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN, {RS}},
5565 {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}},
5566 {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}},
5567 {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}},
5568 {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}},
5569 {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}},
5570 {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}},
5571 {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}},
5572 {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}},
5573 {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}},
5574 {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}},
5575 {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}},
5576 {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}},
5577 {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}},
5578 {"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, 0, {RS}},
5579 {"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, 0, {RS}},
5580 {"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, 0, {RS}},
5581 {"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, 0, {RS}},
5582 {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}},
5583 {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}},
5584 {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}},
5585 {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}},
5586 {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}},
5587 {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}},
5588 {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}},
5589 {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}},
5590 {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}},
5591 {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}},
5592 {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}},
5593 {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}},
5594 {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}},
5595 {"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, 0, {RS}},
5596 {"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, 0, {RS}},
5597 {"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, 0, {RS}},
5598 {"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, 0, {RS}},
5599 {"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5600 {"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5601 {"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5602 {"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, 0, {RS}},
5603 {"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, 0, {RS}},
5604 {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}},
5605 {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}},
5606 {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}},
5607 {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}},
5608 {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}},
5609 {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}},
5610 {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}},
5611 {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}},
5612 {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}},
5613 {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}},
5614 {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}},
5615 {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}},
5616 {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}},
5617 {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}},
5618 {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}},
5619 {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}},
5620 {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}},
5621 {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}},
5622 {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}},
5623 {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}},
5624 {"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, 0, {RS}},
5625 {"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, 0, {RS}},
5626 {"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, 0, {RS}},
5627 {"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, 0, {RS}},
5628 {"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, 0, {RS}},
5629 {"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, 0, {RS}},
5630 {"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, 0, {RS}},
5631 {"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, 0, {RS}},
5632 {"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, 0, {RS}},
5633 {"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, 0, {RS}},
5634 {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}},
5635 {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
5636 {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
5637 {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}},
5638 {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}},
5639 {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}},
5640 {"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, 0, {RS}},
5641 {"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5642 {"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, 0, {RS}},
5643 {"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5644 {"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, 0, {RS}},
5645 {"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, 0, {RS}},
5646 {"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5647 {"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN, {SPRBAT, RS}},
5648 {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}},
5649 {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}},
5650 {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}},
5651 {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}},
5652 {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}},
5653 {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}},
5654 {"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, 0, {RS}},
5655 {"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, 0, {RS}},
5656 {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}},
5657 {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}},
5658 {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}},
5659 {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}},
5660 {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}},
5661 {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}},
5662 {"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, 0, {RS}},
5663 {"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, 0, {RS}},
5664 {"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, 0, {RS}},
5665 {"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, 0, {RS}},
5666 {"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, 0, {RS}},
5667 {"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, 0, {RS}},
5668 {"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, 0, {RS}},
5669 {"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, 0, {RS}},
5670 {"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, 0, {RS}},
5671 {"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, 0, {RS}},
5672 {"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, 0, {RS}},
5673 {"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, 0, {RS}},
5674 {"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, 0, {RS}},
5675 {"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, 0, {RS}},
5676 {"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, 0, {RS}},
5677 {"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, 0, {RS}},
5678 {"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, 0, {RS}},
5679 {"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, 0, {RS}},
5680 {"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, 0, {RS}},
5681 {"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, 0, {RS}},
5682 {"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, 0, {RS}},
5683 {"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, 0, {RS}},
5684 {"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, 0, {RS}},
5685 {"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, 0, {RS}},
5686 {"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, 0, {RS}},
5687 {"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, 0, {RS}},
5688 {"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, 0, {RS}},
5689 {"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, 0, {RS}},
5690 {"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, 0, {RS}},
5691 {"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, 0, {RS}},
5692 {"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, 0, {RS}},
5693 {"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, 0, {RS}},
5694 {"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, 0, {RS}},
5695 {"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, 0, {RS}},
5696 {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}},
5697 {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}},
5698 {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}},
5699 {"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}},
5700 {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}},
5701 {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}},
5702 {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}},
5703 {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}},
5704 {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}},
5705 {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}},
5706 {"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, 0, {RS}},
5707 {"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, 0, {RS}},
5708 {"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, 0, {RS}},
5709 {"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, 0, {RS}},
5710 {"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, 0, {RS}},
5711 {"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, 0, {RS}},
5712 {"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, 0, {RS}},
5713 {"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, 0, {RS}},
5714 {"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, 0, {RS}},
5715 {"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, 0, {RS}},
5716 {"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}},
5717
5718 {"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}},
5719
5720 {"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}},
5721 {"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}},
5722
5723 {"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}},
5724
5725 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
5726
5727 {"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}},
5728
5729 {"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}},
5730
5731 {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
5732 {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
5733
5734 {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5735 {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5736
5737 {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5738 {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5739
5740 {"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}},
5741
5742 {"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}},
5743 {"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}},
5744
5745 {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
5746
5747 {"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}},
5748
5749 {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}},
5750
5751 {"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
5752
5753 {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
5754 {"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
5755
5756 {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
5757
5758 {"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}},
5759 {"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5760
5761 {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5762 {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5763 {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5764 {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5765 {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5766 {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5767
5768 {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5769 {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5770 {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5771 {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5772
5773 {"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}},
5774
5775 {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
5776
5777 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
5778
5779 {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
5780 {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5781
5782 {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
5783 {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5784
5785 {"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
5786
5787 {"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5788 {"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5789 {"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
5790 {"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
5791
5792 {"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}},
5793 {"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}},
5794
5795 {"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}},
5796 {"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}},
5797
5798 {"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}},
5799 {"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}},
5800
5801 {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
5802 {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
5803
5804 {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
5805 {"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
5806
5807 {"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5808
5809 {"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}},
5810
5811 {"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}},
5812 {"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5813
5814 {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5815 {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5816 {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5817 {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
5818
5819 {"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}},
5820
5821 {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
5822
5823 {"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}},
5824 {"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}},
5825
5826 {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
5827
5828 {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
5829 {"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
5830
5831 {"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5832
5833 {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
5834
5835 {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5836
5837 {"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
5838
5839 {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
5840
5841 {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
5842 {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
5843
5844 {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
5845 {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
5846 {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
5847 {"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
5848 {"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
5849 {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
5850 {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
5851 {"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
5852 {"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}},
5853
5854 {"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}},
5855
5856 {"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}},
5857 {"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}},
5858
5859 {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
5860
5861 {"lvswx", X(31,613), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
5862
5863 {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
5864
5865 {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5866
5867 {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
5868 {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
5869
5870 {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
5871 {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
5872
5873 {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
5874
5875 {"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}},
5876
5877 {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
5878
5879 {"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
5880 {"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
5881
5882 {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
5883 {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5884
5885 {"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}},
5886
5887 {"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}},
5888
5889 {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5890 {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5891 {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5892 {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5893
5894 {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5895 {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5896 {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5897 {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5898
5899 {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
5900
5901 {"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}},
5902
5903 {"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}},
5904 {"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
5905
5906 {"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}},
5907 {"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}},
5908
5909 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
5910
5911 {"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}},
5912 {"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}},
5913
5914 {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
5915 {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
5916
5917 {"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
5918 {"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
5919
5920 {"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5921
5922 {"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}},
5923 {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5924
5925 {"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}},
5926 {"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}},
5927
5928 {"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
5929
5930 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
5931
5932 {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
5933 {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
5934
5935 {"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
5936 {"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
5937
5938 {"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5939
5940 {"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}},
5941
5942 {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5943
5944 {"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
5945
5946 {"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}},
5947
5948 {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5949 {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5950 {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5951 {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5952
5953 {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5954 {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5955 {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5956 {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5957
5958 {"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}},
5959 {"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}},
5960
5961 {"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}},
5962
5963 {"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
5964
5965 {"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}},
5966 {"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}},
5967
5968 {"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}},
5969 {"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}},
5970
5971 {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
5972 {"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}},
5973
5974 {"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}},
5975
5976 {"stvswx", X(31,741), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
5977
5978 {"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}},
5979
5980 {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
5981
5982 {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5983 {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5984 {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5985 {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5986
5987 {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5988 {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5989
5990 {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5991 {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5992 {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5993 {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5994
5995 {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5996 {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5997 {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5998 {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5999
6000 {"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6001 {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6002 {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}},
6003
6004 {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
6005
6006 {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6007 {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}},
6008
6009 {"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}},
6010
6011 {"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}},
6012 {"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}},
6013
6014 {"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6015
6016 {"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
6017
6018 {"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6019 {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
6020 {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6021
6022 {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6023 {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6024
6025 {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6026 {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6027 {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6028 {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6029
6030 {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6031 {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
6032
6033 {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6034 {"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6035
6036 {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
6037
6038 {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}},
6039
6040 {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
6041
6042 {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
6043
6044 {"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRTp, RA0, RB}},
6045 {"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}},
6046
6047 {"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6048 {"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6049 {"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}},
6050 {"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}},
6051
6052 {"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}},
6053 {"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}},
6054
6055 {"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}},
6056
6057 {"lvtrxl", X(31,805), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6058 {"stvepx", X(31,807), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6059 {"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}},
6060
6061 {"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6062 {"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6063
6064 {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}},
6065
6066 {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
6067
6068 {"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}},
6069
6070 {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
6071
6072 {"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}},
6073
6074 {"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}},
6075
6076 {"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6077 {"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6078 {"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}},
6079 {"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}},
6080
6081 {"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6082 {"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}},
6083
6084 {"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6085
6086 {"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
6087
6088 {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6089 {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6090
6091 {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}},
6092 {"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}},
6093
6094 {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
6095
6096 {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
6097
6098 {"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
6099 {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6100 {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
6101
6102 {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
6103
6104 {"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}},
6105 {"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}},
6106 {"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}},
6107 {"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}},
6108
6109 {"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}},
6110
6111 {"lvswxl", X(31,869), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
6112
6113 {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
6114 {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
6115
6116 {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6117 {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6118
6119 {"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
6120
6121 {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}},
6122
6123 {"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}},
6124
6125 {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
6126
6127 {"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}},
6128
6129 {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}},
6130
6131 {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6132 {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
6133
6134 {"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
6135
6136 {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
6137 {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
6138
6139 {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6140 {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6141 {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6142 {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6143
6144 {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6145 {"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6146
6147 {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}},
6148
6149 {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6150 {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}},
6151
6152 {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6153 {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
6154
6155 {"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}},
6156
6157 {"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}},
6158
6159 {"stfdpx", X(31,919), X_MASK, POWER6, POWER7, {FRSp, RA0, RB}},
6160 {"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}},
6161
6162 {"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}},
6163 {"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}},
6164
6165 {"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}},
6166 {"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}},
6167
6168 {"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}},
6169 {"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}},
6170 {"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}},
6171 {"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}},
6172
6173 {"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}},
6174
6175 {"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6176
6177 {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
6178 {"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
6179 {"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
6180
6181 {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
6182
6183 {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6184 {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6185 {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6186 {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6187
6188 {"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6189 {"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6190
6191 {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}},
6192
6193 {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6194 {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6195 {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
6196
6197 {"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}},
6198
6199 {"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}},
6200 {"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}},
6201
6202 {"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}},
6203
6204 {"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}},
6205 {"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}},
6206
6207 {"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}},
6208 {"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}},
6209
6210 {"stvflxl", X(31,965), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6211
6212 {"iccci", X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, 0, {RAOPT, RBOPT}},
6213 {"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}},
6214
6215 {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6216 {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6217
6218 {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6219 {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6220
6221 {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}},
6222 {"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}},
6223
6224 {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
6225 {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
6226 {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
6227 {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}},
6228
6229 {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
6230
6231 {"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}},
6232
6233 {"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}},
6234
6235 {"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}},
6236
6237 {"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}},
6238 {"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}},
6239
6240 {"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
6241
6242 {"stvswxl", X(31,997), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
6243
6244 {"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}},
6245
6246 {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
6247 {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
6248
6249 {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6250 {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6251
6252 {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6253 {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6254
6255 {"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}},
6256
6257 {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}},
6258
6259 {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}},
6260
6261 {"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}},
6262
6263 {"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6264 {"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}},
6265
6266 {"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
6267
6268 {"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}},
6269
6270 {"cctpl", 0x7c210b78, 0xffffffff, CELL, 0, {0}},
6271 {"cctpm", 0x7c421378, 0xffffffff, CELL, 0, {0}},
6272 {"cctph", 0x7c631b78, 0xffffffff, CELL, 0, {0}},
6273
6274 {"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6275 {"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}},
6276 {"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}},
6277
6278 {"db8cyc", 0x7f9ce378, 0xffffffff, CELL, 0, {0}},
6279 {"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, 0, {0}},
6280 {"db12cyc", 0x7fdef378, 0xffffffff, CELL, 0, {0}},
6281 {"db16cyc", 0x7ffffb78, 0xffffffff, CELL, 0, {0}},
6282
6283 {"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
6284 {"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6285
6286 {"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
6287 {"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6288
6289 {"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6290
6291 {"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6292
6293 {"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6294 {"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
6295
6296 {"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}},
6297 {"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
6298
6299 {"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
6300
6301 {"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
6302
6303 {"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6304
6305 {"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6306
6307 {"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6308
6309 {"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6310
6311 {"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}},
6312
6313 {"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}},
6314
6315 {"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
6316 {"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6317
6318 {"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}},
6319 {"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}},
6320
6321 {"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
6322
6323 {"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
6324
6325 {"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}},
6326
6327 {"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}},
6328
6329 {"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
6330
6331 {"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
6332
6333 {"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}},
6334
6335 {"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}},
6336
6337 {"lq", OP(56), OP_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}},
6338 {"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6339 {"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
6340
6341 {"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6342 {"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}},
6343 {"lfdp", OP(57), OP_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}},
6344 {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6345 {"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}},
6346
6347 {"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6348 {"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
6349 {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6350
6351 {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6352 {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6353
6354 {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6355 {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
6356
6357 {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6358 {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6359
6360 {"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6361 {"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6362
6363 {"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6364 {"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6365
6366 {"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6367 {"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}},
6368
6369 {"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6370 {"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6371 {"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6372 {"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6373
6374 {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6375 {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6376
6377 {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6378 {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6379 {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6380 {"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6381
6382 {"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6383 {"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6384
6385 {"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6386 {"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6387
6388 {"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6389 {"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6390
6391 {"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6392 {"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6393
6394 {"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6395 {"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6396
6397 {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6398 {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
6399
6400 {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6401 {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6402
6403 {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6404 {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
6405
6406 {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6407 {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
6408
6409 {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6410 {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6411
6412 {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6413
6414 {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6415 {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
6416 {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
6417
6418 {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6419 {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
6420
6421 {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6422 {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6423
6424 {"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6425 {"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6426
6427 {"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6428 {"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}},
6429
6430 {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6431 {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6432
6433 {"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6434 {"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6435
6436 {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6437 {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6438
6439 {"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6440
6441 {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
6442 {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
6443
6444 {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6445 {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
6446
6447 {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6448 {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6449
6450 {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6451 {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
6452
6453 {"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6454 {"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6455
6456 {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6457 {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
6458
6459 {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6460 {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6461
6462 {"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6463 {"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6464 {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}},
6465 {"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6466 {"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6467 {"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6468 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
6469 {"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6470 {"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6471 {"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S, DMEX}},
6472 {"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6473 {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6474 {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6475 {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}},
6476 {"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6477 {"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6478 {"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6479 {"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6480 {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6481 {"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6482 {"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6483 {"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6484 {"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6485 {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6486 {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6487 {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6488 {"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6489 {"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6490 {"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6491 {"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6492 {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6493 {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6494 {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6495 {"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6496 {"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6497 {"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6498 {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6499 {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6500 {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6501 {"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6502 {"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6503 {"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6504 {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6505 {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6506 {"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6507 {"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}},
6508 {"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6509 {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6510 {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6511 {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6512 {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6513 {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6514 {"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6515 {"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6516 {"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6517 {"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6518 {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6519 {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6520 {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6521 {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6522 {"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6523 {"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6524 {"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6525 {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6526 {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6527 {"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}},
6528 {"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6529 {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6530 {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6531 {"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6532 {"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6533 {"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6534 {"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6535 {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6536 {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6537 {"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}},
6538 {"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}},
6539 {"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6540 {"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6541 {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6542 {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6543 {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6544 {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6545 {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6546 {"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6547 {"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6548 {"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6549 {"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6550 {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6551 {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6552 {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6553 {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6554 {"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6555 {"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6556 {"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6557 {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6558 {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6559 {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6560 {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6561 {"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6562 {"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6563 {"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}},
6564 {"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6565 {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6566 {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6567 {"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6568 {"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6569 {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}},
6570 {"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6571 {"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6572 {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6573 {"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6574 {"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6575 {"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6576 {"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6577 {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6578 {"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6579 {"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6580 {"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6581 {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6582 {"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6583 {"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6584 {"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6585 {"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6586 {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6587 {"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6588 {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6589 {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6590 {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6591 {"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6592 {"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6593 {"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}},
6594 {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6595 {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6596 {"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6597 {"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6598 {"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6599 {"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6600 {"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6601 {"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6602 {"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6603 {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6604 {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6605 {"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6606 {"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6607 {"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6608 {"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}},
6609 {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6610 {"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}},
6611 {"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6612 {"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6613 {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6614 {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6615 {"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6616 {"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6617 {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6618 {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6619 {"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6620 {"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6621 {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6622 {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6623 {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6624 {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6625 {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6626 {"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6627 {"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6628 {"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6629 {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6630 {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6631 {"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6632 {"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6633 {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6634 {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6635 {"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}},
6636 {"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6637 {"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6638 {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6639 {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6640 {"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6641 {"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6642 {"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6643 {"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6644 {"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6645 {"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6646 {"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6647 {"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6648 {"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6649 {"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}},
6650 {"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6S}},
6651 {"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6652 {"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6653 {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6654 {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6655 {"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
6656 {"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
6657 {"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
6658 {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6659 {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
6660
6661 {"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6662 {"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6663
6664 {"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}},
6665 {"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}},
6666 {"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6667 {"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}},
6668 {"stfdp", OP(61), OP_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}},
6669 {"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6670 {"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}},
6671
6672 {"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}},
6673 {"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}},
6674 {"stq", DSO(62,2), DS_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}},
6675
6676 {"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6677
6678 {"daddq", XRC(63,2,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6679 {"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6680
6681 {"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6682 {"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}},
6683
6684 {"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6685 {"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6686
6687 {"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6688 {"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6689
6690 {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6691 {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}},
6692
6693 {"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6694 {"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6695
6696 {"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6697 {"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6698 {"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6699 {"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6700
6701 {"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6702 {"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6703 {"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}},
6704 {"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}},
6705
6706 {"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6707 {"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6708 {"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6709 {"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6710
6711 {"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6712 {"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6713 {"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6714 {"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6715
6716 {"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6717 {"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6718 {"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
6719 {"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}},
6720
6721 {"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6722 {"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}},
6723
6724 {"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6725 {"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6726
6727 {"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6728 {"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6729 {"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6730 {"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
6731
6732 {"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6733 {"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6734 {"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
6735 {"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}},
6736
6737 {"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6738 {"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6739 {"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
6740 {"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}},
6741
6742 {"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6743 {"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6744 {"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6745 {"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6746
6747 {"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6748 {"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6749 {"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6750 {"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6751
6752 {"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6753 {"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6754 {"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6755 {"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6756
6757 {"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6758 {"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6759 {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}},
6760 {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}},
6761
6762 {"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}},
6763
6764 {"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6765 {"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6766
6767 {"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6768 {"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}},
6769
6770 {"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6771 {"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6772
6773 {"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}},
6774
6775 {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BT}},
6776 {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BT}},
6777
6778 {"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6779 {"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6780
6781 {"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
6782
6783 {"dscliq", ZRC(63,66,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6784 {"dscliq.", ZRC(63,66,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6785
6786 {"dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6787 {"dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}},
6788
6789 {"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BT}},
6790 {"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BT}},
6791
6792 {"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6793 {"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6794
6795 {"dscriq", ZRC(63,98,0), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6796 {"dscriq.", ZRC(63,98,1), Z_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}},
6797
6798 {"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6799 {"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6800
6801 {"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6802
6803 {"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}},
6804
6805 {"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6806
6807 {"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6808
6809 {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6810 {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6811 {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}},
6812 {"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}},
6813
6814 {"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6815 {"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6816
6817 {"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6818 {"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6819 {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6820 {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
6821
6822 {"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}},
6823
6824 {"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6825
6826 {"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6827
6828 {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}},
6829 {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}},
6830
6831 {"drintnq", ZRC(63,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6832 {"drintnq.", ZRC(63,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}},
6833
6834 {"dctqpq", XRC(63,258,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6835 {"dctqpq.", XRC(63,258,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6836
6837 {"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6838 {"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}},
6839
6840 {"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6841 {"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6842
6843 {"ddedpdq", XRC(63,322,0), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6844 {"ddedpdq.", XRC(63,322,1), X_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}},
6845
6846 {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6847 {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}},
6848
6849 {"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6850 {"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6851
6852 {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6853 {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6854
6855 {"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6856 {"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6857
6858 {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6859 {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6860
6861 {"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6862 {"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6863
6864 {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6865 {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6866
6867 {"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6868 {"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6869
6870 {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6871 {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}},
6872
6873 {"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6874 {"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6875
6876 {"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6877 {"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6878
6879 {"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6880 {"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}},
6881
6882 {"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6883 {"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6884
6885 {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6886 {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}},
6887
6888 {"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6889 {"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6890 {"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}},
6891 {"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}},
6892 {"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}},
6893 {"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}},
6894
6895 {"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}},
6896
6897 {"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}},
6898
6899 {"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}},
6900 {"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}},
6901
6902 {"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}},
6903
6904 {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6905 {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6906 {"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}},
6907 {"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}},
6908
6909 {"drdpq", XRC(63,770,0), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6910 {"drdpq.", XRC(63,770,1), X_MASK, POWER6, PPCVLE, {FRTp, FRBp}},
6911
6912 {"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6913 {"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCVLE, {FRTp, FRB}},
6914
6915 {"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6916 {"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6917 {"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6918 {"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6919 {"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6920 {"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6921 {"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6922
6923 {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6924 {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6925 {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6926 {"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6927
6928 {"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6929 {"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6930 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6931 {"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6932
6933 {"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
6934 {"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}},
6935
6936 {"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6937 {"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6938 {"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6939 {"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6940 {"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6941 {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6942 {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6943 {"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6944 {"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}},
6945
6946 {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
6947
6948 {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6949 {"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6950 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}},
6951 {"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}},
6952
6953 {"diexq", XRC(63,866,0), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
6954 {"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}},
6955
6956 {"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}},
6957
6958 {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6959 {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6960
6961 {"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6962 {"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6963
6964 {"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}},
6965
6966 {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6967 {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
6968 };
6969
6970 const int powerpc_num_opcodes = ARRAY_SIZE(powerpc_opcodes);
6971
6972 /* The VLE opcode table.
6973
6974 The format of this opcode table is the same as the main opcode table. */
6975
6976 const struct powerpc_opcode vle_opcodes[] = {
6977 {"se_illegal", C(0), C_MASK, PPCVLE, 0, {}},
6978 {"se_isync", C(1), C_MASK, PPCVLE, 0, {}},
6979 {"se_sc", C(2), C_MASK, PPCVLE, 0, {}},
6980 {"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}},
6981 {"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}},
6982 {"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}},
6983 {"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}},
6984 {"se_rfi", C(8), C_MASK, PPCVLE, 0, {}},
6985 {"se_rfci", C(9), C_MASK, PPCVLE, 0, {}},
6986 {"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}},
6987 {"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}},
6988 {"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}},
6989 {"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}},
6990 {"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}},
6991 {"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}},
6992 {"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}},
6993 {"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}},
6994 {"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}},
6995 {"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}},
6996 {"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}},
6997 {"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}},
6998 {"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
6999 {"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}},
7000 {"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}},
7001 {"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7002 {"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7003 {"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7004 {"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7005 {"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7006 {"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7007 {"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7008 {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7009
7010 {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7011 {"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7012 {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7013 {"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
7014 {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7015 {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7016 {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7017 {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7018 {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7019 {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7020 {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7021 {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7022 {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7023 {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7024 {"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7025 {"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7026 {"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, 0, {0}},
7027 {"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7028 {"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7029 {"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7030 {"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}},
7031 {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7032 {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7033 {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7034 {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7035 {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7036 {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7037 {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7038 {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7039 {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7040 {"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7041 {"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7042 {"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7043 {"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7044 {"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7045 {"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7046 {"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7047 {"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7048 {"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7049 {"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
7050 {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
7051 {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7052 {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
7053
7054 {"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7055 {"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7056 {"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7057 {"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}},
7058 {"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7059 {"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7060 {"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7061
7062 {"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7063 {"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7064 {"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7065
7066 {"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7067 {"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7068 {"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7069 {"se_nop", SE_RR(17,0), 0xffff, PPCVLE, 0, {0}},
7070 {"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7071 {"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7072 {"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7073 {"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
7074 {"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}},
7075
7076 {"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7077 {"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7078 {"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7079 {"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7080
7081 {"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7082 {"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7083 {"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7084 {"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7085 {"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7086 {"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7087 {"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}},
7088
7089 {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7090 {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7091 {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7092 {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7093 {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
7094 {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7095 {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7096 {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
7097 {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7098 {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
7099 {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7100 {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7101 {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
7102 {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
7103 {"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
7104 {"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}},
7105 {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},
7106 {"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}},
7107 {"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}},
7108 {"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7109 {"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7110 {"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, 0, {B15}},
7111 {"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, 0, {B15}},
7112 {"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7113 {"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7114 {"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7115 {"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7116 {"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7117 {"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7118 {"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7119 {"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7120 {"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7121 {"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7122 {"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7123 {"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7124 {"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7125 {"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7126 {"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7127 {"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7128 {"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7129 {"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7130 {"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7131 {"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7132 {"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7133 {"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7134 {"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7135 {"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, 0, {CRS,B15}},
7136 {"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7137 {"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}},
7138
7139 {"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7140 {"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7141 {"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7142 {"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, 0, {BI32,B15}},
7143
7144 {"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7145 {"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}},
7146 {"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7147 {"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7148 {"e_crnot", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7149 {"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7150 {"e_crclr", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7151 {"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7152 {"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}},
7153 {"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7154 {"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7155
7156 {"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7157
7158 {"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7159 {"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}},
7160
7161 {"e_crset", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BAT, BBA}},
7162 {"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7163
7164 {"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7165 {"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7166
7167 {"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7168
7169 {"e_crmove", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BBA}},
7170 {"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}},
7171
7172 {"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, 0, {RS}},
7173
7174 {"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7175 {"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}},
7176
7177 {"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7178
7179 {"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}},
7180
7181 {"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7182
7183 {"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}},
7184
7185 {"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7186
7187 {"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}},
7188
7189 {"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7190 {"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7191 {"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7192 {"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7193 {"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7194 {"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7195 {"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7196 {"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7197 {"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7198 {"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7199 {"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7200 {"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7201 {"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, 0, {B8}},
7202 {"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, 0, {BI16, B8}},
7203 {"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}},
7204 {"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}},
7205 {"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}},
7206 };
7207
7208 const int vle_num_opcodes = ARRAY_SIZE(vle_opcodes);
7209
7210 /* The macro table. This is only used by the assembler. */
7211
7212 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
7213 when x=0; 32-x when x is between 1 and 31; are negative if x is
7214 negative; and are 32 or more otherwise. This is what you want
7215 when, for instance, you are emulating a right shift by a
7216 rotate-left-and-mask, because the underlying instructions support
7217 shifts of size 0 but not shifts of size 32. By comparison, when
7218 extracting x bits from some word you want to use just 32-x, because
7219 the underlying instructions don't support extracting 0 bits but do
7220 support extracting the whole word (32 bits in this case). */
7221
7222 const struct powerpc_macro powerpc_macros[] = {
7223 {"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"},
7224 {"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"},
7225 {"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7226 {"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"},
7227 {"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"},
7228 {"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"},
7229 {"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"},
7230 {"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"},
7231 {"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"},
7232 {"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"},
7233 {"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"},
7234 {"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"},
7235 {"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"},
7236 {"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"},
7237 {"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"},
7238 {"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"},
7239
7240 {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"},
7241 {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"},
7242 {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7243 {"extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7244 {"inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7245 {"inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7246 {"insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7247 {"insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7248 {"rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7249 {"rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7250 {"slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)"},
7251 {"sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)"},
7252 {"slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)"},
7253 {"sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)"},
7254 {"srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7255 {"sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7256 {"srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7257 {"sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7258 {"clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)"},
7259 {"clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)"},
7260 {"clrlslwi", 4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7261 {"clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
7262
7263 {"e_extlwi", 4, PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
7264 {"e_extrwi", 4, PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
7265 {"e_inslwi", 4, PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
7266 {"e_insrwi", 4, PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
7267 {"e_rotlwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
7268 {"e_rotrwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
7269 {"e_slwi", 3, PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
7270 {"e_srwi", 3, PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
7271 {"e_clrlwi", 3, PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
7272 {"e_clrrwi", 3, PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
7273 {"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
7274 };
7275
7276 const int powerpc_num_macros = ARRAY_SIZE(powerpc_macros);
7277