1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Zheng Yang <zhengyang@rock-chips.com>
6 * Heiko Stuebner <heiko@sntech.de>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/io.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/nvmem-consumer.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20 #include <linux/phy/phy.h>
21 #include <linux/slab.h>
22
23 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
24
25 /* REG: 0x00 */
26 #define RK3228_PRE_PLL_REFCLK_SEL_PCLK BIT(0)
27 /* REG: 0x01 */
28 #define RK3228_BYPASS_RXSENSE_EN BIT(2)
29 #define RK3228_BYPASS_PWRON_EN BIT(1)
30 #define RK3228_BYPASS_PLLPD_EN BIT(0)
31 /* REG: 0x02 */
32 #define RK3228_BYPASS_PDATA_EN BIT(4)
33 #define RK3228_PDATAEN_DISABLE BIT(0)
34 /* REG: 0x03 */
35 #define RK3228_BYPASS_AUTO_TERM_RES_CAL BIT(7)
36 #define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
37 /* REG: 0x04 */
38 #define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
39 /* REG: 0xaa */
40 #define RK3228_POST_PLL_CTRL_MANUAL BIT(0)
41 /* REG: 0xe0 */
42 #define RK3228_POST_PLL_POWER_DOWN BIT(5)
43 #define RK3228_PRE_PLL_POWER_DOWN BIT(4)
44 #define RK3228_RXSENSE_CLK_CH_ENABLE BIT(3)
45 #define RK3228_RXSENSE_DATA_CH2_ENABLE BIT(2)
46 #define RK3228_RXSENSE_DATA_CH1_ENABLE BIT(1)
47 #define RK3228_RXSENSE_DATA_CH0_ENABLE BIT(0)
48 /* REG: 0xe1 */
49 #define RK3228_BANDGAP_ENABLE BIT(4)
50 #define RK3228_TMDS_DRIVER_ENABLE GENMASK(3, 0)
51 /* REG: 0xe2 */
52 #define RK3228_PRE_PLL_FB_DIV_8_MASK BIT(7)
53 #define RK3228_PRE_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)
54 #define RK3228_PCLK_VCO_DIV_5_MASK BIT(5)
55 #define RK3228_PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5)
56 #define RK3228_PRE_PLL_PRE_DIV_MASK GENMASK(4, 0)
57 #define RK3228_PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
58 /* REG: 0xe3 */
59 #define RK3228_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
60 /* REG: 0xe4 */
61 #define RK3228_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5)
62 #define RK3228_PRE_PLL_PCLK_DIV_B_SHIFT 5
63 #define RK3228_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
64 #define RK3228_PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0)
65 #define RK3228_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
66 /* REG: 0xe5 */
67 #define RK3228_PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5)
68 #define RK3228_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)
69 #define RK3228_PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0)
70 #define RK3228_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0)
71 /* REG: 0xe6 */
72 #define RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(5, 4)
73 #define RK3228_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 5, 4)
74 #define RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(3, 2)
75 #define RK3228_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2)
76 #define RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(1, 0)
77 #define RK3228_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 1, 0)
78 /* REG: 0xe8 */
79 #define RK3228_PRE_PLL_LOCK_STATUS BIT(0)
80 /* REG: 0xe9 */
81 #define RK3228_POST_PLL_POST_DIV_ENABLE UPDATE(3, 7, 6)
82 #define RK3228_POST_PLL_PRE_DIV_MASK GENMASK(4, 0)
83 #define RK3228_POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
84 /* REG: 0xea */
85 #define RK3228_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
86 /* REG: 0xeb */
87 #define RK3228_POST_PLL_FB_DIV_8_MASK BIT(7)
88 #define RK3228_POST_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)
89 #define RK3228_POST_PLL_POST_DIV_MASK GENMASK(5, 4)
90 #define RK3228_POST_PLL_POST_DIV(x) UPDATE(x, 5, 4)
91 #define RK3228_POST_PLL_LOCK_STATUS BIT(0)
92 /* REG: 0xee */
93 #define RK3228_TMDS_CH_TA_ENABLE GENMASK(7, 4)
94 /* REG: 0xef */
95 #define RK3228_TMDS_CLK_CH_TA(x) UPDATE(x, 7, 6)
96 #define RK3228_TMDS_DATA_CH2_TA(x) UPDATE(x, 5, 4)
97 #define RK3228_TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2)
98 #define RK3228_TMDS_DATA_CH0_TA(x) UPDATE(x, 1, 0)
99 /* REG: 0xf0 */
100 #define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS_MASK GENMASK(5, 4)
101 #define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS(x) UPDATE(x, 5, 4)
102 #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS_MASK GENMASK(3, 2)
103 #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2)
104 #define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS_MASK GENMASK(1, 0)
105 #define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS(x) UPDATE(x, 1, 0)
106 /* REG: 0xf1 */
107 #define RK3228_TMDS_CLK_CH_OUTPUT_SWING(x) UPDATE(x, 7, 4)
108 #define RK3228_TMDS_DATA_CH2_OUTPUT_SWING(x) UPDATE(x, 3, 0)
109 /* REG: 0xf2 */
110 #define RK3228_TMDS_DATA_CH1_OUTPUT_SWING(x) UPDATE(x, 7, 4)
111 #define RK3228_TMDS_DATA_CH0_OUTPUT_SWING(x) UPDATE(x, 3, 0)
112
113 /* REG: 0x01 */
114 #define RK3328_BYPASS_RXSENSE_EN BIT(2)
115 #define RK3328_BYPASS_POWERON_EN BIT(1)
116 #define RK3328_BYPASS_PLLPD_EN BIT(0)
117 /* REG: 0x02 */
118 #define RK3328_INT_POL_HIGH BIT(7)
119 #define RK3328_BYPASS_PDATA_EN BIT(4)
120 #define RK3328_PDATA_EN BIT(0)
121 /* REG:0x05 */
122 #define RK3328_INT_TMDS_CLK(x) UPDATE(x, 7, 4)
123 #define RK3328_INT_TMDS_D2(x) UPDATE(x, 3, 0)
124 /* REG:0x07 */
125 #define RK3328_INT_TMDS_D1(x) UPDATE(x, 7, 4)
126 #define RK3328_INT_TMDS_D0(x) UPDATE(x, 3, 0)
127 /* for all RK3328_INT_TMDS_*, ESD_DET as defined in 0xc8-0xcb */
128 #define RK3328_INT_AGND_LOW_PULSE_LOCKED BIT(3)
129 #define RK3328_INT_RXSENSE_LOW_PULSE_LOCKED BIT(2)
130 #define RK3328_INT_VSS_AGND_ESD_DET BIT(1)
131 #define RK3328_INT_AGND_VSS_ESD_DET BIT(0)
132 /* REG: 0xa0 */
133 #define RK3328_PCLK_VCO_DIV_5_MASK BIT(1)
134 #define RK3328_PCLK_VCO_DIV_5(x) UPDATE(x, 1, 1)
135 #define RK3328_PRE_PLL_POWER_DOWN BIT(0)
136 /* REG: 0xa1 */
137 #define RK3328_PRE_PLL_PRE_DIV_MASK GENMASK(5, 0)
138 #define RK3328_PRE_PLL_PRE_DIV(x) UPDATE(x, 5, 0)
139 /* REG: 0xa2 */
140 /* unset means center spread */
141 #define RK3328_SPREAD_SPECTRUM_MOD_DOWN BIT(7)
142 #define RK3328_SPREAD_SPECTRUM_MOD_DISABLE BIT(6)
143 #define RK3328_PRE_PLL_FRAC_DIV_DISABLE UPDATE(3, 5, 4)
144 #define RK3328_PRE_PLL_FB_DIV_11_8_MASK GENMASK(3, 0)
145 #define RK3328_PRE_PLL_FB_DIV_11_8(x) UPDATE((x) >> 8, 3, 0)
146 /* REG: 0xa3 */
147 #define RK3328_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
148 /* REG: 0xa4*/
149 #define RK3328_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(1, 0)
150 #define RK3328_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 1, 0)
151 #define RK3328_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(3, 2)
152 #define RK3328_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 3, 2)
153 #define RK3328_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(5, 4)
154 #define RK3328_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 5, 4)
155 /* REG: 0xa5 */
156 #define RK3328_PRE_PLL_PCLK_DIV_B_SHIFT 5
157 #define RK3328_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5)
158 #define RK3328_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
159 #define RK3328_PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0)
160 #define RK3328_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
161 /* REG: 0xa6 */
162 #define RK3328_PRE_PLL_PCLK_DIV_C_SHIFT 5
163 #define RK3328_PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5)
164 #define RK3328_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)
165 #define RK3328_PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0)
166 #define RK3328_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0)
167 /* REG: 0xa9 */
168 #define RK3328_PRE_PLL_LOCK_STATUS BIT(0)
169 /* REG: 0xaa */
170 #define RK3328_POST_PLL_POST_DIV_ENABLE GENMASK(3, 2)
171 #define RK3328_POST_PLL_REFCLK_SEL_TMDS BIT(1)
172 #define RK3328_POST_PLL_POWER_DOWN BIT(0)
173 /* REG:0xab */
174 #define RK3328_POST_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)
175 #define RK3328_POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
176 /* REG: 0xac */
177 #define RK3328_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
178 /* REG: 0xad */
179 #define RK3328_POST_PLL_POST_DIV_MASK GENMASK(1, 0)
180 #define RK3328_POST_PLL_POST_DIV_2 0x0
181 #define RK3328_POST_PLL_POST_DIV_4 0x1
182 #define RK3328_POST_PLL_POST_DIV_8 0x3
183 /* REG: 0xaf */
184 #define RK3328_POST_PLL_LOCK_STATUS BIT(0)
185 /* REG: 0xb0 */
186 #define RK3328_BANDGAP_ENABLE BIT(2)
187 /* REG: 0xb2 */
188 #define RK3328_TMDS_CLK_DRIVER_EN BIT(3)
189 #define RK3328_TMDS_D2_DRIVER_EN BIT(2)
190 #define RK3328_TMDS_D1_DRIVER_EN BIT(1)
191 #define RK3328_TMDS_D0_DRIVER_EN BIT(0)
192 #define RK3328_TMDS_DRIVER_ENABLE (RK3328_TMDS_CLK_DRIVER_EN | \
193 RK3328_TMDS_D2_DRIVER_EN | \
194 RK3328_TMDS_D1_DRIVER_EN | \
195 RK3328_TMDS_D0_DRIVER_EN)
196 /* REG:0xc5 */
197 #define RK3328_BYPASS_TERM_RESISTOR_CALIB BIT(7)
198 #define RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(x) UPDATE((x) >> 8, 6, 0)
199 /* REG:0xc6 */
200 #define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x) UPDATE(x, 7, 0)
201 /* REG:0xc7 */
202 #define RK3328_TERM_RESISTOR_50 UPDATE(0, 2, 1)
203 #define RK3328_TERM_RESISTOR_62_5 UPDATE(1, 2, 1)
204 #define RK3328_TERM_RESISTOR_75 UPDATE(2, 2, 1)
205 #define RK3328_TERM_RESISTOR_100 UPDATE(3, 2, 1)
206 /* REG 0xc8 - 0xcb */
207 #define RK3328_ESD_DETECT_MASK GENMASK(7, 6)
208 #define RK3328_ESD_DETECT_340MV (0x0 << 6)
209 #define RK3328_ESD_DETECT_280MV (0x1 << 6)
210 #define RK3328_ESD_DETECT_260MV (0x2 << 6)
211 #define RK3328_ESD_DETECT_240MV (0x3 << 6)
212 /* resistors can be used in parallel */
213 #define RK3328_TMDS_TERM_RESIST_MASK GENMASK(5, 0)
214 #define RK3328_TMDS_TERM_RESIST_75 BIT(5)
215 #define RK3328_TMDS_TERM_RESIST_150 BIT(4)
216 #define RK3328_TMDS_TERM_RESIST_300 BIT(3)
217 #define RK3328_TMDS_TERM_RESIST_600 BIT(2)
218 #define RK3328_TMDS_TERM_RESIST_1000 BIT(1)
219 #define RK3328_TMDS_TERM_RESIST_2000 BIT(0)
220 /* REG: 0xd1 */
221 #define RK3328_PRE_PLL_FRAC_DIV_23_16(x) UPDATE((x) >> 16, 7, 0)
222 /* REG: 0xd2 */
223 #define RK3328_PRE_PLL_FRAC_DIV_15_8(x) UPDATE((x) >> 8, 7, 0)
224 /* REG: 0xd3 */
225 #define RK3328_PRE_PLL_FRAC_DIV_7_0(x) UPDATE(x, 7, 0)
226
227 struct inno_hdmi_phy_drv_data;
228
229 struct inno_hdmi_phy {
230 struct device *dev;
231 struct regmap *regmap;
232 int irq;
233
234 struct phy *phy;
235 struct clk *sysclk;
236 struct clk *refoclk;
237 struct clk *refpclk;
238
239 /* platform data */
240 const struct inno_hdmi_phy_drv_data *plat_data;
241 int chip_version;
242
243 /* clk provider */
244 struct clk_hw hw;
245 struct clk *phyclk;
246 unsigned long pixclock;
247 unsigned long tmdsclock;
248 unsigned long opts_tmds_char_rate;
249 };
250
251 struct pre_pll_config {
252 unsigned long pixclock;
253 unsigned long tmdsclock;
254 u8 prediv;
255 u16 fbdiv;
256 u8 tmds_div_a;
257 u8 tmds_div_b;
258 u8 tmds_div_c;
259 u8 pclk_div_a;
260 u8 pclk_div_b;
261 u8 pclk_div_c;
262 u8 pclk_div_d;
263 u8 vco_div_5_en;
264 u32 fracdiv;
265 };
266
267 struct post_pll_config {
268 unsigned long tmdsclock;
269 u8 prediv;
270 u16 fbdiv;
271 u8 postdiv;
272 u8 version;
273 };
274
275 struct phy_config {
276 unsigned long tmdsclock;
277 u8 regs[14];
278 };
279
280 struct inno_hdmi_phy_ops {
281 int (*init)(struct inno_hdmi_phy *inno);
282 int (*power_on)(struct inno_hdmi_phy *inno,
283 const struct post_pll_config *cfg,
284 const struct phy_config *phy_cfg);
285 void (*power_off)(struct inno_hdmi_phy *inno);
286 };
287
288 struct inno_hdmi_phy_drv_data {
289 const struct inno_hdmi_phy_ops *ops;
290 const struct clk_ops *clk_ops;
291 const struct phy_config *phy_cfg_table;
292 };
293
294 static const struct pre_pll_config pre_pll_cfg_table[] = {
295 { 25175000, 25175000, 3, 125, 3, 1, 1, 1, 3, 3, 4, 0, 0xe00000},
296 { 25175000, 31468750, 1, 41, 0, 3, 3, 1, 3, 3, 4, 0, 0xf5554f},
297 { 27000000, 27000000, 1, 36, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
298 { 27000000, 33750000, 1, 45, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
299 { 31500000, 31500000, 1, 42, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
300 { 31500000, 39375000, 1, 105, 1, 3, 3, 10, 0, 3, 4, 0, 0x0},
301 { 33750000, 33750000, 1, 45, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
302 { 33750000, 42187500, 1, 169, 2, 3, 3, 15, 0, 3, 4, 0, 0x0},
303 { 35500000, 35500000, 1, 71, 2, 2, 2, 6, 0, 3, 4, 0, 0x0},
304 { 35500000, 44375000, 1, 74, 3, 1, 1, 25, 0, 1, 1, 0, 0x0},
305 { 36000000, 36000000, 1, 36, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
306 { 36000000, 45000000, 1, 45, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
307 { 40000000, 40000000, 1, 40, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
308 { 40000000, 50000000, 1, 50, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
309 { 49500000, 49500000, 1, 66, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
310 { 49500000, 61875000, 1, 165, 1, 3, 3, 10, 0, 3, 4, 0, 0x0},
311 { 50000000, 50000000, 1, 50, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
312 { 50000000, 62500000, 1, 125, 2, 2, 2, 15, 0, 2, 2, 0, 0x0},
313 { 54000000, 54000000, 1, 36, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
314 { 54000000, 67500000, 1, 45, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
315 { 56250000, 56250000, 1, 75, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
316 { 56250000, 70312500, 1, 117, 3, 1, 1, 25, 0, 1, 1, 0, 0x0},
317 { 59341000, 59341000, 1, 118, 2, 2, 2, 6, 0, 3, 4, 0, 0xae978d},
318 { 59341000, 74176250, 2, 148, 2, 1, 1, 15, 0, 1, 1, 0, 0x5a3d70},
319 { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0x0},
320 { 59400000, 74250000, 1, 99, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
321 { 65000000, 65000000, 1, 65, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
322 { 65000000, 81250000, 3, 325, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
323 { 68250000, 68250000, 1, 91, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
324 { 68250000, 85312500, 1, 142, 3, 1, 1, 25, 0, 1, 1, 0, 0x0},
325 { 71000000, 71000000, 1, 71, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
326 { 71000000, 88750000, 3, 355, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
327 { 72000000, 72000000, 1, 36, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
328 { 72000000, 90000000, 1, 60, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
329 { 73250000, 73250000, 3, 293, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
330 { 73250000, 91562500, 1, 61, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
331 { 74176000, 74176000, 1, 37, 2, 0, 0, 1, 1, 2, 2, 0, 0x16872b},
332 { 74176000, 92720000, 2, 185, 2, 1, 1, 15, 0, 1, 1, 0, 0x70a3d7},
333 { 74250000, 74250000, 1, 99, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
334 { 74250000, 92812500, 4, 495, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
335 { 75000000, 75000000, 1, 50, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
336 { 75000000, 93750000, 1, 125, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
337 { 78750000, 78750000, 1, 105, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
338 { 78750000, 98437500, 1, 164, 3, 1, 1, 25, 0, 1, 1, 0, 0x0},
339 { 79500000, 79500000, 1, 53, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
340 { 79500000, 99375000, 1, 199, 2, 2, 2, 15, 0, 2, 2, 0, 0x0},
341 { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
342 { 83500000, 104375000, 1, 104, 2, 1, 1, 15, 0, 1, 1, 0, 0x600000},
343 { 85500000, 85500000, 1, 57, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
344 { 85500000, 106875000, 1, 178, 3, 1, 1, 25, 0, 1, 1, 0, 0x0},
345 { 85750000, 85750000, 3, 343, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
346 { 85750000, 107187500, 1, 143, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
347 { 88750000, 88750000, 3, 355, 0, 3, 3, 1, 2, 3, 4, 0, 0x0},
348 { 88750000, 110937500, 1, 110, 2, 1, 1, 15, 0, 1, 1, 0, 0xf00000},
349 { 94500000, 94500000, 1, 63, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
350 { 94500000, 118125000, 1, 197, 3, 1, 1, 25, 0, 1, 1, 0, 0x0},
351 {101000000, 101000000, 1, 101, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
352 {101000000, 126250000, 1, 42, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
353 {102250000, 102250000, 4, 409, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
354 {102250000, 127812500, 1, 128, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
355 {106500000, 106500000, 1, 71, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
356 {106500000, 133125000, 1, 133, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
357 {108000000, 108000000, 1, 36, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
358 {108000000, 135000000, 1, 45, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
359 {115500000, 115500000, 1, 77, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
360 {115500000, 144375000, 1, 48, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
361 {117500000, 117500000, 2, 235, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
362 {117500000, 146875000, 1, 49, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
363 {119000000, 119000000, 1, 119, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
364 {119000000, 148750000, 3, 148, 0, 1, 1, 1, 3, 1, 1, 0, 0xc00000},
365 {121750000, 121750000, 4, 487, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
366 {121750000, 152187500, 1, 203, 0, 3, 3, 1, 3, 3, 4, 0, 0x0},
367 {122500000, 122500000, 2, 245, 2, 1, 1, 1, 1, 3, 4, 0, 0x0},
368 {122500000, 153125000, 1, 51, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
369 {135000000, 135000000, 1, 45, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
370 {135000000, 168750000, 1, 169, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
371 {136750000, 136750000, 1, 68, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000},
372 {136750000, 170937500, 1, 113, 0, 2, 2, 1, 3, 2, 2, 0, 0xf5554f},
373 {140250000, 140250000, 2, 187, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
374 {140250000, 175312500, 1, 117, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
375 {146250000, 146250000, 2, 195, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
376 {146250000, 182812500, 1, 61, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
377 {148250000, 148250000, 3, 222, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000},
378 {148250000, 185312500, 1, 123, 0, 2, 2, 1, 3, 2, 2, 0, 0x8aaab0},
379 {148352000, 148352000, 2, 148, 2, 0, 0, 1, 1, 2, 2, 0, 0x5a1cac},
380 {148352000, 185440000, 3, 185, 0, 1, 1, 1, 3, 1, 1, 0, 0x70a3d7},
381 {148500000, 148500000, 1, 99, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
382 {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
383 {154000000, 154000000, 1, 77, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
384 {154000000, 192500000, 1, 64, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
385 {156000000, 156000000, 1, 52, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
386 {156000000, 195000000, 1, 65, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
387 {156750000, 156750000, 2, 209, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
388 {156750000, 195937500, 1, 196, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
389 {157000000, 157000000, 2, 157, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
390 {157000000, 196250000, 1, 131, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
391 {157500000, 157500000, 1, 105, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
392 {157500000, 196875000, 1, 197, 2, 1, 1, 15, 0, 1, 1, 0, 0x0},
393 {162000000, 162000000, 1, 54, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
394 {162000000, 202500000, 2, 135, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
395 {175500000, 175500000, 1, 117, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
396 {175500000, 219375000, 1, 73, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
397 {179500000, 179500000, 3, 359, 0, 2, 2, 1, 0, 3, 4, 0, 0x0},
398 {179500000, 224375000, 1, 75, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
399 {182750000, 182750000, 1, 91, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000},
400 {182750000, 228437500, 1, 152, 0, 2, 2, 1, 3, 2, 2, 0, 0x4aaab0},
401 {182750000, 228437500, 1, 152, 0, 2, 2, 1, 3, 2, 2, 0, 0x4aaab0},
402 {187000000, 187000000, 2, 187, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
403 {187000000, 233750000, 1, 39, 0, 0, 0, 1, 3, 0, 0, 1, 0x0},
404 {187250000, 187250000, 3, 280, 2, 0, 0, 1, 1, 2, 2, 0, 0xe00000},
405 {187250000, 234062500, 1, 156, 0, 2, 2, 1, 3, 2, 2, 0, 0xaaab0},
406 {189000000, 189000000, 1, 63, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
407 {189000000, 236250000, 1, 79, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
408 {193250000, 193250000, 3, 289, 2, 0, 0, 1, 1, 2, 2, 0, 0xe00000},
409 {193250000, 241562500, 1, 161, 0, 2, 2, 1, 3, 2, 2, 0, 0xaaab0},
410 {202500000, 202500000, 2, 135, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
411 {202500000, 253125000, 1, 169, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
412 {204750000, 204750000, 4, 273, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
413 {204750000, 255937500, 1, 171, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
414 {208000000, 208000000, 1, 104, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
415 {208000000, 260000000, 1, 173, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
416 {214750000, 214750000, 1, 107, 2, 0, 0, 1, 1, 2, 2, 0, 0x600000},
417 {214750000, 268437500, 1, 178, 0, 2, 2, 1, 3, 2, 2, 0, 0xf5554f},
418 {218250000, 218250000, 4, 291, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
419 {218250000, 272812500, 1, 91, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
420 {229500000, 229500000, 2, 153, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
421 {229500000, 286875000, 1, 191, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
422 {234000000, 234000000, 1, 39, 0, 0, 0, 1, 0, 1, 1, 0, 0x0},
423 {234000000, 292500000, 1, 195, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
424 {241500000, 241500000, 2, 161, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
425 {241500000, 301875000, 1, 201, 0, 2, 2, 1, 3, 2, 2, 0, 0x0},
426 {245250000, 245250000, 4, 327, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
427 {245250000, 306562500, 1, 51, 0, 0, 0, 1, 3, 0, 0, 1, 0x0},
428 {245500000, 245500000, 4, 491, 2, 0, 0, 1, 1, 2, 2, 0, 0x0},
429 {245500000, 306875000, 1, 51, 0, 0, 0, 1, 3, 0, 0, 1, 0x0},
430 {261000000, 261000000, 1, 87, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
431 {261000000, 326250000, 1, 109, 0, 1, 1, 1, 3, 1, 1, 0, 0x0},
432 {268250000, 268250000, 9, 402, 0, 0, 0, 1, 0, 1, 1, 0, 0x600000},
433 {268250000, 335312500, 1, 111, 0, 1, 1, 1, 3, 1, 1, 0, 0xc5554f},
434 {268500000, 268500000, 2, 179, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
435 {268500000, 335625000, 1, 56, 0, 0, 0, 1, 3, 0, 0, 1, 0x0},
436 {281250000, 281250000, 4, 375, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
437 {281250000, 351562500, 1, 117, 0, 3, 1, 1, 3, 1, 1, 0, 0x0},
438 {288000000, 288000000, 1, 48, 0, 0, 0, 1, 0, 1, 1, 0, 0x0},
439 {288000000, 360000000, 1, 60, 0, 2, 0, 1, 3, 0, 0, 1, 0x0},
440 {296703000, 296703000, 1, 49, 0, 0, 0, 1, 0, 1, 1, 0, 0x7353f7},
441 {296703000, 370878750, 1, 123, 0, 3, 1, 1, 3, 1, 1, 0, 0xa051eb},
442 {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
443 {297000000, 371250000, 4, 495, 0, 3, 1, 1, 3, 1, 1, 0, 0x0},
444 {312250000, 312250000, 9, 468, 0, 0, 0, 1, 0, 1, 1, 0, 0x600000},
445 {312250000, 390312500, 1, 130, 0, 3, 1, 1, 3, 1, 1, 0, 0x1aaab0},
446 {317000000, 317000000, 3, 317, 0, 1, 1, 1, 0, 2, 2, 0, 0x0},
447 {317000000, 396250000, 1, 66, 0, 2, 0, 1, 3, 0, 0, 1, 0x0},
448 {319750000, 319750000, 3, 159, 0, 0, 0, 1, 0, 1, 1, 0, 0xe00000},
449 {319750000, 399687500, 3, 199, 0, 2, 0, 1, 3, 0, 0, 1, 0xd80000},
450 {333250000, 333250000, 9, 499, 0, 0, 0, 1, 0, 1, 1, 0, 0xe00000},
451 {333250000, 416562500, 1, 138, 0, 3, 1, 1, 3, 1, 1, 0, 0xdaaab0},
452 {348500000, 348500000, 9, 522, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000},
453 {348500000, 435625000, 1, 145, 0, 3, 1, 1, 3, 1, 1, 0, 0x35554f},
454 {356500000, 356500000, 9, 534, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000},
455 {356500000, 445625000, 1, 148, 0, 3, 1, 1, 3, 1, 1, 0, 0x8aaab0},
456 {380500000, 380500000, 9, 570, 0, 2, 0, 1, 0, 1, 1, 0, 0xc00000},
457 {380500000, 475625000, 1, 158, 0, 3, 1, 1, 3, 1, 1, 0, 0x8aaab0},
458 {443250000, 443250000, 1, 73, 0, 2, 0, 1, 0, 1, 1, 0, 0xe00000},
459 {443250000, 554062500, 1, 92, 0, 2, 0, 1, 3, 0, 0, 1, 0x580000},
460 {505250000, 505250000, 9, 757, 0, 2, 0, 1, 0, 1, 1, 0, 0xe00000},
461 {552750000, 552750000, 3, 276, 0, 2, 0, 1, 0, 1, 1, 0, 0x600000},
462 {593407000, 296703500, 3, 296, 0, 1, 1, 1, 0, 1, 1, 0, 0xb41893},
463 {593407000, 370879375, 4, 494, 0, 3, 1, 1, 3, 0, 0, 1, 0x817e4a},
464 {593407000, 593407000, 3, 296, 0, 2, 0, 1, 0, 1, 1, 0, 0xb41893},
465 {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 1, 1, 0, 0x0},
466 {594000000, 371250000, 4, 495, 0, 3, 1, 1, 3, 0, 0, 1, 0x0},
467 {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0x0},
468 { /* sentinel */ }
469 };
470
471 static const struct post_pll_config post_pll_cfg_table[] = {
472 {33750000, 1, 40, 8, 1},
473 {33750000, 1, 80, 8, 2},
474 {74250000, 1, 40, 8, 1},
475 {74250000, 18, 80, 8, 2},
476 {148500000, 2, 40, 4, 3},
477 {297000000, 4, 40, 2, 3},
478 {594000000, 8, 40, 1, 3},
479 { /* sentinel */ }
480 };
481
482 /* phy tuning values for an undocumented set of registers */
483 static const struct phy_config rk3228_phy_cfg[] = {
484 { 165000000, {
485 0xaa, 0x00, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
486 0x00, 0x00, 0x00, 0x00, 0x00,
487 },
488 }, {
489 340000000, {
490 0xaa, 0x15, 0x6a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00,
491 0x00, 0x00, 0x00, 0x00, 0x00,
492 },
493 }, {
494 594000000, {
495 0xaa, 0x15, 0x7a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00,
496 0x00, 0x00, 0x00, 0x00, 0x00,
497 },
498 }, { /* sentinel */ },
499 };
500
501 /* phy tuning values for an undocumented set of registers */
502 static const struct phy_config rk3328_phy_cfg[] = {
503 { 165000000, {
504 0x07, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x08, 0x08, 0x08,
505 0x00, 0xac, 0xcc, 0xcc, 0xcc,
506 },
507 }, {
508 340000000, {
509 0x0b, 0x0d, 0x0d, 0x0d, 0x07, 0x15, 0x08, 0x08, 0x08,
510 0x3f, 0xac, 0xcc, 0xcd, 0xdd,
511 },
512 }, {
513 594000000, {
514 0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08,
515 0x00, 0xac, 0xcc, 0xcc, 0xcc,
516 },
517 }, { /* sentinel */ },
518 };
519
to_inno_hdmi_phy(struct clk_hw * hw)520 static inline struct inno_hdmi_phy *to_inno_hdmi_phy(struct clk_hw *hw)
521 {
522 return container_of(hw, struct inno_hdmi_phy, hw);
523 }
524
525 /*
526 * The register description of the IP block does not use any distinct names
527 * but instead the databook simply numbers the registers in one-increments.
528 * As the registers are obviously 32bit sized, the inno_* functions
529 * translate the databook register names to the actual registers addresses.
530 */
inno_write(struct inno_hdmi_phy * inno,u32 reg,u8 val)531 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)
532 {
533 regmap_write(inno->regmap, reg * 4, val);
534 }
535
inno_read(struct inno_hdmi_phy * inno,u32 reg)536 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg)
537 {
538 u32 val;
539
540 regmap_read(inno->regmap, reg * 4, &val);
541
542 return val;
543 }
544
inno_update_bits(struct inno_hdmi_phy * inno,u8 reg,u8 mask,u8 val)545 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,
546 u8 mask, u8 val)
547 {
548 regmap_update_bits(inno->regmap, reg * 4, mask, val);
549 }
550
551 #define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \
552 regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \
553 sleep_us, timeout_us)
554
inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy * inno,unsigned long rate)555 static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno,
556 unsigned long rate)
557 {
558 if (inno->opts_tmds_char_rate)
559 return inno->opts_tmds_char_rate;
560
561 return rate;
562 }
563
inno_hdmi_phy_rk3328_hardirq(int irq,void * dev_id)564 static irqreturn_t inno_hdmi_phy_rk3328_hardirq(int irq, void *dev_id)
565 {
566 struct inno_hdmi_phy *inno = dev_id;
567 int intr_stat1, intr_stat2, intr_stat3;
568
569 intr_stat1 = inno_read(inno, 0x04);
570 intr_stat2 = inno_read(inno, 0x06);
571 intr_stat3 = inno_read(inno, 0x08);
572
573 if (intr_stat1)
574 inno_write(inno, 0x04, intr_stat1);
575 if (intr_stat2)
576 inno_write(inno, 0x06, intr_stat2);
577 if (intr_stat3)
578 inno_write(inno, 0x08, intr_stat3);
579
580 if (intr_stat1 || intr_stat2 || intr_stat3)
581 return IRQ_WAKE_THREAD;
582
583 return IRQ_HANDLED;
584 }
585
inno_hdmi_phy_rk3328_irq(int irq,void * dev_id)586 static irqreturn_t inno_hdmi_phy_rk3328_irq(int irq, void *dev_id)
587 {
588 struct inno_hdmi_phy *inno = dev_id;
589
590 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
591 usleep_range(10, 20);
592 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
593
594 return IRQ_HANDLED;
595 }
596
597 /*
598 * phy_validate() is expected to be called from encoder atomic_check(), before
599 * the hdmiphy pixel clock is known. Without knowing the actual pixel clock, we
600 * cannot do full validation of the configuration. Instead, we do a simple check
601 * that the pre-pll table contains an entry for the requested TMDS char rate.
602 */
inno_hdmi_phy_validate(struct phy * phy,enum phy_mode mode,int submode,union phy_configure_opts * opts)603 static int inno_hdmi_phy_validate(struct phy *phy, enum phy_mode mode,
604 int submode, union phy_configure_opts *opts)
605 {
606 const struct pre_pll_config *cfg = pre_pll_cfg_table;
607 unsigned long tmdsclock;
608
609 if (!(mode == PHY_MODE_HDMI && submode == PHY_HDMI_MODE_TMDS))
610 return -EINVAL;
611
612 if (!opts)
613 return -EINVAL;
614
615 if (!opts->hdmi.tmds_char_rate || opts->hdmi.tmds_char_rate > 594000000)
616 return -EINVAL;
617
618 tmdsclock = opts->hdmi.tmds_char_rate;
619 for (; cfg->pixclock != 0; cfg++)
620 if (cfg->tmdsclock == tmdsclock)
621 return 0;
622
623 return -EINVAL;
624 }
625
626 /*
627 * phy_configure() is expected to be called from encoder atomic_set_mode(),
628 * before the hdmiphy pixel clock is known. Store the requested TMDS character
629 * rate, so that it can be used later in power_on() and/or set_rate() when the
630 * pixel clock is known.
631 */
inno_hdmi_phy_configure(struct phy * phy,union phy_configure_opts * opts)632 static int inno_hdmi_phy_configure(struct phy *phy,
633 union phy_configure_opts *opts)
634 {
635 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
636 int ret;
637
638 ret = inno_hdmi_phy_validate(phy, phy_get_mode(phy),
639 PHY_HDMI_MODE_TMDS, opts);
640 if (ret)
641 return ret;
642
643 inno->opts_tmds_char_rate = opts->hdmi.tmds_char_rate;
644
645 return 0;
646 }
647
inno_hdmi_phy_power_on(struct phy * phy)648 static int inno_hdmi_phy_power_on(struct phy *phy)
649 {
650 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
651 const struct post_pll_config *cfg = post_pll_cfg_table;
652 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;
653 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno,
654 inno->pixclock);
655 int ret;
656
657 if (!tmdsclock) {
658 dev_err(inno->dev, "TMDS clock is zero!\n");
659 return -EINVAL;
660 }
661
662 if (!inno->plat_data->ops->power_on)
663 return -EINVAL;
664
665 for (; cfg->tmdsclock != 0; cfg++)
666 if (tmdsclock <= cfg->tmdsclock &&
667 cfg->version & inno->chip_version)
668 break;
669
670 for (; phy_cfg->tmdsclock != 0; phy_cfg++)
671 if (tmdsclock <= phy_cfg->tmdsclock)
672 break;
673
674 if (cfg->tmdsclock == 0 || phy_cfg->tmdsclock == 0)
675 return -EINVAL;
676
677 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
678
679 inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000);
680
681 ret = clk_prepare_enable(inno->phyclk);
682 if (ret)
683 return ret;
684
685 ret = inno->plat_data->ops->power_on(inno, cfg, phy_cfg);
686 if (ret) {
687 clk_disable_unprepare(inno->phyclk);
688 return ret;
689 }
690
691 return 0;
692 }
693
inno_hdmi_phy_power_off(struct phy * phy)694 static int inno_hdmi_phy_power_off(struct phy *phy)
695 {
696 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
697
698 if (!inno->plat_data->ops->power_off)
699 return -EINVAL;
700
701 inno->plat_data->ops->power_off(inno);
702
703 clk_disable_unprepare(inno->phyclk);
704
705 inno->tmdsclock = 0;
706
707 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
708
709 return 0;
710 }
711
712 static const struct phy_ops inno_hdmi_phy_ops = {
713 .owner = THIS_MODULE,
714 .power_on = inno_hdmi_phy_power_on,
715 .power_off = inno_hdmi_phy_power_off,
716 .configure = inno_hdmi_phy_configure,
717 .validate = inno_hdmi_phy_validate,
718 };
719
720 static const
inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi_phy * inno,unsigned long rate)721 struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi_phy *inno,
722 unsigned long rate)
723 {
724 const struct pre_pll_config *cfg = pre_pll_cfg_table;
725 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
726
727 for (; cfg->pixclock != 0; cfg++)
728 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock)
729 break;
730
731 if (cfg->pixclock == 0)
732 return ERR_PTR(-EINVAL);
733
734 return cfg;
735 }
736
inno_hdmi_phy_rk3228_clk_is_prepared(struct clk_hw * hw)737 static int inno_hdmi_phy_rk3228_clk_is_prepared(struct clk_hw *hw)
738 {
739 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
740 u8 status;
741
742 status = inno_read(inno, 0xe0) & RK3228_PRE_PLL_POWER_DOWN;
743 return status ? 0 : 1;
744 }
745
inno_hdmi_phy_rk3228_clk_prepare(struct clk_hw * hw)746 static int inno_hdmi_phy_rk3228_clk_prepare(struct clk_hw *hw)
747 {
748 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
749
750 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
751 return 0;
752 }
753
inno_hdmi_phy_rk3228_clk_unprepare(struct clk_hw * hw)754 static void inno_hdmi_phy_rk3228_clk_unprepare(struct clk_hw *hw)
755 {
756 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
757
758 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
759 RK3228_PRE_PLL_POWER_DOWN);
760 }
761
762 static
inno_hdmi_phy_rk3228_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)763 unsigned long inno_hdmi_phy_rk3228_clk_recalc_rate(struct clk_hw *hw,
764 unsigned long parent_rate)
765 {
766 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
767 u8 nd, no_a, no_b, no_d;
768 u64 vco;
769 u16 nf;
770
771 nd = inno_read(inno, 0xe2) & RK3228_PRE_PLL_PRE_DIV_MASK;
772 nf = (inno_read(inno, 0xe2) & RK3228_PRE_PLL_FB_DIV_8_MASK) << 1;
773 nf |= inno_read(inno, 0xe3);
774 vco = parent_rate * nf;
775
776 if (inno_read(inno, 0xe2) & RK3228_PCLK_VCO_DIV_5_MASK) {
777 do_div(vco, nd * 5);
778 } else {
779 no_a = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_A_MASK;
780 if (!no_a)
781 no_a = 1;
782 no_b = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_B_MASK;
783 no_b >>= RK3228_PRE_PLL_PCLK_DIV_B_SHIFT;
784 no_b += 2;
785 no_d = inno_read(inno, 0xe5) & RK3228_PRE_PLL_PCLK_DIV_D_MASK;
786
787 do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
788 }
789
790 inno->pixclock = vco;
791
792 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
793
794 return vco;
795 }
796
inno_hdmi_phy_rk3228_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)797 static int inno_hdmi_phy_rk3228_clk_determine_rate(struct clk_hw *hw,
798 struct clk_rate_request *req)
799 {
800 const struct pre_pll_config *cfg = pre_pll_cfg_table;
801
802 req->rate = (req->rate / 1000) * 1000;
803
804 for (; cfg->pixclock != 0; cfg++)
805 if (cfg->pixclock == req->rate && !cfg->fracdiv)
806 break;
807
808 if (cfg->pixclock == 0)
809 return -EINVAL;
810
811 req->rate = cfg->pixclock;
812
813 return 0;
814 }
815
inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)816 static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
817 unsigned long rate,
818 unsigned long parent_rate)
819 {
820 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
821 const struct pre_pll_config *cfg;
822 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
823 u32 v;
824 int ret;
825
826 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
827 __func__, rate, tmdsclock);
828
829 if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
830 return 0;
831
832 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
833 if (IS_ERR(cfg))
834 return PTR_ERR(cfg);
835
836 /* Power down PRE-PLL */
837 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
838 RK3228_PRE_PLL_POWER_DOWN);
839
840 inno_update_bits(inno, 0xe2, RK3228_PRE_PLL_FB_DIV_8_MASK |
841 RK3228_PCLK_VCO_DIV_5_MASK |
842 RK3228_PRE_PLL_PRE_DIV_MASK,
843 RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) |
844 RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en) |
845 RK3228_PRE_PLL_PRE_DIV(cfg->prediv));
846 inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
847 inno_update_bits(inno, 0xe4, RK3228_PRE_PLL_PCLK_DIV_B_MASK |
848 RK3228_PRE_PLL_PCLK_DIV_A_MASK,
849 RK3228_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) |
850 RK3228_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a));
851 inno_update_bits(inno, 0xe5, RK3228_PRE_PLL_PCLK_DIV_C_MASK |
852 RK3228_PRE_PLL_PCLK_DIV_D_MASK,
853 RK3228_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |
854 RK3228_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d));
855 inno_update_bits(inno, 0xe6, RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK |
856 RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK |
857 RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK,
858 RK3228_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |
859 RK3228_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |
860 RK3228_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b));
861
862 /* Power up PRE-PLL */
863 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
864
865 /* Wait for Pre-PLL lock */
866 ret = inno_poll(inno, 0xe8, v, v & RK3228_PRE_PLL_LOCK_STATUS,
867 100, 100000);
868 if (ret) {
869 dev_err(inno->dev, "Pre-PLL locking failed\n");
870 return ret;
871 }
872
873 inno->pixclock = rate;
874 inno->tmdsclock = tmdsclock;
875
876 return 0;
877 }
878
879 static const struct clk_ops inno_hdmi_phy_rk3228_clk_ops = {
880 .prepare = inno_hdmi_phy_rk3228_clk_prepare,
881 .unprepare = inno_hdmi_phy_rk3228_clk_unprepare,
882 .is_prepared = inno_hdmi_phy_rk3228_clk_is_prepared,
883 .recalc_rate = inno_hdmi_phy_rk3228_clk_recalc_rate,
884 .determine_rate = inno_hdmi_phy_rk3228_clk_determine_rate,
885 .set_rate = inno_hdmi_phy_rk3228_clk_set_rate,
886 };
887
inno_hdmi_phy_rk3328_clk_is_prepared(struct clk_hw * hw)888 static int inno_hdmi_phy_rk3328_clk_is_prepared(struct clk_hw *hw)
889 {
890 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
891 u8 status;
892
893 status = inno_read(inno, 0xa0) & RK3328_PRE_PLL_POWER_DOWN;
894 return status ? 0 : 1;
895 }
896
inno_hdmi_phy_rk3328_clk_prepare(struct clk_hw * hw)897 static int inno_hdmi_phy_rk3328_clk_prepare(struct clk_hw *hw)
898 {
899 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
900
901 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
902 return 0;
903 }
904
inno_hdmi_phy_rk3328_clk_unprepare(struct clk_hw * hw)905 static void inno_hdmi_phy_rk3328_clk_unprepare(struct clk_hw *hw)
906 {
907 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
908
909 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
910 RK3328_PRE_PLL_POWER_DOWN);
911 }
912
913 static
inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)914 unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
915 unsigned long parent_rate)
916 {
917 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
918 unsigned long frac;
919 u8 nd, no_a, no_b, no_d;
920 u64 vco;
921 u16 nf;
922
923 nd = inno_read(inno, 0xa1) & RK3328_PRE_PLL_PRE_DIV_MASK;
924 nf = ((inno_read(inno, 0xa2) & RK3328_PRE_PLL_FB_DIV_11_8_MASK) << 8);
925 nf |= inno_read(inno, 0xa3);
926 vco = parent_rate * nf;
927
928 if (!(inno_read(inno, 0xa2) & RK3328_PRE_PLL_FRAC_DIV_DISABLE)) {
929 frac = inno_read(inno, 0xd3) |
930 (inno_read(inno, 0xd2) << 8) |
931 (inno_read(inno, 0xd1) << 16);
932 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24));
933 }
934
935 if (inno_read(inno, 0xa0) & RK3328_PCLK_VCO_DIV_5_MASK) {
936 do_div(vco, nd * 5);
937 } else {
938 no_a = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_A_MASK;
939 no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK;
940 no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT;
941 no_b += 2;
942 no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK;
943
944 do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
945 }
946
947 inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;
948
949 dev_dbg(inno->dev, "%s rate %lu vco %llu\n",
950 __func__, inno->pixclock, vco);
951
952 return inno->pixclock;
953 }
954
inno_hdmi_phy_rk3328_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)955 static int inno_hdmi_phy_rk3328_clk_determine_rate(struct clk_hw *hw,
956 struct clk_rate_request *req)
957 {
958 const struct pre_pll_config *cfg = pre_pll_cfg_table;
959
960 req->rate = (req->rate / 1000) * 1000;
961
962 for (; cfg->pixclock != 0; cfg++)
963 if (cfg->pixclock == req->rate)
964 break;
965
966 if (cfg->pixclock == 0)
967 return -EINVAL;
968
969 req->rate = cfg->pixclock;
970
971 return 0;
972 }
973
inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)974 static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
975 unsigned long rate,
976 unsigned long parent_rate)
977 {
978 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
979 const struct pre_pll_config *cfg;
980 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
981 u32 val;
982 int ret;
983
984 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
985 __func__, rate, tmdsclock);
986
987 if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
988 return 0;
989
990 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
991 if (IS_ERR(cfg))
992 return PTR_ERR(cfg);
993
994 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
995 RK3328_PRE_PLL_POWER_DOWN);
996
997 /* Configure pre-pll */
998 inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK,
999 RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en));
1000 inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv));
1001
1002 val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE;
1003 if (!cfg->fracdiv)
1004 val |= RK3328_PRE_PLL_FRAC_DIV_DISABLE;
1005 inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val);
1006 inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
1007 inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) |
1008 RK3328_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b));
1009 inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |
1010 RK3328_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d));
1011 inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |
1012 RK3328_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |
1013 RK3328_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b));
1014 inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv));
1015 inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv));
1016 inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv));
1017
1018 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
1019
1020 /* Wait for Pre-PLL lock */
1021 ret = inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS,
1022 1000, 10000);
1023 if (ret) {
1024 dev_err(inno->dev, "Pre-PLL locking failed\n");
1025 return ret;
1026 }
1027
1028 inno->pixclock = rate;
1029 inno->tmdsclock = tmdsclock;
1030
1031 return 0;
1032 }
1033
1034 static const struct clk_ops inno_hdmi_phy_rk3328_clk_ops = {
1035 .prepare = inno_hdmi_phy_rk3328_clk_prepare,
1036 .unprepare = inno_hdmi_phy_rk3328_clk_unprepare,
1037 .is_prepared = inno_hdmi_phy_rk3328_clk_is_prepared,
1038 .recalc_rate = inno_hdmi_phy_rk3328_clk_recalc_rate,
1039 .determine_rate = inno_hdmi_phy_rk3328_clk_determine_rate,
1040 .set_rate = inno_hdmi_phy_rk3328_clk_set_rate,
1041 };
1042
inno_hdmi_phy_clk_register(struct inno_hdmi_phy * inno)1043 static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
1044 {
1045 struct device *dev = inno->dev;
1046 struct device_node *np = dev->of_node;
1047 struct clk_init_data init;
1048 const char *parent_name;
1049 int ret;
1050
1051 parent_name = __clk_get_name(inno->refoclk);
1052
1053 init.parent_names = &parent_name;
1054 init.num_parents = 1;
1055 init.flags = 0;
1056 init.name = "pin_hd20_pclk";
1057 init.ops = inno->plat_data->clk_ops;
1058
1059 /* optional override of the clock name */
1060 of_property_read_string(np, "clock-output-names", &init.name);
1061
1062 inno->hw.init = &init;
1063
1064 inno->phyclk = devm_clk_register(dev, &inno->hw);
1065 if (IS_ERR(inno->phyclk)) {
1066 ret = PTR_ERR(inno->phyclk);
1067 dev_err(dev, "failed to register clock: %d\n", ret);
1068 return ret;
1069 }
1070
1071 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->phyclk);
1072 if (ret) {
1073 dev_err(dev, "failed to register clock provider: %d\n", ret);
1074 return ret;
1075 }
1076
1077 return 0;
1078 }
1079
inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy * inno)1080 static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
1081 {
1082 /*
1083 * Use phy internal register control
1084 * rxsense/poweron/pllpd/pdataen signal.
1085 */
1086 inno_write(inno, 0x01, RK3228_BYPASS_RXSENSE_EN |
1087 RK3228_BYPASS_PWRON_EN |
1088 RK3228_BYPASS_PLLPD_EN);
1089 inno_update_bits(inno, 0x02, RK3228_BYPASS_PDATA_EN,
1090 RK3228_BYPASS_PDATA_EN);
1091
1092 /* manual power down post-PLL */
1093 inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL,
1094 RK3228_POST_PLL_CTRL_MANUAL);
1095
1096 inno->chip_version = 1;
1097
1098 return 0;
1099 }
1100
1101 static int
inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy * inno,const struct post_pll_config * cfg,const struct phy_config * phy_cfg)1102 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno,
1103 const struct post_pll_config *cfg,
1104 const struct phy_config *phy_cfg)
1105 {
1106 int ret;
1107 u32 v;
1108
1109 inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE,
1110 RK3228_PDATAEN_DISABLE);
1111 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
1112 RK3228_POST_PLL_POWER_DOWN,
1113 RK3228_PRE_PLL_POWER_DOWN |
1114 RK3228_POST_PLL_POWER_DOWN);
1115
1116 /* Post-PLL update */
1117 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_PRE_DIV_MASK,
1118 RK3228_POST_PLL_PRE_DIV(cfg->prediv));
1119 inno_update_bits(inno, 0xeb, RK3228_POST_PLL_FB_DIV_8_MASK,
1120 RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv));
1121 inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
1122
1123 if (cfg->postdiv == 1) {
1124 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
1125 0);
1126 } else {
1127 int div = cfg->postdiv / 2 - 1;
1128
1129 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
1130 RK3228_POST_PLL_POST_DIV_ENABLE);
1131 inno_update_bits(inno, 0xeb, RK3228_POST_PLL_POST_DIV_MASK,
1132 RK3228_POST_PLL_POST_DIV(div));
1133 }
1134
1135 for (v = 0; v < 4; v++)
1136 inno_write(inno, 0xef + v, phy_cfg->regs[v]);
1137
1138 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
1139 RK3228_POST_PLL_POWER_DOWN, 0);
1140 inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE,
1141 RK3228_BANDGAP_ENABLE);
1142 inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE,
1143 RK3228_TMDS_DRIVER_ENABLE);
1144
1145 /* Wait for post PLL lock */
1146 ret = inno_poll(inno, 0xeb, v, v & RK3228_POST_PLL_LOCK_STATUS,
1147 100, 100000);
1148 if (ret) {
1149 dev_err(inno->dev, "Post-PLL locking failed\n");
1150 return ret;
1151 }
1152
1153 if (cfg->tmdsclock > 340000000)
1154 msleep(100);
1155
1156 inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE, 0);
1157 return 0;
1158 }
1159
inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy * inno)1160 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno)
1161 {
1162 inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE, 0);
1163 inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE, 0);
1164 inno_update_bits(inno, 0xe0, RK3228_POST_PLL_POWER_DOWN,
1165 RK3228_POST_PLL_POWER_DOWN);
1166 }
1167
1168 static const struct inno_hdmi_phy_ops rk3228_hdmi_phy_ops = {
1169 .init = inno_hdmi_phy_rk3228_init,
1170 .power_on = inno_hdmi_phy_rk3228_power_on,
1171 .power_off = inno_hdmi_phy_rk3228_power_off,
1172 };
1173
inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy * inno)1174 static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
1175 {
1176 struct nvmem_cell *cell;
1177 unsigned char *efuse_buf;
1178 size_t len;
1179
1180 /*
1181 * Use phy internal register control
1182 * rxsense/poweron/pllpd/pdataen signal.
1183 */
1184 inno_write(inno, 0x01, RK3328_BYPASS_RXSENSE_EN |
1185 RK3328_BYPASS_POWERON_EN |
1186 RK3328_BYPASS_PLLPD_EN);
1187 inno_write(inno, 0x02, RK3328_INT_POL_HIGH | RK3328_BYPASS_PDATA_EN |
1188 RK3328_PDATA_EN);
1189
1190 /* Disable phy irq */
1191 inno_write(inno, 0x05, 0);
1192 inno_write(inno, 0x07, 0);
1193
1194 /* try to read the chip-version */
1195 inno->chip_version = 1;
1196 cell = nvmem_cell_get(inno->dev, "cpu-version");
1197 if (IS_ERR(cell)) {
1198 if (PTR_ERR(cell) == -EPROBE_DEFER)
1199 return -EPROBE_DEFER;
1200
1201 return 0;
1202 }
1203
1204 efuse_buf = nvmem_cell_read(cell, &len);
1205 nvmem_cell_put(cell);
1206
1207 if (IS_ERR(efuse_buf))
1208 return 0;
1209 if (len == 1)
1210 inno->chip_version = efuse_buf[0] + 1;
1211 kfree(efuse_buf);
1212
1213 return 0;
1214 }
1215
1216 static int
inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy * inno,const struct post_pll_config * cfg,const struct phy_config * phy_cfg)1217 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
1218 const struct post_pll_config *cfg,
1219 const struct phy_config *phy_cfg)
1220 {
1221 int ret;
1222 u32 v;
1223
1224 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
1225 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,
1226 RK3328_POST_PLL_POWER_DOWN);
1227
1228 inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
1229 if (cfg->postdiv == 1) {
1230 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
1231 RK3328_POST_PLL_PRE_DIV(cfg->prediv));
1232 inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS |
1233 RK3328_POST_PLL_POWER_DOWN);
1234 } else {
1235 v = (cfg->postdiv / 2) - 1;
1236 v &= RK3328_POST_PLL_POST_DIV_MASK;
1237 inno_write(inno, 0xad, v);
1238 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
1239 RK3328_POST_PLL_PRE_DIV(cfg->prediv));
1240 inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE |
1241 RK3328_POST_PLL_REFCLK_SEL_TMDS |
1242 RK3328_POST_PLL_POWER_DOWN);
1243 }
1244
1245 for (v = 0; v < 14; v++)
1246 inno_write(inno, 0xb5 + v, phy_cfg->regs[v]);
1247
1248 /* set ESD detection threshold for TMDS CLK, D2, D1 and D0 */
1249 for (v = 0; v < 4; v++)
1250 inno_update_bits(inno, 0xc8 + v, RK3328_ESD_DETECT_MASK,
1251 RK3328_ESD_DETECT_340MV);
1252
1253 if (phy_cfg->tmdsclock > 340000000) {
1254 /* Set termination resistor to 100ohm */
1255 v = clk_get_rate(inno->sysclk) / 100000;
1256 inno_write(inno, 0xc5, RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(v)
1257 | RK3328_BYPASS_TERM_RESISTOR_CALIB);
1258 inno_write(inno, 0xc6, RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(v));
1259 inno_write(inno, 0xc7, RK3328_TERM_RESISTOR_100);
1260 inno_update_bits(inno, 0xc5,
1261 RK3328_BYPASS_TERM_RESISTOR_CALIB, 0);
1262 } else {
1263 inno_write(inno, 0xc5, RK3328_BYPASS_TERM_RESISTOR_CALIB);
1264
1265 /* clk termination resistor is 50ohm (parallel resistors) */
1266 if (phy_cfg->tmdsclock > 165000000)
1267 inno_update_bits(inno, 0xc8,
1268 RK3328_TMDS_TERM_RESIST_MASK,
1269 RK3328_TMDS_TERM_RESIST_75 |
1270 RK3328_TMDS_TERM_RESIST_150);
1271
1272 /* data termination resistor for D2, D1 and D0 is 150ohm */
1273 for (v = 0; v < 3; v++)
1274 inno_update_bits(inno, 0xc9 + v,
1275 RK3328_TMDS_TERM_RESIST_MASK,
1276 RK3328_TMDS_TERM_RESIST_150);
1277 }
1278
1279 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN, 0);
1280 inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE,
1281 RK3328_BANDGAP_ENABLE);
1282 inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE,
1283 RK3328_TMDS_DRIVER_ENABLE);
1284
1285 /* Wait for post PLL lock */
1286 ret = inno_poll(inno, 0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS,
1287 1000, 10000);
1288 if (ret) {
1289 dev_err(inno->dev, "Post-PLL locking failed\n");
1290 return ret;
1291 }
1292
1293 if (phy_cfg->tmdsclock > 340000000)
1294 msleep(100);
1295
1296 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
1297
1298 /* Enable PHY IRQ */
1299 inno_write(inno, 0x05, RK3328_INT_TMDS_CLK(RK3328_INT_VSS_AGND_ESD_DET)
1300 | RK3328_INT_TMDS_D2(RK3328_INT_VSS_AGND_ESD_DET));
1301 inno_write(inno, 0x07, RK3328_INT_TMDS_D1(RK3328_INT_VSS_AGND_ESD_DET)
1302 | RK3328_INT_TMDS_D0(RK3328_INT_VSS_AGND_ESD_DET));
1303 return 0;
1304 }
1305
inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy * inno)1306 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno)
1307 {
1308 inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE, 0);
1309 inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE, 0);
1310 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,
1311 RK3328_POST_PLL_POWER_DOWN);
1312
1313 /* Disable PHY IRQ */
1314 inno_write(inno, 0x05, 0);
1315 inno_write(inno, 0x07, 0);
1316 }
1317
1318 static const struct inno_hdmi_phy_ops rk3328_hdmi_phy_ops = {
1319 .init = inno_hdmi_phy_rk3328_init,
1320 .power_on = inno_hdmi_phy_rk3328_power_on,
1321 .power_off = inno_hdmi_phy_rk3328_power_off,
1322 };
1323
1324 static const struct inno_hdmi_phy_drv_data rk3228_hdmi_phy_drv_data = {
1325 .ops = &rk3228_hdmi_phy_ops,
1326 .clk_ops = &inno_hdmi_phy_rk3228_clk_ops,
1327 .phy_cfg_table = rk3228_phy_cfg,
1328 };
1329
1330 static const struct inno_hdmi_phy_drv_data rk3328_hdmi_phy_drv_data = {
1331 .ops = &rk3328_hdmi_phy_ops,
1332 .clk_ops = &inno_hdmi_phy_rk3328_clk_ops,
1333 .phy_cfg_table = rk3328_phy_cfg,
1334 };
1335
1336 static const struct regmap_config inno_hdmi_phy_regmap_config = {
1337 .reg_bits = 32,
1338 .val_bits = 32,
1339 .reg_stride = 4,
1340 .max_register = 0x400,
1341 };
1342
inno_hdmi_phy_action(void * data)1343 static void inno_hdmi_phy_action(void *data)
1344 {
1345 struct inno_hdmi_phy *inno = data;
1346
1347 clk_disable_unprepare(inno->refpclk);
1348 clk_disable_unprepare(inno->sysclk);
1349 }
1350
inno_hdmi_phy_probe(struct platform_device * pdev)1351 static int inno_hdmi_phy_probe(struct platform_device *pdev)
1352 {
1353 struct inno_hdmi_phy *inno;
1354 struct phy_provider *phy_provider;
1355 void __iomem *regs;
1356 int ret;
1357
1358 inno = devm_kzalloc(&pdev->dev, sizeof(*inno), GFP_KERNEL);
1359 if (!inno)
1360 return -ENOMEM;
1361
1362 inno->dev = &pdev->dev;
1363
1364 inno->plat_data = of_device_get_match_data(inno->dev);
1365 if (!inno->plat_data || !inno->plat_data->ops)
1366 return -EINVAL;
1367
1368 regs = devm_platform_ioremap_resource(pdev, 0);
1369 if (IS_ERR(regs))
1370 return PTR_ERR(regs);
1371
1372 inno->sysclk = devm_clk_get(inno->dev, "sysclk");
1373 if (IS_ERR(inno->sysclk)) {
1374 ret = PTR_ERR(inno->sysclk);
1375 dev_err(inno->dev, "failed to get sysclk: %d\n", ret);
1376 return ret;
1377 }
1378
1379 inno->refpclk = devm_clk_get(inno->dev, "refpclk");
1380 if (IS_ERR(inno->refpclk)) {
1381 ret = PTR_ERR(inno->refpclk);
1382 dev_err(inno->dev, "failed to get ref clock: %d\n", ret);
1383 return ret;
1384 }
1385
1386 inno->refoclk = devm_clk_get(inno->dev, "refoclk");
1387 if (IS_ERR(inno->refoclk)) {
1388 ret = PTR_ERR(inno->refoclk);
1389 dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n",
1390 ret);
1391 return ret;
1392 }
1393
1394 ret = clk_prepare_enable(inno->sysclk);
1395 if (ret) {
1396 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret);
1397 return ret;
1398 }
1399
1400 /*
1401 * Refpclk needs to be on, on at least the rk3328 for still
1402 * unknown reasons.
1403 */
1404 ret = clk_prepare_enable(inno->refpclk);
1405 if (ret) {
1406 dev_err(inno->dev, "failed to enable refpclk\n");
1407 clk_disable_unprepare(inno->sysclk);
1408 return ret;
1409 }
1410
1411 ret = devm_add_action_or_reset(inno->dev, inno_hdmi_phy_action,
1412 inno);
1413 if (ret)
1414 return ret;
1415
1416 inno->regmap = devm_regmap_init_mmio(inno->dev, regs,
1417 &inno_hdmi_phy_regmap_config);
1418 if (IS_ERR(inno->regmap))
1419 return PTR_ERR(inno->regmap);
1420
1421 /* only the newer rk3328 hdmiphy has an interrupt */
1422 inno->irq = platform_get_irq(pdev, 0);
1423 if (inno->irq > 0) {
1424 ret = devm_request_threaded_irq(inno->dev, inno->irq,
1425 inno_hdmi_phy_rk3328_hardirq,
1426 inno_hdmi_phy_rk3328_irq,
1427 IRQF_SHARED,
1428 dev_name(inno->dev), inno);
1429 if (ret)
1430 return ret;
1431 }
1432
1433 inno->phy = devm_phy_create(inno->dev, NULL, &inno_hdmi_phy_ops);
1434 if (IS_ERR(inno->phy)) {
1435 dev_err(inno->dev, "failed to create HDMI PHY\n");
1436 return PTR_ERR(inno->phy);
1437 }
1438
1439 phy_set_drvdata(inno->phy, inno);
1440 phy_set_mode_ext(inno->phy, PHY_MODE_HDMI, PHY_HDMI_MODE_TMDS);
1441
1442 if (inno->plat_data->ops->init) {
1443 ret = inno->plat_data->ops->init(inno);
1444 if (ret)
1445 return ret;
1446 }
1447
1448 ret = inno_hdmi_phy_clk_register(inno);
1449 if (ret)
1450 return ret;
1451
1452 phy_provider = devm_of_phy_provider_register(inno->dev,
1453 of_phy_simple_xlate);
1454 return PTR_ERR_OR_ZERO(phy_provider);
1455 }
1456
inno_hdmi_phy_remove(struct platform_device * pdev)1457 static void inno_hdmi_phy_remove(struct platform_device *pdev)
1458 {
1459 of_clk_del_provider(pdev->dev.of_node);
1460 }
1461
1462 static const struct of_device_id inno_hdmi_phy_of_match[] = {
1463 {
1464 .compatible = "rockchip,rk3228-hdmi-phy",
1465 .data = &rk3228_hdmi_phy_drv_data
1466 }, {
1467 .compatible = "rockchip,rk3328-hdmi-phy",
1468 .data = &rk3328_hdmi_phy_drv_data
1469 }, { /* sentinel */ }
1470 };
1471 MODULE_DEVICE_TABLE(of, inno_hdmi_phy_of_match);
1472
1473 static struct platform_driver inno_hdmi_phy_driver = {
1474 .probe = inno_hdmi_phy_probe,
1475 .remove = inno_hdmi_phy_remove,
1476 .driver = {
1477 .name = "inno-hdmi-phy",
1478 .of_match_table = inno_hdmi_phy_of_match,
1479 },
1480 };
1481 module_platform_driver(inno_hdmi_phy_driver);
1482
1483 MODULE_AUTHOR("Zheng Yang <zhengyang@rock-chips.com>");
1484 MODULE_DESCRIPTION("Innosilion HDMI 2.0 Transmitter PHY Driver");
1485 MODULE_LICENSE("GPL v2");
1486